STMicroelectronics L9347 Datasheet
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L9347
Intelligent quad (2x5A/2x2.5A) low-side switch
Features
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Quad low-side switch
2 x 5A designed as conventional switch
2 x 2.5A designed as switched currentregulator
Low ON resistance 2 x 0.2
, 2 x 0.35
(typ.)
Power SO-36 package with integrated cooling area
Integrated free wheeling and clamping Z diodes
Output slope control
Short circuit protection
Selective overtemperature shutdown
Open load detection
Ground and supply loss detection
External clock control
Recirculation control
Regulator drift detection
Regulator error control
Regulator resolution 5mA
Status monitoring
Status push-pull stages
Electrostatic discharge (ESD) protection
Table 1.
Device summary
Part number
L9347LF
L9347LF-TR
L9347DIE1
Package
PowerSO-36
PowerSO-36
Bare die
PowerSO-36 Bare Die
Description
The L9347 is an integrated quad low-side power switch to drive inductive loads like valves used in
ABS systems. Two of the four channels are current regulators with current range from 250mA to 2.25A and an accuracy of 10%.
All channels are protected against fail functions.
They are monitored by a status output.
Packing
Tray
Tape and reel
Bare die
September 2013 Rev 3 1/29 www.st.com
1
Contents
Contents
L9347
Block diagram and pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Output stages (not regulated) Channel 1 and 2 . . . . . . . . . . . . . . . . . . . . 13
Current regulator stages Channel 3 and 4 . . . . . . . . . . . . . . . . . . . . . . . . 13
Drift detection (regulated channels only) . . . . . . . . . . . . . . . . . . . . . . . . . 17
2/29
L9347
List of tables
List of tables
Table 10.
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3/29
List of figures
List of figures
L9347
4/29
L9347
1
Block diagram and pin connections
Block diagram and pin connections
Figure 1.
Block diagram
EN
CLK
IN1
VS VCC VDD
Internal Supply
Overtemperature
Channel 4
LOGIC
Overtemperature
Channel 1
Open Load
Overload
Q1
ST1
IPD
IN4
LOGIC
&
DA
GND-det.
Open Load
Overload
D4
Q4
ST4
IPD
IN2
Overtemperature
Channel 3
LOGIC
GND-det.
Overtemperature
Channel 2
Open Load
Overload
Q2
ST2
IPD
IN3
LOGIC
&
DA
GND-det.
Open Load
Overload
D3
Q3
ST3
TEST drift-det.
GND-det.
IPD
99AT0059
GND
5/29
Block diagram and pin connections
Figure 2.
Pin connections
GND
PGND3
PGND3
Q3
Q3
D3
D3
Q1
Q1
Q2
Q2
D4
D4
Q4
Q4
PGND4
PGND4
N.C.
9
10
11
12
13
14
15
4
5
6
7
8
1
2
3
16
17
18
99AT0060
Table 2.
N°
16, 17
18
19
20
21
22
23
24
1
2, 3
4, 5
6, 7
8, 9
10, 11
12, 13
14, 15
25
26
27, 28
29
Pin description
Pin
PGND 3
Q 3
D 3
Q 1
Q 2
D 4
Q 4
PGND 4
NC
VCC
VDD
ST 4
IN 2
IN 4
ST 2
EN
TEST
PGND 2
VS
Function
Power Ground Channel 3
Power Output Channel 3
Free-Wheeling Diode Channel 3
Power Output Channel 1
Power Output Channel 2
Free-Wheeling Diode Channel 4
Power Output Channel 4
Power Ground Channel 4
Not Connected
5V Supply
5V Supply
Status Output Channel 4
Control Input Channel 2
Control Input Channel 4
Status Output Channel 2
Enable Input for all four Channels
Enable Input for Drift detection
Power Ground Channel 2
Supply Voltage
28
27
26
25
24
23
22
36
35
34
33
32
31
30
29
21
20
19
CLK
ST3
IN1
IN3
ST1
PGND1
PGND1
VS
PGND2
PGND2
TEST
EN
ST2
IN4
IN2
ST4
VDD
VCC
6/29
L9347
L9347 Block diagram and pin connections
Table 2.
N°
30, 31
32
33
34
35
36
Pin description (continued)
Pin
PGND 1
ST 1
IN 3
IN 1
ST 3
CLK
Power Ground Channel 1
Status Output Channel 1
Control Input Channel 3
Control Input Channel 1
Status Output Channel 3
Clock Input
Function
7/29
Electrical specifications L9347
Table 3.
Electrical characteristcs :
(Vs = 4.8 to 18V; T j
= -40 to 150°C unless otherwise specified)
Parameter Test condition Symbol Min. Typ.
Max.
Unit
Power supply
I
I
SON
SOFF
Supply current
Quiescent current
V
S
18V
(outputs ON)
V
S
18V
(outputs OFF)
I
I
I cc dd dd
Supply current VCC (analog supply) VCC =5V
Supply current VDD (digital supply) VDD =5V f
CLK
=0Hz
Supply current VDD (digital supply) VDD =5V f
CLK
=250kHz
General diagnostic functions
5
5
5
5
5 mA mA mA uA mA
V
QU
Open load voltage
V
S
6.5V
(outputs OFF)
0.3
V thGND
V thPGL f
CLK,min
Signal-GND-loss threshold
Power-GND-loss threshold
Clock frequency error
VCC= 5V
VCC= 5V
DC
CLKe_low
DC
CLKe_high
VS loss
Clock duty cycle error detection low f
CLK
= 250 kHz
Clock duty cycle error detection high f
CLK
= 250 kHz
Supply detection VCC = VDD = 5V
0.1
1.5
10
55
2
Additional diagnostic functions channel 1 and channel 2 (non regulated channels)
I
I
QU1,2
QO1,2
Open-load current channel 1, 2
Over-load current channel 1, 2
V
S
6.5V
V
S
6.5V
Additional diagnostic functions channel 3 and channel 4 (regulated channels)
50
5
0.33
2.5
33,3
66,6
7.5
DC
I
OUT
QO3,4
Output duty cycle range
Overload current channel 3,4 filtered with 10ms
V
S
6.5V
10
2.5
5
V rerr
Recirculation error shutdown threshold (open D3/D4)
Iout > 50mA 45 50
PWM dOUT
Output PWM ratio during drift comparison
V
IN3
= V
IN4
= PWM
IN
V
TEST
= H
-14.3
Digital inputs (IN1 to IN4, ENA, CLK, TEST). The valid PWM-Ratio for IN3/IN4 is 10% to 90%
0.36
1
3.5
100
45
4.5
140
9
90
8
60
+14.3
x V mA
A
%
A
V
%
Q
V
V kHz
%
%
V
V
IL
V
IH
V
IHy
Input low voltage
Input high voltage
Input voltage hysteresis
(1)
-0.3
2
20
1
6
500
V
V mV
8/29
L9347 Electrical specifications
Table 3.
Electrical characteristcs : (continued)
(Vs = 4.8 to 18V; T j
= -40 to 150°C unless otherwise specified)
Parameter Test condition Symbol
I
I
Input pull down current
Digital outputs (ST1 to ST4)
V
STL
Status output voltage in low state
(2)
V
STH
V
IN
= 5V, V
S
Status output voltage in high state
(2)
I
ST
40 A
I
ST
-40 A
I
ST
-120 A
6.5V
R
DIAGL
R
DIAGH
R
R
OUT
OUT
+ R
+ R
DSON
DSON
Power outputs (Q1 to Q4)
in low state
in high state
R
R
V
V
DSON1,2
DSON3,4
F_250mA
F_2.25A
R
I
I sens
V
Z
PD
Qlk
Timing
I
Q
= 1A; V
S
9.5V
Static drain-source ON-resistance
Q1 and Q2
(non-reg. channels)
T j
= 25°C
T j
= 125°C
(3)
T j
= 150°C
(4)
I
Q
= 1A; V
S
9.5V
Static drain-source ON-resistance
Q3 and Q4
(reg. channels)
T j
= 25°C
T j
= 125°C
(3)
T j
= 150°C
(4)
Forward voltage of free wheeling path
D3, D4 @250mA
I
D3/4
= -250mA
Forward voltage of free wheeling path
D3, D4 @2.25A
I
D3/4
= -2.25A
Sense resistor = (V
F_2.25A-
V
F_250mA
)/2A
Z-diode clamping voltage
Output pull down current
Output leakage current
I
Q
100mA
V
EN
= H, V
IN
= L
V
EN
= L; V
Q
= 20V t
ON t
OFF t
OFFREG t r t f t sf t lf t
SCP
Output ON delay time
Output OFF delay time channel
Output OFF delay time regulator
Output rise time
Output fall time
Short error detection filter time
Long error detection filter time
Short circuit switch-OFF delay time
I
Q
= 1A
I
Q
= 1A
(5)
I
Q
= 1A
I
Q
= 1A f
CLK
= 250kHz DC = 50%
(5) f
CLK
= 250kHz DC = 50%
(5)
(5)
Min. Typ.
Max.
Unit
8 20 40 A
0.5
0.5
4
16
4
0
2.5
2
0.3
1.5
0.64
3.2
0.4
3.45
3.45
1.5
7.0
0.2
0.5
0.5
0.5
0.35
0.75
0.75
1.5
2.0
45
10
0
0
1
5
10
528
1.5
1.5
4.5
20
30
32
30
8
8
8
60
150
5
V
s
s
s
s
s
s
s
s
V
V
V k k
W
W
W
V
V
A
A
9/29
Electrical specifications L9347
Table 3.
Symbol t
D t
RE t
Dreg
Reg. current accuracy (reg. channels only)
I
Q3/Q4
I
Q3/Q4
Minimum current
Maximum current
I
REG
Electrical characteristcs : (continued)
(Vs = 4.8 to 18V; T j
= -40 to 150°C unless otherwise specified)
Parameter Test condition
Status delay time
(5)
Regulation error status delay time
Output off status delay time
(5)
(reg. channels only)
(5)
(reg. channels only
Max. regulation deviation @
DC 10% - 90%
DC = 10%
DC = 90%
250mA < I
Q3/Q4
400mA
I
Q3/Q4
< 400mA
800mA
800mA < I
Q3/Q4
< 2.25A
I
Q3/Q4
Frequencies
Min. quant. step
Min. Typ.
Max.
Unit
896 1024 us
200
2
10
528
250
2.25
5
300
2.5
±10
±6
±10 ms
s
E
Q
Voltages
V
S
V
CC
, V
DD
V
Q
V
Q
V
IN
, V
EN
V
CLK
V
ST
V
D
CLK frequency
Input PWM frequency crystal-controlled
(reg. channels only)
250
2 kHz kHz
1.
This parameter will not be tested but assured by design
2.
Short circuit between two digital outputs (one in high the other in low state) will lead to the defined result "LOW"
3.
Measured chip, bond wires not included
4.
Measured on Power SO-36 devices
5.
Digital filtered with external clock, only functional test
Table 4.
.
Absolute maximum ratings
The absolute maximum ratings are the limiting values for this device. Damage may occur if this device is subjected to conditions which are beyond these values
Symbol Parameter Test conditions Min Typ Max Unit
Switch off energy for inductive loads 50 mJ
V
DRmax
Supply voltage
Supply voltage
Output voltage static
Output voltage during clamping
Input voltage IN1 to IN4, EN
Input Voltage CLK
Output voltage status
Recirculation circuits D3, D4 max. reverse breakdown voltage of free wheeling diodes D3, D4 t < 1ms
I
I
< |10|mA
-0.3
-0.3
-1.5
-1.5
-0.3
40
6
40
60
6
6
6
40
55 V
V
V
V
V
V
V
V
V mA
A
%
%
% mA
10/29
L9347 Electrical specifications
Table 4.
Symbol
Absolute maximum ratings (continued)
The absolute maximum ratings are the limiting values for this device. Damage may occur if this device is subjected to conditions which are beyond these values
Parameter Test conditions Min Typ Max Unit
Currents
I
Q1/2
Output current for Q1 and Q2 >5
>3 internal limited internal limited
A
A I
Q3/4
Output current for Q3 and Q4
I
Q1/2
,
I
PGND1/2
I
Q3/4
,
I
PGND3/4
I
ST
Output current at reversal supply for Q1 and Q2
Output current at reversal supply for Q3 and Q4
Output current status pin
ESD Protection
ESD Electrostatical Discharging
ESD Output Pins (Qx, Dx)
MIL883C vs. Common GND
(PGND1-4 + GND)
-4
-2
-5
2
4
5
A
A mA kV kV
Table 5.
Symbol
Thermal data
Parameter Test conditions
T
T j jc
Junction temperature
Junction temperature during clamping
(life time)
T stg
T th
T hy
R thJC
Storage temperature
Overtemperature shutdown threshold
Overtemperature shutdown hysteresis
Thermal resistance junction to case
1.
This parameter will not be tested but assured by design.
T j
t = 30min
t = 15min
T stg
(1)
(1)
R thJC
Table 6.
Symbol
Operating range
Parameter
V
S
V
CC
, V
DD
Supply voltage
Supply voltage dV
S
/dt Supply voltage transient time
V
Q
Output voltage static
Test conditions
V
Q
Output voltage induced by inductive switching
Voltage will be limited by internal
Z-diode clamping
Min
-40
-55
175
Min.
4.8
4.5
-1
-0.3
V
ST
Output voltage status -0.3
Typ
10
2
Typ.
Max.
18
5.5
1
40
60
6
Max
150
175
190
150
200
Unit
V
V
V/ s
V
V
V
Unit
°C
°C
°C
°C
°C
K/W
11/29
Electrical specifications
Table 6.
Symbol
I
ST
T j
T jc
Operating range (continued)
Parameter
Output current status
Junction temperature
Junction temperature during clamping
L9347
Test conditions Min.
-1
-40
= 30min
= 15min
Typ.
Max.
1
150
175
190
Unit mA
°C
°C
12/29
L9347 Functional Description
3.1 Overview
The L9347 is designed to drive inductive loads (relays, electromagnetic valves) in low side configuration. Integrated active Zener-clamp (for channel1 and 2) or free wheeling diodes
(for channel 3 and 4) allow the recirculation of the inductive loads. All four channels are monitored with a status output. All wiring to the loads and supply pins of the device are controlled. The device is self-protected against short circuit at the outputs and overtemperature. For each channel one independent push-pull status output is used for a parallel diagnostic function.
Channel 3 and 4 work as current regulator. A PWM signal on the input defines the target output current. The output current is controlled through the output PWM of the power stage.
The regulator limits of 10% or 90% are detected and monitored with the status signal. The current is measured during recirculation phase of the load.
A test mode compares the differences between the two regulators. This “drift” test compares the output PWM of the regulators. By this feature a drift of the load during lifetime can be detected.
3.3
3.4
The INput, CLK, TEST and ENable inputs, are active high, consist of Schmidt triggers with hysteresis. All inputs are connected to pull-down current sources.
Output stages (not regulated) Channel 1 and 2
The two power outputs (5A) consist of DMOS power transistors with open drain output. The output stages are protected against short circuit. Via integrated Zener clamp diodes the overvoltage of the inductive loads due to recirculation are clamped to typ. 52V for fast shut off of the valves. Parallel to the DMOS transistors there are internal pull-down current sources. They are provided to assure an open load condition in the OFF state. With EN=low this current source is switched off, but the open load comparator is still active.
Current regulator stages Channel 3 and 4
The current-regulator channels are designed to drive inductive loads. The target value of the current is given by the duty cycle (DC) of the 2kHz PWM input signal. The following figure shows the relation between the input PWM and the output current and the specified accuracy.
13/29
Functional Description
Figure 3.
Input PWM to output current range
L9347
2250
Cu rre nt
p re ci sio n
+-10%
800
+- 6%
400
±10%
250
10
INPUT PWM[%]
90
The ON period of the input signal is measured with a 1MHz clock, synchronized with the external 250kHz clock. For requested precision of the output current the ratio between the frequencies of the input signal and the external 250kHz clock has to be fixed according to
.
Figure 4.
Current accuracy according to the input and clock frequency ratio
112.5
5.6%
125
0%
132
Regulator switched off f
CLK
/ f
IN
-10%
14/29
The theoretical error is zero for f
CLK
/ f
IN
= 125.
If the period of the input signal is longer than 132 times the period of the clock the regulator is switched off. For a clock frequency lower than 100kHz the clock control will also disable the regulator. For high precision applications the clock frequency and the input frequency have to be correlated.
L9347 Functional Description
The output current is measured during the recirculation of the load. The current sense resistor is in series to the free wheeling diode. If this recirculation path is interrupted the regulator stops immediately and the status output remains low for the rest of the input cycle.
The output period is 64 times the clock period. With a clock frequency of 250kHz the output
PWM frequency is 3.9kHz. The output PWM is synchronized with the first negative edge of the input signal. After that the output and the input are asynchronous. The first period is used to measure the current. This means the first turn-on of the power is 256
s after the first negative edge of the input signal.
As regulator a digital PI-regulator with the Transfer function for:
KI: and KP: 0.96
z – 1
for a sampling time of 256
s is realised.
To speed up the current settling time the regulator output is locked to 90% output PWM untill the target current value is reached. This happens alsowhen the target current value changes and the output PWM reaches 90% during the regulation. The status output gets low if the target current value is not reached within the regulation error delay time of t
RE
=10ms. The output PWM is than out of the regulation range from 10% to 90%.
The outputs are protected against current overload, overtemperature, and power-GND-loss.
The external clock is monitored by a clock watchdog. This clock watchdog detects a minimal frequency f
CLK,min and wrong clock duty cycles. The allowed clock duty cycle range is 45% to
55%. The current-regulator stages are protected against recirculation errors, when D3 or D4 is not connected. All these error conditions shut off the power stage and invert the status output information.
The status outputs indicate the switching state under normal conditions (status LOW = OFF; status HIGH = ON). If an error occurs, the logic level of the status output is inverted, as listed in the diagnostic table below. All external errors, for example open load, are filtered internally. The following table shows the detected errors, the filter times and the detection mode (on/off).
15/29
Functional Description L9347
Table 7.
Detected errors
ON State
EN &IN =
HIGH
OFF State
EN &IN =
LOW
Filter time
Reset done by
Short circuit of the load X t sf
EN & IN = “LOW” for T
D
or T
Dreg
Open load
(under voltage detection)
Open load
(under current detection)
X
X t lf t sf timer T
D timer T
D
Over temperature
Power-GND-loss
Signal-GND-loss
Supply-VS-loss
Clock control
Output voltage clamp active
X
X
X
X
X
X
(regulated channels)
X
X
X
X t sf t lf t lf t lf no no
EN & IN = “LOW” for T
D
or T
Dreg in on: EN & IN = “LOW” for T
D
or T
Dreg in off: timer T
D timer T
D timer T
D in on: EN & IN = “LOW” for T
D
or T
Dreg in off: timer T
D in on: EN & IN = “LOW” for T
D
or T
Dreg in off: timer T
D
EN&IN=low means that at least one between enable and input is low. For the inputs IN = low means also no input PWM. For the regulator input period longer than T
Dreg and for the standard channel input period longer thanT
D
.
A detected error is stored in an error register. The reset of this register is made with a timer
T
D
. With this approach all errors are present at the status output at least for the time T
D
.
All protection functions like short circuit of the output, overtemperature, clock failure or power-GND-loss in ON condition are stored into an internal “fail” register. The output is then shut off. The register must be reset with a low signal at the input. A “low signal” means that the input is low for a time longer than T
D
or T
DReg
for the reulated channel, otherwise it is interpreted as a PWM input signal and the register is left in set mode.
Signal-GND-loss and VS-loss are detected in the active on mode, but they do not set the fail register. This type of error is only delayed with the standard timer t lf function.
Open load is detected for all four channels in on and off state.
Open load in off condition detects the voltage on the output pin. If this voltage is below 0.33
* VS the error register is set and delayed with T
D
. A sink current stage pull the output down to ground, with EN high. With EN low the output is floating in case of openload and the detection is not assured. In the ON state the load current is monitored by the non-regulated channels. If it drops below the specified threshold value I
QU
an open load is detected and the error register is set and delayed with T
D
. A regulated channel detects the open load in the on state with the current regulator error detection. If the output PWM reaches 90% for a time longer than t
RE
than an error occurs. This could happen when no load is connected, the
16/29
L9347
3.7
3.8
Functional Description resistivity of the load is too high or the supply voltage too low. The same error is shown if the regulator is not able to reduce the current in the load in the time t
RE
, so the output PWM falls below 10%.
A clock failure (clock loss) is detected when the frequency becomes lower than f
CLK,min
. All status outputs are set on error and all power outputs are shut off. The status signals remain in their state until the clock signal is present again. A clock failure during power on of VCC is detected only on the regulated channels. The status outputs of the channel 1 and 2 are low in this case.
Drift detection (regulated channels only)
The drift detection is used to compare the two regulated channels during regulation. This
“Drift” test compares the output PWM of the regulators. The resistivity of the load influences the output PWM. The approximated formula for the output current below shows the dependency of the load resistor to the output PWM. In this formula the energy reduction during the recirculation is not taken into account. The real output PWM is higher. The testmode is enabled with IN,EN and TEST high. With an identical 2kHz PWM-Signal connected to the IN-inputs the output PWM must be in a range of +-14.3%. If the difference between the two on-times is more than ±14.3% of the expected value an error is detected and monitored by the status outputs, in the same way as described above, but a drift error will not be registered and also not delayed with T
D
as other errors
IOUT =
VBAT
PWM
RL + RON
Drift Definition:
Drift = PWM(1+E) - PWM (1-E) = 2PWM E
Drift * 4 < PWM (1+E) with E >14.3% a drift is detected
E.. not correlated Error of the channels
%PWM ... Corresponding ideal output PWM to a given input PWM
A 7bit output-PWM-register is used for the comparison. The register with the lower value is subtracted from the higher one. This result is multiplied by four and compared with the higher value.
Other test modes
The test pin is also used to test the regulated channels in the production. With a special sequence on this pin the power stages of the regulated channels can be controlled direct from the input. No status feedback of the regulated channels is given. The status output is clocked by the regulator logic. The output sequence is a indication of a proper logic
functionality. The functionality of this special test mode is shown in Table 8
.
17/29
Functional Description
Table 8.
EN
0
0
0
0
1
1
0
Special test mode functionality
In Test Out
0
1
X
X
X
1
X
X
1 off off off on
X on off
Status
X
1 test pattern test pattern test pattern test pattern test pattern
For more details about the test conditions see timing diagrams in
Note disable test mode
Drift mode test condition one test condition two test condition three test condition four test condition four
L9347
The status follows the input signal in normal operating conditions.
If any error is detected the status is inverted.
Table 9.
Diagnostic table
Operating Condition
Normal function
Open load or short to ground
Overload or short to supply
Latched overload
Reset latch
Reset latch
Overtemperature
Latched overtemperature
Reset latch
Reset latch
Recirculation error (reg.chn.)
Latched error
Reset latch
Reset latch
Test
Input
TEST
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Enable
Input
ENA
H
H
H –> L
H
H
H
H –> L
H
H
H
H –> L
H
H
H
L
L
L
L
H
H
Control
Input nonreg./reg. IN
Power
Output/Curr ent reg. Q
L
H/PWM
L
H/PWM
L
H/PWM
L
H/PWM
H/PWM
H/PWM
X
H/PWM –> L
H/PWM
H/PWM
X
H/PWM –> L
PWM
PWM
X
PWM –> L
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
OFF
OFF
OFF
ON
Status
Output
ST
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
X
X
H
L
18/29
L9347 Functional Description
Table 9.
Diagnostic table (continued)
Operating Condition
Test
Input
TEST
Enable
Input
ENA
Control
Input nonreg./reg. IN
Power
Output/Curr ent reg. Q
Clock failure (clock loss)
Drift
(2)
Failure
No failure
(1)
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H/PWM
L
H/PWM
L
H/PWM
H/PWM
H/PWM
1.
During power on sequence only detected on channel 3 and 4 (see description).
2.
This input combination is also used for an internal chip-test and must not be used.
OFF
OFF
OFF
OFF
OFF
OFF
ON
ON
Status
Output
ST
X
X
L
H
H
H
H
L
19/29
Timing diagrams
Figure 5.
Output slope, resistive load
V
I
V
IH
V
IL t
ON t f V
Q
V
S
85% V
S
15% V
S
99AT0061
Figure 6.
Overload switch OFF delay
I
Q
I
QO
I
QU
V
ST t
D t
OFF t r t
SCP t sf
00RS0001 t t t t
L9347
20/29
L9347
Figure 7.
Normal condition, resistive load, pulsed input signal
V
IN
Timing diagrams
V
Q
I
Q t
D
V
ST
99AT0063
Figure 8.
Current overload t
D
I
QU t
D
Reset Fail register
V
IN
V
Q
I
Q
Set Fail register
I
QO t
D
V
ST
99AT0064
21/29
Timing diagrams
Figure 9 and Figure 10 show diagnostic status output at different OPEN load current
conditions followed by normal operation.
Figure 9.
Under current condition t
D
L9347
V
IN
V
Q
I
Q t
D
V
ST
99AT0065
Figure 10.
Open load condition in the case of pulsed input signal
I
QU t
D
V
IN
V
Q
I
Q
I
QU t
D
V
ST
99AT0066
22/29
L9347 Timing diagrams
Figure 11.
Pulsed open load conditions (regulated and non-regulated channels)
V
IN
V
Q
I
Q
0.33 x V
S t lf t
D t lf
V
ST
99AT0067
2kHz PWM input signal)
Figure 12.
Normal condition, inductive load
500 μ s
V
IN
V
Q
I
Q
256
μ s
256 μ s
V
ST
99AT0068 t
DREG
Target Current
23/29
Timing diagrams
Figure 13.
Current overload
500
μ s
V
IN
V
Q
I
Q
I
QO
V
ST
99AT0069
Figure 14.
Recirculation error
500
μ s
V
IN t sf t
DREG
Set fail registor t
DREG
Reset Fail register
Reset Fail register
V
Q
I
Q target current
V
ST
99AT0070
Set Fail register
L9347
24/29
L9347 Timing diagrams
Figure 15.
Current regulation error (e.g. as a result of voltage reduction)
500
μ s
V
IN
V
Q
I
Q target current
V
ST
99AT0071
Figure 16.
Over temperature
Over temperature
Condition
500ms t
DREG
V
IN
PWM ratio
= 90% t
RE
Reset Fail register
V
Q
I
Q target current
Set Fail register
V
ST
99AT0072
25/29
Timing diagrams
Figure 17.
Test mode 4 VEN low
V
TEST
V
IN3/4
V
Q3/4
99AT0073
L9347
26/29
L9347 Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Figure 18.
PowerSO-36 mechanical data and package dimensions
DIM.
A a1 a2 a3 b c mm inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
3.60
0.1417
0.10
0
0.22
0.23
0.30
0.0039
3.30
0.10
0.38
0.0087
0.32
0.0091
0.0118
0.1299
0.0039
0.0150
0.0126
E3 e e3
G
H
D
D1
E
E1
E2
15.80
9.40
13.90
10.90
5.80
0.65
11.05
16.00 0.6220
9.80
0.3701
14.5
0.5472
11.10 0.4291
2.90
6.20
0.2283
0.0256
0.4350
0.6299
0.3858
0.5709
0.4370
0.1142
0.2441
0
15.50
0.10
15.90 0.6102
0.0039
0.6260
h
L
N s
0.8
1.10
1.10
0.0315
10˚ (max)
8˚ (max)
0.0433
0.0433
Note: “D and E1” do not include mold flash or protusions.
- Mold flash or protusions shall not exceed 0.15mm (0.006”)
- Critical dimensions are "a3", "E" and "G".
OUTLINE AND
MECHANICAL DATA
PowerSO-36
0096119 C
27/29
Revision history
Table 10.
Document revision history
Date Revision
06-July-2002
02-May-2007
25-Sep-2013
1
2
3
Changes
Initial release.
Package change, text modifications, corporate layout changes.
Updated disclaimer.
L9347
28/29
L9347
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