STMicroelectronics L9822E Datasheet
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L9822E
Octal serial solenoid driver
Features
■
■
■
■
■
■
■
■
■
■
Eight low R
DSon
DMOS outputs (0.5
@ I
O
=
1 A @ 25 °C V
CC
= 5 V ± 5 %)
8 bit serial input data (SPI)
8 bit serial diagnostic output for overload and open circuit conditions
Output short circuit protection
Chip enable select function (active low)
Internal 36 V clamping for each output
Cascadable with another octal driver
Low quiescent current (10 mA Max.)
Multipower BCD technology
Package Multiwatt 15 and PowerSO-20
PowerSO-20
Multiwatt 15
Description
The L9822E is an octal low-side solenoid driver realized in Multipower BCD technology particularly suited for driving lamps, relays and solenoids in automotive environment. The DMOS outputs L9822E has a very low power consumption.
Table 1.
Device summary
Order code
L9822E
L9822EPD
Package
Multiwatt 15
PowerSO-20
Data is transmitted serially to the device using the
Serial Peripheral Interface (SPI) protocol.
Status monitor function is available on all output lines.
Packing
Tube
Tube
September 2013 Rev 3 1/17 www.st.com
1
Contents
Contents
L9822E
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
CE high to low transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CE low to high transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2/17
L9822E
List of tables
List of tables
3/17
List of figures
List of figures
L9822E
4/17
L9822E Block diagram
Figure 1.
Block diagram
RESET
CE
SO
SCLK
SI
Q D
CK
PARALLEL
LOAD
SHIFT
CLOCK
Q0
:
:
:
Q7
8 BIT
SHIFT
REGISTER
PARALLEL
INPUTS
SERIAL
INPUT
100µs DELAY
TRIGGER OUTPUT
CLOCK RESET
D0
:
:
:
D7
8 BIT
PARALLEL
LATCH
Q7
:
:
:
Q0
FAULT RESET
INPUT
INTERNAL
ZENER CLAMP
CURRENT
LIMIT
INPUTS
OUTPUTS
1. . . . . 7
FAULT
INDICATORS
01
02
03
04
05
06
07
FAULT INDICATOR
00
OUTPUT 0
+
FAULT
REFERENCE
VOLTAGE
5/17
Pin description
Figure 2.
PowerSO-20 pin connection (top view)
GND
SO
V
CC
RESET
OUT7
OUT6
OUT5
OUT4
N.C.
GND
1
2
3
4
5
6
7
8
9
10
D94AT119
20
19
18
17
16
15
14
13
12
11
GND
SI
SCLK
CE
OUT0
OUT1
OUT2
OUT3
N.C.
GND
Figure 3.
Multiwatt 15 pin connection (top view)
12
11
10
9
8
7
6
5
4
15
14
13
3
2
1
MULT15
OUT 4
OUT 5
OUT 6
OUT 7
RESET
Vcc
SO
GND
SI
SCLK
CE
OUT 0
OUT 1
OUT 2
OUT 3
L9822E
6/17
L9822E Pin description
Table 2.
PowerSO20 pin #
Pin function
Multiwatt15 pin #
Name
1, 10, 11, 20
2
3
4
5-8, 13-16
9,12
17
18
19
8
9
10
11
1-4, 12-15
-
5
6
7
Function
GND
SO
V
CC
RESET
OUTPUT
1-7
N.C.
CE
SCLK
SI
Device ground.
This ground applies for the logic circuits as well as the power output stages.
Serial output.
This pin is the serial output from the shift register and it is tri-stated when CE is high. A high for a data bit on this pin indicates that the particular output is high. A low on this pin for a data bit indicates that the output is low.
Comparing the serial output bits with the previous serial input bits the external microcontroller implements the diagnostic data supplied by the L9822E.
Logic supply voltage - nominally 5V.
Asynchronous reset for the output stages, the parallel latch and the shift register inside the L9822E . This pin is active low and it must not be left floating. A power on clear function may be implemented connecting this pin to VCC with an external resistor and to ground with an external capacitor.
Power output pins.
The input and output bits corresponding to 07 are sent and received first via the SPI bus and 00 is the last. The outputs are provided with current limiting and voltage sense functions for fault indication and protection. The nominal load current for these outputs is 500mA, but the current limiting is set to a minimum of 1.05A.
The outputs also have on board clamps set at about 36V for recirculation of inductive load current.
Pins not connected.
Chip enable.
Data is transferred from the shift registers to the outputs on the rising edge of this signal. The falling edge of this signal sets the shift register with the output voltage sense bits coming from the output stages. The output driver for the SO pin is enabled when this pin is low.
Serial clock.
This pin clocks the shift register. New SO data will appear on every rising edge of this pin and new SI data will be latched on every SCLK’s falling edge into the shift register.
Serial input.
This pin is the serial data input. A high on this pin will program a particular output to be OFF, while a low will turn it ON.
7/17
Electrical specifications L9822E
3.1 Absolute maximum ratings
Table 3.
Absolute maximum ratings
Symbol Parameter
V
CC
V
O
DC logic supply voltage
Output voltage
I
I
Input transient current (CE, SI, SCLK, RESET, SO):
Duration time t = 1 s,
V
I
< 0
V
I
> V
CC
I
Odc
Continuos output current (for each output)
T j
, T stg
Junction and storage temperature range
– 0.7
– 0.7
7 V
40 V
– 25
+ 25
Internally limited
– 40 150 mA
A
°C
Table 4.
Thermal data
Symbol Parameter Multiwatt15 PowerSO20 Unit
R th j-case
Thermal resistance junction to case
R th j-amb
Thermal resistance junction to ambient
Max.
Max.
2
35
1.5
60
°C/W
°C/W
Table 5.
Electrical characteristics
(V
CC
= 5 V ± 5 %. T j
= – 40 to 125 °C ; unless otherwise specified)
Symbol Parameter Test Min.
V
OC
E
OC
Output clamping volt. I
O
= 0.5 A, Output programmed OFF
Output clamping energy I
O
= 0.5 A, when ON
I
O leak
Output leakage current V
O
= 24 V, Output programmed OFF
Output programmed ON
R
DSon
I
O
= 0.5 A
I
O
= 0.8 A
I
O
= 1 A
With fault reset disabled
I
OL
Output self limiting current
Output programmed ON t
PHL t
P
I
O
= 500 mA no reactive load
I
O
= 500 mA no reactive load
30
20
1.05
0.55
0.55
0.55
10
10
40
1
1
1
1
V mJ mA
A
µs
µs
8/17
L9822E Electrical specifications
Table 5.
Electrical characteristics (continued)
(V
CC
= 5 V ± 5 %. T j
= – 40 to 125 °C ; unless otherwise specified)
Symbol Parameter Test Min.
V
OREF
Fault refer. voltage
Output progr. OFF
Fault detected if V
O
> V
OREF t
UD
Fault reset delay (after
CE L to H transition)
V
OFF
Output OFF voltage Output pin floating. Output progr. OFF
Input buffer (SI, CE, SCLK and RESET pins) f op t lead t lag t wSCKH t wSCKL t su t
H t
EN t
DIS t
V t rSO t fSO
V
T–
Threshold voltage at falling edge SCLK only
V
CC
= 5 V ± 10 %
0.2V
CC
0.6
V
V
T+
Threshold voltage at rising edge SCLK only
V
CC
= 5 V ± 10 % V
V
H
Hysteresis V
T+
– V
T–
0.85
I
I
C
I
Input capacitance
V
CC
= 5.50 V, 0 < V
I
0 < V
I
< V
CC
< V
CC
– 10 + 10 µA
20 pF
Output buffer (SO pin)
0.7V
CC
4.15
V
SOL
Output low voltage I
O
= 1.6 mA 0.4 V
V
SOH
Output high voltage I
O
= 0.8 mA
V
CC
– 1.3V
V
I
C
I
SOtl
SO
CC
Output tristate leakage current
Output capacitance
Quiescent supply current at V
CC
pin
0 < V
O
< V
CC
, CE pin held high,
V
CC
= 5.25 V
0 < V
O
< V
CC
, CE pin held high
All outputs progr. ON. I
O output simultaneously
Serial peripheral interface (see Figure 5 , timing diagram)
= 0.5 A per
– 20 20
20
µA pF
10 mA t t t rSI fSI ho
Enable lead time
Clock low time
Data setup time
Data hold time
Data valid time
Rise time (SO output)
Fall time (SO output)
Rise time SPI inputs
(SCK, SI, CE)
Fall time SPI inputs
(SCLK, SI, CE)
Output data hold time
V
CC
V
CC
V
V
CC
CC
= 20 to 70 % C
= 70 to 20 % C
= 20 to 70 % C
= 70 to 20 % C
L
L
L
L
= 200 pF
= 200 pF
= 200 pF
= 200 pF
D.C.
250
250
200
200
75
75
250
250
100
200
200
0
1 V
2 MHz ns ns ns ns ns ns ns
50
50 ns ns ns ns ns ns
µs
9/17
Functional description L9822E
4.1
The L9822E DMOS output is a low operating power device featuring, eight 1
R
DSON
DMOS drivers with transient protection circuits in output stages.
Each channel is independently controlled by an output latch and a common RESET line which disables all eight outputs. The driver has low saturation and short circuit protection and can drive inductive and resistive loads such as solenoids, lamps and relays.
Data is transmitted to the device serially using the Serial Peripheral Interface (SPI) protocol.
The circuit receives 8 bit serial data by means of the serial input (SI) which is stored in an internal register to control the output drivers. The serial output (SO) provides 8 bit of diagnostic data representing the voltage level at the driver output. This allows the microprocessor to diagnose the condition of the output drivers.
The output saturation voltage is monitored by a comparator for an out of saturation condition and is able to unlatch the particular driver through the fault reset line. This circuit is also cascadable with another octal driver in order to jam 8 bit multiple data.
The device is selected when the chip enable (CE) line is low.
Additionally the (SO) is placed in a tri-state mode when the device is deselected. The negative edge of the (CE) transfers the voltage level of the drivers to the shift register and the positive edge of the (CE) latches the new data from the shift register to the drivers.
When CE is Low, data bit contained into the shift register is transferred to SO output at every
SCLK positive transition while data bit present at SI input is latched into the shift register on every SCLK negative transition.
Internal blocks description
The internal architecture of the device is based on the three internal major blocks:
1.
the octal shift register for talking to the SPI bus,
2. the octal latch for holding control bits written into the device
3. the octal load driver array.
The shift register has both serial and parallel inputs and serial and parallel outputs. The serial input accepts data from the SPI bus and the serial output simultaneously sends data into the SPI bus. The parallel outputs are latched into the parallel latch inside the L9822E at the end of a data transfer. The parallel inputs jam diagnostic data into the shift register at the beginning of a data transfer cycle.
10/17
The parallel latch holds the input data from the shift register. This data then actuates the output stages. Individual registers in the latch may be cleared by fault conditions in order to protect the overloaded output stages. The entire latch may also be cleared by the RESET signal.
L9822E Functional description
The output stages provide an active low drive signal suitable for 0.75 A continuous loads.
Each output has a current limit circuit which limits the maximum output current to at least
1.05A to allow for high inrush currents. Additionally, the outputs have internal zeners set to
36 volts to clamp inductive transients at turn-off. Each output also has a voltage comparator observing the output node. If the voltage exceeds 1.8 V on an ON output pin, a fault condition is assumed and the latch driving this particular stage is reset, turning the output
OFF to protect it. The timing of this action is described below. These comparators also provide diagnostic feedback data to the shift register. Additionally, the comparators contain an internal pulldown current which will cause the cell to indicate a low output voltage if the output is programmed OFF and the output pin is open circuited.
4.5 Timing transfer
Figure 5 shows the overall timing diagram from a byte transfer to and from the L9822E using
the SPI bus.
4.5.1 CE high to low transition
The action begins when the Chip Enable (CE) pin is pulled low. The tri-state Serial Output
(SO) pin driver will be enabled entire time that CE is low. At the falling edge of the CE pin, the diagnostic data from the voltage comparators in the output stages will be latched into the shift register. If a particular output is high, a logic one will be jammed into that bit in the shift register. If the output is low, a logic zero will be loaded there. The most significant bit (07) should be presented at the Serial Input (SI) pin. A zero at this pin will program an output ON, while a one will program the output OFF.
4.5.3
The Serial Clock (SCLK) pin should then be pulled high. At this point the diagnostic bit from the most significant output (07) will appear at the SO pin. A high here indicates that the 07 pin is higher than 1.8 V. The SCLK pin should then be toggled low then high. New SO data will appear following every rising edge of SCLK and new SI data will be latched into the
L9822E shift register on the falling edges. An unlimited amount of data may be shifted through the device shift register (into the SI pin and out the SO pin), allowing the other SPI devices to be cascaded in a daisy chain with the L9822E.
CE low to high transition
Once the last data bit has been shifted into the L9822E, the CE pin should be pulled high. At the rising edge of CE the shift register data is latched into the parallel latch and the output stages will be actuated by the new data. An internal 160 µs delay timer will also be started at this rising edge (see t
UD
). During the 160ms period, the outputs will be protected only by the analog current limiting circuits since the resetting of the parallel latches by faults conditions will be inhibited during this period.
This allows the part to overcome any high inrush currents that may flow immediately after turn on. Once the delay period has elapsed, the output voltages are sensed by the comparators and any output with voltages higher than 1.8 V are latched OFF. It should be noted that the SCLK pin should be low at both transitions of the CE pin to avoid any false clocking of the shift register. The SCLK input is gated by the CE pin, so that the SCLK pin is ignored whenever the CE pin is high.
11/17
Functional description
4.6
L9822E
Fault conditions check
Checking for fault conditions may be done in the following way. Clock in a new control byte.
Wait 160 µs or so to allow the outputs to settle.
Clock in the same control byte and observe the diagnostic data that comes out of the device.
The diagnostic bits should be identical to the bits that were first clocked in. Any differences would point to a fault on that output. If the output was programmed ON by clocking in a zero, and a one came back as the diagnostic bit for that output, the output pin was still high and a short circuit or overload condition exists.
If the output was programmed OFF by clocking in a one, and a zero came back as the diagnostic bit for that output, nothing had pulled the output pin high and it must be floating, so an open circuit condition exists for that output.
Figure 4.
Byte timing with asynchronous reset.
RESET
CE
SCLK
SI
SO
OUTPUTS
Figure 5.
Timing diagram.
CE
SCLK
SI
TLEAD
TEN
I/FOP TWSCKH
#7
TSU
TWSCKL
TH
#6
DI7
TV
SO D07 D06
OUTS
#7 #6 #5 #4 #3 #2 #1
#7 #6 #5 #4 #3 #2 #1 #0
OLD NEW
FAULTS
RESET
OLD
#0
TLAG
THD
DI0
TDIS
D00
TPHL
TPLH
FAULT-INDUCED
TURN/OFF
NEW
TUD
12/17
L9822E Functional description
Figure 6.
Typical application diagram
MICRO
CONTROLLER
WITH
SPI - bus
V
CC
CE
SI
SO
SCLK
RESET
GND
L9822E
03
04
05
00
01
02
06
07
L R
V bat
V
CC
= 5.0 V +/- 5 %
Vbat = 14.0 V +/- 0.5 V
R = 30 Ω +/- 5 %
L = 10mH +/- 10 %
8 loads up to 0.75 A each
13/17
Package information L9822E
14/17
In order to meet environmental requirements, ST (also) offers these devices in ECOPACK
® packages. ECOPACK
®
packages are lead-free. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard
JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 7.
PowerSO-20 mechanical data and package dimensions
DIM.
A a1 a2 mm inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.1
3.6
0.3
0.004
3.3
0.142
0.012
0.130
a3 b
0
0.4
c 0.23
D (1) 15.8
D1 (2) 9.4
E 13.9
e e3
1.27
11.43
0.1
0.53
0.32
16
9.8
14.5
0.000
0.016
0.009
0.622
0.370
0.547
0.050
0.450
E1 (1) 10.9
E2
E3
G
H
5.8
0
15.5
11.1
2.9
6.2
0.429
0.228
0.1
0.000
15.9
0.610
h
L
N
S
0.8
1.1
1.1
0.031
8˚(typ.)
8˚(max. )
T 10 0.394
(1) “D and E1” do not include mold flash or protusions.
- Mold flash or protusions shall not exceed 0.15mm (0.006”)
- Critical dimensions: “E”, “G” and “a3”.
(2) For subcontractors, the limit is the one quoted in jedec MO-166
0.437
0.114
0.244
0.004
0.626
0.043
0.043
0.004
0.021
0.013
0.630
0.386
0.570
OUTLINE AND
MECHANICAL DATA
Weight: 1.9gr
JEDEC MO-166
PowerSO-20
N N b
DETAIL A e3
H
R e a2 A
DETAIL B lead c
E a1
DETAIL A
D
20 11 a3
DETAIL B
Gage Plane
BOTTOM VIEW
S
0.35
L slug
- C -
SEATING PLANE
G C
(COPLANARITY) E2 E1
1 1
T
0
E3
D1
PSO20MEC h x 45˚
0056635 I
L9822E Package information
Figure 8.
Multiwatt 15 mechanical data and package dimensions
DIM.
A5
B
C
D mm inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
2.65
1.6
0.197
0.104
0.063
1 0.039
E
F
G
0.49
0.66
0.55
0.75
0.019
0.026
0.022
0.030
1.02
1.27
1.52
0.040
0.050
0.060
G1 17.53
17.78
18.03
0.690
0.700
0.710
H1 19.6
0.772
H2 20.2
0.795
L3
L4
L7
L
L1
L2
21.9
22.2
22.5
0.862
0.874
0.886
21.7
22.1
22.5
0.854
0.87
0.886
17.65
18.1
0.695
0.713
17.25
17.5
17.75
0.679
0.689
0.699
10.3
10.7
10.9
0.406
0.421
0.429
2.65
2.9
0.104
0.114
M
M1
S
4.25
4.73
1.9
S1 1.9
Dia1 3.65
4.55
5.08
4.85
5.43
0.167
0.186
2.6
0.075
2.6
3.85
0.075
0.144
0.179
0.200
0.191
0.214
0.102
0.102
0.152
OUTLINE AND
MECHANICAL DATA
Multiwatt15 (Vertical)
0016036 J
15/17
Revision history L9822E
Table 6.
Date
12-Jan-2002
27-Oct-2008
Document revision history
20-Sep-2013
Revision
1
2
3
Changes
Initial release.
Document reformatted.
Corrected in Table 5: Electrical characteristics
, the max. value of the parameter “C
I
Input capacitance”.
Updated Disclaimer.
16/17
L9822E
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