STMicroelectronics STNRGPF02 Datasheet
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STNRGPF02, STNRGPF12
Datasheet
2-channel interleaved PFC driver with embedded digital inrush current limiter function
Product status link
STNRGPF02
STNRGPF12
Product summary
Package Part number
TSSOP38
TSSOP38
STNRGPF02
STNRGPF12
Product label
Features
• Embedded digital inrush current limiter function
• Interleaved PFC digital controller
• Two interleaved channels PFC
• Continuous conduction mode
• Fixed frequency operation
• Average current mode control
• Mixed signal architecture
• Soft start-up management
• Burst mode support
• Load feed forward
• Input voltage feed forward
• Channel current balance function
• Programmable phase shedding
• Status indicator signaling for cooling system, PFC Fault and PFC OK
• Configurable driver by means of dedicated graphic tool
• Programmable fast overcurrent and thermal protection
• Serial communication port available for:
– Device programming;
– Monitoring of the PFC parameters
• Suitable for >600 W applications:
– Welding, air conditioner
– Industrial motors
– UPS, chargers, high power systems
• Customizable firmware
• Configuration via eDesign suite
• Embedded memory
– Program memory: 32 Kbytes flash
– Data retention 15 years at 85 °C after 10 kcycles at 25 °C
– Data memory: 1 Kbyte true data E 2 PROM; data retention: 15 years at 85
°C after 100 kcycles at 85 °C
– Flash and E 2 PROM with read while write (RWW) and error correction code
(ECC)
– RAM: 6 Kbytes
• Communication interfaces
– UART asynchronous protocol for bootloader support and monitoring of the
PFC parameters
• Operating temperature: -40 °C up to 105 °C
Description
The STNRGPF02/12 embed the Inrush Current Limiter function.
STNRGPF12 features a digital inrush current control generating two PWM’s signals in order to drives the input semi-controlled bridge.
DS12895 - Rev 2 - June 2020
For further information contact your local STMicroelectronics sales office.
www.st.com
STNRGPF02, STNRGPF12
STNRGPF02 embeds inrush current control function setting high a signal that is used to short a resistive element.
Documentation
This datasheet contains the description of features, pinout, pin assignment, electrical characteristics, mechanical data and ordering information.
• For information on programming, erasing and protection of the internal Flash memory, please refer to the RM0446 User Manual (see www.st.com
)
DS12895 - Rev 2 page 2/43
STNRGPF02, STNRGPF12
General description
1
1.1
1.1.1
General description
The STNRGPFx2 are digital controllers designed specifically for interleaved CCM boost PFC topologies in high power applications and embed the Inrush current limiter function.
The Interleaving technique splits the PFC management into two or more parallel channels depending on the load condition. The driving signal will be out of phase of a proper value.
This phase shift will be calculated basing on the number of paralleled channels according to the following formula:
Equation 1
Pℎase sℎift =
360° number of cℎannels
The benefits of the interleaved topology, compared to traditional single stage PFC, are measured in terms of reduction of EMI filter and inductor volume, and a reduction of rms capacitor current.
The STNRGPFx2 contain all the control functions for designing a high efficiency-mode power supply with sinusoidal line current consumption.
They work in CCM, fixed frequency with average current mode control, implementing a mixed signal (analog/ digital) control joining the advantages of very high-end digital solution without typical limits of analog ones.
In the mixed signal approach, the inner current loop is performed in hardware realizing an analog Proportional-
Integral (PI) compensator, and the outer voltage loop is performed by a digital PI controller with fast dynamic response.
The STNRGPFx2 can be configured by a dedicated software tool (eDesignSuite) in order to be customized for a specific application. So, the user has to open the software tool, enters the converter specs and runs the configurator. The results will be: Schematic, BoM, and Binary code containing the parameters calculated by the tool.
The binary code can be downloaded into the STNRGPFx2 through the programming software STSW-
STNRGPF01 (by means serial interface) having a customized device that can be used like analog device ready to use in application.
Inrush current limiter function description
The STNRGPFx2 devices have the Inrush Current Limiter function embedded. As soon as power supplies are connected to AC line, they are subject to short-duration, high amplitude, input current called “Inrush Current”. The inrush current continues until the voltage across the internal capacitors reaches approximately the peak amplitude of the input AC line. If uncontrolled, the inrush current can damage the components of the power supply. Several solutions can be adopted to limit this current and STNRGPFx2 devices are able to manage two control methods.
Inrush current limiter function with resistive element (STNRGPF02 only)
One method to limit the Inrush Current is to add a resistive element R (resistors, thermistors, etc.) in series with
DC capacitors. Figure 1 shows one implementation of this technique. As soon as the capacitor C is charged, no current flows, and the STNRGPF02 will do the ON signal to switch S1 in order to short R. In this way the losses during normal operation are minimized.
DS12895 - Rev 2 page 3/43
STNRGPF02, STNRGPF12
Inrush current limiter function description
Figure 1. STNRGPF02: Inrush current limiter with resistor in series to output capacitor
S1
C
V
AC
R
1.1.2
The switch S1 can be a silicon device as Triac or a mechanical switch of a relay.
Inrush current limiter function with controlled bridge (STNRGPF12 only)
The second method to control the charge current of output capacitor is to replace the input bridge rectifier with a controlled one, The STNRGPF12 modulates progressively the conduction time of the switches S1 and S2 in order to charge smoothly the output capacitor avoiding overcurrent’s in the systems. One implementation of this method circuit may use Silicon Controlled Rectifier (SCR) and the circuit in figure 2 is shown. The high side of input rectifier bridge it’s composed by SCR’s S1, S2 and the low side are diodes
Figure 2. STNRFPF12: Inrush current limiter with controlled rectifier bridge
V
AC
S1 S2
C
This methodology can be applied only when an inductor is present on the line. In this case an inductor is already present because the application is an Interleaved PFC.
DS12895 - Rev 2 page 4/43
2
STNRGPF02, STNRGPF12
STNRGPF02/12 control architecture
STNRGPF02/12 control architecture
The STNRGPFx2 digital controllers implement a mixed signal (analog/digital) control. The inner current loop is performed in hardware and the outer voltage loop is performed by a digital PI controller.
The device performs a cascaded control for voltage and current loops to regulate the output voltage by acting on the total average inductor current.
Figure 3. STNRGPF12 control scheme
DS12895 - Rev 2
shows the control scheme for STNRGPFx2 controllers. As can be seen the difference between output voltage feedback vout_fb and reference vout_ref is sent to Digital Voltage Control block (PI regulator) which calculate the peak of input average total current ipk_ref.
The PFC current reference is internally generated and come out from Multiplier block as PWM signal. After filtering it became the total average sinusoidal input current reference itot_ref for inner current loop (analog section, red line). The difference between the current reference itot_ref and the input current feedback Itot_fb is sent to Analog Current compensator PI.
So the master PWM signal is generated by comparing the analog PI output Vctrl and a triangular wave Vtriang at switching frequency. Finally, an interleaving operation is performed and two PWM signals 180° phase shifted drive
S1 and S2 power switches.
Moreover, the digital section includes an input voltage and load feedforward for fast transient response when main voltage changes suddenly or a load step current occurs, avoiding large over or under-voltage on output capacitor C.
page 5/43
3
3.1
STNRGPF02, STNRGPF12
STNRGPF02/12 blocks diagram
STNRGPF02/12 blocks diagram
The block diagram of both STNRGPF02/12 devices is shown in
Figure 4. STNRGPFx2 Block diagram
STNRGPFx2
Voltage & current loops
Status indicators Measurements
Driving
& Interleaving
Digital controller
Analog comparators
Programming
Start-up & Inrush function
Cooling system control
Voltage and current loops
The STNRGPFx2 controllers implement a mixed signal average current control. The task of digital voltage loop is to regulate the output voltage of the PFC. Vin and Iout measurements are used to implement Input/Output Feed-
Forward (I/O FFD), so load steps or input voltage variations are quickly compensated by acting on digital PI output calculations. This function allows to keep the output voltage to the setpoint value and as constant as
DS12895 - Rev 2 page 6/43
STNRGPF02, STNRGPF12
Measurements section
Figure 5. Voltage loop and current reference
3.2
3.2.1
The output of digital PI is the peak current reference. In order to obtain a sinusoidal current reference Ipk_ref is multiplied by a Look-Up Table (LUT). The LUT is synchronized with the Input voltage thanks to the ZVD signal
(pin 17). The output of multiplier is a PWM signal having sinusoidal Duty Cycle that is configured on Pin 4 SIN
REF.
An Analog filter is used to obtain the final sinusoidal current reference for the external current loop (Itot_ref). The analog current PI compare the reference Itot_ref with the total input current feedback (Itot_fb) and generate the duty cycle wave for PWM modulation. The master PWM signal is obtained by comparing (COMP2,3) the output of
and Section 3.4 PWM Section: driving & interleaving ).
Measurements section
•
•
•
•
•
•
•
The STNRGPFx2 include 4 input measurements channels. These inputs are defined from Pin 31 to Pin 38 and they are below specified.
Pin 31. Vin_L1: AC Input Voltage measurement Line 1
Pin 32. Temp: ambient temperature.
Pin 33. Iout: PFC output current.
Pin 34. Vout: PFC output voltage.
Pin 35. I[0]: RMS current channel [0]
Pin 36. I[1]: RMS current channel [1]
Pin 38 AVin_L2: AC Input Voltage measurement Line 2
AC input voltage measurement
The STNRGPFx2 have two dedicated pin’s, Pin 31 and Pin 38, for AC RMS line voltage measurement. The devices, by means two resistor dividers, measures simultaneously the instantaneous voltage on both pins, performs the difference between them and calculate the rms value (see
Vin_fb signal). Vin_fb (RMS AC input voltage) is used for the following functions: a) Normal operation. It’s used to generate the sinusoidal current reference signal.
b) AC input voltage variation. This signal is used to implements the Input Voltage Feed Forward that
DS12895 - Rev 2 page 7/43
Figure 6. Vin, Measurement
STNRGPF02, STNRGPF12
Measurements section
3.2.2
Ambient temperature measurements
Pin 32, Temp. Input for board temperature measurement. The PWM activity will be stopped when the temperature
device will stop the system.
Figure 7. Temperature measurement
DS12895 - Rev 2
The admissible voltage that the pin can accept is between 0 and 1.23 V page 8/43
STNRGPF02, STNRGPF12
Measurements section
3.2.3
3.2.4
•
Output Current measurement
Pin 33, Iout. PFC Output current. The measurement of this current allows to implement the following functions.
• Load feedforward. The input current reference is modified proportionally to the load, in order to give a faster response versus load transient.
Channels power management. Each channel can be enabled or disabled based on output current level. For example, up to 50% of the load, only one channel may be enabled, above 50% two channel configurations can be selected,
Output voltage sensing
•
•
Pin 34, Vout. Output Voltage sensing. This feedback input is connected via a voltage divider to the boost output voltage. The voltage divider will give the Vout_fb to Digital Voltage Control Block and it’s used in order to implements the following functions.
Output voltage regulation.
Over voltage protection
In
the block scheme of Vin Iout and Vout is reported.
Figure 8. Vin, Iout and Vout Measurement
3.2.5
Channel current measurement
Pin 35 Pin 36. ICH[0], ICH[1]: channel current measurements. These pins measure the currents flowing in each channel. The signal coming from sensing resistors is sent to a low pass filter and finally it’s connected to Pin 35 and Pin 36. The low pass filter must be sized so that its passband is about ten times lower than the switching frequency of the single channel. The result of this measurement is internally used to perform the current balance between the two channels.
DS12895 - Rev 2 page 9/43
STNRGPF02, STNRGPF12
Analog comparators section
Figure 9. Channel current measurement
3.3
Analog comparators section
The STNRGPFx2 include four fast analog comparators, COMP0 … 3.
COMP3 and COMP2 have external reference voltage and they are used to define the duty cycle of PWM0 master.
COMP1 and COMP0 have internal reference voltage and are used to realize overcurrent protections.
DS12895 - Rev 2 page 10/43
STNRGPF02, STNRGPF12
PWM Section: driving & interleaving
Figure 10. Analog comparators section
3.4
•
•
A description of the comparator pins is reported below.
•
•
•
Pin 24 OUT_PI[3]: Positive input of COMP3. It receives the out of analog PI current.
Pin 25 OUT_PI[2]: Positive input of COMP2. It receives the out of analog PI current.
Pin 26 TRIANG_REF: Negative common input analog COMP2,3. It receives the reference triangular waveform.
Pin 27: Positive input of COMP1. It receives the sensing signal of total input current.
Pin 28: Positive input of COMP0. It receives the sensing signal of all switch currents.
COMP0 stops the driving when an overcurrent occurs in any switch.
PWM Section: driving & interleaving
The STNRGPFx2 PWMs for channels driving are pins: 1 and 16. Below
Figure 11 shows the configuration for
PWMs generation.
DS12895 - Rev 2 page 11/43
Figure 11. Driving & interleaving
STNRGPF02, STNRGPF12
Programming section
3.5
Once the device is programmed as soon as the device is supplied the following sequence to generate the PWM starts:
• Pin n. 2 emits CLOCK signal at selected switching frequency. This pin must be connected to ENABLE pin (n.
6) and the clock signal will be internally used in order to enable the PWM GENERATION block. The
ENABLE signal moreover is used to avoid undesired commutations also when high level of noise is present.
•
•
The PWM0 signal trigger the SYNCR pin (pin 7) and internally the SET GENERATOR BLOCK will generate the SET pulse with an out of phase of 180º (for a correct interleaving) respect the PWM0 signal. The SET will fix the “ON” instant of PWM1 signal.
The SET signal comes out from the SET_O pin and will enter in the SET inputs (pin 18 SET_I) of an internal
FLIP FLOP.
The internal FLIP FLOP receives the SET from pin 18 and the RESET signal from PWM GENERATOR BLOCK and in this way it is able to generate the PW1 with the right out of phase respect to PWM0. The PWM1 comes out from the pin 16 “PWM1”.
Programming section
Device programming is done by using: a PC with a dedicated loader software (STSW-STNRGPF01), a FTDI cable and an adapter board (See
DS12895 - Rev 2 page 12/43
Figure 12. Programming section
STNRGPF02, STNRGPF12
Status indicator
3.6
Status indicator
The STNRGPFx2 include two pin to identify the running or fault status. These functions are defined on Pin 14 and
)
Figure 13. Status Indicator
3.7
Start-up & Inrush Current Limiter function
The start-up function can be divided in two phases. The first phase is the Inrush Current Limiter and the second phase is the PFC Soft Power-On.
DS12895 - Rev 2 page 13/43
In
Figure 14 the timing of start-up sequence is reported.
Figure 14. Start-Up sequence
Vout
Vout_ref
STNRGPF02, STNRGPF12
Start-up & Inrush Current Limiter function
Vin_pk
3.7.1
Inrush current limiter
ON
T INRUSH
Inrush current limiter
OFF
T START
PFC Soft Power-On Time
T BURST
Initially the device performs the function of “Inrush Current Limiter” and after the Tinrush time it stops this phase.
Sequentially it applies a short delay and at the end starts the PFC Soft Power-On procedure increasing the Vout voltage up to the nominal voltage (Vout ref).
Inrush Current Limiter Function
The devices embed the Inrush Current Limiter Function. There are several topologies to perform this function but the most used are the following:
1.
Inrush Current Limiter function with limiter resistor and bypass relay. This solution consists to insert a resistor in series with the output capacitors. The capacitor Inrush current is limited by a resistor or a thermistor. As soon as the capacitor is charged in STNRGPF02 set high pin 21 and this signal is used to
short resistor using the Switch S1 (See Figure 15
) in order to reduce the power losses. This switch S1 can be a silicon-based switch or mechanical contact of a relay.
Figure 15. Inrush Current Limiter function with limiter resistor and bypass relay
S1
V
AC
R
C
2.
Digital Inrush Current Limiter function with a semi-controlled input bridge: Another topology uses a semicontrolled bridge composed by two silicon switches T1, T2 (SCR, IGBT….) and two separate diodes for the inrush path. T1, T2 are modulated ON and OFF by the controller in order to limit the peak current but this can work if an inductor is present in series with the line. (see
DS12895 - Rev 2 page 14/43
STNRGPF02, STNRGPF12
Start-up & Inrush Current Limiter function
Figure 16. Digital Inrush Current Limiter function with a semi-controlled input bridge
T1 T2
L
V
AC
STNRGPF12 has embedded this technique, and it drives T1 and T2 alternately according the polarity of the mains and applying a short ON time. To reduce the inrush current the switches are triggered at the end of the line voltage. In this way the output capacitors initially are charged at low voltage and after it will increase smoothly allowing also a better control of the Inrush current.
Figure 17. Digital Inrush Current Limiter function: sequence of driving of the SCR v
AC DC Bus t
T1
3.7.2
T2
T
OFF
T
OFF
- T
ON
T
ON
T
T
OFF
- 2T
ON
2T
ON 3T
ON
T
OFF
-3T
ON
4T
ON
T T T T T
In order to charge the output capacitors up to the peak voltage of AC mains, the switches T1 and T2 must be
triggered on the following cycle with TON phase shift respect the previous one. (See Figure 17
). If this Step
Phase Shift is very short (few microseconds) from half cycle to half cycle, thanks to the presence of the PFC inductors, the capacitors will be charged maintaining low the line current. Usually this delay is constant, and we call this technique “Constant Progressive Step Phase Control”.
•
PFC Soft Power-ON
After the inrush current limiter phase the device will performs the Soft Power-On phase. The current reference will generate a constant reference signal and both PWM0 and PWM1 channels will be activated. In this phase the
PFC output voltage will increase up to the setpoint (Vout_ref).
As soon as the PFC Soft Power ON procedure is completed and the voltage reaches the setpoint Vout_ref (See
Figure 18 ) the device performs the following operations:
The PFC_OK pin is pulled low . When this pin is low indicates that the PFC is ready for load connection on the output.
DS12895 - Rev 2 page 15/43
STNRGPF02, STNRGPF12
Start-up & Inrush Current Limiter function
• The device will enter in Burst Mode regulation.
The PFC output voltage will oscillate between two settable levels (Vburst_min and Vburst_max). These levels can be defined during device customization.
Figure 18. Running mode or Burst mode
Vout
Vburst_max
Vburst_min
Vout_ref
Vin_pk
3.7.3
PFC_OK PFC_OK
T
START
PFC Soft Power-On
(a)
PFC Running Mode PFC Burst Mode Time
(b)
As soon as the PFC_OK pin becomes low two conditions may occur: The load is applied.
a) The device immediately will regulate the output voltage at Vout_ref value.
b) The PFC remains in no-load condition: the output voltage will range between Vburst_min and
Vburst_max until the load will be applied Figure 18
(b)
Fan control
The device offers the possibility to realize a control on cooling system. The customer will defines the power level for the function activation. Pin 20 , FAN gives a CMOS/TTL signal that became low for power level higher than the specified threshold. See
DS12895 - Rev 2 page 16/43
Figure 19. Fan Control function
STNRGPF02, STNRGPF12
Start-up & Inrush Current Limiter function
DS12895 - Rev 2 page 17/43
4
4.1
STNRGPF02, STNRGPF12
Pinout and pin description
Pinout and pin description
Pinout
Figure 20. STNRGPF12 - TSSOP38 pinout
DS12895 - Rev 2 page 18/43
STNRGPF02, STNRGPF12
Pin description
Figure 21. STNRGPF02 - TSSOP38 pinout
4.2
Pin description
1
N
OP
TYPE
2
3
O
O
NAME
STNRGPF12
PWM[0]
CLOCK
OFFSET
Table 1. Pin description
NAME
STNRGPF02
PWM[0]
PIN DESCRIPTION
This pin generates the PWM0 for the channel CH[0]
This pin generates a PWM signal at selected working frequency having duty cycle 50%. This signal it's used to generate a triangular waveforms at switching frequency by means an external op_amp. The CLOCK signal is also used to realize a protection against undesired commutations
This pin generated a PWM signal in order to compensate the offset of the external operational amplifier that performs the current loop PI compensator.
DS12895 - Rev 2 page 19/43
DS12895 - Rev 2
STNRGPF02, STNRGPF12
Pin description
OP
I
O
O
OP
NC
NC
PS
PS
PS
I
O
O
8
14
15
16
17
9
10
11
12
13
18
19
20
4
5
6
7
21
22
23
24
25
N TYPE
I
I
I
OP
OP
OP
O
AI
AI
NAME
STNRGPF12
SCR[0]
SCR[1]
RES[0]
RES[1]
V
DD
V
SS
V
OUT
P
FC_FAULT
P
FC_OK
PWM[1]
ZVD
NAME
STNRGPF02
SIN_REF
SET_O
ENABLE
SYNCR[2]
SET_I
OCP
FAN
PTX
PRX
OUT_PI[3]
OUT_PI[2]
RES[2]
RELAY
PIN DESCRIPTION
This pin generates a PWM signal with sinusoidal duty cycle. This PWM signal must be filtered in order to have the current sinusoidal reference that is synchronized with input voltage mains.
This pin generates a pulse in order to trigger set ON the
CH1 channel with the right out of phase. This pin must be connected to pin 18
This pin receive the CLOCK signal in order to avoid undesired commutation
This pin receives the PWM0 signal in order to synchronize the others channels. The falling edge of PWM0 signal is used to trigger OFF the slave channels CH1 and CH2
STNRGPF12 : This pin generates the PWM signal in order to drive one of the two switches in the input semicontrolled bridge to performs the Inrush Current Limiter feature. The switch can be an SCR. STNRGPF02 : Reserved
Reserved
Reserved
Supply Voltage
Ground
Supply Voltage of digital section. An external capacitor must be connected to VOUT pin.
During normal operation this pin is high. If a fault condition happens it’s forced low.
During fault condition this pin is high. When the PFC is ready for load connection it’s forced low.
This pin generates the PWM for the channel CH1
This pin receives a square wave signal synchronized with input AC voltage. The rising edge of square wave signal is used by the STNRGPF12 to detect the ZVD instant.
This pin receives a pulse in order to trigger ON the CH1 channel. This pin must be connected to pin 5
During normal operation this pin is high. If an overcurrent occurs, it's forced low instantaneously
It generates a CMOS/TTL signal that is low until the PFC output power is below a threshold defined during device customization
STNRGPF12: This pin generates the PWM signal in order to drive one of the two switches in the input semicontrolled bridge to performs the Inrush Current Limiter feature. The switch can be an SCR. STNRGPF02: It generates a signal that is low during the inrush phase. As soon as the inrush phase is completed this signal became high and it can be used to short the limiter resistor or to disable any current limiter apparatus
Programming data transmit
Programming data receive
Positive input of internal analog comparator 3. It receives the out of analog PI current
Positive input of internal analog comparator 3. It receives the out of analog PI current page 20/43
4.3
STNRGPF02, STNRGPF12
Input/output specification
26
27
28
29
30
31
32
33
34
35
36
37
38
N
AI
AI
AI
PS
PS
MI
MI
MI
MI
MI
MI
RI
MI
TYPE
NAME
STNRGPF12
TRIANG REF
NAME
STNRGPF02
OCP[0]
OCP[1
V
DDA
V
SSA
V
IN_L1
ICH[2]
TEMP
V
ICH[0]
ICH[0]
V
I
OUT
OUT
IN-L2
RES[3]
1. In the following table the legend of pin type is shown.
PIN DESCRIPTION
Negative input analog comparators 3 and 2. It receives voltage triangular waveform
Input overcurrent protection
Inductor overcurrent protection
Analog supply voltage
Analog ground
This pin is one of the two inputs for the RMS input voltage measurements. A divider resistor is connected to line/ neutral input wire
TThis pin is used to performs a double function : 1) monitoring the ambient board temperature. This measurement is realized using the curve of STLM20 device that give an output voltage proportional to temperature. 2) overtemperature protection: if the voltage falls below a settable treshold the device enter in fault mode and will stop the PFC.
This pin measures the PFC output current
This pin measures the PFC output voltage
This pin measure the rms current for channel CH[0]
This pin measure the rms current for channel CH[1]
Reserved. This pin must be pulled down by means a 10k resistor
This pin is one of the two inputs for the RMS input voltage measurements. A divider resistor is connected to line/ neutral input wire
Table 2. Legend of the pins
TYPE
OP
O
I
I/O
PS
AI
MI
Pin identification
PWM driver
Digital output
Digital input
Digital bidirectional
Power supply
Analog input
Measure input
Input/output specification
•
•
The STNRGPFx2 family includes three different I/O types:
• Normal I/Os (O or I);
Fast I/O (OP);
High speed I/O (CLOCK)
The STNRGPFx2 I/Os are designed to withstand current injection. For a negative injection current of 4 mA, the resulting leakage current in the adjacent input does not exceed 1 μA.
DS12895 - Rev 2 page 21/43
STNRGPF02, STNRGPF12
Electrical characteristics
5
Electrical characteristics
5.1
5.1.1
5.1.2
5.1.3
5.1.4
Parameter conditions
Unless otherwise specified, all voltages are referred to V
SS.
V
DDA
and V
DD
must be connected to the same voltage value. V
SS
and V
SSA
must be connected together with the shortest wire loop.
Minimum and maximum values
Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with the ambient temperature at T
A
= 25 °C and T
A
= T
A
max. (given by the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics are indicated according to each table’s specific notes and are not tested in production.
Typical values
Unless otherwise specified, typical data are based on T
A
= 25 °C, V
DD
and V
DDA
= 3.3 V. They are given only as design guidelines and are not tested. For the measurement section the accuracy is determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range.
Typical curves
Unless otherwise specified, all typical curves are given as design guidelines only and are not tested.
Typical current consumption
For typical current consumption measurements, V
DD
and V
DDA
are connected as shown in Figure 22
Figure 22. Supply current measurement conditions
5.1.5
Loading capacitors
The loading conditions used for pin parameter measurement are shown in
DS12895 - Rev 2 page 22/43
Figure 23. Pin loading conditions
STNRGPF02, STNRGPF12
Absolute maximum ratings
5.1.6
Pin output voltage
The input voltage measurement on a pin is described in Figure 24
.
Figure 24. Pin input voltage
5.2
Absolute maximum ratings
Stresses above those listed as 'absolute maximum ratings' may cause permanent damage to the device. This is a stress rating only and the functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect the device reliability.
Symbol
V
DDX
–V
SSX
VIN
Table 3. Voltage characteristics
Ratings
Input voltage on any other pin
Min.
-0.3
V
SS
-0.3
Max.
6.5
V
DD
+0.3
Unit
V
DS12895 - Rev 2 page 23/43
5.3
STNRGPF02, STNRGPF12
Operating conditions
V
V
DD
SS
–V
–V
DDA
SSA
Symbol Ratings
Variation between different power pins
Variation between all the different
Min.
Max.
50
50
Unit mV
1. All power V
DDX
(V
DD
, V
DDA
) and ground V
SSX
(V
SS
, V
SSA
) pins must always be connected to the external power supply
2. I
INJ(PIN)
mustnever be exceeded. This is implicitly insured if V
IN
maximum isrespected. If V
IN
maximumcannot be respected, the injection current must be limited externally to the I
INJ(PIN)
value.A positive injection is induced by V
IN
> V
DD
whilea negative injection is induced by V
IN
<V
SS
.
3. V
SS and V
SSA
signals must be interconnected together with a short wire loop
Table 4. Current characteristics
Symbol Ratings
Unit
I
I
I
VDDX
VSSX
IO
Total currentinto V
DDX
Total current out of V
SSX
Output current sunk by any I/Os and control pin
Output current source by any I/Os and control pin
100
100
mA
I
INJ(PIN)
I
INJ(TOT)
Injected current on any pin
Sumofinjected currents
±4
±20
1. Data based on characterization results, not tested in production.
2. All power V
DDX
(V
DD
, V
DDA
) and ground V
SSX
(V
SS
, V
SSA
) pins must always be connected to the external power supply.
3. I
INJ(PIN)
must never be exceeded. This is implicitly insured if V
IN
maximum is respected. If V
IN
maximum cannot be respected, the injection current must be limited externally to the I
INJ(PIN)
value. A positive injection is induced by V
IN
> V
DD while a negative injection is induced by V
IN
< V
SS
4. Negative injection disturbs the analog performance of the device.
5. When several inputs are submitted to a current injection, the maximum I
INJ(PIN)
is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterization with the I
INJ(PIN) current injection on four I/O port pins of the device.
maximum
T
STG
T
J
Symbol
Table 5. Thermal characteristics
Ratings
Storage temperature range
Maximum junction temperature
Max.
-65 to 150
150
Unit
ºC
Operating conditions
The device must be used in operating conditions that respect the parameters listed in
. In addition, a full account must be taken for all physical capacitor characteristics and tolerances.
Symbol
V
DD1
, V
DDA1
V
DD
, V
DDA
V
COUT
Table 6. General operating conditions
Parameter
Operating voltages
Nominal operating voltages
Core digital power supply
Conditions
-
-
Min.
3
-
-
Typ.
-
5
1.8
Max.
5.5
-
-
Unit
V
DS12895 - Rev 2 page 24/43
STNRGPF02, STNRGPF12
Operating conditions
5.3.1
V
Symbol
(Continued)
COUT
Parameter
C
VOUT
: capacitance of external capacitor
ESR of external capacitor
ESL of external capacitor
FR4 multilayer PCB
Conditions at 1 MHz
Min.
470
0.05
-
Typ.
-
-
-
Max.
3300
0.2
15
Unit nF
Ω nH
Θ
JA
T
A
Ambient temperature
TSSOP38
Pd =100 mW
-
-40
80
-
-
105
°C/W
°C
1. Internal core power supply voltage.
2. To calculate P
Dmax
(T
A)
, use the formula P
Dmax
= (T
Jmax
- T
A)
/Θ
JA
.
3. Care should be taken when the capacitor is selected due to its tolerance, its dependency on temperature, DC bias and frequency.
Table 7. Operating conditions at power-up/power-down
Symbol Parameter Conditions t
VDD
VDD rise time rate
VDD fall time rate t
TEMP
V
IT+
V
IT-
V
HYS(BOR)
Reset release delay
Power-on reset threshold
Brownout reset threshold
Brownout reset hysteresis
VDD rising
1. Guaranteed by design, not tested in production.
2 μs/V
2 μs/V
2.65
2.58
Typ.
3
2.8
2.73
70
Max.
2.98
2.88
Unit ms
V mV
VOUT external capacitor
The stabilization of the main regulator is achieved by connecting an external capacitor C
VCOUT
to the VCOUT pin.
C
VCOUT
is specified in
Table 6. General operating conditions .
Care should be taken to limit the series inductance to less than 15 nH.
Figure 25. External capacitor CVOUT
5.3.2
Supply current characteristics
The STNRGPFx2 current consumption is declared based on, for example, an application where the application firmware is loaded and running.
Table 8. Supply current characteristics
Symbol Parameter Test condition
V
DD
/V
DDA
SECTION: current consumption
Min.
Typ.
Max.
Unit
DS12895 - Rev 2 page 25/43
STNRGPF02, STNRGPF12
Operating conditions
5.3.3
5.3.4
5.3.5
IDD
Symbol
(RUN)
Parameter
Total current consumption
Test condition
V
DD
/V
DDA
= 5 V
Min.
28
Typ.
34
Max.
mA
Unit
1. Test conditions: data based on characterization results not tested in production. Temperature operating: T
A in run mode.
= 25 °C.Device
Memory characteristics
Flash program and memory/data E 2 PROM.
General conditions: T
A
= -40 °C to 105 °C.
Table 9. Flash program memory/data E 2 PROM t
Symbol
PROG
Parameter
Standard programming time (including erase) for byte/word/block
Fast programming time for 1 block (128 bytes)
Erase time for 1 block (128 bytes)
Conditions
Typ
6
3
Max
6.6
3.3
Unit ms t
ERASE
3 3.3
I t
NWE
RET
DDPRG
Erase/write cycles
T
A
= 25°C
T
A
= 85°C
Erase/write cycles
T
A
= 105°C
Data retention (program memory) after
10K erase/write cycles at T
A
= 25°C
Data retention (program memory) after
10K erase/write cycles at T
A
= 25°C
T
RET
T
= 85°C
RET =
105°C
Data retention (data memory) after
100K erase/write cycles at TA= 85°C
Data retention (data memory) after 35K erase/write cycles at T
A
= 105°C
T
RET
T
= 85°C
RET
=
105°C
Supply current during program and erase cycles
-40 ºC ≤ T
A
≤ 105 ºC
10K
100K
35K
15
11
15
6
2
Cycles
Years mA
1. Data based on characterization results, not tested in production.
2. The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation addresses a single byte.
•
Input/output specifications
The STNRGPFx2 device includes three different I/O types:
• Normal I/Os (O or I);
• Fast I/O (OP);
High speed I/O (CLOCK).
The STNRGPFx2 I/Os are designed to withstand the current injection. For the negative injection current of 4 mA, the resulting leakage current in the adjacent input does not exceed 1 μA
I/O port pin characteristics
Subject to general operating conditions for V
DD
and T
A be left floating.
unless otherwise specified. Unused input pins should not
DS12895 - Rev 2 page 26/43
STNRGPF02, STNRGPF12
Operating conditions
5.3.6
Symbol
V
IL
V
IH
V
OL1
V
OL3
V
OH1
V
OH3
Table 10. Voltage DC characteristics
Description
Input low voltage
Output low voltage at 5 V
Output low voltage high sink at 5 V (2) ,
-0.3
0.7 x V
DD
-
-
Typ
-
-
-
-
V
DD
-0.5
-
Output high voltage at 5 V (3)(4)
Output high voltage high sink at 5 V
,
V
DD
-0.6
-
H
VS
R
PU
Hysteresis input voltage
Pull-up resistor
0.1 x V
30
DD
1. Data based on characterization result, not tested in production.
2. Input signals can't be exceeded V
DDX
(V
DDX
= V
DD
, V
DDA
).
3. The parameter applicable to signals on pins 14, 15, 20, 21, 22 and 23.
4. The parameter applicable to signals on pins 1, 4, 5, 8 16 and 19.
5. The parameter applicable to the signal on pin 2.
6. Applicable to pins 3, 6, 7, 17 and 18.
-
45
Max
0.3 x V
DD
V
DD
0.5
0.6
-
-
-
60
Unit
V kΩ
Table 11. Current DC characteristics
Symbol
I
OL1
I
OLhs1
I
OH1
I
OHhs1
I
LKg
I
_Inj
∑
I_Inj
Description
Standard output low level current at 5 V and V
High sink output low level currentat 5 V and V
Input leakage current digital - analog VSS ≤ V
Injection current
OL1
OL3
Standard output high level current at 5 V and V
High sink output high level current at 5 V and V
OH1
IN
OH3
≤ V
DD
Total injection current sum of all I/O and control pins) (6)
Min
-
-
-
-
-
-
-
Typ
-
-
-
-
-
-
-
3
7.5
3
7.5
± 1
± 4
± 20
1. Data based on characterization result, not tested in production.
2. The parameter applicable to signals on pins 14, 15, 20, 21, 22 and 23.
3. The parameter applicable to signals on pins 1, 4, 5, 8 16 and 19.
4. The parameter applicable to the signal on pin 2.
5. Applicable to pins 3, 6, 7, 17 and 18.
6. Maximum value must never be exceeded.
7. Negative injection current on pins 31, 32, 33 and 34 must be avoided. It has impact on the measurement section.
Typical output level curves
This section shows the typical output voltage level curves measured on a single output pin for the three-pad family present in the STNRGPFx2 devices.
Normal I/Os
These pads are associated with the O type pins.
Unit mA
µA mA
DS12895 - Rev 2 page 27/43
Figure 26. V
OH
normal pin
STNRGPF02, STNRGPF12
Operating conditions
Figure 27. V
OL
normal pin
DS12895 - Rev 2
Fast I/Os
These pads are associated with the OP type pins.
page 28/43
Figure 28. V
OH
fast I/Os pins
STNRGPF02, STNRGPF12
Operating conditions
Figure 29. V
OL
fast I/Os pins
DS12895 - Rev 2
Output CLOCK
This pad is associated with the OUTPUT CLOCK pin.
page 29/43
Figure 30. V
OH
CLOCK pin
STNRGPF02, STNRGPF12
Operating conditions
Figure 31. V
OL
CLOCK pin
5.3.7
Reset pin characteristics
Subject to general operating conditions for V
DD
and T
A
unless otherwise specified.
DS12895 - Rev 2 page 30/43
STNRGPF02, STNRGPF12
Analog input characteristics
5.4
5.4.1
5.4.2
Table 12. NRST pin characteristics
Symbol
V
IL(NRST)
V
IH(NRST)
V
OL(NRST)
R
PU(NRST) t
IFP(NRST) t
INFP(NRST) t
OP(NRST)
Parameter
NRST input low level voltage
NRST output low level voltage
NRST input filtered pulse
NRST not input filtered pulse
NRST output filtered pulse
Conditions
I
OL
= 2 mA
1. Data based on characterization results, not tested in production.
2. The RPU pull-up equivalent resistor is based on a resistive transistor.
3. Data guaranteed by design, not tested in production.
Analog input characteristics
Min
-0.3
0.7 x V
DD
30
500
15
Typ
40
Max
0.3 x V
DD
V
DD
+ 0.3
0.5
60
75
Unit
V kΩ ns
µs
Measurement section
Subject to general operating conditions for V
DDA
and T
A
unless otherwise specified.
It applies to the [MI] class.
Table 13. Measurement pin characteristics
Symbol
RIN
VIN
Input impedance
Measurement range
Parameter
Vref Measure reference voltage
1. Maximum input analog voltage cannot exceed V
DDA
.
2. Reference voltage at TA = 25 °C.
Analog section
In
Table 14. Analog comparator characteristics
s are reported.
It applies to the [AI] class.
Conditions
-
-
-
Min.
1
0
-
Typ.
-
-
1.25
Max.
-
1.25
Unit
M
V
DS12895 - Rev 2 page 31/43
STNRGPF02, STNRGPF12
EMC characteristics
5.5
5.5.1
5.5.2
Table 14. Analog comparator characteristics
Symbol Parameter Conditions
V
V
V
CPP01
CPP23
CPM23
Comparator CP0,1 positive input voltage range
Comparator CP2,3 positive input voltage range
Comparator CP2,3 negative external input voltage range
-40 ºC ≤ TA ≤ 105 ºC
-40 ºC ≤ TA ≤ 105 ºC
-40 ºC ≤ TA ≤ 105 ºC
C
IN
V offset t
COMP
Input capacitance
Comparator offset error
Comparison delay time
-
-
-
1. Data based on characterization results, not tested in production.
2. Maximum analog input voltage for comparators CP0 and CP1.
3. Maximum analog input voltage for comparators CP2 and CP3.
4. The overdrive voltage is ± 50 mV.
EMC characteristics
0
0
0
Min.
-
-
-
-
-
3
Typ.
Unit
1.23
V
-
15
50
V
V pF mV ns
Electrostatic discharge (ESD)
Electrostatic discharges (3 positive then 3 negative pulses separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device
[3 parts * (n + 1) supply pin].
Table 15. ESD absolute maximum ratings (Data based on characterization results, not tested in production).
Symbol Maximum value Unit
V
ESD(HBM)
V
ESD(CDM)
V
ESD(MM)
Ratings
Electrostatic discharge voltage
(human body model)
Electrostatic discharge voltage
(charge device model)
Electrostatic discharge voltage
(machine model)
Conditions
T
A
= 25 °C, conforming to
JEDEC/JESD22-A114E
T
A
= 25 °C, conforming to
ANSI/ESD STM 5.3.1 ESDA
T
A
= 25 °C, conforming to
JEDEC/JESD-A115-A
2000
500
200
V
Static latch-up
Two complementary static tests are required on 10 parts to assess the latch-up performance.
A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD78 IC latch-up standard.
LU
Symbol
Table 16. Electrical sensitivity
Parameter
Static latch-up class T
A
= 105 °C
Conditions
A
Level
DS12895 - Rev 2 page 32/43
6
STNRGPF02, STNRGPF12
Thermal data
Thermal data
The STNRGPFx2 functionality cannot be guaranteed when the device, in operation, exceeds the maximum chip junction temperature (TJmax).
Equation 2
T
Jmax
= T
Amax
+ (P
Dmax
x ΘJ
A
)
Where:
T
Amax is the maximum ambient temperature in °C
ΘJ
A
is the package junction to ambient thermal resistance in °C/W
P
Dmax
is the sum of P
INTmax
and P
I/Omax
(P
Dmax
= P
INTmax
+ P
I/Omax
)
P
INTmax
is the product of I
DD and V
DD
, expressed in watts. This is the maximum chip internal power.
P
I/Omax
represents the maximum power dissipation on output pins where:
P
I/Omax
= (V
OL
x I
OL)
+ ∑ [(V
DD
- V
OH
) x I
OH
], taking into account the actual V
OL/IOL
and V
OH/IOH
of the I/Os at the low and high level.
Table 17. Package thermal characteristics
JA
Symbol Package thermal characteristics
TSSOP38 - thermal resistance junction to ambient (1)
80
Value
1. Thermal resistance is based on the JEDEC JESD51-2 with the 4-layer PCB in natural convection
°C/W
Unit
DS12895 - Rev 2 page 33/43
7
7.1
STNRGPF02, STNRGPF12
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
TSSOP38 package information
Figure 32. TSSOP38 package outline
DS12895 - Rev 2
0117861_C
Table 18. TSSOP38 package mechanical data (“TSSOP” stands for “Thin Shrink Small Outline Package”)
Symbol
A
A1
A2 b
Min.
-
0.05
0.80
0.17
Dimensions (mm)
Typ.
-
-
1.00
-
Max
1.20
0.15
1.05
0.27
page 34/43
STNRGPF02, STNRGPF12
TSSOP38 package information
Symbol c
E
e
L
L1 k aaa
Min.
0.09
9.60
6.20
4.30
-
0.45
-
0
-
Dimensions (mm)
Typ.
-
9.70
6.40
4.40
0.50
0.60
1.00
-
-
Max
0.20
9.80
6.60
4.50
-
0.75
-
8
0.10
1. “Dimensions “D” and “E1”do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
DS12895 - Rev 2 page 35/43
8
STNRGPF02, STNRGPF12
STNRGPF02/12 development tools
STNRGPF02/12 development tools
The development tools for the STNRGPFx2 are provided by:
• eDesign Suite This tool uses a graphical user interface to guide customers step-by-step to implementation of a solution in accordance with their specifications. The tool gives users the ability to navigate through an interactive and hierarchical schematic, providing additional information like Bode diagrams for both the current and the voltage loop, power loss calculation, bill of material, and easy shortcuts for datasheets and product folder web pages. The final output of this process is a complete design, with a binary file that contains the optimized firmware for that specific application, which can be uploaded to the STNRGPFx2 device using the UART serial communication port.
• STNRG LOADER This tool permits the user to download the binary code from the eDesign Suite.
DS12895 - Rev 2 page 36/43
STNRGPF02, STNRGPF12
Ordering information
9
Ordering information
Order codes
STNRGPF02
STNRGPF02TR
STNRGPF12
STNRGPF12TR
Package
TSSOP38
Tube
Tape and reel
Tube
Tape and reel
Packaging
DS12895 - Rev 2 page 37/43
STNRGPF02, STNRGPF12
Revision history
Date
04-May-2019
23-Jun-2020
Version
1
2
Table 19. Document revision history
Changes
Initial release.
Added STNRGPF02
DS12895 - Rev 2 page 38/43
STNRGPF02, STNRGPF12
Contents
Contents
DS12895 - Rev 2 page 39/43
STNRGPF02, STNRGPF12
Contents
DS12895 - Rev 2 page 40/43
STNRGPF02, STNRGPF12
List of tables
List of tables
DS12895 - Rev 2 page 41/43
STNRGPF02, STNRGPF12
List of figures
List of figures
DS12895 - Rev 2 page 42/43
STNRGPF02, STNRGPF12
IMPORTANT NOTICE – PLEASE READ CAREFULLY
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Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2020 STMicroelectronics – All rights reserved
DS12895 - Rev 2 page 43/43
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