STMicroelectronics STNRGPF01 Datasheet
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STNRGPF01 Three-channel interleaved CCM PFC digital controller Datasheet - production data Flexible design customization to meet specific customer needs Firmware – Turnkey solution for quick design – eDesign Suite graphical user interface (GUI) for application configuration Embedded memory data retention 15 years with ECC Communication interfaces – UART asynchronous protocol for bootloader support Features Operating temperature: -40 °C to 105 °C Interleaved boost PFC Applications Up to 3 interleaved channels Suitable for welding, industrial motors, UPS, battery chargers, power supplies, air conditioners CCM, fixed frequency Average current control, cycle-by-cycle Inrush current control Table 1. Device summary Burst mode support Overcurrent and thermal protection Order code Packing Soft start-up STNRGPF01 Tube STNRGPF01TR Tape and reel Flexible phase-shedding strategy – High operating frequency with small PFC inductor, suitable for high power-density applications – Low ripple current (input/output) – Simpler integration with other applications April 2017 This is information on a product in full production. DocID030377 Rev 2 1/40 www.st.com Contents STNRGPF01 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 STNRGPF01 control architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 STNRGPF01 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 Voltage and current loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 Measurements section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3 Analog input section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.4 Driving and interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.5 Programming section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.6 Status indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.7 Start-up function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.8 4 5 Inrush current limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.7.2 PFC soft power-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Fan control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1 2/40 3.7.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1.4 Typical current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1.5 Loading capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.6 Pin output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.3.1 VCOUT external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.3.2 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.3.3 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DocID030377 Rev 2 STNRGPF01 5.4 5.5 Contents 5.3.4 Input/output specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3.5 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.3.6 Typical output level curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.3.7 Reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Analog input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.4.1 Measurement section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.4.2 Analog section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.5.1 Electrostatic discharge (ESD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.5.2 Static latch-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.1 TSSOP38 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8 STNRGPF01 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 DocID030377 Rev 2 3/40 40 Description 1 STNRGPF01 Description The STNRGPF01 is a digital controller designed specifically for interleaved PFC boost topologies and intended for use in high power applications. The controller is capable of driving up to 3 interleaved channels, generating the proper signals in each condition. Moreover, it implements a flexible phase shedding strategy that enables the correct number of PFC channels based on the actual load condition. With this function, the STNRGPF01 is always able to guarantee the highest power efficiency across a wide range of load current requirements. The device works in CCM at fixed frequency with average current mode control, and implements mixed signal (analog/digital) control. The inner current loop is performed by hardware, ensuring cycle-by-cycle regulation. The outer voltage loop is performed by a digital PI controller with fast dynamic response. The controller implements several functions: inrush current control, soft start-up, burst mode cooling management and status indicators. It also features a full set of embedded protections against overvoltage, overcurrent, and thermal faults. The STNRGPF01 is configured through a visual dedicated software tool (eDesignSuite) to match a wide range of specific applications. Using eDesignSuite, the user can customize the PFC conversion configuration and all the relevant electrical components. As a result, the tool will automatically generate a full schematic which includes a complete list of material and the final binary object code (FW) to be downloaded to the STNRGPF01. 4/40 DocID030377 Rev 2 STNRGPF01 2 STNRGPF01 control architecture STNRGPF01 control architecture The STNRGPF01 implements mixed signal (analog/digital) control. The inner current loop is performed by hardware and the outer voltage loop is performed by a digital PI controller. The device performs cascaded control for voltage and current loops to regulate the output voltage by acting on the total average inductor current. Figure 1. STNRGPF01 control scheme Figure 1 shows the STNRGPF01 control scheme. As can be observed, the difference between the output voltage feedback Vout_fb and reference Vout_ref is sent to a digital PI controller, which calculates the peak of the input average total current ipk_ref. (internal digital section, green line). The PFC current reference is internally generated and is output from the I/O FFD block as the PWM signal. After filtering it becomes the total average sinusoidal input current reference itot_ref for the inner current loop (external analog section, red line). The difference between the current reference itot_ref and the input current feedback itot_fb is sent to the analog PI controller. DocID030377 Rev 2 5/40 40 STNRGPF01 control architecture STNRGPF01 Thus the master PWM signal is generated by comparing the analog PI output Vctrl and a triangular wave Vtriang at switching frequency. Finally, an interleaving operation is performed and three 120° phase-shifted PWM signals (180° for two channels only) drive the three power switches. Moreover, the digital section includes the input voltage and load feed-forward for fast transient response when the main voltage changes suddenly or a load step current occurs, preventing large over or undervoltage on the output capacitor Cout. 6/40 DocID030377 Rev 2 STNRGPF01 3 STNRGPF01 block diagram STNRGPF01 block diagram The block diagram of the STNRGPF01 device is shown in Figure 2. Figure 2. STNRGPF01 block diagram DocID030377 Rev 2 7/40 40 STNRGPF01 block diagram 3.1 STNRGPF01 Voltage and current loop The STNRGPF01 implements mixed signal average current control. The task of the digital voltage loop is to regulate the output voltage of the PFC. The VIN and IOUT measurements are used to implement the input/output feed-forward (I/O FFD), so load steps or input voltage variations are quickly compensated for by acting on digital PI output calculations. This function allows keeping the output voltage at the set point value and as constant as possible (see Figure 3). Figure 3. Voltage loop and current reference The output of the digital PI controller is the peak current reference. In order to obtain a sinusoidal current reference, the Ipk_ref is multiplied by a lookup table (LUT). The LUT is synchronized with the input voltage thanks to the ZVD signal (pin 17). The output of the multiplier is a PWM signal with a sinusoidal duty cycle that is configured on pin 19 SIN REF. An analog filter is used to obtain the final sinusoidal current reference for the external current loop (itot_ref). The analog PI current compares the reference itot_ref with the total input current feedback (itot_fb) and generates the duty cycle wave for the PWM modulation. The master PWM signal is obtained by comparing (COMP2,3) the output of the PI current with a triangular wave at switching frequency (see Figure 6: Analog comparators section and Section 3.4: Driving and interleaving). 8/40 DocID030377 Rev 2 STNRGPF01 3.2 STNRGPF01 block diagram Measurements section The STNRGPF01 includes 4 input measurement channels. These inputs are defined from pin 31 to pin 34 and they are specified below. Pin 31. VIN: RMS input voltage Pin 32. Temp: ambient temperature Pin 33. IOUT: PFC output current Pin 34: VOUT: PFC output voltage Pin 31, VIN This is the input of the RMS line voltage and also implements the voltage input feed-forward. The input voltage feed-forward modifies the PI output, compensating rapidly the effect of the line voltage changes. See Figure 5. Pin 32, Temp This is the input for the board temperature measurement. An external ST temperature sensor, STLM20, measures the board temperature. The PWM activity will be stopped when the temperature exceeds the user-defined threshold. See Figure 4. Figure 4. Temperature measurement DocID030377 Rev 2 9/40 40 STNRGPF01 block diagram STNRGPF01 Pin 33, IOUT Output current sensing. The measurement of this pin voltage allows implementation of the following functions: Load feed-forward. The input current reference is modified proportionally to the load, in order to provide a faster response versus the load transient. Channel power management. Each channel can be enabled or disabled based on the output current level. For example, up to 30% of the load, only one channel may be enabled, from 30% to 60% of the load, two configuration channels can be selected and at full load all channels may be activated. Pin 34, VOUT Output voltage sensing. This feedback input is connected via a voltage divider to the boost output voltage. This measurement allows implementation of the following functions: Output voltage regulation Overvoltage protection In Figure 5 the block scheme of the VIN, IOUT and VOUT is shown. Figure 5. VIN, IOUT and VOUT measurement 10/40 DocID030377 Rev 2 STNRGPF01 3.3 STNRGPF01 block diagram Analog input section The STNRGPF01 device includes four fast analog comparators, from COMP0 to COMP3. COMP3 and COMP2 have external reference voltages and are used to define the duty cycle of the PWM[0] master. COMP1 and COMP0 have internal reference voltage and are used to implement the overcurrent protection features. Figure 6. Analog comparators section The positive inputs of COMP3 and COMP2 are on pin 24 and pin 25. Moreover, these comparators use a common external triangular reference voltage connected to pin 26. The positive inputs of COMP1 and COMP0 are configured on pin 27 and pin 28. DocID030377 Rev 2 11/40 40 STNRGPF01 block diagram STNRGPF01 A description of the comparator pins is given below: 3.4 Pin 24 OUT_PI[3]: positive input of the COMP3. It receives the output of the analog PI current. Pin 25 OUT_PI[2]: positive input of the COMP2. It receives the output of the analog PI current. Pin 26 OSC: negative common input analog COMP2, 3. It receives the reference triangular waveform. Pin 27: positive input of the COMP1. It receives the sensing signal of the total input current. Pin 28: positive input of the COMP0. It receives the sensing signal of all switch currents. COMP0 stops driving when an overcurrent occurs in any switch. Driving and interleaving The STNRGPF01 PWMs for channel driving are pins: 1, 4, 5, 8 and 16. Figure 7 shows the configuration for PWM generation. Figure 7. VIN, IOUT and VOUT measurement 12/40 DocID030377 Rev 2 STNRGPF01 STNRGPF01 block diagram The output level of COMP3 and COMP2 are used to generate the master PWM[0]. The SYNCR[1] and SYNCR[2] inputs are triggered respectively on the rising and falling edge of the PWM[0]. These trigger signals are sent to interleaving blocks which generate the phase shifted (120º/180º and 240º) ON/OFF signals for the other channels. The SET[1], SET[2], RESET[1] and RESET[2] (pins: 4, 5, 8, 16) signals must be connected to external devices (for example two flip-flops) in order to obtain the driving signals PWM1 and PWM2. The ENABLE input (pin 18) performs a protection function. The connection to the CLOCK signal (pin 2 at switching frequency) prevents undesired commutation of the PWM[0] and consequently on the other channels. 3.5 Programming section Device programming is done by using a PC with dedicated loader software (STNRG LOADER), an FTDI cable and an adapter board (see Figure 8). Figure 8. Programming section DocID030377 Rev 2 13/40 40 STNRGPF01 block diagram 3.6 STNRGPF01 Status indicator The STNRGPF01 device includes two pins to identify the running or fault status. These functions are defined on pin 14 and pin 15 (see Figure 9). Figure 9. Status indicator 6715*3) 3)&B)$8/7 ',*,7$/&21752//(5 3)&B2. 3527(&7,21 14/40 67$57 83 )81&7,21 DocID030377 Rev 2 STNRGPF01 3.7 STNRGPF01 block diagram Start-up function The start-up function is divided into two logical parts. The first is the inrush current limiter and the second part a PFC soft power-on. In Figure 10 the timing of this function is shown. Figure 10. Start-up function 3.7.1 Inrush current limiter The device includes the possibility to perform the inrush current limiter function. Pin 21 gives a CMOS/TTL signal that becomes high after a settable time. 3.7.2 PFC soft power-on After the inrush current limiter phase the PFC switching activity on the master channel starts using the integrated function named soft power-on. Thanks to a controlled loop regulation the PFC output voltage will increase up to the set point (Vout_ref). The soft power-on function will be activated only in the conditions indicated below: No load condition. In this case the master channel enters into burst mode regulation. The PFC output voltage will oscillate between two settable levels (Vburst_min and Vburst_max). See Figure 11. These levels can be defined during device customization. Light load condition (below 5%). The PFC operates as in the no load condition. Load condition (down to 10%). In this case the PFC enters in the run mode and the output voltage will be regulated to the nominal value Vout_ref. See Figure 11. When the PFC output voltage is controlled (burst mode or run mode - see conditions 1, 2, and 3) the soft power-on function will be completed and the PFC_OK pin will be activated. At the end of this phase the PFC is ready to work at the full load. DocID030377 Rev 2 15/40 40 STNRGPF01 block diagram STNRGPF01 Figure 11. Running mode or burst mode 16/40 DocID030377 Rev 2 STNRGPF01 3.8 STNRGPF01 block diagram Fan control The device offers the possibility to implement a fan control function. The customer defines the power level for activation of this function. Pin 20 provides a CMOS/TTL signal that becomes high for a power level higher than the specified threshold. See Figure 12. Figure 12. Fan control function DocID030377 Rev 2 17/40 40 Pinout and pin description STNRGPF01 4 Pinout and pin description 4.1 Pinout Figure 13. STNRGPF01 - TSSOP38 pinout 18/40 DocID030377 Rev 2 STNRGPF01 4.2 Pinout and pin description Pin description Table 2. Pin description No. Type(1) 1 OP Name Pin description PWM[0] This pin generates the PWM[0] for the master channel CH0. 2 O CLOCK This pin generates a PWM signal at selected working frequency with a duty cycle of 50%. This signal is used to generate triangular waveforms at switching frequency by means of an external op-amp. The CLOCK signal is also used to implement protection against undesired commutations. 3 I SYNCR[1] This pin receives the PWM[0] signal in order to synchronize the other channels. The rising edge of the PWM[0] signal is used to trigger ON the slave channels CH1 and CH2. SET[1] This pin generates a pulse in order to set to ON the CH1 channel with the right outof-phase. This out-of-phase will be 120° electrical degrees when three channels are activated and 180° when only two channels work. This pin is connected to a SET pin of an external flip-flop in order to start the conduction of the CH1. 4 OP 5 OP RESET[1] This pin generates a pulse in order to set OFF the CH1 channel with the right out-ofphase. This out-of-phase will be 120° electrical degrees when three channels are activated and 180° when only two channels work. This pin is connected to a RESET pin of an external flip-flop in order to stop the conduction of the CH1. 6 I SYNCR[2] This pin receives the PWM[0] signal in order to synchronize the other channels. The falling edge of the PWM[0] signal is used to trigger OFF the slave channels CH1 and CH2. 7 NC NC[1] 8 OP RESET[2] 9 NC NC[2] Reserved 10 I/O NRST Reset 11 PS VDD Supply voltage 12 PS VSS Ground 13 PS VCOUT 14 O 15 O PFC_OK When the PFC has completed the start-up procedure, this pin is forced low. During the start-up phase or when in fault condition, this pin is high. 16 OP SET[2] This pin generates a pulse in order to set ON the CH2 channel with out-of-phase of 240°. This pin is connected to a SET pin of an external flip-flop in order to start the conduction of the CH2. 17 I ZVD This pin receives a square wave signal synchronized with input AC voltage. The rising edge of the square wave signal is used by the STNRGPF01 to detect the ZVD instant. 18 I ENABLE Reserved This pin generates a pulse in order to set OFF the CH2 channel with out-of-phase of 240°. This pin is connected to a RESET pin of an external flip-flop in order to stop the conduction of the CH2. Supply voltage of the digital section. An external capacitor must be connected to the VCOUT pin. PFC_FAULT During normal operation this pin is high. If a fault condition occurs it is forced low. This pin receives the CLOCK signal in order to avoid undesired commutation. DocID030377 Rev 2 19/40 40 Pinout and pin description STNRGPF01 Table 2. Pin description (continued) No. Type(1) Name Pin description This pin generates a PWM signal with the sinusoidal duty cycle. This PWM signal must be filtered in order to have the current sinusoidal reference that is synchronized with input voltage mains. 19 OP SIN_REF 20 O FAN 21 O RELAY 22 O PTX Programming data transmit 23 I PRX Programming data receive 24 AI OUT_PI[3] Positive input of the internal analog comparator 3. It receives the out of the analog PI current. 25 AI OUT_PI[2] Positive input of the internal analog comparator 3. It receives the out of the analog PI current. 26 AI TRIANG REF Negative input analog comparators 3 and 2. It receives the voltage triangular waveform. 27 AI OCP[0] Input overcurrent protection 28 AI OCP[1] Inductor overcurrent protection 29 PS VDDA Analog supply voltage 30 PS VSSA Analog ground 31 MI VIN 32 MI TEMP This pin measures the ambient board temperature. This measurement is performed using the STLM20 device, which gives an output voltage proportional to temperature. 33 MI IOUT This pin measures the PFC output current. 34 MI VOUT This pin measures the PFC output voltage. 35 RI RI[1] Reserved. This pin must be pulled down by means a 10 k resistor. 36 RI RI[2] Reserved. This pin must be pulled down by means a 10 k resistor. 37 RI RI[3] Reserved. This pin must be pulled down by means a 10 k resistor. 38 RI RI[4] Reserved. This pin must be pulled down by means a 10 k resistor. It generates a CMOS/TTL signal that is low until the PFC output power is below a threshold defined during device customization. It generates a CMOS/TTL signal. This signal becomes high after a settable time defined during device customization. It is useful to perform the inrush current limiter function. This pin measures the RMS input voltage. 1. In Table 3 a legend describing pin type is provided. 20/40 DocID030377 Rev 2 STNRGPF01 Pinout and pin description Table 3. Pin identification legend Type Pin identification OP PWM driver O Digital output I Digital input I/O Digital bidirectional PS Power supply AI Analog input MI Measure input DocID030377 Rev 2 21/40 40 Electrical characteristics STNRGPF01 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referred to VSS. VDDA and VDD must be connected to the same voltage value. VSS and VSSA must be connected together with the shortest wire loop. 5.1.1 Minimum and maximum values Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with the ambient temperature at TA = 25 °C and TA = TA max. (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated according to each table specific notes and are not tested in production. 5.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 °C, VDD and VDDA = 3.3 V. They are given only as design guidelines and are not tested. For the measurement section the accuracy is determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range. 5.1.3 Typical curves Unless otherwise specified, all typical curves are given as design guidelines only and are not tested. 5.1.4 Typical current consumption For typical current consumption measurements, VDD and VDDA are connected as shown in Figure 14. Figure 14. Supply current measurement conditions 22/40 DocID030377 Rev 2 STNRGPF01 5.1.5 Electrical characteristics Loading capacitors The loading conditions used for pin parameter measurement are shown in Figure 15. Figure 15. Pin loading conditions 5.1.6 Pin output voltage The input voltage measurement on a pin is described in Figure 16. Figure 16. Pin input voltage DocID030377 Rev 2 23/40 40 Electrical characteristics 5.2 STNRGPF01 Absolute maximum ratings Stresses above those listed as 'absolute maximum ratings' may cause permanent damage to the device. This is a stress rating only and the functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect the device reliability. Table 4. Voltage characteristics Symbol Ratings Min. Max. -0.3 6.5 VSS - 0.3 VDD + 0.3 - 50 - 50 VDDX - VSSX Supply voltage(1) VIN VDD - VDDA VSS - VSSA VESD Input voltage on any other pin (2) Variation between different power pins Variation between all the different ground pins(3) Electrostatic discharge voltage Unit V mV Refer to Table 15 on page 33. 1. All power VDDX (VDD, VDDA) and ground VSSX (VSS, VSSA) pins must always be connected to the external power supply. 2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. 3. VSS and VSSA signals must be interconnected together with a short wire loop. Table 5. Current characteristics Symbol IVDDX IVSSX IIO IINJ(PIN)(3), (4) IINJ(TOT)(3), (4), (5) Max.(1) Ratings Total current into VDDX power lines(2) Total current out of VSSX power lines(2) Output current sunk by any I/Os and control pin Output current source by any I/Os and control pin Unit 100 100 Ref. to Table 12 on page 28 Injected current on any pin ±4 Sum of injected currents ± 20 mA 1. Data based on characterization results, not tested in production. 2. All power VDDX (VDD, VDDA) and ground VSSX (VSS, VSSA) pins must always be connected to the external power supply. 3. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. 4. Negative injection disturbs the analog performance of the device. 5. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterization with the IINJ(PIN) maximum current injection on four I/O port pins of the device. Table 6. Thermal characteristics Symbol TSTG TJ 24/40 Ratings Storage temperature range Maximum junction temperature DocID030377 Rev 2 Max. -65 to 150 150 Unit ºC STNRGPF01 5.3 Electrical characteristics Operating conditions The device must be used in operating conditions that respect the parameters listed in Table 7. In addition, a full account must be taken for all physical capacitor characteristics and tolerances. Table 7. General operating conditions Symbol Parameter Conditions Min. Typ. Max. - 3 - 5.5 Nominal operating voltages - - 5 - Core digital power supply - - 1.8(1) - 470 - 3300 nF 0.05 - 0.2 - - 15 nH VDD1, VDDA1 Operating voltages VDD, VDDA VCOUT CVCOUT: capacitance of external capacitor(2) ESR of external capacitor(1) ESL of external at 1 MHz capacitor(1) Unit V JA(3) FR4 multilayer PCB TSSOP38 - 80 - °C/W TA Ambient temperature Pd = 100 mW -40 - 105 °C 1. Internal core power supply voltage. 2. Care should be taken when the capacitor is selected due to its tolerance, its dependency on temperature, DC bias and frequency. 3. To calculate PDmax (TA), use the formula PDmax = (TJmax - TA)/JA. Table 8. Operating conditions at power-up/power-down Symbol tVDD tTEMP Parameter Conditions Min.(1) Typ. Max.(1) Unit VDD rise time rate - 2 µs/V - 1 s/V(2) VDD fall time rate - 2 µs/V - 1 s/V(2) VDD rising - 3 - ms V Reset release delay VIT+ Power-on reset threshold - 2.65 2.8 2.98 VIT- Brownout reset threshold - 2.58 2.73 2.88 VHYS(BOR) Brownout reset hysteresis - - 70 - mV 1. Guaranteed by design, not tested in production. 2. The power supply ramp must be monotone. DocID030377 Rev 2 25/40 40 Electrical characteristics 5.3.1 STNRGPF01 VCOUT external capacitor The stabilization of the main regulator is achieved by connecting an external capacitor CVCOUT(a) to the VCOUT pin. CVCOUT is specified in Table 7: General operating conditions. Care should be taken to limit the series inductance to less than 15 nH. Figure 17. External capacitor CVCOUT 5.3.2 Supply current characteristics The STNRGPF01 current consumption is declared based on, for example, an application where the application firmware is loaded and running. Table 9. Supply current characteristics Symbol Parameter Test condition Min. Typ.(1) Max.(1) Unit - 28 34 mA VDD/VDDA SECTION: current consumption IDD(RUN) Total current consumption VDD/VDDA = 5 V 1. Test conditions: Data based on characterization results not tested in production. Temperature operating: TA = 25 °C. Device in the run mode. a. ESR is the equivalent series resistance and ESL is the equivalent inductance. 26/40 DocID030377 Rev 2 STNRGPF01 5.3.3 Electrical characteristics Memory characteristics Flash program and memory/data E2PROM. General conditions: TA = -40 °C to 105 °C. Table 10. Flash program memory/data E2PROM Parameter Conditions Min.(1) Standard programming time (including erase) for byte/word/block (1 byte/4 bytes/128 bytes) - - 6 6.6 Fast programming time for 1 block (128 bytes) - - 3 3.3 Erase time for 1 block (128 bytes) - - 3 3.3 TA = 25 °C 10 K - - TA = 85 °C 100 K - - TA = 105 °C 35 K - - Data retention (program memory) after 10 K erase/write cycles at TA = 25 °C TRET = 85 °C 15 - - Data retention (program memory) after 10 K erase/write cycles at TA = 25 °C TRET = 105 °C 11 - - Data retention (data memory) after 100 K erase/write cycles at TA = 85 °C TRET = 85 °C 15 - - Data retention (data memory) after 35 K erase/write cycles at TA = 105 °C TRET = 105 °C 6 - - Supply current during program and erase cycles -40 ºC TA 105 ºC - 2 - Symbol tPROG tERASE Erase/write NWE tRET IDDPRG cycles(2) (program memory) Erase/write cycles(2)(data memory) Typ.(1) Max.(1) Unit ms Cycles Years mA 1. Data based on characterization results, not tested in production. 2. The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation addresses a single byte. 5.3.4 Input/output specifications The STNRGPF01 device includes three different I/O types: Normal I/Os (O or I) Fast I/O (OP) High speed I/O (CLOCK) The STNRGPF01 I/Os are designed to withstand the current injection. For the negative injection current of 4 mA, the resulting leakage current in the adjacent input does not exceed 1 µA. DocID030377 Rev 2 27/40 40 Electrical characteristics 5.3.5 STNRGPF01 I/O port pin characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. Unused input pins should not be left floating. Table 11. Voltage DC characteristics Symbol VIL VIH VOL1 Typ. Max.(1) -0.3 - 0.3 x VDD 0.7 x VDD - VDD - - 0.5 - - 0.6 VDD - 0.5 - - VDD - 0.6 - - 0.1 x VDD - - 30 45 60 Input low voltage Input high voltage (2) (3) (4) Output low voltage at 5 V , (2) (5) VOL3 Output low voltage high sink at 5 V , VOH1 Output high voltage at 5 V(3), (4) VOH3 Min.(1) Description Output high voltage high sink at 5 HVS Hysteresis input RPU Pull-up resistor V(2), (5) voltage(6) Unit V k 1. Data based on characterization result, not tested in production. 2. Input signals can't be exceeded VDDX (VDDX = VDD, VDDA). 3. The parameter applicable to signals on pins 14, 15, 20, 21, 22 and 23. 4. The parameter applicable to signals on pins 1, 4, 5, 8 16 and 19. 5. The parameter applicable to the signal on pin 2. 6. Applicable to pins 3, 6, 7, 17 and 18. Table 12. Current DC characteristics Symbol IOL1 IOLhs1 Description Max.(1) Unit Min. Typ. Standard output low level current at 5 V and VOL1(2), (3) - - 3 VOL3(2), (4) - - 7.75 High sink output low level current at 5 V and IOH1 Standard output high level current at 5 V and VOH1(2), (3) - - 3 IOHhs1 High sink output high level current at 5 V and VOH3(2), (4) - - 7.75 - - ±1 ILKg Input leakage current digital - analog VSS ≤ VIN ≤ VDD (5) (6) (7) I_Inj Injection current , - - ±4 I_Inj Total injection current sum of all I/O and control pins)(6) - - ± 20 1. Data based on characterization result, not tested in production. 2. The parameter applicable to signals on pins 14, 15, 20, 21, 22 and 23. 3. The parameter applicable to signals on pins1, 4, 5, 8 16 and 19. 4. The parameter applicable to the signal on pin 2. 5. Applicable to pins 3, 6, 7, 17 and 18. 6. Maximum value must never be exceeded. 7. Negative injection current on pins 31, 32, 33 and 34 must be avoided. It has impact on the measurement section. 28/40 DocID030377 Rev 2 mA µA mA STNRGPF01 5.3.6 Electrical characteristics Typical output level curves This section shows the typical output voltage level curves measured on a single output pin for the three-pad family present in the STNRG device. Normal I/Os These pads are associated with the O type pins. Figure 18. VOH normal pin Figure 19. VOL normal pin DocID030377 Rev 2 29/40 40 Electrical characteristics STNRGPF01 Fast I/Os These pads are associated with the OP type pins. Figure 20. VOH fast I/Os pins Figure 21. VOL fast I/Os pins 30/40 DocID030377 Rev 2 STNRGPF01 Electrical characteristics Output CLOCK This pad is associated with the OUTPUT CLOCK pin. Figure 22. VOH CLOCK pin Figure 23. VOL CLOCK pin DocID030377 Rev 2 31/40 40 Electrical characteristics 5.3.7 STNRGPF01 Reset pin characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. Table 13. NRST pin characteristics Symbol VIL(NRST) VIH(NRST) Parameter Typ. Max.(1) - -0.3 - 0.3 x VDD (1) - 0.7 x VDD - VDD + 0.3 (1) IOL = 2 mA - - 0.5 - 30 40 60 - - - 75 - 500 - - - 15 - - NRST input high level voltage RPU(NRST) NRST pull-up resistor (2) NRST input filtered pulse(3) tINFP(NRST) NRST not input filtered tOP(NRST) Min.(1) NRST input low level voltage(1) VOL(NRST) NRST output low level voltage tIFP(NRST) Conditions pulse(3) NRST output filtered pulse(3) Unit V k ns µs 1. Data based on characterization results, not tested in production 2. The RPU pull-up equivalent resistor is based on a resistive transistor. 3. Data guaranteed by design, not tested in production. 5.4 Analog input characteristics 5.4.1 Measurement section Subject to general operating conditions for VDDA and TA unless otherwise specified. It applies to the [MI] class. Table 14. Measurement pin characteristics Symbol Parameter Conditions Min. Typ. Max. Unit M RIN Input impedance - 1 - - VIN Measurement range - 0 - 1.25(1) Vref Measure reference voltage(2) - - 1.25 - 1. Maximum input analog voltage cannot exceed VDDA. 2. Reference voltage at TA = 25 °C. 32/40 DocID030377 Rev 2 V STNRGPF01 5.4.2 Electrical characteristics Analog section In Table 15 analog comparator characteristics are reported. It applies to the [AI] class. Table 15. Analog comparator characteristics Symbol Parameter Conditions Min.(1) Typ. Max(1) Unit VCPP01 Comparator CP0,1 positive input voltage range -40 ºC TA 105 ºC 0 - 1.23(2) V VCPP23 Comparator CP2,3 positive input voltage range -40 ºC TA 105 ºC 0 - 2(3) V VCPM23 Comparator CP2,3 negative external input voltage range -40 ºC TA 105 ºC 0 - 2(3) V Input capacitance - - 3 - pF Voffset Comparator offset error - - - 15 mV tCOMP Comparison delay time - - - 50(4) ns CIN 1. Data based on characterization results, not tested in production. 2. Maximum analog input voltage for comparators CP0 and CP1. 3. Maximum analog input voltage for comparators CP2 and CP3. 4. The overdrive voltage is ± 50 mV. 5.5 EMC characteristics 5.5.1 Electrostatic discharge (ESD) Electrostatic discharges (3 positive then 3 negative pulses separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device [3 parts * (n + 1) supply pin]. Table 16. ESD absolute maximum ratings(1) Symbol Ratings Conditions Maximum value VESD(HBM) Electrostatic discharge voltage TA = 25 °C, conforming to (human body model) JEDEC/JESD22-A114E 2000 VESD(CDM) Electrostatic discharge voltage TA = 25 °C, conforming to (charge device model) ANSI/ESD STM 5.3.1 ESDA 500 VESD(MM) Electrostatic discharge voltage TA = 25 °C, conforming to (machine model) JEDEC/JESD-A115-A 200 Unit V 1. Data based on characterization results, not tested in production. DocID030377 Rev 2 33/40 40 Electrical characteristics 5.5.2 STNRGPF01 Static latch-up Two complementary static tests are required on 10 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD78 IC latch-up standard. Table 17. Electrical sensitivity Symbol LU 34/40 Parameter Conditions Level Static latch-up class TA = 105 °C A DocID030377 Rev 2 STNRGPF01 6 Thermal data Thermal data The STNRG functionality cannot be guaranteed when the device, in operation, exceeds the maximum chip junction temperature (TJmax). Equation 1 TJmax = TAmax + (PDmax x JA) Where: TAmax is the maximum ambient temperature in °C JA is the package junction to ambient thermal resistance in °C/W PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax) PINTmax is the product of IDD and VDD, expressed in watts. This is the maximum chip internal power. PI/Omax represents the maximum power dissipation on output pins where: PI/Omax = (VOL x IOL) + [(VDD - VOH) x IOH], taking into account the actual VOL/IOL and VOH/IOH of the I/Os at the low and high level. Table 18. Package thermal characteristics Symbol JA Parameter TSSOP38 - thermal resistance junction to ambient(1) Value Unit 80 °C/W 1. Thermal resistance is based on the JEDEC JESD51-2 with the 4-layer PCB in natural convection. DocID030377 Rev 2 35/40 40 Package information 7 STNRGPF01 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 7.1 TSSOP38 package information Figure 24. TSSOP38 package outline @$ 36/40 DocID030377 Rev 2 STNRGPF01 Package information Table 19. TSSOP38 package mechanical data(1) Dimensions (mm) Symbol Min. Typ. Max. A - - 1.20 A1 0.05 - 0.15 A2 0.80 1.00 1.05 b 0.17 - 0.27 c 0.09 - 0.20 (2) 9.60 9.70 9.80 E 6.20 6.40 6.60 E1(2) 4.30 4.40 4.50 e - 0.50 - L 0.45 0.60 0.75 L1 - 1.00 - k 0 - 8 aaa - - 0.10 D 1. “TSSOP” stands for “Thin Shrink Small Outline Package”. 2. “Dimensions “D” and “E1”do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. DocID030377 Rev 2 37/40 40 STNRGPF01 development tools 8 STNRGPF01 STNRGPF01 development tools The development tools for the STNRGPF01 are provided by: 38/40 eDesign Suite This tool uses a graphical user interface to guide customers step-by-step to implementation of a solution in accordance with their specifications. The tool gives users the ability to navigate through an interactive and hierarchical schematic, providing additional information like Bode diagrams for both the current and the voltage loop, power loss calculation, bill of material, and easy shortcuts for datasheets and product folder web pages. The final output of this process is a complete design, with a binary file that contains the optimized firmware for that specific application, which can be uploaded to the STNRGPF01 device using the UART serial communication port. STNRG LOADER This tool permits the user to download the binary code from the eDesign Suite. DocID030377 Rev 2 STNRGPF01 9 Ordering information Ordering information Table 20. Ordering information Order codes Package STNRGPF01 Tube TSSOP38 STNRGPF01TR 10 Packaging Tape and reel Revision history Table 21. Document revision history Date Revision 23-Feb-2017 1 Initial release. 2 Replaced “PWM0” by “PWM[0]”, “SET1” by “SET[1]”, “SET2” by “SET[2]”, “RESET1” by “RESET[1]”, “RESET2” by “RESET[2]”, “OCP” by “OCP[0]”, “OCP1” by “OCP[1]” and “CVOUT” by “CVCOUT” in the whole document. Updated Figure 13 on page 18 (replaced by new figure). Added “NC[1]”, “NC[2]”, “RI[1]”, “RI[2]”, “RI[3]”, “RI[4]” in Table 2 on page 19. Replaced “VOUT” by “VCOUT” in Table 2 on page 19, Table 7 on page 25 and Section 5.3.1 on page 26. Minor modifications throughout document. 14-Apr-2017 Changes DocID030377 Rev 2 39/40 40 STNRGPF01 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2017 STMicroelectronics – All rights reserved 40/40 DocID030377 Rev 2 ">
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