STMicroelectronics STM32G0B1VB Datasheet

) using the same architecture, so the advanced-control timers can work

N/A

• Write protection (WRP): the protected area is protected against erasing and programming. Two areas per bank can be selected, with 2-Kbyte granularity.

• Proprietary code readout protection (PCROP): a part of the Flash memory can be protected against read and write from third parties. The protected area is execute-only: it can only be reached by the STM32 CPU as instruction code, while all other accesses

(DMA, debug and CPU data read, write and erase) are strictly prohibited. An additional option bit (PCROP_RDP) determines whether the PCROP area is erased or not when the RDP protection is changed from Level 1 to Level 0.

The whole non-volatile memory embeds the error correction code (ECC) feature supporting:

• single error detection and correction

• double error detection

• readout of the ECC fail address from the ECC register

A part of the Flash memory can be hidden from the application once the code it contains is executed. As soon as the write-once SEC_PROT bit is set, the securable memory cannot be accessed until the system resets. The securable area generally contains the secure boot code to execute only once at boot. This helps to isolate secret code from untrusted application code.

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Functional overview STM32G0B1xB/xC/xE

STM32G0B1xB/xC/xE devices have 128 Kbytes of embedded SRAM with parity. Hardware parity check allows memory data errors to be detected, which contributes to increasing functional safety of applications.

When the parity protection is not required because the application is not safety-critical, the parity memory bits can be used as additional SRAM, to increase its total size to 144 Kbytes.

The memory can be read/write-accessed at CPU clock speed, with 0 wait states.

At startup, the boot pin and boot selector option bit are used to select one of the three boot options:

• boot from User Flash memory

• boot from System memory

• boot from embedded SRAM

The boot pin is shared with a standard GPIO and can be enabled through the boot selector option bit. The boot loader is located in System memory. It manages the Flash memory reprogramming through one of the following interfaces:

• USART on pins PA9/PA10, PC10/PC11, or PA2/PA3

• I

C-bus on pins PB6/PB7 or PB10/PB11

• SPI on pins PA4/PA5/PA6/PA7 or PB12/PB13/PB14/PB15

• USB on pins PA11/PA12

• FDCAN on pins PD0/PD1

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at link time and stored at a given memory location.

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3.7.1 Power supply schemes

The STM32G0B1xB/xC/xE devices require a 1.7 V to 3.6 V operating supply voltage (V

Several different power supplies are provided to specific peripherals:

• V

= 1.7 (1.6) to 3.6 V

DD is the external power supply for the internal regulator and the system analog such as reset, power management and internal clocks. It is provided externally through

VDD/VDDA pin.

The minimum voltage of 1.7 V corresponds to power-on reset release threshold

POR

(max). Once this threshold is crossed and power-on reset is released, the functionality is guaranteed down to power-down reset threshold V

PDR

(min).

• V

DDA

= 1.62 V (ADC and COMP) / 1.8 V (DAC) / 2.4 V (VREFBUF) to 3.6 V

DDA is the analog power supply for the A/D converter, D/A converter, voltage reference buffer and comparators. V

DDA voltage level is identical to V provided externally through VDD/VDDA pin.

voltage as it is

• V

DDIO1

= V

DDIO1

is the power supply for the I/Os. V

DDIO1

voltage level is identical to V

DD as it is provided externally through VDD/VDDA pin.

voltage

• V

DDIO2

= 1.6 to 3.6 V

DDIO2

is the power supply from VDDIO2 pin for selected I/Os and V

DDUSB

. On packages without VDDIO2 pin, V

DDUSB

Although V

DDIO2

is independent of V

and V

DDIO2

or V

DDA

are internally connected with V

, it must not be applied without valid

• V

BAT

= 1.55 V to 3.6 V. V

BAT

is the power supply (through a power switch) for RTC,

TAMP, low-speed external 32.768 kHz oscillator and backup registers when V

DD present. V

BAT on the package, VBAT bonding pad is internally bonded to the VDD/VDDA pin.

is not

is provided externally through VBAT pin. When this pin is not available

• V

REF+

is the analog peripheral input reference voltage, or the output of the internal voltage reference buffer (when enabled). When V

DDA

. When V

DDA

≥ 2 V, V

REF+

must be between 2 V and V when the analog peripherals using V

REF+

< 2 V, V are not active.

REF+

DDA

must be equal to

. It can be grounded

The internal voltage reference buffer supports two output voltages, which is configured with VRS bit of the VREFBUF_CSR register:

– V

REF+

around 2.048 V (requiring V

DDA

equal to or higher than 2.4 V)

– V

REF+

around 2.5 V (requiring V

DDA

equal to or higher than 2.8 V)

REF+

is delivered through VREF+ pin. On packages without VREF+ pin, V internally connected with V

DD disabled (refer to datasheets for package pinout description).

REF+ is

, and the internal voltage reference buffer must be kept

• V

CORE

An embedded linear voltage regulator is used to supply the V

CORE power. V

CORE

The Flash memory is also supplied with V

internal digital is the power supply for digital peripherals, SRAM and Flash memory.

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Functional overview

3.7.2

STM32G0B1xB/xC/xE

VREF+

Figure 2. Power supply overview

REF+

DDA

SSA

DDA

domain

A/D converter

Comparators

D/A converter

Voltage reference buffer

VDDIO2

VSS/VSSA

VDD/VDDA

DDIO1

DDIO2

I/O ring

USB

domain

DDIO1

domain

DDIO2

domain

Reset block

Temp. sensor

PLL, HSI

Standby circuitry

(Wakeup, IWDG)

Voltage regulator

CORE

domain

Core

SRAM

Digital peripherals

VBAT

Low-voltage detector

Flash memory

RTC domain

BKP registers

LSE crystal 32.768 kHz osc

RCC BDCR register

RTC and TAMP

MSv63104V2

Power supply supervisor

The device has an integrated power-on/power-down (POR/PDR) reset active in all power modes except Shutdown and ensuring proper operation upon power-on and power-down. It maintains the device in reset when the supply voltage is below V

POR/PDR

threshold, without the need for an external reset circuit. Brownout reset (BOR) function allows extra flexibility. It can be enabled and configured through option bytes, by selecting one of four thresholds for rising V

and other four for falling V

The device also features an embedded programmable voltage detector (PVD) that monitors the V

DD when V

power supply and compares it to V

PVD

level crosses the V

PVD

threshold. It allows generating an interrupt

threshold, selectively while falling, while rising, or while falling and rising. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

Two embedded linear voltage regulators, main regulator (MR) and low-power regulator

(LPR), supply most of digital circuitry in the device.

The MR is used in Run and Sleep modes. The LPR is used in Low-power run, Low-power sleep and Stop modes.

In Standby and Shutdown modes, both regulators are powered down and their outputs set in high-impedance state, such as to bring their current consumption close to zero. However,

SRAM data retention is possible in Standby mode, in which case the LPR remains active and it only supplies the SRAM.

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By default, the microcontroller is in Run mode after system or power reset. It is up to the user to select one of the low-power modes described below:

• Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

• Low-power run mode

This mode is achieved with V

CORE

supplied by the low-power regulator to minimize the regulator's operating current. The code can be executed from SRAM or from Flash, and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can be clocked by HSI16.

• Low-power sleep mode

This mode is entered from the low-power run mode. Only the CPU clock is stopped.

When wakeup is triggered by an event or an interrupt, the system reverts to the Lowpower run mode.

• Stop 0 and Stop 1 modes

In Stop 0 and Stop 1 modes, the device achieves the lowest power consumption while retaining the SRAM and register contents. All clocks in the V

CORE

domain are stopped.

The PLL, as well as the HSI16 RC oscillator and the HSE crystal oscillator are disabled. The LSE or LSI keep running. The RTC can remain active (Stop mode with

RTC, Stop mode without RTC).

Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode, so as to get clock for processing the wakeup event. The main regulator remains active in Stop 0 mode while it is turned off in Stop 1 mode.

• Standby mode

The Standby mode is used to achieve the lowest power consumption, with POR/PDR always active in this mode. The main regulator is switched off to power down V

CORE domain. The low-power regulator is either switched off or kept active. In the latter case, it only supplies SRAM to ensure data retention. The PLL, as well as the HSI16 RC oscillator and the HSE crystal oscillator are also powered down. The RTC can remain active (Standby mode with RTC, Standby mode without RTC).

For each I/O, the software can determine whether a pull-up, a pull-down or no resistor shall be applied to that I/O during Standby mode.

Upon entering Standby mode, register contents are lost except for registers in the RTC domain and standby circuitry. The SRAM contents can be retained through register setting.

The device exits Standby mode upon external reset event (NRST pin), IWDG reset event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC event

(alarm, periodic wakeup, timestamp, tamper), or when a failure is detected on LSE

(CSS on LSE).

• Shutdown mode

The Shutdown mode allows to achieve the lowest power consumption. The internal regulator is switched off to power down the V

CORE

domain. The PLL, as well as the

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Functional overview STM32G0B1xB/xC/xE

HSI16 and LSI RC-oscillators and HSE crystal oscillator are also powered down. The

RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).

The BOR is not available in Shutdown mode. No power voltage monitoring is possible in this mode. Therefore, switching to RTC domain is not supported.

SRAM and register contents are lost except for registers in the RTC domain.

The device exits Shutdown mode upon external reset event (NRST pin), IWDG reset event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC event

(alarm, periodic wakeup, timestamp, tamper).

During and upon exiting reset, the schmitt triggers of I/Os are disabled so as to reduce power consumption. In addition, when the reset source is internal, the built-in pull-up resistor on NRST pin is deactivated.

Note:

3.8

The V

BAT

power domain, consuming very little energy, includes RTC, and LSE oscillator and backup registers.

In VBAT mode, the RTC domain is supplied from VBAT pin. The power source can be, for example, an external battery or an external supercapacitor. Two anti-tamper detection pins are available.

The RTC domain can also be supplied from VDD/VDDA pin.

By means of a built-in switch, an internal voltage supervisor allows automatic switching of

RTC domain powering between V

DD voltage of the RTC domain (V

BAT

and voltage from VBAT pin to ensure that the supply

) remains within valid operating conditions. If both voltages are valid, the RTC domain is supplied from VDD/VDDA pin.

An internal circuit for charging the battery on VBAT pin can be activated if the V

DD within a valid range.

voltage is

External interrupts and RTC alarm/events cannot cause the microcontroller to exit the VBAT mode, as in that mode the V

is not within a valid range.

Interconnect of peripherals

Several peripherals have direct connections between them. This allows autonomous communication between peripherals, saving CPU resources thus power supply consumption. In addition, these hardware connections allow fast and predictable latency.

Depending on peripherals, these interconnections can operate in Run, Sleep and Stop modes.

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Interconnect source

Table 4. Interconnect of peripherals

Interconnect destination

Interconnect action

TIMx

COMPx

ADCx

RTC

GPIO

TIMx

ADCx

DACx

DMA

COMPx

TIM1,2,3,4

LPTIMERx

TIM1

TIM16

LPTIMERx

Timer synchronization or chaining

Conversion triggers

Memory-to-memory transfer trigger

Comparator output blanking

Timer input channel, trigger, break from analog signals comparison

Low-power timer triggered by analog signals comparison

Timer triggered by analog watchdog

Timer input channel from RTC events

Low-power timer triggered by RTC alarms or tampers

Clock source used as input channel for

RC measurement and trimming

All clock sources (internal and external)

CSS

RAM (parity error)

Flash memory (ECC error)

COMPx

PVD

CPU (hard fault)

TIM14,16,17

TIM1,15,16,17 Timer break

TIMx External trigger

LPTIMERx External trigger

ADC

DACx

Conversion external trigger

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Functional overview

3.9 Clocks and startup

STM32G0B1xB/xC/xE

The clock controller distributes the clocks coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness. It features:

• Clock prescaler: to get the best trade-off between speed and current consumption, the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler

• Safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register.

• Clock management: to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory.

• System clock source: three different sources can deliver SYSCLK system clock:

– 4-48 MHz high-speed oscillator with external crystal or ceramic resonator (HSE). It can supply clock to system PLL. The HSE can also be configured in bypass mode for an external clock.

– 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software. It can supply clock to system PLL.

– System PLL with maximum output frequency of 64 MHz. It can be fed with HSE or

HSI16 clocks.

• Auxiliary clock source: two ultra-low-power clock sources for the real-time clock

(RTC):

– 32.768 kHz low-speed oscillator with external crystal (LSE), supporting four drive capability modes. The LSE can also be configured in bypass mode for using an external clock.

– 32 kHz low-speed internal RC oscillator (LSI) with ±5% accuracy, also used to clock an independent watchdog.

• USB clock source:

– HSI 48 MHz in association with CRS can provide a dedicated clock to USB FS allowing the peripheral to operate as device without requiring an external resonator

• Peripheral clock sources: several peripherals ( I2S, USARTs, I2Cs, LPTIMs, ADC,

USB FS) have their own clock independent of the system clock.

• Clock security system (CSS): in the event of HSE clock failure, the system clock is automatically switched to HSI16 and, if enabled, a software interrupt is generated. LSE clock failure can also be detected and generate an interrupt. The CCS feature can be enabled by software.

• Clock output:

– MCO (microcontroller clock output) provides one of the internal clocks for external use by the application

– LSCO (low speed clock output) provides LSI or LSE in all low-power modes

(except in VBAT operation).

Several prescalers allow the application to configure AHB and APB domain clock frequencies, 64 MHz at maximum.

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Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function (AF). Most of the GPIO pins are shared with special digital or analog functions.

Through a specific sequence, this special function configuration of I/Os can be locked, such as to avoid spurious writing to I/O control registers.

3.11 Direct memory access controller (DMA)

The direct memory access (DMA) controller is a bus master and system peripheral with single-AHB architecture.

With 12 channels, it performs data transfers between memory-mapped peripherals and/or memories, to offload the CPU.

Each channel is dedicated to managing memory access requests from one or more peripherals. The unit includes an arbiter for handling the priority between DMA requests.

Main features of the DMA controller:

• Single-AHB master

• Peripheral-to-memory, memory-to-peripheral, memory-to-memory and peripheral-toperipheral data transfers

• Access, as source and destination, to on-chip memory-mapped devices such as Flash memory, SRAM, and AHB and APB peripherals

• All DMA channels independently configurable:

– Each channel is associated either with a DMA request signal coming from a peripheral, or with a software trigger in memory-to-memory transfers. This configuration is done by software.

– Priority between the requests is programmable by software (four levels per channel: very high, high, medium, low) and by hardware in case of equality (such as request to channel 1 has priority over request to channel 2).

– Transfer size of source and destination are independent (byte, half-word, word), emulating packing and unpacking. Source and destination addresses must be aligned on the data size.

– Support of transfers from/to peripherals to/from memory with circular buffer management

– Programmable number of data to be transferred: 0 to 2

- 1

• Generation of an interrupt request per channel. Each interrupt request originates from any of the three DMA events: transfer complete, half transfer, or transfer error.

3.12 DMA request multiplexer (DMAMUX)

The DMAMUX request multiplexer enables routing a DMA request line between the peripherals and the DMA controller. Each channel selects a unique DMA request line, unconditionally or synchronously with events from its DMAMUX synchronization inputs.

DMAMUX may also be used as a DMA request generator from programmable events on its input trigger signals.

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Functional overview STM32G0B1xB/xC/xE

The device flexibly manages events causing interrupts of linear program execution, called exceptions. The Cortex-M0+ processor core, a nested vectored interrupt controller (NVIC) and an extended interrupt/event controller (EXTI) are the assets contributing to handling the exceptions. Exceptions include core-internal events such as, for example, a division by zero and, core-external events such as logical level changes on physical lines. Exceptions result in interrupting the program flow, executing an interrupt service routine (ISR) then resuming the original program flow.

The processor context (contents of program pointer and status registers) is stacked upon program interrupt and unstacked upon program resume, by hardware. This avoids context stacking and unstacking in the interrupt service routines (ISRs) by software, thus saving time, code and power. The ability to abandon and restart load-multiple and store-multiple operations significantly increases the device’s responsiveness in processing exceptions.

3.13.1 Nested vectored interrupt controller (NVIC)

The configurable nested vectored interrupt controller is tightly coupled with the core. It handles physical line events associated with a non-maskable interrupt (NMI) and maskable interrupts, and Cortex-M0+ exceptions. It provides flexible priority management.

The tight coupling of the processor core with NVIC significantly reduces the latency between interrupt events and start of corresponding interrupt service routines (ISRs). The ISR vectors are listed in a vector table, stored in the NVIC at a base address. The vector address of an ISR to execute is hardware-built from the vector table base address and the

ISR order number used as offset.

If a higher-priority interrupt event happens while a lower-priority interrupt event occurring just before is waiting for being served, the later-arriving higher-priority interrupt event is served first. Another optimization is called tail-chaining. Upon a return from a higher-priority

ISR then start of a pending lower-priority ISR, the unnecessary processor context unstacking and stacking is skipped. This reduces latency and contributes to power efficiency.

Features of the NVIC:

• Low-latency interrupt processing

• 4 priority levels

• Handling of a non-maskable interrupt (NMI)

• Handling of 32 maskable interrupt lines

• Handling of 10 Cortex-M0+ exceptions

• Later-arriving higher-priority interrupt processed first

• Tail-chaining

• Interrupt vector retrieval by hardware

3.13.2 Extended interrupt/event controller (EXTI)

The extended interrupt/event controller adds flexibility in handling physical line events and allows identifying wake-up events at processor wakeup from Stop mode.

The EXTI controller has a number of channels, of which some with rising, falling or rising, and falling edge detector capability. Any GPIO and a few peripheral signals can be connected to these channels.

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The channels can be independently masked.

The EXTI controller can capture pulses shorter than the internal clock period.

A register in the EXTI controller latches every event even in Stop mode, which allows the software to identify the origin of the processor's wake-up from Stop mode or, to identify the

GPIO and the edge event having caused an interrupt.

3.14 Analog-to-digital converter (ADC)

A native 12-bit analog-to-digital converter is embedded into STM32G0B1xB/xC/xE devices.

It can be extended to 16-bit resolution through hardware oversampling. The ADC has up to

16 external channels and 3 internal channels (temperature sensor, voltage reference, V

BAT monitoring). It performs conversions in single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs.

The ADC frequency is independent from the CPU frequency, allowing maximum sampling rate of ~2 MSps even with a low CPU speed. An auto-shutdown function guarantees that the ADC is powered off except during the active conversion phase.

The ADC can be served by the DMA controller. It can operate in the whole V

DD range.

supply

The ADC features a hardware oversampler up to 256 samples, improving the resolution to

16 bits (refer to AN2668).

An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all scanned channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.

The events generated by the general-purpose timers (TIMx) can be internally connected to the ADC start triggers, to allow the application to synchronize A/D conversions with timers.

The temperature sensor (TS) generates a voltage V

that varies linearly with temperature.

The temperature sensor is internally connected to an ADC input to convert the sensor output voltage into a digital value.

The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor may vary from part to part due to process variation, the uncalibrated internal temperature sensor is suitable only for relative temperature measurements.

To improve the accuracy of the temperature sensor, each part is individually factorycalibrated by ST. The resulting calibration data are stored in the part’s engineering bytes, accessible in read-only mode.

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Functional overview STM32G0B1xB/xC/xE

Table 5. Temperature sensor calibration values

Calibration value name Description Memory address

TS_CAL1

TS_CAL2

TS ADC raw data acquired at a temperature of 30 °C (± 5 °C),

DDA

= V

REF+

= 3.0 V (± 10 mV)

TS ADC raw data acquired at a temperature of 130 °C (± 5 °C),

DDA

= V

REF+

= 3.0 V (± 10 mV)

0x1FFF 75A8 - 0x1FFF 75A9

0x1FFF 75CA - 0x1FFF 75CB

3.14.2 Internal voltage reference (V

REFINT

)

The internal voltage reference (V

REFINT

ADC and comparators. V

REFINT

) provides a stable (bandgap) voltage output for the

is internally connected to an ADC input. The V

REFINT voltage is individually precisely measured for each part by ST during production test and stored in the part’s engineering bytes. It is accessible in read-only mode.

Table 6. Internal voltage reference calibration values

Calibration value name Description Memory address

REFINT

Raw data acquired at a temperature of 30 °C (± 5 °C),

DDA

= V

REF+

= 3.0 V (± 10 mV)

0x1FFF 75AA - 0x1FFF 75AB

3.14.3 V

BAT

battery voltage monitoring

This embedded hardware feature allows the application to measure the V

BAT using an internal ADC input. As the V

BAT

voltage may be higher than V

DDA

battery voltage

and thus outside the ADC input range, the VBAT pin is internally connected to a bridge divider by three. As a consequence, the converted digital value is one third the V

BAT

voltage.

The 2-channel 12-bit buffered DAC converts a digital value into an analog voltage available on the channel output. The architecture of either channel is based on integrated resistor string and an inverting amplifier. The digital circuitry is common for both channels.

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Features of the DAC:

• Two DAC output channels

• 8-bit or 12-bit output mode

• Buffer offset calibration (factory and user trimming)

• Left or right data alignment in 12-bit mode

• Synchronized update capability

• Noise-wave generation

• Triangular-wave generation

• Independent or simultaneous conversion for DAC channels

• DMA capability for either DAC channel

• Triggering with timer events, synchronized with DMA

• Triggering with external events

• Sample-and-hold low-power mode, with internal or external capacitor

When enabled, an embedded buffer provides the internal reference voltage to analog blocks (for example ADC) and to VREF+ pin for external components.

The internal voltage reference buffer supports two voltages:

• 2.048 V

• 2.5 V

An external voltage reference can be provided through the VREF+ pin when the internal voltage reference buffer is disabled.

On some packages, the VREF+ pad of the silicon die is double-bonded with supply pad to common VDD/VDDA pin and so the internal voltage reference buffer cannot be used.

Three embedded rail-to-rail analog comparators have programmable reference voltage

(internal or external), hysteresis, speed (low for low-power) and output polarity.

The reference voltage can be one of the following:

• external, from an I/O

• internal, from DAC

• internal reference voltage (V

REFINT

) or its submultiple (1/4, 1/2, 3/4)

The comparators can wake up the device from Stop mode, generate interrupts, breaks or triggers for the timers and can be also combined into a window comparator.

3.18 Timers and watchdogs

The device includes an advanced-control timer, seven general-purpose timers, two basic timers, two low-power timers, two watchdog timers and a SysTick timer.

Table 7

compares features of the advanced-control, general-purpose and basic timers.

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Functional overview STM32G0B1xB/xC/xE

Timer type

Advanced- control

Generalpurpose

Basic

Low-power

Timer

TIM1

TIM2

TIM3

TIM4

TIM14

TIM15

TIM16

TIM17

TIM6

TIM7

LPTIM1

LPTIM2

Counter resolution

Table 7. Timer feature comparison

Counter type

Maximum operating frequency

Prescaler factor

DMA request generation

Capture/ compare channels

16-bit

32-bit

16-bit

Up, down, up/down

128 MHz

64 MHz

128 MHz

64 MHz

Integer from

1 to 2 16

Integer from

1 to 2

Integer from

1 to 2

Integer from

1 to 2 16

Integer from

1 to 2

Integer from

1 to 2

Integer from

1 to 2 16

Integer from

1 to 2

2 n where n=0 to 7

Yes

N/A

Complementary outputs

3.18.1 Advanced-control timer (TIM1)

The advanced-control timer can be seen as a three-phase PWM unit multiplexed on 6 channels. It has complementary PWM outputs with programmable inserted dead-times. It can also be seen as a complete general-purpose timer. The four independent channels can be used for:

• input capture

• output compare

• PWM output (edge or center-aligned modes) with full modulation capability (0-100%)

• one-pulse mode output

In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled, so as to turn off any power switches driven by these outputs.

Many features are shared with those of the general-purpose TIMx timers (described in

Section 3.18.2

together with the TIMx timers via the Timer Link feature for synchronization or event chaining.

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There are seven synchronizable general-purpose timers embedded in the device (refer to

Table 7 for comparison). Each general-purpose timer can be used to generate PWM outputs

or act as a simple timebase.

• TIM2, TIM3, and TIM4

These are full-featured general-purpose timers:

– TIM2 with 32-bit auto-reload up/downcounter and 16-bit prescaler

– TIM3 and TIM4 with 16-bit auto-reload up/downcounter and 16-bit prescaler

They have four independent channels for input capture/output compare, PWM or onepulse mode output. They can operate in combination with other general-purpose timers via the Timer Link feature for synchronization or event chaining. They can generate independent DMA request and support quadrature encoders. Their counter can be frozen in debug mode.

• TIM14

This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. It has one channel for input capture/output compare, PWM output or one-pulse mode output. Its counter can be frozen in debug mode.

• TIM15, TIM16, TIM17

These are general-purpose timers featuring:

– 16-bit auto-reload upcounter and 16-bit prescaler

– 2 channels and 1 complementary channel for TIM15

– 1 channel and 1 complementary channel for TIM16 and TIM17

All channels can be used for input capture/output compare, PWM or one-pulse mode output. The timers can operate together via the Timer Link feature for synchronization or event chaining. They can generate independent DMA request. Their counters can be frozen in debug mode.

3.18.3 Basic timers (TIM6 and TIM7)

These timers are mainly used for triggering DAC conversions. They can also be used as generic 16-bit timebases.

These timers have an independent clock. When fed with LSE, LSI or external clock, they keep running in Stop mode and they can wake up the system from it.

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Functional overview STM32G0B1xB/xC/xE

Features of LPTIM1 and LPTIM2:

• 16-bit up counter with 16-bit autoreload register

• 16-bit compare register

• Configurable output (pulse, PWM)

• Continuous/one-shot mode

• Selectable software/hardware input trigger

• Selectable clock source:

– Internal: LSE, LSI, HSI16 or APB clocks

– External: over LPTIM input (working even with no internal clock source running, used by pulse counter application)

• Programmable digital glitch filter

• Encoder mode

The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with user-defined refresh window. It is clocked from an independent 32 kHz internal RC (LSI).

Independent of the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. Its counter can be frozen in debug mode.

3.18.6 System window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked by the system clock. It has an early-warning interrupt capability. Its counter can be frozen in debug mode.

This timer is dedicated to real-time operating systems, but it can also be used as a standard down counter.

Features of SysTick timer:

• 24-bit down counter

• Autoreload capability

• Maskable system interrupt generation when the counter reaches 0

• Programmable clock source

3.19 Real-time clock (RTC), tamper (TAMP) and backup registers

The device embeds an RTC and five 32-bit backup registers, located in the RTC domain of the silicon die.

The ways of powering the RTC domain are described in

Section 3.7.6

The RTC is an independent BCD timer/counter.

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Features of the RTC:

• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format

• Automatic correction for 28, 29 (leap year), 30, and 31 days of the month

• Programmable alarm

• On-the-fly correction from 1 to 32767 RTC clock pulses, usable for synchronization with a master clock

• Reference clock detection - a more precise second-source clock (50 or 60 Hz) can be used to improve the calendar precision

• Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal inaccuracy

• Two anti-tamper detection pins with programmable filter

• Timestamp feature to save a calendar snapshot, triggered by an event on the timestamp pin or a tamper event, or by switching to VBAT mode

• 17-bit auto-reload wakeup timer (WUT) for periodic events, with programmable resolution and period

• Multiple clock sources and references:

– A 32.768 kHz external crystal (LSE)

– An external resonator or oscillator (LSE)

– The internal low-power RC oscillator (LSI, with typical frequency of 32 kHz)

– The high-speed external clock (HSE) divided by 32

When clocked by LSE, the RTC operates in VBAT mode and in all low-power modes. When clocked by LSI, the RTC does not operate in VBAT mode, but it does in low-power modes except for the Shutdown mode.

All RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt and wake the device up from the low-power modes.

The backup registers allow keeping 20 bytes of user application data in the event of V

DD failure, if a valid backup supply voltage is provided on VBAT pin. They are not affected by the system reset, power reset, and upon the device’s wakeup from Standby or Shutdown modes.

The device embeds three I2C peripherals. Refer to

Table 8

for the features.

The I

C-bus interface handles communication between the microcontroller and the serial

C-bus. It controls all I

C-bus-specific sequencing, protocol, arbitration and timing.

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Functional overview STM32G0B1xB/xC/xE

Features of the I2C peripheral:

• I 2 C-bus specification and user manual rev. 5 compatibility:

– Slave and master modes, multimaster capability

– Standard-mode (Sm), with a bitrate up to 100 kbit/s

– Fast-mode (Fm), with a bitrate up to 400 kbit/s

– Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and extra output drive I/Os

– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses

– Programmable setup and hold times

– Clock stretching

• SMBus specification rev 3.0 compatibility:

– Hardware PEC (packet error checking) generation and verification with ACK control

– Command and data acknowledge control

– Address resolution protocol (ARP) support

– Host and Device support

– SMBus alert

– Timeouts and idle condition detection

• PMBus rev 1.3 standard compatibility

• Independent clock: a choice of independent clock sources allowing the I2C communication speed to be independent of the PCLK reprogramming

• Wakeup from Stop mode on address match

• Programmable analog and digital noise filters

• 1-byte buffer with DMA capability

Table 8. I 2 C implementation

C features

(1)

Standard mode (up to 100 kbit/s)

Fast mode (up to 400 kbit/s)

Fast Mode Plus (up to 1 Mbit/s) with extra output drive I/Os

Programmable analog and digital noise filters

SMBus/PMBus hardware support

Independent clock

Wakeup from Stop mode on address match

1. X: supported

I2C1

I2C2

I2C3

(USART)

The device embeds universal synchronous/asynchronous receivers/transmitters that communicate at speeds of up to 8 Mbit/s.

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They provide hardware management of the CTS, RTS and RS485 DE signals, multiprocessor communication mode, master synchronous communication and single-wire half-duplex communication mode. Some can also support SmartCard communication (ISO

7816), IrDA SIR ENDEC, LIN Master/Slave capability and auto baud rate feature, and have a clock domain independent of the CPU clock, which allows them to wake up the MCU from

Stop mode. The wakeup events from Stop mode are programmable and can be:

• start bit detection

• any received data frame

• a specific programmed data frame

All USART interfaces can be served by the DMA controller.

Table 9. USART implementation

USART modes/features

(1)

USART1

USART2

USART3

Hardware flow control for modem

Continuous communication using DMA

Multiprocessor communication

Synchronous mode

Smartcard mode

Single-wire half-duplex communication

IrDA SIR ENDEC block

LIN mode

Dual clock domain and wakeup from Stop mode

Receiver timeout interrupt

Modbus communication

Auto baud rate detection

Driver Enable

1. X: supported

USART4

USART5

USART6

(LPUART)

The device embeds two LPUARTs. The peripheral supports asynchronous serial communication with minimum power consumption. It supports half duplex single wire communication and modem operations (CTS/RTS). It allows multiprocessor communication.

The LPUART has a clock domain independent of the CPU clock, and can wakeup the system from Stop mode. The Stop mode wakeup events are programmable and can be:

• start bit detection

• any received data frame

• a specific programmed data frame

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Functional overview STM32G0B1xB/xC/xE

Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while having an extremely low energy consumption. Higher speed clock can be used to reach higher baudrates.

The LPUART interface can be served by the DMA controller.

3.23 Serial peripheral interface (SPI)

The device contains three SPIs running at up to 32 Mbits/s in master and slave modes. It supports half-duplex, full-duplex and simplex communications. A 3-bit prescaler gives eight master mode frequencies. The frame size is configurable from 4 bits to 16 bits. The SPI peripherals support NSS pulse mode, TI mode and hardware CRC calculation.

The SPI peripherals can be served by the DMA controller.

The I

S interface mode of the SPI peripheral (if supported, see the following table) supports four different audio standards can operate as master or slave, in half-duplex communication mode. It can be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data resolution and synchronized by a specific signal. Audio sampling frequency from 8 kHz up to

192 kHz can be set by an 8-bit programmable linear prescaler. When operating in master mode, it can output a clock for an external audio component at 256 times the sampling frequency.

Hardware CRC calculation

Rx/Tx FIFO

NSS pulse mode

S mode

TI mode

1. X = supported.

Table 10. SPI/I2S implementation

SPI features

(1)

SPI1

SPI2

SPI3

3.24 Universal serial bus device (USB) and host (USBH)

The devices embed a USB controller with full-speed USB device and host functionality compliant with the USB specification version 2.0. The internal USB PHY supports USB FS signaling, embedded DP pull-up and also battery charging detection according to Battery

Charging Specification Revision 1.2. The USB interface implements a full-speed (12 Mbit/s) function interface with added support for USB 2.0 Link Power Management. It has softwareconfigurable endpoint setting with packet memory up to 1 KB and suspend/resume support.

It requires a precise 48 MHz clock that is generated from the internal main PLL (the clock source must use a HSE crystal oscillator) or by the internal 48 MHz oscillator in automatic trimming mode. The synchronization for this oscillator can be taken from the USB data stream itself (SOF signalization) which allows crystal less operation.

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3.25 USB Type-C™ Power Delivery controller

The device embeds two controllers (UCPD1 and UCPD2) compliant with USB Type-C Rev.

1.2 and USB Power Delivery Rev. 3.0 specifications.

The controllers use specific I/Os supporting the USB Type-C and USB Power Delivery requirements, featuring:

• USB Type-C pull-up (Rp, all values) and pull-down (Rd) resistors

• “Dead battery” support

• USB Power Delivery message transmission and reception

• FRS (fast role swap) support

The digital controller handles notably:

• USB Type-C level detection with de-bounce, generating interrupts

• FRS detection, generating an interrupt

• byte-level interface for USB Power Delivery payload, generating interrupts (DMA compatible)

• USB Power Delivery timing dividers (including a clock pre-scaler)

• CRC generation/checking

• 4b5b encode/decode

• ordered sets (with a programmable ordered set mask at receive)

• frequency recovery in receiver during preamble

The interface offers low-power operation compatible with Stop mode, maintaining the capacity to detect incoming USB Power Delivery messages and FRS signaling.

3.26 Controller area network (FDCAN)

The controller area network (CAN) subsystem consists of two CAN modules and a message

RAM.

The CAN modules are compliant with ISO 11898-1 (CAN protocol specification version 2.0 part A, B) and CAN FD protocol specification version 1.0.

The 1-Kbyte message RAM per CAN module implements filters, receive FIFOs, receive buffers, transmit event FIFOs, and transmit buffers.

3.27.1 Serial wire debug port (SW-DP)

An Arm SW-DP interface is provided to allow a serial wire debugging tool to be connected to the MCU.

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4

STM32G0B1xB/xC/xE

Pinouts, pin description and alternate functions

The devices housed in 32-pin, 48-pin, and 64-pin packages come in two variants - “GP” and

“N” (the latter with ordering code having N behind the temperature range digit). Refer to

Table 2: Features and peripheral counts for differences.

Figure 3. STM32G0B1VxT LQFP100 pinout

Top view

PB9

PC10

PC11

PE4

PE5

PE6

PC12

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

VBAT

VREF+

VDD/VDDA

VSS/VSSA

PF0-OSC_IN

PF1-OSC_OUT

PF2-NRST

PF3

PF4

PF5

PC0

PC1

PC2

PC3

PA0

LQFP100

PD11

PD10

PD9

PD8

PC7

PC6

PA9

PA8

PB15

PB14

PB13

PB12

PA15

PA14-BOOT0

PA13

PF8

PA12 [PA10]

PA11 [PA9]

PA10

PD15

PD14

PD13

PD12

VDDIO2

VSS

1. The I/O pins supplied by V

DDIO2

are shown in gray.

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Figure 4. STM32G0B1VxI UFBGA100 pinout

Top view

1 2 3 4 5 6 7 8 9 10 11 12

A PB8 PE3 PE2 PE0 PB3 PF13 PF11 PF9 PD6 PD5 PD2 PC9

PC11 PC10 PB7 PE1

PE6 PE4

VDD VREF+

PB9

PC14-

OSC32

_IN

PC15-

OSC32

_OUT

PC12

VBAT

PE5

PC13

PB6

PB4 PF12 PF10 PD7

PB5 PD3

PD4 PD0 PA15

PA14-

BOOT0

PD1 PC8 PA13

PA12

[PA10]

PF8 PD15

PA11

[PA9]

PA10 PD14 PD13

PD12

VDDIO

VSS

PF2-

NRST

PF0-

OSC_I

PF1-

OSC_

OUT

PF4

PF5

PF3

PC1

PC0 PC2 PA0 PA3 PA7

PD11 VSS

PA9 PD9 PD10

PB15 PC6 PD8

PE9 PE14 PB12 PB14 PC7

L PC3 PA1 PA4 PC4 PB0 PB2 PF7 PE10 PE12 PE15 PB11 PA8

M PA2 PA5 PA6 PC5 PB1 PF6 PE7 PE8 PE11 PE13 PB10 PB13

1. The I/O pads supplied by V

DDIO2

are shown in gray.

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Pinouts, pin description and alternate functions

Figure 5. STM32G0B1MxT LQFP80 pinout

Top view

STM32G0B1xB/xC/xE

PB9

PC10

PC11

PC12

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

VBAT

VREF+

VDD

VSS

PF0-OSC_IN

PF1-OSC_OUT

PF2-NRST

PC0

PC1

PC2

PC3

PA0

PA1

LQFP80

PA14-BOOT0

PA13

PA12 [PA10]

PA11 [PA9]

PA10

PD15

PD8

PC7

PC6

PA9

PA8

PB15

PD14

PD13

PD12

VDDIO2

VSS

PD11

PD10

PD9

1. The I/O pins supplied by V

DDIO2

are shown in gray.

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STM32G0B1xB/xC/xE Pinouts, pin description and alternate functions

Figure 6. STM32G0B1RxT LQFP64 pinout

Top view

PC11

PC12

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

VBAT

VREF+

VDD/VDDA

VSS/VSSA

PF0-OSC_IN

PF1-OSC_OUT

PF2-NRST

PC0

PC1

PC2

PC3

LQFP64

PC8

PA15

PA14-BOOT0

PA13

PA12 [PA10]

PA11 [PA9]

PA10

PD9

PD8

PC7

GP version

(_RxT)

PC6

PA9

PA8

PB15

PB14

PB13

Top view

PC11

PC12

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

VBAT

VREF+

VDD/VDDA

VSS/VSSA

PF0-OSC_IN

PF1-OSC_OUT

PF2-NRST

PC0

PC1

PC2

PC3

LQFP64

PC8

PA15

PA14-BOOT0

PA13

PA12 [PA10]

PA11 [PA9]

PA10

VDDIO2

VSS

PC7

PC6

PA9

PA8

PB15

PB14

PB13

N version

(_RxTxN)

1. The I/O pins supplied by V

DDIO2

are shown in gray.

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Pinouts, pin description and alternate functions STM32G0B1xB/xC/xE

Figure 7. STM32G0B1RxI UFBGA64 pinout

1 2 3 4 5 6 7 8

Top view

PC11 PC10 PB7 PB6

PC15-

OSC32

_OUT

PC14-

OSC32

_IN

PC12

PC13

PB8

PB9

VDD/

VDDA

VREF+ VBAT

PB3

PB4

PB5

PD6

PD5

PD2

PD1

PD0 PC8

PC9

PA12

[PA10]

PD4 PA15

PA14-

BOOT0

PA11

[PA9]

PD3 PA10 PA13

VDDIO

VSS/

VSSA

PF2-

NRST

PF0-

OSC_I

PF1-

OSC_

OUT

PC1

PC2

PC0

PA3

PA2

PC3 PA0 PA1

PA7

PA6

PA5

PA4

PC7 PA9

PC4 PC5

PC6 VSS

PB0 PB14 PB15 PA8

PB1 PB10 PB12 PB13

PB2 PB11

N version

(_RxIxN)

1. The I/O pads supplied by V

DDIO2

are shown in gray.

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Top view

Pinouts, pin description and alternate functions

Figure 8. STM32G0B1NxY WLCSP52 pinout

1 2 3 4 5 6 7 8 9 10 11 12 13

PA15 PD0 PD3 PB3 PB5 PB8

PA12

[PA10]

PA11

[PA9]

PA13

PA10

PA14-

BOOT0

PD1

PD2

PB6

PB4

VBAT

PC13

PC15-

OSC32

_OUT

PC14-

OSC32

_IN

VDDIO

PC7 PC6 PB7 PB9 VREF+

VDD/

VDDA

VSS PA9 PB12 PA2 PA1

VSS/

VSSA

PA8

PB14

PB15

PB2

PB11

PC5

PA6

PC4

PA5

PA4

PF2-

NRST

PF1-

OSC_

OUT

PF0-

OSC_IN

PB13 PB10 PB1 PB0 PA7 PA3 PA0

1. The I/O pads supplied by V

DDIO2

are shown in gray.

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Pinouts, pin description and alternate functions

Figure 9. STM32G0B1CxT LQFP48 pinout

Top view

STM32G0B1xB/xC/xE

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

VBAT

VREF+

VDD/VDDA

VSS/VSSA

PF0-OSC_IN

PF1-OSC_OUT

PF2-NRST

PA0

PA1

LQFP48

PA14-BOOT0

PA13

PA12 [PA10]

PA11 [PA9]

PA10

PC7

PC6

PA9

PA8

PB15

PB14

PB13

GP version

(_RxT)

Top view

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

VBAT

VREF+

VDD/VDDA

VSS/VSSA

PF0-OSC_IN

PF1-OSC_OUT

PF2-NRST

PA0

PA1

LQFP48

PA14-BOOT0

PA13

PA12 [PA10]

PA11 [PA9]

PA10

VDDIO2

VSS

PA9

PA8

PB15

PB14

PB13

N version

(_RxTxN)

1. The I/O pins supplied by V

DDIO2

are shown in gray.

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Figure 10. STM32G0B1CxU UFQFPN48 pinout

Top view

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

VBAT

VREF+

VDD/VDDA

VSS/VSSA

PF0-OSC_IN

PF1-OSC_OUT

PF2-NRST

PA0

PA1

UFQFPN48 31

PA14-BOOT0

PA13

PA12 [PA10]

PA11 [PA9]

PA10

PC7

PC6

PA9

PA8

PB15

PB14

PB13

GP version

(_CxT)

VSS

Top view

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

VBAT

VREF+

VDD/VDDA

VSS/VSSA

PF0-OSC_IN

PF1-OSC_OUT

PF2-NRST

PA0

PA1

UFQFPN48

PA14-BOOT0

PA13

PA12 [PA10]

PA11 [PA9]

PA10

VDDIO2

VSS

PA9

PA8

PB15

PB14

PB13

N version

(_CxTxN)

VSS

1. The I/O leads supplied by V

DDIO2

are shown in dark gray.

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Pinouts, pin description and alternate functions

Figure 11. STM32G0B1KxT LQFP32 pinout

STM32G0B1xB/xC/xE

Top view

PB9

PC14-OSC32_IN

PC15-OSC32_OUT

VDD/VDDA

VSS/VSSA

PF2-NRST

PA0

PA1

LQFP32

PA13

PA12 [PA10]

PA11 [PA9]

PA10

PC6

PA9

PA8

PB2

GP version

(_KxT)

Top view

PB9

PC14-OSC32_IN

PC15-OSC32_OUT

VDD/VDDA

VSS/VSSA

PF2-NRST

PA0

PA1

LQFP32

PA13

PA12 [PA10]

PA11 [PA9]

PA10

VDDIO2

PA9

PA8

PB15

N version

(_KxTxN)

MSv39712V3

1. The I/O pins supplied by V

DDIO2

are shown in dark gray.

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Figure 12. STM32G0B1KxU UFQFPN32 pinout

Top view

PB9

PC14-OSC32_IN

PC15-OSC32_OUT

VDD/VDDA

VSS/VSSA

PF2-NRST

PA0

PA1

UFQFPN32

PA13

PA12 [PA10]

PA11 [PA9]

PA10

PC6

PA9

PA8

PB2

VSS

GP version

(_KxU)

Top view

PB9

PC14-OSC32_IN

PC15-OSC32_OUT

VDD/VDDA

VSS/VSSA

PF2-NRST

PA0

PA1

UFQFPN32

PA13

PA12 [PA10]

PA11 [PA9]

PA10

VDDIO2

PA9

PA8

PB15

VSS

N version

(_KxUxN)

MSv39715V3

1. The I/O leads supplied by V

DDIO2

are shown in dark gray.

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Pinouts, pin description and alternate functions STM32G0B1xB/xC/xE

Column

Pin name

Pin type

I/O structure

Table 11. Terms and symbols used in Table 12

Symbol Definition

Terminal name corresponds to its by-default function at reset, unless otherwise specified in parenthesis under the pin name.

Supply pin

Input only pin

I/O

RST

Input / output pin

5 V tolerant I/O

3.6 V tolerant I/O

Bidirectional reset pin with embedded weak pull-up resistor

Options for TT or FT I/Os

I/O, Fm+ capable

I/O, with analog switch function

I/O, USB Type-C PD capable

I/O, with switchable diode to V

DDIOx

I/O, USB Type-C PD Dead Battery function

I/O, supplied from VDDIO2 only

Note Upon reset, all I/Os are set as analog inputs, unless otherwise specified.

Pin functions

Alternate functions

Functions selected through GPIOx_AFR registers

Additional functions

Functions directly selected/enabled through peripheral registers

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Pin number

Table 12. Pin assignment and description

Pin name

Alternate functions

Additional functions

64 64 A2 2

1 1 A1 3

2 B2

3 B1

4 C2

5 D3

6 C1

7 D2

PC10

PC11

PE4

PE5

PE6

PC12

2 2

3 3

4 4

5 5

1 1 B11 3 3 C2 5 8 E3 PC13 I/O

B13

3 3 C12 5

4 4 C10 6

5 5 D11 7

6 6 D13 8

7 7 E12 9

PC14-

OSC32_IN

PC14-

OSC32_IN

PC15-

OSC32_OUT

6 D3 8

7 D2 9

11 E2

12 F2

VBAT

VREF+

8 D1 10 13 F1 VDD/VDDA

9 E1 11 14 G1 VSS/VSSA

I/O

8 8 F13 10 10 F1 12 15 H1 PF0-OSC_IN I/O

I/O

USART3_TX, USART4_TX, TIM1_CH3, SPI3_SCK

USART3_RX, USART4_RX, TIM1_CH4, SPI3_MISO

TIM3_CH2

TIM3_CH3

TIM3_CH4

LPTIM1_IN1, UCPD1_FRSTX, TIM14_CH1,

USART5_TX, SPI3_MOSI

(1)(2) TIM1_BKIN

(1)(2)

TIM1_BKIN2

(1)(2) TIM1_BKIN2

(1)(2)

OSC32_EN, OSC_EN, TIM15_BKIN

CRS1_SYNC, EVENTOUT, TIM14_CH1

TAMP_IN3, WKUP3

TAMP_IN1, RTC_TS,

RTC_OUT1, WKUP2

OSC32_IN

OSC32_IN, OSC_IN

OSC32_OUT

VREFBUF_OUT

OSC_IN

Pin number

Table 12. Pin assignment and description (continued)

Pin name

Alternate functions

Additional functions

9 9 G12 11 11 G1 13 16 J1

PF1-

OSC_OUT

I/O

6 6 10 10 F11 12 12 E2 14 17 G2 PF2-NRST I/O

18 H3 PF3 I/O

19 H2

20 J2

PF4

PF5

I/O

11 H13 17

12 E10 18

13 E8 19

15 G2

19 G3

PC0

PC1

PC2

PC3

PA0

PA1

PA2

I/O

I/O FT_ea

I/O

FT_a

OSC_EN, EVENTOUT, TIM15_CH1N

MCO, LPUART2_TX, LPUART2_RTS_DE

LPUART2_RX, USART6_RTS_DE_CK

LPUART1_TX

LPUART1_RX

LPTIM1_IN1, LPUART1_RX, LPTIM2_IN1,

LPUART2_TX, USART6_TX, I2C3_SCL,

COMP3_OUT

LPTIM1_OUT, LPUART1_TX, TIM15_CH1,

LPUART2_RX, USART6_RX, I2C3_SDA

LPTIM1_IN2, SPI2_MISO/I2S2_MCK, TIM15_CH2,

FDCAN2_RX, COMP3_OUT

LPTIM1_ETR, SPI2_MOSI/I2S2_SD, LPTIM2_ETR,

FDCAN2_TX

SPI2_SCK/I2S2_CK, USART2_CTS,

TIM2_CH1_ETR, USART4_TX, LPTIM1_OUT,

UCPD2_FRSTX, COMP1_OUT

SPI1_SCK/I2S1_CK, USART2_RTS_DE_CK,

TIM2_CH2, USART4_RX, TIM15_CH1N,

I2C1_SMBA, EVENTOUT

SPI1_MOSI/I2S1_SD, USART2_TX, TIM2_CH3,

UCPD1_FRSTX, TIM15_CH1, LPUART1_TX,

COMP2_OUT

OSC_OUT

NRST

COMP3_INM7

COMP3_INP1

COMP1_INM8, ADC_IN0,

TAMP_IN2, WKUP1

COMP1_INP2, ADC_IN1

COMP2_INM8, ADC_IN2,

WKUP4, LSCO

Pin number

Table 12. Pin assignment and description (continued)

Pin name

Alternate functions

Additional functions

12 12 16 16 F9 22 22 G4 24 30 M2

13 13 17 17 F7 23 23 F4 25 31 M3

14 H11 20

15 G10 21

G8 25 25 H5 27 33 L4

G6 26 26 H6 28 34 M4

PA3

PA4

PA5

PA6

PA7

PC4

PC5

I/O FT_ea

I/O

TT_a

TT_ea

FT_ea

FT_a

SPI2_MISO/I2S2_MCK, USART2_RX, TIM2_CH4,

UCPD2_FRSTX, TIM15_CH2, LPUART1_RX,

EVENTOUT

SPI1_NSS/I2S1_WS, SPI2_MOSI/I2S2_SD,

USB_NOE, USART6_TX, TIM14_CH1,

LPTIM2_OUT, UCPD2_FRSTX, EVENTOUT,

SPI3_NSS

SPI1_NSS/I2S1_WS, SPI2_MOSI/I2S2_SD,

USB_NOE, USART6_TX, TIM14_CH1,

LPTIM2_OUT, UCPD2_FRSTX, EVENTOUT,

SPI3_NSS

SPI1_SCK/I2S1_CK, CEC, TIM2_CH1_ETR,

USART6_RX, USART3_TX, LPTIM2_ETR,

UCPD1_FRSTX, EVENTOUT

SPI1_MISO/I2S1_MCK, TIM3_CH1, TIM1_BKIN,

USART6_CTS, USART3_CTS, TIM16_CH1,

LPUART1_CTS, COMP1_OUT, I2C2_SDA,

I2C3_SDA

SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM1_CH1N,

USART6_RTS_DE_CK, TIM14_CH1, TIM17_CH1,

UCPD1_FRSTX, COMP2_OUT, I2C2_SCL,

I2C3_SCL

USART3_TX, USART1_TX, TIM2_CH1_ETR,

FDCAN1_RX

USART3_RX, USART1_RX, TIM2_CH2,

FDCAN1_TX

COMP2_INP2, ADC_IN3

ADC_IN4, DAC1_OUT1,

RTC_OUT2

ADC_IN4, DAC1_OUT1,

TAMP_IN1, RTC_TS,

RTC_OUT1, WKUP2

ADC_IN5, DAC1_OUT2

ADC_IN6

ADC_IN7

COMP1_INM7, ADC_IN17

COMP1_INP0, ADC_IN18,

WKUP5

Pin number

Table 12. Pin assignment and description (continued)

Pin name

Alternate functions

Additional functions

27 F5

28 G5

PB0

PB1

17 21 21 G4 29 29 H7 31 37 L6

38 M6

39 L7

32 40 M7

33 41 M8

34 42 K8

35 43 L8

44 M9

45 L9

46 M10

47 K9

48 L10

PB2

PF6

PF7

PE7

PE8

PE9

PE10

PE11

PE12

PE13

PE14

PE15

I/O FT_ea

I/O

I/O FT_a

SPI1_NSS/I2S1_WS, TIM3_CH3, TIM1_CH2N,

FDCAN2_RX, USART3_RX, LPTIM1_OUT,

UCPD1_FRSTX, COMP1_OUT, USART5_TX,

LPUART2_CTS

TIM14_CH1, TIM3_CH4, TIM1_CH3N, FDCAN2_TX,

USART3_RTS_DE_CK, LPTIM2_IN1,

LPUART1_RTS_DE, COMP3_OUT, USART5_RX,

LPUART2_RTS_DE

SPI2_MISO/I2S2_MCK, MCO2, USART3_TX,

LPTIM1_OUT, EVENTOUT

LPUART1_RTS_DE

LPUART1_CTS, USART5_CTS

TIM1_ETR, USART5_RTS_DE_CK

USART4_TX, TIM1_CH1N

USART4_RX, TIM1_CH1

TIM1_CH2N, USART5_TX

TIM1_CH2, USART5_RX

SPI1_NSS/I2S1_WS, TIM1_CH3N

SPI1_SCK/I2S1_CK, TIM1_CH3

SPI1_MISO/I2S1_MCK, TIM1_CH4, TIM1_BKIN2

SPI1_MOSI/I2S1_SD, TIM1_BKIN

COMP3_INP0, ADC_IN8

COMP1_INM6, ADC_IN9

COMP1_INP1,

COMP3_INM6, ADC_IN10

COMP3_INP2

COMP3_INM8

Pin number

Table 12. Pin assignment and description (continued)

Pin name

Alternate functions

Additional functions

22 22 H3 30 30 G6 36 49 M11

23 23 F5 31 31 H8 37 50 L11

PB10

PB11

24 24 E6 32 32 G7 38 51 K10 PB12

25 25 H1 33 33 G8 39 52 M12 PB13

K11

J10

L12

H10

20 30 D5 38 38 E7 44 57 J11

31 D3 39 39 E5 45 58 K12

PB15

PA8

PA9

PC6

PC7

PB14

I/O

FT_fa

FT_fs

I/O FT_fcs

(3)

I/O

FT_fcs

FT_fds

FT_s

CEC, LPUART1_RX, TIM2_CH3, USART3_TX,

SPI2_SCK/I2S2_CK, I2C2_SCL, COMP1_OUT

SPI2_MOSI/I2S2_SD, LPUART1_TX, TIM2_CH4,

USART3_RX, I2C2_SDA, COMP2_OUT

SPI2_NSS/I2S2_WS, LPUART1_RTS_DE,

TIM1_BKIN, FDCAN2_RX, TIM15_BKIN,

UCPD2_FRSTX, EVENTOUT, I2C2_SMBA

SPI2_SCK/I2S2_CK, LPUART1_CTS, TIM1_CH1N,

FDCAN2_TX, USART3_CTS, TIM15_CH1N,

I2C2_SCL, EVENTOUT

ADC_IN11

ADC_IN15

ADC_IN16

SPI2_MISO/I2S2_MCK, UCPD1_FRSTX,

TIM1_CH2N, USART3_RTS_DE_CK, TIM15_CH1,

I2C2_SDA, EVENTOUT, USART6_RTS_DE_CK

SPI2_MOSI/I2S2_SD, TIM1_CH3N, TIM15_CH1N,

TIM15_CH2, EVENTOUT, USART6_CTS

MCO, SPI2_NSS/I2S2_WS, TIM1_CH1,

CRS1_SYNC, LPTIM2_OUT, EVENTOUT,

I2C2_SMBA

MCO, USART1_TX, TIM1_CH2,

SPI2_MISO/I2S2_MCK, TIM15_BKIN, I2C1_SCL,

EVENTOUT, I2C2_SCL

UCPD1_FRSTX, TIM3_CH1, TIM2_CH3,

LPUART2_TX

UCPD2_FRSTX, TIM3_CH2, TIM2_CH4,

LPUART2_RX

UCPD1_CC2, RTC_REFIN

UCPD1_CC1

UCPD1_DBCC1

Pin number

Table 12. Pin assignment and description (continued)

Pin name

Alternate functions

Additional functions

30 E2 40 E8 50 63 G12

20 31 D1 41 D8 51 64 F12

52 65 F11

53 66 E12

54 67 E11

J12

H11

H12

G11

D11

E10

D12

C12

D10

PD8

PD9

PD10

PD11

VSS

VDDIO2

PD12

PD13

PD14

PD15

PA10

PA11 [PA9]

PA12 [PA10]

PF8

I/O

FT_s

I/O FT_s

I/O FT_fds

I/O

FT_fs

FT_s

(4)

USART3_TX, SPI1_SCK/I2S1_CK, LPTIM1_OUT

USART3_RX, SPI1_NSS/I2S1_WS, TIM1_BKIN2

MCO

USART3_CTS, LPTIM2_ETR

USART3_RTS_DE_CK, LPTIM2_IN1, TIM4_CH1,

FDCAN1_RX

LPTIM2_OUT, TIM4_CH2, FDCAN1_TX

LPUART2_CTS, TIM4_CH3, FDCAN2_RX

CRS1_SYNC, LPUART2_RTS_DE, TIM4_CH4,

FDCAN2_TX

SPI2_MOSI/I2S2_SD, USART1_RX, TIM1_CH3,

MCO2, TIM17_BKIN, I2C1_SDA, EVENTOUT,

I2C2_SDA

SPI1_MISO/I2S1_MCK, USART1_CTS, TIM1_CH4,

FDCAN1_RX, TIM1_BKIN2, I2C2_SCL,

COMP1_OUT

SPI1_MOSI/I2S1_SD, USART1_RTS_DE_CK,

TIM1_ETR, FDCAN1_TX, I2S_CKIN, I2C2_SDA,

COMP2_OUT

UCPD1_DBCC2

USB_DM

USB_DP

Pin number

Table 12. Pin assignment and description (continued)

Pin name

Alternate functions

Additional functions

24 24 35 35 B3 45 45 D7 59 73 C11 PA13 I/O FT_es

25 25 36 36 B5 46 46 C7 60 74 B12 PA14-BOOT0 I/O FT_s

B11

C10

A12

B10

A11

A10

PA15

PC8

PC9

PD0

PD1

PD2

PD3

PD4

PD5

PD6

I/O

FT_s

I/O FT_ds

I/O

FT_cs

FT_ds

FT_s

(5)

1. Refer to Table 22 for the maximum allowed injected current values.

SWDIO, IR_OUT, USB_NOE, EVENTOUT,

LPUART2_RX

SWCLK, USART2_TX, EVENTOUT, LPUART2_TX

SPI1_NSS/I2S1_WS, USART2_RX,

TIM2_CH1_ETR, MCO2, USART4_RTS_DE_CK,

USART3_RTS_DE_CK, USB_NOE, EVENTOUT,

I2C2_SMBA, SPI3_NSS

UCPD2_FRSTX, TIM3_CH3, TIM1_CH1,

LPUART2_CTS

I2S_CKIN, TIM3_CH4, TIM1_CH2,

LPUART2_RTS_DE, USB_NOE

EVENTOUT, SPI2_NSS/I2S2_WS, TIM16_CH1,

FDCAN1_RX

EVENTOUT, SPI2_SCK/I2S2_CK, TIM17_CH1,

FDCAN1_TX

USART3_RTS_DE_CK, TIM3_ETR, TIM1_CH1N,

USART5_RX

USART2_CTS, SPI2_MISO/I2S2_MCK,

TIM1_CH2N, USART5_TX

USART2_RTS_DE_CK, SPI2_MOSI/I2S2_SD,

TIM1_CH3N, USART5_RTS_DE_CK

USART2_TX, SPI1_MISO/I2S1_MCK, TIM1_BKIN,

USART5_CTS

USART2_RX, SPI1_MOSI/I2S1_SD, LPTIM2_OUT

BOOT0

UCPD2_CC1

UCPD2_DBCC1

UCPD2_CC2

UCPD2_DBCC2

Pin number

Table 12. Pin assignment and description (continued)

Pin name

Alternate functions

Additional functions

71 85 B8

86 A8

29 44 44 A10 59 59 D4 74 93 C5

75 94 A4

76 95 B4

96 A3

77 97 A2

PB5

PE0

PE1

PE2

PE3

PD7

PF9

PF10

PF11

PF12

PF13

PB3

PB4

I/O FT_a

I/O

MCO2

USART6_TX

USART6_RX

USART6_RTS_DE_CK

TIM15_CH1, USART6_CTS

TIM15_CH2

SPI1_SCK/I2S1_CK, TIM1_CH2, TIM2_CH2,

USART5_TX, USART1_RTS_DE_CK, I2C3_SCL,

EVENTOUT, I2C2_SCL, SPI3_SCK

SPI1_MISO/I2S1_MCK, TIM3_CH1, USART5_RX,

USART1_CTS, TIM17_BKIN, I2C3_SDA,

EVENTOUT, I2C2_SDA, SPI3_MISO

SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM16_BKIN,

FDCAN2_RX, LPTIM1_IN1, I2C1_SMBA,

COMP2_OUT, USART5_RTS_DE_CK, SPI3_MOSI

TIM16_CH1, EVENTOUT, TIM4_ETR

TIM17_CH1, EVENTOUT

TIM3_ETR

TIM3_CH1

COMP2_INM6

COMP2_INP0

WKUP6

Pin number

Table 12. Pin assignment and description (continued)

Pin name

Alternate functions

Additional functions

PB6

PB7

I/O

FT_fa

USART1_TX, TIM1_CH3, TIM16_CH1N,

FDCAN2_TX, SPI2_MISO/I2S2_MCK, LPTIM1_ETR,

I2C1_SCL, EVENTOUT, USART5_CTS, TIM4_CH1,

LPUART2_TX

USART1_RX, SPI2_MOSI/I2S2_SD, TIM17_CH1N,

USART4_CTS, LPTIM1_IN2, I2C1_SDA,

EVENTOUT, TIM4_CH2, LPUART2_RX

COMP2_INP1

COMP2_INM7, PVD_IN

32 32 47 47 A12 62 62 B3 80 100 A1 PB8 I/O FT_f -

CEC, SPI2_SCK/I2S2_CK, TIM16_CH1,

FDCAN1_RX, USART3_TX, TIM15_BKIN,

I2C1_SCL, EVENTOUT, USART6_TX, TIM4_CH3

1 1 48 48 D9 63 63 C3 1 1 C3 PB9 I/O FT_f -

IR_OUT, UCPD2_FRSTX, TIM17_CH1,

FDCAN1_TX, USART3_RX, SPI2_NSS/I2S2_WS,

I2C1_SDA, EVENTOUT, USART6_RX, TIM4_CH4

1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:

- The speed should not exceed 2 MHz with a maximum load of 30 pF

- These GPIOs must not be used as current sources (for example to drive a LED).

2. After an RTC domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers. The RTC registers are not reset upon system reset. For details on how to manage these GPIOs, refer to the RTC domain and RTC register descriptions in the RM0444 reference manual.

3. Upon reset, a pull-down resistor might be present on PA8, PB15, PD0, or PD2 depending on voltage level on PA9, PA10, PD1, and PD3, respectively. In order to disable this resistor, strobe the UCPDx_STROBE bit in SYSCFG_CFGR1 register during start-up sequence.

4. Pins PA9/PA10 can be remapped in place of pins PA11/PA12 (default mapping), using SYSCFG_CFGR1 register.

5. Upon reset, these pins are configured as SW debug alternate functions, and the internal pull-up on PA13 pin and the internal pull-down on PA14 pin are activated.

Port

PA0

PA5

PA6

PA7

PA8

PA1

PA2

PA3

PA4

PA9

PA10

PA11

PA12

PA13

PA14

PA15

AF0

SPI2_SCK/

I2S2_CK

SPI1_SCK/

I2S1_CK

SPI1_MOSI/

I2S1_SD

SPI2_MISO/

I2S2_MCK

SPI1_NSS/

I2S1_WS

SPI1_SCK/

I2S1_CK

SPI1_MISO/

I2S1_MCK

SPI1_MOSI/

I2S1_SD

MCO

SPI2_MOSI/

I2S2_SD

SPI1_MISO/

I2S1_MCK

SPI1_MOSI/

I2S1_SD

SWDIO

SWCLK

SPI1_NSS/

I2S1_WS

AF1

USART2_CTS

USART2_RTS

_DE_CK

USART2_TX

Table 13. Port A alternate function mapping (AF0 to AF7)

AF2 AF3 AF4 AF5

TIM2_CH1_ETR

TIM2_CH2

TIM2_CH3 -

USART4_TX

USART4_RX

UCPD1_FRSTX

LPTIM1_OUT

TIM15_CH1N

TIM15_CH1

USART2_RX

SPI2_MOSI/

I2S2_SD

CEC

TIM3_CH1

TIM3_CH2

SPI2_NSS/

I2S2_WS

USART1_TX

USART1_RX

TIM2_CH4

USB_NOE

TIM2_CH1_ETR

TIM1_BKIN

TIM1_CH1N

TIM1_CH1

USART6_RX

USART6_CTS

USART6_RTS

_DE_CK

TIM1_CH2

TIM1_CH3

USART1_CTS

USART1_RTS

_DE_CK

IR_OUT

USART2_TX

USART2_RX

TIM1_CH4

TIM1_ETR

USB_NOE

TIM2_CH1_ETR

USART6_TX

MCO2

FDCAN1_RX

FDCAN1_TX

MCO2

UCPD2_FRSTX

TIM14_CH1

TIM15_CH2

LPTIM2_OUT

USART3_TX

USART3_CTS

TIM14_CH1

CRS1_SYNC

SPI2_MISO/

I2S2_MCK

USART4_RTS

_DE_CK

LPTIM2_ETR

TIM16_CH1

TIM17_CH1

LPTIM2_OUT

TIM15_BKIN

TIM17_BKIN

TIM1_BKIN2

I2S_CKIN

USART3_RTS

_DE_CK

AF6

UCPD2_FRSTX

I2C1_SMBA

LPUART1_TX

LPUART1_RX

UCPD2_FRSTX

AF7

COMP1_OUT

EVENTOUT

COMP2_OUT

EVENTOUT

UCPD1_FRSTX

LPUART1_CTS

EVENTOUT

COMP1_OUT

UCPD1_FRSTX

COMP2_OUT

EVENTOUT

I2C1_SCL

I2C1_SDA

I2C2_SCL

I2C2_SDA

USB_NOE

EVENTOUT

COMP1_OUT

COMP2_OUT

EVENTOUT

Port

PA5

PA6

PA7

PA8

PA9

PA10

PA11

PA12

PA0

PA1

PA2

PA3

PA4

PA13

PA14

PA15

AF8

I2C2_SDA

I2C2_SCL

I2C2_SMBA

I2C2_SCL

I2C2_SDA

I2C2_SMBA

AF9

SPI3_NSS

I2C3_SDA

I2C3_SCL

SPI3_NSS

Table 14. Port A alternate function mapping (AF8 to AF15)

AF10 AF11 AF12 AF13

LPUART2_RX

LPUART2_TX

AF14

AF15

Port

PB0

PB5

PB6

PB7

PB8

PB1

PB2

PB3

PB4

PB9

PB10

PB11

PB12

PB13

USART1_RX

CEC

IR_OUT

CEC

SPI2_MOSI/

I2S2_SD

SPI2_NSS/

I2S2_WS

SPI2_SCK/

I2S2_CK

AF0

SPI1_NSS/

I2S1_WS

TIM14_CH1

SPI1_SCK/

I2S1_CK

SPI1_MISO/

I2S1_MCK

SPI1_MOSI/

I2S1_SD

USART1_TX

AF1

TIM3_CH3

TIM3_CH4

SPI2_MISO/

I2S2_MCK

TIM1_CH2

TIM3_CH1

Table 15. Port B alternate function mapping (AF0 to AF7)

AF2 AF3 AF4 AF5

TIM1_CH2N FDCAN2_RX LPTIM1_OUT

TIM1_CH3N

TIM2_CH2

FDCAN2_TX

MCO2

USART5_TX

USART5_RX

USART3_RX

USART3_RTS

_DE_CK

USART3_TX

USART1_RTS

_DE_CK

USART1_CTS

LPTIM2_IN1

LPTIM1_OUT

TIM17_BKIN

TIM3_CH2

TIM1_CH3

SPI2_MOSI/

I2S2_SD

SPI2_SCK/

I2S2_CK

UCPD2_FRSTX

LPUART1_RX

LPUART1_TX

LPUART1_RTS

_DE

LPUART1_CTS

TIM16_BKIN

TIM16_CH1N

TIM17_CH1N

TIM16_CH1

TIM17_CH1

TIM2_CH3

TIM2_CH4

TIM1_BKIN

TIM1_CH1N

FDCAN2_RX

FDCAN2_TX

FDCAN1_RX

FDCAN1_TX

FDCAN2_RX

FDCAN2_TX

SPI2_MISO/

I2S2_MCK

USART4_CTS

USART3_TX

USART3_RX

USART3_TX

USART3_RX

USART3_CTS

LPTIM1_IN1

LPTIM1_ETR

LPTIM1_IN2

TIM15_BKIN

SPI2_NSS/

I2S2_WS

SPI2_SCK/

I2S2_CK

TIM15_BKIN

TIM15_CH1N

AF6

UCPD1_FRSTX

LPUART1_RTS

_DE

AF7

COMP1_OUT

I2C3_SCL

I2C3_SDA

I2C1_SMBA

I2C1_SCL

I2C1_SDA

I2C1_SCL

I2C1_SDA

I2C2_SCL

I2C2_SDA

UCPD2_FRSTX

I2C2_SCL

EVENTOUT

COMP1_OUT

COMP2_OUT

EVENTOUT

COMP3_OUT

EVENTOUT

COMP2_OUT

EVENTOUT

Port

PB14

PB15

AF0

SPI2_MISO/

I2S2_MCK

SPI2_MOSI/

I2S2_SD

AF1

Table 15. Port B alternate function mapping (AF0 to AF7) (continued)

AF2 AF3 AF4 AF5

UCPD1_FRSTX TIM1_CH2N -

USART3_RTS

_DE_CK

TIM15_CH1

TIM1_CH3N TIM15_CH1N TIM15_CH2

AF6

I2C2_SDA

Port

PB0

PB5

PB6

PB7

PB8

PB9

PB10

PB11

PB12

PB13

PB14

PB15

PB1

PB2

PB3

PB4

AF8

USART5_TX

USART5_RX

I2C2_SCL

I2C2_SDA

USART5_RTS

_DE_CK

USART5_CTS

USART6_TX

USART6_RX

I2C2_SMBA

USART6_RTS

_DE_CK

USART6_CTS

AF9

SPI3_SCK

SPI3_MISO

Table 16. Port B alternate function mapping (AF8 to AF15)

AF10 AF11 AF12 AF13

LPUART2_CTS

LPUART2_RTS

_DE

SPI3_MOSI

TIM4_CH1

TIM4_CH2

TIM4_CH3

TIM4_CH4

LPUART2_TX

LPUART2_RX

AF14

AF7

EVENTOUT

AF15

Port

PC0

PC1

PC2

AF0

LPTIM1_IN1

LPTIM1_OUT

LPTIM1_IN2

PC9

PC10

PC11

PC12

PC13

PC14

PC15

PC3 LPTIM1_ETR

PC4 USART3_TX

PC5 USART3_RX

PC6 UCPD1_FRSTX

PC7 UCPD2_FRSTX

PC8 UCPD2_FRSTX

I2S_CKIN

USART3_TX

USART3_RX

LPTIM1_IN1

OSC32_EN

AF1

LPUART1_RX

LPUART1_TX

SPI2_MISO/

I2S2_MCK

SPI2_MOSI/

I2S2_SD

USART1_TX

USART1_RX

TIM3_CH1

TIM3_CH2

TIM3_CH3

TIM3_CH4

USART4_TX

USART4_RX

UCPD1_FRSTX

OSC_EN

Table 17. Port C alternate function mapping

AF2

LPTIM2_IN1

TIM15_CH1

TIM15_CH2

AF3

LPUART2_TX

LPUART2_RX

FDCAN2_RX

LPTIM2_ETR FDCAN2_TX

TIM2_CH1_ETR

TIM2_CH2

TIM2_CH3

TIM2_CH4

TIM1_CH1

TIM1_CH2

TIM1_CH3

TIM1_CH4

TIM14_CH1

TIM1_BKIN

TIM1_BKIN2

TIM15_BKIN

FDCAN1_RX

FDCAN1_TX

LPUART2_TX

LPUART2_RX

LPUART2_CTS

LPUART2_RTS_

USART5_TX

AF4

USART6_TX

USART6_RX

SPI3_SCK

SPI3_MISO

SPI3_MOSI

AF5

AF6

I2C3_SCL

I2C3_SDA

USB_NOE

AF7

COMP3_OUT

Port

PD0

AF0

EVENTOUT

PD1

PD2

PD3

PD4

PD5

EVENTOUT

USART3_RTS

_DE_CK

USART2_CTS

USART2_RTS

_DE_CK

USART2_TX

PD6

PD7

PD8

USART2_RX

USART3_TX

PD9

PD10

PD11

PD12

PD13

PD14

PD15

USART3_RX

MCO

USART3_CTS

USART3_RTS

_DE_CK

CRS1_SYNC

AF1

SPI2_NSS/

I2S2_WS

SPI2_SCK/

I2S2_CK

TIM3_ETR

SPI2_MISO/

I2S2_MCK

SPI2_MOSI/

I2S2_SD

SPI1_MISO/

I2S1_MCK

SPI1_MOSI/

I2S1_SD

SPI1_SCK/

I2S1_CK

SPI1_NSS/

I2S1_WS

LPTIM2_ETR

LPTIM2_IN1

LPTIM2_OUT

LPUART2_CTS

LPUART2_RTS

_DE

TIM17_CH1

TIM1_CH1N

TIM1_CH2N

TIM1_CH3N

TIM1_BKIN

LPTIM2_OUT

LPTIM1_OUT

TIM1_BKIN2

TIM4_CH1

TIM4_CH2

TIM4_CH3

TIM4_CH4

Table 18. Port D alternate function mapping

AF2 AF3 AF4

TIM16_CH1 FDCAN1_RX -

AF5

FDCAN1_TX

USART5_RX

USART5_TX

USART5_RTS

_DE_CK

USART5_CTS

MCO2

FDCAN1_RX

FDCAN1_TX

FDCAN2_RX

FDCAN2_TX

AF6

AF7

Port

PE0

PE1

PE2

PE3

PE4

PE5

PE6

AF0

TIM16_CH1

TIM17_CH1

PE7 -

PE8

PE9

PE10

PE11

PE12

PE13

PE14

PE15

USART4_TX

USART4_RX

SPI1_NSS/

I2S1_WS

SPI1_SCK/

I2S1_CK

SPI1_MISO/I2S1

_MCK

SPI1_MOSI/I2S1

_SD

AF1

EVENTOUT

TIM3_ETR

TIM3_CH1

TIM3_CH2

TIM3_CH3

TIM3_CH4

TIM1_ETR

TIM1_CH1N

TIM1_CH1

TIM1_CH2N

TIM1_CH2

TIM1_CH3N

TIM1_CH3 -

TIM1_CH4 TIM1_BK2

TIM1_BK -

Table 19. Port E alternate function mapping

AF2 AF3 AF4

TIM4_ETR

USART5_RTS_D

E_CK

USART5_TX

USART5_RX

AF5

AF6

AF7

Port

PF0

PF1

PF2

PF3

PF4

PF5

PF6

PF7

PF8

PF9

PF10

PF11

PF12

PF13

AF0

CRS1_SYNC

OSC_EN

MCO

TIM15_CH1

TIM15_CH2

AF1

EVENTOUT

LPUART2_TX

LPUART2_RX

LPUART1_TX

LPUART1_RX

LPUART1_RTS

_DE

LPUART1_CTS

Table 20. Port F alternate function mapping

AF2 AF3 AF4

TIM14_CH1

TIM15_CH1N

LPUART2_RTS

_DE

USART6_RTS

_DE_CK

USART5_CTS

USART6_TX

USART6_RX

USART6_RTS

_DE_CK

USART6_CTS

AF5

AF6

AF7

Electrical characteristics STM32G0B1xB/xC/xE

5.1.1

Unless otherwise specified, all voltages are referenced to V

Parameter values defined at temperatures or in temperature ranges out of the ordering information scope are to be ignored.

Packages used for characterizing certain electrical parameters may differ from the commercial packages as per the ordering information.

Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T

A the selected temperature range).

= 25 °C and T

= T

(max) (given by

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ±3 σ ).

Unless otherwise specified, typical data are based on T

= 25 °C, V

V. They are given only as design guidelines and are not tested.

= V

DDA

= V

DDIO2

= 3

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ±2 σ )

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

5.1.5

The loading conditions used for pin parameter measurement are shown in

Figure 13

Pin input voltage

The input voltage measurement on a pin of the device is described in

Figure 14 .

Figure 13. Pin loading conditions Figure 14. Pin input voltage

MCU pin

C = 50 pF

64/159

DS13560 Rev 3

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5.1.6 Power supply scheme

Figure 15. Power supply scheme

Electrical characteristics

VBAT

1.55 V to 3.6 V

1 x 100 nF

+ 1 x 4.7 μF

VDD/VDDA

GPIOs

DDIO2

VDDIO2

GPIOs

100 nF

+4.7 μF

REF VREF+

100 nF 1 μF

VSS/VSSA

Power switch

Backup circuitry

(LSE, RTC and backup registers)

CORE

Regulator

DDIO1

OUT

IO logic

Kernel logic

(CPU, digital and memories)

DDIO2

OUT

DDA

REF+

REF-

SSA

ADC

DAC

COMPs

VREFBUF

IO logic

MSv66839V2

Caution: Power supply pin pair (VDD/VDDA/VDDIO2 and VSS/VSSA) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device.

DS13560 Rev 3

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124

Electrical characteristics STM32G0B1xB/xC/xE

Figure 16. Current consumption measurement scheme

BAT

DDA

)

DDVBAT

VBAT

VDD/VDDA

VDDIO2

MSv66840V1

5.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in

Table 21 ,

Table 22 and Table 23

may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

All voltages are defined with respect to V

Symbol

Table 21. Voltage characteristics

Ratings Min Max

DDIO2

BAT

REF+

(1)

External supply voltage

External supply voltage for selected I/Os

External supply voltage on VBAT pin

External voltage on VREF+ pin

Input voltage on FT_xx pins except FT_c

Input voltage on FT_c pins

Input voltage on any other pin

- 0.3

2. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.

4.0

Min(V

+ 0.4, 4.0)

+ 4.0

(2)

5.5

4.0

Unit

66/159

DS13560 Rev 3

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Symbol

Table 22. Current characteristics

Ratings Max Unit

VDD/VDDA

/VDDIO2

VSS/VSSA

Current into VDD/VDDA/VDDIO2 power pin (source)

Current out of VSS/VSSA ground pin (sink)

Section 6.11: Thermal characteristics

Output current sunk by any I/O and control pin except FT_f

100

IO(PIN)

Output current sunk by any FT_f pin 20

Output current sourced by any I/O and control pin 15

Total output current sunk by sum of all I/Os and control pins 80

∑ I

IO(PIN)

Total output current sourced by sum of all I/Os and control pins

INJ(PIN)

(2)

Injected current on a FT_xx pin

Injected current on a TT_a pin (4)

∑ |I

INJ(PIN)

| Total injected current (sum of all I/Os and control pins)

(5)

-5 / NA

-5 / 0

(3)

1. All main power (VDD/VDDA/VDDIO2, VBAT) and ground (VSS/VSSA) pins must always be connected to the external power supplies, in the permitted range.

2. A positive injection is induced by V

exceeded. Refer also to

> V

DDIOx

while a negative injection is induced by V < V

. I

INJ(PIN)

must never be

3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.

4. On these I/Os, any current injection disturbs the analog performances of the device.

5. When several inputs are submitted to a current injection, the maximum ∑ |I injected currents (instantaneous values).

INJ(PIN)

| is the absolute sum of the negative mA

Symbol

STG

Table 23. Thermal characteristics

Ratings

Storage temperature range

Maximum junction temperature

Value

–65 to +150

150

Unit

°C

5.3.1 General operating conditions

Symbol f

HCLK f

PCLK

DDIO2

Parameter

Table 24. General operating conditions

Conditions Min

Internal AHB clock frequency

Internal APB clock frequency

Standard operating voltage

External supply voltage for selected I/Os

1.7

(1)

1.7

Max

3.6

Unit

MHz

DS13560 Rev 3

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124

Electrical characteristics STM32G0B1xB/xC/xE

Symbol

Table 24. General operating conditions (continued)

Parameter Conditions Min Max Unit

DDA

BAT

Backup operating voltage

I/O input voltage

Ambient temperature

Junction temperature

(3)

For ADC and COMP operation

For DAC operation

For VREFBUF operation

1.62

1.8

2.4

1.55

All except TT_xx and FT_c -0.3

TT_xx

FT_c

Suffix 6

(4)

Suffix 7

(4)

Suffix 3

(4)

Suffix 6

(4)

Suffix 7

(4)

Suffix 3 (4)

-0.3

-40

3.6

Min(V

+ 3.6, 5.5)

(2)

+ 0.3

5.0

(2)

105

125

105

125

130

°C

1. When RESET is released functionality is guaranteed down to V

PDR

min.

2. For operation with voltage higher than V

+0.3 V, the internal pull-up and pull-down resistors must be disabled.

3. The T

(max) applies to P

(max). At P

< P

(max) the ambient temperature is allowed to go higher than T

does not exceed T

(max). Refer to

(max) provided

4. Temperature range digit in the order code. See

Section 7: Ordering information

The parameters given in

Table 25 are derived from tests performed under the ambient

temperature condition summarized in

Table 24 .

Symbol t

VDD

Table 25. Operating conditions at power-up / power-down

Parameter Conditions Min Max

slew rate

rising

falling; ULPEN = 0

falling; ULPEN = 1

100

∞

Unit

µs/V ms/V

5.3.3 Embedded reset and power control block characteristics

The parameters given in

Table 26 are derived from tests performed under the ambient

temperature conditions summarized in Table 24: General operating conditions

Symbol t

RSTTEMPO

(2)

POR

(2)

Table 26. Embedded reset and power control block characteristics

Parameter Conditions

(1)

Min Typ Max Unit

POR temporization when V

crosses V

POR

Power-on reset threshold

DD rising

250 400

1.62

1.66

1.70

μ s

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DS13560 Rev 3

STM32G0B1xB/xC/xE Electrical characteristics

Table 26. Embedded reset and power control block characteristics (continued)

Symbol Parameter Conditions (1) Min Typ Max Unit

PDR

(2)

BOR1

BOR2

BOR3

BOR4

PVD0

PVD1

PVD2

PVD3

PVD4

PVD5

PVD6

Power-down reset threshold

Brownout reset threshold 1

Brownout reset threshold 2

Brownout reset threshold 3

Brownout reset threshold 4

Programmable voltage detector threshold 0

PVD threshold 1

PVD threshold 2

PVD threshold 3

PVD threshold 4

PVD threshold 5

PVD threshold 6

DD rising

DD falling

DD rising

DD falling

DD rising

DD falling

DD rising

DD falling

DD rising

DD falling

DD rising

DD falling

DD rising

DD falling

DD rising

DD falling

DD rising

DD falling

DD rising

DD falling

DD rising

DD falling

Hysteresis in continuous mode

1.60

2.05

1.95

2.20

2.10

2.50

2.40

2.80

2.70

2.05

1.95

2.20

2.10

2.35

2.25

2.50

2.40

2.65

2.55

2.80

2.70

2.90

2.80

1.64

2.10

2.00

2.31

2.21

2.62

2.52

2.91

2.81

2.15

2.05

2.30

2.20

2.46

2.36

2.62

2.52

2.74

2.64

2.91

2.81

3.01

2.91

1.69

2.18

2.08

2.38

2.28

2.68

2.58

3.00

2.90

2.22

2.12

2.37

2.27

2.54

2.44

2.70

2.60

2.87

2.77

3.03

2.93

3.14

3.04

V hyst_POR_PDR

Hysteresis of V

POR

and V

PDR mV

Hysteresis in other mode

30 -

V hyst_BOR_PVD

DD(BOR_PVD)

(2)

Hysteresis of V

BORx

and V

PVDx

BOR and PVD consumption -

100

1.1

1.6

1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes.

2. Guaranteed by design.

µA

DS13560 Rev 3

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124

Electrical characteristics STM32G0B1xB/xC/xE

The parameters given in

Table 27 are derived from tests performed under the ambient

temperature and supply voltage conditions summarized in Table 24: General operating conditions

Symbol

Table 27. Embedded internal voltage reference

Parameter Conditions Min Typ Max t

REFINT

S_vrefint

(1)

Internal reference voltage

ADC sampling time when reading the internal reference voltage t start_vrefint

DD(VREFINTBUF)

∆ V

REFINT

Start time of reference voltage buffer when ADC is enable

REFINT

buffer consumption from

when converted by ADC

Internal reference voltage spread over the temperature range

-40°C < T

< 130°C

= 3 V

Coeff_vrefint

Coeff

DDCoeff

REFINT_DIV1

REFINT_DIV2

REFINT_DIV3

Temperature coefficient

Long term stability

Voltage coefficient

1/4 reference voltage

1/2 reference voltage

3/4 reference voltage

1000 hours, T = 25 °C

3.0 V < V

< 3.6 V

1. The shortest sampling time can be determined in the application by multiple iterations.

2. Guaranteed by design.

1.182 1.212

1.232

(2)

12.5

7.5

(2)

300 1000 (2)

250 1200

(2)

Unit

µs

µA mV ppm/°C ppm ppm/V

REFINT

Figure 17. V

REFINT

vs. temperature

1.235

1.23

1.225

1.22

1.215

1.21

1.205

1.2

1.195

1.19

1.185

-40 -20 0 20

Mean

Min

Max

80 100 120 °C

MSv40169V1

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5.3.5 Supply current characteristics

Electrical characteristics

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code.

The current consumption is measured as described in

Figure 16: Current consumption measurement scheme

Typical and maximum current consumption

The MCU is placed under the following conditions:

• All I/O pins are in analog input mode

• All peripherals are disabled except when explicitly mentioned

• The Flash memory access time is adjusted with the minimum wait states number, depending on the f

HCLK

frequency (refer to the table “Number of wait states according to CPU clock (HCLK) frequency” available in the RM0444 reference manual).

• When the peripherals are enabled f

PCLK

= f

HCLK

• For Flash memory and shared peripherals f

PCLK

= f

HCLK

= f

HCLKS

Unless otherwise stated, values given in

Table 28 through

Table 36 are derived from tests

performed under ambient temperature and supply voltage conditions summarized in

DS13560 Rev 3

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124

Electrical characteristics STM32G0B1xB/xC/xE

Table 28. Current consumption in Run and Low-power run modes

at different die temperatures

Conditions Typ Max

(1)

Symbol Parameter

General f

HCLK

64 MHz

Fetch from

(2)

°C

125

°C

130

°C

8.6

8.8

9.4

9.0

9.1

9.7

DD(Run)

DD(LPRun)

Supply current in

Run mode

(from Flash memory)

Range 1;

PLL enabled; f

HCLK

= f

HSE_bypass f

( ≤ 16 MHz),

HCLK

= f

PLLRCLK

(>16 MHz);

(3)

56 MHz

48 MHz

32 MHz

24 MHz

16 MHz

64 MHz

56 MHz

48 MHz

32 MHz

Range 2;

PLL enabled; f

HCLK

= f

HSE_bypass f

( ≤ 16 MHz),

HCLK

= f

PLLRCLK

(>16 MHz);

(3)

24 MHz

16 MHz

8 MHz

2 MHz

16 MHz

8 MHz

2 MHz

1 MHz

500 kHz

Supply current in

Low-power run mode f

PLL disabled;

HCLK

= f

HSE bypass (> 32 kHz), f

HCLK

= f

LSE bypass (= 32 kHz);

(3)

125 kHz

32 kHz

2 MHz

1 MHz

500 kHz

125 kHz

32 kHz

Flash memory

SRAM

Flash memory

SRAM

Flash memory

SRAM

7.5

7.8

8.3

7.9

8.0

8.6

6.7

7.0

7.6

7.1

7.2

7.8

4.6

4.8

5.4

4.8

5.0

5.5

3.6

3.8

4.3

3.8

4.1

4.6

2.3

2.5

3.0

2.4

2.6

3.2

8.8

8.9

9.4

9.3

9.4

9.9

7.7

7.8

8.3

8.2

8.3

8.8

6.9

7.0

7.5

7.3

7.4

7.9

4.7

4.8

5.3

5.0

5.1

5.6

3.6

3.8

4.3

4.1

4.2

4.7

2.3

2.4

2.9

2.5

2.6

3.2

1.8

2.0

2.4

2.2

2.3

2.9

1.0

1.1

1.6

1.3

1.4

2.1

0.3

0.4

0.9

0.6

0.9

1.4

1.9

2.0

2.5

2.3

2.4

3.0

1.0

1.1

1.6

1.3

1.5

2.1

0.3

0.4

0.9

0.6

0.9

1.4

280 415 950 585 845 1515

155 285 820 530 835 1315

90 220 750 475 795 1220

45 170 700 445 745 1190

30 155 695 430 720 1185

250 360 855 575 835 1495

140 260 730 530 825 1300

80 205 650 475 780 1230

40 155 635 440 745 1200

30 135 625 415 715 1180

Unit

1. Based on characterization results, not tested in production.

2. Prefetch and cache enabled when fetching from Flash memory. Code compiled with high optimization for space in SRAM.

3. V

= 3.0 V for values in Typ columns and 3.6 V for values in Max columns, all peripherals disabled.

µA

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Table 29. Typical current consumption in Run and Low-power run modes, depending on code executed

Conditions Typ Typ

Symbol Parameter Unit

General Code

Fetch from (1)

25 °C 25 °C

DD(Run)

DD(LPRun)

Supply current in

Run mode f

Range 1;

HCLK

= f

64 MHz;

(2)

PLLRCLK

= f

Range 2;

HCLK

= f

16 MHz,

PLL disabled,

(2)

HSI16

Supply current in

Low-power run mode f

HCLK

= f

HSI16

/8 =

2 MHz;

PLL disabled,

(2)

Reduced code

(3)

Coremark

Dhrystone 2.1

Fibonacci

While(1) loop

Reduced code

Coremark

Dhrystone 2.1

Fibonacci

While(1) loop

Reduced code

Coremark

Dhrystone 2.1

Fibonacci

While(1) loop

Reduced code

Coremark

Dhrystone 2.1

Fibonacci

While(1) loop

Reduced code

Coremark

Dhrystone 2.1

Fibonacci

While(1) loop

Reduced code

3. Reduced code used for characterization results provided in Table 28 .

Coremark

Dhrystone 2.1

Fibonacci

While(1) loop

Flash memory

SRAM

Flash memory

SRAM

Flash memory

SRAM mA

μ A

500

515

490

485

480

510

480

2.05

485

475

480

2.10

2.05

2.25

1.90

1.70

1.35

8.95

9.85

8.85

2.45

8.70

8.15

8.00

7.30

5.90

8.85

9.10

250

258

245

243

240

255

240

128

243

238

240

131

128

141

119

106

140

154

138

153

136

127

125

114

138

142

1. Prefetch and cache enabled when fetching from Flash. Code compiled with high optimization for space in SRAM.

= 3.3 V, all peripherals disabled, cache enabled, prefetch disabled for execution in Flash and enabled in SRAM

Unit

μ A/MHz

DS13560 Rev 3

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Electrical characteristics STM32G0B1xB/xC/xE

Table 30. Current consumption in Sleep and Low-power sleep modes

Conditions Typ Max

(1)

Symbol Parameter

General

Voltage scaling f

HCLK

°C

125

°C

130

°C

64 MHz 1.9

2.0

2.6

2.5

2.6

3.3

DD(Sleep)

DD(LPSleep)

Supply current in

Sleep mode f

Flash memory enabled;

HCLK

= f

HSE

bypass

( ≤ 16 MHz; PLL f disabled),

HCLK

= f

PLLRCLK

(>16 MHz; PLL enabled);

All peripherals disabled

Range 1

Range 2

56 MHz 1.7

1.8

2.4

2.2

2.4

3.2

48 MHz

32 MHz

24 MHz

16 MHz

1.5

1.1

0.9

0.5

1.6

1.2

1.0

0.6

2.2

1.8

1.6

1.2

1.9

1.4

1.2

0.7

2.1

1.6

1.3

0.9

2.8

2.3

2.1

1.6

16 MHz 0.4

0.6

1.0

0.6

0.7

1.4

8 MHz 0.3

0.4

0.9

0.4

0.5

1.2

2 MHz 0.2

0.3

0.7

0.2

0.4

1.0

2 MHz 70 200 705 175 500 1325

Supply current in

Low-power sleep mode f

Flash memory disabled;

PLL disabled;

HCLK f

HCLK

= f

HSE

= f

LSE

bypass (> 32 kHz),

bypass (= 32 kHz);

All peripherals disabled

1 MHz

500 kHz

125 kHz

175

165

155

685

670

665

145 438 1285

130 413 1255

105 388 1250

32 kHz 26 150 660 90 375 1210

1. Based on characterization results, not tested in production.

Unit mA

µA

Table 31. Current consumption in Stop 0 mode

Conditions Typ

Symbol Parameter

DD(Stop 0)

Supply current in

Stop 0 mode

HSI kernel

Enabled

Disabled

1.8 V

2.4 V

3 V

3.6 V

1.8 V

2.4 V

3 V

3.6 V

1. Based on characterization results, not tested in production.

25°C 85°C 125°C 25°C 85°C 130°C

290

295

300

100

105

370

375

380

190

195

200

675

680

695

505

510

525

530

370

375

180

185

Max

(1)

470

475

290

295

305

850

870

930

1050

680

685

695

830

Unit

µA

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Table 32. Current consumption in Stop 1 mode

Conditions Typ

Symbol Parameter

Flash memory

RTC

(2)

DD(Stop 1)

Supply current in

Stop 1 mode

Not powered

Powered

Disabled

Enabled

Disabled

1.8 V

2.4 V

3 V

3.6 V

1.8 V

2.4 V

3 V

3.6 V

1.8 V

2.4 V

3 V

3.6 V

1. Based on characterization results, not tested in production.

2. Clocked by LSI

105

110

105

110

115

3.3

3.6

3.7

4.2

2.9

3.1

3.3

3.6

7.0

7.3

7.5

7.8

Max

(1)

25°C 85°C 125°C 25°C 85°C 130°C

Unit

µA

Symbol

DD(Standby)

Parameter

Table 33. Current consumption in Standby mode

Conditions Typ

General V

1.8 V

Max

(1)

25°C 85°C 125°C 25°C 85°C 130°C

0.1

2.1

9.4

0.8

14 45

Supply current in Standby mode

(2)

RTC disabled

RTC enabled, clocked by LSI;

IWDG enabled, clocked by LSI

ULPEN = 0

2.3

2.6

3.0

2.5

3.0

3.3

2.1

1.2

1.4

1.8

2.0

11.5

13.5

16.0

9.4

11.0

13.5

15.5

11.5

13.5

16.0

9.7

11.5

14.0

16.0

9.6

2.7

3.3

3.8

2.0

2.4

2.9

3.4

2.8

3.4

4.0

2.3

2.5

3.0

3.5

2.3

0.4

0.5

0.7

0.9

1.1

1.3

0.5

0.7

0.9

0.3

0.1

0.2

0.3

0.4

2.4 V

3.0 V

3.6 V

1.8 V

2.4 V

3.0 V

3.6 V

2.4 V

3.0 V

3.6 V

1.8 V

2.4 V

3.0 V

3.6 V

1.8 V

Unit

µA

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124

Electrical characteristics STM32G0B1xB/xC/xE

Symbol

∆ I

DD(SRAM)

Table 33. Current consumption in Standby mode (continued)

Max

(1)

Parameter

Conditions Typ

General V

25°C 85°C 125°C 25°C 85°C 130°C

1.8 V -

Extra supply current to retain SRAM content

(3)

SRAM retention enabled

2.4 V

3.0 V

3.6 V

1. Based on characterization results, not tested in production.

2. Without SRAM retention and with ULPEN bit set

3. To be added to I

DD(Standby)

as appropriate

Symbol

DD(Shutdown)

Table 34. Current consumption in Shutdown mode

Conditions

Parameter

Typ

Supply current in Shutdown mode

RTC

Disabled

Enabled, clocked by LSE bypass at

32.768 kHz

Max

(1)

1.8 V

2.4 V

3.0 V

3.6 V

25 °C 85 °C 125 °C 25 °C 85 °C 130 °C

840

965

1100

1350

7050

8050

9550

11000

240

370

500

3210

3910

4700

5700

39200

44600

51500

59400

1.8 V 235 1050 7400 290 3850 47000

2.4 V 320 1250 8400 440 4690 53500

3.0 V 425 1500 9950 450 5640 61800

3.6 V 550 1850 11500 590 6840 71200

1. Based on characterization results, not tested in production.

Unit

µA

Unit nA

Symbol

DD(VBAT)

Table 35. Current consumption in VBAT mode

Conditions

Parameter

RTC V

1.8 V

25°C

195

Enabled, clocked by

LSE bypass at

32.768 kHz

2.4 V

3.0 V

320

492

3.6 V

1.8 V

627

130

Supply current in

VBAT mode

Enabled, clocked by

LSE crystal at

32.768 kHz

2.4 V

3.0 V

160

210

3.6 V

1.8 V

285

Disabled

2.4 V

3.0 V

3.6 V

Typ

85°C

416

530

635

908

325

400

500

605

160

190

220

270

125°C

2015

2366

2838

3339

1550

1800

2050

2400

1450

1700

1950

2250

Unit nA

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I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in

Table 55: I/O static characteristics

For the output pins, any external pull-down or external load must also be considered to estimate the current consumption.

Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs.

Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode.

I/O dynamic current consumption

In addition to the internal peripheral current consumption measured previously

(see Table 36: Current consumption of peripherals ), the I/Os used by an application also

contribute to the current consumption. When an I/O pin switches, it uses the current from the I/O supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin:

= V

DDIOx

×

C where

is the current sunk by a switching I/O to charge/discharge the capacitive load

DDIOx

is the I/O supply voltage f

is the I/O switching frequency

C is the total capacitance seen by the I/O pin: C = C

INT

+ C

EXT

+ C

is the PCB board capacitance including the pad pin.

The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency.

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Electrical characteristics STM32G0B1xB/xC/xE

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in the following table. The MCU is placed under the following conditions:

• All I/O pins are in Analog mode

• The given value is calculated by measuring the difference of the current consumptions:

– when the peripheral is clocked on

– when the peripheral is clocked off

•

Ambient operating temperature and supply voltage conditions summarized in Table 21:

Voltage characteristics

• The power consumption of the digital part of the on-chip peripherals is given in the following table. The power consumption of the analog part of the peripherals (where applicable) is indicated in each related section of the datasheet.

Peripheral

IOPORT Bus

GPIOA

GPIOB

GPIOC

GPIOD

GPIOE

GPIOF

Bus matrix

All AHB Peripherals

DMA1/DMAMUX

CRC

FLASH

All APB peripherals

AHB to APB bridge (1)

PWR

WWDG

DMA2

TIM1

TIM2

TIM3

TIM4

TIM6

TIM7

TIM14

Table 36. Current consumption of peripherals

Consumption in µA/MHz

Bus

Range 1 Range 2

Low-power run and sleep

APB

AHB

APB

IOPORT

AHB

1.5

7.6

5.2

4.7

4.4

5.1

0.4

120

0.2

0.4

1.2

0.8

1.4

0.5

3.1

2.9

3.0

2.7

1.6

2.8

0.5

1.3

6.3

4.3

3.9

3.7

4.3

0.4

110

0.2

0.3

0.4

1.0

0.7

1.2

0.4

2.4

2.3

2.4

2.2

1.4

2.3

0.5

1.5

7.2

4.9

4.3

4.2

4.9

0.5

220

0.1

0.4

1.1

0.8

1.3

0.3

3.0

2.8

2.5

1.6

2.6

0.5

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STM32G0B1xB/xC/xE Electrical characteristics

Table 36. Current consumption of peripherals (continued)

Consumption in µA/MHz

Peripheral Bus

Range 1 Range 2

Low-power run and sleep

SPI1

SPI2

SPI3

USART1

USART2

USART3

USART4

USART5

USART6

LPUART1

LPUART2

ADC

DAC1

TIM15

TIM16

TIM17

LPTIM1

LPTIM2

I2C1

I2C2

I2C3

SYSCFG/VREFBUF/COMP

CEC

CRS

USB

FDCAN

APB

2.2

4.5

4.9

2.4

1.9

2.2

2.1

1.4

7.4

2.1

2.3

4.2

2.7

0.8

3.3

3.2

3.6

3.4

0.9

0.5

0.4

0.2

3.3

UCPD1

UCPD2

APB

4.0

7.9

1. The AHB to APB Bridge is automatically active when at least one peripheral is ON on the APB.

2. UCPDx are always clocked by HSI16.

1.8

3.7

4.1

2.0

1.6

1.9

1.7

1.2

6.2

1.8

1.9

3.5

2.3

0.7

2.7

3.0

2.8

0.7

0.4

0.3

0.2

2.7

0.5

0.3

3.0

59.0

(2)

59.5

(2)

2.1

4.2

4.6

2.3

1.8

2.1

2.0

1.3

6.9

7.0

6.9

2.0

2.1

3.9

2.5

0.7

3.1

3.3

3.2

0.8

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Electrical characteristics STM32G0B1xB/xC/xE

5.3.6 Wakeup time from low-power modes and voltage scaling transition times

The wakeup times given in

Table 37 are the latency between the event and the execution of

the first user instruction.

Symbol Parameter

Table 37. Low-power mode wakeup times

(1)

Conditions t

WUSLEEP

Wakeup time from

Sleep to Run mode

WULPSLEEP

Wakeup time from

Low-power sleep mode

Transiting to Low-power-run-mode execution in Flash memory not powered in Low-power sleep mode;

HCLK = HSI16 / 8 = 2 MHz t t t

WUSTOP0

WUSTOP1

WUSTBY

Wakeup time from

Stop 0

Transiting to Run-mode execution in Flash memory not powered in Stop 0 mode;

HCLK = HSI16 = 16 MHz;

Regulator in Range 1 or Range 2

Transiting to Run-mode execution in SRAM or in Flash memory powered in Stop 0 mode;

HCLK = HSI16 = 16 MHz;

Regulator in Range 1 or Range 2

Wakeup time from

Stop 1

Transiting to Run-mode execution in Flash memory not powered in Stop 1 mode;

HCLK = HSI16 = 16 MHz;

Regulator in Range 1 or Range 2

Transiting to Run-mode execution in SRAM or in Flash memory powered in Stop 1 mode;

HCLK = HSI16 = 16 MHz;

Regulator in Range 1 or Range 2

Transiting to Low-power-run-mode execution in Flash memory not powered in Stop 1 mode;

HCLK = HSI16/8 = 2 MHz;

Regulator in low-power mode (LPR = 1 in PWR_CR1)

Transiting to Low-power-run-mode execution in SRAM or in Flash memory powered in Stop 1 mode;

HCLK = HSI16 / 8 = 2 MHz;

Regulator in low-power mode (LPR = 1 in PWR_CR1)

Wakeup time from

Standby mode

Transiting to Run mode;

HCLK = HSI16 = 16 MHz;

Regulator in Range 1

Typ

5.6

9.0

14.5

Max

2.4

11.2

7.5

25.3

23.5

Unit

CPU cycles

µs

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Symbol

Table 37. Low-power mode wakeup times (1) (continued)

Parameter Conditions t t

WUSHDN

WULPRUN

Wakeup time from

Shutdown mode

Transiting to Run mode;

HCLK = HSI16 = 16 MHz;

Regulator in Range 1

Wakeup time from

Low-power run mode (2)

Transiting to Run mode;

HSISYS = HSI16/8 = 2 MHz

1. Based on characterization results, not tested in production.

2. Time until REGLPF flag is cleared in PWR_SR2.

Typ Max Unit

258 340

5 7

µs

Symbol

Table 38. Regulator mode transition times (1)

Parameter Conditions t

VOST

Transition times between regulator

Range 1 and Range 2

(2)

1. Based on characterization results, not tested in production.

2. Time until VOSF flag is cleared in PWR_SR2.

HSISYS = HSI16

Symbol

Table 39. Wakeup time using LPUART (1)

Parameter Conditions t

WULPUART

Wakeup time needed to calculate the maximum

LPUART baud rate allowing to wakeup up from Stop mode when LPUART clock source is HSI16

Stop mode 0

Stop mode 1

1. Guaranteed by design.

Typ

Max

Unit

µs

Typ Max Unit

1.7

µs

8.5

High-speed external user clock generated from an external source

In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in Section 5.3.14

. See

Figure 18

for recommended clock input waveform.

Symbol

HSEH

HSEL

Table 40. High-speed external user clock characteristics

(1)

Parameter Conditions Min Typ f

HSE_ext

User external clock source frequency

OSC_IN input pin high level voltage

OSC_IN input pin low level voltage

Voltage scaling

Range 1

Voltage scaling

Range 2

0.7 V

DDIO1

Max

DDIO1

0.3 V

DDIO1

Unit

MHz

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124

Electrical characteristics STM32G0B1xB/xC/xE

Symbol

Table 40. High-speed external user clock characteristics (1) (continued)

Parameter Conditions Min Typ Max t w(HSEH) t w(HSEL)

OSC_IN high or low time

Voltage scaling

Range 1

Voltage scaling

Range 2

18 -

1. Guaranteed by design.

Unit ns

Figure 18. High-speed external clock source AC timing diagram tw(HSEH)

VHSEH

VHSEL

90%

10% tr(HSE)

THSE tf(HSE) tw(HSEL) t

MS19214V2

Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in Section 5.3.14

. See

Figure 19

for recommended clock input waveform.

Symbol

Table 41. Low-speed external user clock characteristics

(1)

Parameter f

LSE_ext

LSEH

LSEL t w(LSEH) t w(LSEL)

User external clock source frequency

OSC32_IN input pin high level voltage

OSC32_IN input pin low level voltage

OSC32_IN high or low time

1. Guaranteed by design.

Conditions

Min

0.7 V

DDIO1

250

Typ

32.768

Max

1000

DDIO1

0.3 V

DDIO1

Unit kHz

V ns

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Figure 19. Low-speed external clock source AC timing diagram tw(LSEH)

VLSEH

VLSEL

90%

10% tr(LSE) tw(LSEL) t

TLSE tf(LSE)

MS19215V2

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in

Table 42 . In the

application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics

(frequency, package, accuracy).

Symbol

Table 42. HSE oscillator characteristics

(1)

Parameter Conditions

(2) f

OSC_IN

Oscillator frequency

Feedback resistor

During startup

(3)

= 3 V,

Rm = 30 Ω ,

CL = 10 pF@8 MHz

= 3 V,

Rm = 45 Ω ,

CL = 10 pF@8 MHz

DD(HSE)

HSE current consumption

= 3 V,

Rm = 30 Ω ,

CL = 5 pF@48 MHz

= 3 V,

Rm = 30 Ω ,

CL = 10 pF@48 MHz

= 3 V,

Rm = 30 Ω ,

CL = 20 pF@48 MHz

G m

Maximum critical crystal transconductance

Startup t

SU(HSE)

(4)

Startup time V

is stabilized

1. Guaranteed by design.

2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

Min

Typ

200

0.44

0.45

0.68

0.94

1.77

Max

5.5

1.5

Unit

MHz k Ω mA mA/V ms

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124

Electrical characteristics STM32G0B1xB/xC/xE

3. This consumption level occurs during the first 2/3 of the t

SU(HSE) startup time

4. t

SU(HSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer

Note:

For C

and C

, it is recommended to use high-quality external ceramic capacitors in the

5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match

the requirements of the crystal or resonator (see Figure 20

). C

and C

L2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C

and C

. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing

and C

For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com

Figure 20. Typical application with an 8 MHz crystal

Resonator with integrated capacitors

OSC_IN f

HSE

8 MHz resonator

EXT

(1) OSC_OUT

Bias controlled gain

MS19876V1

1. R

EXT

value depends on the crystal characteristics.

Low-speed external clock generated from a crystal resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in

Table 43 . In the application, the

resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

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Symbol

Table 43. LSE oscillator characteristics (f

LSE

= 32.768 kHz) (1)

Parameter Conditions

(2)

Min Typ Max Unit

DD(LSE)

LSE current consumption

LSEDRV[1:0] = 00

Low drive capability

LSEDRV[1:0] = 01

Medium low drive capability

LSEDRV[1:0] = 10

Medium high drive capability

LSEDRV[1:0] = 11

High drive capability

250

315

500

630 -

LSEDRV[1:0] = 00

Low drive capability

LSEDRV[1:0] = 01

Medium low drive capability

0.5

0.75

Gm critmax

Maximum critical crystal gm

1.7

µA/V

LSEDRV[1:0] = 10

Medium high drive capability

LSEDRV[1:0] = 11

High drive capability

2.7

SU(LSE)

(3)

Startup time V

is stabilized 2 -

1. Guaranteed by design.

2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for

ST microcontrollers”.

3. t

SU(LSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer s

Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com

Figure 21. Typical application with a 32.768 kHz crystal

Resonator with integrated capacitors

OSC32_IN f

LSE

32.768 kHz resonator

Drive programmable amplifier

OSC32_OUT

Note:

MS30253V2

An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one.

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Electrical characteristics STM32G0B1xB/xC/xE

5.3.8 Internal clock source characteristics

The parameters given in

Table 44 are derived from tests performed under ambient

temperature and supply voltage conditions summarized in Table 24: General operating conditions

. The provided curves are characterization results, not tested in production.

High-speed internal (HSI16) RC oscillator

Symbol

Table 44. HSI16 oscillator characteristics (1)

Parameter Conditions

∆

∆ f

HSI16

Temp(HSI16)

VDD(HSI16)

TRIM

HSI16 Frequency

HSI16 oscillator frequency drift over temperature

HSI16 frequency user trimming step

=3.0 V, T

=30 °C

= 0 to 85 °C

= -40 to 125 °C

HSI16 oscillator frequency drift over

=1.62 V to 3.6 V

From code 127 to 128

From code 63 to 64

From code 191 to 192

HSI16

(2) t su(HSI16)

(2) t stab(HSI16)

(2)

DD(HSI16)

(2)

Duty Cycle

HSI16 oscillator start-up time

HSI16 oscillator stabilization time

HSI16 oscillator power consumption

1. Based on characterization results, not tested in production.

2. Guaranteed by design.

For all other code increments

Min

15.88

-1

-2

-0.1

-8

-5.8

0.2

Typ

-6

-3.8

0.3

0.8

155

Max Unit

16.08

MHz

1 %

1.5

0.05

-4

-1.8

0.4

1.2

190

μ s

μ A

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Figure 22. HSI16 frequency vs. temperature

MHz

16.4

16.3

16.2

16.1

15.9

15.8

15.7

15.6

-40

+2%

+1.5%

+1%

0 min

-1%

-1.5%

-2%

40 mean

60 -20 80 max

100 120 °C

MSv39299V1

High-speed internal 48 MHz (HSI48) RC oscillator

Symbol

Table 45. HSI48 oscillator characteristics (1)

Parameter Conditions f

HSI48

TRIM

HSI48 Frequency

HSI48 user trimming step

=3.0V, T

=30°C

USER TRIM

COVERAGE

HSI48 user trimming coverage

DuCy(HSI48) Duty Cycle

±64 steps

ACC

HSI48_REL

VDD

(HSI48)

Accuracy of the HSI48 oscillator over temperature (factory calibrated)

HSI48 oscillator frequency drift with V

I t su

(HSI48) HSI48 oscillator start-up time

(HSI48)

HSI48 oscillator power consumption

jitter

Next transition jitter

Accumulated jitter on 28 cycles

(4)

Paired transition jitter

Accumulated jitter on 56 cycles

(4)

= 3.0 V to 3.6 V,

= –15 to 85 °C

= 1.65 V to 3.6 V,

= –40 to 125 °C

= 3 V to 3.6 V

= 1.65 V to 3.6 V

Min

±6

(3)

(2)

Typ

0.11

(2)

±7

(3)

0.025

(3)

0.05

(3)

2.5

(2)

340

(2)

+/-0.15

(2)

+/-0.25

(2)

±4.5

(3)

0.05

(3)

0.1

(3)

(2)

380

(2)

Max Unit

0.18

(2)

MHz

% -

(2)

±3

(3)

μ s

ns ns

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124

Electrical characteristics STM32G0B1xB/xC/xE

1. V

= 3 V, T

= –40 to 125°C unless otherwise specified.

2. Guaranteed by design.

3. Guaranteed by characterization results.

4. Jitter measurement are performed without clock source activated in parallel.

Figure 23. HSI48 frequency versus temperature

-2

-4

-6

-50 -30 10 70 -10

Avg

30 min

50 90 max

110 130

°C

MSv40989V1

Low-speed internal (LSI) RC oscillator

Symbol

Table 46. LSI oscillator characteristics (1)

Parameter Conditions t

SU(LSI)

(2) t

STAB(LSI)

(2)

I f

LSI

DD(LSI)

(2)

LSI frequency

= 3.0 V, T

= 30 °C

= 1.62 V to 3.6 V, T

125 °C

= -40 to

LSI oscillator start-up time -

LSI oscillator stabilization time 5% of final frequency

LSI oscillator power consumption

1. Based on characterization results, not tested in production.

2. Guaranteed by design.

Min Typ Max Unit

31.04

32.96

kHz

29.5

125

110

130

180

μ s s nA

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The parameters given in

Table 47 are derived from tests performed under temperature and

supply voltage conditions summarized in

Symbol

Table 47. PLL characteristics

(1)

Parameter

PLL input clock frequency

(2)

Conditions

Min f

PLL_IN

PLL input clock duty cycle -

2.66

45 f f f

PLL_P_OUT

PLL_Q_OUT

PLL_R_OUT f

VCO_OUT t

LOCK

Jitter

PLL multiplier output clock P

PLL multiplier output clock Q

PLL multiplier output clock R

PLL VCO output

PLL lock time

RMS cycle-to-cycle jitter

RMS period jitter

Voltage scaling Range 1

Voltage scaling Range 2

Voltage scaling Range 1

Voltage scaling Range 2

Voltage scaling Range 1

Voltage scaling Range 2

Voltage scaling Range 1

Voltage scaling Range 2

System clock 56 MHz

DD(PLL)

PLL power consumption on V

The test results are given in Table 50

VCO freq = 96 MHz

VCO freq = 192 MHz

VCO freq = 344 MHz

1. Guaranteed by design.

2. Make sure to use the appropriate division factor M to obtain the specified PLL input clock values.

3.09

Typ Max Unit

16 MHz

% 55

40 -

200 260

300 380

520 650

344

128

122

128

MHz

±ps

μ s

Symbol t prog t prog_row t prog_page t

ERASE t prog_bank t

Table 48. Flash memory characteristics (1)

Parameter Conditions

64-bit programming time

Row (32 double word) programming time

Page (2 Kbyte) programming time

Page (2 Kbyte) erase time

Bank (512 Kbyte

(2)

) programming time

Mass erase time

Normal programming

Fast programming

Normal programming

Fast programming

Normal programming

Fast programming

Typ

13.7

22.0

2.8

1.8

22.1

2.7

1.7

21.8

Max

22.4

40.0

4.7

2.9

40.1

125

4.6

2.8

36.6

Unit

µs ms s ms

DS13560 Rev 3

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124

Electrical characteristics STM32G0B1xB/xC/xE

Symbol

Table 48. Flash memory characteristics (1) (continued)

Parameter Conditions

DD(FlashA)

DD(FlashP)

Average consumption from V

Maximum current (peak)

Programming

Page erase

Mass erase

Programming, 2 µs peak duration

Erase, 41 µs peak duration

1. Guaranteed by design.

2. Values provided also apply to devices with less Flash memory than one 512 Kbyte bank

Typ

Max

Unit mA mA

Symbol

Table 49. Flash memory endurance and data retention

Parameter Conditions

N t

END

RET

Endurance

Data retention

= -40 to +105 °C

1 kcycle

(2)

at T

= 85 °C

1 kcycle

(2)

at T

= 105 °C

1 kcycle

(2)

at T

= 125 °C

10 kcycles

(2)

at T

= 55 °C

10 kcycles (2) at T

= 85 °C

10 kcycles

(2)

at T

= 105 °C

1. Guaranteed by characterization results.

2. Cycling performed over the whole temperature range.

Min

(1)

Unit kcycles

Years

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

• FTB : A Burst of Fast Transient voltage (positive and negative) is applied to V

through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard.

and

A device reset allows normal operations to be resumed.

. They are based on the EMS levels and classes defined in application note AN1709.

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Table 50. EMS characteristics

Parameter Conditions Symbol

FESD

EFTB

Voltage limits to be applied on any I/O pin to induce a functional disturbance f

= 3.3 V, T

HCLK

= +25 °C,

= 64 MHz, LQFP100, conforming to IEC 61000-4-2

Fast transient voltage burst limits to be applied through 100 pF on V

DD functional disturbance

and V

SS pins to induce a f

= 3.3 V, T

HCLK

= +25 °C,

= 64 MHz, LQFP100, conforming to IEC 61000-4-4

Level/

Class

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

• corrupted program counter

• unexpected reset

• critical data corruption (for example control registers)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with

IEC 61967-2 standard which specifies the test board and the pin loading.

DS13560 Rev 3

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124

Electrical characteristics

EMI

Symbol Parameter

Table 51. EMI characteristics

Conditions

Monitored frequency band

Peak level

= 3.6 V, T

= 25 °C,

LQFP100 package compliant with IEC 61967-2

0.1 MHz to 30 MHz

30 MHz to 130 MHz

130 MHz to 1 GHz

1 GHz to 2 GHz

EMI level

STM32G0B1xB/xC/xE

Max vs.

HSE

HCLK

]

8 MHz / 64 MHz

2.5

Unit dBµV

Symbol

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the ANSI/JEDEC standard.

Table 52. ESD absolute maximum ratings

Ratings Conditions Class

Maximum value (1)

Unit

ESD(HBM)

ESD(CDM)

Electrostatic discharge voltage

(human body model)

Electrostatic discharge voltage

(charge device model)

= +25 °C, conforming to

ANSI/ESDA/JEDEC JS-001

= +25 °C, conforming to

ANSI/ESDA/JEDEC JS-002

1. Based on characterization results, not tested in production.

C2a

2000

250

Symbol

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up performance:

• A supply overvoltage is applied to each power supply pin.

• A current is injected to each input, output and configurable I/O pin.

These tests are compliant with EIA/JESD 78A IC latch-up standard.

Parameter

Static latch-up class

Table 53. Electrical sensitivity

Conditions

= +125 °C conforming to JESD78

Class

II Level A

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As a general rule, current injection to the I/O pins, due to external voltage below V

SS above V

DDIOx product operation. However, in order to give an indication of the robustness of the

(for standard, 3.3 V-capable I/O pins) should be avoided during normal microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out-of-range parameter: ADC error above a certain limit

(higher than 5 LSB TUE), induced leakage current on adjacent pins out of conventional limits (-5 µA/+0 µA range) or other functional failure (for example reset occurrence or oscillator frequency deviation).

Negative induced leakage current is caused by negative injection and positive induced leakage current is caused by positive injection.

Symbol

Table 54. I/O current injection susceptibility

(1)

Functional susceptibility

Description

Negative injection

Positive injection

INJ

Injected current on pin

All except PA4, PA5, PA6, PB0,

PB3, and PC0

PA4, PA5

PA6, PB0, PB3, and PC0

1. Based on characterization results, not tested in production.

-5

N/A

Unit mA mA mA

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Electrical characteristics STM32G0B1xB/xC/xE

Symbol

General input/output characteristics

Unless otherwise specified, the parameters given in

Table 55 are derived from tests

performed under the conditions summarized in Table 24: General operating conditions

. All

I/Os are designed as CMOS- and TTL-compliant.

Parameter

Table 55. I/O static characteristics

Conditions Min Typ

All except

FT_c

1.62 V < V

DDIOx

< 3.6 V -

(1)

I/O input low level voltage

1. Refer to Figure 24: I/O input characteristics .

hys

(3)

I lkg

I/O input high level voltage

I/O input hysteresis

Input leakage current

(3)

FT_c

All except

FT_c

2.7 V < V

DDIOx

1.62 V < V

< 3.6 V

DDIOx

< 2.7 V

1.62 V < V

DDIOx

< 3.6 V

FT_c 1.62 V < V

DDIOx

< 3.6 V

TT_xx,

FT_xx,

NRST

1.62 V < V

DDIOx

< 3.6 V

FT_xx except

FT_c and

FT_d

0 < V

≤ V

DDIOx

≤ V

DDIOx

+1 V

5.5 V

+1 V < V

≤

FT_c

FT_d

TT_a

0 < V

≤ V

DDIOx

< V

≤ 5 V

0 < V

≤ V

DDIOx

< V

≤ 5.5 V

0 < V

≤ V

DDIOx

< V

≤

+ 0.3 V

0.7 x V

DDIOx

(

0.49 x V

+ 0.26

0.7 x V

DDIOx

Weak pull-up equivalent resistor

(5)

= V

Weak pull-down equivalent resistor

(5)

= V

DDIOx

I/O pin capacitance

2. Tested in production.

3. Guaranteed by design.

200

±70

600 (4)

150

(4)

2000

3000

(4)

4500

9000 (4)

±150

2000

(4)

Max

0.3 x V

(2)

DDIOx

Unit

0.39 x V

- 0.06

0.3 x V

DDIOx

0.25 x V

DDIOx

mV nA k Ω k Ω pF

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4. This value represents the pad leakage of the I/O itself. The total product pad leakage is provided by this formula:

Total_Ileak_max

= 10 µA + [number of I/Os where V

is applied on the pad] ₓ I lkg

(Max).

5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

PMOS/NMOS contribution to the series resistance is minimal (~10% order).

All I/Os are CMOS- and TTL-compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters, as shown in

Figure 24

Figure 24. I/O input characteristics

2.5

Minimum required logic level 1 zone

TTL standard requirement

(V)

1.5

0.5

DDIO

(CMOS standard requirement)

IHmin

= 0.7 V

IHmin

= 0.49 V

DDIO

+ 0.26

Undefined input range

ILmax

= 0.39 V DDIO

- 0.06

ILmax

= 0.3 V DDIO

(CMOS standard requirement)

TTL standard requirement

Minimum required logic level 0 zone

1.6

1.8

2.0

Device characteristics

Test thresholds

2.2

2.4

2.6

DDIO

(V)

2.8

3.0

3.2

3.4

3.6

MSv47925V1

Characteristics of FT_e I/Os

The following table and figure specify input characteristics of FT_e I/Os.

Symbol

INJ

DDIO1

-V

R d

Table 56. Input characteristics of FT_e I/Os

Parameter Conditions Min

Injected current on pin

Voltage over V

DDIO1

Diode dynamic serial resistor

INJ

= 5 mA

INJ

= 5 mA -

Typ

Max

300

Unit mA

Ω

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Electrical characteristics STM32G0B1xB/xC/xE

Figure 25. Current injection into FT_e input with diode active

-40°C 25°C 125°C

INJ

(mA)

0 0.2

0.4

0.6

0.8

1.0

1.2

– V

DDIO1

(V)

1.4

1.6

1.8

MSv63112V1

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and up to

±15 mA with relaxed V

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in

Section 5.2

• The sum of the currents sourced by all the I/Os on V

DDIO1,

I consumption of the MCU sourced on V

DD,

VDD

(see

Table 21: Voltage characteristics

plus the maximum cannot exceed the absolute maximum rating

• The sum of the currents sunk by all the I/Os on V

, plus the maximum consumption of the MCU sunk on V

, cannot exceed the absolute maximum rating I

Voltage characteristics

VSS

(see Table 21:

Output voltage levels

Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in

Table 24: General operating conditions . All I/Os are CMOS- and TTL-compliant (FT OR TT

unless otherwise specified).

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Symbol

Table 57. Output voltage characteristics (1)

Parameter Conditions Min Max Unit

(3)

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

CMOS port

DDIOx

(2)

= 2 mA for FT_c I/Os

= 8 mA for other I/Os

≥ 2.7 V

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

TTL port

DDIOx

(2)

= 2 mA for FT_c I/Os

= 8 mA for other I/Os

≥ 2.7 V

Output low level voltage for an I/O pin All I/Os except FT_c

Output high level voltage for an I/O pin

| = 15 mA

DDIOx

≥ 2.7 V

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

= 3 mA for other I/Os

| = 1 mA for FT_c I/Os

DDIOx

≥ 1.62 V

Output low level voltage for an FT I/O pin in FM+ mode (FT I/O with _f option)

| = 20 mA

DDIOx

≥ 2.7 V

| = 9 mA

DDIOx

≥ 1.62 V

DDIOx

2.4

DDIOx

- 0.4

- 1.3

- 0.45

0.4

1.3

0.4

1. The I

current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 21:

Voltage characteristics

, and the sum of respect the absolute maximum ratings the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always

Σ I

2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

3. Guaranteed by design.

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in

Figure 26

and

Table 58 , respectively.

Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in

Table 24: General operating conditions

Speed Symbol

Table 58. I/O AC characteristics

(1)(2)

Parameter

Fmax Maximum frequency

Tr/Tf Output rise and fall time

Conditions

C=50 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=50 pF, 1.6 V ≤ V

DDIOx

≤ 2.7 V

C=10 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=10 pF, 1.6 V ≤ V

DDIOx

≤ 2.7 V

C=50 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=50 pF, 1.6 V ≤ V

DDIOx

≤ 2.7 V

C=10 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=10 pF, 1.6 V ≤ V

DDIOx

≤ 2.7 V

Min

Max

0.35

0.45

100

225

150

Unit

MHz ns

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124

Electrical characteristics STM32G0B1xB/xC/xE

Table 58. I/O AC characteristics (1)(2) (continued)

Speed Symbol

Fm+

Fmax

Tr/Tf

Fmax

Tr/Tf

Fmax

Tr/Tf

Parameter

Maximum frequency

Output rise and fall time

Maximum frequency

Output rise and fall time

Maximum frequency

Output rise and fall time

Fmax Maximum frequency

Tf Output fall time

(4)

Conditions

C=50 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=50 pF, 1.6 V ≤ V

DDIOx

≤ 2.7 V

C=10 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=10 pF, 1.6 V ≤ V

DDIOx

≤ 2.7 V

C=50 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=50 pF, 1.6 V ≤ V

DDIOx

≤ 2.7 V

C=10 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=10 pF, 1.6 V ≤ V

DDIOx

≤ 2.7 V

C=50 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=50 pF, 1.6 V ≤ V

DDIOx

≤ 2.7 V

C=10 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=10 pF, 1.6 V ≤ V

DDIOx

≤ 2.7 V

C=50 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=50 pF, 1.6 V ≤ V

DDIOx

≤ 2.7 V

C=10 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=10 pF, 1.6 V ≤ V

DDIOx

≤ 2.7 V

C=30 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=30 pF, 1.6 V ≤ V

DDIOx

≤ 2.7 V

C=10 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=10 pF, 1.6 V ≤ V

DDIOx

≤ 2.7 V

C=30 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=30 pF, 1.6 V ≤ V

DDIOx

≤ 2.7 V

C=10 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=10 pF, 1.6 V ≤ V

DDIOx

≤ 2.7 V

C=50 pF, 1.6 V ≤ V

DDIOx

≤ 3.6 V

Min

Max

2.5

(3)

5.5

2.5

Unit

MHz ns

1. The I/O speed is configured using the OSPEEDRy[1:0] bits. The Fm+ mode is configured in the SYSCFG_CFGR1 register.

Refer to the RM0444 reference manual for a description of GPIO Port configuration register.

2. Guaranteed by design.

3. This value represents the I/O capability but the maximum system frequency is limited to 64 MHz.

4. The fall time is defined between 70% and 30% of the output waveform, according to I

C specification.

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Figure 26. I/O AC characteristics definition

(1)

90% 10%

50% 50%

10% 90% t r(IO)out t f(IO)out

T when loaded by the specified capacitance.

MS32132V2

1. Refer to Table 58: I/O AC characteristics .

5.3.15 NRST input characteristics

The NRST input driver uses CMOS technology. It is connected to a permanent pull-up resistor, R

Unless otherwise specified, the parameters given in the following table are derived from tests performed under the ambient temperature and supply voltage conditions summarized in

Table 59: NRST pin characteristics

Symbol Parameter

Table 59. NRST pin characteristics (1)

Conditions Min Typ Max Unit

IL(NRST)

IH(NRST)

V hys(NRST)

F(NRST)

NF(NRST)

NRST input low level voltage

NRST input high level voltage

NRST Schmitt trigger voltage hysteresis

Weak pull-up equivalent resistor

(2)

NRST input filtered pulse

NRST input not filtered pulse

= V

1.7 V ≤ V

≤ 3.6 V

0.7 x V

DDIO1

350

200

0.3 x V

DDIO1

1. Guaranteed by design.

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimal (~10% order)

V mV k Ω ns ns

DS13560 Rev 3

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Electrical characteristics STM32G0B1xB/xC/xE

Figure 27. Recommended NRST pin protection

External reset circuit

(1)

0.1 μF

NRST

(2)

Filter

Internal reset

MS19878V3

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the V

IL(NRST)

max level specified in

. Otherwise the reset will not be taken into account by the device.

3. The external capacitor on NRST must be placed as close as possible to the device.

Symbol

Table 60. Analog switch booster characteristics (1)

Parameter

DD t

SU(BOOST)

Supply voltage

Booster startup time

DD(BOOST)

Booster consumption for

1.62 V ≤ V

≤ 2.0 V

Booster consumption for

2.0 V ≤ V

≤ 2.7 V

Booster consumption for

2.7 V ≤ V

≤ 3.6 V

1. Guaranteed by design.

Min

1.62 V

Typ

Max

3.6

240

250

500

900

Unit

µs

µA

Note:

Symbol

DDA

REF+

Unless otherwise specified, the parameters given in Table 61

are preliminary values derived from tests performed under ambient temperature, f

PCLK frequency and V

conditions summarized in Table 24: General operating conditions

DDA

supply voltage

It is recommended to perform a calibration after each power-up.

Parameter

Table 61. ADC characteristics (1)

Conditions

(2)

Min

Analog supply voltage

Positive reference voltage

DDA

≥ 2 V

DDA

< 2 V

1.62

Typ

DDA

Max

3.6

DDA

Unit

100/159

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Symbol f

ADC f s f

TRIG

AIN

(3)

AIN

ADC t

STAB t

CAL t

LATR t s

Table 61. ADC characteristics (1) (continued)

Parameter Conditions (2) Min Typ

ADC clock frequency

Sampling rate

External trigger frequency

Range 1

Range 2

12 bits

10 bits

8 bits

6 bits f

ADC

= 35 MHz; 12 bits

12 bits -

0.14

Conversion voltage range

External input impedance

Internal sample and hold capacitor

SSA

ADC power-up time

Calibration time

Trigger conversion latency

Sampling time t

ADCVREG_STUP

ADC voltage regulator start-up time

ADC

= 35 MHz

CKMODE = 00

CKMODE = 01

CKMODE = 10

CKMODE = 11 f

ADC

= 35 MHz;

DDA

> 2V f

ADC

= 35 MHz;

DDA

< 2V

ADC

= 35 MHz

Resolution = 12 bits

0.043

1.5

0.1

3.5

2.35

6.5

12.5

CONV

Total conversion time

(including sampling time)

Resolution = 12 bits

0.40

4.95

t s

+ 12.5 cycles for successive approximation

= 14 to 173

Max

2.50

2.92

3.50

4.38

2.33

ADC

/15

REF+

4.59

160.5

4.59

160.5

20 t

IDLE

Laps of time allowed between two conversions without rearm

100

Unit

MHz

MSps

MHz

V k Ω pF

Conversion cycle

µs

1/f

ADC

1/f

ADC

1/f

PCLK

µs

1/f

ADC

µs

1/f

ADC

µs

1/f

ADC

µs

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124

Electrical characteristics STM32G0B1xB/xC/xE

Symbol

Table 61. ADC characteristics (1) (continued)

Parameter Conditions (2) Min Typ Max Unit

DDA(ADC)

DDV(ADC)

ADC consumption from V

DDA

ADC consumption from V

REF+ f s

= 2.5 MSps f s

= 1 MSps f s

= 10 kSps f s

= 2.5 MSps f s

= 1 MSps f s

= 10 kSps -

410

164

0.26

1. Guaranteed by design

2. I/O analog switch voltage booster must be enabled (BOOSTEN = 1 in the SYSCFG_CFGR1) when V disabled when V

DDA

≥ 2.4 V.

DDA

< 2.4 V and

REF+

is internally connected to V

for further details.

DDA

on some packages.Refer to Section 4: Pinouts, pin description and alternate

µA

Resolution

12 bits

10 bits

Table 62. Maximum ADC R

AIN

Sampling cycle at 35 MHz

Sampling time at 35 MHz

[ns]

1.5

(3)

3.5

7.5

12.5

19.5

39.5

79.5

160.5

1.5

(3)

3.5

7.5

12.5

19.5

39.5

79.5

160.5

100

214

357

557

1129

2271

4586

100

214

357

557

1129

2271

4586

Max. R

AIN

(1)(2)

( Ω )

820

3300

5600

10000

22000

39000

50000

680

2200

4700

8200

15000

33000

50000

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STM32G0B1xB/xC/xE Electrical characteristics

Resolution

8 bits

6 bits

Table 62. Maximum ADC R

AIN

(continued)

Sampling cycle at 35 MHz

Sampling time at 35 MHz

[ns]

3.5

7.5

12.5

19.5

39.5

79.5

160.5

1.5

(3)

3.5

7.5

12.5

19.5

39.5

79.5

160.5

1.5

(3)

4586

100

214

357

557

1129

2271

4586

100

214

357

557

1129

2271

Max. R

AIN

(1)(2)

( Ω )

50000

390

2200

5600

10000

15000

33000

50000

1500

3900

6800

12000

27000

50000

1. Guaranteed by design.

2. I/O analog switch voltage booster must be enabled (BOOSTEN = 1 in the SYSCFG_CFGR1) when V disabled when V

DDA

≥ 2.4 V.

DDA

< 2.4 V and

3. Only allowed with V

DDA

> 2 V

Symbol

Parameter

Total unadjusted error

Table 63. ADC accuracy (1)(2)(3)

Conditions

(4) f

DDA

= V

ADC

REF+

= 25 °C

= 3 V;

= 35 MHz; f s

≤ 2.5 MSps; f

2 V < V

ADC

DDA

REF+

= 35 MHz; f s

= entire range

< 3.6 V;

≤ 2.5 MSps;

1.65 V < V

DDA

REF+

< 3.6 V;

= entire range

Range 1: f

ADC

Range 2: f

ADC

= 35 MHz; f

= 16 MHz; f s s

≤ 2.2 MSps;

≤ 1.1 MSps;

Min Typ Max Unit

6.5

7.5

LSB

DS13560 Rev 3

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124

Electrical characteristics

Symbol

STM32G0B1xB/xC/xE

Parameter

Offset error

Gain error

Differential linearity error

Integral linearity error

Table 63. ADC accuracy (1)(2)(3) (continued)

Conditions (4) Min f

DDA

= V

ADC

REF+

= 25 °C

= 3 V;

= 35 MHz; f s

≤ 2.5 MSps; f

2 V < V

ADC

DDA

= V

REF+

= 35 MHz; f s

= entire range

< 3.6 V;

≤ 2.5 MSps;

1.65 V < V

DDA

REF+

< 3.6 V;

= entire range

Range 1: f

ADC

Range 2: f

ADC

= 35 MHz; f

= 16 MHz; f s s

≤ 2.2 MSps;

≤ 1.1 MSps; f

DDA

= V

ADC

REF+

= 25 °C

= 3 V;

= 35 MHz; f s

≤ 2.5 MSps; f

2 V < V

ADC

DDA

= V

REF+

= 35 MHz; f s

= entire range

< 3.6 V;

≤ 2.5 MSps;

1.65 V < V

DDA

= V

REF+

< 3.6 V;

= entire range

Range 1: f

ADC

Range 2: f

ADC

= 35 MHz; f

= 16 MHz; f s s

≤ 2.2 MSps;

≤ 1.1 MSps; f

DDA

= V

ADC

REF+

= 25 °C

= 3 V;

= 35 MHz; f s

≤ 2.5 MSps; f

2 V < V

ADC

DDA

= V

REF+

= 35 MHz; f s

= entire range

< 3.6 V;

≤ 2.5 MSps;

1.65 V < V

DDA

= V

REF+

< 3.6 V;

= entire range

Range 1: f

ADC

Range 2: f

ADC

= 35 MHz; f

= 16 MHz; f s s

≤ 2.2 MSps;

≤ 1.1 MSps; f

DDA

= V

ADC

REF+

= 25 °C

= 3 V;

= 35 MHz; f s

≤ 2.5 MSps; f

2 V < V

ADC

DDA

= V

REF+

= 35 MHz; f s

= entire range

< 3.6 V;

≤ 2.5 MSps;

1.65 V < V

DDA

= V

REF+

< 3.6 V;

= entire range

Range 1: f

ADC

Range 2: f

ADC

= 35 MHz; f

= 16 MHz; f s s

≤ 2.2 MSps;

≤ 1.1 MSps;

Typ Max Unit

1.5

1.2

2.5

4.5

5.5

3.5

6.5

1.5

3.5

LSB

104/159

DS13560 Rev 3

STM32G0B1xB/xC/xE Electrical characteristics

Symbol Parameter

Table 63. ADC accuracy (1)(2)(3) (continued)

Conditions (4) Min Typ Max Unit

ENOB

SINAD

SNR

THD

Effective number of bits

Signal-to-noise and distortion ratio f

DDA

= V

ADC

REF+

= 25 °C

= 3 V;

= 35 MHz; f s

≤ 2.5 MSps; f

2 V < V

ADC

DDA

= V

REF+

= 35 MHz; f s

= entire range

< 3.6 V;

≤ 2.5 MSps;

1.65 V < V

DDA

= V

REF+

< 3.6 V;

= entire range

Range 1: f

ADC

Range 2: f

ADC

= 35 MHz; f

= 16 MHz; f s s

≤ 2.2 MSps;

≤ 1.1 MSps; f

DDA

= V

ADC

REF+

= 25 °C

= 3 V;

= 35 MHz; f s

≤ 2.5 MSps; f

2 V < V

ADC

DDA

= V

REF+

= 35 MHz; f s

= entire range

< 3.6 V;

≤ 2.5 MSps;

Signal-to-noise ratio

1.65 V < V

DDA

= V

REF+

< 3.6 V;

= entire range

Range 1: f

ADC

Range 2: f

ADC

= 35 MHz; f

= 16 MHz; f s s

≤ 2.2 MSps;

≤ 1.1 MSps; f

DDA

= V

ADC

REF+

= 25 °C

= 3 V;

= 35 MHz; f s

≤ 2.5 MSps; f

2 V < V

ADC

DDA

= V

REF+

= 35 MHz; f s

= entire range

< 3.6 V;

≤ 2.5 MSps;

Total harmonic distortion

1.65 V < V

DDA

= V

REF+

< 3.6 V;

= entire range

Range 1: f

ADC

Range 2: f

ADC

= 35 MHz; f

= 16 MHz; f s s

≤ 2.2 MSps;

≤ 1.1 MSps; f

DDA

= V

ADC

REF+

= 25 °C

= 3 V;

= 35 MHz; f s

≤ 2.5 MSps; f

2 V < V

ADC

DDA

= V

REF+

= 35 MHz; f s

= entire range

< 3.6 V;

≤ 2.5 MSps;

1.65 V < V

DDA

= V

REF+

< 3.6 V;

= entire range

Range 1: f

ADC

Range 2: f

ADC

= 35 MHz; f

= 16 MHz; f s s

≤ 2.2 MSps;

≤ 1.1 MSps;

10.1

9.6

9.5

62.5

59.5

10.2

-74

-73

-70

1. Based on characterization results, not tested in production.

2. ADC DC accuracy values are measured after internal calibration.

3. Injecting negative current on any analog input pin significantly reduces the accuracy of A-to-D conversion of signal on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins susceptible to receive negative current.

4. I/O analog switch voltage booster enabled (BOOSTEN = 1 in the SYSCFG_CFGR1) when V when V

DDA

≥ 2.4 V.

DDA

< 2.4 V and disabled bit dB dB dB

DS13560 Rev 3

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124

Electrical characteristics

Code

4095

4094

4093

STM32G0B1xB/xC/xE

Figure 28. ADC accuracy characteristics

(2)

(3)

(1)

(1) Example of an actual transfer curve

(2) Ideal transfer curve

(3) End point correlation line

T total unadjusted error: maximum deviation between the actual and ideal transfer curves.

O offset error: maximum deviation between the first actual transition and the first ideal one.

G gain error: deviation between the last ideal transition and the last actual one.

D differential linearity error: maximum deviation between actual steps and the ideal ones.

L integral linearity error: maximum deviation between any actual transition and the end point correlation line.

1 LSB ideal

1 2 3 4 5 6 7 4093 4094 4095 (V

AIN

/ V

REF+

)*4095

MSv19880V3

Figure 29. Typical connection diagram using the ADC

DDA

AIN

(1)

AINx

C parasitic

(2)

I lkg

(3)

Sample and hold ADC converter

ADC

12-bit converter

ADC

MS33900V5

1. Refer to Table 61: ADC characteristics

for the values of R

AIN

and C

ADC

2. C parasitic

represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

Table 55: I/O static characteristics for the value of the pad capacitance). A high

C parasitic

value will downgrade conversion accuracy. To remedy this, f

ADC

should be reduced.

3. Refer to Table 55: I/O static characteristics for the values of Ilkg.

General PCB design guidelines

Power supply decoupling should be performed as shown in

Figure 15: Power supply scheme

. The 100 nF capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip.

106/159

DS13560 Rev 3

STM32G0B1xB/xC/xE Electrical characteristics

Symbol

DDA

REF+

BON

BOFF

Parameter

Table 64. DAC characteristics (1)

Analog supply voltage for

DAC ON

Conditions Min

DAC output buffer OFF, DAC_OUT pin not connected (internal connection only)

1.71

Other modes 1.80

Positive reference voltage

DAC output buffer OFF, DAC_OUT pin not connected (internal connection only)

Other modes

1.71

1.80

Resistive load

Output Impedance

Output impedance sample and hold mode, output buffer ON

Output impedance sample and hold mode, output buffer OFF

Capacitive load

DAC output buffer ON connected to V

SSA connected to V

DDA

DAC output buffer OFF

= 2.7 V

= 2.0 V

= 2.7 V

= 2.0 V

DAC output buffer ON

Sample and hold mode

9.6

DAC_OUT t

SETTLING t

WAKEUP

(2)

PSRR

Voltage on DAC_OUT output

DAC output buffer ON

DAC output buffer OFF

±0.5 LSB

Settling time (full scale: for a 12-bit code transition between the lowest and the highest input codes when

DAC_OUT reaches final value ±0.5LSB, ±1 LSB,

±2 LSB, ±4 LSB, ±8 LSB)

Normal mode

DAC output buffer ON

CL ≤ 50 pF,

RL ≥ 5 k Ω

±1 LSB

±2 LSB

±4 LSB

±8 LSB

Normal mode DAC output buffer

OFF, ±1LSB, CL = 10 pF

Wakeup time from off state

(setting the ENx bit in the

DAC Control register) until final value ±1 LSB

DDA

supply rejection ratio

Normal mode DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω

Normal mode DAC output buffer

OFF, CL ≤ 10 pF

Normal mode DAC output buffer ON

CL ≤ 50 pF, RL = 5 k Ω , DC

0.2

Typ

1.7

1.6

1.55

1.48

1.4

11.7

0.1

4.2

-80

Max Unit

3.6 V

DDA

13.8

3.5

16.5

18.0

REF+

– 0.2

REF+

2.9

2.85

2.8

2.75

2.5

k Ω k Ω k Ω k Ω pF

µF

µs

7.5

-28

µs dB

DS13560 Rev 3

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124

Electrical characteristics STM32G0B1xB/xC/xE

Symbol

W_to_W t

SAMP

I leak

CI int t

TRIM

V offset

DDA(DAC)

Table 64. DAC characteristics (1) (continued)

Parameter Conditions Min

Minimum time between two consecutive writes into the

DAC_DORx register to guarantee a correct

DAC_OUT for a small variation of the input code

(1 LSB)

DAC_MCR:MODEx[2:0] = 000 or

001

CL ≤ 50 pF; RL ≥ 5 k Ω

DAC_MCR:MODEx[2:0] = 010 or

011

CL ≤ 10 pF

Sampling time in sample and hold mode (code transition between the lowest input code and the highest input code when

DACOUT reaches final value ±1LSB)

Output leakage current

DAC_OUT pin connected

DAC output buffer

ON, C

= 100 nF

DAC output buffer

OFF, C

= 100 nF

DAC_OUT pin not connected

(internal connection only)

DAC output buffer

OFF

Sample and hold mode,

DAC_OUT pin connected

Internal sample and hold capacitor

Middle code offset trim time DAC output buffer ON

Middle code offset for 1 trim code step

REF+

= 3.6 V

REF+

= 1.8 V

DAC consumption from

DDA

DAC output buffer ON

DAC output buffer OFF

No load, middle code (0x800)

No load, worst code

(0xF1C)

No load, middle code (0x800)

1.4

5.2

Sample and hold mode, C

100 nF

Typ

0.7

10.5

1500

750

315

450

Max

3.5

(3)

8.8

500

670

0.2

315 ₓ on

/(T

T off

)

670 ₓ

T on

/(T

T off

)

Unit

µs ms

µs nA pF

µs

µV

µA

108/159

DS13560 Rev 3

STM32G0B1xB/xC/xE Electrical characteristics

Symbol

Table 64. DAC characteristics (1) (continued)

Parameter Conditions Min Typ Max Unit

DAC output buffer ON

No load, middle code (0x800)

No load, worst code

(0xF1C)

185

340

240

400

DDV(DAC)

DAC consumption from

REF+

DAC output buffer OFF

No load, middle code (0x800)

Sample and hold mode, buffer ON,

= 100 nF, worst case

Sample and hold mode, buffer OFF,

= 100 nF, worst case

155 205

185 ₓ

T on

/(T

T off

)

155 ₓ

T on

/(T

T off

)

400 ₓ

T on

/(T

T off

)

205 ₓ

T on

/(T

T off

)

1. Guaranteed by design.

2. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).

3. Refer to Table 55: I/O static characteristics .

4. T on

is the Refresh phase duration. T off

is the Hold phase duration. Refer to RM0444 reference manual for more details.

µA

Figure 30. 12-bit buffered / non-buffered DAC

Buffered / non-buffered DAC

Buffer

(1)

LOAD

12-bit digital-to-analog converter

DAC_OUTx

LOAD

MSv47959V1

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the

DAC_CR register.

DS13560 Rev 3

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124

Electrical characteristics

Symbol

DNL

INL

Parameter

Table 65. DAC accuracy (1)

Conditions

Differential non linearity

(2) monotonicity

Integral non linearity

(3)

DAC output buffer ON

DAC output buffer OFF

10 bits

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω

DAC output buffer OFF

CL ≤ 50 pF, no RL

Offset

Offset1

Offset error at code 0x800

(3)

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω

Offset error at code 0x001

(4)

DAC output buffer OFF

CL ≤ 50 pF, no RL

DAC output buffer OFF

CL ≤ 50 pF, no RL

REF+

= 3.6 V

= 1.8 V

OffsetCal

Gain

TUE

TUECal

SNR

THD

Offset Error at code 0x800 after calibration

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω

REF+

= 3.6 V

REF+

= 1.8 V

Gain error

Total unadjusted error

(5)

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω

DAC output buffer OFF

CL ≤ 50 pF, no RL

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω

DAC output buffer OFF

CL ≤ 50 pF, no RL

Total unadjusted error after calibration

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω

Signal-to-noise ratio

Total harmonic distortion

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω

1 kHz, BW 500 kHz

DAC output buffer OFF

CL ≤ 50 pF, no RL, 1 kHz

BW 500 kHz

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω , 1 kHz

DAC output buffer OFF

CL ≤ 50 pF, no RL, 1 kHz

STM32G0B1xB/xC/xE

Min

Typ

guaranteed

Max

±2

±4

±5

±7

±0.5

±30

±12

±25

±8

±5

Unit

LSB

71.2

71.6

-78

-79

±23 LSB

dB dB

110/159

DS13560 Rev 3

STM32G0B1xB/xC/xE Electrical characteristics

Symbol Parameter

Table 65. DAC accuracy (1) (continued)

Conditions Min Typ Max Unit

SINAD

ENOB

Signal-to-noise and distortion ratio

Effective number of bits

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω , 1 kHz

DAC output buffer OFF

CL ≤ 50 pF, no RL, 1 kHz

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω , 1 kHz

DAC output buffer OFF

CL ≤ 50 pF, no RL, 1 kHz

70.4

11.4

11.5

dB bits

1. Guaranteed by design.

2. Difference between two consecutive codes - 1 LSB.

3. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095.

4. Difference between the value measured at Code (0x001) and the ideal value.

5. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when buffer is OFF, and from code giving 0.2 V and (V

REF+

– 0.2) V when buffer is ON.

Symbol

DDA

REFBUF_

OUT

TRIM

CL esr

I load

I line_reg

I load_reg

Parameter

Table 66. VREFBUF characteristics

(1)

Conditions Min

Analog supply voltage

Voltage reference output

Normal mode

Degraded mode

I load

= 100 µA

T = 30 °C

(2)

= 0

= 1

= 0

= 1

= 0

= 1

= 0

= 1

Trim step resolution

Load capacitor

Equivalent

Serial Resistor of C load

Static load current

Line regulation 2.8 V ≤ V

DDA

≤ 3.6 V

I load

= 500 µA

I load

= 4 mA

Load regulation 500 μ A ≤ I load

≤ 4 mA Normal mode

2.4

2.8

1.65

2.038

2.497

DDA

-150 mV

DDA

-150 mV

0.5

Typ

2.042

2.5

±0.05

200

100

Max

3.6

2.4

2.8

2.046

2.503

DDA

±0.1

1.5

Unit

µF

Ω

4 mA

1000

500 ppm/V

500 ppm/mA

DS13560 Rev 3

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124

Electrical characteristics STM32G0B1xB/xC/xE

Symbol Parameter

Table 66. VREFBUF characteristics (1) (continued)

Conditions Min Typ Max Unit

Coeff_vrefbuf

Temperature coefficient of

VREFBUF

(3)

-40 °C < T

< +125 °C 50 ppm/ °C t

PSRR

START

Power supply rejection

Start-up time

100 kHz

CL = 0.5 µF

(4)

CL = 1.1 µF

(4)

CL = 1.5 µF (4)

300

500

650

350

650

800 dB

µs

INRUSH

Control of maximum DC current drive on

VREFBUF_OUT during start-up phase (5)

8 mA

DDA(VREFB

UF)

VREFBUF consumption from V

DDA

I load

= 0 µA

I load

= 500 µA

I load

= 4 mA -

µA

1. Guaranteed by design.

2. In degraded mode, the voltage reference buffer can not maintain accurately the output voltage which will follow (V drop voltage).

DDA

3. The temperature coefficient at VREF+ output is the sum of T

Coeff_vrefint

and T

Coeff_vrefbuf

4. The capacitive load must include a 100 nF capacitor in order to cut-off the high frequency noise.

5. To correctly control the VREFBUF inrush current during start-up phase and scaling change, the V the range [2.4 V to 3.6 V] and [2.8 V to 3.6 V] respectively for V

= 0 and V

= 1.

DDA

voltage should be in

Symbol Parameter

Table 67. COMP characteristics (1)

Conditions

DDA

(2)

DDA(SCALER) t

START_SCALER

Analog supply voltage

Comparator input voltage range

Scaler input voltage

Scaler offset voltage

Scaler static consumption from

DDA

Scaler startup time -

BRG_EN=0 (bridge disable)

BRG_EN=1 (bridge enable)

Min Typ Max Unit

1.62

3.6

0 V

DDA

REFINT

±5 ±10 mV

200 300 nA

0.8

1 µA

100 200 µs

112/159

DS13560 Rev 3

STM32G0B1xB/xC/xE Electrical characteristics

Symbol

Table 67. COMP characteristics (1) (continued)

Parameter Conditions t

START

Comparator startup time to reach propagation delay specification

High-speed mode

Medium-speed mode t

Propagation delay

200 mV step;

100 mV overdrive

>200 mV step;

100 mV overdrive

High-speed mode

Medium-speed mode

High-speed mode

Medium-speed mode

V offset

Comparator offset error

Full common mode range

V hys

DDA(COMP)

Comparator hysteresis

Comparator consumption from

DDA

No hysteresis

Low hysteresis

Medium hysteresis

High hysteresis

Static

Medium-speed mode;

No deglitcher

With 50 kHz and ±100 mV overdrive square signal

Static

Medium-speed mode;

With deglitcher

With 50 kHz and ±100 mV overdrive square signal

Static

High-speed mode With 50 kHz and ±100 mV overdrive square signal

1. Guaranteed by design.

2. Refer to

Table 27: Embedded internal voltage reference .

Min Typ Max Unit

µs

30 50

0.3

0.6

1.2

µs ns

µs

±5 ±20 mV

7.5

8 -

250 400

250 -

µA

5.3.21 Temperature sensor characteristics

Symbol

Table 68. TS characteristics

Parameter

(1)

Avg_Slope

(2)

linearity with temperature

Average slope

Voltage at 30°C (±5 °C)

(3) t

START(TS_BUF)

(1) Sensor Buffer Start-up time in continuous mode

(4)

Min

2.3

0.742

START

(1) Start-up time when entering in continuous mode

(4)

Typ

±1

2.5

0.76

Max

±2

2.7

0.785

120

Unit

°C mV/°C

µs

DS13560 Rev 3

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124

Electrical characteristics STM32G0B1xB/xC/xE

Symbol

Table 68. TS characteristics (continued)

Parameter Min Typ Max Unit t

S_temp

(1) ADC sampling time when reading the temperature 5 µs

DD(TS)

(1)

Temperature sensor consumption from V

DD selected by ADC

, when

4.7

1. Guaranteed by design.

2. Based on characterization results, not tested in production.

3. Measured at V

DDA

= 3.0 V ±10 mV. The V

ADC conversion result is stored in the TS_CAL1 byte.

4. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes.

µA

5.3.22 V

BAT monitoring characteristics

Symbol

Table 69. V

BAT

monitoring characteristics

Parameter

(1)

Resistor bridge for V

BAT

Ratio on V

BAT

measurement

Error on Q t

S_vbat

(1) ADC sampling time when reading the VBAT

1. Guaranteed by design.

Min

-10

Typ

Max

Unit k Ω

µs

Symbol

Table 70. V

BAT

charging characteristics

Parameter Conditions Min Typ

Battery charging resistor

VBRS = 0

VBRS = 1 -

1.5

Max

Unit k Ω

The parameters given in the following tables are guaranteed by design. Refer to

Section 5.3.14: I/O port characteristics

for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output).

Symbol t res(TIM) f

EXT

Res

TIM

Parameter

Table 71. TIMx

(1)

characteristics

Conditions Min

Timer resolution time

Timer external clock frequency on CH1 to CH4 f

TIMxCLK

= 64 MHz

TIMxCLK

= 64 MHz

TIMx (except TIM2)

Timer resolution

TIM2

15.625

Max

TIMxCLK

Unit t

TIMxCLK ns

MHz bit

114/159

DS13560 Rev 3

STM32G0B1xB/xC/xE Electrical characteristics

Symbol

Table 71. TIMx (1) characteristics (continued)

Parameter Conditions Min t

COUNTER

1 t

MAX_COUNT

16-bit counter clock period

Maximum possible count with

32-bit counter f

TIMxCLK

= 64 MHz

TIMxCLK

= 64 MHz

0.015625

1. TIMx

, is used as a general term in which x stands for 1, 2, 3, 4, 5, 6, 7, 8, 15, 16 or 17.

Max Unit

65536

1024 t

TIMxCLK

µs

65536 × 65536 t

TIMxCLK

67.10

Table 72. IWDG min/max timeout period at 32 kHz LSI clock

(1)

Prescaler divider PR[2:0] bits Min timeout RL[11:0]= 0x000 Max timeout RL[11:0]= 0xFFF

/16

/32

/64

/128

/256

6 or 7

0.125

0.250

0.500

1.0

2.0

4.0

8.0

512

1024

2048

4096

8192

16384

32768

1. The exact timings further depend on the phase of the APB interface clock versus the LSI clock, which causes an uncertainty of one RC period.

Unit ms

I

C-bus interface characteristics

The I

C-bus interface meets timing requirements of the I

C-bus specification and user manual rev. 03 for:

• Standard-mode (Sm): with a bit rate up to 100 kbit/s

• Fast-mode (Fm): with a bit rate up to 400 kbit/s

• Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.

The timings are guaranteed by design as long as the I2C peripheral is properly configured

(refer to the reference manual RM0444) and when the I2CCLK frequency is greater than the minimum shown in the following table.

DS13560 Rev 3

115/159

124

Electrical characteristics

Symbol f

I2CCLK(min)

Table 73. Minimum I2CCLK frequency

Parameter Condition

Minimum I2CCLK frequency for correct operation of I2C peripheral

Fast-mode

Fast-mode Plus

Standard-mode

Analog filter enabled

DNF = 0

Analog filter disabled

DNF = 1

Analog filter enabled

DNF = 0

Analog filter disabled

DNF = 1

STM32G0B1xB/xC/xE

Typ

Unit

MHz

The SDA and SCL I/O requirements are met with the following restrictions: the SDA and

SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and V

DDIO1

is disabled, but is still present. Only FT_f I/O pins support Fm+ low-level output current maximum requirement. Refer to

Section 5.3.14: I/O port characteristics for the I2C I/Os characteristics.

All I2C SDA and SCL I/Os embed an analog filter. Refer to the following table for its characteristics:

Symbol

Table 74. I2C analog filter characteristics

(1)

Parameter t

Limiting duration of spikes suppressed by the filter

(2)

1. Based on characterization results, not tested in production.

2. Spikes shorter than the limiting duration are suppressed.

Min

Max

260

Unit ns

SPI/I

S characteristics

Unless otherwise specified, the parameters given in

Table 75

for SPI are derived from tests performed under the ambient temperature, f

PCLKx frequency and supply voltage conditions summarized in

Table 24: General operating conditions . The additional general conditions

are:

• OSPEEDRy[1:0] set to 11 (output speed)

• capacitive load C = 30 pF

• measurement points at CMOS levels: 0.5 x V

Refer to Section 5.3.14: I/O port characteristics

for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI).

116/159

DS13560 Rev 3

STM32G0B1xB/xC/xE Electrical characteristics

Symbol

SCK

1/t c(SCK)

SPI clock frequency t su(NSS) t h(NSS)

NSS setup time

NSS hold time t w(SCKH)

SCK high time t w(SCKL)

SCK low time t su(MI) t su(SI) t h(MI) t h(SI) t a(SO) t dis(SO) t v(SO) t v(MO)

Parameter

Table 75. SPI characteristics (1)

Conditions Min

Master mode

1.65 < V

Range 1

< 3.6 V

Master transmitter

1.65 < V

Range 1

< 3.6 V

Slave receiver

1.65 < V

Range 1

< 3.6 V

Slave transmitter/full duplex

2.7 < V

< 3.6 V

Range 1

Slave transmitter/full duplex

1.65 < V

Range 1

< 3.6 V

1.65 < V

Range 2

< 3.6 V

Slave mode, SPI prescaler = 2

Master mode

4 ₓ T

PCLK

2 ₓ T

PCLK

- 1.5

PCLK

- 1.5

Master data input setup time

Slave data input setup time

Master data input hold time

Slave data input hold time

Data output access time Slave mode

Data output disable time Slave mode

2.7 < V

Range 1

< 3.6 V

Slave data output valid time

1.65 < V

Range 1

< 3.6 V

1.65 < V

< 3.6 V

Voltage Range 2

Master data output valid time

Typ

PCLK

Max Unit

MHz

PCLK

+ 1.5

PCLK

+ 1.5

14 ns ns ns ns ns ns ns ns ns ns ns ns

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124

Electrical characteristics

Symbol Parameter

Table 75. SPI characteristics (1) (continued)

Conditions t t h(SO) h(MO)

Slave data output hold time

Master data output hold time

1. Based on characterization results, not tested in production.

Min

STM32G0B1xB/xC/xE

Typ

Figure 31. SPI timing diagram - slave mode and CPHA = 0

Max

Unit ns ns

NSS input t su(NSS) t w(SCKH) t c(SCK) t r(SCK) t h(NSS)

CPHA=0

CPOL=0

CPHA=0

CPOL=1 t a(SO)

MISO output t w(SCKL)

First bit OUT t h(SI) t v(SO) t h(SO)

Next bits OUT t f(SCK)

Last bit OUT t dis(SO) t su(SI)

MOSI input First bit IN Next bits IN Last bit IN

MSv41658V1

Figure 32. SPI timing diagram - slave mode and CPHA = 1

NSS input t su(NSS) t w(SCKH) t c(SCK) t f(SCK) t h(NSS)

CPHA=1

CPOL=0

CPHA=1

CPOL=1

MISO output

MOSI input t a(SO) t w(SCKL) t v(SO)

First bit OUT t su(SI) t h(SI)

First bit IN t h(SO)

Next bits OUT

Next bits IN t r(SCK) t dis(SO)

Last bit OUT

Last bit IN

MSv41659V1

1. Measurement points are done at CMOS levels: 0.3 V

and 0.7 V

118/159

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STM32G0B1xB/xC/xE

Figure 33. SPI timing diagram - master mode

Electrical characteristics

NSS input

High

CPHA= 0

CPOL=0

CPHA= 0

CPOL=1 tc(SCK)

CPHA=1

CPOL=0

CPHA=1

CPOL=1

MISO

INP UT

MOSI

OUTPUT tsu(MI) tw(SCKH) tw(SCKL)

MSB IN th(MI)

MSB OUT tv(MO)

BIT6 IN

B I T1 OUT th(MO)

1. Measurement points are set at CMOS levels: 0.3 V

and 0.7 V

Table 76. I

S characteristics

(1)

Symbol Parameter Conditions f

MCK f

I2S main clock output

I2S clock frequency f

MCK

= 256 x Fs; (Fs = audio sampling frequency)

Fs min

= 8 kHz; Fs max

= 192 kHz;

Master data

Slave data

I2S clock frequency duty cycle

Slave receiver

Min

2.048

30 tr(SCK) tf(SCK)

LSB IN

LSB OUT

Max ai14136c

Unit

49.152

64xFs

MHz

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124

Electrical characteristics STM32G0B1xB/xC/xE

Symbol

Table 76. I 2 S characteristics (1) (continued)

Parameter Conditions t v(WS) t h(WS) t su(WS) t h(WS) t su(SD_MR) t su(SD_SR) t h(SD_MR) t h(SD_SR)

WS valid time

WS hold time

WS setup time

WS hold time

Data input setup time

Data input hold time

Master mode

Slave mode

Master receiver

Slave receiver

Master receiver

Slave receiver t v(SD_ST)

Data output valid time - slave transmitter after enable edge; 2.7 < V

< 3.6V after enable edge; 1.65 < V

< 3.6V

t t t v(SD_MT) h(SD_ST) h(SD_MT)

Data output valid time master transmitter

Data output hold time - slave transmitter

Data output hold time - master transmitter after enable edge after enable edge after enable edge

1. Based on characterization results, not tested in production.

Figure 34. I

S slave timing diagram (Philips protocol) tc(CK)

Min

4.5

Max

5.5

CPOL = 0

Unit ns

CPOL = 1 tw(CKH) tw(CKL) th(WS)

WS input

SDtransmit tsu(WS)

LSB transmit(2) tsu(SD_SR)

LSB receive(2)

MSB transmit

MSB receive tv(SD_ST)

Bitn transmit th(SD_SR)

Bitn receive th(SD_ST)

LSB receive SDreceive

MSv39721V1

1. Measurement points are done at CMOS levels: 0.3 V

DDIO1

and 0.7 V

DDIO1

2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

120/159

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STM32G0B1xB/xC/xE Electrical characteristics

Figure 35. I 2 S master timing diagram (Philips protocol)

90%

10% tf(CK) tr(CK) tc(CK)

CPOL = 0

CPOL = 1 tv(WS)

WS output tw(CKH)

SDtransmit

SDreceive tw(CKL) th(WS) tv(SD_MT)

LSB transmit(2) tsu(SD_MR)

LSB receive(2)

MSB transmit

MSB receive

Bitn transmit th(SD_MR)

Bitn receive th(SD_MT)

LSB transmit

LSB receive

MSv39720V1

1. Based on characterization results, not tested in production.

2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

USART characteristics

Unless otherwise specified, the parameters given in

Table 77 for USART are derived from

tests performed under the ambient temperature, f

PCLKx frequency and supply voltage

conditions summarized in Table 24: General operating conditions

. The additional general conditions are:

• OSPEEDRy[1:0] set to 10 (output speed)

• capacitive load C = 30 pF

• measurement points at CMOS levels: 0.5 x V

Refer to Section 5.3.14: I/O port characteristics

for more details on the input/output alternate function characteristics (NSS, CK, TX, and RX for USART).

Symbol f

Parameter

USART clock frequency

Table 77. USART characteristics

Conditions Min

Master mode

Slave mode -

Typ

Max

Unit

MHz

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124

Electrical characteristics STM32G0B1xB/xC/xE

Symbol t su(NSS) t h(NSS) t w(CKH) t w(CKL) t su(RX) t h(RX) t v(TX) t h(TX)

Parameter

NSS setup time

NSS hold time

CK high time

CK low time

Data input setup time

Data input hold time

Data output valid time

Data output hold time

Table 77. USART characteristics

Conditions Min

Slave mode

Slave mode t ker

+ 2

Master mode

Slave mode

Master mode

Slave mode

Master mode

Slave mode

Master mode

Slave mode

1 / f

/ 2

- 1

t ker

+ 2

0.5

Typ

0.5

1 / f

/ 2

Max

1 / f

/ 2

+ 1

Unit ns

USB full speed (FS) characteristics

The STM32G0B1xB/xC/xE USB interface is fully compliant with the USB specification version 2.0 and is USB-IF certified (for Full-speed device operation).

Symbol

Table 78. USB DC electrical characteristics

Parameter Conditions Min (1) Typ Max (1) Unit

DDUSB

(3)

USB full speed transceiver operating voltage

Differential input sensitivity

Differential input common mode range

Single ended receiver input threshold

Static output level low

Static output level high

Pull down resistor on PA11,

PA12 (USB_FS_DP/DM)

Pull Up Resistor on PA12

(USB_FS_DP)

Pull Up Resistor on PA12

(USB_FS_DP)

Over VCM range

Includes V

DI range

of 1.5

k Ω to 3.6 V (4)

of 15 k Ω to V

(4)

= V

, during idle

= V

SS reception

during

3.0

(2)

0.2

0.8

2.8

14.25

3.6

2.5

2.0

0.3

3.6

24.8

0.9

1.25

1.575

k Ω

1.425

2.25

3.09

1. All the voltages are measured from the local ground potential.

2. The USB full speed transceiver functionality is ensured down to 2.7 V but not the full USB full speed electrical characteristics which are degraded in the 2.7-to-3.0 V V

voltage range.

3. Guaranteed by design.

4. R

is the load connected on the USB full speed drivers.

V k Ω k Ω

122/159

DS13560 Rev 3

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Note:

Electrical characteristics

When VBUS sensing feature is enabled, PA9 should be left at its default state (floating input), not as alternate function. A typical 200 µA current consumption of the sensing block

(current to voltage conversion to determine the different sessions) can be observed on PA9 when the feature is enabled.

Differential data lines

CRS

Figure 36. USB timings – definition of data signal rise and fall time

Cross over points

SS t f t r ai14137b

Table 79. USB electrical characteristics

(1)

Driver characteristics

Symbol Parameter Conditions Min Max Unit t rLS t fLS t rfmLS t rFS t fFS t rfmFS

CRS

DRV

Rise time in LS

Fall time in LS

Rise time in FS

Fall time in FS

(2)

Rise/ fall time matching in LS

(2)

Rise/ fall time matching in FS

Output signal crossover voltage (LS/FS)

Output driver impedance

(3)

L t r

/t f f

= 200 to 600 pF

= 50 pF

Driving high or low

1.3

300

125

111

2.0

1. Guaranteed by design.

2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB

Specification - Chapter 7 (version 2.0).

3. No external termination series resistors are required on DP (D+) and DM (D-) pins since the matching impedance is included in the embedded driver.

ns ns

% ns ns

Ω

Symbol

DD(USBBCD)

Table 80. USB BCD DC electrical characteristics

(1)

Parameter Conditions Min.

Typ.

Max.

Unit

Primary detection mode consumption

Secondary detection mode consumption

300

DS13560 Rev 3

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124

Electrical characteristics STM32G0B1xB/xC/xE

Symbol

Table 80. USB BCD DC electrical characteristics (1) (continued)

Parameter Conditions Min.

Typ.

Max.

Unit

RDAT_LKG

VDAT_LKG

RDCP_DAT

VLGC_HI

VLGC_LOW

VLGC

VDAT_REF

VDP_SRC

VDM_SRC

IDP_SINK

IDM_SINK

1. Guaranteed by design.

Data line leakage resistance

Data line leakage voltage

Dedicated charging port resistance across D+/D-

Logic high

Logic low

Logic threshold

Data detect voltage

D+ source voltage

D- source voltage

D+ sink current

D- sink current

300

0.0

2.0

0.8

0.25

0.5

3.6

200

3.6

0.8

2.0

0.4

0.7

175

175 k Ω

Ω

μ A

CAN (controller area network) interface

Refer to Section 5.3.14: I/O port characteristics

for more details on the input/output alternate function characteristics (FDCANx_TX and FDCANx_RX).

UCPD1 and UCPD2 controllers comply with USB Type-C Rev.1.2 and USB Power Delivery

Rev. 3.0 specifications.

Symbol

Parameter

Table 81. UCPD operating conditions

Conditions Min

UCPD operating supply voltage

Sink mode only

Sink and source mode

3.0

3.135

Typ

3.3

Max

3.6

3.465

Unit

124/159

DS13560 Rev 3

STM32G0B1xB/xC/xE Package information

6.1

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com

ECOPACK is an ST trademark.

UFQFPN32 package information

UFQFPN32 is a 32-pin, 5x5 mm, 0.5 mm pitch ultra-thin fine-pitch quad flat package.

Figure 37. UFQFPN32 package outline

D e

A3 ddd C

SEATINGPLANE b

D1 e

E2 b

E1 E

D2 L

PIN 1 Identifier

A0B8_ME_V3

A3 b

(2)

1. Drawing is not to scale.

2. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this backside pad to PCB ground.

Table 82. UFQFPN32 package mechanical data millimeters inches

(1)

Symbol

Min

0.500

0.000

0.180

4.900

3.400

4.900

Typ

0.550

0.020

0.152

0.230

5.000

3.500

5.000

Max

0.600

0.050

0.280

5.100

3.600

5.100

Min

0.0197

0.000

0.0071

0.1929

0.1339

0.1929

Typ

0.0217

0.0007

0.0060

0.0091

0.1969

0.1378

0.1969

Max

0.0236

0.0020

0.0110

0.2008

0.1417

0.2008

DS13560 Rev 3

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154

Package information

STM32G0B1xB/xC/xE

Table 82. UFQFPN32 package mechanical data (continued) millimeters inches (1)

Symbol

Min Typ Max Min

E2 e

L ddd

3.400

0.300

3.500

0.500

0.400

3.600

0.500

0.080

0.1339

0.0118

1. Values in inches are converted from mm and rounded to 4 decimal digits.

2. Dimensions D and E do not include mold protrusion, not to exceed 0,15mm.

Typ

0.1378

0.0197

0.0157

Figure 38. Recommended footprint for UFQFPN32 package

5.30

3.80

0.60

Max

0.1417

0.0197

0.0031

3.45

5.30

3.80

0.30

3.45

0.50

0.75

3.80

A0B8_FP_V2

1. Dimensions are expressed in millimeters

126/159

DS13560 Rev 3

STM32G0B1xB/xC/xE Package information

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 39. UFQFPN32 package marking example

Product identification

(1)

32G0B1KCU6

Y WW R

Date code

Revision code

Pin 1 identifier

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.

DS13560 Rev 3

127/159

154

Package information

6.2 LQFP32 package information

LQFP32 is a 32-pin, 7 x 7 mm low-profile quad flat package.

SEATING

PLANE

Figure 40. LQFP32 package outline

STM32G0B1xB/xC/xE ccc C

0.25 mm

GAUGE PLANE

128/159

PIN 1

IDENTIFICATION

8 e

1. Drawing is not to scale.

Symbol

Min

0.050

1.350

Table 83. LQFP32 mechanical data millimeters

Typ

1.400

Max

1.600

0.150

1.450

Min

0.0020

0.0531

inches

(1)

Typ

0.0551

5V_ME_V2

Max

0.0630

0.0059

0.0571

DS13560 Rev 3

STM32G0B1xB/xC/xE Package information

Table 83. LQFP32 mechanical data (continued) millimeters inches (1)

Symbol

Min Typ Max Min

E1 b c

0.300

0.090

8.800

6.800

8.800

6.800

0.370

9.000

7.000

5.600

9.000

7.000

0.450

0.200

9.200

7.200

9.200

7.200

E3 e

0.450

5.600

0.800

0.600

1.000

0.750

0.0177

k ccc

0°

3.5°

7°

0.100

0°

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.0118

0.0035

0.3465

0.2677

0.3465

0.2677

Typ

0.2205

0.0315

0.0236

0.0394

3.5°

0.0146

0.3543

0.2756

0.2205

0.3543

0.2756

Figure 41. Recommended footprint for LQFP32 package

0.80

Max

0.0295

7°

0.0039

0.0177

0.0079

0.3622

0.2835

0.3622

0.2835

0.30

1.20

0.50

7.30

9.70

6.10

7.30

1 8

1.20

6.10

9.70

5V_FP_V2

1. Dimensions are expressed in millimeters.

DS13560 Rev 3

129/159

154

Package information STM32G0B1xB/xC/xE

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 42. LQFP32 package marking example

STM32G

0B1KET6

Product identification

(1)

Date code

Revision code

Pin 1 identifier R

130/159

DS13560 Rev 3

STM32G0B1xB/xC/xE

6.3 UFQFPN48 package information

Package information

UFQFPN48 is a 48-lead, 7x7 mm, 0.5 mm pitch, ultra-thin fine-pitch quad flat package

Pin 1 identifier laser marking area

Figure 43. UFQFPN48 package outline

E E

Y e b

Detail Y ddd

Seating plane

Exposed pad area

C 0.500x45° pin1 corner

Detail Z

R 0.125 typ.

A0B9_ME_V3

1. Drawing is not to scale.

2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.

3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this back-side pad to PCB ground.

Table 84. UFQFPN48 package mechanical data millimeters inches

(1)

Symbol

Min

0.500

0.000

6.900

5.500

Typ

0.550

0.020

7.000

5.600

Max

0.600

0.050

7.100

5.700

Min

0.0197

0.0000

0.2717

0.2165

Typ

0.0217

0.0008

0.2756

0.2205

Max

0.0236

0.0020

0.2795

0.2244

DS13560 Rev 3

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154

Package information STM32G0B1xB/xC/xE

Table 84. UFQFPN48 package mechanical data (continued) millimeters inches (1)

Symbol

Min Typ Max Min

T b e ddd

0.300

0.200

0.400

0.152

0.250

0.500

0.300

0.080

0.0118

0.0079

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Typ

0.0157

0.0060

0.0098

0.0197

Figure 44. Recommended footprint for UFQFPN48 package

Max

0.0197

0.0118

0.0031

7.30

6.20

48 37

7.30

6.20

0.20

0.30

0.55

5.60

5.80

1. Dimensions are expressed in millimeters.

5.60

0.50

0.75

5.80

A0B9_FP_V2

132/159

DS13560 Rev 3

STM32G0B1xB/xC/xE Package information

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 45. UFQFPN48 package marking example

STM32G0B1

CEU6

Product identification

(1)

Date code

Revision code

Pin 1 identifier

DS13560 Rev 3

133/159

154

Package information

6.4 LQFP48 package information

LQFP48 is a 48-pin, 7 x 7 mm low-profile quad flat package.

SEATING

PLANE

Figure 46. LQFP48 package outline

STM32G0B1xB/xC/xE ccc C b

0.25 mm

GAUGE PLANE

134/159

PIN 1

IDENTIFICATION

12 e

Symbol c

A2 b

1. Drawing is not to scale.

Min

0.050

1.350

0.170

0.090

8.800

6.800

Table 85. LQFP48 mechanical data millimeters

Typ

1.400

0.220

9.000

7.000

5.500

Max

1.600

0.150

1.450

0.270

0.200

9.200

7.200

Min

0.0020

0.0531

0.0067

0.0035

0.3465

0.2677

inches

(1)

Typ

0.0551

0.0087

0.3543

0.2756

0.2165

5B_ME_V2

Max

0.0630

0.0059

0.0571

0.0106

0.0079

0.3622

0.2835

DS13560 Rev 3

STM32G0B1xB/xC/xE Package information

Table 85. LQFP48 mechanical data (continued) millimeters inches (1)

Symbol

Min Typ Max Min

L1 k e

L ccc

8.800

6.800

0.450

0°

9.000

7.000

5.500

0.500

0.600

1.000

3.5°

9.200

7.200

0.750

7°

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.3465

0.2677

0.0177

0°

Typ

0.3543

0.2756

0.2165

0.0197

0.0236

0.0394

3.5°

Figure 47. Recommended footprint for LQFP48 package

0.50

1.20

Max

0.3622

0.2835

0.0295

7°

0.0031

0.30

36 25

0.20

7.30

9.70

5.80

7.30

1 12

1.20

5.80

9.70

ai14911d

1. Dimensions are expressed in millimeters.

DS13560 Rev 3

135/159

154

Package information STM32G0B1xB/xC/xE

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 48. LQFP48 package marking example

STM32G0B1

CET6

Product identification

(1)

Date code

Revision code

Pin 1 identifier

136/159

DS13560 Rev 3

STM32G0B1xB/xC/xE

6.5 WLCSP52 package information

Package information

WLCSP52 is a 52-ball, 3.09 x 3.15 mm, 0.4 mm pitch, wafer-level chip-scale package.

Figure 49. WLCSP52 - Outline

E e2

13 12 11 10 9 8 7 6 5 4 3 2 1

A1 BALL ORIENTATION

H e1

DETAIL B

(4x) aaa

BOTTOM VIEW

BUMP

DETAIL A eee Z

TOP VIEW bbb Z

SIDE VIEW

FRONT VIEW b(52x) ccc ddd

X Y

DETAIL A

SEATING PLANE

DETAIL B

B0BG_WLCSP52_ME_V1

1. Drawing is not to scale.

2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.

3. Primary datum Z and seating plane are defined by the spherical crowns of the bump.

4. Bump position designation per JESD 95-1, SPP-010.

Table 86. WLCSP52 - Mechanical data millimeters inches

(1)

Symbol

(2)

(3)

Min

Typ

0.17

0.38

0.025

Max

0.58

Min

Typ

0.007

0.015

0.001

Max

0.023

DS13560 Rev 3

137/159

154

Package information STM32G0B1xB/xC/xE

Table 86. WLCSP52 - Mechanical data (continued) millimeters inches (1)

Symbol

Min Typ Max Min Typ Max e e1 e2

(4)

N b

E aaa bbb ccc ddd eee

0.23

3.06

3.12

0.26

3.09

3.15

0.40

2.40

2.42

0.35

0.36

0.28

3.12

3.18

0.10

0.05

0.58

0.009

0.120

0.123

0.010

0.122

0.124

0.016

0.094

0.095

0.014

1. Values in inches are converted from mm and rounded to 3 decimal digits.

2. The maximum total package height is calculated by the RSS method (Root Sum Square) using nominal and tolerances values of A1 and A2.

3. Back side coating. Nominal dimension is rounded to the 3rd decimal place resulting from process capability.

4. Calculated dimensions are rounded to the 3rd decimal place

0.004

0.002

0.023

0.011

0.123

0.125

Figure 50. WLCSP52 - Recommended footprint

138/159

Dpad

Dsm

DS13560 Rev 3

BGA_WLCSP_FT_V1

STM32G0B1xB/xC/xE Package information

Table 87. WLCSP52 - Recommended PCB design rules

Dimension Recommended values

Pitch

Dpad

Dsm

Stencil opening

Stencil thickness

0.4 mm

0,225 mm

0.290 mm typ. (depends on soldermask registration tolerance)

0.250 mm

0.100 mm

Device marking

The following figure gives an example of topside marking orientation versus ball A1 identifier location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks that identify the parts throughout supply chain operations, are not indicated below.

Figure 51. WLCSP52 package marking example

Pin 1 identifier

Product identification

(1)

G0B1E6

Y WW R

Date code

Revision code

DS13560 Rev 3

139/159

154

Package information

6.6 UFBGA64 package information

STM32G0B1xB/xC/xE

UFBGA64 is a 64-ball, 5 x 5 mm, 0.5 mm pitch ultra-low-profile fine-pitch ball grid array package.

Z Seating plane

A3 A2 e

Figure 52. UFBGA64 package outline

F ddd Z

A1 A

A1 ball identifier

A1 ball index area

140/159

D1 D e

8 1

BOTTOM VIEW

Øb (64 balls)

Ø eee fff

Z Y X

A4 b

E1 e

1. Drawing is not to scale.

Table 88. UFBGA64 package mechanical data millimeters inches

(1)

Symbol

Min

0.460

0.050

0.400

0.080

0.270

0.170

4.850

3.450

4.850

3.450

0.700

Typ

0.530

0.080

0.450

0.130

0.320

0.280

5.000

3.500

5.000

3.500

0.500

0.750

Max

0.600

0.110

0.500

0.180

0.370

0.330

5.150

3.550

5.150

3.550

0.800

Min

0.0181

0.0020

0.0157

0.0031

0.0106

0.0067

0.1909

0.1358

0.1909

0.1358

0.0276

Typ

0.0209

0.0031

0.0177

0.0051

0.0126

0.0110

0.1969

0.1378

0.1969

0.1378

0.0197

0.0295

TOP VIEW

Max

0.0236

0.0043

0.0197

0.0071

0.0146

0.0130

0.2028

0.1398

0.2028

0.1398

0.0315

A019_ME_V1

DS13560 Rev 3

STM32G0B1xB/xC/xE Package information

Table 88. UFBGA64 package mechanical data (continued) millimeters inches (1)

Symbol

Min Typ Max Min

A ddd eee fff

0.460

0.530

0.600

0.080

0.150

0.050

0.0181

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Typ

0.0209

Max

0.0236

0.0031

0.0059

0.0020

Figure 53. Recommended footprint for UFBGA64 package

Dpad

Pitch

Dpad

Dsm

BGA_WLCSP_FT_V1

Table 89. Recommended PCB design rules for UFBGA64 package

Dimension Recommended values

Stencil opening

Stencil thickness

Pad trace width

0.5

0.280 mm

0.370 mm typ. (depends on the solder mask registration tolerance)

0.280 mm

Between 0.100 mm and 0.125 mm

0.100 mm

DS13560 Rev 3

141/159

154

Package information STM32G0B1xB/xC/xE

Device marking

The following figure gives an example of topside marking orientation versus ball A1 identifier location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 54. UFBGA64 package marking example

G0B1RE6N Product identification

(1)

Date code

Revision code

Will be provided later

Y WW R

Pin 1 identifier

142/159

DS13560 Rev 3

STM32G0B1xB/xC/xE

6.7 LQFP64 package information

LQFP64 is a 64-pin, 10 x 10 mm low-profile quad flat package.

SEATING PLANE

Figure 55. LQFP64 package outline

Package information

0.25 mm

GAUGE PLANE ccc C

K D

D3 L1

48 33

32 b

64 17

PIN 1

IDENTIFICATION

1 e

16 c

A2 b

1. Drawing is not to scale.

Table 90. LQFP64 package mechanical data millimeters inches

(1)

Symbol

Min

0.050

1.350

0.170

0.090

Typ

1.400

0.220

12.000

10.000

7.500

12.000

10.000

Max

1.600

0.150

1.450

0.270

0.200

Min

0.0020

0.0531

0.0067

0.0035

Typ

0.0551

0.0087

0.4724

0.3937

0.2953

0.4724

0.3937

5W_ME_V3

Max

0.0630

0.0059

0.0571

0.0106

0.0079

DS13560 Rev 3

143/159

154

Package information STM32G0B1xB/xC/xE

Table 90. LQFP64 package mechanical data (continued) millimeters inches (1)

Symbol

Min Typ Max Min

L1 ccc

E3 e

0°

0.450

7.500

0.500

3.5°

0.600

1.000

7°

0.750

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0°

0.0177

Typ

0.2953

0.0197

3.5°

0.0236

0.0394

Figure 56. Recommended footprint for LQFP64 package

Max

7°

0.0295

0.0031

0.5

0.3

12.7

10.3

1.2

7.8

12.7

16 ai14909c

1. Dimensions are expressed in millimeters.

144/159

DS13560 Rev 3

STM32G0B1xB/xC/xE Package information

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 57. LQFP64 package marking example

STM32G0B1

RET6

Will be provided later

Y WW

Product identification

(1)

Date code

Revision code

Pin 1 identifier

DS13560 Rev 3

145/159

154

Package information

6.8 LQFP80 package information

This LQFP is a 80 pin, 12 x 12 mm low-profile quad flat package.

SEATING

PLANE

Figure 58. LQFP80 - Outline

STM32G0B1xB/xC/xE c

0.25 mm

GAUGE PLANE ccc C

L k

60 41

146/159

PIN 1

IDENTIFICATION

1 e

1. Drawing is not to scale.

Dim.

A2 b c

Min

0.050

1.350

0.170

0.090

Table 91. LQFP80 - Mechanical data mm inches

(1)

Typ

1.400

0.220

14.000

12.000

Max

1.600

0.150

1.450

0.270

0.200

Min

0.0020

0.0531

0.0067

0.0035

Typ

0.0551

0.0087

0.5512

0.4724

9X_ME

Max

0.0630

0.0059

0.0571

0.0106

0.0079

DS13560 Rev 3

STM32G0B1xB/xC/xE Package information

Table 91. LQFP80 - Mechanical data (continued) mm inches (1)

Dim.

Min Typ Max Min

E3 e

E1 ccc k

0.450

0.0°

9.500

14.000

12.000

9.500

0.500

0.600

1.000

0.750

0.080

7.0°

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.0177

0.0°

Typ

0.3740

0.5512

0.4724

0.3740

0.0197

0.0236

0.0394

Figure 59. LQFP80 - Recommended footprint

Max

0.0295

0.0031

7.0°

0.5

1. Dimensions are expressed in millimeters.

9.8

14.7

1.2

9X_LQFP80_FP

DS13560 Rev 3

147/159

154

Package information STM32G0B1xB/xC/xE

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 60. LQFP80 package marking example

STM32G0B1

Will be provided later

Y WW

Product identification

(1)

Revision code

Date code

Pin 1 identifier

148/159

DS13560 Rev 3

STM32G0B1xB/xC/xE

6.9 UFBGA100 package information

Package information

UFBGA100 is a 100-ball, 7 x 7 mm, 0.5 mm pitch ultra-fine-profile ball grid array package.

Z Seating plane

A3 A2 e

Figure 61. UFBGA100 package outline

Z ddd Z

A1 A

A1 ball identifier

A1 ball index area

D1 D e

12 1

BOTTOM VIEW

Øb (100 balls)

Ø eee

M Z Y X

Ø fff M Z

TOP VIEW

A0C2_ME_V5

1. Drawing is not to scale.

Symbol

Min.

A -

A1 -

A2 -

A3 -

Table 92. UFBGA100 package mechanical data millimeters inches

(1)

Typ.

Max.

Min.

0.110 -

0.450 -

0.130

Typ.

Max.

0.0177

0.0051

0.0236

0.0043

0.0094

0.0126 -

0.2165 ddd 0.080

0.2165 e - -

Z 0.750 0.0295

0.0031

DS13560 Rev 3

149/159

154

Package information STM32G0B1xB/xC/xE

Table 92. UFBGA100 package mechanical data (continued) millimeters inches (1)

Symbol

Min.

Typ.

Max.

Min.

eee fff -

0.150

0.050

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Typ.

Figure 62. Recommended footprint for UFBGA100 package

Max.

0.0059

0.0020

Dpad

Dsm

A0C2_FP_V1

Pitch

Dpad

Dsm

Stencil opening

Stencil thickness

Table 93. UFBGA100 recommended PCB design rules

Dimension Recommended values

0.5

0.280 mm

0.370 mm typ. (depends on the solder mask registration tolerance)

0.280 mm

Between 0.100 mm and 0.125 mm

150/159

DS13560 Rev 3

STM32G0B1xB/xC/xE Package information

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 63. UFBGA100 package marking example

STM32G

0B1VEI6

Will be provided later

Y WW R

Product identification

(1)

Date code

Revision code

Pin 1 identifier

DS13560 Rev 3

151/159

154

Package information STM32G0B1xB/xC/xE

LQFP100 is a 100-pin, 14 x 14 mm low-profile quad flat package.

Figure 64. LQFP100 package outline

SEATING PLANE

C c ccc C

75 51

0.25 mm

GAUGE PLANE

L K

152/159

100

PIN 1

IDENTIFICATION

1 25 e c

A2 b

1. Drawing is not to scale.

Table 94. LQFP100 package mechanical data millimeters inches

(1)

Symbol

Min

0.050

1.350

0.170

0.090

15.800

13.800

15.800

13.800

Typ

1.400

0.220

16.000

14.000

12.000

16.000

14.000

Max

1.600

0.150

1.450

0.270

0.200

16.200

14.200

16.200

14.200

Min

0.0020

0.0531

0.0067

0.0035

0.6220

0.5433

0.6220

0.5433

Typ

0.0551

0.0087

0.6299

0.5512

0.4724

0.6299

0.5512

1L_ME_V5

Max

0.0630

0.0059

0.0571

0.0106

0.0079

0.6378

0.5591

0.6378

0.5591

DS13560 Rev 3

STM32G0B1xB/xC/xE Package information

Table 94. LQFP100 package mechanical data (continued) millimeters inches (1)

Symbol

Min Typ Max Min

L1 k ccc

E3 e

0.450

0.0°

12.000

0.500

0.600

1.000

3.5°

0.750

7.0°

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.0177

0.0°

Typ

0.4724

0.0197

0.0236

0.0394

3.5°

Figure 65. Recommended footprint for LQFP100 package

75 51

Max

0.0295

7.0°

0.0031

76 50

0.5

0.3

16.7

14.3

100

1. Dimensions are expressed in millimeters.

12.3

16.7

1.2

DS13560 Rev 3

153/159

154

Package information STM32G0B1xB/xC/xE

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 66. LQFP100 package marking example

STM32G0B1

Will be provided later

Y WW

Product identification

(1)

Revision code

Date code

Pin 1 identifier

154/159

DS13560 Rev 3

STM32G0B1xB/xC/xE

The operating junction temperature T

must never exceed the maximum given in