This document should be read in conjunction with the STM32L43xxx/44xxx/45xxx/46xxx reference manual (RM0394). The reference manual is available from the

STMicroelectronics website www.st.com

For information on the Arm ®(a) Cortex ® -M4 core, please refer to the Cortex

Reference Manual, available from the www.arm.com website.

® -M4 Technical

10/157

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

DS11450 Rev 4

STM32L442KC

2 Description

Description

The STM32L442KC devices are the ultra-low-power microcontrollers based on the highperformance Arm ® Cortex ® -M4 32-bit RISC core operating at a frequency of up to 80 MHz.

The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all

Arm ® single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security.

The STM32L442KC devices embed high-speed memories (256 Kbyte of Flash memory,

64 Kbyte of SRAM), a Quad SPI flash memories interface and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix.

The STM32L442KC devices embed several protection mechanisms for embedded Flash memory and SRAM: readout protection, write protection, proprietary code readout protection and Firewall.

The devices offer a fast 12-bit ADC (5 Msps), two comparators, one operational amplifier, two DAC channels, a low-power RTC, one general-purpose 32-bit timer, one 16-bit PWM timer dedicated to motor control, four general-purpose 16-bit timers, and two 16-bit lowpower timers.

In addition, up to 3 capacitive sensing channels are available.

They also feature standard and advanced communication interfaces.

• Two I2Cs

• Two SPIs

• Two USARTs and one Low-Power UART.

• One SAI (Serial Audio Interfaces)

• One CAN

• One USB full-speed device crystal less

• One SWPMI (Single Wire Protocol Master Interface)

The STM32L442KC devices embed AES hardware accelerator.

The STM32L442KC operates in the -40 to +85 °C (+105 °C junction), -40 to +105 °C

(+125 °C junction) and -40 to +125 °C (+130 °C junction) temperature ranges from a 1.71 to

3.6 V power supply. A comprehensive set of power-saving modes allows the design of lowpower applications.

Some independent power supplies are supported: analog independent supply input for

ADC, DAC, OPAMP and comparators

The STM32L442KC family offers a single 32-pin package.

Table 1. STM32L442KC family device features and peripheral counts

Peripheral STM32L442KC

Flash memory

SRAM

Quad SPI

256KB

64KB

Yes

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Description STM32L442KC

Table 1. STM32L442KC family device features and peripheral counts (continued)

Peripheral STM32L442KC

Packages

Advanced control

General purpose

Timers

Comm. interfaces

RTC

Tamper pins

Random generator

AES

GPIOs

Wakeup pins

Capacitive sensing

Number of channels

12-bit ADC

Number of channels

12-bit DAC channels

Analog comparator

Operational amplifiers

Max. CPU frequency

Operating voltage

Basic

Low -power

SysTick timer

Watchdog timers (independent, window)

SPI

I 2 C

USART

LPUART

SAI

CAN

USB FS

SWPMI

Operating temperature

1 (16-bit)

2 (16-bit)

1 (32-bit)

2 (16-bit)

Yes

(1)

Yes

80 MHz

1.71 to 3.6 V

Ambient operating temperature: -40 to 85 °C / -

40 to 105 °C / -40 to 125 °C

Junction temperature: -40 to 105 °C / -40 to

125 °C / -40 to 130 °C

UFQFPN32

1. There is no VDDUSB pin. V

3.3 V (+/- 10%).

DDUSB

is connected internally at V

. To be functional, V

must be equal to

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DS11450 Rev 4

STM32L442KC Description

Figure 1. STM32L442KC block diagram

NJTRST, JTDI,

JTCK/SWCLK

JTDO/SWD, JTDO

TRACECLK

TRACED[3:0]

1 Group of

3 channels max as AF

PA[15:0]

PB[7:3],

PB[1:0]

PC[15:14]

PH[3]

10 external analog inputs

@ VDDA

ADC1

26 AF

3 compl. channels (TIM1_CH[1:3]N),

4 channels (TIM1_CH[1:4]),

ETR, BKIN, BKIN2 as AF

2 channels,

1 compl. channel, BKIN as AF

1 channel,

1 compl. channel, BKIN as AF

RX, TX, CK,CTS,

RTS as AF

MOSI, MISO,

SCK, NSS as AF

MCLK_A, SD_A, FS_A, SCK_A, EXTCLK

MCLK_B, SD_B, FS_B, SCK_B as AF

Note:

JTAG & SW

ETM

ARM Cortex-M4

80 MHz

FPU

MPU

NVIC

D-BUS

I-BUS

S-BUS

TIM15

TIM16

16b

16b smcard

IrDA

USART1

SPI1

SAI1

INP, INM, OUT

@ VDDA

COMP1

COMP2

FIREWALL

DMA2

DMA1

Touch sensing controller

GPIO PORT A

GPIO PORT B

GPIO PORT C

GPIO PORT H

@ VDD

EXT IT. WKUP

ITF

TIM1 / PWM 16b

AF: alternate function on I/O pins.

Quad SPI memory interface

D0[3:0],

CLK0,

AHB/APB2

Flash up to

256 KB

SRAM 48 KB

SRAM 16 KB

AHB2 80 MHz

AHB/APB1

WWDG

RNG

AES

@ VDD

MSI

RC HSI

RC LSI

PLL 1&2

HSI48

Reset & clock control

CRC reset

Int

VDD Power management

Voltage regulator

3.3 to 1.2 V

@ VDD

Supply supervision

BOR

PVD, PVM

VDD = 1.71 to 3.6 V

VSS

VDDA, VSSA

VDD, VSS, NRST

@VDD

IWDG

Standby interface

@VBAT

XTAL 32 kHz

RTC

AWU

Backup register

OSC32_IN

OSC32_OUT

RTC_TAMPx

TIM2

32b

@ VDDUSB

USB FS

4 channels, ETR as AF

NOE

CRS_SYNC CRS

USART2 smcard

IrDA

SPI3

I2C1/SMBUS

I2C3/SMBUS

RX, TX, CK, CTS, RTS as AF

MOSI, MISO, SCK, NSS as AF

SCL, SDA, SMBA as AF

SCL, SDA, SMBA as AF bxCAN1

@VDDA

OpAmp1

TX, RX as AF

VOUT, VINM, VINP TIM6

TIM7

16b

@ VDDA

DAC1

DAC2

OUT1 OUT2

ITF

LPUART1

SWPMI1

LPTIM1

LPTIM2

RX, TX, CTS, RTS as AF

RX, TX, SUSPEND as AF

IN1, IN2, OUT, ETR as AF

IN1, OUT, ETR as AF

MSv39218V3

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Functional overview STM32L442KC

3.1 Arm

®

Cortex

®

-M4 core with FPU

The Arm

Cortex

-M4 with FPU processor is the latest generation of Arm

processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of

MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.

The Arm

Cortex

-M4 with FPU 32-bit RISC processor features exceptional codeefficiency, delivering the high-performance expected from an Arm

core in the memory size usually associated with 8- and 16-bit devices.

The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution.

Its single precision FPU speeds up software development by using metalanguage development tools, while avoiding saturation.

With its embedded Arm

core, the STM32L442KC family is compatible with all Arm

tools and software.

Figure 1 shows the general block diagram of the STM32L442KC family devices.

3.2 Adaptive real-time memory accelerator (ART Accelerator™)

The ART Accelerator™ is a memory accelerator which is optimized for STM32 industrystandard Arm ® Cortex the Arm ® Cortex ®

® -M4 processors. It balances the inherent performance advantage of

-M4 over Flash memory technologies, which normally requires the processor to wait for the Flash memory at higher frequencies.

To release the processor near 100 DMIPS performance at 80MHz, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 64-bit Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 80 MHz.

3.3 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory.

The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the

MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

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DS11450 Rev 4

STM32L442KC

3.4

Functional overview

Embedded Flash memory

STM32L442KC devices feature 256 Kbyte of embedded Flash memory available for storing programs and data in single bank architecture. The Flash memory contains 128 pages of 2

Kbyte.

Flexible protections can be configured thanks to option bytes:

• Readout protection (RDP) to protect the whole memory. Three levels are available:

– Level 0: no readout protection

– Level 1: memory readout protection: the Flash memory cannot be read from or written to if either debug features are connected, boot in RAM or bootloader is selected

– Level 2: chip readout protection: debug features (Cortex-M4 JTAG and serial wire), boot in RAM and bootloader selection are disabled (JTAG fuse). This selection is irreversible.

Table 2. Access status versus readout protection level and execution modes

Area

Protection level

User execution

Debug, boot from RAM or boot from system memory (loader)

Read Write Erase Read Write Erase

Main memory

System memory

Option bytes

Backup registers

SRAM2

Yes

1. Erased when RDP change from Level 1 to Level 0.

Yes

N/A

(1)

N/A

Yes (1)

Yes

N/A

Yes

N/A

Yes

N/A

Yes

N/A

Yes

N/A

(1)

N/A

No (1)

N/A

• Write protection (WRP): the protected area is protected against erasing and programming. Two areas can be selected, with 2-Kbyte granularity.

• Proprietary code readout protection (PCROP): a part of the flash memory can be protected against read and write from third parties. The protected area is execute-only: it can only be reached by the STM32 CPU, as an instruction code, while all other accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited.

The PCROP area granularity is 64-bit wide. An additional option bit (PCROP_RDP) allows to select if the PCROP area is erased or not when the RDP protection is changed from Level 1 to Level 0.

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Functional overview STM32L442KC

The whole non-volatile memory embeds the error correction code (ECC) feature supporting:

• single error detection and correction

• double error detection.

• The address of the ECC fail can be read in the ECC register

STM32L442KC devices feature 64 Kbyte of embedded SRAM. This SRAM is split into two blocks:

• 48 Kbyte mapped at address 0x2000 0000 (SRAM1)

• 16 Kbyte located at address 0x1000 0000 with hardware parity check (SRAM2).

This memory is also mapped at address 0x2000 C000, offering a contiguous address space with the SRAM1 (16 Kbyte aliased by bit band)

This block is accessed through the ICode/DCode buses for maximum performance.

These 16 Kbyte SRAM can also be retained in Standby mode.

The SRAM2 can be write-protected with 1 Kbyte granularity.

The memory can be accessed in read/write at CPU clock speed with 0 wait states.

3.6 Firewall

The device embeds a Firewall which protects code sensitive and secure data from any access performed by a code executed outside of the protected areas.

Each illegal access generates a reset which kills immediately the detected intrusion.

The Firewall main features are the following:

• Three segments can be protected and defined thanks to the Firewall registers:

– Code segment (located in Flash or SRAM1 if defined as executable protected area)

– Non-volatile data segment (located in Flash)

– Volatile data segment (located in SRAM1)

• The start address and the length of each segments are configurable:

– Code segment: up to 1024 Kbyte with granularity of 256 bytes

– Non-volatile data segment: up to 1024 Kbyte with granularity of 256 bytes

– Volatile data segment: up to 48 Kbyte with a granularity of 64 bytes

• Specific mechanism implemented to open the Firewall to get access to the protected areas (call gate entry sequence)

• Volatile data segment can be shared or not with the non-protected code

• Volatile data segment can be executed or not depending on the Firewall configuration

The Flash readout protection must be set to level 2 in order to reach the expected level of protection.

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DS11450 Rev 4

STM32L442KC Functional overview

At startup, BOOT0 pin or nSWBOOT0 option bit, and BOOT1 option bit are used to select one of three boot options:

• Boot from user Flash

• Boot from system memory

• Boot from embedded SRAM

BOOT0 value may come from the PH3-BOOT0 pin or from an option bit depending on the value of a user option bit to free the GPIO pad if needed.

A Flash empty check mechanism is implemented to force the boot from system flash if the first flash memory location is not programmed and if the boot selection is configured to boot from main flash.

The boot loader is located in system memory. It is used to reprogram the Flash memory by using USART, I2C, SPI or USB FS in Device mode through DFU (device firmware upgrade).

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.

3.9.1

Note:

Power supply schemes

• V

= 1.71 to 3.6 V: external power supply for I/Os (V

DDIO1

), the internal regulator and the system analog such as reset, power management and internal clocks. It is provided externally through VDD pins.

• V

DDA

= 1.62 V (ADCs/COMPs) / 1.8 (DAC/OPAMP) to 3.6 V: external analog power supply for ADCs, DAC, OPAMPs, Comparators and Voltage reference buffer. The V

DDA voltage level is independent from the V

voltage.

When the functions supplied by V

DDA preferably be shorted to V

or V

DDUSB

are not used, these supplies should

If these supplies are tied to ground, the I/Os supplied by these power supplies are not 5 V tolerant (refer to

Table 18: Voltage characteristics

DDIOx

DDIO1

is the I/Os general purpose digital functions supply. V

DDIOx

= V

represents V

DDIO1

, with

DS11450 Rev 4

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Functional overview

DDA

SSA

DDUSB

Figure 2. Power supply overview

DDA

domain

A/D converters

Comparators

D/A converters

Operational amplifiers

Voltage reference buffer

USB transceivers

domain

DDIO1

I/O ring

Reset block

Temp. sensor

PLL, HSI, MSI, HSI48

Standby circuitry

(Wakeup logic, IWDG)

Voltage regulator

CORE

domain

Core

Memories

Digital peripherals

STM32L442KC

BAT

Low voltage detector

Backup domain

LSE crystal 32 K osc

BKP registers

RCC BDCR register

RTC

MSv39216V3

During power-up and power-down phases, the following power sequence requirements must be respected:

• When V

300 mV.

is below 1 V, other power supplies (V

DDA

) must remain below V

• When V

is above 1 V, all power supplies are independent.

During the power-down phase, V

can temporarily become lower than other supplies only if the energy provided to the MCU remains below 1 mJ; this allows external decoupling capacitors to be discharged with different time constants during the power- down transient phase.

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DS11450 Rev 4

STM32L442KC Functional overview

Figure 3. Power-up/down sequence

3.6

DDX

(1)

BOR0

3.9.2

0.3

Power-on Operating mode Power-down time

Invalid supply area V

DDX

< V

+ 300 mV V

DDX

independent from V

MSv47490V1

1. V

DDX

refers to V

DDA

Power supply supervisor

The device has an integrated ultra-low-power brown-out reset (BOR) active in all modes except Shutdown and ensuring proper operation after power-on and during power down.

The device remains in reset mode when the monitored supply voltage V

DD specified threshold, without the need for an external reset circuit.

is below a

The lowest BOR level is 1.71V at power on, and other higher thresholds can be selected through option bytes.The device features an embedded programmable voltage detector

(PVD) that monitors the V

power supply and compares it to the VPVD threshold. An interrupt can be generated when V

drops below the VPVD threshold and/or when V

is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

In addition, the device embeds a Peripheral Voltage Monitor which compares the independent supply voltage V

DDA

with a fixed threshold in order to ensure that the peripheral is in its functional supply range.

DS11450 Rev 4

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Functional overview STM32L442KC

Two embedded linear voltage regulators supply most of the digital circuitries: the main regulator (MR) and the low-power regulator (LPR).

• The MR is used in the Run and Sleep modes and in the Stop 0 mode.

• The LPR is used in Low-Power Run, Low-Power Sleep, Stop 1 and Stop 2 modes. It is also used to supply the 16 Kbyte SRAM2 in Standby with SRAM2 retention.

• Both regulators are in power-down in Standby and Shutdown modes: the regulator output is in high impedance, and the kernel circuitry is powered down thus inducing zero consumption.

The ultralow-power STM32L442KC supports dynamic voltage scaling to optimize its power consumption in run mode. The voltage from the Main Regulator that supplies the logic

CORE

) can be adjusted according to the system’s maximum operating frequency.

There are two power consumption ranges:

• Range 1 with the CPU running at up to 80 MHz.

• Range 2 with a maximum CPU frequency of 26 MHz. All peripheral clocks are also limited to 26 MHz.

The V

CORE

can be supplied by the low-power regulator, the main regulator being switched off. The system is then in Low-power run mode.

• Low-power run mode with the CPU running at up to 2 MHz. Peripherals with independent clock can be clocked by HSI16.

The ultra-low-power STM32L442KC supports seven low-power modes to achieve the best compromise between low-power consumption, short startup time, available peripherals and available wakeup sources.

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DS11450 Rev 4

Mode

Run

LPRun

Sleep

LPSleep

Regulator

(1)

MR range 1

MR range2

LPR

MR range 1

MR range2

LPR

Stop 0

MR Range 1

MR Range 2

Table 3. STM32L442KC modes overview

CPU Flash SRAM Clocks DMA & Peripherals

(2)

Wakeup source Consumption

(3)

Yes ON

(4)

ON Any

All

All except USB_FS, RNG

N/A

97 µA/MHz

84 µA/MHz

Yes ON

(4)

Any except

PLL

All except USB_FS, RNG N/A 94 µA/MHz

No ON

(4)

(5)

Any

All

All except USB_FS, RNG

Any interrupt or event

28 µA/MHz

26 µA/MHz

No ON

(4)

(5)

Any except

PLL

All except USB_FS, RNG

Any interrupt or event

29 µA/MHz

Wakeup time

N/A to Range 1: 4 µs to Range 2: 64 µs

6 cycles

No OFF ON

LSE

LSI

BOR, PVD, PVM

RTC, IWDG

COMPx (x=1,2)

DAC1

OPAMPx (x=1)

USARTx (x=1,2)

(6)

LPUART1

(6)

I2Cx (x=1,3)

(7)

LPTIMx (x=1,2)

***

All other peripherals are frozen.

Reset pin, all I/Os

BOR, PVD, PVM

RTC, IWDG

COMPx (x=1..2)

USARTx (x=1,2)

(6)

LPUART1

(6)

I2Cx (x=1,3)

(7)

LPTIMx (x=1,2)

USB_FS

(8)

SWPMI1

(9)

108 µA

2.4 µs in SRAM

4.1 µs in Flash

Mode

Stop 1

Stop 2

Regulator

(1)

LPR

Table 3. STM32L442KC modes overview (continued)

CPU Flash SRAM Clocks DMA & Peripherals

(2)

Wakeup source Consumption

(3)

Off

LSE

LSI

LSE

LSI

BOR, PVD, PVM

RTC, IWDG

COMPx (x=1,2)

DAC1

OPAMPx (x=1)

USARTx (x=1,2)

(6)

LPUART1

(6)

I2Cx (x=1,3)

(7)

LPTIMx (x=1,2)

***

All other peripherals are frozen.

BOR, PVD, PVM

RTC, IWDG

COMPx (x=1..2)

I2C3

(7)

LPUART1

(6)

LPTIM1

***

All other peripherals are frozen.

Reset pin, all I/Os

BOR, PVD, PVM

RTC, IWDG

COMPx (x=1..2)

USARTx (x=1,2)

(6)

LPUART1

(6)

I2Cx (x=1,3)

(7)

LPTIMx (x=1,2)

USB_FS

(8)

SWPMI1

(9)

Reset pin, all I/Os

BOR, PVD, PVM

RTC, IWDG

COMPx (x=1..2)

I2C3

(7)

LPUART1

(6)

LPTIM1

4.34 µA w/o RTC

4.63 µA w RTC

1.3 µA w/o RTC

1.4 µA w/RTC

Wakeup time

6.3 µs in SRAM

7.8 µs in Flash

6.8 µs in SRAM

8.2 µs in Flash

Mode Regulator

(1)

Table 3. STM32L442KC modes overview (continued)

CPU Flash SRAM Clocks DMA & Peripherals

(2)

Wakeup source Consumption

(3)

Wakeup time

Standby

Shutdown

LPR

OFF

Power ed Off

Off

SRAM

2 ON

Power ed

Off

Power ed

Off

LSE

LSI

LSE

BOR, RTC, IWDG

***

All other peripherals are powered off.

***

I/O configuration can be floating, pull-up or pull-down

RTC

***

All other peripherals are powered off.

***

I/O configuration can be floating, pull-up or pulldown

(11)

Reset pin

5 I/Os (WKUPx)

BOR, RTC, IWDG

Reset pin

5 I/Os (WKUPx)

RTC

(10)

0.20 µA w/o RTC

0.46 µA w/ RTC

0.03 µA w/o RTC

0.29 µA w/ RTC

0.01 µA w/o RTC

0.20 µA w/ RTC

1. LPR means Main regulator is OFF and Low-power regulator is ON.

2. All peripherals can be active or clock gated to save power consumption.

3. Typical current at V

LPRun/LPSleep.

= 1.8 V, 25°C. Consumptions values provided running from SRAM, Flash memory Off, 80 MHz in Range 1, 26 MHz in Range 2, 2 MHz in

4. The Flash memory can be put in power-down and its clock can be gated off when executing from SRAM.

5. The SRAM1 and SRAM2 clocks can be gated on or off independently.

6. U(S)ART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event.

7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.

8. USB_FS wakeup by resume from suspend and attach detection protocol event.

9. SWPMI1 wakeup by resume from suspend.

10. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5.

11. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode.

12.2 µs

262 µs

Functional overview STM32L442KC

By default, the microcontroller is in Run mode after a system or a power Reset. It is up to the user to select one of the low-power modes described below:

• Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

• Low-power run mode

This mode is achieved with V

CORE

supplied by the low-power regulator to minimize the regulator's operating current. The code can be executed from SRAM or from Flash, and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can be clocked by HSI16.

• Low-power sleep mode

This mode is entered from the low-power run mode. Only the CPU clock is stopped.

When wakeup is triggered by an event or an interrupt, the system reverts to the lowpower run mode.

• Stop 0, Stop 1 and Stop 2 modes

Stop mode achieves the lowest power consumption while retaining the content of

SRAM and registers. All clocks in the V

CORE

domain are stopped, the PLL, the MSI RC and the HSI16 RC are disabled. The LSE or LSI is still running.

The RTC can remain active (Stop mode with RTC, Stop mode without RTC).

Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode to detect their wakeup condition.

Three Stop modes are available: Stop 0, Stop 1 and Stop 2 modes. In Stop 2 mode, most of the V

CORE

domain is put in a lower leakage mode.

Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller wakeup time but a higher consumption than Stop 2. In Stop 0 mode, the main regulator remains ON, allowing a very fast wakeup time but with much higher consumption.

The system clock when exiting from Stop 0, Stop 1 or Stop 2 modes can be either MSI up to 48 MHz or HSI16, depending on software configuration.

• Standby mode

The Standby mode is used to achieve the lowest power consumption with BOR. The internal regulator is switched off so that the V

CORE

MSI RC and the HSI16 RC are also switched off.

domain is powered off. The PLL, the

The RTC can remain active (Standby mode with RTC, Standby mode without RTC).

The brown-out reset (BOR) always remains active in Standby mode.

The state of each I/O during standby mode can be selected by software: I/O with internal pull-up, internal pull-down or floating.

After entering Standby mode, SRAM1 and register contents are lost except for registers in the Backup domain and Standby circuitry. Optionally, SRAM2 can be retained in

Standby mode, supplied by the low-power Regulator (Standby with SRAM2 retention mode).

The device exits Standby mode when an external reset (NRST pin), an IWDG reset,

WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic wakeup, timestamp, tamper) or a failure is detected on LSE (CSS on LSE).

The system clock after wakeup is MSI up to 8 MHz.

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STM32L442KC Functional overview

• Shutdown mode

The Shutdown mode allows to achieve the lowest power consumption. The internal regulator is switched off so that the V

CORE

domain is powered off. The PLL, the HSI16, the MSI and the LSI oscillators are also switched off.

The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).

The BOR is not available in Shutdown mode. No power voltage monitoring is possible in this mode, therefore the switch to Backup domain is not supported.

SRAM1, SRAM2 and register contents are lost except for registers in the Backup domain.

The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic wakeup, timestamp, tamper).

The system clock after wakeup is MSI at 4 MHz.

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Peripheral

STM32L442KC

Table 4. Functionalities depending on the working mode (1)

Stop 0/1 Stop 2 Standby Shutdow

Run Sleep

Lowpower run

Lowpower sleep -

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CPU

Flash memory

(256 KB)

SRAM1 (48 KB)

SRAM2 (16 KB)

Quad SPI

Backup Registers

Brown-out reset

(BOR)

Programmable

Voltage Detector

(PVD)

Peripheral Voltage

Monitor (PVMx; x=1,3,4)

DMA

High Speed Internal

(HSI16)

Oscillator RC48

High Speed

External (HSE)

Low Speed Internal

(LSI)

Low Speed External

(LSE)

Multi-Speed Internal

(MSI)

Clock Security

System (CSS)

Clock Security

System on LSE

RTC / Auto wakeup

Number of RTC

Tamper pins

USB FS

(2)

(8)

(2)

(3)

Y (3)

(8)

(2)

(3)

Y (3)

O (4)

Y Y

O O O O

O O O O -

(5)

O O -

O -

O O O O O O -

O O O O O O O

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STM32L442KC Functional overview

Table 4. Functionalities depending on the working mode (1) (continued)

Stop 0/1 Stop 2 Standby Shutdow

Peripheral Run Sleep

Lowpower run

Lowpower sleep -

USARTx (x=1,2)

Low-power UART

(LPUART)

I2Cx (x=1)

I2C3

SPIx (x=1,3)

CAN

SWPMI1

SAIx (x=1)

ADCx (x=1)

DAC1

OPAMPx (x=1)

COMPx (x=1,2)

Temperature sensor

Timers (TIMx)

Low-power timer 1

(LPTIM1)

Low-power timer 2

(LPTIM2)

Independent watchdog (IWDG)

Window watchdog

(WWDG)

SysTick timer

Touch sensing controller (TSC)

Random number generator (RNG)

AES hardware accelerator

(8)

O O

(6)

O O

(6)

O O

(7)

O O

(7)

O -

(7)

O -

O O O O

O O O O O

O O -

O O O O O O

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Functional overview STM32L442KC

Table 4. Functionalities depending on the working mode (1) (continued)

Stop 0/1 Stop 2 Standby Shutdow

Peripheral Run Sleep

Lowpower run

Lowpower sleep -

CRC calculation unit

O O O O -

GPIOs O O O O O O O O

(9)

2 pins

(10)

(11)

2 pins

(10)

1. Legend: Y = Yes (Enable). O = Optional (Disable by default. Can be enabled by software). - = Not available.

2. The Flash can be configured in power-down mode. By default, it is not in power-down mode.

3. The SRAM clock can be gated on or off.

4. SRAM2 content is preserved when the bit RRS is set in PWR_CR3 register.

5. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not need it anymore.

6. UART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event.

7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.

8. Voltage scaling Range 1 only.

9. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.

10. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PA2.

11. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode.

In order to improve the consumption under reset, the I/Os state under and after reset is

“analog state” (the I/O schmitt trigger is disable). In addition, the internal reset pull-up is deactivated when the reset source is internal.

Several peripherals have direct connections between them. This allows autonomous communication between peripherals, saving CPU resources thus power supply consumption. In addition, these hardware connections allow fast and predictable latency.

Depending on peripherals, these interconnections can operate in Run, Sleep, low-power run and sleep, Stop 0, Stop 1 and Stop 2 modes.

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Table 5. STM32L442KC peripherals interconnect matrix

Functional overview

Interconnect source

Interconnect destination

Interconnect action

TIMx

TIM15/TIM16

COMPx

ADCx

RTC

TIMx

ADCx

DAC1

DMA

COMPx

IRTIM

TIM1

TIM2

LPTIMERx

TIM1

TIM16

LPTIMERx

All clocks sources (internal and external)

TIM2

TIM15, 16

USB TIM2

CSS

CPU (hard fault)

RAM (parity error)

Flash memory (ECC error)

COMPx

PVD

TIM1

TIM15,16

GPIO

TIMx

LPTIMERx

ADCx

DAC1

1. LPTIM1 only.

Timers synchronization or chaining

Conversion triggers

Memory to memory transfer trigger

Comparator output blanking

Infrared interface output generation

Timer input channel, trigger, break from analog signals comparison

Y Y Y Y -

Low-power timer triggered by analog signals comparison

Timer triggered by analog watchdog

Timer input channel from RTC events

Low-power timer triggered by RTC alarms or tampers

Y Y Y Y Y

(1)

Y Y Y Y -

Y Y Y Y Y

(1)

Clock source used as input channel for

RC measurement and trimming

Timer triggered by USB SOF

Timer break

External trigger

Conversion external trigger

(1)

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Functional overview STM32L442KC

3.11 Clocks and startup

The clock controller (see Figure 4

) distributes the clocks coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness. It features:

• Clock prescaler: to get the best trade-off between speed and current consumption, the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler

• Safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register.

• Clock management: to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory.

• System clock source: four different clock sources can be used to drive the master clock SYSCLK:

– High Speed External clock (HSE) can supply a PLL.

– 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software, that can supply a PLL

– Multispeed internal RC oscillator (MSI), trimmable by software, able to generate

12 frequencies from 100 kHz to 48 MHz. When a 32.768 kHz clock source is available in the system (LSE), the MSI frequency can be automatically trimmed by hardware to reach better than ±0.25% accuracy. In this mode the MSI can feed the

USB device. The MSI can supply a PLL.

– System PLL which can be fed by HSE, HSI16 or MSI, with a maximum frequency at 80 MHz.

• RC48 with clock recovery system (HSI48) : internal RC48 MHz clock source can be used to drive the USB or the RNG peripherals. This clock can be output on the MCO.

• Auxiliary clock source: two ultralow-power clock sources that can be used to drive the real-time clock:

– 32.768 kHz low-speed external crystal (LSE), supporting four drive capability modes. The LSE can also be configured in bypass mode for an external clock.

– 32 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.

The LSI clock accuracy is ±5% accuracy.

• Peripheral clock sources: Several peripherals (USB, RNG, SAI, USARTs, I2Cs,

LPTimers, ADC, SWPMI) have their own independent clock whatever the system clock.

Two PLLs, each having three independent outputs allowing the highest flexibility, can generate independent clocks for the ADC, the USB/RNG and the SAI.

• Startup clock: after reset, the microcontroller restarts by default with an internal 4 MHz clock (MSI). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts.

• Clock security system (CSS): this feature can be enabled by software. If a HSE clock failure occurs, the master clock is automatically switched to HSI16 and a software

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STM32L442KC Functional overview interrupt is generated if enabled. LSE failure can also be detected and generated an interrupt.

• Clock-out capability:

– MCO: microcontroller clock output: it outputs one of the internal clocks for external use by the application. Low frequency clocks (LSI, LSE) are available down to Stop 1 low power state.

– LSCO: low speed clock output: it outputs LSI or LSE in all low-power modesdown to Standby mode. LSE can also be output on LSCO in Shutdown mode. LSCO is not available in VBAT mode.

Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the APB domains is 80 MHz.

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Functional overview STM32L442KC

Figure 4. Clock tree to IWDG

LSI RC 32 kHz

LSCO to RTC

OSC32_OUT

OSC32_IN

MCO

/ 1

LSE OSC

32.768 kHz

䊻㻝㻢

LSE

LSI

HSE

SYSCLK

MSI

HSI16

HSI48

PLLCLK

CK_IN

Clock detector

PLL

100 kHz – 48 MHz

VCO

HSI RC

16 MHz

MSI RC

/ P

/ Q

/ R

PLLSAI1CLK

PLL48M1CLK

PLLCLK

PLLSAI1

VCO

/ P

/ Q

/ R

PLLSAI2CLK

PLL48M2CLK

PLLADC1CLK

/32 to PWR

/ M

HSE

MSI

HSI16

Clock source control

SYSCLK

AHB PRESC

/ 1,2,..512

HCLK

/ 8 to AHB bus, core, memory and DMA

FCLK Cortex free running clock to Cortex system timer

APB1 PRESC

/ 1,2,4,8,16

PCLK1 to APB1 peripherals x1 or x2 to TIMx x=2,6,7

LSE

HSI16

SYSCLK to USARTx x=2..3

to LPUART1

HSI16

SYSCLK to I2Cx x=1,2,3

LSI

LSE

HSI16 to LPTIMx x=1,2

MSI

HSI16

HSE

HSI16

APB2 PRESC

/ 1,2,4,8,16 to SWPMI

PCLK2 to APB2 peripherals x1 or x2 to TIMx x=1,15,16

LSE

HSI16

SYSCLK to USART1

SYSCLK

HSI RC

48 MHz

CRS

HSI16

MSI to ADC

48 MHz clock to USB, RNG

HSI16

SAI1_EXTCLK to SAI1

MSv39217V4

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Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be achieved thanks to their mapping on the AHB2 bus.

The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers.

3.13 Direct memory access controller (DMA)

The device embeds 2 DMAs. Refer to Table 6: DMA implementation for the features

implementation.

Direct memory access (DMA) is used in order to provide high-speed data transfer between peripherals and memory as well as memory to memory. Data can be quickly moved by DMA without any CPU actions. This keeps CPU resources free for other operations.

The two DMA controllers have 14 channels in total, each dedicated to managing memory access requests from one or more peripherals. Each has an arbiter for handling the priority between DMA requests.

The DMA supports:

• 14 independently configurable channels (requests)

• Each channel is connected to dedicated hardware DMA requests, software trigger is also supported on each channel. This configuration is done by software.

• Priorities between requests from channels of one DMA are software programmable (4 levels consisting of very high, high, medium, low) or hardware in case of equality

(request 1 has priority over request 2, etc.)

• Independent source and destination transfer size (byte, half word, word), emulating packing and unpacking. Source/destination addresses must be aligned on the data size.

• Support for circular buffer management

• 3 event flags (DMA Half Transfer, DMA Transfer complete and DMA Transfer Error) logically ORed together in a single interrupt request for each channel

• Memory-to-memory transfer

• Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral transfers

• Access to Flash, SRAM, APB and AHB peripherals as source and destination

• Programmable number of data to be transferred: up to 65536.

Table 6. DMA implementation

DMA features DMA1

Number of regular channels 7

DMA2

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Functional overview STM32L442KC

3.14.1 Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 61 maskable interrupt channels plus the 16 interrupt lines of the Cortex

M4.

The NVIC benefits are the following:

• Closely coupled NVIC gives low latency interrupt processing

• Interrupt entry vector table address passed directly to the core

• Allows early processing of interrupts

• Processing of late arriving higher priority interrupts

• Support for tail chaining

• Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction overhead

The NVIC hardware block provides flexible interrupt management features with minimal interrupt latency.

3.14.2 Extended interrupt/event controller (EXTI)

The extended interrupt/event controller consists of 34 edge detector lines used to generate interrupt/event requests and wake-up the system from Stop mode. Each external line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests.

The internal lines are connected to peripherals with wakeup from Stop mode capability. The

EXTI can detect an external line with a pulse width shorter than the internal clock period. Up to 26 GPIOs can be connected to the 16 external interrupt lines.

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3.15 Analog to digital converter (ADC)

The device embeds a successive approximation analog-to-digital converter with the following features:

• 12-bit native resolution, with built-in calibration

• 5.33 Msps maximum conversion rate with full resolution

– Down to 18.75 ns sampling time

– Increased conversion rate for lower resolution (up to 8.88 Msps for 6-bit resolution)

• Up to 10 external channels.

• 4 internal channels: internal reference voltage, temperature sensor, DAC1_OUT1 and

DAC1_OUT2.

• Single-ended and differential mode inputs

• Low-power design

– Capable of low-current operation at low conversion rate (consumption decreases linearly with speed)

– Dual clock domain architecture: ADC speed independent from CPU frequency

• Highly versatile digital interface

– Single-shot or continuous/discontinuous sequencer-based scan mode: 2 groups of analog signals conversions can be programmed to differentiate background and high-priority real-time conversions

– ADC supports multiple trigger inputs for synchronization with on-chip timers and external signals

– Results stored into data register or in RAM with DMA controller support

– Data pre-processing: left/right alignment and per channel offset compensation

– Built-in oversampling unit for enhanced SNR

– Channel-wise programmable sampling time

– Three analog watchdog for automatic voltage monitoring, generating interrupts and trigger for selected timers

– Hardware assistant to prepare the context of the injected channels to allow fast context switching

The temperature sensor (TS) generates a voltage V

that varies linearly with temperature.

The temperature sensor is internally connected to the ADC1_IN17 input channel which is used to convert the sensor output voltage into a digital value.

The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only.

To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode.

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Functional overview STM32L442KC

Table 7. Temperature sensor calibration values

Calibration value name Description Memory address

TS_CAL1

TS_CAL2

TS ADC raw data acquired at a temperature of 30 °C (± 5 °C),

DDA

= V

REF+

= 3.0 V (± 10 mV)

TS ADC raw data acquired at a temperature of 130 °C (± 5 °C),

DDA

= V

REF+

= 3.0 V (± 10 mV)

0x1FFF 75A8 - 0x1FFF 75A9

0x1FFF 75CA - 0x1FFF 75CB

3.15.2 Internal voltage reference (V

REFINT

)

The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the ADC and Comparators. VREFINT is internally connected to the ADC1_IN0 input channel. The precise voltage of VREFINT is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode.

Table 8. Internal voltage reference calibration values

Calibration value name Description Memory address

VREFINT

Raw data acquired at a temperature of 30 °C (± 5 °C),

DDA

= V

REF+

= 3.0 V (± 10 mV)

0x1FFF 75AA - 0x1FFF 75AB

3.16 Digital to analog converter (DAC)

Two 12-bit buffered DAC channels can be used to convert digital signals into analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration.

This digital interface supports the following features:

• Up to two DAC output channels

• 8-bit or 12-bit output mode

• Buffer offset calibration (factory and user trimming)

• Left or right data alignment in 12-bit mode

• Synchronized update capability

• Noise-wave generation

• Triangular-wave generation

• Dual DAC channel independent or simultaneous conversions

• DMA capability for each channel

• External triggers for conversion

• Sample and hold low-power mode, with internal or external capacitor

The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels.

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The STM32L442KC devices embed two rail-to-rail comparators with programmable reference voltage (internal or external), hysteresis and speed (low speed for low-power) and with selectable output polarity.

The reference voltage can be one of the following:

• External I/O

• DAC output channels

• Internal reference voltage or submultiple (1/4, 1/2, 3/4).

All comparators can wake up from Stop mode, generate interrupts and breaks for the timers and can be also combined into a window comparator.

The STM32L442KC embeds one operational amplifier with external or internal follower routing and PGA capability.

The operational amplifier features:

• Low input bias current

• Low offset voltage

• Low-power mode

• Rail-to-rail input

3.19 Touch sensing controller (TSC)

The touch sensing controller provides a simple solution for adding capacitive sensing functionality to any application. Capacitive sensing technology is able to detect finger presence near an electrode which is protected from direct touch by a dielectric (glass, plastic, ...). The capacitive variation introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle.

The touch sensing controller is fully supported by the STMTouch touch sensing firmware library which is free to use and allows touch sensing functionality to be implemented reliably in the end application.

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Functional overview

Note:

STM32L442KC

The main features of the touch sensing controller are the following:

• Proven and robust surface charge transfer acquisition principle

• Supports up to 3 capacitive sensing channels

• Up to 3 capacitive sensing channels can be acquired in parallel offering a very good response time

• Spread spectrum feature to improve system robustness in noisy environments

• Full hardware management of the charge transfer acquisition sequence

• Programmable charge transfer frequency

• Programmable sampling capacitor I/O pin

• Programmable channel I/O pin

• Programmable max count value to avoid long acquisition when a channel is faulty

• Dedicated end of acquisition and max count error flags with interrupt capability

• One sampling capacitor for up to 3 capacitive sensing channels to reduce the system components

• Compatible with proximity, touchkey, linear and rotary touch sensor implementation

• Designed to operate with STMTouch touch sensing firmware library

The number of capacitive sensing channels is dependent on the size of the packages and subject to I/O availability.

3.20 Random number generator (RNG)

All devices embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit.

3.21 Advanced encryption standard hardware accelerator (AES)

The devices embed an AES hardware accelerator can be used to both encipher and decipher data using AES algorithm.

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The AES peripheral supports:

• Encryption/Decryption using AES Rijndael Block Cipher algorithm

• NIST FIPS 197 compliant implementation of AES encryption/decryption algorithm

• 128-bit and 256-bit register for storing the encryption, decryption or derivation key (4x

32-bit registers)

• Electronic codebook (ECB), Cipher block chaining (CBC), Counter mode (CTR), Galois

Counter Mode (GCM), Galois Message Authentication Code mode (GMAC) and Cipher

Message Authentication Code mode (CMAC) supported.

• Key scheduler

• Key derivation for decryption

• 128-bit data block processing

• 128-bit, 256-bit key length

• 1x32-bit INPUT buffer and 1x32-bit OUTPUT buffer.

• Register access supporting 32-bit data width only.

• One 128-bit Register for the initialization vector when AES is configured in CBC mode or for the 32-bit counter initialization when CTR mode is selected, GCM mode or

CMAC mode.

• Automatic data flow control with support of direct memory access (DMA) using 2 channels, one for incoming data, and one for outcoming data.

• Suspend a message if another message with a higher priority needs to be processed

3.22 Timers and watchdogs

The STM32L442KC includes one advanced control timers, up to five general-purpose timers, two basic timers, two low-power timers, two watchdog timers and a SysTick timer.

The table below compares the features of the advanced control, general purpose and basic timers.

Timer type

Advanced control

Generalpurpose

Timer

TIM1

TIM2

TIM15

Table 9. Timer feature comparison

Counter resolution

Counter type

Prescaler factor

DMA request generation

16-bit

32-bit

16-bit

Up, down,

Up/down

Up, down,

Up/down

Any integer between 1 and 65536

Yes

Capture/ compare channels

Complementary outputs

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Functional overview STM32L442KC

Timer type

Generalpurpose

Basic

Timer

TIM16

TIM6, TIM7

Table 9. Timer feature comparison (continued)

Counter resolution

Counter type

Prescaler factor

DMA request generation

Capture/ compare channels

Complementary outputs

16-bit

Any integer between 1 and 65536

Yes

3.22.1 Advanced-control timer (TIM1)

The advanced-control timer can each be seen as a three-phase PWM multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted deadtimes. They can also be seen as complete general-purpose timers. The 4 independent channels can be used for:

• Input capture

• Output compare

• PWM generation (edge or center-aligned modes) with full modulation capability (0-

100%)

• One-pulse mode output

In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled to turn off any power switches driven by these outputs.

Many features are shared with those of the general-purpose TIMx timers (described in

Section 3.22.2

) using the same architecture, so the advanced-control timer can work

together with the TIMx timers via the Timer Link feature for synchronization or event chaining.

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There are up to three synchronizable general-purpose timers embedded in the

STM32L442KC (see

Table 9 for differences). Each general-purpose timer can be used to

generate PWM outputs, or act as a simple time base.

• TIM2

It is a full-featured general-purpose timer:

TIM2 has a 32-bit auto-reload up/downcounter and 32-bit prescaler.

This timer features 4 independent channels for input capture/output compare, PWM or one-pulse mode output. It can work with the other general-purpose timers via the Timer

Link feature for synchronization or event chaining.

The counter can be frozen in debug mode.

It has independent DMA request generation and support quadrature encoder.

• TIM15 and 16

They are general-purpose timers with mid-range features:

They have 16-bit auto-reload upcounters and 16-bit prescalers.

– TIM15 has 2 channels and 1 complementary channel

– TIM16 has 1 channel and 1 complementary channel

All channels can be used for input capture/output compare, PWM or one-pulse mode output.

The timers can work together via the Timer Link feature for synchronization or event chaining. The timers have independent DMA request generation.

The counters can be frozen in debug mode.

3.22.3 Basic timers (TIM6 and TIM7)

The basic timers are mainly used for DAC trigger generation. They can also be used as generic 16-bit timebases.

The devices embed two low-power timers. These timers have an independent clock and are running in Stop mode if they are clocked by LSE, LSI or an external clock. They are able to wakeup the system from Stop mode.

LPTIM1 is active in Stop 0, Stop 1 and Stop 2 modes.

LPTIM2 is active in Stop 0 and Stop 1 mode.

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Functional overview STM32L442KC

This low-power timer supports the following features:

• 16-bit up counter with 16-bit autoreload register

• 16-bit compare register

• Configurable output: pulse, PWM

• Continuous/ one shot mode

• Selectable software/hardware input trigger

• Selectable clock source

– Internal clock sources: LSE, LSI, HSI16 or APB clock

– External clock source over LPTIM input (working even with no internal clock source running, used by pulse counter application).

• Programmable digital glitch filter

• Encoder mode (LPTIM1 only)

The STM32L442KC includes one infrared interface (IRTIM). It can be used with an infrared

LED to perform remote control functions. It uses TIM15 and TIM16 output channels to generate output signal waveforms on IR_OUT pin.

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC (LSI) and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode.

3.22.7 System window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features:

• A 24-bit down counter

• Autoreload capability

• Maskable system interrupt generation when the counter reaches 0.

• Programmable clock source

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The RTC is an independent BCD timer/counter. It supports the following features:

• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format.

• Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.

• Two programmable alarms.

• On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master clock.

• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision.

• Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal inaccuracy.

• One anti-tamper detection pin with programmable filter.

• Timestamp feature which can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event.

• 17-bit auto-reload wakeup timer (WUT) for periodic events with programmable resolution and period.

The RTC and the 32 backup registers are supplied through a switch that takes power from the V

supply.

The backup registers are 32-bit registers used to store 128 bytes of user application data when V

power is not present. They are not reset by a system or power reset, or when the device wakes up from Standby or Shutdown mode.

The RTC clock sources can be:

• A 32.768 kHz external crystal (LSE)

• An external resonator or oscillator (LSE)

• The internal low power RC oscillator (LSI, with typical frequency of 32 kHz)

• The high-speed external clock (HSE) divided by 32.

The RTC is functional in all low-power modes when it is clocked by the LSE. When clocked by the LSI, the RTC is functional in all low-power modes except Shutdown mode.

All RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt and wakeup the device from the low-power modes.

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Functional overview STM32L442KC

circuit interface (I

2

C)

The device embeds two I2C. Refer to

Table 10: I2C implementation

for the features implementation.

The I

C bus interface handles communications between the microcontroller and the serial

C bus. It controls all I

C bus-specific sequencing, protocol, arbitration and timing.

The I2C peripheral supports:

• I 2 C-bus specification and user manual rev. 5 compatibility:

– Slave and master modes, multimaster capability

– Standard-mode (Sm), with a bitrate up to 100 kbit/s

– Fast-mode (Fm), with a bitrate up to 400 kbit/s

– Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os

– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses

– Programmable setup and hold times

– Optional clock stretching

• System Management Bus (SMBus) specification rev 2.0 compatibility:

– Hardware PEC (Packet Error Checking) generation and verification with ACK control

– Address resolution protocol (ARP) support

– SMBus alert

• Power System Management Protocol (PMBus TM ) specification rev 1.1 compatibility

• Independent clock: a choice of independent clock sources allowing the I2C communication speed to be independent from the PCLK reprogramming. Refer to

Figure 4: Clock tree .

• Wakeup from Stop mode on address match

• Programmable analog and digital noise filters

• 1-byte buffer with DMA capability

Table 10. I2C implementation

I2C features

(1)

Standard-mode (up to 100 kbit/s)

Fast-mode (up to 400 kbit/s)

Fast-mode Plus with 20mA output drive I/Os (up to 1 Mbit/s)

Programmable analog and digital noise filters

SMBus/PMBus hardware support

Independent clock

Wakeup from Stop 0 / Stop 1 mode on address match

Wakeup from Stop 2 mode on address match

1. X: supported

I2C1

I2C3

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STM32L442KC Functional overview

(USART)

The STM32L442KC devices have two embedded universal synchronous receiver transmitters (USART1 and USART2).

These interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. They provide hardware management of the CTS and RTS signals, and RS485 Driver Enable. They are able to communicate at speeds of up to

10Mbit/s.

USART1 and USART2 also provide Smart Card mode (ISO 7816 compliant) and SPI-like communication capability.

All USART have a clock domain independent from the CPU clock, allowing the USARTx

(x=1,2) to wake up the MCU from Stop mode using baudrates up to 204 Kbaud. The wake up events from Stop mode are programmable and can be:

• Start bit detection

• Any received data frame

• A specific programmed data frame

All USART interfaces can be served by the DMA controller.

Table 11. STM32L442KC USART/LPUART features

USART modes/features (1)

Hardware flow control for modem

Continuous communication using DMA

Multiprocessor communication

Synchronous mode

Smartcard mode

Single-wire half-duplex communication

IrDA SIR ENDEC block

LIN mode

Dual clock domain

Wakeup from Stop 0 / Stop 1 modes

Wakeup from Stop 2 mode

Receiver timeout interrupt

Modbus communication

Auto baud rate detection

Driver Enable

LPUART/USART data length

1. X = supported.

USART1 USART2

X (4 modes)

7, 8 and 9 bits

LPUART1

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Functional overview STM32L442KC

(LPUART)

The device embeds one Low-Power UART. The LPUART supports asynchronous serial communication with minimum power consumption. It supports half duplex single wire communication and modem operations (CTS/RTS). It allows multiprocessor communication.

The LPUART has a clock domain independent from the CPU clock, and can wakeup the system from Stop mode using baudrates up to 220 Kbaud. The wake up events from Stop mode are programmable and can be:

• Start bit detection

• Any received data frame

• A specific programmed data frame

Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while having an extremely low energy consumption. Higher speed clock can be used to reach higher baudrates.

LPUART interface can be served by the DMA controller.

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STM32L442KC Functional overview

3.27 Serial peripheral interface (SPI)

Two SPI interfaces allow communication up to 40 Mbits/s in master and up to 24 Mbits/s slave modes, in half-duplex, full-duplex and simplex modes. The 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits. The SPI interfaces support NSS pulse mode, TI mode and Hardware CRC calculation.

All SPI interfaces can be served by the DMA controller.

The device embeds 1 SAI. Refer to Table 12: SAI implementation for the features

implementation. The SAI bus interface handles communications between the microcontroller and the serial audio protocol.

The SAI peripheral supports:

• Two independent audio sub-blocks which can be transmitters or receivers with their respective FIFO.

• 8-word integrated FIFOs for each audio sub-block.

• Synchronous or asynchronous mode between the audio sub-blocks.

• Master or slave configuration independent for both audio sub-blocks.

• Clock generator for each audio block to target independent audio frequency sampling when both audio sub-blocks are configured in master mode.

• Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit.

• Peripheral with large configurability and flexibility allowing to target as example the following audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF out.

• Up to 16 slots available with configurable size and with the possibility to select which ones are active in the audio frame.

• Number of bits by frame may be configurable.

• Frame synchronization active level configurable (offset, bit length, level).

• First active bit position in the slot is configurable.

• LSB first or MSB first for data transfer.

• Mute mode.

• Stereo/Mono audio frame capability.

• Communication clock strobing edge configurable (SCK).

• Error flags with associated interrupts if enabled respectively.

– Overrun and underrun detection.

– Anticipated frame synchronization signal detection in slave mode.

– Late frame synchronization signal detection in slave mode.

– Codec not ready for the AC’97 mode in reception.

• Interruption sources when enabled:

– Errors.

– FIFO requests.

• DMA interface with 2 dedicated channels to handle access to the dedicated integrated

FIFO of each SAI audio sub-block.

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Functional overview

Table 12. SAI implementation

SAI features

I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97

Mute mode

Stereo/Mono audio frame capability.

16 slots

Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit

FIFO Size

SPDIF

1. X: supported

STM32L442KC

Support

(1)

X (8 Word)

The Single wire protocol master interface (SWPMI) is the master interface corresponding to the Contactless Frontend (CLF) defined in the ETSI TS 102 613 technical specification. The main features are:

• full-duplex communication mode

• automatic SWP bus state management (active, suspend, resume)

• configurable bitrate up to 2 Mbit/s

• automatic SOF, EOF and CRC handling

SWPMI can be served by the DMA controller.

3.30 Controller area network (CAN)

The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and

14 scalable filter banks.

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STM32L442KC Functional overview

The CAN peripheral supports:

• Supports CAN protocol version 2.0 A, B Active

• Bit rates up to 1 Mbit/s

• Transmission

– Three transmit mailboxes

– Configurable transmit priority

• Reception

– Two receive FIFOs with three stages

– 14 Scalable filter banks

– Identifier list feature

– Configurable FIFO overrun

• Time-triggered communication option

– Disable automatic retransmission mode

– 16-bit free running timer

– Time Stamp sent in last two data bytes

• Management

– Maskable interrupts

– Software-efficient mailbox mapping at a unique address space

3.31 Universal serial bus (USB)

The STM32L442KC devices embed a full-speed USB device peripheral compliant with the

USB specification version 2.0. The internal USB PHY supports USB FS signaling, embedded DP pull-up and also battery charging detection according to Battery Charging

Specification Revision 1.2. The USB interface implements a full-speed (12 Mbit/s) function interface with added support for USB 2.0 Link Power Management. It has softwareconfigurable endpoint setting with packet memory up-to 1 KB and suspend/resume support.

It requires a precise 48 MHz clock which can be generated from the internal main PLL or by the internal 48 MHz oscillator in automatic trimming mode. The synchronization for this oscillator can be taken from the USB data stream itself (SOF signalization) which allows crystal less operation.

The STM32L442KC devices embed a special block which allows automatic trimming of the internal 48 MHz oscillator to guarantee its optimal accuracy over the whole device operational range. This automatic trimming is based on the external synchronization signal, which could be either derived from USB SOF signalization, from LSE oscillator, from an external signal on CRS_SYNC pin or generated by user software. For faster lock-in during startup it is also possible to combine automatic trimming with manual trimming action.

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Functional overview STM32L442KC

The Quad SPI is a specialized communication interface targeting single, dual or quad SPI flash memories. It can operate in any of the three following modes:

• Indirect mode: all the operations are performed using the QUADSPI registers

• Status polling mode: the external flash status register is periodically read and an interrupt can be generated in case of flag setting

• Memory-mapped mode: the external Flash is memory mapped and is seen by the system as if it were an internal memory

Both throughput and capacity can be increased two-fold using dual-flash mode, where two

Quad SPI flash memories are accessed simultaneously.

The Quad SPI interface supports:

• Three functional modes: indirect, status-polling, and memory-mapped

• SDR and DDR support

• Fully programmable opcode for both indirect and memory mapped mode

• Fully programmable frame format for both indirect and memory mapped mode

• Each of the 5 following phases can be configured independently (enable, length, single/dual/quad communication)

– Instruction phase

– Address phase

– Alternate bytes phase

– Dummy cycles phase

– Data phase

• Integrated FIFO for reception and transmission

• 8, 16, and 32-bit data accesses are allowed

• DMA channel for indirect mode operations

• Programmable masking for external flash flag management

• Timeout management

• Interrupt generation on FIFO threshold, timeout, status match, operation complete, and access error

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STM32L442KC Functional overview

The Arm

SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.

Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with

SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

3.34.2 Embedded Trace Macrocell™

The Arm ® Embedded Trace Macrocell™ provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the

STM32L442KC through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. Real-time instruction and data flow activity be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors.

The Embedded Trace Macrocell™ operates with third party debugger software tools.

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Pinouts and pin description

4 Pinouts and pin description

Figure 5. STM32L442KC UFQFPN32 pinout (1)

STM32L442KC

VDD

PC14-OSC32_IN

PC15-OSC32_OUT

NRST

VDDA/VREF+

PA0/CK_IN

PA1

PA2

UFQFPN32

PA14

PA13

PA12

PA11

PA10

PA9

PA8

VDD

MSv37605V2

Name

Notes

1. The above figure shows the package top view.

Pin name

Pin type

I/O structure

Table 13. Legend/abbreviations used in the pinout table

Abbreviation Definition

Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name

Supply pin

Input only pin

I/O

RST

Input / output pin

5 V tolerant I/O

3.6 V tolerant I/O

Bidirectional reset pin with embedded weak pull-up resistor

(1)

(2)

(3)

Option for TT or FT I/Os

I/O, Fm+ capable

I/O, with USB function supplied by V

DDUSB

I/O, with Analog switch function supplied by V

DDA

Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset.

Alternate functions

Functions selected through GPIOx_AFR registers

Pin functions

Additional functions

Functions directly selected/enabled through peripheral registers

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Pin

Number

Pinouts and pin description

Table 14. STM32L442KC pin definitions

Pin functions

Alternate functions Additional functions

PC14-

OSC32_I

N (PC14)

PC15-

OSC32_

OUT

(PC15)

NRST

VDDA/VR

EF+

I/O

(1)

(2)

(1)

(2)

I/O RST -

S -

PA0/

CK_IN

PA1

PA2

PA3

PA4

PA5

PA6

EVENTOUT

OSC32_IN

OSC32_OUT

I/O FT_a -

I/O

FT_a

TT_a -

I/O TT_a -

I/O FT_a -

TIM2_CH1, USART2_CTS,

COMP1_OUT, SAI1_EXTCLK,

TIM2_ETR, EVENTOUT

OPAMP1_VINP,

COMP1_INM, ADC1_IN5,

RTC_TAMP2, WKUP1,

CK_IN

TIM2_CH2, I2C1_SMBA,

SPI1_SCK,

USART2_RTS_DE,

TIM15_CH1N, EVENTOUT

TIM2_CH3, USART2_TX,

LPUART1_TX,

QUADSPI_BK1_NCS,

COMP2_OUT, TIM15_CH1,

EVENTOUT

TIM2_CH4, USART2_RX,

LPUART1_RX,

QUADSPI_CLK,

SAI1_MCLK_A, TIM15_CH2,

EVENTOUT

OPAMP1_VINM,

COMP1_INP, ADC1_IN6

COMP2_INM, ADC1_IN7,

WKUP4, LSCO

OPAMP1_VOUT,

COMP2_INP, ADC1_IN8

SPI1_NSS, SPI3_NSS,

USART2_CK, SAI1_FS_B,

LPTIM2_OUT, EVENTOUT

TIM2_CH1, TIM2_ETR,

SPI1_SCK, LPTIM2_ETR,

EVENTOUT

TIM1_BKIN, SPI1_MISO,

COMP1_OUT, USART3_CTS,

LPUART1_CTS,

QUADSPI_BK1_IO3,

TIM1_BKIN_COMP2,

TIM16_CH1, EVENTOUT

COMP1_INM,

COMP2_INM, ADC1_IN9,

DAC1_OUT1

COMP1_INM,

COMP2_INM, ADC1_IN10,

DAC1_OUT2

ADC1_IN11

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Pinouts and pin description

Pin

Number

Table 14. STM32L442KC pin definitions (continued)

Pin functions

STM32L442KC

Alternate functions Additional functions

PA7

PB0

PB1

VSS

VDD

PA8

PA9

PA10

PA11

PA12

PA13

(JTMS-

SWDIO)

I/O

FT_fa

FT_a

FT_f

FT_u

(3)

TIM1_CH1N, I2C3_SCL,

SPI1_MOSI,

QUADSPI_BK1_IO2,

COMP2_OUT, EVENTOUT

TIM1_CH2N, SPI1_NSS,

USART3_CK,

QUADSPI_BK1_IO1,

COMP1_OUT, SAI1_EXTCLK,

EVENTOUT

TIM1_CH3N,

USART3_RTS_DE,

LPUART1_RTS_DE,

QUADSPI_BK1_IO0,

LPTIM2_IN1, EVENTOUT

MCO, TIM1_CH1,

USART1_CK, SWPMI1_IO,

SAI1_SCK_A, LPTIM2_OUT,

EVENTOUT

TIM1_CH2, I2C1_SCL,

USART1_TX, SAI1_FS_A,

TIM15_BKIN, EVENTOUT

TIM1_CH3, I2C1_SDA,

USART1_RX,

USB_CRS_SYNC,

SAI1_SD_A, EVENTOUT

TIM1_CH4, TIM1_BKIN2,

SPI1_MISO, COMP1_OUT,

USART1_CTS, CAN1_RX,

USB_DM,

TIM1_BKIN2_COMP1,

EVENTOUT

TIM1_ETR, SPI1_MOSI,

USART1_RTS_DE,

CAN1_TX, USB_DP,

EVENTOUT

JTMS-SWDIO, IR_OUT,

USB_NOE, SWPMI1_TX,

SAI1_SD_B, EVENTOUT

ADC1_IN12

ADC1_IN15

COMP1_INM, ADC1_IN16

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STM32L442KC Pinouts and pin description

Table 14. STM32L442KC pin definitions (continued)

Pin functions

Pin

Number

Alternate functions Additional functions

PA14

(JTCK-

SWCLK)

PA15

(JTDI)

PB3

(JTDO-

TRACE

SWO)

PB4

(NJTRST)

PB5

PB6

PB7

I/O

FT_a

FT_fa

(3)

JTCK-SWCLK, LPTIM1_OUT,

I2C1_SMBA, SWPMI1_RX,

SAI1_FS_B, EVENTOUT

JTDI, TIM2_CH1, TIM2_ETR,

USART2_RX, SPI1_NSS,

SPI3_NSS,

USART3_RTS_DE,

TSC_G3_IO1,

SWPMI1_SUSPEND,

EVENTOUT

JTDO-TRACESWO,

TIM2_CH2, SPI1_SCK,

SPI3_SCK,

USART1_RTS_DE,

SAI1_SCK_B, EVENTOUT

NJTRST, I2C3_SDA,

SPI1_MISO, SPI3_MISO,

USART1_CTS, TSC_G2_IO1,

SAI1_MCLK_B, EVENTOUT

LPTIM1_IN1, I2C1_SMBA,

SPI1_MOSI, SPI3_MOSI,

USART1_CK, TSC_G2_IO2,

COMP2_OUT, SAI1_SD_B,

TIM16_BKIN, EVENTOUT

LPTIM1_ETR, I2C1_SCL,

USART1_TX, TSC_G2_IO3,

SAI1_FS_B, TIM16_CH1N,

EVENTOUT

LPTIM1_IN2, I2C1_SDA,

USART1_RX, TSC_G2_IO4,

EVENTOUT

COMP2_INM

COMP2_INP

COMP2_INM, PVD_IN

PH3/

BOOT0

VSS

VDD

I/O

EVENTOUT

BOOT0

1. PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC14 to PC15 in output mode is limited:

- The speed should not exceed 2 MHz with a maximum load of 30 pF

- These GPIOs must not be used as current sources (e.g. to drive an LED).

2. After a Backup domain power-up, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers which are not reset by the system reset. For details on how to manage these

GPIOs, refer to the Backup domain and RTC register descriptions in the RM0394 reference manual.

3. After reset, these pins are configured as JTAG/SW debug alternate functions, and the internal pull-up on

PA15, PA13, PB4 pins and the internal pull-down on PA14 pin are activated.

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AF0 AF1

Port

SYS_AF

TIM1/TIM2/

LPTIM1

Port A

PA2

PA3

PA4

PA5

PA6

PA7

PA8

PA9

PA10

PA11

PA12

PA0

PA1 -

MCO

TIM2_CH1

TIM2_CH2

PA13 JTMS-SWDIO IR_OUT

PA14 JTCK-SWCLK LPTIM1_OUT

PA15 JTDI TIM2_CH1

TIM2_CH3

TIM2_CH4

TIM2_CH1

TIM1_BKIN

TIM1_CH1N

TIM1_CH1

TIM1_CH2

TIM1_CH3

TIM1_CH4

TIM1_ETR

Table 15. Alternate function AF0 to AF7 (1)

AF2 AF3 AF4

TIM1/TIM2

TIM2_ETR

TIM1_BKIN2

TIM2_ETR

USART2

USART2_RX

I2C1/I2C2/I2C3

I2C1_SMBA

I2C3_SCL

I2C1_SCL

I2C1_SDA

I2C1_SMBA

AF5

SPI1/SPI2

SPI1_SCK

SPI1_NSS

SPI1_SCK

SPI1_MISO

SPI1_MOSI

SPI1_MISO

SPI1_MOSI

SPI1_NSS

AF6 AF7

SPI3

USART1/

USART2/

USART3

USART2_CTS

USART2_RTS_

USART2_TX -

SPI3_NSS

USART2_RX

USART2_CK

COMP1_OUT USART3_CTS

USART1_CK

USART1_TX

USART1_RX

COMP1_OUT USART1_CTS

USART1_RTS_

SPI3_NSS

USART3_RTS_

AF0 AF1

Table 15. Alternate function AF0 to AF7 (1) (continued)

AF2 AF3 AF4 AF5

Port

SYS_AF

TIM1/TIM2/

LPTIM1

PB0

PB1

TIM1_CH2N

TIM1_CH3N

PB3

Port B

PB4

PB5

PB6

PB7

PC14

Port C

PC15

Port H PH3

JTDO-

TRACESWO

NJTRST

TIM2_CH2

LPTIM1_IN1

LPTIM1_ETR

LPTIM1_IN2

1. Please refer to Table 16

for AF8 to AF15.

TIM1/TIM2

USART2

I2C1/I2C2/I2C3

I2C3_SDA

I2C1_SMBA

I2C1_SCL

I2C1_SDA

SPI1/SPI2

SPI1_NSS

SPI1_SCK

SPI1_MISO

SPI1_MOSI

AF6

SPI3

SPI3_SCK

SPI3_MISO

SPI3_MOSI

AF7

USART1/

USART2/

USART3

USART3_CK

USART3_RTS_

USART1_RTS_

USART1_CTS

USART1_CK

USART1_TX

USART1_RX

Port

Port A

PA0

PA1

AF8

LPUART1

PA3 LPUART1_RX

PA4 -

PA5 -

PA8

PA9

PA12

PA13

PA14 -

PA2 LPUART1_TX

PA6 LPUART1_CTS

PA7

PA10

PA11

PA15 -

AF9

CAN1/TSC

CAN1_RX

CAN1_TX

TSC_G3_IO1

Table 16. Alternate function AF8 to AF15 (1)

AF10

USB/QUADSPI

AF11

AF12 AF13

COMP1/

COMP2/

SWPMI1

SAI1

COMP1_OUT SAI1_EXTCLK

QUADSPI_

BK1_NCS

QUADSPI_CLK

QUADSPI_

BK1_IO3

QUADSPI_

BK1_IO2

USB_CRS_

SYNC

COMP2_OUT

TIM1_BKIN_

COMP2

COMP2_OUT

SWPMI1_IO

SAI1_MCLK_A

SAI1_FS_B

SAI1_SCK_A

SAI1_FS_A

SAI1_SD_A

USB_DM

USB_DP

USB_NOE

TIM1_BKIN2_

COMP1

SWPMI1_TX

SWPMI1_RX

SWPMI1_

SUSPEND

SAI1_SD_B

SAI1_FS_B

AF14

TIM2/TIM15/

TIM16/LPTIM2

TIM2_ETR

TIM15_CH1N

TIM15_CH1

TIM15_CH2

LPTIM2_OUT

LPTIM2_ETR

TIM16_CH1

LPTIM2_OUT

TIM15_BKIN

AF15

EVENTOUT

EVENTOUT

Port

PB0

AF8

LPUART1

PB1

Port B

PB3

PB4

PB5

PB6

PB7

PC14

Port C

PC15

Port H PH3

LPUART1_RTS

_DE

1. Please refer to Table 15 for AF0 to AF7.

TSC_G2_IO1

TSC_G2_IO2

TSC_G2_IO3

TSC_G2_IO4

AF9

Table 16. Alternate function AF8 to AF15 (1) (continued)

AF10 AF11 AF12 AF13

CAN1/TSC USB/QUADSPI -

COMP1/

COMP2/

SWPMI1

SAI1

QUADSPI_

BK1_IO1

QUADSPI_

BK1_IO0

COMP1_OUT SAI1_EXTCLK

COMP2_OUT

SAI1_SCK_B

SAI1_MCLK_B

SAI1_SD_B

SAI1_FS_B

AF14

TIM2/TIM15/

TIM16/LPTIM2

LPTIM2_IN1

TIM16_BKIN

TIM16_CH1N

AF15

EVENTOUT

EVENTOUT

Memory mapping STM32L442KC

Figure 6. STM32L442KC memory map

0xFFFF FFFF

Cortex™-M4 with FPU

Internal

Peripherals

0xE000 0000

0xC000 0000

QUADSPI registers

0xA000 1000

0xA000 0000

4 0x9000 0000

QUADSPI Flash bank

0x8000 0000

0x6000 0000

0xBFFF FFFF

0xA000 1400

0xA000 1000

Reserved

QUADSPI registers

0x5FFF FFFF

0x5006 0C00

0x4800 0000

0x4002 4400

0x4002 0000

0x4001 5800

0x4001 0000

0x4000 9800

0x4000 0000

0x1FFF FFFF

Reserved

AHB2

Reserved

AHB1

Reserved

APB2

Reserved

APB1

Reserved

0x4000 0000

0x2000 C000

0x2000 0000

Peripherals

SRAM2

SRAM1

CODE

0x0000 0000

Reserved

0x1FFF 7810

0x1FFF 7800

0x1FFF 7400

0x1FFF 7000

0x1FFF 0000

0x1000 4000

0x1000 0000

0x0804 0000

0x0800 0000

0x0004 0000

0x0000 0000

Options Bytes

Reserved

OTP area

System memory

Reserved

SRAM2

Reserved

Flash memory

Reserved

Flash, system memory or SRAM, depending on

BOOT configuration

MSv36892V2

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Table 17. STM32L442KC memory map and peripheral register boundary addresses (1)

Bus Boundary address Size(bytes) Peripheral

AHB2

AHB1

APB2

0x5006 0800 - 0x5006 0BFF

0x5006 0400 - 0x5006 07FF

0x5006 0000 - 0x5006 03FF

0x5004 0400 - 0x5006 5FFF

0x5004 0000 - 0x5004 03FF

0x5000 0000 - 0x5003 FFFF

0x4800 2000 - 0x4FFF FFFF

0x4800 1C00 - 0x4800 1FFF

0x4800 0C00 - 0x4800 1BFF

0x4800 0800 - 0x4800 0BFF

0x4800 0400 - 0x4800 07FF

0x4800 0000 - 0x4800 03FF

0x4002 4400 - 0x47FF FFFF

0x4002 4000 - 0x4002 43FF

0x4002 3400 - 0x4002 3FFF

0x4002 3000 - 0x4002 33FF

0x4002 2400 - 0x4002 2FFF

0x4002 2000 - 0x4002 23FF

0x4002 1400 - 0x4002 1FFF

0x4002 1000 - 0x4002 13FF

0x4002 0800 - 0x4002 0FFF

0x4002 0400 - 0x4002 07FF

0x4002 0000 - 0x4002 03FF

0x4001 5800 - 0x4001 FFFF

0x4001 5400 - 0x4000 57FF

0x4001 4800 - 0x4000 53FF

0x4001 4400 - 0x4001 47FF

0x4001 4000 - 0x4001 43FF

0x4001 3C00 - 0x4001 3FFF

0x4001 3800 - 0x4001 3BFF

0x4001 3400 - 0x4001 37FF

0x4001 3000 - 0x4001 33FF

0x4001 2C00 - 0x4001 2FFF

0x4001 2000 - 0x4001 2BFF

2 KB

1 KB

42 KB

1 KB

3 KB

1 KB

3 KB

1 KB

3 KB

1 KB

3 KB

1 KB

158 KB

1 KB

158 KB

RNG

Reserved

AES

Reserved

1 KB

16 KB

ADC

Reserved

~127 MB Reserved

1 KB GPIOH

4 KB

1 KB

Reserved

GPIOC

GPIOB

1 KB GPIOA

~127 MB Reserved

1 KB TSC

TIM16

TIM15

Reserved

USART1

Reserved

SPI1

TIM1

Reserved

CRC

Reserved

FLASH registers

Reserved

RCC

Reserved

DMA2

DMA1

Reserved

SAI1

Reserved

DS11450 Rev 4

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Memory mapping STM32L442KC

Table 17. STM32L442KC memory map and peripheral register boundary addresses (1)

(continued)

Bus Boundary address Size(bytes) Peripheral

APB2

APB1

0x4001 1C00 - 0x4001 1FFF

0x4001 0800- 0x4001 1BFF

0x4001 0400 - 0x4001 07FF

0x4001 0200 - 0x4001 03FF

0x4001 0030 - 0x4001 01FF

0x4001 0000 - 0x4001 002F

0x4000 9800 - 0x4000 FFFF

0x4000 9400 - 0x4000 97FF

0x4000 8C00 - 0x4000 93FF

0x4000 8800 - 0x4000 8BFF

0x4000 8400 - 0x4000 87FF

0x4000 8000 - 0x4000 83FF

0x4000 7C00 - 0x4000 7FFF

0x4000 7800 - 0x4000 7BFF

0x4000 7400 - 0x4000 77FF

0x4000 7000 - 0x4000 73FF

0x4000 6C00 - 0x4000 6FFF

0x4000 6800 - 0x4000 6BFF

0x4000 6400 - 0x4000 67FF

0x4000 6000 - 0x4000 63FF

0x4000 5C00- 0x4000 5FFF

0x4000 5800 - 0x4000 5BFF

0x4000 5400 - 0x4000 57FF

0x4000 4800 - 0x4000 53FF

0x4000 4400 - 0x4000 47FF

0x4000 4000 - 0x4000 43FF

0x4000 3C00 - 0x4000 3FFF

0x4000 3400 - 0x4000 3BFF

0x4000 3000 - 0x4000 33FF

0x4000 2C00 - 0x4000 2FFF

0x4000 2800 - 0x4000 2BFF

0x4000 1800 - 0x4000 27FF

0x4000 1400 - 0x4000 17FF

1 KB

5 KB

1 KB

2 KB

1 KB

4 KB

1 KB

3 KB

26 KB

1 KB

2 KB

1 KB

CAN1

CRS

I2C3

Reserved

I2C1

Reserved

USART2

Reserved

SPI3

Reserved

IWDG

WWDG

RTC

Reserved

TIM7

FIREWALL

Reserved

EXTI

COMP

Reserved

SYSCFG

Reserved

LPTIM2

Reserved

SWPMI1

Reserved

LPUART1

LPTIM1

OPAMP

DAC1

PWR

USB SRAM

USB FS

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DS11450 Rev 4

STM32L442KC Memory mapping

Table 17. STM32L442KC memory map and peripheral register boundary addresses (1)

(continued)

Bus Boundary address Size(bytes) Peripheral

APB1

0x4000 1000 - 0x4000 13FF

0x4000 0400- 0x4000 0FFF

0x4000 0000 - 0x4000 03FF

1. The gray color is used for reserved boundary addresses.

1 KB

3 KB

1 KB

TIM6

Reserved

TIM2

DS11450 Rev 4

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Electrical characteristics STM32L442KC

6.1.1

Unless otherwise specified, all voltages are referenced to V

Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T

A the selected temperature range).

= 25 °C and T

= T

A max (given by

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ±3 σ ).

Unless otherwise specified, typical data are based on T

A are given only as design guidelines and are not tested.

= 25 °C, V

= V

DDA

= 3 V. They

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ±2 σ )

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

6.1.5

The loading conditions used for pin parameter measurement are shown in

Figure 7

Pin input voltage

The input voltage measurement on a pin of the device is described in

Figure 8 .

Figure 7. Pin loading conditions Figure 8. Pin input voltage

MCU pin MCU pin

C = 50 pF

MS19210V1

MS19211V1

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DS11450 Rev 4

STM32L442KC

6.1.6 Power supply scheme

Figure 9. Power supply scheme

Electrical characteristics

1.55 – 3.6 V

Backup circuitry

(LSE, RTC,

Backup registers)

CORE n x VDD n x 100 nF

+1 x 4.7 μF

GPIOs

Regulator

DDIO1

OUT

IO logic

Kernel logic

(CPU, Digital

& Memories) n x VSS

10 nF

+1 μF

DDA

REF

VDDA

100 nF +1 μF

REF+

REF-

ADCs/

DACs/

OPAMPs/

COMPs

VSSA

MSv40915V2

Caution: Each power supply pair (V

, V

DDA

SSA

etc.) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device.

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149

Electrical characteristics

Figure 10. Current consumption measurement scheme

DD_USB

DDUSB

STM32L442KC

DDA

MSv41630V1

The I

DD_ALL

parameters given in

Table 25 to

Table 37 represent the total MCU consumption

including the current supplying V

, V

DDA

, V

DDUSB

and V

BAT

6.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in

Table 18: Voltage characteristics

Table 19: Current characteristics

and

Table 20: Thermal characteristics may cause

permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 qualification standard, extended mission profiles are available on demand.

Symbol

DDX

- V

(2)

| ∆ V

DDx

SSx

-V

Table 18. Voltage characteristics (1)

Ratings Min

External main supply voltage (including

, V

DDA

, V

DDUSB

)

-0.3

Input voltage on FT_xxx pins

Input voltage on TT_xx pins

Input voltage on any other pins

Variations between different V

DDX pins of the same domain

power

Variations between all the different ground pins

(5)

-0.3

Max

4.0

min (V

, V

+ 4.0

4.0

, V

DDUSB

)

Unit

V mV mV

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DS11450 Rev 4

STM32L442KC Electrical characteristics

1. All main power (V

, V in the permitted range.

DDA

, V

DDUSB

) and ground (V

, V

SSA

) pins must always be connected to the external power supply,

2. V

maximum must always be respected. Refer to

Table 19: Current characteristics for the maximum allowed injected

current values.

3. This formula has to be applied only on the power supplies related to the IO structure described in the pin definition table.

4. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.

5. Include VREF- pin.

Symbol

∑ IV

DD(PIN)

SS(PIN)

Table 19. Current characteristics

Ratings

Total current into sum of all V

power lines (source)

(1)

Total current out of sum of all V

ground lines (sink)

(1)

Maximum current into each V

power pin (source)

(1)

Maximum current out of each V

ground pin (sink)

(1)

Output current sunk by any I/O and control pin except FT_f

Max

140

100

Unit

IO(PIN)

∑ I

IO(PIN)

Output current sunk by any FT_f pin

Output current sourced by any I/O and control pin

Total output current sunk by sum of all I/Os and control pins

(2)

Total output current sourced by sum of all I/Os and control pins

(2)

100 mA

100

INJ(PIN)

(3)

Injected current on FT_xxx, TT_xx, RST and B pins, except PA4,

PA5

-5/+0

(4)

∑ |I

INJ(PIN)

Injected current on PA4, PA5

Total injected current (sum of all I/Os and control pins) (5)

-5/0

1. All main power (V

, V

DDA

, V

DDUSB

) and ground (V

, V

SSA

) pins must always be connected to the external power

2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.

3. Positive injection (when V specified maximum value.

> V

DDIOx

) is not possible on these I/Os and does not occur for input voltages lower than the

4. A negative injection is induced by V

< V

. I

INJ(PIN)

must never be exceeded. Refer also to

Table 18: Voltage characteristics

for the maximum allowed input voltage values.

5. When several inputs are submitted to a current injection, the maximum ∑ |I injected currents (instantaneous values).

INJ(PIN)

| is the absolute sum of the negative

Symbol

STG

Table 20. Thermal characteristics

Ratings

Storage temperature range

Maximum junction temperature

Value

–65 to +150

150

Unit

°C

DS11450 Rev 4

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149

Electrical characteristics STM32L442KC

6.3.1 General operating conditions

Table 21. General operating conditions

Symbol f

HCLK f

PCLK1 f

PCLK2

Parameter

Internal AHB clock frequency

Internal APB1 clock frequency

Internal APB2 clock frequency

Conditions

Min

Standard operating voltage -

1.71

(1)

Max

3.6

Unit

MHz

DDA

DDUSB

Analog supply voltage

USB supply voltage

I/O input voltage

ADC or COMP used

DAC or OPAMP used

ADC, DAC, OPAMP, COMP not used

USB used

USB not used

TT_xx I/O

All I/O except TT_xx

1.62

1.8

3.0

-0.3

3.6

DDIOx

+0.3

Min(Min(V

DDUSB

, V

DDA

5.5 V)

)+3.6 V,

(2)(3)

Power dissipation at

= 125 °C for suffix 3

(4)

Power dissipation at

= 85 °C for suffix 6 or

= 105 °C for suffix 7

(4)

UFQFPN32

UFQFPN32 -

128

523 mW mW

Ambient temperature for the suffix 6 version

Ambient temperature for the suffix 7 version

Ambient temperature for the suffix 3 version

Maximum power dissipation

Low-power dissipation

(5)

Maximum power dissipation

Low-power dissipation

(5)

Maximum power dissipation

Low-power dissipation

(5)

Suffix 6 version

–40

105

125

130

105

°C

Junction temperature range Suffix 7 version

Suffix 3 version

–40

125

130

1. When RESET is released functionality is guaranteed down to V

BOR0

Min.

2. This formula has to be applied only on the power supplies related to the IO structure described by the pin definition table.

Maximum I/O input voltage is the smallest value between Min(V

, V

DDA

, V

DDUSB

)+3.6 V and 5.5V.

3. For operation with voltage higher than Min (V be disabled.

, V

DDA

, V

DDUSB

) +0.3 V, the internal Pull-up and Pull-Down resistors must

4. If T

is lower, higher P

values are allowed as long as T

does not exceed T

Jmax

(see Section 7.2: Thermal characteristics

°C

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DS11450 Rev 4

STM32L442KC Electrical characteristics

5. In low-power dissipation state, T

Thermal characteristics

can be extended to this range as long as T

does not exceed T

Jmax

(see Section 7.2:

6.3.3

The parameters given in

Table 22 are derived from tests performed under the ambient

temperature condition summarized in

Table 21 .

Symbol t

VDD t

VDDA t

VDDUSB

Table 22. Operating conditions at power-up / power-down

Parameter Conditions Min Max

rise time rate

fall time rate

DDA

rise time rate

DDA

fall time rate

DDUSB

rise time rate

DDUSB

fall time rate

∞

Unit

µs/V

The requirements for power-up/down sequence specified in Section 3.9.1: Power supply schemes must be respected.

Embedded reset and power control block characteristics

The parameters given in

Table 23 are derived from tests performed under the ambient

temperature conditions summarized in Table 21: General operating conditions

Table 23. Embedded reset and power control block characteristics

Symbol Parameter Conditions

(1)

Min Typ Max t

RSTTEMPO

(2)

Reset temporization after

BOR0 is detected

DD rising 250 400

BOR0

(2)

BOR1

BOR2

BOR3

BOR4

PVD0

Brown-out reset threshold 0

Brown-out reset threshold 1

Brown-out reset threshold 2

Brown-out reset threshold 3

Brown-out reset threshold 4

Programmable voltage detector threshold 0

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

1.62

1.6

2.06

1.96

2.26

2.16

2.56

2.47

2.85

2.76

2.1

1.66

1.64

2.1

2.31

2.20

2.61

2.52

2.90

2.81

2.15

2.05

1.7

1.69

2.14

2.04

2.35

2.24

2.66

2.57

2.95

2.86

2.19

2.1

Unit

μ s

DS11450 Rev 4

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149

Electrical characteristics STM32L442KC

Table 23. Embedded reset and power control block characteristics (continued)

Symbol Parameter Conditions (1) Min Typ Max Unit

PVD1

PVD2

PVD3

PVD4

PVD5

PVD6 hyst_BORH0

PVD threshold 1

PVD threshold 2

PVD threshold 3

PVD threshold 4

PVD threshold 5

PVD threshold 6

Hysteresis voltage of BORH0

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Hysteresis in continuous mode

Hysteresis in other mode

V hyst_BOR_PVD

(BOR_PVD)

(2)

PVM1

Hysteresis voltage of BORH

(except BORH0) and PVD

BOR (3) (except BOR0) and

PVD consumption from V

DDUSB

peripheral voltage monitoring

PVM3

PVM4 hyst_PVM3

V hyst_PVM4

(PVM1)

(2)

V monitoring

DDA

peripheral voltage

peripheral voltage monitoring

PVM3 hysteresis

PVM4 hysteresis

PVM1 consumption from V

Rising edge

Falling edge

Rising edge

Falling edge

2.56

2.47

2.69

2.59

2.26

2.15

2.41

2.31

2.85

2.75

2.92

2.84

1.18

1.61

1.6

1.78

1.77

100

1.1

1.22

1.65

1.64

1.82

1.81

2.61

2.52

2.74

2.64

2.31

2.20

2.46

2.36

2.91

2.81

2.98

2.90

0.2

1.69

1.68

1.86

1.85

2.66

2.57

2.79

2.69

2.36

2.25

2.51

2.41

2.96

2.86

3.04

2.96

1.6

1.26

V mV mV

µA

V mV mV

µA

(PVM3/PVM4)

(2)

PVM3 and PVM4 consumption from V

2 µA

1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes.

2. Guaranteed by design.

3. BOR0 is enabled in all modes (except shutdown) and its consumption is therefore included in the supply current characteristics tables.

70/157

DS11450 Rev 4

STM32L442KC Electrical characteristics

The parameters given in

Table 24 are derived from tests performed under the ambient

temperature and supply voltage conditions summarized in Table 21: General operating conditions

Symbol

Table 24. Embedded internal voltage reference

Parameter Conditions Min Typ Max

REFINT

Internal reference voltage t t

S_vrefint

(1) start_vrefint

ADC sampling time when reading the internal reference voltage

Start time of reference voltage buffer when ADC is enable

REFINTBUF

)

REFINT

buffer consumption from V

ADC

when converted by

–40 °C < T

< +130 °C

∆ V

REFINT

Internal reference voltage spread over the temperature range

= 3 V

Coeff

DDCoeff

REFINT_DIV1

REFINT_DIV2

REFINT_DIV3

Temperature coefficient

Long term stability

Voltage coefficient

1/4 reference voltage

1/2 reference voltage

3/4 reference voltage

–40°C < T

< +130°C

1000 hours, T = 25°C

3.0 V < V

< 3.6 V

1. The shortest sampling time can be determined in the application by multiple iterations.

2. Guaranteed by design.

1.182

1.212

1.232

(2)

12.5

7.5

(2)

30 50

(2)

300 1000

(2)

250 1200

(2)

Unit

µs

µA mV ppm/°C ppm ppm/V

REFINT

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149

Electrical characteristics STM32L442KC

1.235

1.23

1.225

1.22

1.215

1.21

1.205

1.2

1.195

1.19

1.185

-40 -20

Figure 11. V

REFINT

versus temperature

0 20

Mean

Min

Max

80 100 120 °C

MSv40169V1

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6.3.5

Electrical characteristics

Supply current characteristics

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code.

The current consumption is measured as described in

Figure 10: Current consumption measurement scheme

Typical and maximum current consumption

The MCU is placed under the following conditions:

• All I/O pins are in analog input mode

• All peripherals are disabled except when explicitly mentioned

• The Flash memory access time is adjusted with the minimum wait states number, depending on the f

HCLK

frequency (refer to the table “Number of wait states according to CPU clock (HCLK) frequency” available in the RM0394 reference manual).

• When the peripherals are enabled f

PCLK

= f

HCLK

The parameters given in

Table 25 to

Table 37 are derived from tests performed under

ambient temperature and supply voltage conditions summarized in

Table 21: General operating conditions

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149

Symbol Parameter

DD_ALL

(Run)

DD_ALL

(LPRun)

Table 25. Current consumption in Run and Low-power run modes, code with data processing running from Flash, ART enable (Cache ON Prefetch OFF)

Conditions TYP MAX

(1)

Voltage scaling f

HCLK

25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C

Unit

26 MHz 2.37

2.38

2.44

16 MHz 1.5

1.52

1.57

2.52

1.64

2.66

1.79

2.7

1.7

2.7

1.7

2.8

1.8

2.9

2.0

3.2

2.3

Supply current in

Run mode f

HCLK

= f

HSE

up to

48MHz included, bypass mode

PLL ON above

48 MHz all peripherals disable

Range 2

8 MHz 0.81

0.82

0.87

4 MHz 0.46

0.47

0.52

2 MHz 0.29

0.3

1 MHz 0.2

0.21

0.34

0.25

100 kHz 0.12

0.13

0.17

80 MHz 8.53

8.56

8.64

72 MHz 7.7

7.73

64 MHz 6.86

6.9

7.8

6.97

Supply current in

Low-power run mode f

HCLK

= f

MSI all peripherals disable

Range 1 48 MHz 5.13

5.16

5.23

32 MHz 3.46

3.48

3.55

24 MHz 2.63

2.64

2.71

16 MHz 1.8

1.81

1.87

2 MHz 211 230

1 MHz 117 134

280

179

400 kHz 58.5

70.4

100 kHz 30 41.1

116

85.2

355

254

189

159

5.32

3.64

2.79

1.96

0.24

8.74

7.9

7.06

0.94

0.59

0.41

0.32

0.38

8.92

8.08

7.23

1.08

0.73

0.55

0.46

0.1

9.5

8.6

7.7

0.9

0.5

0.3

0.2

9.6

8.6

7.7

0.9

0.6

0.4

0.3

0.2

9.7

8.7

7.8

1.0

0.6

0.4

0.3

0.4

9.9

8.9

8.0

1.2

0.8

0.6

0.5

5.49

3.8

2.96

2.12

5.8

3.9

3.0

2.0

5.8

4.0

3.0

2.1

6.0

4.1

3.1

2.2

6.1

4.2

3.3

2.3

506 273.8

301.1

360.4

502.7

815.9

404 154.7

184.6

249.6

398.4

712.4

338

308

80.2

46.5

111.5

76.6

179.7

147.1

330.8

299.1

643.4

611.2

6.5

4.6

3.6

2.7

0.7

10.3

9.3

8.3

1.5

1.1

0.9

0.8

µA

1. Guaranteed by characterization results, unless otherwise specified.

Symbol Parameter

Table 26. Current consumption in Run and Low-power run modes, code with data processing running from Flash, ART disable

Conditions TYP MAX

(1)

Voltage scaling f

HCLK

25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C

Unit

DD_ALL

(Run)

DD_ALL

(LPRun)

Supply current in

Run mode f

HCLK

= f

HSE

up to

48MHz included, bypass mode

PLL ON above

48 MHz all peripherals disable

Supply current in

Low-power run f

HCLK

= f

MSI all peripherals disable

Range 2

Range 1

26 MHz 2.66

2.68

2.73

16 MHz 1.88

1.9

1.94

8 MHz 1.05

1.06

1.11

4 MHz 0.6

0.62

0.66

2 MHz 0.36

0.37

0.34

1 MHz 0.23

0.25

100 kHz 0.12

0.14

0.17

80 MHz 8.56

8.61

8.69

72 MHz 7.74

7.79

7.86

64 MHz 7.63

7.68

7.75

48 MHz 6.36

6.4

32 MHz 4.56

4.6

6.48

4.66

24 MHz 3.45

3.48

3.54

16 MHz 2.48

2.51

2.56

2 MHz 310 317 364

1 MHz 157 173 226

400 kHz 72.6

100 kHz 32.3

130

89.7

1. Guaranteed by characterization results, unless otherwise specified.

8.79

7.96

7.85

6.58

4.76

3.64

2.65

440

2.81

2.02

1.18

0.73

0.48

0.36

0.25

296

206

164

2.96

2.17

1.33

0.87

0.62

0.5

0.39

3.0

2.1

1.2

0.7

0.4

0.3

0.1

3.1

2.2

1.2

0.7

0.4

0.3

0.2

3.2

2.3

1.3

0.8

0.5

0.4

0.2

3.3

2.4

1.4

0.9

0.6

0.5

0.4

8.97

8.14

8.04

6.76

4.93

3.8

2.82

9.6

8.7

8.6

7.2

5.2

3.9

2.8

9.7

8.7

8.6

7.3

5.2

4.0

2.9

9.8

8.8

8.7

7.4

5.3

4.1

3.0

10.0

9.0

8.9

7.6

5.5

4.2

3.1

10.3

9.4

9.3

7.9

5.8

4.6

3.5

593 375.3

400.9

456.7

595.3

909.6

3.6

2.7

1.7

1.2

0.9

0.8

0.7

448 204.8

234.2

298.2

445.8

758.9

356

314

99.7

131.2

199.7

349.3

663.7

52.4

82.1

153.3

301.2

616.9

µA

Table 27. Current consumption in Run and Low-power run modes, code with data processing running from SRAM1

Conditions TYP MAX

(1)

Symbol Parameter

Voltage scaling f

HCLK

25 °C 55 °C 85 °C

105

°C

125

°C

25 °C 55 °C 85 °C

DD_ALL

(Run)

DD_ALL

(LPRun)

Supply current in

Run mode

Supply current in low-power run mode f

HCLK

48MHz included, bypass mode

PLL ON above

48 MHz all peripherals disable f

HCLK

= f

HSE

= f

MSI

up to

Range 2

Range 1 all peripherals disable

FLASH in power-down

26 MHz 2.42

2.43

2.49

2.56

2.71

16 MHz 1.54

1.55

1.6

1.67

1.82

8 MHz 0.82

0.84

0.88

0.95

1.1

4 MHz 0.47

0.48

0.52

0.59

0.73

2 MHz 0.29

0.3

0.34

0.41

0.55

1 MHz 0.2

0.21

0.25

0.32

0.46

2.7

1.7

0.9

0.5

0.3

0.2

2.7

1.7

1.0

0.6

0.4

0.3

2.8

1.8

1.0

0.6

0.4

0.3

3.0

2.0

1.2

0.8

0.6

0.5

100 kHz 0.12

0.13

0.17

0.24

0.38

80 MHz 8.63

8.68

8.74

8.84

9.01

72 MHz 7.79

7.83

7.9

7.99

8.17

64 MHz 6.95

6.99

7.05

7.15

7.32

48 MHz 5.19

5.22

5.29

5.38

5.55

32 MHz 3.51

3.53

3.6

3.68

3.85

24 MHz 2.66

2.68

2.74

2.83

2.99

16 MHz 1.82

1.84

1.89

1.98

2.14

2 MHz 205 228 275 352

0.1

9.5

8.6

7.7

5.8

3.9

3.0

2.0

0.2

9.6

8.6

7.7

5.8

4.0

3.0

2.1

0.2

9.7

8.8

7.9

5.9

4.1

3.1

2.2

0.4

9.9

8.9

8.0

6.1

4.2

3.3

2.3

0.7

10.2

9.3

8.4

6.5

4.6

3.6

2.7

501 276.5

302.3

358.4

502.5

816.4

3.3

2.3

1.5

1.1

0.9

0.8

1 MHz 111 126 175 248 397 151.3

180.9

245.3

390.7

703.4

400 kHz 49.2

62.7

108

100 kHz 21.5

33.3

76.6

181

151

330 73.3

104.0

170.8

321.0

632.4

299 36.4

67.7

137.2

287.8

600.8

1. Guaranteed by characterization results, unless otherwise specified.

105

°C

125

°C

Unit mA

µA

STM32L442KC Electrical characteristics

Table 28. Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART enable (Cache ON Prefetch OFF)

Conditions TYP TYP

Symbol Parameter Unit Unit

Voltage scaling

Code 25 °C 25 °C

Reduced code

(1)

2.37

Coremark 2.69

103 mA µA/MHz

DD_ALL

(Run)

DD_ALL

(LPRun)

Supply current in

Run mode f

HCLK

= f

HSE

up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable

Supply current in

Low-power run f

HCLK

= f

MSI

= 2 MHz all peripherals disable

Dhrystone 2.1

Fibonacci

2.74

2.58

While(1) 2.30

Reduced code

(1)

8.53

Coremark

Dhrystone 2.1

Fibonacci

While(1)

Reduced code

(1)

Coremark

9.68

9.76

9.27

8.20

Dhrystone 2.1

Fibonacci

While(1)

211

251

269

230

286 mA

µA

121

122

116

103

105

107

106

126

135

115

143

µA/MHz

1. Reduced code used for characterization results provided in Table 25 ,

Table 26 ,

Table 27

DS11450 Rev 4

77/157

149

Electrical characteristics STM32L442KC

Table 29. Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART disable

TYP Conditions TYP

Symbol Parameter

Voltage scaling

Code 25 °C

DD_ALL

(Run)

DD_ALL

(LPRun)

Supply current in

Run mode

Supply current in

Low-power run f f

HCLK HSE

48 MHz included, bypass mode

PLL ON above

48 MHz all peripherals disable

HCLK

= f

MSI

up to

= 2 MHz all peripherals disable

Reduced code

(1)

2.66

Coremark 2.44

Dhrystone 2.1

Fibonacci

While(1)

Reduced code

(1)

Coremark

Dhrystone 2.1

Fibonacci

2.46

2.27

2.20

8.56

8.00

7.98

7.41

While(1)

Reduced code

(1)

Coremark

Dhrystone 2.1

Fibonacci

While(1)

7.83

310

342

324

384

1. Reduced code used for characterization results provided in Table 25 ,

Table 26 ,

Table 27

Unit mA mA

µA

25 °C

Unit

µA/MHz

155

171

162

107

100

162

192

102

84.6

Table 30. Typical current consumption in Run and Low-power run modes, with different codes running from SRAM1

TYP Conditions TYP

Symbol Parameter

Voltage scaling

Code 25 °C

DD_ALL

(Run)

DD_ALL

(LPRun)

Supply current in

Run mode f

HCLK

= f

HSE

up to

48 MHz included, bypass mode

PLL ON above

48 MHz all peripherals disable

Supply current in

Low-power run f

HCLK

= f

MSI

= 2 MHz all peripherals disable

Reduced code

(1)

2.42

Coremark

Dhrystone 2.1

2.18

2.40

Fibonacci

While(1)

Reduced code

(1)

Coremark

Dhrystone 2.1

Fibonacci

While(1)

Reduced code

(1)

Coremark

Dhrystone 2.1

Fibonacci

2.40

2.29

8.63

7.76

8.55

8.56

8.12

205

188

222

204

While(1)

1. Reduced code used for characterization results provided in Table 25 ,

Table 26 ,

Table 27

211

Unit mA mA

µA

25 °C

Unit

µA/MHz

107

102

103

111

102

106

108

78/157

DS11450 Rev 4

Symbol Parameter

Table 31. Current consumption in Sleep and Low-power sleep modes, Flash ON

Conditions

Voltage scaling f

HCLK

TYP MAX

(1)

25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C

Unit

DD_ALL

(Sleep)

DD_ALL

(LPSleep)

Supply current in sleep mode, f

HCLK

= f

HSE

up to 48 MHz included, bypass mode pll ON above

48 MHz all peripherals disable

Range 2

Range 1

Supply current in low-power sleep mode f

HCLK

= f

MSI all peripherals disable

26 MHz 0.68

0.69

0.74

16 MHz 0.46

0.48

0.52

8 MHz 0.29

0.30

0.34

4 MHz 0.20

0.21

0.25

2 MHz 0.16

0.17

0.21

1 MHz 0.13

0.15

0.19

100 kHz 0.11

0.13

0.17

80 MHz 2.23

2.25

2.30

72 MHz 2.02

2.04

2.10

64 MHz 1.82

1.84

1.89

48 MHz 1.34

1.36

1.42

32 MHz 0.93

0.95

1.01

24 MHz 0.73

0.75

0.80

16 MHz 0.53

0.55

0.60

2 MHz 71.8

80.7

125

1 MHz 45.0

57.3

101

0.81

0.59

0.41

0.32

0.28

0.26

0.24

2.38

2.18

1.98

1.50

1.09

0.88

0.68

200

176

400 kHz 27.0

40.7

84.6

158 308 43.9

100 kHz 22.8

30.9

63.3

113.2

207.7

35.2

0.38

2.54

2.34

2.14

1.66

1.25

1.04

0.84

350

0.95

0.73

0.55

0.46

0.42

0.40

325

0.8

0.5

0.3

0.2

0.1

0.8

0.6

0.4

0.3

0.2

0.9

0.6

0.4

0.3

1.0

0.8

0.6

0.5

0.4

1.5

1.1

0.8

0.6

0.1

2.5

2.2

2.0

0.2

2.5

2.3

2.1

1.6

1.1

0.9

0.6

0.2

2.6

2.4

2.1

1.7

1.2

1.0

0.7

0.4

2.8

2.5

2.3

1.8

1.4

1.1

0.9

0.7

3.1

2.9

2.6

2.2

1.7

1.4

1.2

91.1

122.7

191.3

341.5

653.5

1.3

1.1

0.9

0.8

0.7

63.2

95.4

165.4

316.5

628.7

75.8

67.9

147.2

140.9

297.6

290.8

609.2

602.4

1. Guaranteed by characterization results, unless otherwise specified.

µA

Symbol Parameter

Table 32. Current consumption in Low-power sleep modes, Flash in power-down

Conditions TYP MAX

(1)

Voltage scaling f

HCLK

25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C

Unit

DD_ALL

(LPSleep)

Supply current in low-power sleep mode f

HCLK

= f

MSI all peripherals disable

2 MHz 58.7

70.7

103.2

153.7

248.5

1 MHz

400 kHz

39.4

20.8

47.2

30.8

79.3

62.1

129.6

112.5

224.8

207.8

100 kHz 14.3

23.1

55.1

105.7

201.5

1. Guaranteed by characterization results, unless otherwise specified.

113

180

154

137

130

330

304

286

279

641

616

597

590

µA

Symbol

DD_ALL

(Stop 2)

DD_ALL

(Stop 2 with

RTC)

Parameter

Supply current in

Stop 2 mode,

RTC disabled

Table 33. Current consumption in Stop 2 mode

Conditions

RTC clocked by LSI

Supply current in

Stop 2 mode,

RTC enabled

RTC clocked by LSE bypassed at 32768 Hz

RTC clocked by LSE quartz

(2) in low drive mode

TYP MAX

(1)

25 °C 55 °C 85 °C

1.8 V 1 2.54

8.74

2.4 V 1.02

2.59

8.89

3 V 1.06

2.67

9.11

3.6 V 1.23

2.88

9.56

1.8 V 1.3

2.82

9.02

2.4 V 1.39

2.95

9.24

3 V 1.5

3.11

9.55

3.6 V 1.76

3.42

10.1

1.8 V 1.36

2.9

9.1

2.4 V 1.48

3.09

9.44

3 V 1.83

3.67

10.4

3.6 V 3.58

6.17

13.9

1.8 V 1.28

2.81

9.13

2.4 V 1.39

2.93

9.34

3 V 1.59

3.1

9.64

3.6 V 1.86

3.45

10.2

105 °C 125 °C 25 °C

19.8

20.2

20.7

21.6

20.1

20.5

21.1

22.1

20.1

20.8

22.3

26.6

20.8

21.3

21.8

22.8

43.4

44.3

45.5

47.3

43.6

44.6

45.8

47.8

43.7

47.3

2.0

2.1

2.3

2.5

2.8

3.0

3.3

55 °C

5.6

5.8

5.9

6.1

6.2

6.4

6.8

7.2

85 °C 105 °C 125 °C

21.1

21.6

22.2

23.0

21.6

22.3

23.0

24.1

50.8

116.0

52.3

119.6

53.7

123.2

55.8

127.9

51.3

116.3

52.8

120.0

54.5

123.8

56.7

128.7

Unit

µA

Symbol Parameter

DD_ALL

(wakeup from

Stop2)

Supply current during wakeup from Stop 2 mode

Table 33. Current consumption in Stop 2 mode (continued)

Conditions

TYP MAX

(1)

25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C

Wakeup clock is

MSI = 48 MHz, voltage Range 1.

See

(3)

Wakeup clock is

MSI = 4 MHz, voltage Range 2.

See

(3)

Wakeup clock is

HSI16 = 16 MHz, voltage Range 1.

See

(3)

3 V 1.85

3 V 1.52

3 V 1.54

Unit mA

1. Guaranteed based on test during characterization, unless otherwise specified.

2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.

3. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 39: Low-power mode wakeup timings .

Symbol

DD_ALL

(Stop 1)

DD_ALL

(Stop 1 with

RTC)

Parameter

Supply current in

Stop 1 mode,

RTC disabled

Supply current in stop

1 mode,

RTC enabled

RTC clocked by LSI

Table 34. Current consumption in Stop 1 mode

Conditions

RTC clocked by LSE bypassed, at 32768 Hz

RTC clocked by LSE quartz

(2) in low drive mode

TYP MAX

(1)

25 °C 55 °C 85 °C 105 °C 125 °C 25 °C

1.8 V 4.34

12.4

43.6

96.4

2.4 V 4.35

12.5

43.8

3 V 4.41

12.6

44.1

97.7

3.6 V 4.56

12.9

44.8

98.9

1.8 V 4.63

12.7

43.9

96.8

2.4 V 4.78

12.8

44.2

97.4

3 V 4.93

13 44.6

98.1

3.6 V 5.05

13.4

45.3

99.5

1.8 V 4.7

12.8

44 96.9

2.4 V 4.95

13 44.4

97.6

3 V 5.33

13.6

45.4

99.1

3.6 V 6.91

16.1

48.8

103

1.8 V 4.76

12.3

43.7

99.1

2.4 V 4.95

12.4

43.8

99.3

3 V 5.1

12.6

44.1

99.6

3.6 V 5.65

13 44.8

101

204

205

207

210

205

206

207

210

205

206

209

216

9.3

9.4

9.5

9.7

9.9

10.1

10.4

10.8

55 °C

27.4

27.6

85 °C 105 °C 125 °C

98.9

99.5

198.7

199.0

397.5

398.0

27.8

100.3

200.4

400.8

28.3

101.7

202.1

404.2

28.0

99.5

198.9

397.8

28.3

100.3

199.5

399.0

28.7

101.2

200.9

401.9

29.4

102.8

202.5

405.0

Unit

µA

DD_ALL

(wakeup from Stop1)

Supply current during wakeup from

Stop 1

Wakeup clock MSI = 48 MHz, voltage Range 1.

See

(3)

Wakeup clock MSI = 4 MHz, voltage Range 2.

See

(3)

Wakeup clock HSI16 =

16 MHz, voltage Range 1.

See

(3)

3 V 1.14

3 V 1.22

3 V 1.20

1. Guaranteed based on test during characterization, unless otherwise specified.

2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.

3. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 39: Low-power mode wakeup timings .

Symbol

DD_ALL

(Stop 0)

Parameter

Supply current in

Stop 0 mode,

RTC disabled

Conditions

Table 35. Current consumption in Stop 0

TYP MAX

(1)

25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C

Unit

1.8 V

2.4 V

3 V

3.6 V

108 119

110 121

111 123

114 125

158

160

161

163

221

223

224

227

347

349

352

355

133

136

139

142

158

161

164

167

244

248

251

254

395

399

704

710

403 716

408 722

(2)

µA

1. Guaranteed by characterization results, unless otherwise specified.

2. Guaranteed by test in production.

Symbol

DD_ALL

(Standby)

DD_ALL

(Standby with RTC)

Parameter

Supply current in Standby mode (backup registers retained),

RTC disabled

Supply current in Standby mode (backup registers retained),

RTC enabled

Table 36. Current consumption in Standby mode

Conditions

no independent watchdog with independent watchdog

RTC clocked by LSI, no independent watchdog

TYP MAX

(1)

25 °C 55 °C 85 °C 105 °C 125 °C 25 °C

1.8 V 27.7

144

2.4 V 50.9

187

758

892

2 072

2 408

5 425

6 247

119

183

55 °C

425

564

85 °C 105 °C 125 °C

2866

3383

7524

8778

20510

23768

3 V 90.2

253 1 090 2 884 7 409 225

3.6 V 253 459 1 474 3 575 8 836 292

1.8 V 216

2.4 V 342

681

877

3912 10071 26976

4638 11659 30758

3 V 416

3.6 V 551

1.8 V 287

2.4 V 386

407

526

989

1 201

2 230

2 638

5 396

6 274

585

811

944

1230

3344

4007

7866

9246

20504

23824

3 V

3.6 V

513 679 1 478 3 167 7 414 1022 1521 4683 10671 27124

771 978 1 963 3 992 9 039 1284 1924 5577 12383

30954

(2)

Unit nA nA

RTC clocked by LSI, with independent watchdog

RTC clocked by LSE bypassed at 32768Hz

RTC clocked by LSE quartz

(3)

in low drive mode

1.8 V 342

2.4 V 521

3 V 655 -

3.6 V 865

1.8 V 142

126

865

2 220 5 650

2.4 V 249

3 V 404

219

364

1 090

1 410

2 660

3 260

6 600

7 850

3.6 V 742

1.8 V 281

670 2 000 4 230 9 700

423 1 046 2 410 5 700

2.4 V 388

3 V 535

548

715

1 268

1 565

2 847

3 420

6 564

7 694

3.6 V 836 1 048 2 081 4 311 9 338

Symbol

DD_ALL

(SRAM2)

(4)

DD_ALL

(wakeup from

Standby)

Parameter

Supply current to be added in

Standby mode when SRAM2 is retained

Supply current during wakeup from Standby mode

See

(5)

Table 36. Current consumption in Standby mode (continued)

Conditions

MSI = 4 MHz.

Wakeup clock is

TYP MAX

(1)

25 °C 55 °C 85 °C 105 °C 125 °C 25 °C

1.8 V 173

2.4 V 174

3 V

349

345

1 009

1 015

2 158

2 163

4 542

4 535

249

271

178 350 1 019 2 148 4 419 277

3.6 V 184 352 1 033 2 208 4 610 293

55 °C

527

589

594

611

85 °C 105 °C 125 °C

1604 3402 6908

1623 3438 6924

1628

1631

3467

3480

6935

6948

Unit nA

3 V 1.23

1. Guaranteed by characterization results, unless otherwise specified.

2. Guaranteed by test in production.

3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.

4. The supply current in Standby with SRAM2 mode is: I

+ RTC) + I

DD_ALL

(SRAM2).

DD_ALL

(Standby) + I

DD_ALL

(SRAM2). The supply current in Standby with RTC with SRAM2 mode is: I

DD_ALL

(Standby

5. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 39: Low-power mode wakeup timings .

Symbol

DD_ALL

(Shutdown)

Parameter

Supply current in Shutdown mode

(backup registers retained) RTC disabled

Table 37. Current consumption in Shutdown mode

Conditions TYP MAX

(1)

25 °C 55 °C 85 °C

1.8 V 7.82

190

2.4 V 23 229

3 V 44.3

290

386

485

634

105 °C 125 °C 25 °C

1 286

1 517

1 878

3 854

4 431

5 310

25.0

34.9

70.1

55 °C

255

270

345

85 °C 105 °C 125 °C

1721

2085

2454

5052

5878

6755

15543

17639

19984

Unit nA

3.6 V 212 397 977 2 516 6 656 119.1

496 2992 7939 22860

Symbol

DD_ALL

(Shutdown with RTC)

Parameter

Supply current in Shutdown mode

(backup registers retained) RTC enabled

Table 37. Current consumption in Shutdown mode (continued)

Conditions

RTC clocked by LSE bypassed at 32768 Hz

RTC clocked by LSE quartz

(2)

in low drive mode

TYP MAX

(1)

25 °C 55 °C 85 °C

1.8 V 63 133

2.4 V 165 253

522

710

105 °C 125 °C 25 °C

1 490

1 830

4 270

4 980

55 °C

85 °C 105 °C 125 °C

3 V 316 423 990 2 340 6 050

3.6 V 649 787 1 530 3 220 7 710

1.8 V 203 293

2.4 V 303 411

700

880

1 675

2 001

3 V 448 567 1 136 2 479

3.6 V 744 887 1 609 3 256 -

Unit nA

DD_ALL

(wakeup from

Shutdown)

Supply current during wakeup from Shutdown mode

Wakeup clock is

MSI = 4 MHz.

See

(3)

3 V 0.780

1. Guaranteed by characterization results, unless otherwise specified.

2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.

3. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 39: Low-power mode wakeup timings .

STM32L442KC Electrical characteristics

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in

Table 57: I/O static characteristics

For the output pins, any external pull-down or external load must also be considered to estimate the current consumption.

Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs.

Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode.

I/O dynamic current consumption

In addition to the internal peripheral current consumption measured previously (see

Table 38: Peripheral current consumption ), the I/Os used by an application also contribute

to the current consumption. When an I/O pin switches, it uses the current from the I/O supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load

(internal or external) connected to the pin:

= V

DDIOx

×

C where

is the current sunk by a switching I/O to charge/discharge the capacitive load

DDIOx

is the I/O supply voltage f

is the I/O switching frequency

C is the total capacitance seen by the I/O pin: C = C

INT

+ C

EXT

+ C

is the PCB board capacitance including the pad pin.

The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency.

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Electrical characteristics STM32L442KC

AHB

APB1

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in

Table 38 . The MCU is placed

under the following conditions:

• All I/O pins are in Analog mode

• The given value is calculated by measuring the difference of the current consumptions:

– when the peripheral is clocked on

– when the peripheral is clocked off

•

Ambient operating temperature and supply voltage conditions summarized in Table 18:

Voltage characteristics

• The power consumption of the digital part of the on-chip peripherals is given in

Table 38 . The power consumption of the analog part of the peripherals (where

applicable) is indicated in each related section of the datasheet.

Table 38. Peripheral current consumption

Range 1 Range 2 Peripheral

Bus Matrix

(1)

ADC independent clock domain

ADC clock domain

AES

CRC

DMA1

DMA2

FLASH

GPIOA (2)

GPIOB

(2)

)

GPIOC

(2)

GPIOH

(2)

QSPI

RNG independent clock domain

RNG clock domain

SRAM1

SRAM2

TSC

All AHB Peripherals

AHB to APB1 bridge

(3)

CAN1

DAC1

RTCA

6.2

1.7

1.6

1.7

0.6

7.0

3.2

0.4

2.1

1.7

0.4

1.4

1.5

2.2

0.5

0.8

1.0

1.6

21.7

0.9

4.1

2.4

1.7

5.2

1.4

1.3

1.5

0.6

5.8

2.9

0.1

1.9

1.5

0.2

1.3

N/A

0.9

0.8

1.3

18.5

0.7

3.2

1.8

1.1

Low-power run and sleep

5.8

1.6

0.5

7.3

3.1

0.2

1.9

1.6

0.3

1.4

N/A

0.7

0.8

1.3

20.3

0.9

3.9

2.2

2.1

Unit

µA/MHz

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APB1

APB2

Electrical characteristics

Table 38. Peripheral current consumption (continued)

Peripheral Range 1 Range 2

Low-power run and sleep

0.3

0.6

CRS

USB FS independent clock domain

USB FS clock domain

I2C1 independent clock domain

I2C1 clock domain

I2C3 independent clock domain

I2C3 clock domain

LPUART1 independent clock domain

LPUART1 clock domain

LPTIM1 independent clock domain

LPTIM1 clock domain

LPTIM2 independent clock domain

LPTIM2 clock domain

OPAMP

PWR

SPI3

SWPMI1 independent clock domain

SWPMI1 clock domain

TIM2

TIM6

TIM7

USART2 independent clock domain

USART2 clock domain

WWDG

All APB1 on

AHB to APB2

(4)

SAI1 independent clock domain

SAI1 clock domain

SPI1

2.9

2.3

3.5

1.1

2.9

0.9

1.9

0.6

2.9

0.8

3.1

0.8

0.4

1.7

1.9

0.9

6.2

1.0

4.1

0.2

2.3

2.1

1.8

1.3

0.5

40.2

1.0

N/A

1.6

0.6

2.4

0.4

2.7

0.7

0.2

0.1

1.3

1.6

3.6

0.2

1.8

1.6

0.9

0.5

26.7

0.9

N/A

2.8

0.9

2.3

0.4

0.7

5.0

0.6

N/A

0.2

1.9

2.0

1.7

1.1

0.5

37.9

0.9

0.8

5.9

0.9

0.6

0.8

0.4

1.6

N/A

3.4

1.0

2.5

0.8

1.8

0.6

2.8

0.7

3.9

1.9

3.8

Unit

µA/MHz

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149

Electrical characteristics STM32L442KC

Table 38. Peripheral current consumption (continued)

Peripheral Range 1 Range 2

Low-power run and sleep

Unit

APB2

SYSCFG/COMP

TIM1

TIM15

TIM16

USART1 independent clock domain

USART1 clock domain

All APB2 on

ALL

0.6

8.1

3.7

2.7

4.8

1.5

24.2

86.1

0.5

6.5

3.0

2.1

4.2

1.3

19.9

65.1

0.6

7.6

3.4

2.6

4.6

1.7

22.6

80.9

µA/MHz

1. The BusMatrix is automatically active when at least one master is ON (CPU, DMA).

2. The GPIOx (x= A…H) dynamic current consumption is approximately divided by a factor two versus this table values when the GPIO port is locked thanks to LCKK and LCKy bits in the GPIOx_LCKR register. In order to save the full GPIOx current consumption, the GPIOx clock should be disabled in the RCC when all port I/Os are used in alternate function or analog mode (clock is only required to read or write into GPIO registers, and is not used in AF or analog modes).

3. The AHB to APB1 Bridge is automatically active when at least one peripheral is ON on the APB1.

4. The AHB to APB2 Bridge is automatically active when at least one peripheral is ON on the APB2.

6.3.6

Symbol

Wakeup time from low-power modes and voltage scaling transition times

The wakeup times given in

Table 39 are the latency between the event and the execution of

the first user instruction.

The device goes in low-power mode after the WFE (Wait For Event) instruction.

Table 39. Low-power mode wakeup timings

(1)

Parameter Conditions Typ Max Unit t

WUSLEEP

Wakeup time from Sleep mode to Run mode

WULPSLEEP

Wakeup time from Lowpower sleep mode to Lowpower run mode

Wakeup in Flash with Flash in power-down during low-power sleep mode (SLEEP_PD=1 in

FLASH_ACR) and with clock MSI = 2 MHz

8.3

Nb of

CPU cycles

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STM32L442KC Electrical characteristics

Symbol t

WUSTOP0 t

WUSTOP1

Table 39. Low-power mode wakeup timings (1) (continued)

Parameter

Range 1

Wake up time from Stop 0 mode to Run mode in

Flash

Range 2

Range 1

Wake up time from Stop 0 mode to Run mode in

SRAM1

Range 2

Wake up time from Stop 1 mode to Run in Flash

Range 1

Range 2

Range 1

Wake up time from Stop 1 mode to Run mode in

SRAM1

Range 2

Conditions Typ Max Unit

Wakeup clock MSI = 48 MHz 3.8

5.7

Wakeup clock HSI16 = 16 MHz 4.1

6.9

Wakeup clock MSI = 24 MHz 4.07

6.2

Wakeup clock HSI16 = 16 MHz 4.1

6.8

Wakeup clock MSI = 4 MHz

Wakeup clock MSI = 48 MHz

8.45

11.8

1.5

2.9

Wakeup clock HSI16 = 16 MHz 2.4

2.76

Wakeup clock MSI = 24 MHz 2.4

3.48

Wakeup clock HSI16 = 16 MHz 2.4

2.76

Wakeup clock MSI = 4 MHz 8.16 10.94

Wakeup clock MSI = 48 MHz 6.34

7.86

Wakeup clock HSI16 = 16 MHz 6.84

8.23

Wakeup clock MSI = 24 MHz 6.74

8.1

Wakeup clock HSI16 = 16 MHz 6.89

8.21

Wakeup clock MSI = 4 MHz 10.47 12.1

Wakeup clock MSI = 48 MHz 4.7

5.97

Wakeup clock HSI16 = 16 MHz 5.9

6.92

Wakeup clock MSI = 24 MHz 5.4

6.51

Wakeup clock HSI16 = 16 MHz 5.9

6.92

Wakeup clock MSI = 4 MHz 11.1

12.2

µs

Wake up time from Stop 1 mode to Low-power run mode in Flash

Wake up time from Stop 1 mode to Low-power run mode in SRAM1

Regulator in low-power mode (LPR=1 in PWR_CR1)

Wakeup clock MSI = 2 MHz

16.4 17.73

17.3 18.82

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Electrical characteristics STM32L442KC

Symbol t

WUSTOP2 t

WUSTBY

Table 39. Low-power mode wakeup timings (1) (continued)

Parameter

Range 1

Wake up time from Stop 2 mode to Run mode in

Flash

Range 2

Range 1

Wake up time from Stop 2 mode to Run mode in

SRAM1

Range 2

Wakeup time from Standby mode to Run mode

Range 1 t

WUSTBY

SRAM2

Wakeup time from Standby with SRAM2 to Run mode t

WUSHDN

Wakeup time from

Shutdown mode to Run mode

1. Guaranteed by characterization results.

Range 1

Conditions

Wakeup clock MSI = 48 MHz 8.02

9.24

Wakeup clock HSI16 = 16 MHz 7.66

8.95

Wakeup clock MSI = 24 MHz 8.5

9.54

Wakeup clock HSI16 = 16 MHz 7.75

8.95

Wakeup clock MSI = 4 MHz

Wakeup clock MSI = 48 MHz

12.06 13.16

5.45

6.79

Wakeup clock HSI16 = 16 MHz 6.9

7.98

Wakeup clock MSI = 24 MHz 6.3

7.36

Wakeup clock HSI16 = 16 MHz 6.9

7.9

Wakeup clock MSI = 4 MHz 13.1 13.31

Wakeup clock MSI = 8 MHz

Wakeup clock MSI = 4 MHz

12.2 18.35

19.14 25.8

Wakeup clock MSI = 8 MHz

Wakeup clock MSI = 4 MHz

12.1

18.3

19.2 25.87

Wakeup clock MSI = 4 MHz

Typ Max Unit

µs

261.5 315.7

µs

Symbol

Table 40. Regulator modes transition times (1)

Parameter Conditions t

WULPRUN t

VOST

Wakeup time from Low-power run mode to

Run mode

(2)

Code run with MSI 2 MHz

Regulator transition time from Range 2 to

Range 1 or Range 1 to Range 2 (3)

Code run with MSI 24 MHz

1. Guaranteed by characterization results.

2. Time until REGLPF flag is cleared in PWR_SR2.

3. Time until VOSF flag is cleared in PWR_SR2.

Symbol

Table 41. Wakeup time using USART/LPUART

(1)

Parameter t t

WUUSART

WULPUART

Wakeup time needed to calculate the maximum USART/LPUART baudrate allowing to wakeup up from stop mode when USART/LPUART clock source is

HSI16

1. Guaranteed by design.

Conditions

Stop 0 mode

Stop 1 mode and Stop 2 mode

Typ

Max

1.7

8.5

Unit

µs

Unit

µs

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STM32L442KC Electrical characteristics

High-speed external user clock generated from an external source

In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in Section 6.3.14

. However,

Symbol f

HSE_ext

User external clock source frequency

HSEH

HSEL

Table 42. High-speed external user clock characteristics (1)

Parameter Conditions Min Typ

CK_IN input pin high level voltage

CK_IN input pin low level voltage t w(HSEH) t w(HSEL)

CK_IN high or low time

Voltage scaling

Range 1

Voltage scaling

Range 2

Voltage scaling

Range 1

Voltage scaling

Range 2

0.7 V

DDIOx

1. Guaranteed by design.

Max

DDIOx

0.3 V

DDIOx

Unit

MHz

V ns

Figure 12. High-speed external clock source AC timing diagram tw(HSEH)

VHSEH

VHSEL

90%

10% tr(HSE)

THSE tf(HSE) tw(HSEL) t

MS19214V2

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Electrical characteristics STM32L442KC

Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in Section 6.3.14

. However,

Symbol

Table 43. Low-speed external user clock characteristics (1)

Parameter f

LSE_ext

LSEH

LSEL t w(LSEH) t w(LSEL)

User external clock source frequency

OSC32_IN input pin high level voltage

OSC32_IN input pin low level voltage

OSC32_IN high or low time

1. Guaranteed by design.

Conditions

Min

0.7 V

DDIOx

250

Typ

32.768

Max

1000

DDIOx

0.3 V

DDIOx

Unit kHz

V ns

Figure 13. Low-speed external clock source AC timing diagram tw(LSEH)

VLSEH

VLSEL

90%

10% tr(LSE) tw(LSEL) t

TLSE tf(LSE)

MS19215V2

Low-speed external clock generated from a crystal resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in

Table 44 . In the application, the

resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

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DS11450 Rev 4

STM32L442KC Electrical characteristics

Symbol

Table 44. LSE oscillator characteristics (f

LSE

= 32.768 kHz) (1)

Parameter Conditions

(2)

Min Typ Max Unit

DD(LSE)

LSE current consumption

LSEDRV[1:0] = 00

Low drive capability

LSEDRV[1:0] = 01

Medium low drive capability

LSEDRV[1:0] = 10

Medium high drive capability

LSEDRV[1:0] = 11

High drive capability

250

315

500

630 -

LSEDRV[1:0] = 00

Low drive capability

LSEDRV[1:0] = 01

Medium low drive capability

0.5

0.75

Gm critmax

Maximum critical crystal gm

1.7

µA/V

LSEDRV[1:0] = 10

Medium high drive capability

LSEDRV[1:0] = 11

High drive capability

2.7

SU(LSE)

(3)

Startup time V

is stabilized 2 -

1. Guaranteed by design.

2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for

ST microcontrollers”.

3. t

SU(LSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer s

Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com

Figure 14. Typical application with a 32.768 kHz crystal

Resonator with integrated capacitors

OSC32_IN f

LSE

32.768 kHz resonator

Drive programmable amplifier

OSC32_OUT

Note:

MS30253V2

An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one.

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Electrical characteristics STM32L442KC

6.3.8 Internal clock source characteristics

The parameters given in

Table 45 are derived from tests performed under ambient

temperature and supply voltage conditions summarized in Table 21: General operating conditions

. The provided curves are characterization results, not tested in production.

High-speed internal (HSI16) RC oscillator

Symbol

Table 45. HSI16 oscillator characteristics (1)

Parameter Conditions

DuCy(HSI16)

(2)

∆

∆ t

Temp

VDD su t stab

DD f

HSI16

TRIM

(HSI16)

(2)

HSI16 Frequency

HSI16 user trimming step

=3.0 V, T

=30 °C

Trimming code is not a multiple of 64

Trimming code is a multiple of 64

Duty Cycle

HSI16 oscillator frequency drift over temperature

= 0 to 85 °C

= -40 to 125 °C

HSI16 oscillator frequency drift over V

HSI16 oscillator start-up time

=1.62 V to 3.6 V

HSI16 oscillator stabilization time

HSI16 oscillator power consumption

1. Guaranteed by characterization results.

2. Guaranteed by design.

Min

15.88

0.2

-4

-1

-2

-0.1

Typ

0.3

-6

0.8

155

Max Unit

16.08

MHz

0.4

-8

1.5

0.05

1.2

190

μ s

μ A

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MHz

16.4

16.3

16.2

16.1

15.9

15.8

15.7

15.6

-40 -20

Electrical characteristics

Figure 15. HSI16 frequency versus temperature

+2%

+1.5%

+1%

0 min

-1%

-1.5%

-2%

40 mean

60 80 max

100 120 °C

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Electrical characteristics STM32L442KC

Symbol f

MSI

Multi-speed internal (MSI) RC oscillator

∆

TEMP

(MSI) (2)

Parameter

Table 46. MSI oscillator characteristics

(1)

Conditions

MSI frequency after factory calibration, done at V

=3 V and

=30 °C

MSI oscillator frequency drift over temperature

MSI mode

PLL mode

XTAL=

32.768 kHz

MSI mode

Range 0

Range 1

Range 2

Range 3

Range 4

Range 5

Range 6

Range 7

Range 8

Range 9

Range 10

Range 11

Range 0

Range 1

Range 2

Range 3

Range 4

Range 5

Range 6

Range 7

Range 8

Range 9

Range 10

Range 11

= -0 to 85 °C

= -40 to 125 °C

Min

98.7

197.4

394.8

789.6

0.987

1.974

3.948

7.896

15.79

23.69

31.58

47.38

-3.5

-8

Max Unit

24.31

32.42

48.62

101.3

202.6

405.2

810.4

kHz

1.013

2.026

4.052

8.104

MHz

16.21

kHz

MHz

Typ

98.304

196.608

393.216

786.432

1.016

1.999

100

200

400

800

3.998

7.995

15.991

23.986

32.014

48.005

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STM32L442KC Electrical characteristics

Symbol

VDD

(MSI)

P_USB

(2)

(6)

MT_USB

(6)

CC jitter(MSI)

(6)

P jitter(MSI) t

∆

∆ t

(MSI)

Jitter(MSI)

(MSI)

STAB

(6)

(MSI)

(6)

Table 46. MSI oscillator characteristics (1) (continued)

Parameter Conditions Min

MSI oscillator frequency drift over V

(reference is 3 V)

MSI mode

Range 0 to 3

Range 4 to 7

=1.62 V to 3.6 V

=2.4 V to 3.6 V

=1.62 V to 3.6 V

=2.4 V to 3.6 V

Range 8 to 11

=1.62 V to 3.6 V

=2.4 V to 3.6 V

= -40 to 85 °C Frequency variation in sampling mode

(3)

MSI mode

= -40 to 125 °C

Period jitter for

USB clock

(4)

Medium term jitter for USB clock

MSI oscillator

(5) stabilization time

PLL mode

Range 11

PLL mode

Range 11

PLL mode

Range 11

RMS cycle-tocycle jitter

PLL mode Range 11

RMS Period jitter PLL mode Range 11

MSI oscillator start-up time

Range 0

Range 1

Range 2

Range 3

Range 4 to 7

Range 8 to 11 for next transition for paired transition for next transition for paired transition

10 % of final frequency

5 % of final frequency

1 % of final frequency

-1.2

-0.5

-2.5

-0.8

-5

-1.6

Max Unit

0.5

0.7

3.458

3.916

1 ns

0.5

ps ps us

1.25

2.5

Typ

2.5

0.25

0.5

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149

Electrical characteristics STM32L442KC

Symbol

Table 46. MSI oscillator characteristics (1) (continued)

Parameter Conditions Min Typ Max Unit

(MSI)

(6)

MSI oscillator power consumption

MSI and

PLL mode

Range 0

Range 1

Range 2

Range 3

Range 4

Range 5

Range 6

Range 7

Range 8

Range 9

Range 10

Range 11

0.6

0.8

1.2

1.9

4.7

6.5

18.5

110

155

µA

1. Guaranteed by characterization results.

2. This is a deviation for an individual part once the initial frequency has been measured.

3. Sampling mode means Low-power run/Low-power sleep modes with Temperature sensor disable.

4. Average period of MSI @48 MHz is compared to a real 48 MHz clock over 28 cycles. It includes frequency tolerance + jitter of MSI @48 MHz clock.

5. Only accumulated jitter of MSI @48 MHz is extracted over 28 cycles.

For next transition: min. and max. jitter of 2 consecutive frame of 28 cycles of the MSI @48 MHz, for 1000 captures over 28 cycles.

For paired transitions: min. and max. jitter of 2 consecutive frame of 56 cycles of the MSI @48 MHz, for 1000 captures over

56 cycles.

6. Guaranteed by design.

2.5

1.2

1.7

110

130

190

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Figure 16. Typical current consumption versus MSI frequency

High-speed internal 48 MHz (HSI48) RC oscillator

Symbol

Table 47. HSI48 oscillator characteristics

(1)

Parameter Conditions f

HSI48

TRIM

HSI48 Frequency

HSI48 user trimming step

USER TRIM

COVERAGE

HSI48 user trimming coverage

DuCy(HSI48) Duty Cycle

ACC

HSI48_REL

Accuracy of the HSI48 oscillator over temperature (factory calibrated)

VDD

(HSI48)

HSI48 oscillator frequency drift with V

I t su

(HSI48) HSI48 oscillator start-up time

(HSI48)

HSI48 oscillator power consumption

=3.0V, T

±32 steps

=30°C

= 3.0 V to 3.6 V,

= –15 to 85 °C

= 1.65 V to 3.6 V,

= –40 to 125 °C

= 3 V to 3.6 V

= 1.65 V to 3.6 V

Min

±3

(3)

(2)

Typ

0.11

(2)

±3.5

(3)

0.025

(3)

0.05

(3)

2.5

(2)

340

(2)

±4.5

(3)

0.05

(3)

0.1

(3)

(2)

380

(2)

Max Unit

0.18

(2)

MHz

(2)

±3

(3)

μ s

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149

Electrical characteristics

Symbol

Table 47. HSI48 oscillator characteristics (1) (continued)

Parameter Conditions Min

jitter

Next transition jitter

Accumulated jitter on 28 cycles (4)

Paired transition jitter

Accumulated jitter on 56 cycles

(4)

1. V

= 3 V, T

= –40 to 125°C unless otherwise specified.

2. Guaranteed by design.

3. Guaranteed by characterization results.

4. Jitter measurement are performed without clock source activated in parallel.

Typ

+/-0.15

(2)

+/-0.25

(2)

STM32L442KC

Max Unit

Figure 17. HSI48 frequency versus temperature

-2

-4

-6

-50 -30 -10

Avg

10 30 min

50 70 90 max

110 130

°C

MSv40989V1

Low-speed internal (LSI) RC oscillator

Symbol Parameter

Table 48. LSI oscillator characteristics (1)

Conditions Min f

LSI

LSI Frequency

= 3.0 V, T

= 30 °C

= 1.62 to 3.6 V, T

= -40 to 125 °C t t

STAB

(LSI)

(2)

LSI oscillator startup time

LSI oscillator stabilization time

LSI oscillator power consumption

1. Guaranteed by characterization results.

2. Guaranteed by design.

5% of final frequency

31.04

29.5

Typ

125

110

Max Unit

32.96

34 kHz

130 μ s

180 μ s

180 nA

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DS11450 Rev 4

STM32L442KC Electrical characteristics

The parameters given in

Table 49 are derived from tests performed under temperature and

supply voltage conditions summarized in

Table 21: General operating conditions .

Symbol f

PLL_IN f

PLL_P_OUT

PLL multiplier output clock P f

PLL_Q_OUT

PLL multiplier output clock Q f

PLL_R_OUT

PLL multiplier output clock R f

VCO_OUT t

LOCK

Jitter

(PLL)

Table 49. PLL, PLLSAI1 characteristics

(1)

Parameter

PLL input clock

(2)

Conditions

PLL input clock duty cycle

PLL VCO output

PLL lock time

RMS cycle-to-cycle jitter

RMS period jitter

PLL power consumption on

(1)

Voltage scaling Range 1

Voltage scaling Range 2

Voltage scaling Range 1

Voltage scaling Range 2

Voltage scaling Range 1

Voltage scaling Range 2

Voltage scaling Range 1

Voltage scaling Range 2

System clock 80 MHz

VCO freq = 96 MHz

VCO freq = 192 MHz

VCO freq = 344 MHz

Min

3.0968

Typ Max Unit

40 -

30 -

200 260

300 380

520 650

16 MHz

MHz

344

MHz

128

40 μ s

±ps

μ A

1. Guaranteed by design.

2. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared between the 2 PLLs.

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Electrical characteristics STM32L442KC t t

Symbol t prog prog_row prog_page

Table 50. Flash memory characteristics (1)

Parameter

64-bit programming time one row (32 double word) programming time one page (2 Kbyte) programming time t

ERASE

Page (2 KB) erase time t prog_bank t

ME one bank (512 Kbyte) programming time

Mass erase time

(one or two banks)

Conditions

normal programming fast programming normal programming fast programming

normal programming fast programming

Average consumption from V

Maximum current (peak)

Write mode

Erase mode

Write mode

Erase mode

Typ

22.13

3.4

7 (for 2 μ s)

7 (for 41 μ s)

81.69

2.61

1.91

20.91

15.29

22.02

5.35

3.91

1. Guaranteed by design.

Symbol

Table 51. Flash memory endurance and data retention

Parameter Conditions

N t

END

RET

Endurance

Data retention

= –40 to +105 °C

1 kcycle

(2)

at T

= 85 °C

1 kcycle (2) at T

= 105 °C

1 kcycle

(2)

at T

= 125 °C

10 kcycles

(2)

at T

= 55 °C

10 kcycles

(2)

at T

= 85 °C

10 kcycles (2) at T

= 105 °C

1. Guaranteed by characterization results.

2. Cycling performed over the whole temperature range.

Min

(1)

Unit kcycles

Years

Max Unit

90.76

µs

2.90

2.12

23.24

16.98

24.47

5.95

4.35

24.59

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Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

• FTB : A Burst of Fast Transient voltage (positive and negative) is applied to V

through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard.

and

A device reset allows normal operations to be resumed.

The test results are given in Table 52

. They are based on the EMS levels and classes defined in application note AN1709.

Symbol

Table 52. EMS characteristics

Parameter Conditions

Level/

Class

FESD

EFTB

Voltage limits to be applied on any I/O pin to induce a functional disturbance

Fast transient voltage burst limits to be applied through 100 pF on V

and V pins to induce a functional disturbance

SS f

= 3.3 V, T

HCLK

= +25 °C,

= 80 MHz, conforming to IEC 61000-4-2 f

= 3.3 V, T

HCLK

= +25 °C,

= 80 MHz, conforming to IEC 61000-4-4

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

• Corrupted program counter

• Unexpected reset

• Critical Data corruption (control registers...)

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Electrical characteristics STM32L442KC

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with

IEC 61967-2 standard which specifies the test board and the pin loading.

Table 53. EMI characteristics

Symbol Parameter

EMI

Conditions

Monitored frequency band

Peak level

0.1 MHz to 30 MHz

= 3.6 V, T

= 25 °C,

UFQFPN32 package compliant with IEC

61967-2

30 MHz to 130 MHz

130 MHz to 1 GHz

1 GHz to 2 GHz

EMI Level

Max vs.

HSE

HCLK

]

8 MHz/ 80 MHz

-1

Unit dBµV

106/157

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the ANSI/JEDEC standard.

Symbol

Table 54. ESD absolute maximum ratings

Ratings Conditions Class

Maximum value (1)

Unit

ESD(HBM)

Electrostatic discharge voltage (human body model)

ESD(CDM)

Electrostatic discharge voltage (charge device model)

= +25 °C, conforming to ANSI/ESDA/JEDEC

JS-001

= +25 °C, conforming to ANSI/ESD

STM5.3.1

1. Guaranteed by characterization results.

2000

250

DS11450 Rev 4

STM32L442KC Electrical characteristics

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up performance:

• A supply overvoltage is applied to each power supply pin.

• A current injection is applied to each input, output and configurable I/O pin.

These tests are compliant with EIA/JESD 78A IC latch-up standard.

Symbol

Parameter

Table 55. Electrical sensitivities

Conditions

Static latch-up class T

= +105 °C conforming to JESD78A

Class

As a general rule, current injection to the I/O pins, due to external voltage below V

SS above V

DDIOx product operation. However, in order to give an indication of the robustness of the

(for standard, 3.3 V-capable I/O pins) should be avoided during normal microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of the -5 µA/+0 µA range) or other functional failure (for example reset occurrence or oscillator frequency deviation).

The characterization results are given in

Table 56 .

Negative induced leakage current is caused by negative injection and positive induced leakage current is caused by positive injection.

Symbol

INJ

Table 56. I/O current injection susceptibility (1)

Functional susceptibility

Description

Negative injection

Positive injection

Injected current on all pins except PA4, PA5

Injected current on PA4, PA5 pins

-5

N/A

(2)

1. Guaranteed by characterization results.

2. Injection is not possible.

Unit mA

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Electrical characteristics STM32L442KC

General input/output characteristics

Unless otherwise specified, the parameters given in

Table 57 are derived from tests

performed under the conditions summarized in Table 21: General operating conditions

. All

I/Os are designed as CMOS- and TTL-compliant.

Symbol

(1)

V hys

(3)

I lkg

(4)

Parameter

Table 57. I/O static characteristics

Conditions Min

I/O input low level voltage

I/O input high level voltage

1.62 V<V

1.08 V<V

1.62 V<V

DDIOx

<3.6 V

<1.62 V

<3.6 V 0.7xV

DDIOx

(2)

I/O input high level voltage

1.62 V<V

DDIOx

<3.6 V 0.49xV

DDIOX

+0.26

(3)

I/O input high level voltage

TT_xx, FT_xxx and

NRST I/O input hysteresis

1.08 V<V

1.62 V<V

FT_xx input leakage current

(3)(5)

FT_u and PC3 I/Os

TT_xx input leakage current

≤

Max(V

DDXXX

)

(6)(7)

Max(V

DDXXX

Max(V

DDXXX

) ≤ V

)+1 V

≤

Max(V

≤ 5.5 V

)+1 V <

≤

Max(V

DDXXX

)

(6)(7)

Max(V

DDXXX

Max(V

DDXXX

) ≤ V

)+1 V

≤

Max(V

≤ 5.5 V

)+1 V <

≤ Max(V

DDXXX

)

(6)

Max(V

3.6 V

) ≤ V

Weak pull-up equivalent resistor

(8)

= V

DDIOx

<1.62 V 0.61xV

DDIOX

<3.6 V

+0.05

(3)

Weak pull-down equivalent resistor (8)

I/O pin capacitance

= V

DDIOx

Typ

200

0.3xV

0.39xV

0.43xV

Max

DDIOx

(2)

DDIOx

±100

650

200

±150

2500

250

(3)

±150

2000

-0.06

(3)

-0.1

(3)

Unit

V mV nA k Ω k Ω pF

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STM32L442KC Electrical characteristics

1. Refer to Figure 18: I/O input characteristics .

2. Tested in production.

3. Guaranteed by design.

4. This value represents the pad leakage of the IO itself. The total product pad leakage is provided by this formula:

Total_Ileak_max

= 10 µA + [number of IOs where V

is applied on the pad] ₓ I lkg

(Max).

5. All FT_xx GPIOs except FT_u and PC3 I/Os.

6. Max(V

DDXXX

) is the maximum value of all the I/O supplies.

7. To sustain a voltage higher than Min(V disabled.

, V

DDA

, V

DDUSB

) +0.3 V, the internal Pull-up and Pull-Down resistors must be

8. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

PMOS/NMOS contribution to the series resistance is minimal (~10% order).

All I/Os are CMOS- and TTL-compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The

coverage of these requirements is shown in Figure 18

for standard I/Os, and in

Figure 18

for

5 V tolerant I/Os.

Figure 18. I/O input characteristics

TTL requirement Vih min = 2V

min = 0

.7xV

DDIO x

DDIOx

+0.2

6 for V

DDIOx

>1.6

DDIOx

<1.62 or

0.49xV

Teste d in production CMOS requirement Vih on Vi h min = 0.

lation V il max

61xV

DDIOx

=0.43xV

DDIOx

+0.05

for 1.08<V

-0.1 for 1.08

<V DDIOx

<1.62 or 0.39xV

ax = 0.3xVdd

DDIOx

-0.06 for

DDIO x

>1.62

TTL requirement Vil max = 0.8V

Based on simu

Tested in produ ction CMOS

requirement Vil m

MSv37613V1

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source up to ± 20 mA (with a relaxed V

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Electrical characteristics STM32L442KC

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in

Section 6.2

• The sum of the currents sourced by all the I/Os on V

DDIOx, consumption of the MCU sourced on V

DD,

Σ I

VDD

(see Table 18: Voltage characteristics ).

plus the maximum cannot exceed the absolute maximum rating

• The sum of the currents sunk by all the I/Os on V

, plus the maximum consumption of the MCU sunk on V

, cannot exceed the absolute maximum rating

Table 18: Voltage characteristics

Σ I

VSS

(see

Output voltage levels

Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in

Table 21: General operating conditions . All I/Os are CMOS- and TTL-compliant (FT OR TT

unless otherwise specified).

Symbol

Table 58. Output voltage characteristics (1)

Parameter Conditions Min Max Unit

(3)

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

CMOS port

DDIOx

(2)

= 8 mA

≥ 2.7 V

Output low level voltage for an I/O pin TTL port

Output high level voltage for an I/O pin

DDIOx

(2)

= 8 mA

≥ 2.7 V

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

DDIOx

= 20 mA

≥ 2.7 V

= 4 mA

≥ 1.62 V

= 2 mA

1.62 V ≥ V

DDIOx

≥ 1.08 V

DDIOx

2.4

DDIOx

-0.4

-1.3

-0.45

0.65

ₓ V

DDIOx

0.35

0.4

0.45

ₓ

1.3

DDIOx

Output low level voltage for an FT I/O pin in FM+ mode (FT I/O with "f" option)

| = 20 mA

DDIOx

≥ 2.7 V

| = 10 mA

DDIOx

≥ 1.62 V

| = 2 mA

1.62 V ≥ V

DDIOx

≥ 1.08 V

0.4

1. The I

current sourced or sunk by the device must always respect the absolute maximum rating specified in

Table 18:

Voltage characteristics

, and the sum of respect the absolute maximum ratings the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always

Σ I

2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

3. Guaranteed by design.

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in

Figure 19

and

Table 59 , respectively.

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STM32L442KC Electrical characteristics

Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in

Table 21: General operating conditions

Speed Symbol

Table 59. I/O AC characteristics (1)(2)

Parameter Conditions

Fmax Maximum frequency

Tr/Tf Output rise and fall time

Fmax Maximum frequency

Tr/Tf Output rise and fall time

C=50 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=50 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=50 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

C=10 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=10 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=10 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

C=50 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=50 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=50 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

C=10 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=10 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=10 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

C=50 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=50 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=50 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

C=10 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=10 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=10 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

C=50 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=50 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=50 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

C=10 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=10 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=10 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

Unit

MHz ns

Min

Max

1.5

0.1

140

0.1

110

4.5

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149

Electrical characteristics STM32L442KC

Speed Symbol

Table 59. I/O AC characteristics (1)(2) (continued)

Parameter Conditions Min Max Unit

Fmax

Tr/Tf

Fmax

Tr/Tf

Maximum frequency

Output rise and fall time

Maximum frequency

Output rise and fall time

C=50 pF, 2.7 V ≤ V

C=10 pF, 2.7 V ≤ V

C=50 pF, 2.7 V ≤ V

C=10 pF, 2.7 V ≤ V

C=30 pF, 2.7 V ≤ V

C=10 pF, 2.7 V ≤ V

C=30 pF, 2.7 V ≤ V

C=30 pF, 1.08 V ≤

DDIOx

C=50 pF, 1.62 V ≤ V

C=50 pF, 1.08 V ≤ V

DDIOx

C=10 pF, 1.62 V ≤ V

C=10 pF, 1.08 V ≤ V

DDIOx

C=50 pF, 1.62 V ≤ V

C=50 pF, 1.08 V ≤ V

DDIOx

C=10 pF, 1.62 V ≤ V

C=10 pF, 1.08 V ≤ V

DDIOx

C=30 pF, 1.62 V ≤ V

C=30 pF, 1.08 V ≤ V

DDIOx

C=10 pF, 1.62 V ≤ V

C=10 pF, 1.08 V ≤ V

DDIOx

C=30 pF, 1.62 V ≤ V

≤

DDIOx

≤

DDIOx

≤

DDIOx

≤

DDIOx

≤

DDIOx

≤

DDIOx

≤

DDIOx

3.6 V

≤

3.6 V

≤

3.6 V

≤

3.6 V

≤

3.6 V

≤

3.6 V

≤

3.6 V

≤

2.7 V

1.62 V

2.7 V

1.62 V

2.7 V

1.62 V

2.7 V

1.62 V

2.7 V

1.62 V

2.7 V

1.62 V

2.7 V

1.62 V

100

(3)

37.5

5.8

2.5

3.3

MHz ns

Fm+

Fmax Maximum frequency

Tf Output fall time

(4)

C=50 pF, 1.6 V ≤ V

DDIOx

≤ 3.6 V

MHz ns

1. The I/O speed is configured using the OSPEEDRy[1:0] bits. The Fm+ mode is configured in the SYSCFG_CFGR1 register.

Refer to the RM0394 reference manual for a description of GPIO Port configuration register.

2. Guaranteed by design.

3. This value represents the I/O capability but the maximum system frequency is limited to 80 MHz.

4. The fall time is defined between 70% and 30% of the output waveform accordingly to I 2 C specification.

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Figure 19. I/O AC characteristics definition

(1)

90% 10%

50% 50%

10% 90% t r(IO)out t f(IO)out

T when loaded by the specified capacitance.

MS32132V2

1. Refer to Table 59: I/O AC characteristics .

6.3.15 NRST pin characteristics

The NRST pin input driver uses the CMOS technology. It is connected to a permanent pullup resistor, R

Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in

Table 21: General operating conditions .

Symbol Parameter

Table 60. NRST pin characteristics (1)

Conditions Min Typ Max Unit

IL(NRST)

IH(NRST)

V hys(NRST)

F(NRST)

NF(NRST)

NRST input low level voltage

NRST input high level voltage

NRST Schmitt trigger voltage hysteresis

Weak pull-up equivalent resistor

(2)

NRST input filtered pulse

NRST input not filtered pulse

= V

1.71 V ≤ V

≤ 3.6 V

0.7

ₓ V

DDIOx

350

200

0.3

ₓ V

DDIOx

1. Guaranteed by design.

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimal (~10% order)

V mV k Ω ns ns

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149

Electrical characteristics STM32L442KC

Figure 20. Recommended NRST pin protection

External reset circuit

(1)

0.1 μF

NRST

(2)

Filter

Internal reset

MS19878V3

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the V

IL(NRST)

max level specified in

Table 60: NRST pin characteristics

. Otherwise the reset will not be taken into account by the device.

3. The external capacitor on NRST must be placed as close as possible to the device.

6.3.16 Extended interrupt and event controller input (EXTI) characteristics

The pulse on the interrupt input must have a minimal length in order to guarantee that it is detected by the event controller.

Symbol

Table 61. EXTI Input Characteristics (1)

Parameter

PLEC

Pulse length to event controller

1. Guaranteed by design.

Conditions

Min

Typ

Max

Unit ns

6.3.17 Analog switches booster

Symbol

Table 62. Analog switches booster characteristics (1)

Parameter

DD t

SU(BOOST)

Supply voltage

Booster startup time

DD(BOOST)

Booster consumption for

1.62 V ≤ V

≤ 2.0 V

Booster consumption for

2.0 V ≤ V

≤ 2.7 V

Booster consumption for

2.7 V ≤ V

≤ 3 .6 V

1. Guaranteed by design.

Min

1.62

Typ

Max

3.6

240

250

500

900

Unit

µs

µA

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STM32L442KC Electrical characteristics

Note:

Symbol

DDA

REF+

REF-

V f

ADC f s f

TRIG

CMIN

AIN

(3)

AIN

ADC

Unless otherwise specified, the parameters given in Table 63

are preliminary values derived from tests performed under ambient temperature, f

PCLK frequency and V

conditions summarized in Table 21: General operating conditions

DDA

supply voltage

It is recommended to perform a calibration after each power-up.

Parameter

Table 63. ADC characteristics

(1) (2)

Conditions Min

Analog supply voltage

Positive reference voltage

DDA

≥ 2 V

DDA

< 2 V

Negative reference voltage

Range 1

ADC clock frequency

Sampling rate for FAST channels

Range 2

Resolution = 12 bits

Resolution = 10 bits

Resolution = 8 bits

Resolution = 6 bits

Resolution = 12 bits

Resolution = 10 bits

Sampling rate for SLOW channels

Resolution = 8 bits

Resolution = 6 bits

External trigger frequency f

ADC

= 80 MHz

Resolution = 12 bits

1.62

Input common mode Differential mode

0.14

Typ

DDA

SSA

Max

3.6

DDA

7.27

8.88

4.21

4.71

5.33

6.15

5.33

6.15

5.33

REF+

REF-

- 0.18

)/2

REF+

REF-

)/2

REF+

REF-

+ 0.18

)/2

Conversion voltage range(2)

External input impedance

Internal sample and hold capacitor

REF+

Unit

MHz

Msps

MHz

1/f

ADC

V k Ω pF t

STAB t

CAL

Power-up time

Calibration time

ADC

= 80 MHz

1.45

116 conversion cycle

µs

1/f

ADC

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149

Electrical characteristics STM32L442KC

Symbol

Table 63. ADC characteristics (1) (2) (continued)

Parameter Conditions Min Typ Max Unit t t t

LATR

LATRINJ t s

ADCVREG_STUP

Trigger conversion latency Regular and injected channels without conversion abort

CKMODE = 00

CKMODE = 01

CKMODE = 10

CKMODE = 11

Trigger conversion latency Injected channels aborting a regular conversion

CKMODE = 00

CKMODE = 01

CKMODE = 10

CKMODE = 11

Sampling time f

ADC

= 80 MHz

ADC voltage regulator start-up time

ADC

= 80 MHz

Resolution = 12 bits

Total conversion time

(including sampling time)

Resolution = 12 bits

1.5

2.5

0.03125

2.5

0.1875

2.5

2.0

2.25

2.125

3.5

3.0

3.25

3.125

8.00625

640.5

8.1625

1/f

ADC

µs

ADC

µs

I t

CONV

DDA

(ADC)

DDV_S

DDV_D

(ADC)

ADC consumption from the V

DDA

supply

ADC consumption from the V

REF+ mode

ADC consumption from the V mode

single ended

REF+

differential fs = 5 Msps fs = 1 Msps fs = 10 ksps fs = 5 Msps fs = 1 Msps fs = 10 ksps fs = 5 Msps fs = 1 Msps fs = 10 ksps ts + 12.5 cycles for successive approximation

= 15 to 653

730 830

160

130

0.6

260

1.3

220

160

310

1/f

ADC

µA

1. Guaranteed by design

2. The I/O analog switch voltage booster is enable when V

DDA

< 2.4V). It is disable when V

DDA

≥ 2.4 V.

DDA

< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when

REF+

can be internally connected to V

DDA

and V

Section 4: Pinouts and pin description

REF-

can be internally connected to V

for further details.

SSA

, depending on the package.

The maximum value of R

AIN

can be found in Table 64: Maximum ADC RAIN .

116/157

DS11450 Rev 4

STM32L442KC

Resolution

12 bits

10 bits

8 bits

6 bits

1. Guaranteed by design.

Electrical characteristics

Table 64. Maximum ADC R

AIN

(1)(2)

Sampling cycle

@80 MHz

Sampling time [ns]

@80 MHz

AIN

max ( Ω )

Fast channels

(3) channels

(4)

92.5

247.5

640.5

2.5

6.5

12.5

640.5

2.5

6.5

12.5

24.5

47.5

24.5

47.5

92.5

247.5

640.5

2.5

6.5

12.5

24.5

47.5

92.5

247.5

2.5

6.5

12.5

24.5

47.5

92.5

247.5

8006.75

31.25

81.25

156.25

306.25

593.75

1156.25

3093.75

8006.75

31.25

81.25

156.25

8006.75

31.25

81.25

156.25

306.25

593.75

1156.25

3093.75

31.25

81.25

156.25

306.25

593.75

1156.25

3093.75

306.25

593.75

1156.25

3093.75

8006.75

6800

15000

50000

220

560

1200

47000

180

470

1000

1800

2700

39000

120

390

820

1500

2200

5600

12000

100

330

680

1500

2200

4700

12000

2700

3900

8200

18000

50000

5600

12000

50000

N/A

330

1000

39000

N/A

270

680

1500

2200

33000

N/A

180

560

1200

1800

4700

10000

N/A

100

470

1200

1800

3900

10000

2200

3300

6800

15000

50000

DS11450 Rev 4

117/157

149

Electrical characteristics STM32L442KC

2. The I/O analog switch voltage booster is enable when V

DDA

< 2.4V). It is disable when V

DDA

≥ 2.4 V.

DDA

< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when

3. Fast channels are: PC0, PC1, PC2, PC3, PA0, PA1.

4. Slow channels are: all ADC inputs except the fast channels.

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DS11450 Rev 4

STM32L442KC Electrical characteristics

Table 65. ADC accuracy - limited test conditions 1 (1)(2)(3)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

ENOB

SINAD

SNR

Total unadjusted error

Offset error

Gain error

Effective number of bits

Signal-tonoise and distortion ratio

Signal-tonoise ratio

Single ended

Differential

Single ended

Differential

Single ended

Differential

Differential linearity error

Integral linearity error

ADC clock frequency ≤

80 MHz,

Sampling rate ≤ 5.33 Msps,

DDA

= VREF+ = 3 V,

TA = 25 °C

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

1 1.5

1 1.2

1.5

2.5

1.5

2.5

1 2

Slow channel (max speed) 1 2

Fast channel (max speed) 10.4 10.5

Slow channel (max speed) 10.4 10.5

Fast channel (max speed) 10.8 10.9

Slow channel (max speed) 10.8 10.9

Fast channel (max speed) 64.4 65 -

Slow channel (max speed) 64.4 65

Fast channel (max speed) 66.8 67.4

Slow channel (max speed) 66.8 67.4

Fast channel (max speed) 65 66

Slow channel (max speed) 65 66

Fast channel (max speed) 67 68

Slow channel (max speed) 67 68

4 5

3.5

4.5

3.5

4.5

1 2.5

1.5

2.5

1.5

2.5

4.5

2.5

4.5

2.5

3.5

2.5

3.5

1 1.5

LSB bits dB

DS11450 Rev 4

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149

Electrical characteristics STM32L442KC

Table 65. ADC accuracy - limited test conditions 1 (1)(2)(3) (continued)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

THD

Total harmonic distortion

ADC clock frequency ≤

80 MHz,

Sampling rate ≤ 5.33 Msps,

DDA

= V

REF+

= 3 V,

TA = 25 °C

Single ended

Differential

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

-74 -73

-79 -76

-79 -76 dB

1. Guaranteed by design.

2. ADC DC accuracy values are measured after internal calibration.

3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a

Schottky diode (pin to ground) to analog pins which may potentially inject negative current.

4. The I/O analog switch voltage booster is enable when V

DDA

< 2.4 V). It is disable when V

DDA

< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when

≥ 2.4 V. No oversampling.

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DS11450 Rev 4

STM32L442KC Electrical characteristics

Table 66. ADC accuracy - limited test conditions 2 (1)(2)(3)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

ENOB

SINAD

SNR

Total unadjusted error

Offset error

Gain error

Effective number of bits

Signal-tonoise and distortion ratio

Signal-tonoise ratio

Single ended

Differential

Single ended

Differential

Single ended

Differential

Differential linearity error

ADC clock frequency ≤

80 MHz,

Sampling rate ≤ 5.33 Msps,

2 V ≤ V

DDA Integral linearity error

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

1 1.5

1 1.2

1.5

3.5

1.5

3.5

1 3

Slow channel (max speed) 1 2.5

Fast channel (max speed) 10 10.5

Slow channel (max speed) 10 10.5

Fast channel (max speed) 10.7 10.9

Slow channel (max speed) 10.7 10.9

Fast channel (max speed) 62 65 -

Slow channel (max speed) 62 65

Fast channel (max speed) 66 67.4

Slow channel (max speed) 66 67.4

Fast channel (max speed) 64 66

Slow channel (max speed) 64 66

Fast channel (max speed) 66.5 68

Slow channel (max speed) 66.5 68

4 6.5

3.5

5.5

3.5

5.5

1 4.5

1 5

1.5

2.5

3.5

2.5

3.5

1 1.5

LSB bits dB

DS11450 Rev 4

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149

Electrical characteristics STM32L442KC

Table 66. ADC accuracy - limited test conditions 2 (1)(2)(3) (continued)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

THD

Total harmonic distortion

ADC clock frequency ≤

80 MHz,

Sampling rate ≤ 5.33 Msps,

2 V ≤ V

DDA

Single ended

Differential

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

-74 -65

-74 -67

-79 -70

-79 -71 dB

1. Guaranteed by design.

2. ADC DC accuracy values are measured after internal calibration.

Schottky diode (pin to ground) to analog pins which may potentially inject negative current.

4. The I/O analog switch voltage booster is enable when V

DDA

< 2.4 V). It is disable when V

DDA

< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when

≥ 2.4 V. No oversampling.

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DS11450 Rev 4

STM32L442KC Electrical characteristics

Table 67. ADC accuracy - limited test conditions 3 (1)(2)(3)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

ENOB

SINAD

SNR

Total unadjusted error

Offset error

Gain error

Effective number of bits

Signal-tonoise and distortion ratio

Signal-tonoise ratio

Single ended

Differential

Single ended

Differential

Single ended

Differential

Differential linearity error

Integral linearity error

ADC clock frequency ≤

80 MHz,

Sampling rate ≤ 5.33 Msps,

1.65 V ≤ V

DDA

3.6 V,

= V

REF+

≤

Voltage scaling Range 1

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

1.2

1.5

1 1.2

3 3.5

2.5

3.5

2 2.5

Slow channel (max speed) 2 2.5

Fast channel (max speed) 10 10.4

Slow channel (max speed) 10 10.4

Fast channel (max speed) 10.6 10.7

Slow channel (max speed) 10.6 10.7

Fast channel (max speed) 62 64 -

Slow channel (max speed) 62 64

Fast channel (max speed) 65 66

Slow channel (max speed) 65 66

Fast channel (max speed) 63 65

Slow channel (max speed) 63 65

Fast channel (max speed) 66 67

Slow channel (max speed) 66 67

5.5

7.5

4.5

6.5

4.5

7.5

4.5

5.5

2 5

2.5

2 3.5

2.5

4.5

3.5

1.2

1.5

LSB bits dB

DS11450 Rev 4

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149

Electrical characteristics STM32L442KC

Table 67. ADC accuracy - limited test conditions 3 (1)(2)(3) (continued)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

THD

Total harmonic distortion

ADC clock frequency ≤

80 MHz,

Sampling rate ≤ 5.33 Msps,

1.65 V ≤ V

DDA

3.6 V,

= V

REF+

≤

Voltage scaling Range 1

Single ended

Differential

Fast channel (max speed)

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

-69 -67

-71 -67

-72 -71

-72 -71 dB

1. Guaranteed by design.

2. ADC DC accuracy values are measured after internal calibration.

Schottky diode (pin to ground) to analog pins which may potentially inject negative current.

4. The I/O analog switch voltage booster is enable when V

DDA

< 2.4 V). It is disable when V

DDA

< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when

≥ 2.4 V. No oversampling.

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DS11450 Rev 4

STM32L442KC Electrical characteristics

Table 68. ADC accuracy - limited test conditions 4 (1)(2)(3)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

ENOB

SINAD

SNR

Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error

ADC clock frequency ≤

26 MHz,

1.65 V ≤ V

DDA

3.6 V,

= VREF+ ≤

Voltage scaling Range 2

Effective number of bits

Signal-tonoise and distortion ratio

Signal-tonoise ratio

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

1 1.5

1 1.2

2.5

2 2.5

Slow channel (max speed) 2 2.5

Fast channel (max speed) 10.2 10.5

Slow channel (max speed) 10.2 10.5

Fast channel (max speed) 10.6 10.7

Slow channel (max speed) 10.6 10.7

Fast channel (max speed) 63 65 -

Slow channel (max speed) 63 65

Fast channel (max speed) 65 66

Slow channel (max speed) 65 66

Fast channel (max speed) 64 65

Slow channel (max speed) 64 65

Fast channel (max speed) 66 67

Slow channel (max speed) 66 67

5 5.4

3.5

4.5

2 4

2 3.5

4 4.5

1 1.5

LSB bits dB

DS11450 Rev 4

125/157

149

Electrical characteristics STM32L442KC

Table 68. ADC accuracy - limited test conditions 4 (1)(2)(3) (continued)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

THD

Total harmonic distortion

ADC clock frequency

26 MHz,

1.65 V ≤ V

DDA

3.6 V,

≤

= VREF+ ≤

Voltage scaling Range 2

Single ended

Differential

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

-71 -69

-73 -72

-73 -72 dB

1. Guaranteed by design.

2. ADC DC accuracy values are measured after internal calibration.

Schottky diode (pin to ground) to analog pins which may potentially inject negative current.

4. The I/O analog switch voltage booster is enable when V

DDA

< 2.4 V). It is disable when V

DDA

< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when

≥ 2.4 V. No oversampling.

Figure 21. ADC accuracy characteristics

SSA

4095

4094

4093

1 LSB

IDEAL

1 2 3 4 5 6

(2)

(3)

(1)

4093 4094 4095 4096

(1) Example of an actual transfer curve

(2) The ideal transfer curve

(3) End point correlation line

= total unajusted error : maximum deviation

between the actual and ideal transfer curves.

= offset error : maximum deviation

between the first actual transition and

the first ideal one.

= gain error : deviation between the last

ideal transition and the last actual one.

= differential linearity error : maximum

deviation between actual steps and the ideal ones.

= integral linearity error : maximum deviation

between any actual transition and the end point

correlation line.

DDA

MS19880V2

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STM32L442KC

AIN

(1)

Electrical characteristics

Figure 22. Typical connection diagram using the ADC

DDA

AINx

C parasitic

(2)

I lkg

(3)

Sample and hold ADC converter

ADC

12-bit converter

ADC

MS33900V5

1. Refer to Table 63: ADC characteristics

for the values of R

AIN

and C

ADC

2. C parasitic

represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

Table 57: I/O static characteristics for the value of the pad capacitance). A high

C parasitic

value will downgrade conversion accuracy. To remedy this, f

ADC

should be reduced.

3. Refer to Table 57: I/O static characteristics for the values of Ilkg.

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 9: Power supply scheme

The 10 nF capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip.

DS11450 Rev 4

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149

Electrical characteristics STM32L442KC

Symbol

DDA

REF+

REF-

BON

BOFF

Parameter

Table 69. DAC characteristics (1)

Conditions

Analog supply voltage for

DAC ON

DAC output buffer OFF (no resistive load on DAC1_OUTx pin or internal connection)

Other modes

Min

1.71

1.80

Positive reference voltage

DAC output buffer OFF (no resistive load on DAC1_OUTx pin or internal connection)

Other modes

Negative reference voltage

Resistive load

Output Impedance

Capacitive load

DAC output buffer ON connected to V

SSA connected to V

DDA

DAC output buffer OFF

Output impedance sample and hold mode, output buffer ON

= 2.7 V

= 2.0 V

Output impedance sample and hold mode, output buffer OFF

= 2.7 V

= 2.0 V

DAC output buffer ON

Sample and hold mode

1.71

1.80

9.6

DAC_OUT t

SETTLING t

WAKEUP

(2)

PSRR

Voltage on DAC1_OUTx output

DAC output buffer ON

DAC output buffer OFF

Settling time (full scale: for a 12-bit code transition between the lowest and the highest input codes when DAC1_OUTx reaches final value

±0.5LSB, ±1 LSB, ±2 LSB,

±4 LSB, ±8 LSB)

Normal mode

DAC output buffer ON

CL ≤ 50 pF,

RL ≥ 5 k Ω

±0.5 LSB

±1 LSB

±2 LSB

±4 LSB

±8 LSB

Normal mode DAC output buffer

OFF, ±1LSB, CL = 10 pF

Wakeup time from off state

(setting the ENx bit in the

DAC Control register) until final value ±1 LSB

Normal mode DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω

Normal mode DAC output buffer

OFF, CL ≤ 10 pF

DDA

supply rejection ratio

Normal mode DAC output buffer ON

CL ≤ 50 pF, RL = 5 k Ω , DC

0.2

Typ Max Unit

3.6

DDA

13.8

3.5

16.5

18.0

REF+

– 0.2

REF+

2.9

2.85

2.8

2.75

2.5

k Ω k Ω k Ω k Ω pF

µF

µs

1.7

1.6

1.55

1.48

1.4

SSA

11.7

0.1

4.2

-80

7.5

-28

µs dB

128/157

DS11450 Rev 4

STM32L442KC Electrical characteristics

Symbol

W_to_W t

SAMP

I leak

CI int t

TRIM

V offset

DDA

(DAC)

Table 69. DAC characteristics (1) (continued)

Parameter Conditions Min

Minimal time between two consecutive writes into the

DAC_DORx register to guarantee a correct

DAC1_OUTx for a small variation of the input code

(1 LSB)

DAC_MCR:MODEx[2:0] =

000 or 001

DAC_MCR:MODEx[2:0] =

010 or 011

CL ≤ 50 pF, RL ≥ 5 k Ω

CL ≤ 10 pF

Sampling time in sample and hold mode (code transition between the lowest input code and the highest input code when

DAC1_OUTx reaches final value ±1LSB)

DAC1_OUTx pin connected

DAC1_OUTx pin not connected

(internal connection only)

Output leakage current

DAC output buffer

ON, C

DAC output buffer

OFF, C

= 100 nF

DAC output buffer

OFF

Sample and hold mode,

DAC1_OUTx pin connected

Internal sample and hold capacitor

Middle code offset trim time

DAC output buffer ON

Middle code offset for 1 trim code step

REF+

= 3.6 V

REF+

= 1.8 V

DAC consumption from

DDA

DAC output buffer ON

DAC output buffer OFF

No load, middle code (0x800)

No load, worst code

(0xF1C)

No load, middle code (0x800)

1.4

5.2

Sample and hold mode, C

100 nF

Typ

0.7

10.5

1500

750

315

450

Max

3.5

(3)

8.8

500

670

Unit

µs ms

µs nA pF

µs

µV

0.2

315 ₓ

Ton/(Ton

+Toff)

(4)

670 ₓ

Ton/(Ton

+Toff)

(4)

µA

DS11450 Rev 4

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149

Electrical characteristics STM32L442KC

Symbol

DDV

(DAC)

Table 69. DAC characteristics (1) (continued)

Parameter Conditions Min

DAC output buffer ON

DAC output buffer OFF

No load, middle code (0x800)

No load, worst code

(0xF1C)

No load, middle code (0x800)

DAC consumption from

REF+

Sample and hold mode, buffer ON,

= 100 nF, worst case

Typ

185

340

155

Max

240

400

205

Unit

185 ₓ

Ton/(Ton

+Toff)

(4)

400 ₓ

Ton/(Ton

+Toff)

(4)

µA

Sample and hold mode, buffer OFF,

= 100 nF, worst case

155 ₓ

Ton/(Ton

+Toff)

(4)

205 ₓ

Ton/(Ton

+Toff)

(4)

1. Guaranteed by design.

2. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).

3. Refer to Table 57: I/O static characteristics .

4. Ton is the Refresh phase duration. Toff is the Hold phase duration. Refer to RM0394 reference manual for more details.

Figure 23. 12-bit buffered / non-buffered DAC

Buffered/non-buffered DAC

Buffer

(1)

LOAD

12-bit digital to analog converter

DACx_OUT

LOAD ai17157d

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the

DAC_CR register.

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DS11450 Rev 4

STM32L442KC

Symbol

DNL

INL

Parameter

Table 70. DAC accuracy (1)

Conditions

Differential non linearity

(2) monotonicity

Integral non linearity

(3)

DAC output buffer ON

DAC output buffer OFF

10 bits

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω

DAC output buffer OFF

CL ≤ 50 pF, no RL

Offset

Offset1

Offset error at code 0x800

(3)

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω

Offset error at code 0x001

(4)

DAC output buffer OFF

CL ≤ 50 pF, no RL

DAC output buffer OFF

CL ≤ 50 pF, no RL

REF+

= 3.6 V

= 1.8 V

OffsetCal

Gain

TUE

TUECal

SNR

THD

Offset Error at code 0x800 after calibration

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω

REF+

= 3.6 V

REF+

= 1.8 V

Gain error

Total unadjusted error

(5)

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω

DAC output buffer OFF

CL ≤ 50 pF, no RL

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω

DAC output buffer OFF

CL ≤ 50 pF, no RL

Total unadjusted error after calibration

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω

Signal-to-noise ratio

Total harmonic distortion

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω

1 kHz, BW 500 kHz

DAC output buffer OFF

CL ≤ 50 pF, no RL, 1 kHz

BW 500 kHz

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω , 1 kHz

DAC output buffer OFF

CL ≤ 50 pF, no RL, 1 kHz

Electrical characteristics

Min

Typ

guaranteed

Max

±2

±4

±5

±7

±0.5

±30

±12

±25

±8

±5

Unit

LSB

71.2

71.6

-78

-79

±23 LSB

dB dB

DS11450 Rev 4

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149

Electrical characteristics STM32L442KC

Symbol Parameter

Table 70. DAC accuracy (1) (continued)

Conditions Min Typ Max Unit

SINAD

ENOB

Signal-to-noise and distortion ratio

Effective number of bits

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω , 1 kHz

DAC output buffer OFF

CL ≤ 50 pF, no RL, 1 kHz

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω , 1 kHz

DAC output buffer OFF

CL ≤ 50 pF, no RL, 1 kHz

70.4

11.4

11.5

dB bits

1. Guaranteed by design.

2. Difference between two consecutive codes - 1 LSB.

3. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095.

4. Difference between the value measured at Code (0x001) and the ideal value.

5. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when buffer is OFF, and from code giving 0.2 V and (V

REF+

– 0.2) V when buffer is ON.

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Symbol Parameter

Table 71. COMP characteristics (1)

Conditions

DDA

Analog supply voltage

Comparator input voltage range

Scaler input voltage

(2)

Scaler offset voltage

BRG_EN=0 (bridge disable)

DDA

(SCALER)

Scaler static consumption from V

DDA t

START_SCALER

Scaler startup time t

START t

(3)

BRG_EN=1 (bridge enable)

Comparator startup time to reach propagation delay specification

Propagation delay with

100 mV overdrive

High-speed mode

DDA

≥ 2.7 V

DDA

< 2.7 V

Medium mode

DDA

≥ 2.7 V

DDA

< 2.7 V

Ultra-low-power mode

High-speed mode

Medium mode

DDA

≥ 2.7 V

DDA

< 2.7 V

V offset

V hys

Comparator offset error

Comparator hysteresis

Ultra-low-power mode

Full common mode range

No hysteresis

Low hysteresis

Medium hysteresis

High hysteresis

Min Typ Max Unit

1.62

3.6

0 V

DDA

0.55

0.8

100

REFINT

±5

200

±10

300

200

100

0.9

µs ns

µs mV nA

µA

µs

±5

±20

mV mV

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149

Electrical characteristics STM32L442KC

Symbol

DDA

(COMP)

Table 71. COMP characteristics (1) (continued)

Parameter Conditions Min Typ Max Unit

400 600

Ultra-lowpower mode

Comparator consumption from V

DDA

Medium mode

High-speed mode

Static -

With 50 kHz

±100 mV overdrive square signal

Static -

With 50 kHz

±100 mV overdrive square signal

Static -

With 50 kHz

±100 mV overdrive square signal

1200

100 nA

µA

I bias

Comparator input bias current

1. Guaranteed by design, unless otherwise specified.

2. Refer to Table 24: Embedded internal voltage reference

3. Guaranteed by characterization results.

4. Mostly I/O leakage when used in analog mode. Refer to I lkg

parameter in Table 57: I/O static characteristics .

(4) nA

Symbol

DDA

CMIR

OFFSET

∆ VI

OFFSET

Parameter

Table 72. OPAMP characteristics (1)

Conditions

Analog supply voltage

(2)

Common mode input range

Input offset voltage

Input offset voltage drift

25 °C, No Load on output.

All voltage/Temp.

Normal mode

Low-power mode

TRIMOFFSETP

TRIMLPOFFSETP

TRIMOFFSETN

TRIMLPOFFSETN

Offset trim step at low common input voltage

(0.1 ₓ V

DDA

)

Offset trim step at high common input voltage

(0.9 ₓ V

DDA

)

Min

1.8

Typ

Max

3.6

Unit

±5

±10

DDA

±1.5

±3

V mV

μ V/°C

0.8

1.1

1.35

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STM32L442KC

Symbol

LOAD

LOAD_PGA

LOAD

LOAD_PGA

LOAD

CMRR

PSRR

GBW

(3)

OHSAT

(3)

OLSAT

(3)

φ m

Electrical characteristics

Table 72. OPAMP characteristics (1) (continued)

Parameter Conditions Min

Drive current

Drive current in

PGA mode

Normal mode

Low-power mode

Normal mode

Low-power mode

DDA

≥ 2 V

DDA

≥ 2 V

Resistive load

(connected to

VSSA or to

VDDA)

Normal mode

Low-power mode

DDA

< 2 V

Typ

Max

500

100

450

Unit

µA

Resistive load in PGA mode

(connected to

VSSA or to

DDA

)

Capacitive load

Power supply rejection ratio

Low saturation voltage

Phase margin

Normal mode

Low-power mode

Common mode rejection ratio

Normal mode

Low-power mode

Normal mode

Low-power mode

Normal mode

Gain Bandwidth

Product

Low-power mode

Normal mode

Low-power mode

Slew rate

(from 10 and

90% of output voltage)

Open loop gain

Normal mode

Low-power mode

Normal mode

Low-power mode

Normal mode

Low-power mode

High saturation voltage

Normal mode

Low-power mode

Normal mode

Low-power mode

Normal mode

Low-power mode

DDA

< 2 V

4.5

40 -

-85

-90

LOAD

≤ 50 pf,

≥ 4 k Ω DC

LOAD

≤ 50 pf,

≥ 20 k Ω DC

DDA

≥ 2.4 V

(OPA_RANGE = 1)

DDA

< 2.4 V

(OPA_RANGE = 0)

≥ 2.4 V

< 2.4 V

I load

= max or R load min Input at V

DDA

100

DDA

load

= max or R load min Input at 0.

90 -

550 1600 2200

100 420 600

250

700

180

950

280

700

180

300

80 -

110

110 -

100

k Ω pF dB dB kHz

V/ms dB mV

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149

Electrical characteristics STM32L442KC

Symbol

GM t

WAKEUP

I bias

PGA gain

(3)

Table 72. OPAMP characteristics (1) (continued)

Parameter Conditions Min

Gain margin

Normal mode

Low-power mode -

Wake up time from OFF state.

Normal mode

Low-power mode

LOAD

≤

≥ follower

50 pf,

4 k Ω configuration

LOAD

≤

≥ follower

50 pf,

20 k Ω configuration

OPAMP input bias current

General purpose input -

Non inverting gain value

PGA Gain = 2

R network

R2/R1 internal resistance values in PGA mode

(5)

PGA Gain = 4

PGA Gain = 8

PGA Gain = 16

Delta R

Resistance variation (R1 or

R2)

PGA gain error PGA gain error

Gain = 2

-15

-1

PGA BW

PGA bandwidth for different non inverting gain

Gain = 4

Gain = 8

Gain = 16 -

Typ

GBW/

80/80

120/

140/

150/

Max

(4)

Unit dB

µs nA

k Ω /k Ω

MHz

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Symbol

Table 72. OPAMP characteristics (1) (continued)

Parameter Conditions Min Typ Max Unit en

Voltage noise density

Normal mode

Low-power mode

Normal mode

Low-power mode at 1 kHz, Output loaded with 4 k Ω at 1 kHz, Output loaded with 20 k Ω at 10 kHz, Output loaded with 4 k Ω at 10 kHz, Output loaded with 20 k Ω

500

600

180

290 -

nV/ √

DDA

(OPAMP)

(3)

OPAMP consumption from V

DDA

Normal mode

Low-power mode no Load, quiescent mode

120

260

100

1. Guaranteed by design, unless otherwise specified.

2. The temperature range is limited to 0 °C-125 °C when V

DDA

is below 2 V

3. Guaranteed by characterization results.

4. Mostly I/O leakage, when used in analog mode. Refer to I lkg

parameter in

Table 57: I/O static characteristics

5. R2 is the internal resistance between OPAMP output and OPAMP inverting input. R1 is the internal resistance between

OPAMP inverting input and ground. The PGA gain =1+R2/R1

µA

6.3.22 Temperature sensor characteristics

Symbol

(1)

Avg_Slope (2)

30 t

START

(TS_BUF)

(1)

START

(1)

Table 73. TS characteristics

Parameter

linearity with temperature

Average slope

Voltage at 30°C (±5 °C)

(3)

Sensor Buffer Start-up time in continuous mode

Start-up time when entering in continuous mode

(4)

Min

2.3

0.742

Typ

±1

2.5

0.76

Max

±2

2.7

0.785

120

Unit

°C mV/°C

µs

µs t

S_temp

(1)

ADC sampling time when reading the temperature 5 µs

(TS) (1)

Temperature sensor consumption from V

DD selected by ADC

, when

4.7

7 µA

1. Guaranteed by design.

2. Guaranteed by characterization results.

3. Measured at V = 3.0 V ±10 mV. The V

Temperature sensor calibration values

ADC conversion result is stored in the TS_CAL1 byte. Refer to

Table 7:

4. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes.

The parameters given in the following tables are guaranteed by design.

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149

Electrical characteristics STM32L442KC

Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate

function characteristics (output compare, input capture, external clock, PWM output).

Symbol

Table 74. TIMx (1) characteristics

Parameter Conditions Min Max Unit t res(TIM)

Timer resolution time

TIMxCLK

= 80 MHz

12.5

TIMxCLK ns f

EXT

Res

TIM

Timer external clock frequency on CH1 to CH4

Timer resolution f

TIMxCLK

= 80 MHz

TIMx (except

TIM2)

TIMxCLK

/2 MHz

MHz bit

TIM2 32 t

COUNTER

16-bit counter clock period

1 f

TIMxCLK

= 80 MHz 0.0125

MAX_COUNT

Maximum possible count with 32-bit counter f

TIMxCLK

= 80 MHz -

1. TIMx

, is used as a general term in which x stands for 1,2,3,4,5,6,7,8,15,16 or 17.

65536

819.2

TIMxCLK

µs

65536 × 65536 t

TIMxCLK

53.68

Table 75. IWDG min/max timeout period at 32 kHz (LSI) (1)

Prescaler divider PR[2:0] bits

Min timeout RL[11:0]=

0x000

Max timeout RL[11:0]=

0xFFF

Unit

/16

/32

/64

/128

/256

6 or 7

0.125

0.250

0.500

1.0

2.0

4.0

8.0

512

1024

2048

4096

8192

16384

32768 ms

1. The exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.

Prescaler

Table 76. WWDG min/max timeout value at 80 MHz (PCLK)

WDGTB Min timeout value Max timeout value

0.0512

0.1024

0.2048

0.4096

3.2768

6.5536

13.1072

26.2144

Unit ms

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6.3.24 Communication interfaces characteristics

I

C interface characteristics

The I2C interface meets the timings requirements of the I 2 C-bus specification and user manual rev. 03 for:

• Standard-mode (Sm): with a bit rate up to 100 kbit/s

• Fast-mode (Fm): with a bit rate up to 400 kbit/s

• Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.

The I2C timings requirements are guaranteed by design when the I2C peripheral is properly configured (refer to RM0394 reference manual).

The SDA and SCL I/O requirements are met with the following restrictions: the SDA and

SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and V

DDIOx

is disabled, but is still present. Only FT_f I/O pins support Fm+ low level output current maximum requirement. Refer to

Section 6.3.14: I/O port characteristics for the I2C I/Os characteristics.

All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog filter characteristics:

Symbol

Table 77. I2C analog filter characteristics

(1)

Parameter t

Maximum pulse width of spikes that are suppressed by the analog filter

1. Guaranteed by design.

2. Spikes with widths below t

AF(min) are filtered.

3. Spikes with widths above t

AF(max)

are not filtered

Min

(2)

Max

260

(3)

Unit ns

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149

Electrical characteristics STM32L442KC

SPI characteristics

Unless otherwise specified, the parameters given in

Table 78

for SPI are derived from tests performed under the ambient temperature, f

PCLKx frequency and supply voltage conditions summarized in

Table 21: General operating conditions .

• Output speed is set to OSPEEDRy[1:0] = 11

• Capacitive load C = 30 pF

• Measurement points are done at CMOS levels: 0.5 ₓ V

Refer to Section 6.3.14: I/O port characteristics

for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI).

Symbol Parameter

Table 78. SPI characteristics

(1)

Conditions

1/t

SCK c(SCK)

SPI clock frequency

Master mode receiver/full duplex

2.7 < V

< 3.6 V

Voltage Range 1

Master mode receiver/full duplex

1.71 < V

< 3.6 V

Voltage Range 1

Master mode transmitter

1.71 < V

< 3.6 V

Voltage Range 1

Slave mode receiver

1.71 < V

< 3.6 V

Voltage Range 1

Slave mode transmitter/full duplex

2.7 < V

< 3.6 V

Voltage Range 1

Slave mode transmitter/full duplex

1.71 < V

< 3.6 V

Voltage Range 1

Voltage Range 2 t su(NSS) t h(NSS) t w(SCKH) t w(SCKL) t su(MI) t su(SI) t h(MI) t h(SI) t a(SO) t dis(SO)

NSS setup time

NSS hold time

SCK high and low time Master mode

Data input setup time

Data input hold time

Slave mode, SPI prescaler = 2

Master mode

Slave mode

Master mode

Slave mode

Data output access time Slave mode

Data output disable time Slave mode

Min

4 ₓ T

PCLK

2 ₓ T

PCLK

1.5

6.5

1.5

Typ

PCLK

-2 T

PCLK

Max

(2)

Unit

MHz ns ns

PCLK

+2 ns ns ns ns ns

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Symbol Parameter

Table 78. SPI characteristics (1) (continued)

Conditions Min Typ Max Unit t v(SO)

Data output valid time

Slave mode 2.7 < V

Voltage Range 1

< 3.6 V

Slave mode 1.71 < V

Voltage Range 1

< 3.6 V

Slave mode 1.71 < V

Voltage Range 2

< 3.6 V

12.5

13.5

33 ns t v(MO) t h(SO) t h(MO)

Data output hold time

Master mode

Slave mode

Master mode

4.5

1. Guaranteed by characterization results.

2. Maximum frequency in Slave transmitter mode is determined by the sum of t having t su(MI)

= 0 while Duty(SCK) = 50 %.

v(SO)

and t su(MI)

which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master

Figure 24. SPI timing diagram - slave mode and CPHA = 0

NSS input t su(NSS) t w(SCKH) t c(SCK) t r(SCK) t h(NSS)

CPHA=0

CPOL=0

CPHA=0

CPOL=1 t a(SO)

MISO output t w(SCKL)

First bit OUT t h(SI) t v(SO) t h(SO)

Next bits OUT t f(SCK)

Last bit OUT t dis(SO) t su(SI)

MOSI input First bit IN Next bits IN Last bit IN

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149

Electrical characteristics

Figure 25. SPI timing diagram - slave mode and CPHA = 1

NSS input t su(NSS) t w(SCKH) t c(SCK) t f(SCK)

CPHA=1

CPOL=0

CPHA=1

CPOL=1

MISO output

MOSI input t a(SO) t w(SCKL) t v(SO) t su(SI)

First bit OUT t h(SI)

First bit IN t h(SO)

Next bits OUT

Next bits IN

STM32L442KC t h(NSS) t r(SCK) t dis(SO)

Last bit OUT

Last bit IN

MSv41659V1

1. Measurement points are done at CMOS levels: 0.3 V

and 0.7 V

Figure 26. SPI timing diagram - master mode

High

NSS input tc(SCK)

CPHA= 0

CPOL=0

CPHA= 0

CPOL=1

CPHA=1

CPOL=0

CPHA=1

CPOL=1

MISO

INP UT

MOSI

OUTPUT tsu(MI) tw(SCKH) tw(SCKL)

MSB IN th(MI)

MSB OUT tv(MO)

BIT6 IN

B I T1 OUT th(MO)

1. Measurement points are done at CMOS levels: 0.3 V

and 0.7 V

tr(SCK) tf(SCK)

LSB IN

LSB OUT ai14136c

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Quad SPI characteristics

Unless otherwise specified, the parameters given in

Table 79

and Table 80 for Quad SPI

are derived from tests performed under the ambient temperature, f

AHB

frequency and V

supply voltage conditions summarized in Table 21: General operating conditions

, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 11

• Capacitive load C = 15 or 20 pF

• Measurement points are done at CMOS levels: 0.5 ₓ V

Refer to Section 6.3.14: I/O port characteristics

for more details on the input/output alternate function characteristics.

Symbol

1/t

(CK) t w(CKH) t w(CKL) t s(IN) t h(IN) t v(OUT) t h(OUT)

Table 79. Quad SPI characteristics in SDR mode (1)

Parameter Conditions Min

Quad SPI clock frequency

1.71 < V

< 3.6 V, C

LOAD

= 20 pF

Voltage Range 1

1.71 < V

< 3.6 V, C

LOAD

= 15 pF

Voltage Range 1

2.7 < V

< 3.6 V, C

LOAD

= 15 pF

Voltage Range 1

1.71 < V

< 3.6 V C

LOAD

= 20 pF

Voltage Range 2

Quad SPI clock high and low time

Data input setup time

Data input hold time

Data output valid time

Data output hold time f

AHBCLK

= 48 MHz, presc=0

Voltage Range 1

Voltage Range 2

Voltage Range 1

Voltage Range 2

Voltage Range 1

Voltage Range 2

Voltage Range 1

Voltage Range 2

6.5

0 t

(CK)

/2-2 t

(CK)

3.5

1. Guaranteed by characterization results.

Typ

Max

(CK)

/2 t

(CK)

/2+2

Unit

MHz ns

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Electrical characteristics STM32L442KC

Symbol

Table 80. QUADSPI characteristics in DDR mode (1)

Parameter Conditions

1/t

(CK)

Quad SPI clock frequency

1.71 < V

< 3.6 V, C

LOAD

= 20 pF

Voltage Range 1

2 < V

< 3.6 V, C

LOAD

Voltage Range 1

= 20 pF

1.71 < V

< 3.6 V, C

LOAD

= 15 pF

Voltage Range 1

1.71 < V

< 3.6 V C

Voltage Range 2

LOAD

= 20 pF t w(CKH) t w(CKL)

Quad SPI clock high and low time f

AHBCLK

= 48 MHz, presc=0 t t t t sr(IN) sf(IN) hr(IN) hf(IN)

Data input setup time on rising edge

Voltage Range 1

Voltage Range 2

Data input setup time on falling edge

Voltage Range 1

Data input hold time on rising edge

Voltage Range 2

Voltage Range 1

Voltage Range 2

Data input hold time on falling edge

Voltage Range 1

Voltage Range 2 t t vr(OUT) vf(OUT)

Data output valid time on rising edge

Voltage Range 1

Voltage Range 2

Data output valid time on falling edge

Voltage Range 1

Voltage Range 2 t t hr(OUT) hf(OUT)

Data output hold time on rising edge

Voltage Range 1

Voltage Range 2

Data output hold time on falling edge

Voltage Range 1

Voltage Range 2

1. Guaranteed by characterization results.

Min

Typ

Max

26 t

(CK)

/2-2 t

(CK)

/2 t

(CK)

/2+2

3.5

1.5

6.5

5.5

3.5

9.5

5.5

8.5

Unit

MHz ns

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Figure 27. Quad SPI timing diagram - SDR mode t

(CK) t w(CKH) t w(CKL) t f(CK)

Clock

Data output

Data input t v(OUT) t h(OUT)

D0 t s(IN)

D1 t h(IN)

D1 D0 t r(CK)

Figure 28. Quad SPI timing diagram - DDR mode t

(CK) t w(CKH) t w(CKL)

D2 t f(CK)

MSv36878V1

Clock

Data output

Data input t vf(OUT) t hr(OUT)

D0 t vr(OUT)

D1 t sf(IN) t hf(IN)

D1 D2

D3 t hf(OUT)

D4 t sr(IN) t hr(IN)

D4 D5

MSv36879V1

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Electrical characteristics STM32L442KC

SAI characteristics

Unless otherwise specified, the parameters given in

Table 81

for SAI are derived from tests performed under the ambient temperature, f

PCLKx

frequency and V

DD supply voltage conditions summarized in

Table 21: General operating conditions , with

the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 10

• Capacitive load C = 30 pF

• Measurement points are done at CMOS levels: 0.5 ₓ V

Refer to Section 6.3.14: I/O port characteristics

for more details on the input/output alternate function characteristics (CK,SD,FS).

Symbol

Table 81. SAI characteristics (1)

Parameter Conditions Max Unit f

MCLK

SAI Main clock output t f

CK v(FS) t h(FS) t su(FS) t h(FS) t su(SD_A_MR) t su(SD_B_SR) t h(SD_A_MR) t h(SD_B_SR)

SAI clock frequency

(2)

FS valid time

FS hold time

FS setup time

FS hold time

Data input setup time

Data input hold time

Master transmitter

2.7 ≤ V

≤ 3.6

Voltage Range 1

Master transmitter

1.71 ≤ V

≤ 3.6

Voltage Range 1

Master receiver

Voltage Range 1

Slave transmitter

2.7 ≤ V

≤ 3.6

Voltage Range 1

Slave transmitter

1.71 ≤ V

≤ 3.6

Voltage Range 1

Slave receiver

Voltage Range 1

Voltage Range 2

Master mode

2.7 ≤ V

≤ 3.6

Master mode

1.71 ≤ V

≤ 3.6

Master mode

Slave mode

Master receiver

Slave receiver

Master receiver

Slave receiver

1.5

2.5

50 MHz

18.5

12.5

22.5

14.5

12.5

MHz ns ns ns ns ns ns

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Symbol

Table 81. SAI characteristics (1) (continued)

Parameter Conditions Max Unit t v(SD_B_ST)

Data output valid time

Slave transmitter (after enable edge)

2.7 ≤ V

≤ 3.6

Slave transmitter (after enable edge)

1.71 ≤ V

≤ 3.6

Data output hold time Slave transmitter (after enable edge) t h(SD_B_ST) t v(SD_A_MT)

Data output valid time

Master transmitter (after enable edge)

2.7 ≤ V

≤ 3.6

Master transmitter (after enable edge)

1.71 ≤ V

≤ 3.6

Data output hold time Master transmitter (after enable edge) t h(SD_A_MT)

1. Guaranteed by characterization results.

2. APB clock frequency must be at least twice SAI clock frequency.

ns ns ns ns

Figure 29. SAI master timing waveforms

1/fSCK

SAI_SCK_X th(FS)

SAI_FS_X

(output)

SAI_SD_X

(transmit) tv(FS)

SAI_SD_X

(receive) tsu(SD_MR) tv(SD_MT)

Slot n th(SD_MR)

Slot n+2

Slot n th(SD_MT)

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Electrical characteristics STM32L442KC

Figure 30. SAI slave timing waveforms

1/fSCK

SAI_SCK_X tw(CKH_X) tw(CKL_X) th(FS)

SAI_FS_X

(input)

SAI_SD_X

(transmit) tsu(FS) tsu(SD_SR) tv(SD_ST)

Slot n th(SD_SR)

Slot n

Slot n+2 th(SD_ST)

SAI_SD_X

(receive)

MS32772V1

USB characteristics

The STM32L442KC USB interface is fully compliant with the USB specification version 2.0 and is USB-IF certified (for Full-speed device operation).

Symbol

DDUSB

T crystal_less

PUI

PUR

DRV

(3)

Table 82. USB electrical characteristics (1)

Parameter Conditions Min Typ

USB transceiver operating voltage

USB crystal less operation temperature

Embedded USB_DP pull-up value during idle

Embedded USB_DP pull-up value during reception

Output driver impedance

(4)

Driving high and low

3.0

(2)

-15

900

1400

1250

2300

Max

3.6

1600

3200

1. T

= -40 to 125 °C unless otherwise specified.

2. The STM32L442KC USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics which are degraded in the 2.7-to-3.0 V voltage range.

3. Guaranteed by design.

4. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-); the matching impedance is already included in the embedded driver.

Unit

° C

Ω

CAN (controller area network) interface

Refer to Section 6.3.14: I/O port characteristics

for more details on the input/output alternate function characteristics (CAN_TX and CAN_RX).

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SWPMI characteristics

The Single Wire Protocol Master Interface (SWPMI) and the associated SWPMI_IO transceiver are compliant with the ETSI TS 102 613 technical specification.

Symbol t

SWPSTART t

SWPBIT

Table 83. SWPMI electrical characteristics

Parameter Conditions Min Typ Max Unit

SWPMI regulator startup time

SWP bit duration

SWP Class B

2.7 V ≤ V

≤ 3,3V

CORE

voltage range 1

CORE voltage range 2

500 -

620 -

300 μ s

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Package information STM32L442KC

7.1

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com

ECOPACK ® is an ST trademark.

UFQFPN32 package information

Figure 31. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package outline

D e

A3 ddd C

SEATINGPLANE b

D1 e

E2 b

E1 E

D2 L

PIN 1 Identifier

A0B8_ME_V3

1. Drawing is not to scale.

2. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this backside pad to PCB ground.

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Table 84. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max

E2 e

L ddd b

0.500

0.180

4.900

3.400

4.900

3.400

0.300

0.550

0.152

0.230

5.000

3.500

5.000

3.500

0.500

0.400

0.600

0.050

0.280

5.100

3.600

5.100

3.600

0.500

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.1929

0.1339

0.0118

0.0197

0.0071

0.1929

0.1339

0.0217

0.0060

0.0091

0.1969

0.1378

0.1969

0.1378

0.0197

0.0157

0.2008

0.1417

0.0197

0.0031

0.0236

0.0020

0.0110

0.2008

0.1417

Figure 32. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package recommended footprint

5.30

3.80

32 25

0.60

3.45

5.30

3.80

3.45

0.50

0.30

9 16

0.75

3.80

A0B8_FP_V2

1. Dimensions are expressed in millimeters.

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

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Package information STM32L442KC

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 33. UFQFPN32 marking (package top view)

Product identification

(1) L442KC6

Y WW

Date code

Revision code

Pin 1 identifier

MSv40150V1

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.

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The maximum chip junction temperature (T

Table 21: General operating conditions .

max) must never exceed the values given in

The maximum chip-junction temperature, T

J using the following equation:

max, in degrees Celsius, may be calculated

max = T

max + (P

max x Θ

)

Where:

• T

max is the maximum ambient temperature in °C,

• Θ

is the package junction-to-ambient thermal resistance, in °C/W,

• P

max is the sum of P

INT

max and P

I/O max (P

max = P

INT

max + P

I/O max),

• P

INT

max is the product of all I

DDXXX and maximum chip internal power.

DDXXX

, expressed in Watts. This is the

I/O

max represents the maximum power dissipation on output pins where:

I/O

max = Σ (V

× I

) + Σ ((V

DDIOx

– V

) × I

), taking into account the actual V

OL application.

/ I

and V

/ I

OH of the I/Os at low and high level in the

Symbol

Table 85. Package thermal characteristics

Parameter Value

Thermal resistance junction-ambient

UFQFPN32 - 5 × 5 mm / 0.5 mm pitch

Unit

°C/W

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural

Convection (Still Air). Available from www.jedec.org

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Ordering information STM32L442KC

Table 86. STM32L442KC ordering information scheme

Example:

Device family

STM32 = Arm

® based 32-bit microcontroller

STM32 L 442 K C U 6 TR

Product type

L = ultra-low-power

Device subfamily

442: STM32L442KC

Pin count

K = 32 pins

Flash memory size

C = 256 KB of Flash memory

Package

U = QFN ECOPACK

Temperature range

6 = Industrial temperature range, -40 to 85 °C (105 °C junction)

7 = Industrial temperature range, -40 to 105 °C (125 °C junction)

3 = Industrial temperature range, -40 to 125 °C (130 °C junction)

Packing

TR = tape and reel xxx = programmed parts

For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office.

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Date

08-Feb-2016

24-May-2016

12-Jun-2017

Table 87. Document revision history

Revision Changes

Initial release.

Updated document title.

Updated Table 1: STM32L442KC family device features and peripheral counts

Updated Section 3.25: Universal synchronous/asynchronous receiver transmitter

(USART)

Updated Table 14: STM32L442KC pin definitions

Updated Table 16: Alternate function AF8 to AF15 .

Updated Table 18: Voltage characteristics

Updated Table 21: General operating conditions

Added Figure 11: VREFINT versus temperature

Updated Table 23: Embedded reset and power control block characteristics .

Updated Table 39: Low-power mode wakeup timings

Added Table 41: Wakeup time using USART/LPUART

Updated Table 46: MSI oscillator characteristics .

Added Table 47: HSI48 oscillator characteristics

Added Figure 17: HSI48 frequency versus temperature

Updated Table 49: PLL, PLLSAI1 characteristics .

Updated Table 52: EMS characteristics

Updated Table 53: EMI characteristics .

Updated introduction of

Section 6.3.14: I/O port characteristics .

Added note to Figure 20: Recommended NRST pin protection .

Updated Table 62: Analog switches booster characteristics .

Updated Table 63: ADC characteristics .

Updated Table 71: COMP characteristics .

Updated Table 82: USB electrical characteristics .

Added Section : SWPMI characteristics

Updated Table 85: Package thermal characteristics

Added 1x LPUART on cover page.

Replaced all references to RM0393 by RM0394

(Reference Manual).

Added Table 3: STM32L442KC modes overview .

Updated Table 5: STM32L442KC peripherals interconnect matrix

Added Section 3.22.5: Infrared interface (IRTIM)

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Revision history STM32L442KC

Date

12-Jun-2017

21-May-2018

Table 87. Document revision history (continued)

Revision Changes

(continued)

Updated baudrate in

Section 3.25: Universal synchronous/asynchronous receiver transmitter

(USART)

Updated Section 6.1.7: Current consumption measurement

Added footnote to

Table 56: I/O current injection susceptibility

Updated Table 57: I/O static characteristics

Updated Section 6.3.18: Analog-to-Digital converter characteristics .

Added F

ADC

min in

Table 63: ADC characteristics

Updated Table 69: DAC characteristics

Added Ibias parameter in

Table 71: COMP characteristics .

Updated Section 7: Package information .

Updated DAC terminology in all the document for clarification: single DAC instance (= DAC1) with 2 output channels.

Added ECOPACK2® information in Features

Updated Section 3.9.1: Power supply schemes

Added Figure 3: Power-up/down sequence .

Updated Clock-out capability in Section 3.11: Clocks and startup

Updated Figure 4: Clock tree .

Updated Section 3.14.1: Nested vectored interrupt controller (NVIC) .

Updated Section 6.3.2: Operating conditions at powerup / power-down .

Updated A

Coeff

reference .

in Table 24: Embedded internal voltage

Updated Table 57: I/O static characteristics

Added Section 6.3.16: Extended interrupt and event controller input (EXTI) characteristics .

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Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

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