STMicroelectronics IIS2DH Datasheet

IIS2DH

Ultra-low-power high-performance 3-axis accelerometer

with digital output for industrial applications

Datasheet

-

production data

LGA-12 (2.0x2.0x1 mm)

Features

 Wide supply voltage, 1.71 V to 3.6 V

 Independent IOs supply (1.8 V) and supply voltage compatible

 Ultra-low power consumption down to 2 μ A

  2 g /±4 g /  8 g /  16 g selectable full scales

 I

2

C/SPI digital output interface

 3 operating modes: low-power, normal, highresolution mode

 2 independent programmable interrupt generators for free-fall and motion detection

 6D/4D orientation detection

 Motion detection & free-fall detection

 “Sleep-to-wake” and “return-to-sleep” functions

 Embedded FIFO

 Embedded self-test

 Embedded temperature sensor

 ECOPACK

®

, RoHS and “Green” compliant

Description

The IIS2DH is an ultra-low-power highperformance three-axis linear accelerometer with digital I 2 C/SPI serial interface standard output.

The IIS2DH has user-selectable full scales of

 2 g /±4 g /  8 g /  16 g and is capable of measuring accelerations with output data rates from 1 Hz to

5.3 kHz.

The device may be configured to generate interrupt signals by two independent inertial wake-up/free-fall events as well as by the position of the device itself.

The self-test capability allows the user to check the functionality of the sensor in the final application.

The IIS2DH is available in a small thin plastic land grid array package (LGA) and is guaranteed to operate over an extended temperature range from -40 °C to +85 °C.

Order code

Table 1. Device summary

Temperature range [  C]

Package Packaging

IIS2DHTR -40 to +85 LGA-12

Tape and reel

Applications

 Robotics

 Anti-tampering devices

 Vibration monitoring

 Tilt/inclination measurements

 Impact recognition and logging

 Industrial tools and factory equipment

 Motion-activated functions

April 2015

This is information on a product in full production.

DocID027668 Rev 2 1/49 www.st.com

Contents

Contents

1

2

3

4

2/49

IIS2DH

Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.1

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.2

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . 10

2.1

Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2

Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.4

Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.4.1

2.4.2

SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

I

2

C - inter-IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.5

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.6

Terminology and functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.6.1

2.6.2

Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.6.3

High-resolution, normal mode, low-power mode . . . . . . . . . . . . . . . . . . 16

2.6.4

2.6.5

2.6.6

Self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6D / 4D orientation detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

“Sleep-to-wake” and “Return-to-sleep” . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.7

Sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.8

IC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.9

Factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.10

FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.11

Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.1

Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Digital main blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.1

FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.1.1

Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

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5

Contents

4.1.2

4.1.3

4.1.4

4.1.5

FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Stream-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Retrieving data from FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.1

I 2

C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.1.1

I

2

C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.2

SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.2.1

5.2.2

5.2.3

SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

SPI read in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.1

STATUS_REG_AUX (07h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.2

OUT_TEMP_L (0Ch), OUT_TEMP_H (0Dh) . . . . . . . . . . . . . . . . . . . . . . 32

7.3

INT_COUNTER_REG (0Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.4

WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.5

TEMP_CFG_REG (1Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.6

CTRL_REG1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.7

CTRL_REG2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.8

CTRL_REG3 (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.9

CTRL_REG4 (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.10

CTRL_REG5 (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.11

CTRL_REG6 (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.12

REFERENCE/DATACAPTURE (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.13

STATUS_REG (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.14

OUT_X_L (28h), OUT_X_H (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.15

OUT_Y_L (2Ah), OUT_Y_H (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.16

OUT_Z_L (2Ch), OUT_Z_H (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.17

FIFO_CTRL_REG (2Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.18

FIFO_SRC_REG (2Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.19

INT1_CFG (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

DocID027668 Rev 2 3/49

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9

IIS2DH

7.20

INT1_SRC (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.21

INT1_THS (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.22

INT1_DURATION (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.23

INT2_CFG (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.24

INT2_SRC (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.25

INT2_THS (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.26

INT2_DURATION (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.27

CLICK_CFG (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.28

CLICK_SRC (39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

7.29

CLICK_THS (3Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.30

TIME_LIMIT (3Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.31

TIME_LATENCY (3Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.32

TIME_WINDOW (3Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.33

Act_THS (3Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

7.34

Act_DUR (3Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

8.1

LGA package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4/49 DocID027668 Rev 2

IIS2DH

List of tables

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

I

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2

C slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Operating mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 10.

Turn-on time for operating mode transition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 11.

Current consumption of operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 12.

Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 13.

I

2

C terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 14.

SAD+read/write patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 15.

Transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 16.

Transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 17.

Transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 25

Table 18.

Transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 25

Table 19.

Register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 20.

STATUS_REG_AUX register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 21.

STATUS_REG_AUX description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 22.

INT_COUNTER_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 23.

WHO_AM_I register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 24.

TEMP_CFG_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 25.

TEMP_CFG_REG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 26.

CTRL_REG1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 27.

CTRL_REG1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 28.

Data rate configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 29.

CTRL_REG2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 30.

CTRL_REG2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 31.

High-pass filter mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 32.

Low-power mode - high-pass filter cutoff frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 33.

CTRL_REG3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 34.

CTRL_REG3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 35.

CTRL_REG4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 36.

CTRL_REG4 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 37.

Self-test mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 38.

CTRL_REG5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 39.

CTRL_REG5 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 40.

CTRL_REG6 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 41.

CTRL_REG6 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 42.

REFERENCE/DATACAPTURE register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 43.

REFERENCE/DATACAPTURE description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 44.

STATUS_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 45.

STATUS_REG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 46.

FIFO_CTRL_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 47.

FIFO_CTRL_REG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 48.

FIFO mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

DocID027668 Rev 2 5/49

49

List of tables IIS2DH

Table 49.

FIFO_SRC_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 50.

FIFO_SRC_REG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 51.

INT1_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 52.

INT1_CFG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 53.

Interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 54.

INT1_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 55.

INT1_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 56.

INT1_THS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 57.

INT1_THS description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 58.

INT1_DURATION register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 59.

INT1_DURATION description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 60.

INT2_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 61.

INT2_CFG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 62.

Interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 63.

INT2_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 64.

INT2_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 65.

INT2_THS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 66.

INT2_THS description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 67.

INT2_DURATION register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 68.

INT2_DURATION description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 69.

CLICK_CFG register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 70.

CLICK_CFG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 71.

CLICK_SRC register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 72.

CLICK_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 73.

CLICK_THS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 74.

CLICK_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 75.

TIME_LIMIT register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 76.

TIME_LIMIT description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 77.

TIME_LATENCY register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 78.

TIME_LATENCY description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 79.

TIME_WINDOW register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 80.

TIME_WINDOW description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 81.

Act_THS register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 82.

Act_THS description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 83.

Act_DUR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 84.

Act_DUR description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 85.

Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6/49 DocID027668 Rev 2

IIS2DH

List of figures

List of figures

Figure 1.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 2.

Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 3.

SPI slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 4.

I

2

C slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 5.

IIS2DH electrical connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 6.

Read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 7.

SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 8.

Multiple byte SPI read protocol (2-byte example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 9.

SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 10.

Multiple byte SPI write protocol (2-byte example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 11.

SPI read protocol in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 12.

LGA-12 package outline and mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

DocID027668 Rev 2 7/49

49

Block diagram and pin description

1 Block diagram and pin description

D

Figure 1. Block diagram

;

<

=

=

<

;

08;

&+$5*(

$03/,),(5

$'

&219(57(5

&21752/

/2* ,&

,&

63,

&6

6&/63&

6'$6',6'2

6'26$

IIS2DH

6(/ ) 7(67

7HPSHUDWXUH

6HQVRU

75,00,1*

&,5&8,76

&/2&.

/HYHO

),)2

&21752/ /2*,&

,17(55837 *(1

,17

,17

$09

=

Figure 2. Pin connections

9GGB,2

9GG

*1'

*1'

; <

723 9,(:

',5(&7,21 2) 7+(

'(7(&7$%/(

$&&(/(5$7,216

%27720 9,(:

6&/63&

&6

6'26$

6'$6',6'2

8/49 DocID027668 Rev 2

IIS2DH

Pin#

1

2

3

4

10

11

8

9

12

5

6

7

Name

SCL

SPC

CS

SDO

SA0

SDA

SDI

SDO

Res

GND

GND

GND

Vdd

Vdd_IO

INT2

INT1

Block diagram and pin description

Table 2. Pin description

Function

I

2

C serial clock (SCL)

SPI serial port clock (SPC)

SPI enable

I

2

C/SPI mode selection:

1: SPI idle mode / I

2

C communication enabled

0: SPI communication mode / I

2

C disabled

SPI serial data output (SDO)

I

2

C less significant bit of the device address (SA0)

I

2

C serial data (SDA)

SPI serial data input (SDI)

3-wire interface serial data output (SDO)

Connect to GND

0 V supply

0 V supply

0 V supply

Power supply

Power supply for I/O pins

Interrupt pin 2

Interrupt pin 1

DocID027668 Rev 2 9/49

49

Mechanical and electrical specifications

2 Mechanical and electrical specifications

IIS2DH

@ Vdd = 2.5 V, T = 25 °C unless otherwise noted

(a)

Symbol

FS

So

TCSo

TyOff

Parameter

Table 3. Mechanical characteristics

Test conditions

Measurement range

(3)

FS bits set to 00

FS bits set to 01

FS bits set to 10

FS bits set to 11

FS bits set to 00;

Normal mode

FS bits set to 00;

High-resolution mode

FS bits set to 00;

Low-power mode

FS bits set to 01;

Normal mode

Sensitivity

FS bits set to 01;

High-resolution mode

FS bits set to 01;

Low-power mode

FS bits set to 10;

Normal mode

FS bits set to 10;

High-resolution mode

FS bits set to 10;

Low-power mode

FS bits set to 11;

Normal mode

FS bits set to 11;

High-resolution mode

FS bits set to 11;

Low-power mode

Sensitivity change vs. temperature

Typical zerog level offset accuracy

(4)

FS bits set to 00

FS bits set to 00

Min.

(1)

3.52

0.88

14.06

7.03

1.76

28.13

14.06

3.52

56.25

42.25

10.55

Typ.

(2)

±2.0

±4.0

±8.0

±16.0

Max.

(1)

169.81

188.68

207.55

-90

3.91

0.98

15.63

7.81

1.95

31.25

15.63

3.91

62.50

46.95

11.72

±0.01

±40

4.30

1.07

17.19

8.59

2.15

34.38

17.19

4.30

68.75

51.64

12.90

+90

Unit g m g /digit m g /digit m g /digit m g /digit

%/°C m g a. The product is factory calibrated at 2.5 V. The operational power supply range is from 1.71 V to 3.6 V.

10/49 DocID027668 Rev 2

IIS2DH Mechanical and electrical specifications

Symbol Parameter

Table 3. Mechanical characteristics (continued)

Test conditions Min.

(1)

Typ.

(2)

Max.

(1)

Unit

TCOff

Zerog level change vs. temperature

Max delta from 25 °C ±0.5

m g /°C

Vst

Self-test output change

(5) (6) (7)

FS bits set to 00

X-axis; Normal mode

FS bits set to 00

Y-axis; Normal mode

FS bits set to 00

Z-axis; Normal mode

17

17

17

360

360

360

LSb

LSb

LSb

Top

Operating temperature range

-40 +85 °C

1. Minimum and maximum values are based on characterization data and are not guaranteed

2. Typical specifications are not guaranteed.

3. Verified by wafer level test and measurement of initial offset and sensitivity.

4. Typical zero-g level offset value after factory calibration test at socket level.

5. The sign of “Self-test output change” is defined by the ST bit in CTRL_REG4 (23h)

, for all axes.

6. “Self-test output change” is defined as the absolute value of:

OUTPUT[LSb]

(Self test enabled)

- OUTPUT[LSb]

(Self test disabled)

. 1LSb = 4 m g at 10-bit representation, ±2 g full scale

7. After enabling the ST bit, correct data is obtained after two samples (low-power mode / normal mode) or after eight samples

(high-resolution mode).

2.2 Temperature sensor characteristics

@ Vdd = 2.5 V, T = 25 °C unless otherwise noted (b)

Symbol

Table 4. Temperature sensor characteristics

Parameter

TSDr

TODR

Top

Temperature sensor output change vs. temperature

Temperature refresh rate

Operating temperature range

1. Typical specifications are not guaranteed.

2. 8-bit resolution.

3. Refer to

Table 28 .

Min.

-40

Typ.

(1)

1

ODR

(3)

Max.

+85

Unit digit/°C

(2)

Hz

°C b. The product is factory calibrated at 2.5 V. Temperature sensor operation is guaranteed in the range 2 V - 3.6 V.

DocID027668 Rev 2 11/49

49

Mechanical and electrical specifications IIS2DH

@ Vdd = 2.5 V, T = 25 °C unless otherwise noted

(c)

Symbol Parameter

Table 5. Electrical characteristics

Test conditions Min.

Typ.

(1)

Max.

Vdd

Vdd_IO

Idd

Idd

IddLP

IddPdn

VIH

VIL

VOH

VOL

Top

Supply voltage

I/O pins supply voltage

(2)

Current consumption in normal mode

Current consumption in normal mode

Current consumption in low-power mode

Current consumption in power-down mode

Digital high-level input voltage

Digital low-level input voltage

High-level output voltage

Low-level output voltage

Operating temperature range

50 Hz ODR

1 Hz ODR

50 Hz ODR

1.71

1.71

0.8*Vdd_IO

0.9*Vdd_IO

-40

2.5

11

2

6

0.5

3.6

Vdd+0.1

0.2*Vdd_IO

0.1*Vdd_IO

+85

1. Typical specification are not guaranteed.

2. It is possible to remove Vdd, maintaining Vdd_IO without blocking the communication busses, in this condition the measurement chain is powered off.

Unit

V

V

μ A

μ A

μ A

μ A

V

V

V

V

° C

12/49 c. The product is factory calibrated at 2.5 V. The operational power supply range is from 1.71 V to 3.6 V.

DocID027668 Rev 2

IIS2DH Mechanical and electrical specifications

2.4 Communication interface characteristics

2.4.1 SPI - serial peripheral interface

Subject to general operating conditions for Vdd and Top.

Table 6. SPI slave timing values

Value

(1)

Symbol Parameter Unit

Min Max t c(SPC) f c(SPC) t su(CS) t h(CS) t su(SI) t h(SI) t v(SO) t h(SO) t dis(SO)

SPI clock cycle

SPI clock frequency

CS setup time

CS hold time

SDI input setup time

SDI input hold time

SDO valid output time

SDO output hold time

SDO output disable time

100

5

20

5

15

5

10

50

50 ns

MHz ns

1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production.

Figure 3. SPI slave timing diagram

&6

W

VX&6

W

F63&

W

K&6

63&

6',

W

VX6,

06%,1

W

K6,

/6%,1

W

Y62

W

K62

W

GLV62

6'2 06%287 /6%287

1. When no communication is ongoing, data on SDO is driven by internal pull-up resistors.

Note: Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output ports.

DocID027668 Rev 2 13/49

49

Mechanical and electrical specifications IIS2DH

2.4.2 I

2

C - inter-IC control interface

Subject to general operating conditions for Vdd and top.

Symbol Parameter

Table 7. I 2 C slave timing values

I

2

C standard mode

(1)

Min Max f

(SCL) t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t h(ST)

SCL clock frequency

SCL clock low time

SCL clock high time

SDA setup time

SDA data hold time

START condition hold time

0

4.7

4.0

250

0

4

100

3.45

t su(SR)

Repeated START condition setup time

4.7

t su(SP)

STOP condition setup time 4 t w(SP:SR)

Bus free time between STOP and START condition

4.7

1. Data based on standard I 2 C protocol requirement, not tested in production.

Figure 4. I

2

C slave timing diagram

0.6

100

0

0.6

I

2

C fast mode

(1)

Min Max

0

1.3

400

0.9

0.6

0.6

1.3

5(3($7('

67$57

67$57

W

VX65

67$57

6'$

W

Z6365

Unit kHz

μ s ns

μ s

μ s

W

VX6'$

W

K6'$

W

VX63

6723

6&/

Note:

W

K67

W

Z6&//

W

Z6&/+

Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.

14/49 DocID027668 Rev 2

IIS2DH

2.5

Note:

Mechanical and electrical specifications

Absolute maximum ratings

Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Symbol

Table 8. Absolute maximum ratings

Ratings

Vdd Supply voltage

Vdd_IO Supply voltage on I/O pins

Vin

Input voltage on any control pin

(CS, SCL/SPC, SDA/SDI/SDO, SDO/SA0)

Maximum value

-0.3 to 4.8

-0.3 to 4.8

-0.3 to Vdd_IO +0.3

A

POW

A

UNP

T

OP

T

STG

ESD

Acceleration (any axis, powered, Vdd = 2.5 V)

Acceleration (any axis, unpowered)

Operating temperature range

Storage temperature range

Electrostatic discharge protection (HBM)

3000 g for 0.5 ms

10000 g for 0.1 ms

3000 g for 0.5 ms

10000 g for 0.1 ms

-40 to +85

-40 to +125

2

Unit

V

V

V

°C

°C kV

Supply voltage on any pin should never exceed 4.8 V

This device is sensitive to mechanical shock, improper handling can cause permanent damage to the part.

This device is sensitive to electrostatic discharge (ESD), improper handling can cause permanent damage to the part.

DocID027668 Rev 2 15/49

49

Mechanical and electrical specifications IIS2DH

2.6 Terminology and functionality

Terminology

2.6.1 Sensitivity

Sensitivity describes the gain of the sensor and can be determined by applying 1 g acceleration to it. As the sensor can measure DC accelerations, this can be done easily by pointing the axis of interest towards the center of the Earth, noting the output value, rotating the sensor by 180 degrees (pointing to the sky) and noting the output value again. By doing so, ±1 g acceleration is applied to the sensor. Subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This value changes very little over temperature and time. The sensitivity tolerance describes the range of sensitivities of a large population of sensors.

2.6.2 Zerog level

The zerog level offset (TyOff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. A sensor in a steady state on a horizontal surface will measure 0 g for the X-axis and 0 g for the Y-axis whereas the Z-axis will measure 1 g . The output is ideally in the middle of the dynamic range of the sensor (content of OUT registers 00h, data expressed as two’s complement number). A deviation from the ideal value in this case is called zerog offset. Offset is to some extent a result of stress to the MEMS sensor and therefore the offset can slightly change after mounting the sensor on a printed circuit board or exposing it to extensive mechanical stress. Offset changes little over temperature, see

Table 3 “Zero-

g level change vs. temperature” (TCOff). The zerog level tolerance (TyOff) describes the standard deviation of the range of zerog levels of a population of sensors.

Functionality

2.6.3 High-resolution, normal mode, low-power mode

The IIS2DH provides three different operating modes: high-resolution mode , normal mode and low-power mode .

The table below summarizes how to select the different operating modes.

Operating mode

Table 9. Operating mode selection

CTRL_REG1[3]

(LPen bit)

CTRL_REG4[3]

(HR bit)

BW [Hz]

Turn-on time [ms]

1 0 ODR/2 1

Low-power mode

(8-bit data output)

Normal mode

(10-bit data output)

High-resolution mode

(12-bit data output)

Not allowed

0

0

1

0

1

1

ODR/2

ODR/9

--

1.6

7/ODR

--

So @ ±2 g

[m g /digit]

16

4

1

--

16/49 DocID027668 Rev 2

IIS2DH Mechanical and electrical specifications

The turn-on time to transition to another operating mode is given in

Table 10 .

Table 10. Turn-on time for operating mode transition

Operating mode change

Turn-on time

[ms]

12-bit mode to 8-bit mode

12-bit mode to 10-bit mode

10-bit mode to 8-bit mode

10-bit mode to 12-bit mode

8-bit mode to 10-bit mode

8-bit mode to 12-bit mode

1/ODR

1/ODR

1/ODR

7/ODR

1/ODR

7/ODR

1

10

25

50

100

200

400

1344

1620

5376

Table 11. Current consumption of operating modes

Operating mode [Hz]

Low-power mode

(8-bit data output)

[ μ A]

Normal mode

(10-bit data output)

[ μ A]

High resolution

(12-bit data output)

[ μ A]

10

18

36

--

4

6

2

3

100

185

20

38

73

185

--

--

6

11

2

4

20

38

73

185

--

--

6

11

2

4

2.6.4 Self-test

The self-test allows the user to check the sensor functionality without moving it. When the self-test is enabled, an actuation force is applied to the sensor, simulating a definite input acceleration. In this case the sensor outputs will exhibit a change in their DC levels which are related to the selected full scale through the device sensitivity. When the self-test is activated, the device output level is given by the algebraic sum of the signals produced by the acceleration acting on the sensor and by the electrostatic test-force. If the output signals change within the amplitude specified inside

Table 3

, then the sensor is working properly and the parameters of the interface chip are within the defined specifications.

2.6.5 6D / 4D orientation detection

The IIS2DH includes 6D / 4D orientation detection.

DocID027668 Rev 2 17/49

49

Mechanical and electrical specifications

2.6.6

IIS2DH

6D / 4D orientation recognition

In this configuration the interrupt is generated when the device is stable in a known direction. In 4D configuration, detection of the position of the Z-axis is disabled.

“Sleep-to-wake” and “Return-to-sleep”

The IIS2DH can be programmed to automatically switch to low-power mode upon recognition of a determined event.

Once the event condition is over, the device returns back to the preset normal or highresolution mode.

To enable this function the desired threshold value must be stored inside the

Act_THS (3Eh)

register while the duration value is written inside the

Act_DUR (3Fh)

register.

When the acceleration falls below the threshold value, the device automatically switches to low-power mode (10Hz ODR).

During this condition, the ODR[3:0] bits and the LPen bit inside CTRL_REG1 (20h) and the

HR bit in

CTRL_REG3 (22h)

are not considered.

As soon as the acceleration rises above threshold, the module restores the operating mode and ODRs as determined by the

CTRL_REG1 (20h) and

CTRL_REG3 (22h) settings.

A proprietary process is used to create a surface micromachined accelerometer. The technology processes suspended silicon structures which are attached to the substrate in a few points called anchors and are free to move in the direction of the sensed acceleration.

To be compatible with traditional packaging techniques, a cap is placed on top of the sensing element to avoid blocking the moving parts during the molding phase of the plastic encapsulation.

When an acceleration is applied to the sensor, the proof mass displaces from its nominal position, causing an imbalance in the capacitive half-bridge. This imbalance is measured using charge integration in response to a voltage pulse applied to the capacitor.

At steady state the nominal value of the capacitors are a few pF and when an acceleration is applied, the maximum variation of the capacitive load is in the fF range.

18/49

The complete measurement chain is composed of a low-noise capacitive amplifier which converts the capacitive unbalance of the MEMS sensor into an analog voltage that will be available to the user through an analog-to-digital converter.

The acceleration data may be accessed through an I

2

C/SPI interface, thus making the device particularly suitable for direct interfacing with a microcontroller.

The IIS2DH features a data-ready signal (DRDY) which indicates when a new set of measured acceleration data is available, thus simplifying data synchronization in the digital system that uses the device.

The IIS2DH may also be configured to generate an inertial wake-up and free-fall interrupt signal according to a programmed acceleration event along the enabled axes. Both free-fall and wake-up can be available simultaneously on two different pins.

DocID027668 Rev 2

IIS2DH Mechanical and electrical specifications

The IC interface is factory calibrated for sensitivity (So) and zerog level (TyOff).

The trim values are stored inside the device in non-volatile memory. Any time the device is turned on, these values are downloaded into the registers to be used during active operation. This allows using the device without further calibration.

2.10 FIFO

The IIS2DH contains a 10-bit, 32-level FIFO. Buffered output allows the following operation modes: FIFO, Stream, Stream-to-FIFO and FIFO bypass. When FIFO bypass mode is activated, FIFO is not operating and remains empty. In FIFO mode, measurement data from acceleration detection on the x, y, and z axes are stored in the FIFO buffer.

The IIS2DH is supplied with an internal temperature sensor. Temperature data can be

enabled by setting the TEMP_EN[1:0] bits to ‘1’ in the TEMP_CFG_REG (1Fh) register.

To retrieve the temperature sensor data the BDU bit in

CTRL_REG4 (23h)

must be set to ‘1’.

Both the OUT_TEMP_L (0Ch), OUT_TEMP_H (0Dh) registers must be read.

Temperature data is stored inside OUT_TEMP_H as two’s complement data in 8-bit format left-justified.

DocID027668 Rev 2 19/49

49

Application hints IIS2DH

20/49

Figure 5. IIS2DH electrical connections

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The device core is supplied through the Vdd line while the I/O pads are supplied through the

Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 μ F aluminum) should be placed as near as possible to pin 9 of the device (common design practice).

All the voltage and ground supplies must be present at the same time to have proper

behavior of the IC (refer to Figure 5 ). It is possible to remove Vdd while maintaining Vdd_IO

without blocking the communication bus, in this condition the measurement chain is powered off.

The functionality of the device and the measured acceleration data is selectable and accessible through the I 2 C or SPI interfaces. When using the I 2 C, CS must be tied high.

The functions, the threshold and the timing of the two interrupt pins (INT1 and INT2) can be completely programmed by the user through the I 2 C/SPI interface.

The LGA package is compliant with the ECOPACK ® , RoHS and “Green” standard.

It is qualified for soldering heat resistance according to JEDEC J-STD-020.

Leave “Pin 1 Indicator” unconnected during soldering.

Land pattern and soldering recommendations are available at www.st.com

.

DocID027668 Rev 2

IIS2DH

4 Digital main blocks

Digital main blocks

4.1 FIFO

The IIS2DH embeds a 32-level FIFO for each of the three output channels, X, Y and Z. This allows consistent power saving for the system, since the host processor does not need to continuously poll data from the sensor, but it can wake up only when needed and burst the significant data out from the FIFO.

In order to enable the FIFO buffer, the FIFO_EN bit in CTRL_REG5 (24h) must be set to ‘1’.

This buffer can work according to the following different modes: Bypass mode, FIFO mode,

Stream mode and Stream-to-FIFO mode. Each mode is selected by the FM [1:0] bits in

FIFO_CTRL_REG (2Eh) . Programmable FIFO watermark level, FIFO empty or FIFO

overrun events can be enabled to generate dedicated interrupts on the INT1 pin

(configuration through CTRL_REG3 (22h) ).

In the

FIFO_SRC_REG (2Fh) register the EMPTY bit is equal to ‘1’ when all FIFO samples

are ready and FIFO is empty.

In the

FIFO_SRC_REG (2Fh) register the WTM bit goes to ‘1’ if new data is written in the

buffer and

FIFO_SRC_REG (2Fh)

(FSS [4:0]) is greater than or equal to

FIFO_CTRL_REG

(2Eh)

(FTH [4:0]).

FIFO_SRC_REG (2Fh)

(WTM) goes to ‘0’ if reading an X, Y, Z data slot from FIFO and

FIFO_SRC_REG (2Fh) (FSS [4:0]) is less than or equal to

FIFO_CTRL_REG (2Eh) (FTH [4:0]).

In the

FIFO_SRC_REG (2Fh) register the OVRN_FIFO bit is equal to ‘1’ if the FIFO slot is

overwritten.

In Bypass mode the FIFO is not operational and for this reason it remains empty. For each channel only the first address is used. The remaining FIFO levels are empty.

Bypass mode must be used in order to reset the FIFO buffer when a different mode is operating (i.e. FIFO mode).

In FIFO mode, the buffer continues filling data from the X, Y and Z accelerometer channels until it is full (a set of 32 samples stored). When the FIFO is full, it stops collecting data from the input channels and the FIFO content remains unchanged.

An overrun interrupt can be enabled, I1_OVERRUN = '1' in the

CTRL_REG3 (22h) register,

in order to be raised when the FIFO stops collecting data. When the overrun interrupt occurs, the first data has been overwritten and the FIFO stops collecting data from the input channels.

After the last read it is necessary to exit Bypass mode in order to reset the FIFO content.

After this reset command, it is possible to restart FIFO mode just by selecting the FIFO

mode configuration (FM[1:0] bits) in register FIFO_CTRL_REG (2Eh) .

DocID027668 Rev 2 21/49

49

Digital main blocks IIS2DH

In Stream mode the FIFO continues filling data from the X, Y, and Z accelerometer channels until the buffer is full (a set of 32 samples stored) at which point the FIFO buffer index restarts from the beginning and older data is replaced by the current data. The oldest values continue to be overwritten until a read operation frees the FIFO slots.

An overrun interrupt can be enabled, I1_OVERRUN = '1' in the

CTRL_REG3 (22h) register,

in order to read the entire contents of the FIFO at once. If, in the application, it is mandatory not to lose data and it is not possible to read at least one sample for each axis within one

ODR period, a watermark interrupt can be enabled in order to read partially the FIFO and leave memory slots free for incoming data.

Setting the FTH [4:0] bit in the

FIFO_CTRL_REG (2Eh) register to an N value, the number

of X, Y and Z data samples that should be read at the rise of the watermark interrupt is up to

(N+1).

4.1.5

In Stream-to-FIFO mode, data from the X, Y and Z accelerometer channels are collected in a combination of Stream mode and FIFO mode. The FIFO buffer starts operating in Stream mode and switches to FIFO mode when the selected interrupt occurs.

The FIFO operating mode changes according to the INT1 pin value if the TR bit is set to ‘0’ in the

FIFO_CTRL_REG (2Eh)

register or the INT2 pin value if the TR bit is set to‘1’ in the

FIFO_CTRL_REG (2Eh) register.

When the interrupt pin is selected and the interrupt event is configured on the corresponding pin, the FIFO operates in Stream mode if the pin value is equal to ‘0’ and it operates in FIFO mode if the pin value is equal to ‘1’. Switching modes is dynamically performed according to the pin value.

Stream-to-FIFO can be used in order to analyze the sampling history that generates an interrupt. The standard operation is to read the contents of FIFO when the FIFO mode is triggered and the FIFO buffer is full and stopped.

Retrieving data from FIFO

FIFO data is read from OUT_X_L (28h), OUT_X_H (29h) , OUT_Y_L (2Ah), OUT_Y_H

(2Bh)

and

OUT_Z_L (2Ch), OUT_Z_H (2Dh) . When the FIFO is in Stream, Stream-to-FIFO

or FIFO mode, a read operation to the

OUT_X_L (28h), OUT_X_H (29h) , OUT_Y_L (2Ah),

OUT_Y_H (2Bh)

or

OUT_Z_L (2Ch), OUT_Z_H (2Dh)

registers provides the data stored in the FIFO. Each time data is read from the FIFO, the oldest X, Y and Z data are placed in the

OUT_X_L (28h), OUT_X_H (29h)

,

OUT_Y_L (2Ah), OUT_Y_H (2Bh) and OUT_Z_L (2Ch),

OUT_Z_H (2Dh)

registers and both single read and read-burst operations can be used.

The address to be read is automatically updated by the device and it rolls back to 0x28 when register 0x2D is reached. In order to read all FIFO levels in a multiple byte read,

192 bytes (6 output registers of 32 levels) have to be read.

22/49 DocID027668 Rev 2

IIS2DH Digital interfaces

The registers embedded inside the IIS2DH may be accessed through both the I 2 C and SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode.

The serial interfaces are mapped to the same pads. To select/exploit the I 2 C interface, the

CS line must be tied high (i.e. connected to Vdd_IO).

Pin name

CS

SCL

SPC

SDA

SDI

SDO

SA0

SDO

Table 12. Serial interface pin description

Pin description

SPI enable

I

2

C/SPI mode selection:

1: SPI idle mode / I

2

C communication enabled

0: SPI communication mode / I

2

C disabled

I

2

C serial clock (SCL)

SPI serial port clock (SPC)

I

2

C serial data (SDA)

SPI serial data input (SDI)

3-wire interface serial data output (SDO)

I

2

C less significant bit of the device address (SA0)

SPI serial data output (SDO)

5.1 I

2

C serial interface

The IIS2DH I 2 C is a bus slave. The I 2 C is employed to write data into registers whose content can also be read back.

The relevant I 2 C terminology is given in the table below.

Term

Transmitter

Receiver

Master

Slave

Table 13. I 2 C terminology

Description

The device which sends data to the bus

The device which receives data from the bus

The device which initiates a transfer, generates clock signals and terminates a transfer

The device addressed by the master

There are two signals associated with the I

2

C bus: the serial clock line (SCL) and the serial data line (SDA). The latter is a bidirectional line used for sending and receiving data to/from the interface. Both the lines must be connected to Vdd_IO through an external pull-up resistor. When the bus is free, both the lines are high.

The I

2

C interface is compliant with fast mode (400 kHz) I

2

C standards as well as with the normal mode.

DocID027668 Rev 2 23/49

49

Digital interfaces IIS2DH

5.1.1 I

2

C operation

The transaction on the bus is started through a START (ST) signal. A START condition is defined as a high-to-low transition on the data line while the SCL line is held HIGH. After this has been transmitted by the master, the bus is considered busy. The next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the master.

The Slave ADdress (SAD) associated to the IIS2DH is 001100xb. The SDO / SA0 pad can be used to modify the less significant bit of the device address. If the SA0 pad is connected to the voltage supply, LSb is ‘1’ (address 0011001b), else if the SA0 pad is connected to ground, the LSb value is ‘0’ (address 0011000b). This solution permits to connect and address two different accelerometers to the same I 2 C lines.

Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each byte of data received.

The I 2 C embedded inside the IIS2DH behaves like a slave device and the following protocol must be adhered to. After the start condition (ST) a slave address is sent, once a slave acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) is transmitted: the 7

LSb represent the actual register address while the MSB enables address auto increment. If the MSb of the SUB field is ‘1’, the SUB (register address) is automatically increased to allow multiple data read/writes.

The slave address is completed with a Read/Write bit. If the bit was ‘1’ (Read), a repeated

START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (Write) the master will transmit to the slave with direction unchanged.

Table 14 explains how the

SAD+read/write bit pattern is composed, listing all the possible configurations.

Command

Read

Write

Read

Write

Table 14. SAD+read/write patterns

SAD[6:1] SAD[0] = SA0 R/W

001100

001100

001100

001100

0

0

1

1

1

0

1

0

SAD+R/W

00110001 (31h)

00110000 (30h)

00110011 (33h)

00110010 (32h)

Master

Slave

Table 15. Transfer when master is writing one byte to slave

ST SAD + W SUB DATA

SAK SAK SAK

SP

24/49 DocID027668 Rev 2

IIS2DH Digital interfaces

Master

Slave

ST

Table 16. Transfer when master is writing multiple bytes to slave

SAD + W SUB DATA DATA

SAK SAK SAK SAK

SP

Master

Table 17. Transfer when master is receiving (reading) one byte of data from slave

ST SAD + W SUB SR SAD + R NMAK

Slave SAK SAK SAK DATA

SP

Table 18. Transfer when master is receiving (reading) multiple bytes of data from slave

Master ST SAD+W SUB SR SAD+R MAK MAK NMAK SP

Slave SAK SAK SAK DATA DATA DATA

Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit

(MSb) first. If a receiver can’t receive another complete byte of data until it has performed some other function, it can hold the clock line, SCL low to force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and releases the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to receive because it is performing some real-time function) the data line must be left HIGH by the slave. The master can then abort the transfer. A low-to-high transition on the SDA line while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be terminated by the generation of a STOP (SP) condition.

In order to read multiple bytes, it is necessary to assert the most significant bit of the subaddress field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the address of the first register to be read.

In the presented communication format MAK is Master acknowledge and NMAK is No

Master Acknowledge.

DocID027668 Rev 2 25/49

49

Digital interfaces

5.2 SPI bus interface

IIS2DH

The IIS2DH SPI is a bus slave. The SPI allows writing to and reading from the registers of the device.

The serial interface interacts with the outside world with 4 wires: CS , SPC , SDI and SDO .

Figure 6. Read and write protocol

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CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of the transmission and goes back high at the end. SPC is the serial port clock and it is controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and

SDO are respectively the serial port data input and output. These lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC .

Both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in case of multiple read/write bytes. Bit duration is the time between two falling edges of SPC . The first bit (bit 0) starts at the first falling edge of SPC after the falling edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the rising edge of CS .

bit 0 : RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is read. In the latter case, the chip will drive SDO at the start of bit 8.

bit 1 : MS bit. When 0, the address will remain unchanged in multiple read/write commands.

When 1, the address is auto incremented in multiple read/write commands.

bit 2-7 : address AD(5:0). This is the address field of the indexed register.

bit 8-15 : data DI(7:0) (write mode). This is the data that is written into the device (MSb first).

bit 8-15 : data DO(7:0) (read mode). This is the data that is read from the device (MSb first).

In multiple read/write commands further blocks of 8 clock periods will be added. When the

MS bit is ‘0’, the address used to read/write data remains the same for every block. When the MS bit is ‘1’, the address used to read/write data is increased at every block.

The function and the behavior of SDI and SDO remain unchanged.

26/49 DocID027668 Rev 2

IIS2DH Digital interfaces

Figure 7. SPI read protocol

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The SPI read command is performed with 16 clock pulses. A multiple byte read command is performed by adding blocks of 8 clock pulses to the previous one.

bit 0 : READ bit. The value is 1.

bit 1 : MS bit. When 0, does not increment the address, when 1, increments the address in multiple reads.

bit 2-7 : address AD(5:0). This is the address field of the indexed register. bit 8-15 : data DO(7:0) (read mode). This is the data that will be read from the device (MSb first).

bit 16-...

: data DO(...-8). Further data in multiple byte reads.

Figure 8. Multiple byte SPI read protocol (2-byte example)

C S

SPC

SDI

RW

M S A D5 A D4 AD 3 A D2 A D1 A D0

SD O

DO 7 DO 6 DO 5 DO 4 DO 3 DO 2 DO 1 DO 0 DO 15 DO 14 DO 13 DO 12 DO 11 DO 10 D O9 D O8

AM10131V1

DocID027668 Rev 2 27/49

49

Digital interfaces IIS2DH

Figure 9. SPI write protocol

CS

SPC

SDI

RW

MS AD5 AD 4 AD 3 AD2 AD 1 AD0

D I7 D I6 D I5 D I4 DI3 DI2 DI1 DI0

AM10132V1

The SPI write command is performed with 16 clock pulses. A multiple byte write command is performed by adding blocks of 8 clock pulses to the previous one.

bit 0 : WRITE bit. The value is 0.

bit 1 : MS bit. When 0, does not increment the address, when 1, increments the address in multiple writes.

bit 2 -7 : address AD(5:0). This is the address field of the indexed register. bit 8-15 : data DI(7:0) (write mode). This is the data that is written inside the device (MSb first).

bit 16-... : data DI(...-8). Further data in multiple byte writes.

Figure 10. Multiple byte SPI write protocol (2-byte example)

CS

SPC

SDI

RW

MS AD5 AD4 AD3 AD2 AD1 AD 0

DI7 D I6 DI5 D I4 DI3 DI2 DI1 DI0 DI15 D I1 4 DI13 D I1 2 DI11 DI10 DI9 DI8

AM10133V1

28/49 DocID027668 Rev 2

IIS2DH

5.2.3

Digital interfaces

SPI read in 3-wire mode

3-wire mode is entered by setting bit SIM (SPI serial interface mode selection) to ‘1’ in

CTRL_REG4 (23h) .

Figure 11. SPI read protocol in 3-wire mode

CS

SPC

SDI/O

RW

MS AD5 AD 4 AD 3 AD2 AD1 AD 0

D O7 D O6 D O5 DO4 DO3 DO2 DO1 DO0

AM10134V1

The SPI read command is performed with 16 clock pulses.

bit 0 : READ bit. The value is 1.

bit 1 : MS bit. When 0, does not increment the address, when 1, increments the address in multiple reads.

bit 2-7 : address AD(5:0). This is the address field of the indexed register. bit 8-15 : data DO(7:0) (read mode). This is the data that is read from the device (MSb first).

The multiple read command is also available in 3-wire mode.

DocID027668 Rev 2 29/49

49

Register mapping IIS2DH

30/49

The table given below provides a listing of the 8-bit registers embedded in the device and the corresponding addresses.

Name

Reserved

STATUS_REG_AUX

Reserved

OUT_TEMP_L

OUT_TEMP_H

INT_COUNTER_REG

WHO_AM_I

Reserved

TEMP_CFG_REG

CTRL_REG1

CTRL_REG2

CTRL_REG3

CTRL_REG4

CTRL_REG5

CTRL_REG6

REFERENCE/DATACAPTURE

STATUS_REG

OUT_X_L

OUT_X_H

OUT_Y_L

OUT_Y_H

OUT_Z_L

OUT_Z_H

FIFO_CTRL_REG

FIFO_SRC_REG

INT1_CFG

INT1_SRC

INT1_THS

INT1_DURATION r r r r r r rw r rw rw rw rw rw rw rw rw r rw r rw rw

2E

2F

30

31

32

33

2A

2B

2C

2D

26

27

28

29

10 - 1E

1F

20

21

22

23

24

25

00 - 06

07

08-0B

0C

0D

0E

0F

Table 19. Register address map

Register address

Type Default

Hex Binary r r r r r r

Comment

Reserved

000 0111

Reserved

000 1100 Output

000 1101 Output

000 1110

000 1111 00110011 Dummy register

Reserved

001 1111

010 0000 00000111

010 0001 00000000

010 0010 00000000

010 0011 00000000

010 0100 00000000

010 0101 00000000

010 0110 00000000

010 0111 00000000

010 1000 Output

010 1001 Output

010 1010 Output

010 1011 Output

010 1100 Output

010 1101 Output

010 1110 00000000

010 1111 0010000

011 0000 00000000

011 0001 00000000

011 0010 00000000

011 0011 00000000

DocID027668 Rev 2

IIS2DH Register mapping

INT2_CFG

INT2_SRC

INT2_THS

INT2_DURATION

CLICK_CFG

CLICK_SRC

CLICK_THS

TIME_LIMIT

TIME_LATENCY

TIME_WINDOW

Act_THS

Act_DUR

Name

Table 19. Register address map (continued)

Register address

Type Default

Hex Binary

37

38

39

3A

34

35

36

3B

3C

3D

3E

3F rw rw r rw rw r rw rw rw rw rw rw

011 0100 00000000

011 0101 00000000

011 0110 00000000

011 0111 00000000

011 1000 00000000

011 1001 00000000

011 1010 00000000

011 1011 00000000

011 1100 00000000

011 1101 00000000

011 1110 00000000

011 1111 00000000

Comment

Registers marked as Reserved or not listed in the table above must not be changed. Writing to those registers may cause permanent damage to the device.

The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered up.

The boot procedure is complete about 5 milliseconds after device power-up.

DocID027668 Rev 2 31/49

49

Register description IIS2DH

7.2

--

TOR

TDA

TOR --

Table 20. STATUS_REG_AUX register

--TDA

Table 21. STATUS_REG_AUX description

Temperature data overrun. Default value: 0

(0: no overrun has occurred;

1: new temperature data has overwritten the previous data)

Temperature new data available. Default value: 0

(0: new temperature data is not yet available;

1: new temperature data is available)

---

OUT_TEMP_L (0Ch), OUT_TEMP_H (0Dh)

Temperature sensor data. Refer to

Section 2.11: Temperature sensor

for details on how to enable and read the temperature sensor output data.

IC7 IC6

Table 22. INT_COUNTER_REG register

IC5 IC4 IC3 IC2 IC1 IC0

Device identification register.

0 0 1

Table 23. WHO_AM_I register

1 0 0 1 1

32/49

TEMP_EN1 TEMP_EN0

Table 24. TEMP_CFG_REG register

0 0 0 0

TEMP_EN[1:0]

Table 25. TEMP_CFG_REG description

Temperature sensor (T) enable. Default value: 00

(00: T disabled; 11: T enabled)

0 0

DocID027668 Rev 2

IIS2DH Register description

ODR3 ODR2

Table 26. CTRL_REG1 register

ODR1 ODR0 LPen Zen Yen Xen

Zen

Yen

Xen

ODR[3:0]

LPen

Table 27. CTRL_REG1 description

Data rate selection. Default value: 0000

(0000: power-down mode; others: refer to Table 28 )

Low-power mode enable. Default value: 0

(0: normal mode, 1: low-power mode)

(Refer to section

2.6.3: High-resolution, normal mode, low-power mode )

Z-axis enable. Default value: 1

(0: Z-axis disabled; 1: Z-axis enabled)

Y-axis enable. Default value: 1

(0: Y-axis disabled; 1: Y-axis enabled)

X-axis enable. Default value: 1

(0: X-axis disabled; 1: X-axis enabled)

ODR[3:0] is used to set the power mode and ODR selection. The following table indicates the frequency of each combination of ODR[3:0].

0

0

0

0

1

1

0

0

0

0

ODR3

1

1

1

1

0

0

0

0

0

0

ODR2

1

1

0

0

0

0

1

1

0

0

Table 28. Data rate configuration

ODR1 ODR0 Power mode selection

0

1

0

1

0

1

0

1

0

1

Power-down mode

HR / Normal / Low-power mode (1 Hz)

HR / Normal / Low-power mode (10 Hz)

HR / Normal / Low-power mode (25 Hz)

HR / Normal / Low-power mode (50 Hz)

HR / Normal / Low-power mode (100 Hz)

HR / Normal / Low-power mode (200 Hz)

HR/ Normal / Low-power mode (400 Hz)

Low-power mode (1.620 kHz)

HR/ Normal (1.344 kHz);

Low-power mode (5.376 kHz)

DocID027668 Rev 2 33/49

49

Register description IIS2DH

HPM1 HPM0

Table 29. CTRL_REG2 register

HPCF2 HPCF1 FDS HPCLICK HPIS2 HPIS1

HPM[1:0]

Table 30. CTRL_REG2 description

High-pass filter mode selection. Default value: 00

Refer to

Table 31

for filter mode configuration

HPCF[2:1]

High-pass filter cutoff frequency selection. Refer to Table 32 .

FDS

Filtered data selection. Default value: 0

(0: internal filter bypassed; 1: data from internal filter sent to output register and FIFO)

HPCLICK

High-pass filter enable for CLICK function.

(0: filter bypassed; 1: filter enabled)

HPIS2

HPIS1

High-pass filter enable for AOI function on Interrupt 2.

(0: filter bypassed; 1: filter enabled)

High-pass filter enable for AOI function on Interrupt 1.

(0: filter bypassed; 1: filter enabled)

0

1

HPM1

0

1

1

0

HPM0

0

1

Table 31. High-pass filter mode configuration

High-pass filter mode

Normal mode (reset by reading

REFERENCE/DATACAPTURE (26h)

register)

Reference signal for filtering

Normal mode

Autoreset on interrupt event

The bandwidth of the high-pass filter depends on the selected ODR and on the settings of the HPCFx bits of CTRL_REG2. The high-pass filter cutoff frequencies (f

Table 32

.

t

) are shown in

HPCF[2:1] f t

[Hz]

@ 1 Hz

Table 32. Low-power mode - high-pass filter cutoff frequency f t

[Hz]

@ 10 Hz f t

[Hz]

@ 25 Hz f t

[Hz]

@ 50 Hz f t

[Hz]

@ 100 Hz f t

[Hz]

@ 200Hz f t

[Hz]

@ 400 Hz f t

[Hz]

@ 1.6kHz

00

01

10

11

0.02

0.008

0.004

0.002

0.2

0.08

0.04

0.02

0.5

0.2

0.1

0.05

1

0.5

0.2

0.1

2

1

0.5

0.2

4

2

1

0.5

2

1

8

4

8

4

32

16 f t

[Hz]

@ 5kHz

100

50

25

12

34/49 DocID027668 Rev 2

IIS2DH Register description

7.8 CTRL_REG3

I1_CLICK I1_AOI1

Table 33. CTRL_REG3 register

I1_AOI2 I1_DRDY1 I1_DRDY2 I1_WTM I1_OVERRUN --

I1_CLICK

I1_AOI1

I1_AOI2

I1_DRDY1

I1_DRDY2

I1_WTM

I1_OVERRUN

Table 34. CTRL_REG3 description

CLICK interrupt on INT1 pin. Default value 0.

(0: disable; 1: enable)

AOI1 interrupt on INT1 pin. Default value 0.

(0: disable; 1: enable)

AOI2 interrupt on INT1 pin. Default value 0.

(0: disable; 1: enable)

DRDY1 interrupt on INT1 pin. Default value 0.

(0: disable; 1: enable)

DRDY2 interrupt on INT1 pin. Default value 0.

(0: disable; 1: enable)

FIFO watermark interrupt on INT1 pin. Default value 0.

(0: disable; 1: enable)

FIFO overrun interrupt on INT1 pin. Default value 0.

(0: disable; 1: enable)

BDU

BLE

FS[1:0]

HR

ST[1:0]

SIM

BDU BLE

(1)

FS1

Table 35. CTRL_REG4 register

FS0 HR

1. The BLE function can be activated only in high-resolution mode

ST1 ST0 SIM

Table 36. CTRL_REG4 description

Block data update. Default value: 0

(0: continuous update; 1: output registers not updated until MSB and LSB have been read)

Big/Little Endian data selection. Default value: 0

(0: data LSb at lower address; 1: data MSb at lower address)

The BLE function can be activated only in high-resolution mode

Full-scale selection. Default value: 00

(00: ±2 g ; 01: ±4 g ; 10: ±8 g ; 11: ±16 g )

Operating mode selection (refer to section 2.6.3: High-resolution, normal mode, low-power mode

)

Self-test enable. Default value: 00

(00: self-test disabled; other: see

Table 37 )

SPI serial interface mode selection. Default value: 0

(0: 4-wire interface; 1: 3-wire interface).

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49

Register description

1

1

0

0

ST1

0

1

0

1

Table 37. Self-test mode configuration

ST0 Self-test mode

Normal mode

Self test 0

Self test 1

--

IIS2DH

BOOT FIFO_EN --

Table 38. CTRL_REG5 register

-LIR_INT1 D4D_INT1 LIR_INT2 D4D_INT2

BOOT

FIFO_EN

LIR_INT1

D4D_INT1

LIR_INT2

D4D_INT2

Table 39. CTRL_REG5 description

Reboot memory content. Default value: 0

(0: normal mode; 1: reboot memory content)

FIFO enable. Default value: 0

(0: FIFO disabled; 1: FIFO enabled)

Latch interrupt request on INT1_SRC (31h)

, with

INT1_SRC (31h)

register cleared by reading

INT1_SRC (31h) itself. Default value: 0.

(0: interrupt request not latched; 1: interrupt request latched)

4D enable: 4D detection is enabled on INT1 pin when 6D bit on

INT1_CFG (30h) is

set to 1.

Latch interrupt request on INT2_SRC (35h)

register, with

INT2_SRC (35h) register

cleared by reading

INT2_SRC (35h) itself. Default value: 0.

(0: interrupt request not latched; 1: interrupt request latched)

4D enable: 4D detection is enabled on INT2 pin when 6D bit on

INT2_CFG (34h) is

set to 1.

36/49

Table 40. CTRL_REG6 register

I2_CLICKen I2_INT1 I2_INT2 BOOT_I2 P2_ACT - H_LACTIVE --

I2_CLICKen

I2_INT1

Table 41. CTRL_REG6 description

Click interrupt on INT2 pin. Default value: 0

(0: disabled; 1: enabled)

Interrupt 1 function enable on INT2 pin. Default value: 0

(0: function disabled; 1: function enabled)

DocID027668 Rev 2

IIS2DH

I2_INT2

BOOT_I2

P2_ACT

H_LACTIVE

Table 41. CTRL_REG6 description (continued)

Interrupt 2 function enable on INT2 pin. Default value: 0

(0: function disabled; 1: function enabled)

Boot on INT2 pin enable. Default value: 0

(0: disabled; 1:enabled)

Activity interrupt enable on INT2 pin. Default value: 0.

(0: disabled; 1:enabled)

Interrupt active. Default value: 0.

(0: interrupt active-high; 1: interrupt active-low)

Register description

Ref7

Ref [7:0]

Ref6

Table 42. REFERENCE/DATACAPTURE register

Ref5 Ref4 Ref3 Ref2 Ref1

Table 43. REFERENCE/DATACAPTURE description

Reference value for interrupt generation. Default value: 0

Ref0

ZYXOR ZOR YOR

Table 44. STATUS_REG register

XOR ZYXDA ZDA YDA XDA

Table 45. STATUS_REG description

ZYXOR X-, Y- and Z-axis data overrun. Default value: 0

(0: no overrun has occurred; 1: a new set of data has overwritten the previous set)

ZOR

YOR

Z-axis data overrun. Default value: 0

(0: no overrun has occurred; 1: new data for the Z-axis has overwritten the previous data)

Y-axis data overrun. Default value: 0

(0: no overrun has occurred;

1: new data for the Y-axis has overwritten the previous data)

XOR X-axis data overrun. Default value: 0

(0: no overrun has occurred;

1: new data for the X-axis has overwritten the previous data)

ZYXDA X-, Y- and Z-axis new data available. Default value: 0

(0: a new set of data is not yet available; 1: a new set of data is available)

ZDA Z-axis new data available. Default value: 0

(0: new data for the Z-axis is not yet available;

1: new data for the Z-axis is available)

YDA Y-axis new data available. Default value: 0

(0: new data for the Y-axis is not yet available;

1: new data for the Y-axis is available)

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49

Register description

7.14 OUT_X_L (28h), OUT_X_H (29h)

X-axis acceleration data. The value is expressed as two’s complement left-justified.

Please refer to

Section 2.6.3: High-resolution, normal mode, low-power mode .

IIS2DH

7.15 OUT_Y_L (2Ah), OUT_Y_H (2Bh)

Y-axis acceleration data. The value is expressed as two’s complement left-justified.

Please refer to

Section 2.6.3: High-resolution, normal mode, low-power mode .

7.16 OUT_Z_L (2Ch), OUT_Z_H (2Dh)

Z-axis acceleration data. The value is expressed as two’s complement left-justified.

Please refer to

Section 2.6.3: High-resolution, normal mode, low-power mode .

FM1

0

0

1

1

FM[1:0]

TR

FTH[4:0]

Table 47. FIFO_CTRL_REG description

FIFO mode selection. Default value: 00 (see

Table 48 )

Trigger selection. Default value: 0

0: trigger event allows triggering signal on INT1

1: trigger event allows triggering signal on INT2

Default value: 00000

FM1

FM0 TR

Table 46. FIFO_CTRL_REG register

FTH4 FTH3 FTH2

0

1

0

1

Table 48. FIFO mode configuration

FM0 FIFO mode

Bypass mode

FIFO mode

Stream mode

Stream-to-FIFO mode

FTH1 FTH0

38/49

WTM OVRN_FIFO

Table 49. FIFO_SRC_REG register

EMPTY FSS4 FSS3 FSS2 FSS1 FSS0

DocID027668 Rev 2

IIS2DH Register description

WTM

OVRN_FIFO

EMPTY

FSS [4:0]

Table 50. FIFO_SRC_REG description

WTM bit is set high when FIFO content exceeds watermark level.

OVRN bit is set high when FIFO buffer is full; this means that the FIFO buffer contains 32 unread samples. At the following ODR a new sample set replaces the oldest FIFO value. The OVRN bit is set to 0 when the first sample set has been read.

EMPTY flag is set high when all FIFO samples have been read and FIFO is empty.

FSS [4:0] field always contains the current number of unread samples stored in the

FIFO buffer. When FIFO is enabled, this value increases at ODR frequency until the buffer is full, whereas, it decreases every time one sample set is retrieved from

FIFO.

AOI 6D ZHIE/

ZUPE

Table 51. INT1_CFG register

ZLIE/

ZDOWNE

YHIE/

YUPE

YLIE/

YDOWNE

XHIE/

XUPE

XLIE/

XDOWNE

AOI

6D

ZHIE/

ZUPE

ZLIE/

ZDOWNE

YHIE/

YUPE

YLIE/

YDOWNE

Table 52. INT1_CFG description

And/Or combination of interrupt events. Default value: 0. Refer to

Table 53

6-direction detection function enabled. Default value: 0. Refer to

Table 53

Enable interrupt generation on Z high event or on direction recognition. Default value: 0

(0: disable interrupt request;1: enable interrupt request)

Enable interrupt generation on Z low event or on direction recognition. Default value: 0

(0: disable interrupt request;1: enable interrupt request)

Enable interrupt generation on Y high event or on direction recognition. Default value: 0

(0: disable interrupt request; 1: enable interrupt request.)

Enable interrupt generation on Y low event or on direction recognition. Default value: 0

(0: disable interrupt request; 1: enable interrupt request.)

XHIE/

XUPE

XLIE/

XDOWNE

Enable interrupt generation on X high event or on direction recognition. Default value: 0

(0: disable interrupt request; 1: enable interrupt request.)

Enable interrupt generation on X low event or on direction recognition. Default value: 0

(0: disable interrupt request; 1: enable interrupt request.)

The content of this register is loaded at boot.

A write operation to this address is possible only after system boot.

AOI

1

1

0

0

6D

0

1

0

1

Table 53. Interrupt mode

Interrupt mode

OR combination of interrupt events

6-direction movement recognition

AND combination of interrupt events

6-direction position recognition

DocID027668 Rev 2 39/49

49

Register description IIS2DH

The difference between AOI-6D = ‘01’ and AOI-6D = ‘11’.

AOI-6D = ‘01’ is movement recognition. An interrupt is generated when the orientation moves from an unknown zone to a known zone. The interrupt signal remains for a duration

ODR.

AOI-6D = ‘11’ is direction recognition. An interrupt is generated when the orientation is inside a known zone. The interrupt signal remains while the orientation is inside the zone.

0 IA ZH

Table 54. INT1_SRC register

ZL YH YL XH XL

YL

XH

XL

ZL

YH

IA

ZH

Table 55. INT1_SRC description

Interrupt active. Default value: 0

(0: no interrupt has been generated; 1: one or more interrupts have been generated)

Z high. Default value: 0

(0: no interrupt, 1: Z high event has occurred)

Z low. Default value: 0

(0: no interrupt; 1: Z low event has occurred)

Y high. Default value: 0

(0: no interrupt, 1: Y high event has occurred)

Y low. Default value: 0

(0: no interrupt, 1: Y low event has occurred)

X high. Default value: 0

(0: no interrupt, 1: X high event has occurred)

X low. Default value: 0

(0: no interrupt, 1: X low event has occurred)

Interrupt 1 source register. Read-only register.

Reading at this address clears the

INT1_SRC (31h)

IA bit (and the interrupt signal on the

INT1 pin) and allows the refresh of data in the

INT1_SRC (31h) register if the latched option

was chosen.

0 THS6 THS5

Table 56. INT1_THS register

THS4 THS3 THS2 THS1 THS0

40/49 DocID027668 Rev 2

IIS2DH

THS[6:0]

Table 57. INT1_THS description

Interrupt 1 threshold. Default value: 000 0000

1 LSb = 16 m g @ FS = 2 g

1 LSb = 32 m g @ FS = 4 g

1 LSb = 62 m g @ FS = 8 g

1 LSb = 186 m g @ FS = 16 g

Register description

0 D6

Table 58. INT1_DURATION register

D5 D4 D3 D2 D1 D0

D[6:0]

Table 59. INT1_DURATION description

Duration value. Default value: 000 0000

1 LSb = 1/ODR

The D[6:0] bits set the minimum duration of the interrupt 1 event to be recognized. Duration steps and maximum values depend on the ODR chosen.

Duration time is measured in N/ODR, where N is the content of the duration register.

AOI

6D

ZHIE

ZLIE

YHIE

AOI 6D ZHIE

Table 60. INT2_CFG register

ZLIE YHIE YLIE XHIE XLIE

Table 61. INT2_CFG description

AND/OR combination of interrupt events. Default value: 0

(see Table 62

)

6-direction detection function enabled. Default value: 0. Refer to

Table 62.

Enable interrupt generation on Z high event. Default value: 0

(0: disable interrupt request;

1: enable interrupt request on measured accel. value higher than preset threshold)

Enable interrupt generation on Z low event. Default value: 0

(0: disable interrupt request;

1: enable interrupt request on measured accel. value lower than preset threshold)

Enable interrupt generation on Y high event. Default value: 0

(0: disable interrupt request;

1: enable interrupt request on measured accel. value higher than preset threshold)

DocID027668 Rev 2 41/49

49

Register description

YLIE

XHIE

XLIE

IIS2DH

Table 61. INT2_CFG description (continued)

Enable interrupt generation on Y low event. Default value: 0

(0: disable interrupt request;

1: enable interrupt request on measured accel. value lower than preset threshold)

Enable interrupt generation on X high event. Default value: 0

(0: disable interrupt request;

1: enable interrupt request on measured accel. value higher than preset threshold)

Enable interrupt generation on X low event. Default value: 0

(0: disable interrupt request;

1: enable interrupt request on measured accel. value lower than preset threshold)

The content of this register is loaded at boot.

A write operation to this address is possible only after system boot.

AOI

1

1

0

0

6D

0

1

0

1

Table 62. Interrupt mode

Interrupt mode

OR combination of interrupt events

6-direction movement recognition

AND combination of interrupt events

6-direction position recognition

The difference between AOI-6D = ‘01’ and AOI-6D = ‘11’.

AOI-6D = ‘01’ is movement recognition. An interrupt is generated when the orientation moves from an unknown zone to a known zone. The interrupt signal remains for a duration

ODR.

AOI-6D = ‘11’ is direction recognition. An interrupt is generated when the orientation is inside a known zone. The interrupt signal remains while the orientation is inside the zone.

42/49

IA

ZH

ZL

YH

0 IA ZH

Table 63. INT2_SRC register

ZL YH YL XH XL

Table 64. INT2_SRC description

Interrupt active. Default value: 0

(0: no interrupt has been generated; 1: one or more interrupts have been generated)

Z high. Default value: 0

(0: no interrupt, 1: Z high event has occurred)

Z low. Default value: 0

(0: no interrupt; 1: Z low event has occurred)

Y high. Default value: 0

(0: no interrupt, 1: Y high event has occurred)

DocID027668 Rev 2

IIS2DH

YL

XH

XL

Table 64. INT2_SRC description (continued)

Y low. Default value: 0

(0: no interrupt, 1: Y low event has occurred)

X high. Default value: 0

(0: no interrupt, 1: X high event has occurred)

X low. Default value: 0

(0: no interrupt, 1: X low event has occurred)

Register description

Interrupt 2 source register. Read-only register.

Reading at this address clears the

INT2_SRC (35h)

IA bit (and the interrupt signal on the

INT2 pin) and allows the refresh of data in the

INT2_SRC (35h) register if the latched option

was chosen.

0

THS[6:0]

THS6 THS5

Table 65. INT2_THS register

THS4 THS3 THS2

Table 66. INT2_THS description

Interrupt 2 threshold. Default value: 000 0000

1 LSb = 16 m g @ FS = 2 g

1 LSb = 32 m g @ FS = 4 g

1 LSb = 62 m g @ FS = 8 g

1 LSb = 186 m g @ FS = 16 g

THS1 THS0

0 D6

Table 67. INT2_DURATION register

D5 D4 D3 D2 D1 D0

D[6:0]

Table 68. INT2_DURATION description

Duration value. Default value: 000 0000

1 LSb = 1/ODR

(1)

1. Duration time is measured in N/ODR, where N is the content of the duration register.

The D[6:0] bits set the minimum duration of the Interrupt 2 event to be recognized. Duration time steps and maximum values depend on the ODR chosen.

--ZD

Table 69. CLICK_CFG register

ZS YD YS

DocID027668 Rev 2

XD XS

43/49

49

Register description

ZD

YS

XD

ZS

YD

XS

IIS2DH

Table 70. CLICK_CFG description

Enable interrupt double-click on Z-axis. Default value: 0

(0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold)

Enable interrupt single-click on Z-axis. Default value: 0

(0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold)

Enable interrupt double-click on Y-axis. Default value: 0

(0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold)

Enable interrupt single-click on Y-axis. Default value: 0

(0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold)

Enable interrupt double-click on X-axis. Default value: 0

(0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold)

Enable interrupt single-click on X-axis. Default value: 0

(0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold)

IA DClick

Table 71. CLICK_SRC register

SClick Sign Z Y X

Y

X

IA

DClick

SClick

Sign

Z

Table 72. CLICK_SRC description

Interrupt active. Default value: 0

(0: no interrupt has been generated; 1: one or more interrupts have been generated)

Double-click enable. Default value: 0 (0: double-click detection disabled,

1: double-click detection enabled)

Single-click enable. Default value: 0 (0: single-click detection disabled, 1: single-click detection enabled)

Click sign. 0: positive detection, 1: negative detection

Z click detection. Default value: 0

(0: no interrupt, 1: Z high event has occurred)

Y click detection. Default value: 0

(0: no interrupt, 1: Y high event has occurred)

X click detection. Default value: 0

(0: no interrupt, 1: X high event has occurred)

44/49 DocID027668 Rev 2

IIS2DH Register description

-

Ths[6:0]

Ths6 Ths5

Table 73. CLICK_THS register

Ths4 Ths3 Ths2

Table 74. CLICK_SRC description

Click threshold. Default value: 000 0000

Ths1 Ths0

-

TLI[6:0]

TLI6 TLI5

Table 75. TIME_LIMIT register

TLI4 TLI3 TLI2 TLI1 TLI0

Table 76. TIME_LIMIT description

Click time limit. Default value: 000 0000

TLA7 TLA6 TLA5

Table 77. TIME_LATENCY register

TLA4 TLA3 TLA2 TLA1 TLA0

TLA[7:0]

Table 78. TIME_LATENCY description

Click time latency. Default value: 0000 0000

TW7 TW6 TW5

Table 79. TIME_WINDOW register

TW4 TW3 TW2 TW1 TW0

TW[7:0]

Table 80. TIME_WINDOW description

Click time window

DocID027668 Rev 2 45/49

49

Register description IIS2DH

--

Acth[6:0]

Acth6 Acth5

Table 81. Act_THS register

Acth4 Acth3 Acth2 Acth1 Acth0

Table 82. Act_THS description

Sleep-to-wake, return-to-sleep activation threshold in low-power mode

1 LSb = 16 m g @ FS = 2 g

1 LSb = 32 m g @ FS = 4 g

1 LSb = 62 m g @ FS = 8 g

1 LSb = 186 m g @ FS = 16 g

ActD7 ActD6 ActD5

Table 83. Act_DUR register

ActD4 ActD3 ActD2 ActD1 ActD0

ActD[7:0]

Table 84. Act_DUR description

Sleep-to-wake, return-to-sleep duration

1 LSb = (8*1[LSb]+1)/ODR

46/49 DocID027668 Rev 2

IIS2DH Package information

8.1

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com

.

ECOPACK ® is an ST trademark.

LGA package information

Figure 12. LGA-12 package outline and mechanical data

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Revision history

Date

24-Mar-2015

21-Apr-2015

Revision

Table 85. Document revision history

Changes

1

2

Initial release

First public release

IIS2DH

48/49 DocID027668 Rev 2

IIS2DH

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© 2015 STMicroelectronics – All rights reserved

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