STMicroelectronics ISM303DAC Datasheet

FIFO_SAMPLES_A (30h) (Diff[8:0]) is greater than or equal to FTH

(FIFO_FTH) goes to '1' when the number of unread samples

FIFO_SRC_A (2Fh) and

[7:0] in

FIFO_THS_A (2Eh) .

If FTH [7:0] is equal to '0', FIFO_SRC_A (2Fh)

(FIFO_FTH) goes to '0'.

(FIFO_OVRN) is equal to '1' if a FIFO slot is overwritten.

FIFO_SAMPLES_A (30h) (Diff[8:0]) contain stored data levels of

and

unread samples. When Diff[8:0] is equal to '000000000', FIFO is empty. When Diff[8:0] is equal to '100000000', FIFO is full and the unread samples are 256.

To guarantee the correct acquisition of data during the switching into and out of FIFO mode, the first sample acquired must be discarded.

When the FIFO threshold status flag is '0'-logic, FIFO filling is lower than the threshold level and when '1'-logic, FIFO filling is equal to or higher than the threshold level.

In Bypass mode ( FIFO_CTRL_A (25h) (FMODE [2:0])= 000), the FIFO is not operational, no

data is collected in FIFO memory, and it remains empty with the only actual sample available in the output registers.

Bypass mode is also used to reset the FIFO when in FIFO mode.

For each channel only the first address is used. When new data is available, the old data is overwritten.

36/80 DocID030988 Rev 2

ISM303DAC Functionality

In FIFO mode (

FIFO_CTRL_A (25h) (FMODE [2:0])= 001) data from the X, Y and Z

channels are stored in the FIFO until it is full, when 256 unread samples are stored in memory, data collecting is stopped.

To reset the FIFO content, Bypass mode should be written in the

restart FIFO mode, writing the value '001' in FIFO_CTRL_A (25h) (FMODE [2:0]).

The FIFO buffer can memorize 256 slots of X, Y and Z data.

Continuous mode ( FIFO_CTRL_A (25h) (FMODE[2:0] = 110) provides a continuous FIFO

update: when 256 unread samples are stored in memory, as new data arrives the oldest data is discarded and overwritten by the newer.

A FIFO threshold flag

FIFO_THS_A (2Eh) (FTH[7:0]).

(FIFO_FTH) is asserted when the number of unread samples in FIFO is greater than or equal to

It is possible to route

(FTH) to the INT1 pin by writing the INT1_FTH bit to '1' in register

CTRL4_A (23h)

or to the INT2 pin by writing the INT2_FTH bit to '1' in

register CTRL5_A (24h)

If an overrun occurs, the oldest sample in FIFO is overwritten and the FIFO_OVR flag in

FIFO_SAMPLES_A (30h) (Diff[8:0]).

is asserted.

In order to empty the FIFO before it is full, it is also possible to pull from FIFO the number of unread samples available in

FIFO_SRC_A (2Fh) and

In Continuous-to-FIFO mode FIFO_CTRL_A (25h) (FMODE [2:0] = 011), FIFO operates in

Continuous mode and FIFO mode starts upon an internal trigger event. When the FIFO is full, data collecting is stopped.

Figure 10. Continuous-to-FIFO mode x i

,y i

,z i x i

,y i

,z i x

0 x

1 x

2 y

0 y

1 y

2 z

0 z

1 z

2 x

0 x

1 x

2 y

0 y

1 y

2 z

0 z

1 z

2 x

30 x

31 y

30 y

31 z

30 z

31 x

31 y

31 z

Continuous Mode

Trigger event

FIFO Mode

DocID030988 Rev 2 37/80

Functionality

Figure 11. Trigger event to FIFO for Continuous-to-FIFO mode

ISM303DAC

38/80 DocID030988 Rev 2

ISM303DAC Functionality

In Bypass-to-Continuous mode ( FIFO_CTRL_A (25h)

(FMODE[2:0] = '100'), data measurement storage inside FIFO starts in Continuous mode upon an internal trigger event, then the sample that follows the trigger is available in FIFO.

Figure 12. Bypass-to-Continuous mode x i

,y i

,z i empty x

0 x

1 x

2 i 0 y

1 y

2 z

0 z

1 z

2 x i

,y i

,z i x

0 x

1 x

2 y

0 y

1 y

2 z

0 z

1 z

2 x

30 x

31 y

30 y

31 z

30 z

31 x

31 y

31 z

Bypass Mode Continuous Mode

Trigger event

Figure 13. Trigger event to FIFO for Bypass-to-Continuous mode

DocID030988 Rev 2 39/80

Functionality ISM303DAC

4.4.6 Module-to-FIFO

When the MODULE_TO_FIFO bit in the

Figure 14 , so a row of FIFO is written every 3 axes data ready.

register is set to '1', the 14-bit magnitude of the vector of the current axes is sent as FIFO input instead of axes data. X-, Y- and Z-axis data are replaced with 3 times the adjacent data generated by the module routine, as shown in

The module routine must be previously enabled by writing to the FUNC_CTRL_A (3Fh)

The module data in FIFO can be read as output data in the registers 28h-2Dh.

The ISM303DAC calculates the vector sum of the acceleration of the X-, Y-, Z-axis using the following formula: module (14-bit) = Sqrt(x

)

The implementation is based on an approximation of this formula (error below noise level).

As shown in Figure 14

, when module-to-FIFO is enabled, each row of FIFO contains 3 values of the module, related to 3 consecutive ODR.

Figure 14. Module-to-FIFO mode example

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The IC interface is factory calibrated for sensitivity (LA_So, M_GN), Zerog level (LA_TyOff) and Zerogauss level (M_TyOff).

The trim values are stored inside the device in nonvolatile memory. Anytime the device is turned on, the trim parameters are downloaded into the registers to be used during active operation. This allows using the device without further calibration.

40/80 DocID030988 Rev 2

ISM303DAC Application hints

Figure 15. ISM303DAC electrical connections

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The device core is supplied through the Vdd line while the I/O pads are supplied through the

Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 μ F aluminum) should be placed as near as possible to pin 9 of the device (common design practice).

It is possible to remove Vdd, maintaining Vdd_IO, without blocking the communication bus, in this condition the measurement chain is powered off.

The following recommendations apply to capacitor C1:

 It must be connected as close as possible to pins 5 and 6 since very high current pulses flow from C1 to pin 5 and 6. This avoid problems caused by inductive effects due to the length of the copper strips.

 It is highly recommended to use low ESR (max 200 mOhm)

The functionality of the device and the measured acceleration data are selectable and accessible through the I 2 C or SPI interfaces. When using the I 2 C, CS must be tied high (i.e. connected to Vdd_IO).

The functions, the threshold and the timing of the three interrupt pins (INT1_XL, INT2_XL, and INT_MAG/DRDY) can be completely programmed by the user through the I 2 C/SPI interface.

DocID030988 Rev 2 41/80

Application hints ISM303DAC

Pin#

Name

Table 19. Pin status

Function Status

SCL

SPC

Reserved

SDA

SDI

SDO

C serial clock (SCL)

SPI serial port clock (SPC)

C/SPI mode selection

(1: SPI idle mode / I

C communication enabled;

0: SPI communication mode / I

C disabled)

Default: input without pull-up

Reserved, connected to GND

C serial data (SDA)

SPI serial data input (SDI)

3-wire interface serial data output (SDO)

Default: (SDA) input without pull-up

Capacitor connection (C1 = 220 nF)

External cap, voltage forced by the device

0 V GND

INT_MAG/DRDY Magnetometer interrupt/data-ready signal

GND 0 V

Default: output high impedance

Vdd

Vdd_IO

INT2_XL

INT1_XL

Power supply

Power supply for I/O pins

Accelerometer interrupt 2

Accelerometer interrupt 1

Default: output forced to ground

Note: In order to program INT_MAG/DRDY as a push-pull output, write the INT_MAG bit to 1 in

CFG_REG_C_M (62h) .

5.2

The LGA package is compliant with the ECOPACK

, RoHS and “Green” standards.

It is qualified for soldering heat resistance according to JEDEC J-STD-020.

Land pattern and soldering recommendations are available at www.st.com

High-current wiring effects

High current in wiring and printed circuit traces can be culprits in causing errors in magnetic field measurements for compassing.

Conductor-generated magnetic fields will add to the Earth’s magnetic field, leading to errors in compass heading computation.

Keep currents higher than 10 mA a few millimeters away from the sensor IC.

42/80 DocID030988 Rev 2

ISM303DAC Digital interfaces

The registers embedded inside the ISM303DAC may be accessed through both the I 2 C and

SPI serial interfaces. The latter may be SW-configured to operate in 3-wire interface mode.

The serial interfaces are mapped to the same pins. To select/exploit the I 2 C interface, the

CS line must be tied high (i.e. connected to Vdd_IO).

Pin name

SCL

SPC

SDA

SDI

SDO

Table 20. Serial interface pin description

Pin description

SPI enable

C/SPI mode selection (1: SPI idle mode / I

C communication enabled; 0: SPI communication mode / I

C disabled)

C serial clock (SCL)

SPI serial port clock (SPC)

C serial data (SDA)

SPI serial data input (SDI)

3-wire interface serial data output (SDO)

6.1 I

2

C serial interface

The ISM303DAC I

C is a bus slave. The I

C is employed to write data into registers whose content can also be read back.

The relevant I

C terminology is given in the table below.

Term

Transmitter

Receiver

Master

Slave

Table 21. I

C terminology

Description

The device which sends data to the bus

The device which receives data from the bus

The device which initiates a transfer, generates clock signals and terminates a transfer

The device addressed by the master

There are two signals associated with the I 2 C bus: the serial clock line (SCL) and the serial data line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both the lines must be connected to Vdd_IO through an external pullup resistor. When the bus is free, both the lines are high.

The I 2 C interface is compliant with fast mode (400 kHz) I 2 C standards as well as with the normal mode.

DocID030988 Rev 2 43/80

Digital interfaces ISM303DAC

6.1.1 I

C operation

The transaction on the bus is started through a START (ST) signal. A START condition is defined as a high-to-low transition on the data line while the SCL line is held high. After this has been transmitted by the master, the bus is considered busy. The next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the master.

Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line LOW so that it remains stable low during the high period of the acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each byte of data received.

The I 2 C embedded inside the magnetometer block of the ISM303DAC behaves like a slave device and the following protocol must be adhered to. After the start condition (ST) a slave address is sent, once a slave acknowledge (SAK) has been returned, an 8-bit sub-address

(SUB) is transmitted: the 7 LSb represent the actual register address.

The I 2 C embedded inside the accelerometer block of the ISM303DAC behaves like a slave device and the following protocol must be adhered to. After the start condition (ST) a slave address is sent. Once a slave acknowledge (SAK) has been returned, an 8-bit sub-address

(SUB) is transmitted: the 7 LSb represent the actual register address while the IF_ADD_INC bit in

CTRL2_A (21h) defines the increase in the address.

The slave address is completed with a Read/Write bit. If the bit was ‘1’ (Read), a repeated

START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (Write) the master will transmit to the slave with direction unchanged.

Table 26 explains how the

SAD+read/write bit pattern is composed, listing all the possible configurations.

Master

Slave

Table 22. Transfer when master is writing one byte to slave

SAD + W SUB DATA

SAK SAK SAK

Master

Slave

Table 23. Transfer when master is writing multiple bytes to slave

SAD + W SUB DATA DATA

SAK SAK SAK SAK

Master

Table 24. Transfer when master is receiving (reading) one byte of data from slave

ST SAD + W SUB SR SAD + R NMAK

Slave SAK SAK SAK DATA

44/80 DocID030988 Rev 2

ISM303DAC Digital interfaces

Table 25. Transfer when master is receiving (reading) multiple bytes of data from slave

Master ST SAD+W SUB SR SAD+R MAK MAK NMAK SP

Slave SAK SAK SAK DATA

DAT

DATA

Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit

(MSb) first. If a receiver can’t receive another complete byte of data until it has performed some other function, it can hold the clock line SCL low to force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and releases the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to receive because it is performing some real-time function) the data line must be left high by the slave. The master can then abort the transfer. A low-to-high transition on the SDA line while the SCL line is high is defined as a STOP condition. Each data transfer must be terminated by the generation of a STOP (SP) condition.

In the presented communication format MAK is Master acknowledge and NMAK is No

Master Acknowledge.

Default address:

The accelerometer sensor slave address is 0011101b while magnetic sensor slave address is 0011110b.

The slave addresses are completed with a Read/Write bit. If the bit was ‘1’ (Read), a repeated START (SR) condition must be issued after the two sub-address bytes. If the bit is

‘0’ (Write) the master will transmit to the slave with direction unchanged. Table 26

and

Table 27

explain how the SAD+Read/Write bit patterns are composed, listing all the possible configurations.

Linear acceleration sensor: the default (factory setting) 7-bit slave address is

0011101b.

Command

Read

Write

Table 26. SAD+Read/Write patterns

SAD[6:0] R/W

0011101

SAD+R/W

00111 011

00111 010

Magnetic field sensor: the default (factory setting) 7-bit slave address is 0011110b.

Command

Read

Write

Table 27. SAD + Read/Write patterns

SAD[6:0]

0011110

R/W

SAD + R/W

00111101 (3Dh)

00111100 (3Ch)

DocID030988 Rev 2 45/80

Digital interfaces

6.2 SPI bus interface

ISM303DAC

The ISM303DAC SPI is a bus slave. The SPI allows writing to and reading from the registers of the device.

The serial interface interacts with the application using 3 wires: CS , SPC , SDI and SDO

(refer to

Table 20 ).

Figure 16. Read and write protocol

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CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of the transmission and goes back high at the end. SPC is the serial port clock and it is controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and

SDO are respectively the serial port data input and output. Those lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC .

Both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in case of multiple read/write bytes. Bit duration is the time between two falling edges of SPC . The first bit (bit 0) starts at the first falling edge of SPC after the falling edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the rising edge of CS .

bit 0 : RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is read. In latter case, the chip will drive SDO at the start of bit 8.

bit 1-7 : address AD(6:0). This is the address field of the indexed register.

bit 8-15 : data DI(7:0) (write mode). This is the data that is written into the device (MSb first).

bit 8-15 : data DO(7:0) (read mode). This is the data that is read from the device (MSb first).

In multiple read/write commands additional blocks of 8 clock periods will be added. For the accelerometer when the

CTRL2_A (21h) (IF_ADD_INC) bit is ‘0’, the address used to read/write data remains the same for every block. When the CTRL2_A (21h)

(IF_ADD_INC) bit is ‘1’, the address used to read/write data is increased at every block.

The function and the behavior of SDI and SDO remain unchanged.

46/80 DocID030988 Rev 2

ISM303DAC

6.2.1 Accelerometer SPI write

Figure 17. Accelerometer SPI write protocol

Digital interfaces

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The SPI write command is performed with 16 clock pulses. A multiple byte write command is performed by adding blocks of 8 clock pulses to the previous one.

bit 0 : WRITE bit. The value is 0.

bit 1 -7 : address AD(6:0). This is the address field of the indexed register.

bit 8-15 : data DI(7:0) (write mode). This is the data that is written inside the device (MSb first).

bit 16-... : data DI(...-8). Additional data in multiple byte writes.

The accelerometer address auto increment is enabled by default (volatile bit IF_ADD_INC in

CTRL2_A (21h)

must be set to ‘0’ to disable).

Figure 18. Accelerometer multiple byte SPI write protocol (2-byte example)

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DocID030988 Rev 2 47/80

Digital interfaces

6.2.2 Accelerometer SPI read in 3-wire mode

ISM303DAC

3-wire mode is entered by setting the

CTRL2_A (21h) (SPI_ENABLE) bit equal to ‘1’ (SPI

serial interface read enable).

Figure 19. Accelerometer SPI read protocol in 3-wire mode

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The SPI read command is performed with 16 clock pulses: bit 0 : READ bit. The value is 1.

bit 1-7 : address AD(6:0). This is the address field of the indexed register. bit 8-15 : data DO(7:0) (read mode). This is the data that is read from the device (MSb first).

A multiple read command is also available in 3-wire mode.

The accelerometer address auto increment is enabled by default (volatile bit IF_ADD_INC in

CTRL2_A (21h)

must be set to ‘0’ to disable).

48/80 DocID030988 Rev 2

ISM303DAC

6.2.3 Magnetometer SPI write

Figure 20. Magnetometer SPI write protocol

Digital interfaces

SPC

SDI

SPC

SDI

AD6 AD5 AD 4 AD 3 AD2 AD 1 AD0

D I7 D I6 D I5 D I4 DI3 DI2 DI1 DI0

The SPI write command is performed with 16 clock pulses. The multiple byte write command is performed by adding blocks of 8 clock pulses to the previous one.

bit 0 : WRITE bit. The value is 0.

bit 1-7 : address AD(6:0). This is the address field of the indexed register. bit 8-15 : data DI(7:0) (write mode). This is the data that is written inside the device (MSb first).

bit 16-... : data DI(...-8). Further data in multiple byte writes.

Figure 21. Magnetometer multiple byte SPI write protocol (2-byte example)

AD6 AD5 AD4 AD3 AD2 AD1 AD 0

DI7 D I6 DI5 D I4 DI3 DI2 DI1 DI0 DI15 D I1 4 DI13 D I1 2 DI11 DI10 DI9 DI8

DocID030988 Rev 2 49/80

Digital interfaces ISM303DAC

6.2.4

CS

Magnetometer SPI write in 3-wire mode

Figure 22. Magnetometer SPI read protocol in 3-wire mode

SPC

SDI/O

AD6 AD5 AD 4 AD 3 AD2 AD1 AD 0

D O7 D O6 D O5 DO4 DO3 DO2 DO1 DO0

The SPI read command is performed with 16 clock pulses: bit 0 : WRITE bit. The value is 0.

bit 1-7 : address AD(6:0). This is the address field of the indexed register. bit 8-15 : data DO(7:0) (read mode). This is the data that is read from the device (MSb first).

The multiple read command is available in 3-wire mode.

50/80 DocID030988 Rev 2

ISM303DAC Register mapping

RESERVED

Module_8bit_A

RESERVED

WHO_AM_I_A

RESERVED

CTRL1_A

CTRL2_A

CTRL3_A

CTRL4_A

CTRL5_A

FIFO_CTRL_A

OUT_T_A

STATUS_A

OUT_X_L_A

OUT_X_H_A

OUT_Y_L_A

OUT_Y_H_A

OUT_Z_L_A

OUT_Z_H_A

FIFO_THS_A

FIFO_SRC_A

FIFO_SAMPLES_A

The table given below provides a list of the 8-bit registers embedded in the device and the corresponding addresses. Registers 00h through 3Fh are dedicated to the accelerometer while registers 40h through 6Fh are dedicated to the magnetometer.

Name Type

(1)

Table 28. Register map

Register address

Hex Binary

R/W

00001100

00001111

00-0B

0D-0E

10-1F

00100000

00100001

00100010

00100011

00100100

00100101

00100110

00100111

00101000

00101001

00101010

00101011

00101100

00101101

00101110

00101111

Default

output

01000011

00000000

00000100

00000000

00000000 output output output

00000000 output

Comment

RESERVED

Who I am ID

RESERVED

Control registers

FIFO control reg

Temp sensor output

Status data register

Output registers

TAP_6D_THS_A R/W

INT_DUR_A R/W

WAKE_UP_THS_A

R/W

00110000

00110001

00110010

00110011

00000000

FIFO registers

FIFO SRC

Unread samples stored in FIFO

TAP, 4D, 6D threshold

Interrupt duration

TAP/D-TAP selection, Inactivity

EN,

Wakeup threshold

DocID030988 Rev 2 51/80

Register mapping ISM303DAC

Name

Table 28. Register map (continued)

Register address

Type

(1)

Default

Hex Binary

WAKE_UP_DUR_A

FREE_FALL_A

STATUS_DUP_A

WAKE_UP_SRC_A

TAP_SRC_A

6D_SRC_A

RESERVED

FUNC_CTRL_A R/W

RESERVED

OFFSET_X_REG_L_M R/W

OFFSET_X_REG_H_M R/W

OFFSET_Y_REG_L_M R/W

OFFSET_Y_REG_H_M R/W

OFFSET_Z_REG_L_M R/W

OFFSET_Z_REG_H_M R/W

R/W

RESERVED

WHO_AM_I_M

RESERVED

CFG_REG_A_M

CFG_REG_B_M

CFG_REG_C_M

INT_CRTL_REG_M

INT_SOURCE_REG_M

INT_THS_L_REG_M

INT_THS_H_REG_M

STATUS_REG_M

OUTX_L_REG_M

OUTX_H_REG_M

OUTY_L_REG_M

OUTY_H_REG_M

OUTZ_L_REG_M

OUTZ_H_REG_M

RESERVED

R/W

1. R = read-only register, RW = readable/writable register

6E-6F

4B-4C

50-5F

40-44

3A-3E

00110100

00110101

00110110

00110111

00111000

00111001

00000100

01000101

01000110

01000111

01001000

01001001

01001010

01001111

00000000

00000000 output output output output

00000000

01000000

01100000

01100011

01100100

00000011

01100001 00000000

01100010 00000000

11100000

01100101

01100110

01100111

01101000

00000000

01101001

01101010

01101100

01101101 output output output output output output

Comment

Wakeup duration

Free-fall config.

Status register

Wakeup SRC

TAP SRC

6D SRC

Magnetometer hard-iron registers

Who I am ID

Magnetometer configuration registers

Magnetometer interrupt configuration registers

Magnetometer output registers

52/80 DocID030988 Rev 2

ISM303DAC Register mapping

Registers marked as Reserved must not be changed. Writing to those registers may cause permanent damage to the device.

The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered up.

DocID030988 Rev 2 53/80

Register description ISM303DAC

Module out value (r). This register is a read-only register.

Table 29. Module_8bit_A register

Module_7 Module_6 Module_5 Module_4 Module_3 Module_2 Module_1 Module_0

Table 30. Module_8bit_A register description

Module [7:0] Module output value (8-bit). Default value: 0

Who_AM_I register (r). This register is a read-only register. Its value is fixed at 43h.

0 1

Table 31. WHO_AM_I_A register default values

0 0 0 0 1 1

54/80

Control register 1 (r/w)

ODR3 ODR2 ODR1

Table 32. CTRL1_A register

ODR0 FS1 FS0 HF_ODR BDU

ODR [3:0]

FS [1:0]

HF_ODR

BDU

Table 33. CTRL1_A register description

Output data rate & power mode selection . Default value: 0000 (see

Table 34 )

Full-scale selection. Default value: 00 (00: ±2 g ; 01: ±16 g ; 10: ±4 g ; 11: ±8 g )

High-frequency ODR mode enable. Default value: 0

Block data update. Default value: 0

(0: continuous update; 1: output registers not updated until MSB and LSB read)

ODR [3:0] is used to set the power mode and ODR selection. The following table lists the bit settings for power-down mode and each available frequency.

Table 34. ODR register setting: power down (PD) and low power (LP)

ODR[3:0] HF_ODR ODR selection [Hz] Bit resolution Mode

0000

1000

1001

1010

12.5

DocID030988 Rev 2

ISM303DAC Register description

Table 34. ODR register setting: power down (PD) and low power (LP) (continued)

ODR[3:0] HF_ODR ODR selection [Hz] Bit resolution Mode

1011

1100

1101

1110

1111

100

200

400

800

Table 35. ODR register setting: high resolution (HR) and high frequencies (HF)

ODR[3:0] HF_ODR ODR selection [Hz] Bit resolution Mode

0001

0010

0011

0100

0101

0110

0111

0101

0110

0111

12.5

100

200

400

800

1600

3200

6400

The BDU bit is used to inhibit the update of the output registers until both upper and lower register parts are read. In default mode (BDU = ‘0’) the output register values are updated continuously. When the BDU is activated (BDU = ‘1’), the content of the output registers is not updated until both MSB and LSB are read which avoids reading values related to different sample times.

DocID030988 Rev 2 55/80

Register description ISM303DAC

Control register 2 (r/w)

BOOT

SOFT_

RESET

(1)

Table 36. CTRL2_A register

FDS_

SLOPE

IF_ADD_

INC

1. This bit must be set to ‘0’ for the correct operation of the device.

I2C_

DISABLE

SPI_

ENABLE

BOOT

Table 37. CTRL2_A register description

Reboot memory content. Default value: 0

(0: normal mode; 1: reboot memory content)

SOFT_RESET Soft reset acts as reset for all control registers, then goes to 0.

Default value: 0 (0: disabled; 1: enabled)

FDS_SLOPE

High-pass filter data selection on output register and FIFO. Default value: 0

(0: internal filter bypassed; 1: internal filter enabled on output register and FIFO)

IF_ADD_INC Register address automatically incremented during multiple byte access with a serial interface (I

C or SPI). Default value: 1 (0: disabled; 1: enabled)

I2C_DISABLE

Disable I

C communication protocol. Default value: 0

(0: SPI and I

C interfaces enabled; 1: I

C mode disabled)

SPI_ENABLE 3-wire SPI interface read enable. Default value: 0

0: SPI read disabled

1: SPI read enabled

56/80 DocID030988 Rev 2

ISM303DAC Register description

Control register 3 (r/w)

ST2 ST1

Table 38. CTRL3_A register

TAP_X_EN TAP_Y_EN TAP_Z_EN LIR H_LACTIVE PP_OD

ST [2:1]

Table 39. CTRL3_A register description

Self-test enable. Default value: 00

(00: Self-test disabled; Other: see

Table 40 )

TAP_X_EN Tap recognition on X direction enable. Default value: 0

(0: disabled; 1: enabled)

TAP_Y_EN Tap recognition on Y direction enable. Default value: 0

(0: disabled; 1: enabled)

TAP_Z_EN Tap recognition on Z direction enable. Default value: 0

(0: disabled; 1: enabled)

LIR Latched Interrupt. Switches between latched ('1'-logic) and pulsed ('0'-logic) mode for function source signals and interrupts routed to pins (wakeup, tap, double-tap, tilt, pedometer, significant motion). Default value: 0

(0: interrupt request not latched; 1: interrupt request latched)

H_LACTIVE Interrupt active high, low. Default value: 0

(0: active high; 1: active low)

PP_OD Push-pull/open-drain selection on interrupt pad. Default value: 0

(0: push-pull; 1: open-drain)

ST2

Table 40. Self-test mode selection

ST1 Self-test mode

Normal mode

Positive sign self-test

Negative sign self-test

Not allowed

DocID030988 Rev 2 57/80

Register description ISM303DAC

Control register 4 (r/w): interrupt 1 configuration

(1)

Table 41. CTRL4_A register

INT1_S_TAP INT1_WU INT1_FF INT1_TAP INT1_6D INT1_FTH INT1_DRDY

1. This bit must be set to '0' for correct device operation.

Table 42. CTRL4_A register description

INT1_S_TAP Single-tap recognition is routed on INT1 pad. Default value: 0

(0: disabled; 1: enabled)

INT1_WU

INT1_FF

INT1_TAP

INT1_6D

INT1_FTH

Wakeup recognition is routed on INT1 pad. Default value: 0

(0: disabled; 1: enabled)

Free-fall recognition is routed on INT1 pad. Default value: 0

(0: disabled; 1: enabled)

Double-tap recognition is routed on INT1 pad. Default value: 0

(0: disabled; 1: enabled)

6D recognition is routed on INT1 pad. Default value: 0

(0: disabled; 1: enabled)

FIFO threshold interrupt is routed on INT1 pad. Default value: 0

(0: disabled; 1: enabled)

INT1_DRDY Data-Ready is routed on INT1 pad. Default value: 0

(0: disabled; 1: enabled)

58/80

Control register 5 (r/w): interrupt 2 configuration

DRDY_

PULSED

INT2_

BOOT

Table 43. CTRL5_A register

INT2_

ON_INT1

(1)

1. This bit must be set to '0' for correct device operation.

INT2_

FTH

INT2_

DRDY

DRDY_

PULSED

Table 44. CTRL5_A register description

Data-ready interrupt mode selection: latched mode / pulsed mode. Default value: 0

(0: latched mode; 1: pulsed mode for data-ready)

INT2 _BOOT

INT2 _ON INT1 All signals routed on INT2 are also routed on INT1. Default value: 0

(0: disabled; 1: enabled)

INT2_FTH

Boot state routed on INT2 pad. Default value: 0

(0: disabled; 1: enabled)

FIFO threshold interrupt is routed on INT2 pad. Default value: 0

(0: disabled; 1: enabled)

INT2_DRDY Data-Ready is routed on INT2 pad. Default value: 0

(0: disabled; 1: enabled)

DocID030988 Rev 2

ISM303DAC Register description

FIFO control register 5 (r/w).

Table 45. FIFO_CTRL_A register

FMODE2 FMODE1 FMODE0 0

(1)

MODULE_

TO_FIFO

1. This bit must be set to '0' for correct device operation.

FIFO mode selection bits. Default: 000. For further details refer to Table 47.

IF_CS_PU

_ DIS

FMODE [2:0]

MODULE_TO_

FIFO

Table 46. FIFO_CTRL_A register description

When set to '1'-logic, module routine result is send to FIFO instead of X,Y,Z acceleration data

IF_CS_PU_DIS When '1'-logic disconnects pull-up in if_cs pad. Default: 0

When the FIFO has been enabled, data acquired has been stored at the accelerometer

ODR and the trigger signal of FIFO writing is the accelerometer internal data-ready.

FIFO data can be stored in default configuration where inertial data as been stored as X, Y,

Z data or in module configuration:

Default configuration: 256-level inertial data (14-bit stored data for X, Y, Z)

User-selectable: 768 module data (14-bit each module)

FMODE2 FMODE1

Table 47. FIFO mode selection

FMODE0 Mode

Bypass mode: FIFO turned off

FIFO mode: Stops collecting data when FIFO is full.

Reserved

Continuous-to-FIFO: Stream mode until trigger is deasserted, then FIFO mode

Bypass-to-Continuous: Bypass mode until trigger is deasserted, then FIFO mode

Reserved

Continuous mode: data If the FIFO is full, the new sample overwrites the older sample.

Reserved

DocID030988 Rev 2 59/80

Register description ISM303DAC

Temperature output register (r).

TEMP7 TEMP6

Table 48. OUT_T_A register

TEMP5 TEMP4 TEMP3 TEMP2

Temp [7:0]

TEMP1 TEMP0

Table 49. OUT_T_A register description

Temperature sensor output data.

The value is expressed as two’s complement sign. Sensitivity = 1 °C/LSB

0 LSB represents T=25 °C ambient.

Status register (r)

FIFO_THS WU_IA

Table 50. STATUS_A register

SLEEP_

STATE

DOUBLE_

TAP

SINGLE_

TAP

6D_IA FF_IA DRDY

Table 51. STATUS_A register description

FIFO_THS FIFO threshold status flag.

(0: FIFO filling is lower than threshold level; 1: FIFO filling is equal to or higher than the threshold level.)

WU_IA

SLEEP_

STATE

DOUBLE_

TAP

SINGLE_

TAP

6D_IA

Wakeup event detection status.

(0: WU event not detected; 1: Wakeup event detected)

Sleep event status.

(0: Sleep event not detected; 1: Sleep event detected)

Double-tap event status

(0: Double-tap event not detected; 1: Double-tap event detected)

Single-tap event status

(0: Single-tap event not detected; 1: Single-tap event detected)

Source of change in position portrait/landscape/face-up/face-down.

(0: no event detected; 1: a change in position detected)

FF_IA

DRDY

Free-fall event detection status.

(0: free-fall event not detected; 1: free-fall event detected)

Data-ready status.

(0: not ready; 1: X-, Y- and Z-axis new data available)

60/80 DocID030988 Rev 2

ISM303DAC Register description

X-axis LSB output register (r)

X_L7 X_L6

Table 52. OUT_X_L_A register default values

X_L5

(2)

X_L4

(2)

1. If 12-bit mode is enabled, this bit is set to 0.

2. If 10-bit mode is enabled, this bit is set to 0.

X_L3

(1)(2)

X_L2

(1)(2)

0 0

The 8 least significant bits of linear acceleration sensor X-axis output. Together with the

OUT_X_H_A (29h)

X-axis MSB output register (r)

X_H7 X_H6

Table 53. OUT_X_H_A register default values

X_H5 X_H4 X_H3 X_H2 X_H1 X_H0

The 8 most significant bits of linear acceleration sensor X-axis output. Together with the

OUT_X_L_A (28h) register it forms the output value expressed as a 16-bit word in 2's

complement.

Y-axis LSB output register (r)

Y_L7 Y_L6

Table 54. OUT_Y_L_A register default values

Y_L5

(2)

Y_L4

(2)

1. If 12-bit mode is enabled, this bit is set to 0.

2. If 10-bit mode is enabled, this bit is set to 0.

Y_L3

(1)(2)

Y_L2

(1)(2)

0 0

The 8 least significant bits of linear acceleration sensor Y-axis output. Together with the

OUT_Y_H_A (2Bh) register it forms the output value expressed as a 16-bit word in 2's

complement.

Y-axis MSB output register (r)

Y_H7 Y_H6

Table 55. OUT_Y_H_A register default values

Y_H5 Y_H4 Y_H3 Y_H2 Y_H1 Y_H0

The 8 most significant bits of linear acceleration sensor Y-axis output. Together with the

OUT_Y_L_A (2Ah) register it forms the output value expressed as a 16-bit word in 2's

complement.

DocID030988 Rev 2 61/80

Register description ISM303DAC

Z-axis LSB output register (r)

Z_L7 Z_L6

Table 56. OUT_Z_L_A register default values

Z_L5

(2)

Z_L4

(2)

1. If 12-bit mode is enabled, this bit is set to 0.

2. If 10-bit mode is enabled, this bit is set to 0.

Z_L3

(1)(2)

Z_L2

(1)(2)

0 0

The 8 least significant bits of linear acceleration sensor Z-axis output. Together with the

OUT_Z_H_A (2Dh) register it forms the output value expressed as a 16-bit word in 2's

complement.

Z-axis MSB output register (r)

Z_H7 Z_H6

Table 57. OUT_Z_H_A register default values

Z_H5 Z_H4 Z_H3 Z_H2 Z_H1 Z_H0

The 8 most significant bits of linear acceleration sensor Z-axis output. Together with the

OUT_Z_L_A (2Ch) register it forms the output value expressed as a 16-bit word in 2's

complement.

8.17 FIFO_THS_A

FIFO threshold level setting (r/w).

FTH7 FTH6

Table 58. FIFO_THS_A register

FTH5 FTH4 FTH3 FTH2 FTH1 FTH0

FIFO_SRC register (r)

FTH FIFO OVR

Table 59. FIFO_SRC_A register

DIFF8 -

62/80 DocID030988 Rev 2

ISM303DAC

FTH

OVR

DIFF8

Register description

Table 60. FIFO_SRC register description

FIFO threshold status.

(0: FIFO filling is lower than FTH level; 1: FIFO filling is equal to or higher than threshold level)

FIFO overrun status. (0: FIFO is not completely filled; 1: FIFO is completely filled and at least one sample has been overwritten)

Concatenated with FIFO_SAMPLES_A (30h) register, it represents the number of

unread samples stored in FIFO. (000000000 = FIFO empty; 100000000 = FIFO full, 256 unread samples).

FIFO_SAMPLES control register (r)

DIFF7 DIFF6

Table 61. FIFO_SAMPLES_A register

DIFF5 DIFF4 DIFF3 DIFF2

DIFF [7:0]

DIFF1 DIFF0

Table 62. FIFO_SAMPLES_A register description

Concatenated with DIFF8 bit in FIFO_SRC_A (2Fh) register, it represents the

number of unread samples stored in FIFO. (000000000 = FIFO empty;

100000000 = FIFO full, 256 unread samples).

4D configuration enable and TAP threshold configuration (r/w)

Table 63. TAP_6D_THS_A register

4D_EN 6D_THS1 6D_THS0

TAP_

THS4

TAP_

THS3

TAP_

THS2

TAP_

THS1

4D_EN

6D_THS [1:0]

Table 64. TAP_6D_THS_A register description

4D detection portrait/landscape position enable.

(0: no position detected;

1: portrait/landscape detection and face-up/face-down position enabled).

Thresholds for 4D/6D function @ FS=2 g (refer to

Table 65 )

TAP_THS [4:0] Threshold for TAP recognition @ FS=2 g

TAP_

THS0

6D_THS1

Table 65. 4D/6D threshold setting FS @ 2 g

6D_THS0 Threshold decoding (degrees)

6 (80 degrees)

11 (70 degrees)

16 (60 degrees)

21 (50 degrees)

DocID030988 Rev 2 63/80

Register description ISM303DAC

Interrupt duration register (r/w)

LAT3 LAT2

Table 66. INT_DUR_A register

LAT1 LAT0 QUIET1 QUIET0 SHOCK1 SHOCK0

LAT [3:1]

QUIET [1:0]

SHOCK [4:0]

Table 67. INT_DUR_A register description

Duration of maximum time gap for double-tap recognition. When double-tap recognition is enabled, this register expresses the maximum time between two successive detected taps to determine a double-tap event.

1 LSB = 32 TODR.

Expected quiet time after a tap detection: this register represents the time after the first detected tap in which there must not be any over-threshold event.

1 LSB = 4 TODR.

Maximum duration of over-threshold event: this register represents the maximum time of an over-threshold signal detection to be recognized as a tap event.

1 LSB = 8 TODR

Wakeup threshold register (r/w)

SINGLE_

DOUBLE_

TAP

SLEEP_

Table 68. WAKE_UP_THS_A register

WU_

THS_ 5

WU_

THS_4

WU_

THS_3

WU_

THS 2

SINGLE_

DOUBLE_

TAP

SLEEP_ON

WU_THS [5:0]

Table 69. WAKE_UP_THS_A register description

Double/single-tap event detection:

(0: double-tap event detection; 1: single-tap event detection)

Sleep (inactivity) enable

(0: sleep disabled; 1: sleep enabled)

Wakeup threshold

WU_

THS 1

WU_

THS 0

64/80 DocID030988 Rev 2

ISM303DAC Register description

Wakeup and sleep duration configuration register (r/w)

Table 70. WAKE_UP_DUR_A register

FF_DUR5 WU_DUR1 WU_DUR0

INT1_

FSS7

SLEEP_

DUR3

SLEEP_

DUR2

SLEEP_

DUR1

SLEEP_

DUR0

FF DUR5

Table 71. WAKE_UP_DUR_A register description

Free-fall duration. In conjunction with FF_DUR [4:0] bit in FREE_FALL_A

(35h)

Wakeup duration. 1 LSB = 1 TODR WU_DUR [1:0]

INT1_FSS7 FF interrupt is routed on INT1 pad

(0: disabled; 1: enabled)

SLEEP_DUR[5:0] Duration to go in sleep mode. 1 LSB = 512 TODR

Free-fall duration and threshold configuration register (r/w)

Table 72. FREE_FALL_A register

FF_DUR4 FF_DUR3 FF_DUR2 FF_DUR1 FF_DUR0 FF_THS2 FF_THS1 FF_THS0

FF_DUR [4:0]

FF_THS [2:0]

Table 73. FREE_FALL_A register description

Free-fall duration. In conjunction with FF_DUR5 bit in WAKE_UP_DUR_A (34h)

Free-fall threshold @ FS = 2 g (refer to

Table 74 )

FF_THS1

Table 74. FREE_FALL_A threshold decoding @ 2 g FS

FF_THS1 FF_THS0 Threshold decoding (degrees)

0 0 5

DocID030988 Rev 2 65/80

Register description ISM303DAC

Event detection status register (r)

OVR WU_IA

Table 75. STATUS_DUP_A register

SLEEP_

STATE

DOUBLE_

TAP

SINGLE_

TAP

6D_IA FF_IA DRDY

OVR

WU_IA

SLEEP_

STATE

DOUBLE_

TAP

SINGLE_

TAP

6D_IA

FF_IA

DRDY

Table 76. STATUS_DUP_A register description

FIFO overrun status flag.

(0: FIFO filling is not completely filled; 1: FIFO is completely filled and at least one sample has been overwritten)

Wakeup event detection status.

(0: WU event not detected; 1: Wake up event detected)

Sleep event status.

(0: Sleep event not detected; 1: Sleep event detected)

Double-tap event status:

(0: Double-tap event not detected; 1: Double-tap event detected)

Single-tap event status:

(0: Single-tap event not detected; 1: Single-tap event detected)

Source of change in position portrait/landscape/face-up/face-down.

(0: no event detected; 1: a change in position is detected)

Free-fall event detection status.

(0: free-fall event not detected; 1: free-fall event detected)

Data-ready status.

(0: not ready; 1: X-, Y- and Z-axis new data available)

66/80 DocID030988 Rev 2

ISM303DAC Register description

Wakeup source register (r)

Table 77. WAKE_UP_SRC_A register

FF_IA

SLEEP

STATE IA

WU_IA X_WU Y_WU

FF_IA

SLEEP

STATE IA

WU_IA

X_WU

Y_WU

Z_WU

Table 78. WAKE_UP_SRC_A register description

Free-fall event detection status.

(0: FF event not detected; 1: FF event detected)

Sleep event status.

(0: Sleep event not detected; 1: Sleep event detected)

Wakeup event detection status.

(0: Wakeup event not detected; 1: Wakeup event is detected)

Wakeup event detection status on X-axis.

(0: Wakeup event on X not detected; 1: Wakeup event on X-axis is detected)

Wakeup event detection status on Y-axis.

(0: Wakeup event on Y not detected; 1: Wake up event on Y-axis is detected)

Wakeup event detection status on Z-axis.

(0: Wakeup event on Z not detected; 1: Wake up event on Z-axis is detected)

Z_WU

TAP source register (r)

TAP_IA

Table 79. TAP_SRC_A register

SINGLE

TAP

DOUBLE

TAP

TAP SIGN X_TAP Y_TAP Z_TAP

TAP_IA

Table 80. TAP_SRC_A register description

TAP event status.

(0: Tap event not detected; 1: Tap event detected)

SINGLE

TAP

DOUBLE

TAP

TAP_SIGN Sign of acceleration detected by tap event.

(0: positive sign of acceleration detected; 1: negative sign of acceleration detected).

X_TAP Tap event detection status on X-axis.

(0: Tap event on X not detected; 1: Tap event on X-axis is detected)

Y_TAP

Single-tap event status.

(0: Single-tap event not detected; 1: Single-tap event detected)

Double-tap event status.

(0: Double-tap event not detected; 1: Double-tap event detected)

Z_TAP

Tap event detection status on Y-axis.

(0: Tap event on Y not detected; 1: TAP event on Y-axis is detected)

Tap event detection status on Z-axis.

(0: Tap event on Z not detected; 1: Tap event on Z-axis is detected)

DocID030988 Rev 2 67/80

Register description ISM303DAC

6D_IA

6D source register (r)

6D_IA ZH

Table 81. 6D_SRC_A register

ZL YH YL

Table 82. 6D_SRC_A register description

Source of change in position portrait/landscape/face-up/face-down.

(0: no event detected; 1: a change in position is detected)

ZH overthreshold

(0: ZH does not exceed the threshold; 1: ZH is over the threshold)

ZL overthreshold

(0: ZL does not exceed the threshold; 1: ZL is over the threshold)

YH overthreshold

(0: YH does not exceed the threshold; 1: YH is over the threshold)

YL overthreshold

(0: YL does not exceed the threshold; 1: YL is over the threshold)

XH overthreshold:

(0: XH does not exceed the threshold; 1: XH is over the threshold)

XL overthreshold

(0: XL does not exceed the threshold; 1: XL is over the threshold)

XH XL

Functional source register (r)

Table 83. FUNC_SRC_A register

MODULE_

READY

MODULE_READY

Table 84. FUNC_SRC_A register description

Module status.

(0: new module data not available, 1: new module data available)

68/80 DocID030988 Rev 2

ISM303DAC Register description

Functional control register (r/w)

(1)

Table 85. FUNC_CTRL_A register

MODULE_

1. This bit must be set to '0' for the correct operation of the device.

MODULE_ON

Table 86. FUNC_CTRL_A register description

Module processing enable. Default value: 0

(0: disabled; 1: module)