STMicroelectronics LSM6DSL Datasheet
Below you will find brief information for LSM6DSL, LSM6DSLTR. These are iNEMO inertial modules featuring always-on 3D accelerometer and 3D gyroscope. They offer low power consumption, smart FIFO, and embedded functionalities like pedometer, step detector, and tilt function. Applications include motion tracking, indoor navigation, and vibration monitoring.
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LSM6DSL
iNEMO inertial module:
always-on 3D accelerometer and 3D gyroscope
Datasheet
-
production data
LGA-14L
(2.5 x 3 x 0.83 mm) typ.
Features
Power consumption: 0.4 mA in combo normal mode and 0.65 mA in combo high-performance mode
“Always-on” experience with low power consumption for both accelerometer and gyroscope
Smart FIFO up to 4 kbyte based on features set
Android M compliant
Hard, soft ironing for external magnetic sensor corrections
±2/±4/±8/±16 g full scale
±125/±250/±500/±1000/±2000 dps full scale
Analog supply voltage: 1.71 V to 3.6 V
Independent IOs supply (1.62 V)
Compact footprint, 2.5 mm x 3 mm x 0.83 mm
SPI & I
2
C serial interface with main processor data synchronization feature
Pedometer, step detector and step counter
Significant motion and tilt function
Standard interrupts: free-fall, wakeup, 6D/4D orientation, click and double-click
Embedded temperature sensor
ECOPACK
®
, RoHS and “Green” compliant
Applications
Motion tracking and gesture detection
Collecting sensor data
Indoor navigation
IoT and connected devices
Intelligent power saving for handheld devices
Vibration monitoring and compensation
Description
The LSM6DSL is a system-in-package featuring a 3D digital accelerometer and a 3D digital gyroscope performing at 0.65 mA in high-performance mode and enabling always-on low-power features for an optimal motion experience for the consumer.
The LSM6DSL supports main OS requirements, offering real, virtual and batch sensors with 4 kbyte for dynamic data batching.
ST’s family of MEMS sensor modules leverages the robust and mature manufacturing processes already used for the production of micromachined accelerometers and gyroscopes.
The various sensing elements are manufactured using specialized micromachining processes, while the IC interfaces are developed using CMOS technology that allows the design of a dedicated circuit which is trimmed to better match the characteristics of the sensing element.
The LSM6DSL has a full-scale acceleration range of
±2/±4/±8/±16 g and an angular rate range of
±125/±250/±500/±1000/±2000 dps.
High robustness to mechanical shock makes the
LSM6DSL the preferred choice of system designers for the creation and manufacturing of reliable products.
The LSM6DSL is available in a plastic land grid array
(LGA) package.
Table 1. Device summary
Part number
Temp. range [°C]
Package Packing
LSM6DSL -40 to +85
LSM6DSLTR -40 to +85
LGA-14L
(2.5x3x0.83mm)
Tray
Tape &
Reel
September 2017
This is information on a product in full production.
DocID028475 Rev 7 1/114 www.st.com
Contents
Contents
LSM6DSL
Embedded low-power features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 26
SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
C - inter-IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Zero-g and zero-rate level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Gyroscope power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Accelerometer power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Block diagrams of the gyroscope filters . . . . . . . . . . . . . . . . . . . . . . . . . 32
Block diagrams of the accelerometer filters . . . . . . . . . . . . . . . . . . . . . . 33
Continuous-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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Contents
Bypass-to-Continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
FIFO reading procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
C/SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
SPI read in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
LSM6DSL electrical connections in Mode 1 . . . . . . . . . . . . . . . . . . . . . . . 44
LSM6DSL electrical connections in Mode 2 . . . . . . . . . . . . . . . . . . . . . . . 45
FUNC_CFG_ACCESS (01h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
SENSOR_SYNC_TIME_FRAME (04h) . . . . . . . . . . . . . . . . . . . . . . . . . . 52
SENSOR_SYNC_RES_RATIO (05h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
DRDY_PULSE_CFG_G (0Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
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MASTER_CONFIG (1Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
WAKE_UP_SRC (1Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
STATUS_REG (1Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
OUT_TEMP_L (20h), OUT_TEMP_H (21h) . . . . . . . . . . . . . . . . . . . . . . . 72
SENSORHUB1_REG (2Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
SENSORHUB2_REG (2Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
SENSORHUB3_REG (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
SENSORHUB4_REG (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
SENSORHUB5_REG (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
SENSORHUB6_REG (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
SENSORHUB7_REG (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
SENSORHUB8_REG(35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
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SENSORHUB9_REG (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
SENSORHUB10_REG (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
SENSORHUB11_REG (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
SENSORHUB12_REG (39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
FIFO_STATUS1 (3Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
FIFO_STATUS2 (3Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
FIFO_STATUS3 (3Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
FIFO_STATUS4 (3Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
FIFO_DATA_OUT_L (3Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
FIFO_DATA_OUT_H (3Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
TIMESTAMP0_REG (40h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
TIMESTAMP1_REG (41h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
TIMESTAMP2_REG (42h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
STEP_TIMESTAMP_L (49h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
STEP_TIMESTAMP_H (4Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
STEP_COUNTER_L (4Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
STEP_COUNTER_H (4Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
SENSORHUB13_REG (4Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
SENSORHUB14_REG (4Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
SENSORHUB15_REG (4Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
SENSORHUB16_REG (50h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
SENSORHUB17_REG (51h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
SENSORHUB18_REG (52h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
FUNC_SRC1 (53h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
FUNC_SRC2 (54h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
WRIST_TILT_IA (55h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
WAKE_UP_THS (5Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
WAKE_UP_DUR (5Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
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Contents LSM6DSL
MASTER_CMD_CODE (60h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
SENS_SYNC_SPI_ERROR_CODE (61h) . . . . . . . . . . . . . . . . . . . . . . . . 93
OUT_MAG_RAW_X_L (66h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
OUT_MAG_RAW_X_H (67h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
OUT_MAG_RAW_Y_L (68h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
OUT_MAG_RAW_Y_H (69h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
OUT_MAG_RAW_Z_L (6Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
OUT_MAG_RAW_Z_H (6Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Embedded functions register mapping . . . . . . . . . . . . . . . . . . . . . . . . . 96
Embedded functions registers description - Bank A . . . . . . . . . . . . . . 98
SLV0_SUBADD (03h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
SLAVE0_CONFIG (04h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
SLV1_SUBADD (06h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
SLAVE1_CONFIG (07h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
SLV2_SUBADD (09h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
SLAVE2_CONFIG (0Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
11.13 DATAWRITE_SRC_MODE_SUB_SLV0 (0Eh) . . . . . . . . . . . . . . . . . . . . 102
11.14 CONFIG_PEDO_THS_MIN (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
11.17 STEP_COUNT_DELTA (15h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
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Contents
Embedded functions registers description - Bank B . . . . . . . . . . . . . 108
A_WRIST_TILT_LAT (50h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
A_WRIST_TILT_THS (54h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
A_WRIST_TILT_Mask (59h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
LGA-14 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
LGA-14 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
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List of tables
List of tables
LSM6DSL
C slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
C master timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2
C pin details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
C terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 39
Transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 39
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List of tables LSM6DSL
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List of figures
List of figures
LSM6DSL
C timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Read and write protocol (in mode 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
SPI read protocol (in mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
SPI write protocol (in mode 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
SPI read protocol in 3-wire mode (in mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
LGA-14 2.5x3x0.86 mm package outline and mechanical data . . . . . . . . . . . . . . . . . . . . 110
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1 Overview
Overview
The LSM6DSL is a system-in-package featuring a high-performance 3-axis digital accelerometer and 3-axis digital gyroscope.
The integrated power-efficient modes are able to reduce the power consumption down to
0.65 mA in high-performance mode, combining always-on low-power features with superior sensing precision for an optimal motion experience for the consumer thanks to ultra-low noise performance for both the gyroscope and accelerometer.
The LSM6DSL delivers best-in-class motion sensing that can detect orientation and gestures in order to empower application developers and consumers with features and capabilities that are more sophisticated than simply orienting their devices to portrait and landscape mode.
The event-detection interrupts enable efficient and reliable motion tracking and contextual awareness, implementing hardware recognition of free-fall events, 6D orientation, click and double-click sensing, activity or inactivity, and wakeup events.
The LSM6DSL supports main OS requirements, offering real, virtual and batch mode sensors. In addition, the LSM6DSL can efficiently run the sensor-related features specified in Android, saving power and enabling faster reaction time. In particular, the LSM6DSL has been designed to implement hardware features such as significant motion detection, tilt, pedometer functions, timestamping and to support the data acquisition of an external magnetometer with ironing correction (hard, soft).
The LSM6DSL offers hardware flexibility to connect the pins with different mode connections to external sensors to expand functionalities such as adding a sensor hub, etc.
Up to 4 kbyte of FIFO with dynamic allocation of significant data (i.e. external sensors, timestamp, etc.) allows overall power saving of the system.
Like the entire portfolio of MEMS sensor modules, the LSM6DSL leverages the robust and mature in-house manufacturing processes already used for the production of micromachined accelerometers and gyroscopes. The various sensing elements are manufactured using specialized micromachining processes, while the IC interfaces are developed using CMOS technology that allows the design of a dedicated circuit which is trimmed to better match the characteristics of the sensing element.
The LSM6DSL is available in a small plastic land grid array (LGA) package of
2.5 x 3.0 x 0.83 mm to address ultra-compact solutions.
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Embedded low-power features
2 Embedded low-power features
LSM6DSL
The LSM6DSL has been designed to be fully compliant with Android, featuring the following on-chip functions:
4 kbyte data buffering
– 100% efficiency with flexible configurations and partitioning
– Possibility to store timestamp
Event-detection interrupts (fully configurable):
– Free-fall
– Wakeup
– 6D orientation
– Click and double-click sensing
– Activity / inactivity recognition
Specific IP blocks with negligible power consumption and high-performance:
– Pedometer functions: step detector and step counters
– Tilt (refer to
for additional information
–
Absolute Wrist Tilt (refer to Section 2.2: Absolute wrist tilt
for additional information)
– Significant Motion Detection
Sensor hub
– Up to 6 total sensors: 2 internal (accelerometer and gyroscope) and 4 external sensors
Data rate synchronization with external trigger for reduced sensor access and enhanced fusion
The tilt function helps to detect activity change and has been implemented in hardware using only the accelerometer to achieve both the targets of ultra-low power consumption and robustness during the short duration of dynamic accelerations.
It is based on a trigger of an event each time the device's tilt changes. For a more customized user experience, in the LSM6DSL the tilt function is configurable through:
a programmable average window
a programmable average threshold
The tilt function can be used with different scenarios, for example: a) Triggers when phone is in a front pants pocket and the user goes from sitting to standing or standing to sitting; b) Doesn’t trigger when phone is in a front pants pocket and the user is walking, running or going upstairs.
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2.2
Embedded low-power features
Absolute wrist tilt
The LSM6DSL implements in hardware the Absolute Wrist Tilt (AWT) function which allows detecting when the angle between a selectable accelerometer semi-axis and the horizontal plane becomes higher than a specific user-selectable value.
Configurable threshold and latency parameters are associated with the AWT function: the threshold parameter defines the amplitude of the tilt angle; the latency parameter defines the minimum duration of the AWT event to be recognized. The AWT interrupt signal is generated if the tilt angle is higher than the threshold angle for a period of time equal to or greater than the latency period.
The AWT function is based on the accelerometer sensor only and works at 26 Hz, so the accelerometer ODR must be set at a value of 26 Hz or higher.
By default, the AWT algorithm is applied to the positive X-axis.
In order to enable the AWT function it is necessary to set to 1 both the FUNC_EN bit and the
WRIST_TILT_EN bit of CTRL10_C (19h)
.
The AWT interrupt signal can be driven to the INT2 interrupt pin by setting to 1 the
INT2_WRIST_TILT bit of the DRDY_PULSE_CFG_G (0Bh) register; it can also be checked
by reading the WRIST_TILT_IA bit of the
FUNC_SRC2 (54h) register (it will also clear the
interrupt signal if latched).
is the status register to be used to detect which axis has triggered the
AWT event (not applicable when using one axis side only).
The full description and an example is given in the dedicated application note.
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Pin description
Z
Figure 1. Pin connections
Y
X
Ω
Y
Ω
R
NC
NC
(1)
(1)
Ω
P
1. Leave pin electrically unconnected and soldered to PCB.
LSM6DSL
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The LSM6DSL offers flexibility to connect the pins in order to have two different mode connections and functionalities. In detail:
Mode 1 : I 2 C slave interface or SPI (3- and 4-wire) serial interface is available;
Mode 2 : I
2
C slave interface or SPI (3- and 4-wire) serial interface and I
2
C interface master for external sensor connections are available;
Figure 2. LSM6DSL connection modes
0RGH 0RGH
+267
, &63,Z
+267
, &63,Z
/60'6/ /60'6/
0DVWHU, &
/60'60
VHQVRUV
In the following table each mode is described for the pin connections and function.
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Pin description LSM6DSL
Pin# Name
Table 2. Pin description
Mode 1 function Mode 2 function
6
7
8
4
5
2
3
1
9
10
11
12
13
14
SDO/SA0
SDx
SCx
INT1
VDDIO
GND
GND
(1)
VDD
(1)
INT2
NC
NC
(2)
CS
SCL
SDA
SPI 4-wire interface serial data output (SDO)
I
2
C least significant bit of the device address (SA0)
Connect to VDDIO or GND
Connect to VDDIO or GND
SPI 4-wire interface serial data output
(SDO)
I
2
C least significant bit of the device address (SA0)
I
2
C serial data master (MSDA)
I
2
C serial clock master (MSCL)
Programmable interrupt 1
Power supply for I/O pins
0 V supply
0 V supply
Programmable interrupt 2
(INT2) / Data enable (DEN)
Power supply
Programmable interrupt 2 (INT2)/
Data enable (DEN)/
I
2
C master external synchronization signal (MDRDY)
Leave unconnected
Leave unconnected
I
2
C/SPI mode selection
(1: SPI idle mode / I
2
C communication enabled; 0: SPI communication mode / I
2
C disabled)
I
2
C/SPI mode selection
(1: SPI idle mode / I
2 enabled; disabled)
C communication
0: SPI communication mode / I
2
C
I
2
C serial clock (SCL)
SPI serial port clock (SPC)
I
2
C serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output
(SDO)
I
2
C serial clock (SCL)
SPI serial port clock (SPC)
I
2
C serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output
(SDO)
1. Recommended 100 nF filter capacitor.
2. Leave pin electrically unconnected and soldered to PCB.
20/114 DocID028475 Rev 7
LSM6DSL Module specifications
@ Vdd = 1.8 V, T = 25 °C unless otherwise noted.
Symbol
LA_FS
G_FS
Parameter
Table 3. Mechanical characteristics
Test conditions Min.
Linear acceleration measurement range
Angular rate measurement range
LA_So
G_So
Linear acceleration sensitivity
Angular rate sensitivity
(2)
(2)
FS = ±2
FS = ±4
FS = ±8
FS = ±16
FS = ±125
FS = ±250
FS = ±500
FS = ±1000
G_So% Sensitivity tolerance
(3)
LA_SoDr
Linear acceleration sensitivity change vs. temperature
(4)
G_SoDr
FS = ±2000 at component level from -40° to +85°
Angular rate sensitivity change vs.
from -40° to +85°
LA_TyOff
Linear acceleration zerog level offset accuracy
(5)
G_TyOff Angular rate zero-rate level
(4)
LA_OffDr
G_OffDr
Rn
Linear acceleration zerog level change vs. temperature
(4)
Angular rate typical zero-rate level change vs. temperature
(4)
Rate noise density in highperformance mode
(6)
Typ.
(1)
±2000
0.061
0.122
0.244
0.488
4.375
8.75
17.50
±2
±4
±8
±16
±125
±250
±500
±1000
35
70
±1
±0.01
±0.007
±40
±3
±0.1
±0.015
4
Max.
Unit g dps m g /LSB mdps/LSB
%
%/°C
%/°C m g dps m g/ °C dps/°C mdps/
Hz
DocID028475 Rev 7 21/114
114
Module specifications LSM6DSL
Symbol
Table 3. Mechanical characteristics (continued)
Parameter Test conditions Min.
Typ.
(1)
Max.
Unit
RnRMS
Gyroscope RMS noise in normal/low-power mode
(7)
75 mdps
An
RMS
LA_ODR
Acceleration noise density in high-performance mode
Acceleration RMS noise in normal/low-power mode
(8)
(9)(10)
Linear acceleration output data rate
G_ODR Angular rate output data rate
FS = ±2
FS = ±4
FS = ±8
FS = ±2
FS = ±4
FS = ±8 g g g
FS = ±16 g g g
FS = ±16 g g
80
80
90
130
1.8
2.0
2.4
3.0
1.6
(11)
12.5
26
52
104
208
416
833
1666
3332
6664
12.5
26
52
104
208
416
833
1666
3332
6664 m
μ g g / √
Hz
Hz
(RMS)
Vst
Linear acceleration self-test output change
(12)(13)(14)
Angular rate self-test output change
(15)(16)
Operating temperature range
FS = 250 dps
FS = 2000 dps
90
20
150
-40
1700
80
700
+85 Top
1. Typical specifications are not guaranteed.
2. Sensitivity values after factory calibration test and trimming
3. Subject to change.
4. Measurements are performed in a uniform temperature setup and they are based on characterization data in a limited number of samples. Not measured during final test for production.
5. Values after factory calibration test and trimming.
m g dps dps
°C
22/114 DocID028475 Rev 7
LSM6DSL Module specifications
6. Gyroscope rate noise density in high-performance mode is independent of the ODR and FS setting.
7. Gyroscope RMS noise in normal/low-power mode is independent of the ODR and FS setting.
8. Accelerometer noise density in high-performance mode is independent of the ODR.
9. Accelerometer RMS noise in normal/low-power mode is independent of the ODR.
10. Noise RMS related to BW = ODR /2 (for ODR /9, typ value can be calculated by Typ *0.6).
11. This ODR is available when accelerometer is in low-power mode.
12. The sign of the linear acceleration self-test output change is defined by the STx_XL bits in
,
for all axes.
13. The linear acceleration self-test output change is defined with the device in stationary condition as the absolute value of:
OUTPUT[LSb] (self-test enabled) - OUTPUT[LSb] (self-test disabled). 1LSb = 0.061 m g at ±2 g full scale.
14. Accelerometer self-test limits are full-scale independent.
16. The angular rate self-test output change is defined with the device in stationary condition as the absolute value of:
OUTPUT[LSb] (self-test enabled) - OUTPUT[LSb] (self-test disabled). 1LSb = 70 mdps at ±2000 dps full scale.
DocID028475 Rev 7 23/114
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Module specifications LSM6DSL
@ Vdd = 1.8 V, T = 25 °C unless otherwise noted.
Symbol Parameter
Table 4. Electrical characteristics
Test conditions Min.
Typ.
(1)
Max.
Unit
Vdd Supply voltage
Vdd_IO Power supply for I/O
IddHP
IddNM
Gyroscope and accelerometer current consumption in high-performance mode
Gyroscope and accelerometer current consumption in normal mode
IddLP
LA_IddHP
Gyroscope and accelerometer current consumption in low-power mode
Accelerometer current consumption in high-performance mode
LA_IddNM
Accelerometer current consumption in normal mode
LA_IddLM
Accelerometer current consumption in low-power mode
ODR = 52 Hz
ODR = 12.5 Hz
ODR = 1.6 Hz
IddPD
Gyroscope and accelerometer current consumption during power-down
Ton
V
IH
V
IL
V
OH
V
OL
Top
Turn-on time
Digital high-level input voltage
Digital low-level input voltage
High-level output voltage
Low-level output voltage
Operating temperature range
I
I
ODR = 1.6 kHz
ODR = 208 Hz
ODR = 52 Hz
ODR < 1.6 kHz
ODR
ODR = 208 Hz
OH
OL
≥ 1.6 kHz
= 4 mA
= 4 mA
(2)
(2)
1.71
1.62
0.7 *VDD_IO
VDD_IO - 0.2
-40
1.8
0.65
0.45
0.29
150
160
85
25
9
4.5
3
35
3.6
3.6
0.3 *VDD_IO
0.2
+85
V
V mA mA mA
μ
μ
μ
μ
1. T ypical specifications are not guaranteed.
2. 4 mA is the maximum driving capability, i.e. the maximum DC current that can be sourced/sunk by the digital pad in order to guarantee the correct digital output voltage levels V
OH
and V
OL
.
A
A
A
A ms
V
V
V
V
°C
24/114 DocID028475 Rev 7
LSM6DSL
4.3
Module specifications
Temperature sensor characteristics
@ Vdd = 1.8 V, T = 25 °C unless otherwise noted.
Symbol
Table 5. Temperature sensor characteristics
Parameter
TODR
Toff
TSen
TST
(2)
Temperature refresh rate
Temperature offset
(3)
Temperature sensitivity
Temperature stabilization time
T_ADC_res Temperature ADC resolution
Top Operating temperature range
(4)
Test condition Min.
Typ.
(1)
-15
-40
52
256
16
Max.
+15
500
Unit
Hz
°C
LSB/°C
μ s
+85
1. Typical specifications are not guaranteed.
2. When the accelerometer is in Low-Power mode and the gyroscope part is turned off, the TODR value is equal to the accelerometer ODR.
3. The output of the temperature sensor is 0 LSB (typ.) at 25 °C.
4. Time from power ON bit to valid data based on characterization data.
bit
°C
DocID028475 Rev 7 25/114
114
Module specifications LSM6DSL
4.4
4.4.1
Communication interface characteristics
SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top.
Symbol
Table 6. SPI slave timing values (in mode 3)
Value
(1)
Parameter
Min Max
Unit t c(SPC) f c(SPC) t su(CS) t h(CS) t su(SI) t h(SI) t v(SO) t h(SO) t dis(SO)
SPI clock cycle
SPI clock frequency
CS setup time
CS hold time
SDI input setup time
SDI input hold time
SDO valid output time
SDO output hold time
SDO output disable time
100
5
20
5
15
5
10
50
50 ns
MHz ns
1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production
Figure 3. SPI slave timing diagram (in mode 3)
Note: Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output ports.
26/114 DocID028475 Rev 7
LSM6DSL
4.4.2 I
2
C - inter-IC control interface
Subject to general operating conditions for Vdd and Top.
Figure 4. I 2 C timing diagram
Module specifications
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Note: Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.
4.4.2.1 I
2
C slave
Symbol Parameter
Table 7. I 2 C slave timing values
I
2
C standard mode
(1)
Min Max f
(SCL) t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t h(ST)
SCL clock frequency
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
START condition hold time
0
4.7
4.0
250
0
4
100
3.45
t su(SR)
Repeated START condition setup time
4.7
t su(SP)
STOP condition setup time 4 t w(SP:SR)
Bus free time between STOP and START condition
4.7
1. Data based on standard I 2 C protocol requirement, not tested in production.
0.6
100
0
0.6
I
2
C fast mode
(1)
Min Max
0
1.3
400
0.9
0.6
0.6
1.3
6723
Unit kHz
μ s ns
μ s
μ s
DocID028475 Rev 7 27/114
114
Module specifications LSM6DSL
Symbol
4.4.2.2 I
2
C master
When in I supports I
2
2
C Master Mode, an external sensor can be connected to LSM6DSL. LSM6DSL
C Master - Fast Mode only.
Table 8. I
2
C master timing values
Parameter
I
2
C
Master
Unit f
(SCL) t w(SCLL) t w(SCLH) t su(SR) t su(HD) t su(SP) t w(SP:SR)
SCL clock frequency
SCL clock low time
SCL clock high time
Data valid time
SDA hold time
SDA setup time
Repeated START condition setup time
Repeated START condition hold time
STOP condition setup time
Bus free time between STOP and START condition
116.3
5.86
2.74
3.9
≥ 0
≥ 100
1.56
1.56
2.73
21
I
2
C
Fast Mode
(min)
0
(400 kHz max)
1.3
0.6
-
0
100
0.6
0.6
0.6
1.3
kHz ns ns
μ s
μ s
μ s ns
μ s
μ s
μ s
28/114 DocID028475 Rev 7
LSM6DSL
4.5
Note:
Module specifications
Absolute maximum ratings
Stresses above those listed as “Absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Symbol
Table 9. Absolute maximum ratings
Ratings
Vdd
T
STG
Sg
Supply voltage
Storage temperature range
Acceleration g for 0.2 ms
ESD Electrostatic discharge protection (HBM)
Vin
Input voltage on any control pin
(including CS, SCL/SPC, SDA/SDI/SDO, SDO/SA0)
Maximum value
-0.3 to 4.8
-40 to +125
10,000
2
-0.3 to Vdd_IO +0.3
Supply voltage on any pin should never exceed 4.8 V.
This device is sensitive to mechanical shock, improper handling can cause permanent damage to the part.
This device is sensitive to electrostatic discharge (ESD), improper handling can cause permanent damage to the part.
Unit
V
°C g kV
V
DocID028475 Rev 7 29/114
114
Module specifications LSM6DSL
4.6 Terminology
4.6.1 Sensitivity
Linear acceleration sensitivity can be determined, for example, by applying 1 g acceleration to the device. Because the sensor can measure DC accelerations, this can be done easily by pointing the selected axis towards the ground, noting the output value, rotating the sensor 180 degrees (pointing towards the sky) and noting the output value again. By doing so, ±1 g acceleration is applied to the sensor. Subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This value changes very little over temperature and over time. The sensitivity tolerance describes
the range of sensitivities of a large number of sensors (see Table 3 ).
An angular rate gyroscope is a device that produces a positive-going digital output for counterclockwise rotation around the axis considered. Sensitivity describes the gain of the sensor and can be determined by applying a defined angular velocity to it. This value changes very little over temperature and time (see
4.6.2 Zerog and zero-rate level
Linear acceleration zerog level offset (TyOff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. A sensor in a steady state on a horizontal surface will measure 0 g on both the X-axis and Y-axis, whereas the Z-axis will measure 1 g . Ideally, the output is in the middle of the dynamic range of the sensor (content of OUT registers 00h, data expressed as 2’s complement number). A deviation from the ideal value in this case is called zerog offset.
Offset is to some extent a result of stress to MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes little over temperature, see “Linear acceleration zerog level change vs. temperature” in
g level tolerance
(TyOff) describes the standard deviation of the range of zerog levels of a group of sensors.
Zero-rate level describes the actual output signal if there is no angular rate present. The zero-rate level of precise MEMS sensors is, to some extent, a result of stress to the sensor and therefore the zero-rate level can slightly change after mounting the sensor onto a printed circuit board or after exposing it to extensive mechanical stress. This value changes very little over temperature and time (see
30/114 DocID028475 Rev 7
LSM6DSL
5 Functionality
Functionality
5.2
5.3
In the LSM6DSL, the accelerometer and the gyroscope can be turned on/off independently of each other and are allowed to have different ODRs and power modes.
The LSM6DSL has three operating modes available:
only accelerometer active and gyroscope in power-down
only gyroscope active and accelerometer in power-down
both accelerometer and gyroscope sensors active with independent ODR
The accelerometer is activated from power-down by writing ODR_XL[3:0] in
while the gyroscope is activated from power-down by writing ODR_G[3:0] in
. For combo-mode the ODRs are totally independent.
Gyroscope power modes
In the LSM6DSL, the gyroscope can be configured in four different operating modes: powerdown, low-power, normal mode and high-performance mode. The operating mode selected depends on the value of the G_HM_MODE bit in
CTRL7_G (16h) . If G_HM_MODE is set to
'0', high-performance mode is valid for all ODRs (from 12.5 Hz up to 6.66 kHz).
To enable the low-power and normal mode, the G_HM_MODE bit has to be set to '1'. Lowpower mode is available for lower ODRs (12.5, 26, 52 Hz) while normal mode is available for ODRs equal to 104 and 208 Hz.
Accelerometer power modes
In the LSM6DSL, the accelerometer can be configured in four different operating modes: power-down, low-power, normal mode and high-performance mode. The operating mode selected depends on the value of the XL_HM_MODE bit in
. If
XL_HM_MODE is set to '0', high-performance mode is valid for all ODRs (from 12.5 Hz up to 6.66 kHz).
To enable the low-power and normal mode, the XL_HM_MODE bit has to be set to '1'. Lowpower mode is available for lower ODRs (1.6, 12.5, 26, 52 Hz) while normal mode is available for ODRs equal to 104 and 208 Hz.
DocID028475 Rev 7 31/114
114
Functionality
5.4 Block diagram of filters
Figure 5. Block diagram of filters
LSM6DSL
5.4.1 Block diagrams of the gyroscope filters
The gyroscope filtering configuration for both Mode 1 (for User Interface (UI) and Electronic
Image Stabilization (EIS) functionality) and Mode 2 is shown in
.
Figure 6. Gyroscope digital chain - Mode 1 (UI/EIS) and Mode 2
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The gyroscope ODR is selectable from 12.5 Hz up to 6.66 kHz. A low-pass filter (LPF1) is
Data can be acquired from the output registers and FIFO over the I 2 C/SPI interface.
32/114 DocID028475 Rev 7
LSM6DSL
5.4.2
Functionality
Block diagrams of the accelerometer filters
In the LSM6DSL, the filtering chain for the accelerometer part is composed of the following:
Analog filter (anti-aliasing)
Digital filter (LPF1)
Composite filter
Details of the block diagram appear in the following figure.
Figure 7. Accelerometer chain
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The configuration of the digital filter can be set using the LPF1_BW_SEL bit in
and the INPUT_COMPOSITE bit in
.
Figure 8. Accelerometer composite filter
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DocID028475 Rev 7 33/114
114
Functionality LSM6DSL
5.5 FIFO
The presence of a FIFO allows consistent power saving for the system since the host processor does not need continuously poll data from the sensor, but it can wake up only when needed and burst the significant data out from the FIFO.
The LSM6DSL embeds 4 kbytes data FIFO to store the following data:
gyroscope
accelerometer
external sensors
step counter and timestamp
temperature
Writing data in the FIFO can be configured to be triggered by the:
accelerometer/gyroscope data-ready signal; in which case the ODR must be lower than or equal to both the accelerometer and gyroscope ODRs;
sensor hub data-ready signal;
step detection signal.
In addition, each data can be stored at a decimated data rate compared to FIFO ODR and it is configurable by the user, setting the
registers. The available decimation factors are 2, 3, 4, 8, 16, 32.
The programmable FIFO threshold can be set in FIFO_CTRL1 (06h)
using the FTH [10:0] bits.
To monitor the FIFO status, dedicated registers
,
FIFO_STATUS4 (3Dh) ) can be read to detect FIFO overrun
events, FIFO full status, FIFO empty status, FIFO threshold status and the number of unread samples stored in the FIFO. To generate dedicated interrupts on the INT1 and INT2 pads of these status events, the configuration can be set in
and
The FIFO buffer can be configured according to five different modes:
Bypass mode
FIFO mode
Continuous mode
Continuous-to-FIFO mode
Bypass-to-continuous mode
Each mode is selected by the FIFO_MODE_[2:0] bits in the
register. To guarantee the correct acquisition of data during the switching into and out of FIFO mode, the first sample acquired must be discarded.
In Bypass mode (
FIFO_CTRL5 (0Ah) (FIFO_MODE_[2:0] = 000), the FIFO is not
operational and it remains empty.
Bypass mode is also used to reset the FIFO when in FIFO mode.
34/114 DocID028475 Rev 7
LSM6DSL Functionality
In FIFO mode (
FIFO_CTRL5 (0Ah) (FIFO_MODE_[2:0] = 001) data from the output
channels are stored in the FIFO until it is full.
To reset FIFO content, Bypass mode should be selected by writing
(FIFO_MODE_[2:0]) to '000' After this reset command, it is possible to restart FIFO mode by writing
FIFO_CTRL5 (0Ah) (FIFO_MODE_[2:0]) to '001'.
FIFO buffer memorizes up to 4096 samples of 16 bits each but the depth of the FIFO can be
resized by setting the FTH [10:0] bits in FIFO_CTRL1 (06h)
and
STOP_ON_FTH bit in FIFO_CTRL4 (09h)
is set to '1', FIFO depth is limited up to FTH [10:0] bits in
and
.
Continuous mode ( FIFO_CTRL5 (0Ah) (FIFO_MODE_[2:0] = 110) provides a continuous
FIFO update: as new data arrives, the older data is discarded.
A FIFO threshold flag
(FTH) is asserted when the number of unread samples in FIFO is greater than or equal to
and
(FTH [10:0]).
It is possible to route
FIFO_STATUS2 (3Bh) (FTH) to the INT1 pin by writing in register
INT1_CTRL (0Dh) (INT1_FTH) = ‘1’ or to the INT2 pin by writing in register
(INT2_FTH) = ‘1’.
A full-flag interrupt can be enabled,
(INT_ FULL_FLAG) = '1', in order to indicate FIFO saturation and eventually read its content all at once.
If an overrun occurs, at least one of the oldest samples in FIFO has been overwritten and the OVER_RUN flag in
FIFO_STATUS2 (3Bh) is asserted.
In order to empty the FIFO before it is full, it is also possible to pull from FIFO the number of unread samples available in
(DIFF_FIFO [10:0]).
In Continuous-to-FIFO mode
FIFO_CTRL5 (0Ah) (FIFO_MODE_[2:0] = 011), FIFO behavior
changes according to the trigger event detected in one of the following interrupt registers
,
When the selected trigger bit is equal to '1', FIFO operates in FIFO mode.
When the selected trigger bit is equal to '0', FIFO operates in Continuous mode.
In Bypass-to-Continuous mode ( FIFO_CTRL5 (0Ah) (FIFO_MODE_[2:0] = '100'), data
measurement storage inside FIFO operates in Continuous mode when selected triggers in one of the following interrupt registers
,
D6D_SRC (1Dh) are equal to '1', otherwise FIFO content is
reset (Bypass mode).
DocID028475 Rev 7 35/114
114
Functionality
5.5.6
LSM6DSL
FIFO reading procedure
The data stored in FIFO are accessible from dedicated registers (
and
) and each FIFO sample is composed of 16 bits.
All FIFO status registers (
FIFO_STATUS2 (3Bh) , FIFO_STATUS3
) can be read at the start of a reading operation, minimizing the intervention of the application processor.
Saving data in the FIFO buffer is organized in four FIFO data sets consisting of 6 bytes each:
The 1 st
FIFO data set is reserved for gyroscope data;
The 2 nd
FIFO data set is reserved for accelerometer data;
The 3 rd
FIFO data set is reserved for the external sensor data stored in the registers from
to
The 4 th
FIFO data set can be alternately associated to the external sensor data stored in the registers from
to SENSORHUB12_REG (39h) , to the step
counter and timestamp info, or to the temperature sensor data.
36/114 DocID028475 Rev 7
LSM6DSL Digital interfaces
6.1 I
2
C/SPI interface
The registers embedded inside the LSM6DSL may be accessed through both the I
2
C and
SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode. The device is compatible with SPI modes 0 and 3.
The serial interfaces are mapped onto the same pins. To select/exploit the I
2
C interface, the
CS line must be tied high (i.e connected to Vdd_IO).
Pin name
CS
SCL/SPC
SDA/SDI/SDO
SDO/SA0
Table 10. Serial interface pin description
Pin description
SPI enable
I
2
C/SPI mode selection (1: SPI idle mode / I
2
C communication enabled;
0: SPI communication mode / I
2
C disabled)
I
2
C Serial Clock (SCL)
SPI Serial Port Clock (SPC)
I
2
C Serial Data (SDA)
SPI Serial Data Input (SDI)
3-wire Interface Serial Data Output (SDO)
SPI Serial Data Output (SDO)
I
2
C less significant bit of the device address
If the LSM6DSL is configured in Mode2, a master I 2 C line is available. The master serial interface is mapped in the following dedicated pins.
Pin name
MSCL
MSDA
MDRDY
Table 11. Master I 2 C pin details
Pin description
I
2
C serial clock master
I
2
C serial data master
I
2
C master external synchronization signal
DocID028475 Rev 7 37/114
114
Digital interfaces LSM6DSL
6.3 I
2
C serial interface
The LSM6DSL I
2
C is a bus slave. The I
2
C is employed to write the data to the registers, whose content can also be read back.
The relevant I
2
C terminology is provided in the table below.
Term
Transmitter
Receiver
Master
Slave
Table 12. I
2
C terminology
Description
The device which sends data to the bus
The device which receives data from the bus
The device which initiates a transfer, generates clock signals and terminates a transfer
The device addressed by the master
There are two signals associated with the I 2 C bus: the serial clock line (SCL) and the Serial
DAta line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both the lines must be connected to Vdd_IO through external pull-up resistors. When the bus is free, both the lines are high.
The I 2 C interface is implemeted with fast mode (400 kHz) I 2 C standards as well as with the standard mode.
In order to disable the I 2 C block, (I2C_disable) = 1 must be written in CTRL4_C (13h) .
6.3.1 I
2
C operation
The transaction on the bus is started through a START (ST) signal. A START condition is defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After this has been transmitted by the master, the bus is considered busy. The next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the master.
The Slave ADdress (SAD) associated to the LSM6DSL is 110101xb. The SDO/SA0 pin can be used to modify the less significant bit of the device address. If the SDO/SA0 pin is connected to the supply voltage, LSb is ‘1’ (address 1101011b); else if the SDO/SA0 pin is connected to ground, the LSb value is ‘0’ (address 1101010b). This solution permits to connect and address two different inertial modules to the same I 2 C bus.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each byte of data received.
The I 2 C embedded inside the LSM6DSL behaves like a slave device and the following protocol must be adhered to. After the start condition (ST) a slave address is sent, once a slave acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) is transmitted.
The increment of the address is configured by the CTRL3_C (12h) (IF_INC).
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LSM6DSL Digital interfaces
Command
Read
Write
Read
Write
The slave address is completed with a Read/Write bit. If the bit is ‘1’ (Read), a repeated
START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (Write) the master will transmit to the slave with direction unchanged. Table 12 explains how the
SAD+Read/Write bit pattern is composed, listing all the possible configurations.
SAD[6:1]
110101
110101
110101
110101
Table 13. SAD+Read/Write patterns
SAD[0] = SA0 R/W
1
1
0
0
1
0
1
0
SAD+R/W
11010101 (D5h)
11010100 (D4h)
11010111 (D7h)
11010110 (D6h)
Master
Slave
ST
Table 14. Transfer when master is writing one byte to slave
SAD + W SUB DATA
SAK SAK SAK
SP
Master
Slave
ST
Table 15. Transfer when master is writing multiple bytes to slave
SAD + W SUB DATA DATA
SAK SAK SAK SAK
SP
Master
Table 16. Transfer when master is receiving (reading) one byte of data from slave
ST SAD + W SUB SR SAD + R NMAK
Slave SAK SAK SAK DATA
SP
Table 17. Transfer when master is receiving (reading) multiple bytes of data from slave
Master ST SAD+W SUB SR SAD+R MAK MAK NMAK SP
Slave SAK SAK SAK DATA
DAT
A
DATA
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit
(MSb) first. If a receiver can’t receive another complete byte of data until it has performed some other function, it can hold the clock line, SCL LOW to force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and releases the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to receive because it is performing some real-time function) the data line must be left HIGH by the slave. The master can then abort the transfer. A LOW to HIGH transition on the SDA line while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be terminated by the generation of a STOP (SP) condition.
In the presented communication format MAK is Master acknowledge and NMAK is No
Master Acknowledge.
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Digital interfaces
6.4 SPI bus interface
LSM6DSL
The LSM6DSL SPI is a bus slave. The SPI allows writing and reading the registers of the device.
The serial interface communicates to the application using 4 wires: CS , SPC , SDI and SDO .
Figure 9. Read and write protocol (in mode 3)
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CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of the transmission and goes back high at the end. SPC is the serial port clock and it is controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and
SDO are, respectively, the serial port data input and output. Those lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC .
Both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in case of multiple read/write bytes. Bit duration is the time between two falling edges of SPC . The first bit (bit 0) starts at the first falling edge of SPC after the falling edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the rising edge of CS .
bit 0 : RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is read. In latter case, the chip will drive SDO at the start of bit 8.
bit 1-7 : address AD(6:0). This is the address field of the indexed register.
bit 8-15 : data DI(7:0) (write mode). This is the data that is written into the device (MSb first).
bit 8-15 : data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
In multiple read/write commands further blocks of 8 clock periods will be added. When the
CTRL3_C (12h) (IF_INC) bit is ‘0’, the address used to read/write data remains the same for every block. When the CTRL3_C (12h) (IF_INC) bit is ‘1’, the address used to read/write data is increased at every block.
The function and the behavior of SDI and SDO remain unchanged.
40/114 DocID028475 Rev 7
LSM6DSL Digital interfaces
Figure 10. SPI read protocol (in mode 3)
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The SPI Read command is performed with 16 clock pulses. A multiple byte read command is performed by adding blocks of 8 clock pulses to the previous one.
bit 0 : READ bit. The value is 1.
bit 1-7 : address AD(6:0). This is the address field of the indexed register. bit 8-15 : data DO(7:0) (read mode). This is the data that will be read from the device (MSb first).
bit 16-...
: data DO(...-8). Further data in multiple byte reads.
Figure 11. Multiple byte SPI read protocol (2-byte example) (in mode 3)
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DocID028475 Rev 7 41/114
114
Digital interfaces LSM6DSL
Figure 12. SPI write protocol (in mode 3)
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The SPI Write command is performed with 16 clock pulses. A multiple byte write command is performed by adding blocks of 8 clock pulses to the previous one.
bit 0 : WRITE bit. The value is 0.
bit 1 -7 : address AD(6:0). This is the address field of the indexed register.
bit 8-15 : data DI(7:0) (write mode). This is the data that is written inside the device (MSb first).
bit 16-... : data DI(...-8). Further data in multiple byte writes.
Figure 13. Multiple byte SPI write protocol (2-byte example) (in mode 3)
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42/114 DocID028475 Rev 7
LSM6DSL
6.4.3
Digital interfaces
SPI read in 3-wire mode
A 3-wire mode is entered by setting the CTRL3_C (12h) (SIM) bit equal to ‘1’ (SPI serial interface mode selection).
Figure 14. SPI read protocol in 3-wire mode (in mode 3)
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The SPI read command is performed with 16 clock pulses: bit 0 : READ bit. The value is 1.
bit 1-7 : address AD(6:0). This is the address field of the indexed register. bit 8-15 : data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
A multiple read command is also available in 3-wire mode.
DocID028475 Rev 7 43/114
114
Application hints LSM6DSL
7.1 LSM6DSL electrical connections in Mode 1
Figure 15. LSM6DSL electrical connections in Mode 1
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1. Leave pin electrically unconnected and soldered to PCB.
The device core is supplied through the Vdd line. Power supply decoupling capacitors (C1,
C2 = 100 nF ceramic) should be placed as near as possible to the supply pin of the device
(common design practice).
The functionality of the device and the measured acceleration/angular rate data is selectable and accessible through the SPI/I
2
C interface.
The functions, the threshold and the timing of the two interrupt pins for each sensor can be completely programmed by the user through the SPI/I
2
C interface.
44/114 DocID028475 Rev 7
LSM6DSL
7.2 LSM6DSL electrical connections in Mode 2
Figure 16. LSM6DSL electrical connections in Mode 2
Application hints
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1. Leave pin electrically unconnected and soldered to PCB.
The device core is supplied through the Vdd line. Power supply decoupling capacitors (C1,
C2 = 100 nF ceramic) should be placed as near as possible to the supply pin of the device
(common design practice).
The functionality of the device and the measured acceleration/angular rate data is selectable and accessible through the SPI/I
2
C interface.
The functions, the threshold and the timing of the two interrupt pins for each sensor can be completely programmed by the user through the SPI/I
2
C interface.
DocID028475 Rev 7 45/114
114
pin# Name
1
2
3
SDO
SA0
SDx
SCx
Mode 1 function
SPI 4-wire interface serial data output (SDO)
I
2
C least significant bit of the device address (SA0)
Connect to VDDIO or GND
Connect to VDDIO or GND
Table 18. Internal pin status
Mode 2 function Pin status Mode 1
SPI 4-wire interface serial data output (SDO)
I
2
C least significant bit of the device address (SA0)
Default: Input without pull-up.
Pull-up is enabled if bit SIM = 1
(SPI 3-wire) in reg 12h.
I
2
C serial data master (MSDA)
I
2
C serial clock master (MSCL)
7
8
4 INT1
5 Vdd_IO
6 GND
GND
Vdd
9 INT2
Programmable interrupt 1
Power supply for I/O pins
0 V supply
Programmable interrupt 1
Power supply for I/O pins
0 V supply
0 V supply
Power supply
0 V supply
Power supply
Programmable interrupt 2 (INT2)
/ Data enabled (DEN)
Programmable interrupt 2 (INT2)
/ Data enabled (DEN) /
I
2
C master external synchronization signal (MDRDY)
Default: input without pull-up.
Pull-up is enabled if bit
PULL_UP_EN = 1 in reg 1Ah.
Default: input without pull-up.
Pull-up is enabled if bit
PULL_UP_EN = 1 in reg 1Ah.
Default: Output forced to ground
Default: Output forced to ground
10
11
NC
NC
Leave unconnected
(1)
Default: Input with pull-up.
(See note below to disable pull-up)
Default: Input with pull-up.
(See note below to disable pull-up)
12 CS
I
2
C/SPI mode selection
(1:SPI idle mode /
I
2
C communication enabled;
0: SPI communication mode /
I
2
C disabled)
I
2
C/SPI mode selection
(1:SPI idle mode /
I
2
C communication enabled;
0: SPI communication mode /
I
2
C disabled)
Default: Input with pull-up.
Pull-up is disabled if bit I2C_disable = 1 in reg 13h.
Pin status Mode 2
Default: Input without pull-up.
Pull-up is enabled if bit SIM = 1
(SPI 3-wire) in reg 12h.
Default: input without pull-up.
Pull-up is enabled if bit
PULL_UP_EN = 1 in reg 1Ah.
Default: input without pull-up.
Pull-up is enabled if bit
PULL_UP_EN = 1 in reg 1Ah.
Default: Output forced to ground
Default: Output forced to ground
Default: Input with pull-up.
(See note below to disable pull-up)
Default: Input with pull-up.
(See note below to disable pull-up)
Default: Input with pull-up.
Pull-up is disabled if bit I2C_disable = 1 in reg 13h.
pin# Name
13
14
SCL
SDA
Table 18. Internal pin status (continued)
Mode 1 function Mode 2 function
I
2
C serial clock (SCL) / SPI serial port clock (SPC)
I
2
C serial data (SDA) / SPI serial data input (SDI) / 3-wire interface serial data output (SDO)
I
2
C serial clock (SCL) / SPI serial port clock (SPC)
I
2
C serial data (SDA) / SPI serial data input (SDI) / 3-wire interface serial data output (SDO)
Pin status Mode 1
Input without pull-up
Input without pull-up
1. Leave pin electrically unconnected and soldered to PCB.
Note:
Internal pull-up value is from 30 k Ω to 50 k Ω , depending on VDDIO.
The procedure to disable the pull-up on pins 10-11 is as follows:
1. AP side: write 80h in register at address 00h
2. AP side: write 01h in register at address 05h (disable the pull-up on pins 10 and 11 of LSM6DSL)
3. AP side: write 00h in register at address 00h
Pin status Mode 2
Input without pull-up
Input without pull-up
Register mapping LSM6DSL
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The table given below provides a list of the 8/16-bit registers embedded in the device and the corresponding addresses.
Name
RESERVED
FUNC_CFG_ACCESS
INT2_CTRL
WHO_AM_I
CTRL1_XL
CTRL2_G
CTRL3_C
CTRL4_C
CTRL5_C
CTRL6_C
CTRL7_G
CTRL8_XL
CTRL9_XL
CTRL10_C
RESERVED
RESERVED
SENSOR_SYNC_TIME_
FRAME
SENSOR_SYNC_RES_
RATIO
FIFO_CTRL1
FIFO_CTRL2
FIFO_CTRL3
FIFO_CTRL4
FIFO_CTRL5
DRDY_PULSE_CFG_G
RESERVED
INT1_CTRL r/w r/w r/w r/w r/w r/w r r/w r/w r/w r/w r/w r/w r/w r/w
r/w r/w r/w r/w r/w
Table 19. Registers address map
Register address
Type Default
Hex Binary
00 00000000 r/w
-
-
01
02
03
00000001
00000010
00000011
Comment
00000000
-
-
Reserved
Embedded functions configuration register
Reserved
Reserved r/w 04 00000100
05
12
13
14
15
0E
0F
10
11
16
17
18
19
0A
0B
0C
0D
06
07
08
09
00000101
00000110
00000111
00001000
00001001
00001010
00001011
00001100
00001101
00001110
00001111
00010000
00010001
00010010
00010011
00010100
00010101
00010110
0001 0111
00011000
00011001
00000000
00000000
Sensor sync configuration register
00000000
00000000
00000000
00000000
FIFO configuration registers
00000000
00000000
Reserved
00000000 INT1 pin control
00000000 INT2 pin control
01101010 Who I am ID
00000000
00000000
00000100
00000000
00000000
00000000
Accelerometer and gyroscope control registers
00000000
00000000
00000000
00000000
DocID028475 Rev 7
LSM6DSL Register mapping
Name
MASTER_CONFIG
WAKE_UP_SRC
TAP_SRC
D6D_SRC
STATUS_REG
RESERVED
OUT_TEMP_L
OUT_TEMP_H
OUTX_L_G
OUTX_H_G
OUTY_L_G
OUTY_H_G
OUTZ_L_G
OUTZ_H_G
OUTX_L_XL
OUTX_H_XL
OUTY_L_XL
OUTY_H_XL
OUTZ_L_XL
OUTZ_H_XL
SENSORHUB1_REG
SENSORHUB2_REG
SENSORHUB3_REG
SENSORHUB4_REG
SENSORHUB5_REG
SENSORHUB6_REG
SENSORHUB7_REG
SENSORHUB8_REG
SENSORHUB9_REG
SENSORHUB10_REG
SENSORHUB11_REG
SENSORHUB12_REG r r r r r r r r r r r r r r r r r r r r r r r r r r
-
Table 19. Registers address map (continued)
Register address
Type Default
Hex Binary r/w 1A 00011010 00000000
Comment
I
2
C master configuration register r r r 1B
1C
1D
00011011
00011100
00011101 output output output
Interrupt registers r 1E 00011110 output
Status data register for user interface
33
34
35
36
2F
30
31
32
37
38
39
2B
2C
2D
2E
27
28
29
2A
23
24
25
26
1F
20
21
22
00101111
00110000
00110001
00110010
00110011
00110100
00110101
00110110
00110111
00111000
00111001
00011111
00100000
00100001
00100010
00100011
00100100
00100101
00100110
00100111
00101000
00101001
00101010
00101011
00101100
00101101
00101110 output output output output output output output output output output output output output output output output output output output
output output output output output output output
Temperature output data registers
Gyroscope output registers for user interface
Accelerometer output registers
Sensor hub output registers
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114
Register mapping LSM6DSL
Name
FIFO_STATUS1
FIFO_STATUS2
FIFO_STATUS3
FIFO_STATUS4
FIFO_DATA_OUT_L
FIFO_DATA_OUT_H
TIMESTAMP0_REG
TIMESTAMP1_REG
TIMESTAMP2_REG
RESERVED
STEP_TIMESTAMP_L
STEP_TIMESTAMP_H
STEP_COUNTER_L
STEP_COUNTER_H
SENSORHUB13_REG
SENSORHUB14_REG
SENSORHUB15_REG
SENSORHUB16_REG
SENSORHUB17_REG
SENSORHUB18_REG
FUNC_SRC1
FUNC_SRC2
WRIST_TILT_IA
RESERVED
TAP_CFG
TAP_THS_6D
INT_DUR2
WAKE_UP_THS
WAKE_UP_DUR
FREE_FALL
MD1_CFG
MD2_CFG
MASTER_CMD_CODE
Table 19. Registers address map (continued)
Register address
Type Default
Hex Binary r/w r/w r/w r/w
r/w r/w r/w r/w r/w r r r r r r r r r r r r r
r r/w r r r r r r r
5B
5C
5D
5E
56-57
58
59
5A
5F
60
52
53
54
55
4E
4F
50
51
4A
4B
4C
4D
41
42
43-48
49
3D
3E
3F
40
3A
3B
3C
0100 1001
0100 1010
01001011
01001100
01001101
01001110
01001111
01010000
01010001
01010010
01010011
01010100
01010101
01011000
01011001
01011010
01011011
01011100
01011101
01011110
01011111
01100000
00111010
00111011
00111100
00111101
00111110
00111111
01000000
01000001
01000010
-
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000 output output output output output output output output output output
output output output output output output output output output output output output
Comment
FIFO status registers
FIFO data output registers
Timestamp output registers
Reserved
Step counter timestamp registers
Step counter output registers
Sensor hub output registers
Interrupt registers
Interrupt register
Reserved
Interrupt registers
50/114 DocID028475 Rev 7
LSM6DSL Register mapping
Name
SENS_SYNC_SPI_
ERROR_CODE
RESERVED
OUT_MAG_RAW_X_L
OUT_MAG_RAW_X_H
OUT_MAG_RAW_Y_L
OUT_MAG_RAW_Y_H
OUT_MAG_RAW_Z_L
OUT_MAG_RAW_Z_H
RESERVED
X_OFS_USR
Y_OFS_USR
Z_OFS_USR
RESERVED
Table 19. Registers address map (continued)
Register address
Type Default
Hex Binary r/w 61
r/w r/w r/w
r r r r
62-65 r r 66
67
68
69
6A
6B
6C-72
73
74
75
76-7F
0110 0001
01100110
01100111
01101000
01101001
01101010
01101011
01110011
01110100
01110101
00000000
Comment
Reserved output output output output
External magnetometer raw data output registers output output
Reserved -
00000000
00000000
00000000
-
Accelerometer user offset correction
Reserved
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Register description LSM6DSL
52/114
The device contains a set of registers which are used to control its behavior and to retrieve linear acceleration, angular rate and temperature data. The register addresses, made up of
7 bits, are used to identify them and to write the data through the serial interface.
Enable embedded functions register (r/w).
FUNC_
CFG_EN
0
(1)
Table 20. FUNC_CFG_ACCESS register
FUNC_
CFG_EN_B
0
(1)
0
(1)
0
(1)
1. This bit must be set to ‘0’ for the correct operation of the device.
0
(1)
0
(1)
FUNC_CFG_
EN
FUNC_CFG_
EN_B
Table 21. FUNC_CFG_ACCESS register description
Enable access to the embedded functions configuration registers bank A and B
(1)
.
Default value: 0. Refer to Table 22 .
Enable access to the embedded functions configuration register bank B
(1)
.
Default value: 0. Refer to Table 22 .
1. The embedded functions configuration registers details are available in
Section 10: Embedded functions register mapping ,
Section 11: Embedded functions registers description - Bank A , and
Embedded functions registers description - Bank B .
Table 22. Configuration of embedded functions register banks
FUNC_CFG_EN FUNC_CFG_EN_B Status of embedded register banks
1
1
0
0
0
1
0
1
Bank A and B disabled (default)
Forbidden
Bank A enabled
Bank B enabled
Sensor synchronization time frame register (r/w).
0
(1)
0
(1)
Table 23. SENSOR_SYNC_TIME_FRAME register
0
(1)
0
(1)
TPH_3 TPH_2 TPH_1
1. This bit must be set to ‘0’ for the correct operation of the device.
TPH_ [3:0]
TPH_0
Table 24. SENSOR_SYNC_TIME_FRAME register description
Sensor synchronization time frame with the step of 500 ms and full range of 5 s.
Unsigned 8-bit.
Default value: 0000 0000 (sensor sync disabled)
DocID028475 Rev 7
LSM6DSL Register description
Sensor synchronization resolution ratio (r/w)
0
(1)
0
(1)
Table 25. SENSOR_SYNC_RES_RATIO register
0
(1)
0
(1)
0
(1)
1. This bit must be set to ‘0’ for the correct operation of the device.
0
(1)
RR_1
RR_[1:0]
Table 26. SENSOR_SYNC_RES_RATIO register description
Resolution ratio of error code for sensor synchronization:
00: SensorSync, Res_Ratio = 2-11
01: SensorSync, Res_Ratio = 2-12
10: SensorSync, Res_Ratio = 2-13
11: SensorSync, Res_Ratio = 2-14
RR_0
FIFO control register (r/w).
FTH_7 FTH_6
Table 27. FIFO_CTRL1 register
FTH_5 FTH_4 FTH_3 FTH_2 FTH_1 FTH_0
FTH_[7:0]
Table 28. FIFO_CTRL1 register description
FIFO threshold level setting
(1)
. Default value: 0000 0000.
Watermark flag rises when the number of bytes written to FIFO after the next write is greater than or equal to the threshold level.
Minimum resolution for the FIFO is 1 LSB = 2 bytes (1 word) in FIFO
1. For a complete watermark threshold configuration, consider FTH_[10:8] in FIFO_CTRL2 (07h) .
DocID028475 Rev 7 53/114
114
Register description LSM6DSL
FIFO control register (r/w).
TIMER_PEDO
_FIFO_EN
TIMER_PEDO
_FIFO_DRDY
Table 29. FIFO_CTRL2 register
0
(1)
0
(1)
FIFO_
TEMP_EN
FTH10
1. This bit must be set to ‘0’ for the correct operation of the device.
FTH_9 FTH_8
TIMER_PEDO
_FIFO_EN
TIMER_PEDO
_FIFO_DRDY
FIFO_TEMP_EN
FTH_[10:8]
Table 30. FIFO_CTRL2 register description
Enable pedometer step counter and timestamp as 4 th
FIFO data set. Default: 0
(0: disable step counter and timestamp data as 4 th
FIFO data set;
1: enable step counter and timestamp data as 4 th
FIFO data set)
FIFO write mode
(1)
. Default: 0
(0: enable write in FIFO based on XL/Gyro data-ready;
1: enable write in FIFO at every step detected by step counter.)
Enable the temperature data storage in FIFO. Default: 0.
(0: temperature not included in FIFO; 1: temperature included in FIFO)
FIFO threshold level setting
(2)
. Default value: 0000
Watermark flag rises when the number of bytes written to FIFO after the next write is greater than or equal to the threshold level.
Minimum resolution for the FIFO is 1LSB = 2 bytes (1 word) in FIFO
1. This bit is effective if the DATA_VALID_SEL_FIFO bit of the
MASTER_CONFIG (1Ah) register is set to 0.
2. For a complete watermark threshold configuration, consider FTH_[7:0] in FIFO_CTRL1 (06h) .
54/114 DocID028475 Rev 7
LSM6DSL Register description
FIFO control register (r/w).
0
(1)
0
(1)
Table 31. FIFO_CTRL3 register
DEC_FIFO
_GYRO2
DEC_FIFO
_GYRO1
DEC_FIFO
_GYRO0
DEC_FIFO
_XL2
DEC_FIFO
_XL1
DEC_FIFO
_XL0
1. This bit must be set to ‘0’ for the correct operation of the device.
DEC_FIFO_GYRO [2:0]
Table 32. FIFO_CTRL3 register description
Gyro FIFO (first data set) decimation setting. Default: 000
For the configuration setting, refer to
.
DEC_FIFO_XL [2:0]
Accelerometer FIFO (second data set) decimation setting. Default: 000
For the configuration setting, refer to
.
100
101
110
111
000
001
010
011
Table 33. Gyro FIFO decimation setting
DEC_FIFO_GYRO [2:0] Configuration
Gyro sensor not in FIFO
No decimation
Decimation with factor 2
Decimation with factor 3
Decimation with factor 4
Decimation with factor 8
Decimation with factor 16
Decimation with factor 32
100
101
110
111
000
001
010
011
Table 34. Accelerometer FIFO decimation setting
DEC_FIFO_XL [2:0] Configuration
Accelerometer sensor not in FIFO
No decimation
Decimation with factor 2
Decimation with factor 3
Decimation with factor 4
Decimation with factor 8
Decimation with factor 16
Decimation with factor 32
DocID028475 Rev 7 55/114
114
Register description LSM6DSL
56/114
FIFO control register (r/w).
Table 35. FIFO_CTRL4 register
STOP_
ON_
FTH
ONLY_HIGH
_DATA
DEC_DS4
_FIFO2
DEC_DS4
_FIFO1
DEC_DS4
_FIFO0
DEC_DS3
_FIFO2
DEC_DS3
_FIFO1
DEC_DS3
_FIFO0
STOP_ON_FTH
ONLY_HIGH_DATA
DEC_DS4_FIFO[2:0]
DEC_DS3_FIFO[2:0]
Table 36. FIFO_CTRL4 register description
Enable FIFO threshold level use. Default value: 0.
(0: FIFO depth is not limited; 1: FIFO depth is limited to threshold level)
8-bit data storage in FIFO. Default: 0
(0: disable MSByte only memorization in FIFO for XL and Gyro;
1: enable MSByte only memorization in FIFO for XL and Gyro in FIFO)
Fourth FIFO data set decimation setting. Default: 000
For the configuration setting, refer to
Third FIFO data set decimation setting. Default: 000
For the configuration setting, refer to
100
101
110
111
000
001
010
011
Table 37. Fourth FIFO data set decimation setting
DEC_DS4_FIFO[2:0] Configuration
Fourth FIFO data set not in FIFO
No decimation
Decimation with factor 2
Decimation with factor 3
Decimation with factor 4
Decimation with factor 8
Decimation with factor 16
Decimation with factor 32
100
101
110
111
000
001
010
011
Table 38. Third FIFO data set decimation setting
DEC_DS3_FIFO[2:0] Configuration
Third FIFO data set not in FIFO
No decimation
Decimation with factor 2
Decimation with factor 3
Decimation with factor 4
Decimation with factor 8
Decimation with factor 16
Decimation with factor 32
DocID028475 Rev 7
LSM6DSL Register description
FIFO control register (r/w).
0
(1)
ODR_
FIFO_3
ODR_
FIFO_2
Table 39. FIFO_CTRL5 register
ODR_
FIFO_1
ODR_
FIFO_0
FIFO_
MODE_2
1. This bit must be set to ‘0’ for the correct operation of the device.
FIFO_
MODE_1
FIFO_
MODE_0
ODR_FIFO_[3:0]
FIFO_MODE_[2:0]
Table 40. FIFO_CTRL5 register description
FIFO ODR selection, setting FIFO_MODE also. Default: 0000
For the configuration setting, refer to
FIFO mode selection bits, setting ODR_FIFO also. Default value: 000
For the configuration setting, refer to
ODR_FIFO_[3:0]
Table 41. FIFO ODR selection
Configuration
(1)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
FIFO disabled
FIFO ODR is set to 12.5 Hz
FIFO ODR is set to 26 Hz
FIFO ODR is set to 52 Hz
FIFO ODR is set to 104 Hz
FIFO ODR is set to 208 Hz
FIFO ODR is set to 416 Hz
FIFO ODR is set to 833 Hz
FIFO ODR is set to 1.66 kHz
FIFO ODR is set to 3.33 kHz
FIFO ODR is set to 6.66 kHz
1. If the device is working at an ODR slower than the one selected, FIFO ODR is limited to that ODR value.
Moreover, these bits are effective if both the DATA_VALID_SEL_FIFO bit of
the TIMER_PEDO_FIFO_DRDY bit of
are set to 0.
FIFO_MODE_[2:0]
000
001
010
011
100
101
110
111
Table 42. FIFO mode selection
Configuration mode
Bypass mode. FIFO disabled.
FIFO mode. Stops collecting data when FIFO is full.
Reserved
Continuous mode until trigger is deasserted, then FIFO mode.
Bypass mode until trigger is deasserted, then Continuous mode.
Reserved
Continuous mode. If the FIFO is full, the new sample overwrites the older one.
Reserved
DocID028475 Rev 7 57/114
114
Register description LSM6DSL
DataReady configuration register (r/w).
DRDY_
PULSED
0
(1)
Table 43. DRDY_PULSE_CFG_G register
0
(1)
0
(1)
0
(1)
1. This bit must be set to ‘0’ for the correct operation of the device.
0
(1)
0
(1)
INT2_
WRIST_TILT
Table 44. DRDY_PULSE_CFG_G register description
DRDY_PULSED Enable pulsed DataReady mode. Default value: 0
(0: DataReady latched mode. Returns to 0 only after output data have been read;
1: DataReady pulsed mode. The DataReady pulses are 75 μ s long.)
INT2_
WRIST_TILT
Wrist tilt interrupt on INT2 pad. Default value: 0
(0: disabled; 1: enabled)
INT1 pad control register (r/w).
Each bit in this register enables a signal to be carried through INT1. The pad’s output will supply the OR combination of the selected signals.
INT1_STEP_
DETECTOR
INT1_SIGN
_MOT
Table 45. INT1_CTRL register
INT1_FULL
_FLAG
INT1_
FIFO_OVR
INT1_
FTH
INT1_
BOOT
INT1_
DRDY_G
INT1_
DRDY_XL
INT1_ STEP_
DETECTOR
INT1_SIGN_MOT
INT1_FULL_FLAG
INT1_FIFO_OVR
INT1_FTH
INT1_ BOOT
INT1_DRDY_G
INT1_DRDY_XL
Table 46. INT1_CTRL register description
Pedometer step recognition interrupt enable on INT1 pad. Default value: 0
(0: disabled; 1: enabled)
Significant motion interrupt enable on INT1 pad. Default value: 0
(0: disabled; 1: enabled)
FIFO full flag interrupt enable on INT1 pad. Default value: 0
(0: disabled; 1: enabled)
FIFO overrun interrupt on INT1 pad. Default value: 0
(0: disabled; 1: enabled)
FIFO threshold interrupt on INT1 pad. Default value: 0
(0: disabled; 1: enabled)
Boot status available on INT1 pad. Default value: 0
(0: disabled; 1: enabled)
Gyroscope Data Ready on INT1 pad. Default value: 0
(0: disabled; 1: enabled)
Accelerometer Data Ready on INT1 pad. Default value: 0
(0: disabled; 1: enabled)
58/114 DocID028475 Rev 7
LSM6DSL Register description
INT2 pad control register (r/w).
Each bit in this register enables a signal to be carried through INT2. The pad’s output will supply the OR combination of the selected signals.
INT2_STEP
_DELTA
INT2_STEP_
COUNT_OV
Table 47. INT2_CTRL register
INT2_
FULL_FLAG
INT2_
FIFO_OVR
INT2_
FTH
INT2_
DRDY
_TEMP
INT2_
DRDY_G
INT2_
DRDY_XL
INT2_STEP_DELTA
INT2_STEP_COUNT_OV
INT2_ FULL_FLAG
INT2_FIFO_OVR
INT2_FTH
INT2_DRDY_TEMP
INT2_DRDY_G
INT2_DRDY_XL
Table 48. INT2_CTRL register description
Pedometer step recognition interrupt on delta time pad. Default value: 0
(1)
enable on INT2
(0: disabled; 1: enabled)
Step counter overflow interrupt enable on INT2 pad. Default value: 0
(0: disabled; 1: enabled)
FIFO full flag interrupt enable on INT2 pad. Default value: 0
(0: disabled; 1: enabled)
FIFO overrun interrupt on INT2 pad. Default value: 0
(0: disabled; 1: enabled)
FIFO threshold interrupt on INT2 pad. Default value: 0
(0: disabled; 1: enabled)
Temperature Data Ready on INT2 pad. Default value: 0
(0: disabled; 1: enabled)
Gyroscope Data Ready on INT2 pad. Default value: 0
(0: disabled; 1: enabled)
Accelerometer Data Ready on INT2 pad. Default value: 0
(0: disabled; 1: enabled)
1. Delta time value is defined in register
Who_AM_I register (r). This register is a read-only register. Its value is fixed at 6Ah.
0 1 1
Table 49. WHO_AM_I register
0 1 0 1 0
DocID028475 Rev 7 59/114
114
Register description LSM6DSL
Linear acceleration sensor control register 1 (r/w).
Table 50. CTRL1_XL register
ODR_XL3 ODR_XL2 ODR_XL1 ODR_XL0 FS_XL1 FS_XL0
LPF1_BW_
SEL
BW0_XL
ODR_XL [3:0]
FS_XL [1:0]
LPF1_BW_SEL
BW0_XL
Table 51. CTRL1_XL register description
Output data rate and power mode selection . Default value: 0000 (see
Accelerometer full-scale selection. Default value: 00.
(00: ±2 g ; 01: ±16 g ; 10: ±4 g ; 11: ±8 g )
Accelerometer digital LPF (LPF1) bandwidth selection. For bandwidth selection refer to
Accelerometer analog chain bandwidth selection (only for accelerometer
ODR ≥ 1.67 kHz).
(0: BW @ 1.5 kHz;
1: BW @ 400 Hz)
1
1
0
0
1
1
0
0
0
0
0
1
0
ODR_
XL3
ODR_
XL2
ODR_
XL1
Table 52. Accelerometer ODR register setting
ODR_
XL0
ODR selection [Hz] when
XL_HM_MODE = 1
ODR selection [Hz] when
XL_HM_MODE = 0
0
0
1
1
0
1
1
1
0
0
0
0
0
0
0
1
1
1 x
0
0
1
1
0
1
0
0
1
0
1
0 x
0
1
0
1
0
1
1
Power-down
1.6 Hz (low power only)
12.5 Hz (low power)
26 Hz (low power)
52 Hz (low power)
104 Hz (normal mode)
208 Hz (normal mode)
416 Hz (high performance)
833 Hz (high performance)
1.66 kHz (high performance)
3.33 kHz (high performance)
6.66 kHz (high performance)
Not allowed
Power-down
12.5 Hz (high performance)
12.5 Hz (high performance)
26 Hz (high performance)
52 Hz (high performance)
104 Hz (high performance)
208 Hz (high performance)
416 Hz (high performance)
833 Hz (high performance)
1.66 kHz (high performance)
3.33 kHz (high performance)
6.66 kHz (high performance)
Not allowed
60/114 DocID028475 Rev 7
LSM6DSL Register description
Angular rate sensor control register 2 (r/w).
Table 53. CTRL2_G register
ODR_G3 ODR_G2 ODR_G1 ODR_G0 FS_G1 FS_G0
1. This bit must be set to ‘0’ for the correct operation of the device.
ODR_G [3:0]
FS_G [1:0]
FS_125
Table 54. CTRL2_G register description
Gyroscope output data rate selection . Default value: 0000
(Refer to
Gyroscope full-scale selection. Default value: 00
(00: 250 dps; 01: 500 dps; 10: 1000 dps; 11: 2000 dps)
Gyroscope full-scale at 125 dps. Default value: 0
(0: disabled; 1: enabled)
FS_125 0
(1)
ODR_G3 ODR_G2 ODR_G1 ODR_G0
0
0
0
0
0
0
0
1
1
0
1
1
1
1
0
1
0
0
0
0
0
1
0
0
Table 55. Gyroscope ODR configuration setting
1
0
1
0
0
1
0
1
0
1
0
1
0
1
1
0
0
0
1
0
1
1
0
1
ODR [Hz] when
G_HM_MODE = 1
Power down
12.5 Hz (low power)
26 Hz (low power)
52 Hz (low power)
104 Hz (normal mode)
208 Hz (normal mode)
416 Hz (high performance)
833 Hz (high performance)
1.66 kHz (high performance)
3.33 kHz (high performance
6.66 kHz (high performance
Not available
ODR [Hz] when
G_HM_MODE = 0
Power down
12.5 Hz (high performance)
26 Hz (high performance)
52 Hz (high performance)
104 Hz (high performance)
208 Hz (high performance)
416 Hz (high performance)
833 Hz (high performance)
1.66 kHz (high performance)
3.33 kHz (high performance)
6.66 kHz (high performance)
Not available
DocID028475 Rev 7 61/114
114
Register description LSM6DSL
Control register 3 (r/w).
BOOT BDU
Table 56. CTRL3_C register
H_LACTIVE PP_OD SIM IF_INC BLE SW_RESET
BOOT
BDU
H_LACTIVE
PP_OD
SIM
IF_INC
BLE
SW_RESET
Table 57. CTRL3_C register description
Reboot memory content. Default value: 0
(0: normal mode; 1: reboot memory content)
Block Data Update. Default value: 0
(0: continuous update; 1: output registers not updated until MSB and LSB have been read)
Interrupt activation level. Default value: 0
(0: interrupt output pads active high; 1: interrupt output pads active low)
Push-pull/open-drain selection on INT1 and INT2 pads. Default value: 0
(0: push-pull mode; 1: open-drain mode)
SPI Serial Interface Mode selection. Default value: 0
(0: 4-wire interface; 1: 3-wire interface).
Register address automatically incremented during a multiple byte access with a serial interface (I
2
C or SPI). Default value: 1
(0: disabled; 1: enabled)
Big/Little Endian Data selection. Default value 0
(0: data LSB @ lower address; 1: data MSB @ lower address)
Software reset. Default value: 0
(0: normal mode; 1: reset device)
This bit is automatically cleared.
62/114 DocID028475 Rev 7
LSM6DSL Register description
Control register 4 (r/w).
DEN_
XL_EN
SLEEP
INT2_on_
INT1
Table 58. CTRL4_C register
DEN_DRDY
_INT1
DRDY_
MASK
I2C_disable LPF1_SEL_G 0
(1)
1. This bit must be set to ‘0’ for the correct operation of the device.
Table 59. CTRL4_C register description
DEN_XL_EN Extend DEN functionality to accelerometer sensor. Default value: 0
(0: disabled; 1: enabled)
SLEEP
DEN_DRDY
_INT1
Gyroscope sleep mode enable. Default value: 0
(0: disabled; 1: enabled)
DEN DRDY signal on INT1 pad. Default value: 0
(0: disabled; 1: enabled)
INT2_on_INT1 All interrupt signals available on INT1 pad enable. Default value: 0
(0: interrupt signals divided between INT1 and INT2 pads;
1: all interrupt signals in logic or on INT1 pad)
DRDY_MASK Configuration 1 data available enable bit. Default value: 0
(0: DA timer disabled; 1: DA timer enabled)
I2C_disable Disable I
2
C interface. Default value: 0
(0: both I
2
C and SPI enabled; 1: I
2
C disabled, SPI only enabled)
LPF1_SEL_G Enable gyroscope digital LPF1. The bandwidth can be selected through
FTYPE[1:0] in
.
(0: disabled; 1: enabled)
Control register 5 (r/w).
Table 60. CTRL5_C register
ROUNDING2 ROUNDING1 ROUNDING0
DEN
_LH
ST1_G ST0_G ST1_XL ST0_XL
Table 61. CTRL5_C register description
ROUNDING[2:0] Circular burst-mode (rounding) read from the output registers.
Default value: 000
(000: no rounding; Others: refer to
DEN_LH
ST_G [1:0]
ST_XL [1:0]
DEN active level configuration. Default value: 0
(0: active low; 1: active high)
Angular rate sensor self-test enable. Default value: 00
(00: Self-test disabled; Other: refer to
Linear acceleration sensor self-test enable. Default value: 00
(00: Self-test disabled; Other: refer to
DocID028475 Rev 7 63/114
114
Register description LSM6DSL
ROUNDING[2:0]
000
001
010
011
100
101
110
111
Table 62. Output registers rounding pattern
Rounding pattern
No rounding
Accelerometer only
Gyroscope only
Gyroscope + accelerometer
Registers from
to
Accelerometer + registers from SENSORHUB1_REG (2Eh)
to
Gyroscope + accelerometer + registers from
to
SENSORHUB6_REG (33h) and registers from SENSORHUB7_REG (34h)
to
Gyroscope + accelerometer + registers from
to
1
1
0
0
ST1_G
Table 63. Angular rate sensor self-test mode selection
ST0_G Self-test mode
0
1
0
1
Normal mode
Positive sign self-test
Not allowed
Negative sign self-test
1
1
0
0
Table 64. Linear acceleration sensor self-test mode selection
ST1_XL ST0_XL Self-test mode
0
1
0
1
Normal mode
Positive sign self-test
Negative sign self-test
Not allowed
64/114 DocID028475 Rev 7
LSM6DSL Register description
Angular rate sensor control register 6 (r/w).
Table 65. CTRL6_C register
TRIG_EN LVL_EN LVL2_EN XL_HM_MODE
USR_
OFF_W
1. This bit must be set to ‘0’ for the correct operation of the device.
TRIG_EN
LVL_EN
LVL2_EN
XL_HM_MODE
USR_OFF_W
FTYPE[1:0]
0
(1)
FTYPE_1 FTYPE_0
Table 66. CTRL6_C register description
DEN data edge-sensitive trigger enable. Refer to Table 67
.
DEN data level-sensitive trigger enable. Refer to
DEN level-sensitive latched enable. Refer to Table 67
.
High-performance operating mode disable for accelerometer. Default value: 0
(0: high-performance operating mode enabled;
1: high-performance operating mode disabled)
Weight of XL user offset bits of registers
X_OFS_USR (73h) , Y_OFS_USR (74h)
,
0 = 2
-10 g /LSB
1 = 2
-6 g /LSB
Gyroscope's low-pass filter (LPF1) bandwidth selection
Table 68 shows the selectable bandwidth values.
Table 67. Trigger mode selection
TRIG_EN, LVL1_EN, LVL2_EN Trigger mode
100
010
011
110
Edge-sensitive trigger mode is selected
Level-sensitive trigger mode is selected
Level-sensitive latched mode is selected
Level-sensitive FIFO enable mode is selected
FTYPE[1:0]
00
01
10
11
Table 68. Gyroscope LPF1 bandwidth selection
Bandwidth
ODR = 800 Hz
245 Hz
195 Hz
155 Hz
293 Hz
ODR = 1.6 kHz
315 Hz
224 Hz
168 Hz
505 Hz
ODR = 3.3 kHz
343 Hz
234 Hz
172 Hz
925 Hz
ODR = 6.6 kHz
351 Hz
237 Hz
173 Hz
937 Hz
DocID028475 Rev 7 65/114
114
Register description LSM6DSL
Angular rate sensor control register 7 (r/w).
Table 69. CTRL7_G register
G_HM_MODE HP_EN_G HPM1_G HPM0_G 0
(1)
ROUNDING_
STATUS
0
(1)
0
(1)
1. This bit must be set to ‘0’ for the correct operation of the device.
G_HM_MODE
HP_EN_G
HPM_G[1:0]
ROUNDING_
STATUS
Table 70. CTRL7_G register description
High-performance operating mode disable for gyroscope(1). Default: 0
(0: high-performance operating mode enabled;
1: high-performance operating mode disabled)
Gyroscope digital high-pass filter enable. The filter is enabled only if the gyro is in HP mode. Default value: 0
(0: HPF disabled; 1: HPF enabled)
Gyroscope digital HP filter cutoff selection. Default: 00
(00 = 16 mHz
01 = 65 mHz
10 = 260 mHz
11 = 1.04 Hz)
Source register rounding function on WAKE_UP_SRC (1Bh), TAP_SRC (1Ch),
D6D_SRC (1Dh), STATUS_REG (1Eh), and FUNC_SRC (53h).
Default value: 0
(0: Rounding disabled; 1: Rounding enabled)
66/114
Linear acceleration sensor control register 8 (r/w).
LPF2_XL_
EN
HPCF_
XL1
Table 71. CTRL8_XL register
HPCF_
XL0
HP_REF
_MODE
INPUT_
COMPO
SITE
HP_SLOPE_X
L_EN
1. This bit must be set to ‘0’ for the correct operation of the device.
0
(1)
LOW_PASS
_ON_6D
LPF2_XL_EN
Table 72. CTRL8_XL register description
Accelerometer low-pass filter LPF2 selection. Refer to
HPCF_XL[1:0]
HP_REF_MODE
Accelerometer LPF2 and high-pass filter configuration and cutoff
.
Enable HP filter reference mode. Default value: 0
(0: disabled; 1: enabled
(1)
)
INPUT_COMPOSITE
Composite filter input selection. Default: 0
(0: ODR/2 low pass filtered sent to composite filter (default)
1: ODR/4 low pass filtered sent to composite filter)
HP_SLOPE_XL_EN Accelerometer slope filter / high-pass filter selection. Refer to
LOW_PASS_ON_6D LPF2 on 6D function selection. Refer to
1. When enabled, the first output data has to be discarded.
DocID028475 Rev 7
LSM6DSL Register description
HP_SLOPE_
XL_EN
Table 73. Accelerometer bandwidth selection
LPF2_XL_EN LPF1_BW_SEL HPCF_XL[1:0]
INPUT_
COMPOSITE
0
(low-pass path)
1
(high-pass path)
(1)
(2)
0
1
-
0
1
-
-
01
10
11
00
-
-
00
01
10
11
-
-
1 (low noise)
0 (low latency)
0
1. The bandwidth column is related to LPF1 if LPF2_XL_EN = 0 or to LPF2 if LPF2_XL_EN = 1.
2. The bandwidth column is related to the slope filter if HPCF_XL[1:0] = 00 or to the HP filter if
HPCF_XL[1:0] = 01/10/11.
Bandwidth
ODR/2
ODR/4
ODR/50
ODR/100
ODR/9
ODR/400
ODR/4
ODR/100
ODR/9
ODR/400
Linear acceleration sensor control register 9 (r/w).
DEN_X DEN_Y
Table 74. CTRL9_XL register
DEN_Z DEN_XL_G 0
(1)
1. This bit must be set to ‘0’ for the correct operation of the device.
SOFT_EN 0
(1)
0
(1)
DEN_X
DEN_Y
DEN_Z
DEN_XL_G
SOFT_EN
Table 75. CTRL9_XL register description
DEN value stored in LSB of X-axis. Default value: 1
(0: DEN not stored in X-axis LSB; 1: DEN stored in X-axis LSB)
DEN value stored in LSB of Y-axis. Default value: 1
(0: DEN not stored in Y-axis LSB; 1: DEN stored in Y-axis LSB)
DEN value stored in LSB of Z-axis. Default value: 1
(0: DEN not stored in Z-axis LSB; 1: DEN stored in Z-axis LSB)
DEN stamping sensor selection. Default value: 0
(0: DEN pin info stamped in the gyroscope axis selected by bits [7:5];
1: DEN pin info stamped in the accelerometer axis selected by bits [7:5])
Enable soft-iron correction algorithm for magnetometer
(1)
. Default value: 0
(0: soft-iron correction algorithm disabled;
1: soft-iron correction algorithm enabled)
1. This bit is effective if the IRON_EN bit of
MASTER_CONFIG (1Ah) and the FUNC_EN bit of CTRL10_C
DocID028475 Rev 7 67/114
114
Register description LSM6DSL
Control register 10 (r/w).
WRIST_
TILT_EN
0
(1)
TIMER_
EN
Table 76. CTRL10_C register
PEDO_
EN
TILT_
EN
FUNC_EN
1. This bit must be set to ‘0’ for the correct operation of the device.
PEDO_RST
_STEP
SIGN_
MOTION_EN
WRIST_TILT_EN
TIMER_EN
PEDO_EN
TILT_EN
FUNC_EN
PEDO_RST_
STEP
SIGN_MOTION_EN
Table 77. CTRL10_C register description
Enable wrist tilt algorithm
(1)(2)
. Default value: 0
(0: wrist tilt algorithm disabled;
1: wrist tilt algorithm enabled)
Enable timestamp count. The count is saved in TIMESTAMP0_REG (40h)
,
and
. Default: 0
(0: timestamp count disabled; 1: timestamp count enabled)
. Default value: 0
(0: pedometer algorithm disabled;
1: pedometer algorithm enabled)
Enable tilt calculation
(1)
.
Enable embedded functionalities (pedometer, tilt, significant motion detection, sensor hub and ironing). Default value: 0
(0: disable functionalities of embedded functions and accelerometer filters;
1: enable functionalities of embedded functions and accelerometer filters)
Reset pedometer step counter. Default value: 0
(0: disabled; 1: enabled)
Enable significant motion detection function
(1)
. Default value: 0
(0: disabled; 1: enabled)
1. This is effective if the FUNC_EN bit is set to '1'.
2. By default, the wrist tilt algorithm is applied to the positive X-axis.
Master configuration register (r/w).
DRDY_ON
_INT1
DATA_VALID
_SEL_FIFO
Table 78. MASTER_CONFIG register
0
(1)
START_
CONFIG
PULL_UP
_EN
PASS_
THROUGH
_MODE
1. This bit must be set to ‘0’ for the correct operation of the device.
IRON_EN
MASTER_
ON
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LSM6DSL Register description
DRDY_ON_
INT1
Table 79. MASTER_CONFIG register description
Manage the Master DRDY signal on INT1 pad. Default: 0
(0: disable Master DRDY on INT1; 1: enable Master DRDY on INT1)
DATA_VALID_
SEL_FIFO
Selection of FIFO data-valid signal. Default value: 0
(0: data-valid signal used to write data in FIFO is the XL/Gyro data-ready or step detection
(1)
;
1: data-valid signal used to write data in FIFO is the sensor hub data-ready)
START_
CONFIG
PULL_UP_EN
PASS_THROUGH
_MODE
IRON_EN
MASTER_ON
Sensor Hub trigger signal selection. Default value: 0
(0: Sensor hub signal is the XL/Gyro data-ready;
1: Sensor hub signal external from INT2 pad.)
Auxiliary I
2
C pull-up. Default value: 0
(0: internal pull-up on auxiliary I
2
C line disabled;
1: internal pull-up on auxiliary I
2
C line enabled)
I
2
C interface pass-through. Default value: 0
(0: pass-through disabled; 1: pass-through enabled)
Enable hard-iron correction algorithm for magnetometer
(2)
. Default value: 0
(0:hard-iron correction algorithm disabled;
1: hard-iron correction algorithm enabled)
Sensor hub I
2
C master enable
(2)
. Default: 0
(0: master I
2
C of sensor hub disabled; 1: master I
2
C of sensor hub enabled)
1. If the TIMER_PEDO_FIFO_DRDY bit in
FIFO_CTRL2 (07h) is set to 0, the trigger for writing data in FIFO
is XL/Gyro data-ready, otherwise it's the step detection.
2. This is effective if the FUNC_EN bit is set to '1'.
Wake up interrupt source register (r).
0 0
Table 80. WAKE_UP_SRC register
FF_IA
SLEEP_
STATE_IA
WU_IA X_WU
FF_IA
SLEEP_
STATE_IA
WU_IA
X_WU
Y_WU
Z_WU
Y_WU Z_WU
Table 81. WAKE_UP_SRC register description
Free-fall event detection status. Default: 0
(0: free-fall event not detected; 1: free-fall event detected)
Sleep event status. Default value: 0
(0: sleep event not detected; 1: sleep event detected)
Wakeup event detection status. Default value: 0
(0: wakeup event not detected; 1: wakeup event detected.)
Wakeup event detection status on X-axis. Default value: 0
(0: wakeup event on X-axis not detected; 1: wakeup event on X-axis detected)
Wakeup event detection status on Y-axis. Default value: 0
(0: wakeup event on Y-axis not detected; 1: wakeup event on Y-axis detected)
Wakeup event detection status on Z-axis. Default value: 0
(0: wakeup event on Z-axis not detected; 1: wakeup event on Z-axis detected)
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114
Register description LSM6DSL
Tap source register (r).
0 TAP_IA
Table 82. TAP_SRC register
SINGLE_
TAP
DOUBLE_
TAP
TAP_SIGN X_TAP Y_TAP
TAP_IA
SINGLE_TAP
DOUBLE_TAP
TAP_SIGN
X_TAP
Y_TAP
Z_TAP
Table 83. TAP_SRC register description
Tap event detection status. Default: 0
(0: tap event not detected; 1: tap event detected)
Single-tap event status. Default value: 0
(0: single tap event not detected; 1: single tap event detected)
Double-tap event detection status. Default value: 0
(0: double-tap event not detected; 1: double-tap event detected.)
Sign of acceleration detected by tap event. Default: 0
(0: positive sign of acceleration detected by tap event;
1: negative sign of acceleration detected by tap event)
Tap event detection status on X-axis. Default value: 0
(0: tap event on X-axis not detected; 1: tap event on X-axis detected)
Tap event detection status on Y-axis. Default value: 0
(0: tap event on Y-axis not detected; 1: tap event on Y-axis detected)
Tap event detection status on Z-axis. Default value: 0
(0: tap event on Z-axis not detected; 1: tap event on Z-axis detected)
Z_TAP
70/114 DocID028475 Rev 7
LSM6DSL Register description
Portrait, landscape, face-up and face-down source register (r)
DEN_
DRDY
D6D_IA ZH
Table 84. D6D_SRC register
ZL YH YL XH XL
DEN_
DRDY
D6D_
IA
ZH
ZL
YH
YL
XH
XL
Table 85. D6D_SRC register description
DEN data-ready signal. It is set high when data output is related to the data coming from a
DEN active condition.
(1)
Interrupt active for change position portrait, landscape, face-up, face-down. Default value: 0
(0: change position not detected; 1: change position detected)
Z-axis high event (over threshold). Default value: 0
(0: event not detected; 1: event (over threshold) detected)
Z-axis low event (under threshold). Default value: 0
(0: event not detected; 1: event (under threshold) detected)
Y-axis high event (over threshold). Default value: 0
(0: event not detected; 1: event (over-threshold) detected)
Y-axis low event (under threshold). Default value: 0
(0: event not detected; 1: event (under threshold) detected)
X-axis high event (over threshold). Default value: 0
(0: event not detected; 1: event (over threshold) detected)
X-axis low event (under threshold). Default value: 0
(0: event not detected; 1: event (under threshold) detected)
1. The DEN data-ready signal can be latched or pulsed depending on the value of the dataready_pulsed bit of the
DRDY_PULSE_CFG_G (0Bh) register.
The STATUS_REG register is read by the SPI/I
2
C interface (r).
TDA
GDA
0
XLDA
0 0
Table 86. STATUS_REG register
0 0 TDA
Table 87. STATUS_REG register description
Temperature new data available. Default: 0
(0: no set of data is available at temperature sensor output;
1: a new set of data is available at temperature sensor output)
Gyroscope new data available. Default value: 0
(0: no set of data available at gyroscope output;
1: a new set of data is available at gyroscope output)
Accelerometer new data available. Default value: 0
(0: no set of data available at accelerometer output;
1: a new set of data is available at accelerometer output)
GDA XLDA
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114
Register description LSM6DSL
9.28 OUT_TEMP_L (20h), OUT_TEMP_H (21h)
Temperature data output register (r). L and H registers together express a 16-bit word in two’s complement.
Temp7 Temp6
Table 88. OUT_TEMP_L register
Temp5 Temp4 Temp3 Temp2 Temp1
Temp15 Temp14
Table 89. OUT_TEMP_H register
Temp13 Temp12 Temp11 Temp10 Temp9
Temp[15:0]
Table 90. OUT_TEMP register description
Temperature sensor output data
The value is expressed as two’s complement sign extended on the MSB.
Temp0
Temp8
Angular rate sensor pitch axis (X) angular rate output register (r). The value is expressed as a 16-bit word in two’s complement.
Data are according to the full-scale and ODR settings ( CTRL2_G (11h) ) of the gyro user
interface.
D7
D[7:0]
D6 D5
Table 91. OUTX_L_G register
D4 D3 D2 D1 D0
Table 92. OUTX_L_G register description
Pitch axis (X) angular rate value (LSbyte)
D[15:0] expressed in two’s complement and its value depends on the interface used:
SPI1/I
2
C: Gyro UI chain pitch axis output
Angular rate sensor pitch axis (X) angular rate output register (r). The value is expressed as a 16-bit word in two’s complement.
Data are according to the full-scale and ODR settings ( CTRL2_G (11h) ) of the gyro user
interface.
D15
D[15:8]
D14 D13
Table 93. OUTX_H_G register
D12 D11 D10 D9 D8
Table 94. OUTX_H_G register description
Pitch axis (X) angular rate value (MSbyte)
D[15:0] expressed in two’s complement and its value depends on the interface used:
SPI1/I
2
C: Gyro UI chain pitch axis output
72/114 DocID028475 Rev 7
LSM6DSL Register description
Angular rate sensor roll axis (Y) angular rate output register (r). The value is expressed as a
16-bit word in two’s complement.
Data are according to the full-scale and ODR settings ( CTRL2_G (11h) ) of the gyro user
interface.
D7
D[7:0]
D6 D5
Table 95. OUTY_L_G register
D4 D3 D2 D1 D0
Table 96. OUTY_L_G register description
Roll axis (Y) angular rate value (LSbyte)
D[15:0] expressed in two’s complement and its value depends on the interface used:
SPI1/I
2
C: Gyro UI chain roll axis output
Angular rate sensor roll axis (Y) angular rate output register (r). The value is expressed as a
16-bit word in two’s complement.
Data are according to the full-scale and ODR settings ( CTRL2_G (11h) ) of the gyro user
interface.
D15
D[15:8]
D14 D13
Table 97. OUTY_H_G register
D12 D11 D10 D9 D8
Table 98. OUTY_H_G register description
Roll axis (Y) angular rate value (MSbyte)
D[15:0] expressed in two’s complement and its value depends on the interface used:
SPI1/I
2
C: Gyro UI chain roll axis output
Angular rate sensor yaw axis (Z) angular rate output register (r). The value is expressed as a 16-bit word in two’s complement.
Data are according to the full-scale and ODR settings ( CTRL2_G (11h) ) of the gyro user
interface.
D7
D[7:0]
D6 D5
Table 99. OUTZ_L_G register
D4 D3 D2 D1 D0
Table 100. OUTZ_L_G register description
Yaw axis (Z) angular rate value (LSbyte)
D[15:0] expressed in two’s complement and its value depends on the interface used:
SPI1/I
2
C: Gyro UI chain yaw axis output
DocID028475 Rev 7 73/114
114
Register description LSM6DSL
Angular rate sensor Yaw axis (Z) angular rate output register (r). The value is expressed as a 16-bit word in two’s complement.
Data are according to the full-scale and ODR settings ( CTRL2_G (11h) ) of the gyro user
interface.
D15
D[15:8]
D14
Table 101. OUTZ_H_G register
D13 D12 D11 D10 D9 D8
Table 102. OUTZ_H_G register description
Yaw axis (Z) angular rate value (MSbyte)
D[15:0] expressed in two’s complement and its value depends on the interface used:
SPI1/I
2
C: Gyro UI chain yaw axis output
Linear acceleration sensor X-axis output register (r). The value is expressed as a 16-bit word in two’s complement.
D7
D[7:0]
D6
Table 103. OUTX_L_XL register
D5 D4 D3 D2
Table 104. OUTX_L_XL register description
X-axis linear acceleration value (LSbyte)
D1 D0
Linear acceleration sensor X-axis output register (r). The value is expressed as a 16-bit word in two’s complement.
D15 D14
Table 105. OUTX_H_XL register
D13 D12 D11 D10 D9 D8
D[15:8]
Table 106. OUTX_H_XL register description
X-axis linear acceleration value (MSbyte)
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Linear acceleration sensor Y-axis output register (r). The value is expressed as a 16-bit word in two’s complement.
D7
D[7:0]
D6
Table 107. OUTY_L_XL register
D5 D4 D3 D2
Table 108. OUTY_L_XL register description
Y-axis linear acceleration value (LSbyte)
D1 D0
DocID028475 Rev 7
LSM6DSL Register description
Linear acceleration sensor Y-axis output register (r). The value is expressed as a 16-bit word in two’s complement.
D15
D[15:8]
D14
Table 109. OUTY_H_G register
D13 D12 D11 D10
Table 110. OUTY_H_G register description
Y-axis linear acceleration value (MSbyte)
D9 D8
Linear acceleration sensor Z-axis output register (r). The value is expressed as a 16-bit word in two’s complement.
D7
D[7:0]
D6 D5
Table 111. OUTZ_L_XL register
D4 D3 D2
Table 112. OUTZ_L_XL register description
Z-axis linear acceleration value (LSbyte)
D1 D0
Linear acceleration sensor Z-axis output register (r). The value is expressed as a 16-bit word in two’s complement.
D15
D[15:8]
D14
Table 113. OUTZ_H_XL register
D13 D12 D11 D10
Table 114. OUTZ_H_XL register description
Z-axis linear acceleration value (MSbyte)
D9 D8
First byte associated to external sensors. The content of the register is consistent with the
SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 115. SENSORHUB1_REG register
SHub1_7 SHub1_6 SHub1_5 SHub1_4 SHub1_3 SHub1_2 SHub1_1 SHub1_0
Table 116. SENSORHUB1_REG register description
SHub1_[7:0] First byte associated to external sensors
DocID028475 Rev 7 75/114
114
Register description LSM6DSL
Second byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operations configurations (for external sensors from x = 0 to x = 3).
Table 117. SENSORHUB2_REG register
SHub2_7 SHub2_6 SHub2_5 SHub2_4 SHub2_3 SHub2_2 SHub2_1 SHub2_0
Table 118. SENSORHUB2_REG register description
SHub2_[7:0] Second byte associated to external sensors
Third byte associated to external sensors. The content of the register is consistent with the
SLAVEx_CONFIG number of read operations configurations (for external sensors from x = 0 to x = 3).
Table 119. SENSORHUB3_REG register
SHub3_7 SHub3_6 SHub3_5 SHub3_4 SHub3_3 SHub3_2 SHub3_1 SHub3_0
Table 120. SENSORHUB3_REG register description
SHub3_[7:0] Third byte associated to external sensors
Fourth byte associated to external sensors. The content of the register is consistent with the
SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 121. SENSORHUB4_REG register
SHub4_7 SHub4_6 SHub4_5 SHub4_4 SHub4_3 SHub4_2 SHub4_1 SHub4_0
Table 122. SENSORHUB4_REG register description
SHub4_[7:0] Fourth byte associated to external sensors
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Fifth byte associated to external sensors. The content of the register is consistent with the
SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 123. SENSORHUB5_REG register
SHub5_7 SHub5_6 SHub5_5 SHub5_4 SHub5_3 SHub5_2 SHub5_1 SHub5_0
Table 124. SENSORHUB5_REG register description
SHub5_[7:0] Fifth byte associated to external sensors
DocID028475 Rev 7
LSM6DSL Register description
Sixth byte associated to external sensors. The content of the register is consistent with the
SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 125. SENSORHUB6_REG register
SHub6_7 SHub6_6 SHub6_5 SHub6_4 SHub6_3 SHub6_2 SHub6_1 SHub6_0
Table 126. SENSORHUB6_REG register description
SHub6_[7:0] Sixth byte associated to external sensors
Seventh byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 127. SENSORHUB7_REG register
SHub7_7 SHub7_6 SHub7_5 SHub7_4 SHub7_3 SHub7_2 SHub7_1 SHub7_0
Table 128. SENSORHUB7_REG register description
SHub7_[7:0] Seventh byte associated to external sensors
9.48 SENSORHUB8_REG(35h)
Eighth byte associated to external sensors. The content of the register is consistent with the
SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 129. SENSORHUB8_REG register
SHub8_7 SHub8_6 SHub8_5 SHub8_4 SHub8_3 SHub8_2 SHub8_1 SHub8_0
Table 130. SENSORHUB8_REG register description
SHub8_[7:0] Eighth byte associated to external sensors
Ninth byte associated to external sensors. The content of the register is consistent with the
SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 131. SENSORHUB9_REG register
SHub9_7 SHub9_6 SHub9_5 SHub9_4 SHub9_3 SHub9_2 SHub9_1 SHub9_0
Table 132. SENSORHUB9_REG register description
SHub9_[7:0] Ninth byte associated to external sensors
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114
Register description LSM6DSL
Tenth byte associated to external sensors. The content of the register is consistent with the
SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 133. SENSORHUB10_REG register
SHub10_7 SHub10_6 SHub10_5 SHub10_4 SHub10_3 SHub10_2 SHub10_1 SHub10_0
Table 134. SENSORHUB10_REG register description
SHub10_[7:0] Tenth byte associated to external sensors
Eleventh byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 135. SENSORHUB11_REG register
SHub11_7 SHub11_6 SHub11_5 SHub11_4 SHub11_3 SHub11_2 SHub11_1 SHub11_0
Table 136. SENSORHUB11_REG register description
SHub11_[7:0] Eleventh byte associated to external sensors
Twelfth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 137. SENSORHUB12_REG register
SHub12_7 SHub12_6 SHub12_5 SHub12_4 SHub12_3 SHub12_2 SHub12_1 SHub12_0
Table 138. SENSORHUB12_REG register description
SHub12[7:0] Twelfth byte associated to external sensors
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FIFO status control register (r). For a proper reading of the register, it is recommended to set
the BDU bit in CTRL3_C (12h) to 1.
DIFF_
FIFO_7
DIFF_
FIFO_6
Table 139. FIFO_STATUS1 register
DIFF_
FIFO_5
DIFF_
FIFO_4
DIFF_
FIFO_3
DIFF_
FIFO_2
DIFF_
FIFO_1
DIFF_
FIFO_0
DIFF_FIFO_[7:0]
Table 140. FIFO_STATUS1 register description
Number of unread words (16-bit axes) stored in FIFO
(1)
.
1. For a complete number of unread samples, consider DIFF_FIFO [10:8] in FIFO_STATUS2 (3Bh) .
DocID028475 Rev 7
LSM6DSL Register description
FIFO status control register (r). For a proper reading of the register, it is recommended to set
the BDU bit in CTRL3_C (12h) to 1.
WaterM OVER_RUN
Table 141. FIFO_STATUS2 register
FIFO_
FULL_
SMART
FIFO_
EMPTY
0
DIFF_
FIFO_10
DIFF_
FIFO_9
DIFF_
FIFO_8
WaterM
Table 142. FIFO_STATUS2 register description
FIFO watermark status. The watermark is set through bits FTH_[7:0] in
. Default value: 0
(0: FIFO filling is lower than watermark level
(1)
;
1: FIFO filling is equal to or higher than the watermark level)
OVER_RUN
FIFO_FULL_
SMART
FIFO overrun status. Default value: 0
(0: FIFO is not completely filled; 1: FIFO is completely filled)
Smart FIFO full status. Default value: 0
(0: FIFO is not full; 1: FIFO will be full at the next ODR)
FIFO_EMPTY FIFO empty bit. Default value: 0
(0: FIFO contains data; 1: FIFO is empty)
DIFF_FIFO_[10:8] Number of unread words (16-bit axes) stored in FIFO
(2)
.
1. FIFO watermark level is set in FTH_[10:0] in FIFO_CTRL1 (06h) and
2. For a complete number of unread samples, consider DIFF_FIFO [7:0] in
FIFO status control register (r). For a proper reading of the register, it is recommended to set
to 1.
FIFO_
PATTERN
_7
FIFO_
PATTERN
_6
Table 143. FIFO_STATUS3 register
FIFO_
PATTERN
_5
FIFO_
PATTERN
_4
FIFO_
PATTERN
_3
FIFO_
PATTERN
_2
FIFO_
PATTERN
_1
FIFO_
PATTERN
_0
FIFO_
PATTERN_[7:0]
Table 144. FIFO_STATUS3 register description
Word of recursive pattern read at the next reading.
DocID028475 Rev 7 79/114
114
Register description LSM6DSL
FIFO status control register (r). For a proper reading of the register, it is recommended to set
to 1.
0 0 0
Table 145. FIFO_STATUS4 register
0 0 0
FIFO_
PATTERN_9
FIFO_
PATTERN_8
FIFO_
PATTERN_[9:8]
Table 146. FIFO_STATUS4 register description
Word of recursive pattern read at the next reading.
FIFO data output register (r). For a proper reading of the register, it is recommended to set
to 1.
DATA_
OUT_
FIFO_L_7
DATA_
OUT_
FIFO_L_6
Table 147. FIFO_DATA_OUT_L register
DATA_
OUT_
FIFO_L_5
DATA_
OUT_
FIFO_L_4
DATA_
OUT_
FIFO_L_3
DATA_
OUT_
FIFO_L_2
DATA_
OUT_
FIFO_L_1
DATA_
OUT_
FIFO_L_0
Table 148. FIFO_DATA_OUT_L register description
DATA_OUT_FIFO_L_[7:0] FIFO data output (first byte)
FIFO data output register (r). For a proper reading of the register, it is recommended to set
to 1.
DATA_
OUT_
FIFO_H_7
DATA_
OUT_
FIFO_H_6
Table 149. FIFO_DATA_OUT_H register
DATA_
OUT_
FIFO_H_5
DATA_
OUT_
FIFO_H_4
DATA_
OUT_
FIFO_H_3
DATA_
OUT_
FIFO_H_2
DATA_
OUT_
FIFO_H_1
DATA_
OUT_
FIFO_H_0
Table 150. FIFO_DATA_OUT_H register description
DATA_OUT_FIFO_H_[7:0] FIFO data output (second byte)
80/114 DocID028475 Rev 7
LSM6DSL Register description
Timestamp first (least significant) byte data output register (r). The value is expressed as a
24-bit word and the bit resolution is defined by setting the value in
TIMESTA
MP0_7
TIMESTA
MP0_6
Table 151. TIMESTAMP0_REG register
TIMESTA
MP0_5
TIMESTA
MP0_4
TIMESTA
MP0_3
TIMESTA
MP0_2
TIMESTA
MP0_1
TIMESTA
MP0_0
TIMESTAMP0_[7:0]
Table 152. TIMESTAMP0_REG register description
TIMESTAMP first byte data output
Timestamp second byte data output register (r). The value is expressed as a 24-bit word
and the bit resolution is defined by setting value in WAKE_UP_DUR (5Ch) .
TIMESTA
MP1_7
TIMESTA
MP1_6
Table 153. TIMESTAMP1_REG register
TIMESTA
MP1_5
TIMESTA
MP1_4
TIMESTA
MP1_3
TIMESTA
MP1_2
TIMESTA
MP1_1
TIMESTA
MP1_0
Table 154. TIMESTAMP1_REG register description
TIMESTAMP1_[7:0] TIMESTAMP second byte data output
Timestamp third (most significant) byte data output register (r/w). The value is expressed as a 24-bit word and the bit resolution is defined by setting the value in
To reset the timer, the AAh value has to be stored in this register.
TIMESTA
MP2_7
TIMESTA
MP2_6
Table 155. TIMESTAMP2_REG register
TIMESTA
MP2_5
TIMESTA
MP2_4
TIMESTA
MP2_3
TIMESTA
MP2_2
TIMESTA
MP2_1
TIMESTA
MP2_0
Table 156. TIMESTAMP2_REG register description
TIMESTAMP2_[7:0] TIMESTAMP third byte data output
DocID028475 Rev 7 81/114
114
Register description LSM6DSL
Step counter timestamp information register (r). When a step is detected, the value of
TIMESTAMP_REG1 register is copied in STEP_TIMESTAMP_L.
STEP_
TIMESTA
MP_L_7
STEP_
TIMESTA
MP_L_6
Table 157. STEP_TIMESTAMP_L register
STEP_
TIMESTA
MP_L_5
STEP_
TIMESTA
MP_L_4
STEP_
TIMESTA
MP_L_3
STEP_
TIMESTA
MP_L_2
STEP_
TIMESTA
MP_L_1
STEP_
TIMESTA
MP_L_0
Table 158. STEP_TIMESTAMP_L register description
STEP_TIMESTAMP_L[7:0] Timestamp of last step detected.
Step counter timestamp information register (r). When a step is detected, the value of
TIMESTAMP_REG2 register is copied in STEP_TIMESTAMP_H.
STEP_
TIMESTA
MP_H_7
STEP_
TIMESTA
MP_H_6
Table 159. STEP_TIMESTAMP_H register
STEP_
TIMESTA
MP_H_5
STEP_
TIMESTA
MP_H_4
STEP_
TIMESTA
MP_H_3
STEP_
TIMESTA
MP_H_2
STEP_
TIMESTA
MP_H_1
Table 160. STEP_TIMESTAMP_H register description
STEP_TIMESTAMP_H[7:0] Timestamp of last step detected.
STEP_
TIMESTA
MP_H_0
Step counter output register (r).
STEP_CO
UNTER_L
_7
STEP_CO
UNTER_L
_6
Table 161. STEP_COUNTER_L register
STEP_CO
UNTER_L
_5
STEP_CO
UNTER_L
_4
STEP_CO
UNTER_L
_3
STEP_CO
UNTER_L
_2
STEP_CO
UNTER_L
_1
STEP_CO
UNTER_L
_0
Table 162. STEP_COUNTER_L register description
STEP_COUNTER_L_[7:0] Step counter output (LSbyte)
82/114 DocID028475 Rev 7
LSM6DSL Register description
Step counter output register (r).
STEP_CO
UNTER_H
_7
STEP_CO
UNTER_H
_6
Table 163. STEP_COUNTER_H register
STEP_CO
UNTER_H
_5
STEP_CO
UNTER_H
_4
STEP_CO
UNTER_H
_3
STEP_CO
UNTER_H
_2
STEP_CO
UNTER_H
_1
STEP_CO
UNTER_H
_0
Table 164. STEP_COUNTER_H register description
STEP_COUNTER_H_[7:0] Step counter output (MSbyte)
Thirteenth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x
= 0 to x = 3).
Table 165. SENSORHUB13_REG register
SHub13_7 SHub13_6 SHub13_5 SHub13_4 SHub13_3 SHub13_2 SHub13_1 SHub13_0
Table 166. SENSORHUB13_REG register description
SHub13_[7:0] Thirteenth byte associated to external sensors
Fourteenth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 167. SENSORHUB14_REG register
SHub14_7 SHub14_6 SHub14_5 SHub14_4 SHub14_3 SHub14_2 SHub14_1 SHub14_0
Table 168. SENSORHUB14_REG register description
SHub14_[7:0] Fourteenth byte associated to external sensors
Fifteenth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 169. SENSORHUB15_REG register
SHub15_7 SHub15_6 SHub15_5 SHub15_4 SHub15_3 SHub15_2 SHub15_1 SHub15_0
Table 170. SENSORHUB15_REG register description
SHub15_[7:0] Fifteenth byte associated to external sensors
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114
Register description LSM6DSL
Sixteenth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 171. SENSORHUB16_REG register
SHub16_7 SHub16_6 SHub16_5 SHub16_4 SHub16_3 SHub16_2 SHub16_1 SHub16_0
Table 172. SENSORHUB16_REG register description
SHub16_[7:0] Sixteenth byte associated to external sensors
Seventeenth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 173. SENSORHUB17_REG register
SHub17_7 SHub17_6 SHub17_5 SHub17_4 SHub17_3 SHub17_2 SHub17_1 SHub17_0
Table 174. SENSORHUB17_REG register description
SHub17_[7:0] Seventeenth byte associated to external sensors
Eighteenth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 175. SENSORHUB18_REG register
SHub18_7 SHub18_6 SHub18_5 SHub18_4 SHub18_3 SHub18_2 SHub18_1 SHub18_0
Table 176. SENSORHUB18_REG register description
SHub18_[7:0] Eighteenth byte associated to external sensors
84/114 DocID028475 Rev 7
LSM6DSL Register description
Significant motion, tilt, step detector, hard/soft-iron and sensor hub interrupt source register
(r).
Table 177. FUNC_SRC1 register
STEP_
COUNT
_DELTA
_IA
SIGN_
MOTION_IA
TILT_IA
STEP_
DETECTED
STEP_
OVERFLOW
HI_
FAIL
SI_END_
OP
SENSOR
HUB_
END_OP
STEP_COUNT
_DELTA_IA
Table 178. FUNC_SRC1 register description
Pedometer step recognition on delta time status. Default value: 0
(0: no step recognized during delta time;
1: at least one step recognized during delta time)
SIGN_
MOTION_IA
TILT_IA
STEP_
DETECTED
STEP_
OVERFLOW
HI_FAIL
SI_END_OP
SENSORHUB
_END_OP
Significant motion event detection status. Default value: 0
(0: significant motion event not detected; 1: significant motion event detected)
Tilt event detection status. Default value: 0
(0: tilt event not detected; 1: tilt event detected)
Step detector event detection status. Default value: 0
(0: step detector event not detected; 1: step detector event detected)
Step counter overflow status. Default value: 0
(0: step counter value < 2
16
; 1: step counter value reached 2
16
)
Fail in hard/soft-ironing algorithm.
Hard/soft-iron calculation status. Default value: 0
(0: Hard/soft-iron calculation not concluded; 1: Hard/soft-iron calculation concluded)
Sensor hub communication status. Default value: 0
(0: sensor hub communication not concluded;
1: sensor hub communication concluded)
Wrist tilt interrupt source register (r).
0
SLAVE3_
NACK
Table 179. FUNC_SRC2 register
SLAVE2_
NACK
SLAVE1_
NACK
SLAVE0_
NACK
0 0
WRIST_
TILT_IA
Table 180. FUNC_SRC2 register description
SLAVE3_NACK This bit is set to 1 if Not acknowledge occurs on slave 3 communication. Default value: 0
SLAVE2_NACK This bit is set to 1 if Not acknowledge occurs on slave 2 communication. Default value: 0
SLAVE1_NACK This bit is set to 1 if Not acknowledge occurs on slave 1 communication. Default value: 0
SLAVE0_NACK This bit is set to 1 if Not acknowledge occurs on slave 0 communication. Default value: 0
WRIST_TILT_IA
Wrist tilt event detection status. Default value: 0
(0: Wrist tilt event not detected; 1: Wrist tilt event detected)
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114
Register description LSM6DSL
Wrist tilt interrupt source register (r).
WRIST_
TILT_IA_
Xpos
WRIST_
TILT_IA_
Xneg
Table 181. WRIST_TILT_IA register
WRIST_
TILT_IA_
Ypos
WRIST_
TILT_IA_
Yneg
WRIST_
TILT_IA_
Zpos
WRIST_
TILT_IA_
Zneg
0
WRIST_
TILT_IA_ Xpos
WRIST_
TILT_IA_ Xneg
WRIST_
TILT_IA_ Ypos
WRIST_
TILT_IA_ Yneg
WRIST_
TILT_IA_ Zpos
WRIST_
TILT_IA_ Zneg
Table 182. WRIST_TILT_IA register description
Absolute Wrist Tilt event detection status on X-positive axis. Default value: 0
(0: Absolute Wrist Tilt event on X-positive axis not detected;
1: Absolute Wrist Tilt event on X-positive axis detected)
Absolute Wrist Tilt event detection status on X-negative axis. Default value: 0
(0: Absolute Wrist Tilt event on X-negative axis not detected;
1: Absolute Wrist Tilt event on X-negative axis detected)
Absolute Wrist Tilt event detection status on Y-positive axis. Default value: 0
(0: Absolute Wrist Tilt event on Y-positive axis not detected;
1: Absolute Wrist Tilt event on Y-positive axis detected)
Absolute Wrist Tilt event detection status on Y-negative axis. Default value: 0
(0: Absolute Wrist Tilt event on Y-negative axis not detected;
1: Absolute Wrist Tilt event on Y-negative axis detected)
Absolute Wrist Tilt event detection status on Z-positive axis. Default value: 0
(0: Absolute Wrist Tilt event on Z-positive axis not detected;
1: Absolute Wrist Tilt event on Z-positive axis detected)
Absolute Wrist Tilt event detection status on Z-negative axis. Default value: 0
(0: Absolute Wrist Tilt event on Z-negative axis not detected;
1: Absolute Wrist Tilt event on Z-negative axis detected)
0
86/114 DocID028475 Rev 7
LSM6DSL Register description
Enables interrupt and inactivity functions, configuration of filtering and tap recognition functions (r/w).
INTERRUPTS
_ENABLE
Table 183. TAP_CFG register
INACT_EN1 INACT_EN0
SLOPE
_FDS
TAP_X_EN TAP_Y_EN TAP_Z_EN LIR
INTERRUPTS
_ENABLE
Table 184. TAP_CFG register description
Enable basic interrupts (6D/4D, free-fall, wake-up, tap, inactivity). Default 0.
(0: interrupt disabled; 1: interrupt enabled)
INACT_EN[1:0]
Enable inactivity function. Default value: 00
(00: disabled
01: sets accelerometer ODR to 12.5 Hz (low-power mode), gyro does not change;
10: sets accelerometer ODR to 12.5 Hz (low-power mode), gyro to sleep mode;
11: sets accelerometer ODR to 12.5 Hz (low-power mode), gyro to power-down mode)
SLOPE_FDS
HPF or SLOPE filter selection on wake-up and Activity/Inactivity functions. Refer to
(0: SLOPE filter applied; 1: HPF applied)
TAP_X_EN
TAP_Y_EN
TAP_Z_EN
LIR
Enable X direction in tap recognition. Default value: 0
(0: X direction disabled; 1: X direction enabled)
Enable Y direction in tap recognition. Default value: 0
(0: Y direction disabled; 1: Y direction enabled)
Enable Z direction in tap recognition. Default value: 0
(0: Z direction disabled; 1: Z direction enabled)
Latched Interrupt. Default value: 0
(0: interrupt request not latched; 1: interrupt request latched)
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Register description LSM6DSL
Portrait/landscape position and tap function threshold register (r/w).
D4D_EN
SIXD_THS
1
Table 185. TAP_THS_6D register
SIXD_THS
0
TAP_THS
4
TAP_THS
3
TAP_THS
2
TAP_THS
1
TAP_THS
0
00
01
10
11
D4D_EN
SIXD_THS[1:0]
TAP_THS[4:0]
Table 186. TAP_THS_6D register description
4D orientation detection enable. Z-axis position detection is disabled.
Default value: 0
(0: enabled; 1: disabled)
Threshold for 4D/6D function. Default value: 00
For details, refer to Table 187 .
Threshold for tap recognition. Default value: 00000
1 LSb corresponds to FS_XL/2
5
SIXD_THS[1:0]
Table 187. Threshold for D4D/D6D function
Threshold value
80 degrees
70 degrees
60 degrees
50 degrees
88/114
Tap recognition function setting register (r/w).
DUR3
DUR[3:0]
QUIET[1:0]
SHOCK[1:0]
DUR2
Table 188. INT_DUR2 register
DUR1 DUR0 QUIET1 QUIET0 SHOCK1 SHOCK0
Table 189. INT_DUR2 register description
Duration of maximum time gap for double tap recognition. Default: 0000
When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16*ODR_XL time. If the
DUR[3:0] bits are set to a different value, 1LSB corresponds to 32*ODR_XL time.
Expected quiet time after a tap detection. Default value: 00
Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to
2*ODR_XL time. If the QUIET[1:0] bits are set to a different value, 1LSB corresponds to 4*ODR_XL time.
Maximum duration of overthreshold event. Default value: 00
Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4*ODR_XL time. If the SHOCK[1:0] bits are set to a different value, 1LSB corresponds to 8*ODR_XL time.
DocID028475 Rev 7
LSM6DSL Register description
Single and double-tap function threshold register (r/w).
Table 190. WAKE_UP_THS register
SINGLE_
DOUBLE
_TAP
0 WK_THS5 WK_THS4 WK_THS3 WK_THS2 WK_THS1 WK_THS0
Table 191. WAKE_UP_THS register description
SINGLE_DOUBLE_TAP
Single/double-tap event enable. Default: 0
(0: only single-tap event enabled;
1: both single and double-tap events enabled)
WK_THS[5:0]
Threshold for wakeup. Default value: 000000
1 LSb corresponds to FS_XL/2
6
Free-fall, wakeup, timestamp and sleep mode functions duration setting register (r/w).
FF_DUR5
WAKE_
DUR1
Table 192. WAKE_UP_DUR register
WAKE_
DUR0
TIMER_
HR
SLEEP_
DUR3
SLEEP_
DUR2
SLEEP_
DUR1
SLEEP_
DUR0
FF_DUR5
WAKE_DUR[1:0]
TIMER_HR
SLEEP_DUR[3:0]
Table 193. WAKE_UP_DUR register description
Free fall duration event. Default: 0
For the complete configuration of the free-fall duration, refer to FF_DUR[4:0] in
FREE_FALL (5Dh) configuration.
1 LSB = 1 ODR_time
Wake up duration event. Default: 00
1LSB = 1 ODR_time
Timestamp register resolution setting
(1)
. Default value: 0
(0: 1LSB = 6.4 ms; 1: 1LSB = 25 μ s)
Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR)
1 LSB = 512 ODR
1. Configuration of this bit affects
,
,
,
registers.
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114
Register description LSM6DSL
Free-fall function duration setting register (r/w).
Table 194. FREE_FALL register
FF_DUR4 FF_DUR3 FF_DUR2 FF_DUR1 FF_DUR0 FF_THS2 FF_THS1 FF_THS0
FF_DUR[4:0]
FF_THS[2:0]
Table 195. FREE_FALL register description
Free-fall duration event. Default: 0
For the complete configuration of the free fall duration, refer to FF_DUR5 in
WAKE_UP_DUR (5Ch) configuration
Free fall threshold setting. Default: 000
For details refer to
.
000
001
010
011
100
101
110
111
FF_THS[2:0]
Table 196. Threshold for free-fall function
Threshold value
156 m g
219 m g
250 m g
312 m g
344 m g
406 m g
469 m g
500 m g
90/114 DocID028475 Rev 7
LSM6DSL Register description
Functions routing on INT1 register (r/w).
INT1_
INACT_
STATE
INT1_
SINGLE_
TAP
Table 197. MD1_CFG register
INT1_WU INT1_FF
INT1_
DOUBLE_
TAP
INT1_6D INT1_TILT
INT1_
TIMER
INT1_INACT_
STATE
Table 198. MD1_CFG register description
Routing on INT1 of inactivity mode. Default: 0
(0: routing on INT1 of inactivity disabled; 1: routing on INT1 of inactivity enabled)
INT1_SINGLE_
TAP
Single-tap recognition routing on INT1. Default: 0
(0: routing of single-tap event on INT1 disabled;
1: routing of single-tap event on INT1 enabled)
INT1_WU
Routing of wakeup event on INT1. Default value: 0
(0: routing of wakeup event on INT1 disabled;
1: routing of wakeup event on INT1 enabled)
INT1_FF
INT1_DOUBLE
_TAP
Routing of free-fall event on INT1. Default value: 0
(0: routing of free-fall event on INT1 disabled;
1: routing of free-fall event on INT1 enabled)
Routing of tap event on INT1. Default value: 0
(0: routing of double-tap event on INT1 disabled;
1: routing of double-tap event on INT1 enabled)
INT1_6D
INT1_TILT
INT1_TIMER
Routing of 6D event on INT1. Default value: 0
(0: routing of 6D event on INT1 disabled; 1: routing of 6D event on INT1 enabled)
Routing of tilt event on INT1. Default value: 0
(0: routing of tilt event on INT1 disabled; 1: routing of tilt event on INT1 enabled)
Routing of end counter event of timer on INT1. Default value: 0
(0: routing of end counter event of timer on INT1 disabled;
1: routing of end counter event of timer event on INT1 enabled)
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Register description LSM6DSL
Functions routing on INT2 register (r/w).
INT2_
INACT_
STATE
INT2_
SINGLE_
TAP
Table 199. MD2_CFG register
INT2_WU INT2_FF
INT2_
DOUBLE_
TAP
INT2_6D INT2_TILT
INT2_
IRON
INT2_INACT_
STATE
INT2_SINGLE_
TAP
INT2_WU
INT2_FF
INT2_DOUBLE
_TAP
INT2_6D
INT2_TILT
INT2_IRON
Table 200. MD2_CFG register description
Routing on INT2 of inactivity mode. Default: 0
(0: routing on INT2 of inactivity disabled; 1: routing on INT2 of inactivity enabled)
Single-tap recognition routing on INT2. Default: 0
(0: routing of single-tap event on INT2 disabled;
1: routing of single-tap event on INT2 enabled)
Routing of wakeup event on INT2. Default value: 0
(0: routing of wakeup event on INT2 disabled;
1: routing of wake-up event on INT2 enabled)
Routing of free-fall event on INT2. Default value: 0
(0: routing of free-fall event on INT2 disabled;
1: routing of free-fall event on INT2 enabled)
Routing of tap event on INT2. Default value: 0
(0: routing of double-tap event on INT2 disabled;
1: routing of double-tap event on INT2 enabled)
Routing of 6D event on INT2. Default value: 0
(0: routing of 6D event on INT2 disabled; 1: routing of 6D event on INT2 enabled)
Routing of tilt event on INT2. Default value: 0
(0: routing of tilt event on INT2 disabled; 1: routing of tilt event on INT2 enabled)
Routing of soft-iron/hard-iron algorithm end event on INT2. Default value: 0
(0: routing of soft-iron/hard-iron algorithm end event on INT2 disabled;
1: routing of soft-iron/hard-iron algorithm end event on INT2 enabled)
92/114 DocID028475 Rev 7
LSM6DSL Register description
MASTER_
CMD_
CODE7
MASTER_
CMD_
CODE6
Table 201. MASTER_CMD_CODE register
MASTER_
CMD_
CODE5
MASTER_
CMD_
CODE4
MASTER_
CMD_
CODE3
MASTER_
CMD_
CODE2
MASTER_
CMD_
CODE1
MASTER_
CMD_
CODE0
MASTER_CMD_
CODE[7:0]
Table 202. MASTER_CMD_CODE register description
Master command code used for stamping for sensor sync. Default: 0
ERROR_
CODE7
Table 203. SENS_SYNC_SPI_ERROR_CODE register
ERROR_
CODE6
ERROR_
CODE5
ERROR_
CODE4
ERROR_
CODE3
ERROR_
CODE2
ERROR_
CODE1
Table 204. SENS_SYNC_SPI_ERROR_CODE register description
ERROR_CODE[7:0] Error code used for sensor synchronization. Default: 0)
ERROR_
CODE0
External magnetometer raw data (r).
D7
D[7:0]
D6
Table 205. OUT_MAG_RAW_X_L register
D5 D4 D3 D2 D1
Table 206. OUT_MAG_RAW_X_L register description
X-axis external magnetometer value (LSbyte)
D0
External magnetometer raw data (r).
D15
D[15:8]
D14
Table 207. OUT_MAG_RAW_X_H register
D13 D12 D11 D10 D9
Table 208. OUT_MAG_RAW_X_H register description
X-axis external magnetometer value (MSbyte)
D8
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114
Register description LSM6DSL
External magnetometer raw data (r).
D7 D6
Table 209. OUT_MAG_RAW_Y_L register
D5 D4 D3 D2
D[7:0]
D1
Table 210. OUT_MAG_RAW_Y_L register description
Y-axis external magnetometer value (LSbyte)
D0
External magnetometer raw data (r).
D15 D14
Table 211. OUT_MAG_RAW_Y_H register
D13 D12 D11 D10
D[15:8]
D9
Table 212. OUT_MAG_RAW_Y_H register description
Y-axis external magnetometer value (MSbyte)
D8
External magnetometer raw data (r).
D7
D[7:0]
D6
Table 213. OUT_MAG_RAW_Z_L register
D5 D4 D3 D2 D1
Table 214. OUT_MAG_RAW_Z_L register description
Z-axis external magnetometer value (LSbyte)
D0
External magnetometer raw data (r).
D15
D[15:8]
D14
Table 215. OUT_MAG_RAW_Z_H register
D13 D12 D11 D10 D9
Table 216. OUT_MAG_RAW_Z_H register description
Z-axis external magnetometer value (MSbyte)
D8
94/114 DocID028475 Rev 7
LSM6DSL Register description
Accelerometer X-axis user offset correction (r/w). The offset value set in the X_OFS_USR offset register is internally added to the acceleration value measured on the X-axis.
X_OFS_
USR_7
X_OFS_
USR_6
Table 217. X_OFS_USR register
X_OFS_
USR_5
X_OFS_
USR_4
X_OFS_
USR_3
X_OFS_
USR_2
X_OFS_
USR_1
X_OFS_
USR_0
X_OFS_USR_
[7:0]
Table 218. X_OFS_USR register description
Accelerometer X-axis user offset correction expressed in two’s complement, weight depends on CTRL6_C(4) bit. The value must be in the range [-127 127].
Accelerometer Y-axis user offset correction (r/w). The offset value set in the Y_OFS_USR offset register is internally added to the acceleration value measured on the Y-axis.
Y_OFS_
USR_7
Y_OFS_
USR_6
Table 219. Y_OFS_USR register
Y_OFS_
USR_5
Y_OFS_
USR_4
Y_OFS_
USR_3
Y_OFS_
USR_2
Y_OFS_
USR_1
Y_OFS_
USR_0
Y_OFS_USR_
[7:0]
Table 220. Y_OFS_USR register description
Accelerometer Y-axis user offset correction expressed in two’s complement, weight depends on CTRL6_C(4) bit. The value must be in the range [-127 127].
Accelerometer Z-axis user offset correction (r/w). The offset value set in the Z_OFS_USR offset register is internally subtracted from the acceleration value measured on the Z-axis.
Z_OFS_
USR_7
Z_OFS_
USR_6
Table 221. Z_OFS_USR register
Z_OFS_
USR_5
Z_OFS_
USR_4
Z_OFS_
USR_3
Z_OFS_
USR_2
Z_OFS_
USR_1
Z_OFS_
USR_0
Z_OFS_USR_
[7:0]
Table 222. Z_OFS_USR register description
Accelerometer Z-axis user offset correction expressed in two’s complement, weight depends on CTRL6_C(4) bit. The value must be in the range [-127 127].
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Embedded functions register mapping
10 Embedded functions register mapping
Note:
LSM6DSL
The tables given below provide a list of the first (A) and second (B) bank registers related to the embedded functions available in the device and the corresponding addresses.
The embedded functions registers of bank A are accessible when FUNC_CFG_EN is set
to ‘1’ in FUNC_CFG_ACCESS (01h) .
The embedded functions registers of bank B are accessible when both FUNC_CFG_EN and FUNC_CFG_EN_B set to ‘1’ in
.
All modifications of the content of the embedded functions registers have to be performed with the device in power-down mode.
SLV0_ADD
SLV0_SUBADD
SLAVE0_CONFIG
SLV1_ADD
SLV1_SUBADD
SLAVE1_CONFIG
SLV2_ADD
SLV2_SUBADD
SLAVE2_CONFIG
SLV3_ADD
SLV3_SUBADD
SLAVE3_CONFIG
DATAWRITE_SRC_
MODE_SUB_SLV0
CONFIG_PEDO_THS_MIN
RESERVED
SM_THS
PEDO_DEB_REG
STEP_COUNT_DELTA
MAG_SI_XX
MAG_SI_XY
MAG_SI_XZ
MAG_SI_YX
MAG_SI_YY
Table 223. Register address map - Bank A - embedded functions
Register address
Name Type Default Comment
Hex Binary r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w
06
07
08
09
02
03
04
05
0A
0B
0C
0D
00000010
00000011
00000100
00000101
00000110
00000111
00001000
00001001
00001010
00001011
00001100
00001101
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000 r/w r/w r/w r/w r/w r/w
r/w r/w r/w r/w
0E
15
24
25
26
0F
10-12
13
14
27
28
00001110
00001111
00010011
00010100
0001 0101
00100100
00100101
00100110
00100111
00101000
00000000
00010000
00000110
01101110
00000000
00001000
00000000
00000000
00000000
00001000
Reserved
96/114 DocID028475 Rev 7
LSM6DSL Embedded functions register mapping
Table 223. Register address map - Bank A - embedded functions (continued)
Register address
Name Type Default Comment
Hex Binary
MAG_SI_YZ
MAG_SI_ZX
MAG_SI_ZY
MAG_SI_ZZ
MAG_OFFX_L
MAG_OFFX_H
MAG_OFFY_L
MAG_OFFY_H
MAG_OFFZ_L
MAG_OFFZ_H r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w
2C
2D
2E
2F
29
2A
2B
30
31
32
00101001
00101010
00101011
00101100
00101101
00101110
00101111
00110000
00110001
00110010
00000000
00000000
00000000
00001000
00000000
00000000
00000000
00000000
00000000
00000000
Table 224. Register address map - Bank B - embedded functions
Register address
Name Type Default Comment
Hex Binary
01010000 00001111 A_WRIST_TILT_LAT
RESERVED
A_WRIST_TILT_THS
RESERVED
A_WRIST_TILT_Mask r/w
r/w
r/w
50
51-53
54
55-58
59
01010100
01011001
00100000
11000000
Reserved
Reserved
Registers marked as Reserved must not be changed. Writing to those registers may cause permanent damage to the device.
The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered up.
DocID028475 Rev 7 97/114
114
Embedded functions registers description - Bank A
11
LSM6DSL
Embedded functions registers description - Bank A
Note: All modifications of the content of the embedded functions registers have to be performed with the device in power-down mode.
I
2
C slave address of the first external sensor (Sensor1) register (r/w).
Slave0_ add6
Slave0_ add5
Table 225. SLV0_ADD register
Slave0_ add4
Slave0_ add3
Slave0_ add2
Slave0_ add1
Slave0_ add0
Slave0_add[6:0] rw_0
Table 226. SLV0_ADD register description
I
2
C slave address of Sensor1 that can be read by sensor hub.
Default value: 0000000
Read/write operation on Sensor1. Default value: 0
(0: write operation; 1: read operation) rw_0
Address of register on the first external sensor (Sensor1) register (r/w).
Slave0_ reg7
Slave0_ reg6
Table 227. SLV0_SUBADD register
Slave0_ reg5
Slave0_ reg4
Slave0_ reg3
Slave0_ reg2
Slave0_ reg1
Slave0_ reg0
Slave0_reg[7:0]
Table 228. SLV0_SUBADD register description
Address of register on Sensor1 that has to be read/write according to the rw_0 bit
value in SLV0_ADD (02h) . Default value: 00000000
First external sensor (Sensor1) configuration and sensor hub settings register (r/w).
Slave0_ rate1
Slave0_ rate0
Table 229. SLAVE0_CONFIG register
Aux_sens
_on1
Aux_sens
_on0
Src_mode
Slave0_ numop2
Slave0_ numop1
Slave0_ numop0
98/114 DocID028475 Rev 7
LSM6DSL Embedded functions registers description - Bank A
Slave0_rate[1:0]
Aux_sens_on[1:0]
Src_mode
Table 230. SLAVE0_CONFIG register description
Decimation of read operation on Sensor1 starting from the sensor hub trigger.
Default value: 00
(00: no decimation
01: update every 2 samples
10: update every 4 samples
11: update every 8 samples)
Number of external sensors to be read by sensor hub. Default value: 00
(00: one sensor
01: two sensors
10: three sensors
11: four sensors)
Source mode conditioned read
(1)
. Default value: 0
(0: source mode read disabled; 1: source mode read enabled)
Slave0_numop[2:0] Number of read operations on Sensor1.
1. Read conditioned by the content of the register at address specified in the
DATAWRITE_SRC_MODE_SUB_SLV0 (0Eh) register. If the content is non-zero, the operation continues
with the reading of the address specified in the
register, else the operation is interrupted.
I
2
C slave address of the second external sensor (Sensor2) register (r/w).
Slave1_ add6
Slave1_ add5
Table 231. SLV1_ADD register
Slave1_ add4
Slave1_ add3
Slave1_ add2
Slave1_ add1
Slave1_ add0
Slave1_add[6:0]
Table 232. SLV1_ADD register description
I
2
C slave address of Sensor2 that can be read by sensor hub.
Default value: 0000000 r_1
Read operation on Sensor2 enable. Default value: 0
(0: read operation disabled; 1: read operation enabled) r_1
Address of register on the second external sensor (Sensor2) register (r/w).
Slave1_ reg7
Slave1_ reg6
Table 233. SLV1_SUBADD register
Slave1_ reg5
Slave1_ reg4
Slave1_ reg3
Slave1_ reg2
Slave1_ reg1
Slave1_ reg0
Slave1_reg[7:0]
Table 234. SLV1_SUBADD register description
Address of register on Sensor2 that has to be read according to the r_1 bit value
in SLV1_ADD (05h) . Default value: 00000000
DocID028475 Rev 7 99/114
114
Embedded functions registers description - Bank A LSM6DSL
Second external sensor (Sensor2) configuration register (r/w).
Slave1_ rate1
Slave1_ rate0
Table 235. SLAVE1_CONFIG register write_once 0
(1)
0
(1)
1. This bit must be set to ‘0’ for the correct operation of the device.
Slave1_ numop2
Slave1_ numop1
Slave1_ numop0
Slave1_rate[1:0] write_once
Table 236. SLAVE1_CONFIG register description
Decimation of read operation on Sensor2 starting from the sensor hub trigger.
Default value: 00
(00: no decimation
01: update every 2 samples
10: update every 4 samples
11: update every 8 samples)
Slave 0 write operation is performed only at the first sensor hub cycle.
(1)
Default value: 0
0: write operation for each sensor hub cycle
1: write operation only for the first sensor hub cycle
Slave1_numop[2:0] Number of read operations on Sensor2.
1. This is effective if the Aux_sens_on[1:0] field in
SLAVE0_CONFIG (04h) is set to a value other than 00.
I 2 C slave address of the third external sensor (Sensor3) register (r/w).
Slave2_ add6
Slave2_ add5
Table 237. SLV2_ADD register
Slave2_ add4
Slave2_ add3
Slave2_ add2
Slave2_ add1
Slave2_ add0
Slave2_add[6:0] r_2
Table 238. SLV2_ADD register description
I
2
C slave address of Sensor3 that can be read by sensor hub.
Default value: 0000000
Read operation on Sensor3 enable. Default value: 0
(0: read operation disabled; 1: read operation enabled) r_2
100/114
Address of register on the third external sensor (Sensor3) register (r/w).
Slave2_ reg7
Slave2_ reg6
Table 239. SLV2_SUBADD register
Slave2_ reg5
Slave2_ reg4
Slave2_ reg3
Slave2_ reg2
Slave2_ reg1
Slave2_ reg0
Slave2_reg[7:0]
Table 240. SLV2_SUBADD register description
Address of register on Sensor3 that has to be read according to the r_2 bit value
in SLV2_ADD (08h) . Default value: 00000000
DocID028475 Rev 7
LSM6DSL Embedded functions registers description - Bank A
Third external sensor (Sensor3) configuration register (r/w).
Slave2_ rate1
Slave2_ rate0
Table 241. SLAVE2_CONFIG register
0
(1)
0
(1)
0
(1)
1. This bit must be set to ‘0’ for the correct operation of the device.
Slave2_ numop2
Slave2_ numop1
Slave2_ numop0
Table 242. SLAVE2_CONFIG register description
Slave2_rate[1:0]
Decimation of read operation on Sensor3 starting from the sensor hub trigger.
Default value: 00
(00: no decimation
01: update every 2 samples
10: update every 4 samples
11: update every 8 samples)
Slave2_numop[2:0] Number of read operations on Sensor3.
I
2 C slave address of the fourth external sensor (Sensor4) register (r/w).
Slave3_ add6
Slave3_ add5
Table 243. SLV3_ADD register
Slave3_ add4
Slave3_ add3
Slave3_ add2
Slave3_ add1
Slave3_ add0
Slave3_add[6:0] r_3
Table 244. SLV3_ADD register description
I
2
C slave address of Sensor4 that can be read by the sensor hub.
Default value: 0000000
Read operation on Sensor4 enable. Default value: 0
(0: read operation disabled; 1: read operation enabled) r_3
Address of register on the fourth external sensor (Sensor4) register (r/w).
Slave3_ reg7
Slave3_ reg6
Table 245. SLV3_SUBADD register
Slave3_ reg5
Slave3_ reg4
Slave3_ reg3
Slave3_ reg2
Slave3_ reg1
Slave3_ reg0
Slave3_reg[7:0]
Table 246. SLV3_SUBADD register description
Address of register on Sensor4 that has to be read according to the r_3 bit value
. Default value: 00000000
DocID028475 Rev 7 101/114
114
Embedded functions registers description - Bank A LSM6DSL
Fourth external sensor (Sensor4) configuration register (r/w).
Slave3_ rate1
Slave3_ rate0
Table 247. SLAVE3_CONFIG register
0
(1)
0
(1)
0
(1)
1. This bit must be set to ‘0’ for the correct operation of the device.
Slave3_ numop2
Slave3_ numop1
Slave3_ numop0
Slave3_rate[1:0]
Table 248. SLAVE3_CONFIG register description
Decimation of read operation on Sensor4 starting from the sensor hub trigger.
Default value: 00
(00: no decimation
01: update every 2 samples
10: update every 4 samples
11: update every 8 samples)
Slave3_numop[2:0] Number of read operations on Sensor4.
Data to be written into the slave device register (r/w).
Slave_ dataw7
Table 249. DATAWRITE_SRC_MODE_SUB_SLV0 register
Slave_ dataw6
Slave_ dataw5
Slave_ dataw4
Slave_ dataw3
Slave_ dataw2
Slave_ dataw1
Slave_ dataw0
Table 250. DATAWRITE_SRC_MODE_SUB_SLV0 register description
Slave_dataw[7:0]
Data to be written into the slave device according to the rw_0 bit in SLV0_ADD
(02h) register or address to be read in source mode.
Default value: 00000000
PEDO_FS 0
Table 251. CONFIG_PEDO_THS_MIN register
0 ths_min_4 ths_min_3 ths_min_2 ths_min_1 ths_min_0
PEDO_FS ths_min_[4:0]
Table 252. CONFIG_PEDO_THS_MIN register description
Pedometer data elaboration at 4 g.
(0: elaboration of 2 g data;
1: elaboration of 4 g data)
Minimum threshold to detect a peak. Default is 10h.
102/114 DocID028475 Rev 7
LSM6DSL Embedded functions registers description - Bank A
Significant motion configuration register (r/w).
SM_THS_
7
SM_THS_
6
Table 253. SM_THS register
SM_THS_
5
SM_THS_
4
SM_THS_
3
SM_THS_
2
SM_THS_
1
SM_THS_
0
SM_THS[7:0]
Table 254. SM_THS register description
Significant motion threshold. Default value: 00000110
DEB_
TIME4
0
Table 255. PEDO_DEB_REG register default values
DEB_
TIME3
DEB_
TIME2
DEB_
TIME1
DEB_
TIME0
DEB_
STEP2
DEB_
STEP1
1 1 0 1 1 1
DEB_ TIME[4:0]
Table 256. PEDO_DEB_REG register description
Debounce time. If the time between two consecutive steps is greater than
DEB_TIME*80ms, the debouncer is reactivated. Default value: 01101
DEB_ STEP[2:0]
Debounce threshold. Minimum number of steps to increment step counter
(debounce). Default value: 110
DEB_
STEP0
0
Time period register for step detection on delta time (r/w).
SC_
DELTA_7
SC_
DELTA_6
Table 257. STEP_COUNT_DELTA register
SC_
DELTA_5
SC_
DELTA_4
SC_
DELTA_3
SC_
DELTA_2
SC_
DELTA_1
SC_
DELTA_0
SC_DELTA[7:0]
Table 258. STEP_COUNT_DELTA register description
Time period value
(1)
(1LSB = 1.6384 s)
1. This value is effective if the TIMER_EN bit of CTRL10_C (19h) is set to 1 and the TIMER_HR bit of
register is set to 0.
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Embedded functions registers description - Bank A LSM6DSL
Soft-iron matrix correction register (r/w).
MAG_SI_
XX_7
MAG_SI_
XX_6
Table 259. MAG_SI_XX register
MAG_SI_
XX_5
MAG_SI_
XX_4
MAG_SI_
XX_3
MAG_SI_
XX_2
MAG_SI_
XX_1
MAG_SI_
XX_0
Table 260. MAG_SI_XX register description
MAG_SI_XX_[7:0]
Soft-iron correction row1 col1 coefficient
(1)
. Default value: 00001000
1. Value is expressed in sign-module format.
Soft-iron matrix correction register (r/w).
MAG_SI_
XY_7
MAG_SI_
XY_6
Table 261. MAG_SI_XY register
MAG_SI_
XY_5
MAG_SI_
XY_4
MAG_SI_
XY_3
MAG_SI_
XY_2
MAG_SI_
XY_1
MAG_SI_
XY_0
Table 262. MAG_SI_XY register description
MAG_SI_XY_[7:0] Soft-iron correction row1 col2 coefficient
(1)
. Default value: 00000000
1. Value is expressed in sign-module format.
Soft-iron matrix correction register (r/w).
MAG_SI_
XZ_7
MAG_SI_
XZ_6
Table 263. MAG_SI_XZ register
MAG_SI_
XZ_5
MAG_SI_
XZ_4
MAG_SI_
XZ_3
MAG_SI_
XZ_2
MAG_SI_
XZ_1
MAG_SI_
XZ_0
Table 264. MAG_SI_XZ register description
MAG_SI_XZ_[7:0] Soft-iron correction row1 col3 coefficient
(1)
. Default value: 00000000
1. Value is expressed in sign-module format.
104/114
Soft-iron matrix correction register (r/w).
MAG_SI_
YX_7
MAG_SI_
YX_6
Table 265. MAG_SI_YX register
MAG_SI_
YX_5
MAG_SI_
YX_4
MAG_SI_
YX_3
MAG_SI_
YX_2
MAG_SI_
YX_1
MAG_SI_
YX_0
Table 266. MAG_SI_YX register description
MAG_SI_YX_[7:0] Soft-iron correction row2 col1 coefficient
(1)
. Default value: 00000000
1. Value is expressed in sign-module format.
DocID028475 Rev 7
LSM6DSL Embedded functions registers description - Bank A
Soft-iron matrix correction register (r/w).
MAG_SI_
YY_7
MAG_SI_
YY_6
Table 267. MAG_SI_YY register
MAG_SI_
YY_5
MAG_SI_
YY_4
MAG_SI_
YY_3
MAG_SI_
YY_2
MAG_SI_
YY_1
MAG_SI_
YY_0
Table 268. MAG_SI_YY register description
MAG_SI_YY_[7:0] Soft-iron correction row2 col2 coefficient
(1)
. Default value: 00001000
1. Value is expressed in sign-module format.
Soft-iron matrix correction register (r/w).
MAG_SI_
YZ_7
MAG_SI_
YZ_6
Table 269. MAG_SI_YZ register
MAG_SI_
YZ_5
MAG_SI_
YZ_4
MAG_SI_
YZ_3
MAG_SI_
YZ_2
MAG_SI_
YZ_1
MAG_SI_
YZ_0
MAG_SI_YZ_[7:0]
Table 270. MAG_SI_YZ register description
Soft-iron correction row2 col3 coefficient
(1)
. Default value: 00000000
1. Value is expressed in sign-module format.
Soft-iron matrix correction register (r/w).
MAG_SI_
ZX_7
MAG_SI_
ZX_6
Table 271. MAG_SI_ZX register
MAG_SI_
ZX_5
MAG_SI_
ZX_4
MAG_SI_
ZX_3
MAG_SI_
ZX_2
MAG_SI_
ZX_1
MAG_SI_
ZX_0
Table 272. MAG_SI_ZX register description
MAG_SI_ZX_[7:0] Soft-iron correction row3 col1 coefficient
(1)
. Default value: 00000000
1. Value is expressed in sign-module format.
Soft-iron matrix correction register (r/w).
MAG_SI_
ZY_7
MAG_SI_
ZY_6
Table 273. MAG_SI_ZY register
MAG_SI_
ZY_5
MAG_SI_
ZY_4
MAG_SI_
ZY_3
MAG_SI_
ZY_2
MAG_SI_
ZY_1
MAG_SI_
ZY_0
Table 274. MAG_SI_ZY register description
MAG_SI_ZY_[7:0] Soft-iron correction row3 col2 coefficient
(1)
. Default value: 00000000
1. Value is expressed in sign-module format.
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114
Embedded functions registers description - Bank A LSM6DSL
Soft-iron matrix correction register (r/w).
MAG_SI_
ZZ_7
MAG_SI_
ZZ_6
Table 275. MAG_SI_ZZ register
MAG_SI_
ZZ_5
MAG_SI_
ZZ_4
MAG_SI_
ZZ_3
MAG_SI_
ZZ_2
MAG_SI_
ZZ_1
MAG_SI_
ZZ_0
Table 276. MAG_SI_ZZ register description
MAG_SI_ZZ_[7:0] Soft-iron correction row3 col3 coefficient
(1)
. Default value: 00001000
1. Value is expressed in sign-module format.
Offset for X-axis hard-iron compensation register (r/w). The value is expressed as a 16-bit word in two’s complement.
MAG_OFF
X_L_7
MAG_OFF
X_L_6
Table 277. MAG_OFFX_L register
MAG_OFF
X_L_5
MAG_OFF
X_L_4
MAG_OFF
X_L_3
MAG_OFF
X_L_2
MAG_OFF
X_L_1
MAG_OFF
X_L_0
Table 278. MAG_OFFX_L register description
MAG_OFFX_L_[7:0] Offset for X-axis hard-iron compensation. Default value: 00000000
Offset for X-axis hard-iron compensation register (r/w).The value is expressed as a 16-bit word in two’s complement.
MAG_OFF
X_H_7
MAG_OFF
X_H_6
Table 279. MAG_OFFX_H register
MAG_OFF
X_H_5
MAG_OFF
X_H_4
MAG_OFF
X_H_3
MAG_OFF
X_H_2
MAG_OFF
X_H_1
MAG_OFF
X_H_0
Table 280. MAG_OFFX_H register description
MAG_OFFX_H_[7:0] Offset for X-axis hard-iron compensation. Default value: 00000000
106/114
Offset for Y-axis hard-iron compensation register (r/w). The value is expressed as a 16-bit word in two’s complement.
MAG_OFF
Y_L_7
MAG_OFF
Y_L_6
Table 281. MAG_OFFY_L register
MAG_OFF
Y_L_5
MAG_OFF
Y_L_4
MAG_OFF
Y_L_3
MAG_OFF
Y_L_2
MAG_OFF
Y_L_1
MAG_OFF
Y_L_0
Table 282. MAG_OFFY_L register description
MAG_OFFY_L_[7:0] Offset for Y-axis hard-iron compensation. Default value: 00000000
DocID028475 Rev 7
LSM6DSL Embedded functions registers description - Bank A
Offset for Y-axis hard-iron compensation register (r/w). The value is expressed as a 16-bit word in two’s complement.
MAG_OFF
Y_H_7
MAG_OFF
Y_H_6
Table 283. MAG_OFFY_H register
MAG_OFF
Y_H_5
MAG_OFF
Y_H_4
MAG_OFF
Y_H_3
MAG_OFF
Y_H_2
MAG_OFF
Y_H_1
MAG_OFF
Y_H_0
Table 284. MAG_OFFY_H register description
MAG_OFFY_H_[7:0] Offset for Y-axis hard-iron compensation. Default value: 00000000
Offset for Z-axis hard-iron compensation register (r/w). The value is expressed as a 16-bit word in two’s complement.
MAG_OFF
Z_L_7
MAG_OFF
Z_L_6
Table 285. MAG_OFFZ_L register
MAG_OFF
Z_L_5
MAG_OFF
Z_L_4
MAG_OFF
Z_L_3
MAG_OFF
Z_L_2
MAG_OFF
Z_L_1
MAG_OFF
Z_L_0
Table 286. MAG_OFFZ_L register description
MAG_OFFZ_L_[7:0] Offset for Z-axis hard-iron compensation. Default value: 00000000
Offset for Z-axis hard-iron compensation register (r/w). The value is expressed as a 16-bit word in two’s complement.
MAG_OFF
Z_H_7
MAG_OFF
Z_H_6
Table 287. MAG_OFFZ_H register
MAG_OFF
Z_H_5
MAG_OFF
Z_H_4
MAG_OFF
Z_H_3
MAG_OFF
Z_H_2
MAG_OFF
Z_H_1
MAG_OFF
Z_H_0
Table 288. MAG_OFFZ_H register description
MAG_OFFZ_H_[7:0] Offset for Z-axis hard-iron compensation. Default value: 00000000
DocID028475 Rev 7 107/114
114
Embedded functions registers description - Bank B
12
LSM6DSL
Embedded functions registers description - Bank B
Absolute Wrist Tilt latency register (r/w).
WRIST_TILT
_ TIMER7
WRIST_TILT
_ TIMER6
Table 289. A_WRIST_TILT_LAT register
WRIST_TILT
_ TIMER5
WRIST_TILT
_ TIMER4
WRIST_TILT
_ TIMER3
WRIST_TILT
_ TIMER2
WRIST_TILT
_ TIMER1
WRIST_TILT
_ TIMER0
WRIST_TILT_TIMER[7:0]
Table 290. A_WRIST_TILT_LAT register description
Absolute wrist tilt latency parameters. 1 LSB = 40 ms.
Default value: 0Fh (600 ms)
Absolute Wrist Tilt threshold register (r/w).
WRIST_
TILT_ THS7
WRIST_
TILT_ THS6
Table 291. A_WRIST_TILT_THS register
WRIST_
TILT_ THS5
WRIST_
TILT_ THS4
WRIST_
TILT_ THS3
WRIST_
TILT_ THS2
WRIST_
TILT_ THS1
WRIST_
TILT_ THS0
WRIST_TILT_THS[7:0]
Table 292. A_WRIST_TILT_THS register description
Absolute wrist tilt threshold parameters. 1 LSB = 15.625 m g .
Default value: 20h (500 m g )
Absolute Wrist Tilt mask register (r/w).
WRIST_TILT_
MASK_ Xpos
WRIST_TILT_
MASK_ Xneg
Table 293. A_WRIST_TILT_Mask register
WRIST_TILT_
MASK_ Ypos
WRIST_TILT_
MASK_Yneg
WRIST_TILT_
MASK_ Zpos
WRIST_TILT_
MASK_ Zneg
Table 294. A_WRIST_TILT_Mask register description
WRIST_TILT_MASK_ Xpos
Absolute wrist tilt positive X-axis enable. Default value: 1
(0: disable; 1: enable)
WRIST_TILT_MASK_ Xneg
WRIST_TILT_MASK_ Ypos
WRIST_TILT_MASK_ Yneg
WRIST_TILT_MASK_ Zpos
WRIST_TILT_MASK_ Zneg
Absolute wrist tilt negative X-axis enable. Default value: 1
(0: disable; 1: enable)
Absolute wrist tilt positive Y-axis enable. Default value: 0
(0: disable; 1: enable)
Absolute wrist tilt negative Y-axis enable. Default value: 0
(0: disable; 1: enable)
Absolute wrist tilt positive Z-axis enable. Default value: 0
(0: disable; 1: enable)
Absolute wrist tilt negative Z-axis enable. Default value:0
(0: disable; 1: enable)
0
108/114 DocID028475 Rev 7
0
LSM6DSL Soldering information
The LGA package is compliant with the ECOPACK ® , RoHS and "Green" standard.
It is qualified for soldering heat resistance according to JEDEC J-STD-020.
Land pattern and soldering recommendations are available at www.st.com/mems .
DocID028475 Rev 7 109/114
114
Package information LSM6DSL
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
14.1 LGA-14 package information
Figure 17. LGA-14 2.5x3x0.86 mm package outline and mechanical data
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110/114 DocID028475 Rev 7
LSM6DSL
14.2 LGA-14 packing information
Figure 18. Carrier tape information for LGA-14 package
Package information
Figure 19. LGA-14 package orientation in carrier tape
DocID028475 Rev 7 111/114
114
Package information
Figure 20. Reel information for carrier tape of LGA-14 package
7
LSM6DSL
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Table 295. Reel dimensions for carrier tape of LGA-14 package
Reel dimensions (mm)
A (max)
B (min)
C
D (min)
N (min)
G
T (max)
330
1.5
13 ±0.25
20.2
60
12.4 +2/-0
18.4
112/114 DocID028475 Rev 7
LSM6DSL Revision history
Date
03-May-2017
29-Sep-2017
Revision
6
7
Table 296. Document revision history
Changes
Updated Section 4.4.2: I
2
C - inter-IC control interface (added Table 8: I
2
C master timing values )
Updated Figure 11 and Figure 13
Updated pin status mode 1 and 2 for pins 10 and 11 as well as adding procedure to disable pull-ups in Table 18: Internal pin status
Updated bit 0 in CTRL1_XL (10h)
Updated CTRL8_XL (17h)
Updated description of SW_RESET bit in Table 57: CTRL3_C register description
Updated description of X_OFS_USR (73h) , Y_OFS_USR (74h) , Z_OFS_USR (75h)
Minor textual updates
Updated
Table 3: Mechanical characteristics
Specified SPI mode 3 in
Section 4.4.1: SPI - serial peripheral interface
and throughout
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114
LSM6DSL
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114/114 DocID028475 Rev 7
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Key features
Low power consumption (0.4 mA in combo normal mode)
"Always-on" experience for accelerometer and gyroscope
Smart FIFO up to 4 kbyte
±2/±4/±8/±16 g full scale acceleration range
±125/±250/±500/±1000/±2000 dps full scale angular rate range
SPI & I2C serial interface
Frequently asked questions
The power consumption is 0.4 mA in combo normal mode.
The LSM6DSL has a full-scale acceleration range of ±2/±4/±8/±16 g.
Applications include motion tracking and gesture detection, indoor navigation, and vibration monitoring.
The LSM6DSL supports SPI and I2C serial interfaces.
Yes, it has a smart FIFO up to 4 kbyte.