STMicroelectronics MASTERGAN2 Datasheet
Reklamë
Reklamë
MASTERGAN2
Datasheet
High power density 600V Half bridge driver with two enhancement mode GaN
HEMT
Product status link
MASTERGAN2
Product label
Features
• 600 V system-in-package integrating half-bridge gate driver and high-voltage power GaN transistors in asymmetrical configuration:
– QFN 9 x 9 x 1 mm package
– R
DS(ON)
= 150 mΩ (LS) + 225 mΩ (HS)
– I
DS(MAX)
= 10 A (LS) + 6.5 A (HS)
• Reverse current capability
• Zero reverse recovery loss
• UVLO protection on low-side and high-side
• Internal bootstrap diode
• Interlocking function
• Dedicated pin for shutdown functionality
• Accurate internal timing match
• 3.3 V to 15 V compatible inputs with hysteresis and pull-down
• Overtemperature protection
• Bill of material reduction
• Very compact and simplified layout
• Flexible, easy and fast design.
Application
• Switch-mode power supplies
• Chargers and adapters
• High-voltage PFC, and DC-DC converters
Description
The MASTERGAN2 is an advanced power system-in-package integrating a gate driver and two enhancement mode GaN transistors in asymmetrical half ‑ bridge configuration.
The integrated power GaNs have 650 V drain ‑ source blocking voltage and R
DS(ON) of 150 mΩ and 225 mΩ for Low side and High side respectively, while the high side of the embedded gate driver can be easily supplied by the integrated bootstrap diode.
The MASTERGAN2 features UVLO protection on both the lower and upper driving sections, preventing the power switches from operating in low efficiency or dangerous conditions, and the interlocking function avoids cross-conduction conditions.
The input pins extended range allows easy interfacing with microcontrollers, DSP units or Hall effect sensors.
The MASTERGAN2 operates in the industrial temperature range, -40°C to 125°C.
The device is available in a compact 9x9 mm QFN package.
DS13597 - Rev 2.0
- June 2021
For further information contact your local STMicroelectronics sales office.
www.st.com
1
MASTERGAN2
Block diagram
Block diagram
Figure 1. MASTERGAN2 block diagram
BOOT OUTb GH VS
VCC
HIN
LIN
SD/OD
GND
VCC UVLO
Logic, interlocking, overtemp
Level Shifter
Vbo
UVLO
Driver
HON
HOFF
Level Shifter
RGON
H
RGOFF
Driver
LON
RGON
L
LOFF
RGOFF
L
R
BLEED
PVCC PGND GL
H
OUT
SENSE
DS13597 - Rev 2.0
page 2/29
2
Pin description and connection diagram
Figure 2. Pin connection (top view)
31 30 29 28 27 26 25 24 23
MASTERGAN2
Pin description and connection diagram
GND
EP1 PVCC 1
GL
PGND
2
3
22
21
BOOT
OUTb
20 GH
SENSE 4
SENSE 5
SENSE 6
SENSE 7
SENSE 8
SENSE
EP2
9 10 11
OUT
EP3
12 13 14
19 VS
18 VS
17
16
VS
VS
15 VS
2.1
Pin list
Table 1. Pin description
Pin Number
15, 16, 17, 18, 19
Pin Name
VS
Type
Power Supply
12, 13, 14, EP3 OUT Power Output
4, 5, 6, 7, 8, 9, 10, 11, EP2 SENSE Power Supply
22 BOOT Power Supply
21
27
1
28, EP1
3
26
24
25
2
20
23, 29, 30, 31
Function
High voltage supply (high-side GaN Drain)
Half-bridge output
Half-bridge sense (low-side GaN Source)
OUTb Power Supply
VCC Power Supply
PVCC Power Supply
GND Power Supply
Gate driver high-side supply voltage
Gate driver high-side reference voltage, used only for Bootstrap capacitor connection. Internally connected to OUT.
Logic supply voltage
Gate driver low-side supply voltage
PGND
HIN
LIN
Power Supply
Logic Input
Logic Input
Gate driver ground
Gate driver low-side buffer ground. Internally connected to
SENSE
High-Side driver logic input
Low-Side driver logic input
SD/OD Logic Input-Output Driver Shutdown input and Fault Open-Drain
GL
GH
N.C.
Output
Output
Not Connected
Low-Side GaN gate
High-Side GaN gate
Leave floating
DS13597 - Rev 2.0
page 3/29
3
3.1
MASTERGAN2
Electrical Data
Electrical Data
Absolute maximum ratings
Table 2. Absolute maximum ratings each voltage referred to GND unless otherwise specified
Symbol Parameter Test Condition Value Unit
V
DS
VCC
GaN Drain-to-Source Voltage
Logic supply voltage
PVCC-PGND Low-side driver supply voltage
VCC-PGND Logic supply vs. Low-side driver ground
PVCC
PGND
V
BO
BOOT
CGL, CGH
RGL, RGH
Low-side driver supply vs. logic ground
Low-side driver ground vs. logic ground
BOOT to OUTb voltage
Bootstrap voltage
Maximum external capacitance between GL and PGND and between GH and OUTb
Minimum external pull-down resistance between GL and
PGND and GH and OUTb
F
T
J
= 25 °C sw
I
I
D
D
Drain current (Low side GaN transistor)
Drain current (High side GaN transistor)
DC @ T
CB
= 25°C
DC @ T
CB
= 100°C
Peak @ T
CB
DC @ T
CB
= 25°C
DC @ T
CB
= 100°C
Peak @ T
CB
SR out
V i
T
J
T s
Half-bridge outputs slew rate (10% - 90%)
Logic inputs voltage range
Junction temperature
Storage temperature
1. PGND internally connected to SENSE
2. OUTb internally connected to OUT
3. CGx < 0.08/(Pvcc^2*Fsw)-(330*10 -12 )
4. T
CB
is temperature of case exposed pad.
5. Range estimated by characterization, not tested in production.
6. Value specified by design factor, pulse duration limited to 50 µs and junction temperature.
620 V
-0.3 to 11 V
-0.3 to 7 V
-0.3 to 18.3
V
-0.3 to 18.3
V
-7.3 to 11.3
V
-0.3 to 7
-0.3 to 620
3.9
6.8
9.7
6.4
17
6.5
4.4
12
100
-0.3 to 21
-40 to 150
-40 to 150
V
V nF kΩ
A
A
A
A
A
A
V/ns
V
°C
°C
DS13597 - Rev 2.0
page 4/29
3.2
3.3
MASTERGAN2
Recommended operating conditions
Recommended operating conditions
Table 3. Recommended operating conditions
Each voltage referred to GND unless otherwise specified
Symbol Parameter
VS
VCC
High voltage bus
Supply voltage
PVCC-PGND PVCC to PGND low side supply voltage (1)
PVCC Low-side driver supply voltage
VCC-PVCC VCC to PVCC pin voltage
PGND
DT
T
IN_MIN
Low-side driver ground
Suggested minimum deadtime
Minimum duration of input pulse to obtain undistorted output pulse
V
BO
BOOT to OUTb pin voltage
BOOT
V i
T
J
BOOT to GND voltage
Logic inputs voltage range
Junction temperature
1. PGND internally connected to SENSE
2. OUTb internally connected to OUT
3. 5 V is recommended during high-hide turn-on
Note
Best performance
Best performance
5
3
-3
Min Max Unit
0 520 V
4.75
9.5
V
4.75
6.5
V
6.5
V
8.5
V
3 V
-2
5
2 V ns
120 ns
4.4
6.5
V
5 6.5
V
0
530 V
0 20 V
-40 125 °C
Thermal data
Table 4. Thermal data
Symbol
R th(J-CB)_LS
R th(J-CB)_HS
R th(J-A)
Thermal resistance junction-to-ambient
Parameter
Thermal resistance Low side junction to SENSE exposed pad, typical
Thermal resistance High side junction to OUT exposed pad, typical
Value
1.9
2.8
17.8
Unit
°C/W
°C/W
°C/W
1. The junction to ambient thermal resistance is obtained simulating the device mounted on a 2s2p (4 layer) FR4 board as
JESD51-5,7 with 6 thermal vias for each exposed pad. Power dissipation uniformly distributed over the two GaN transistors.
DS13597 - Rev 2.0
page 5/29
4
4.1
MASTERGAN2
Electrical characteristics
Electrical characteristics
Driver
Table 5. Driver electrical characteristics
VCC = PVCC = 6 V; SENSE = GND; T
J specified)
= 25°C, unless otherwise specified (each voltage referred to GND unless otherwise
Symbol Parameter Test condition Min Typ Max Unit
Logic section supply
VCC thON
VCC thOFF
VCC hys
I
QVCCU
VCC UV turn OFF threshold
VCC undervoltage quiescent supply current VCC = PVCC = 3.8 V
4.2
4.5 4.75
V
3.9
4.2
4.5
V
0.2
0.3 0.45
V
320 410 μA
VCC vs. GND
I
QVCC
I
SVCC
VCC quiescent supply current
SD/OD = LIN = 5 V;
HIN = 0 V;
BOOT = 7 V
VCC switching supply current
SD/OD = 5 V;
V
BO
= 6.5 V;
VS = 0 V; F
SW
= 500 kHz
Low-side driver section supply
680 900 μA
0.8
mA
I
QPVCC
I
SPVCC
PVCC quiescent supply current
PVCC vs. PGND
PVCC switching supply current
GL vs. PGND Low side gate bleeder
SD/OD = LIN = 5 V
VS = 0 V
F
SW
= 500 kHz
PVCC = PGND
150
1.4
μA mA
75 100 125 kΩ R
BLEED
RON
L
ROFF
L
Low side turn on resistance
I(GL) = 1 mA (source)
Low side turn off resistance (2)
I(GL) = 1 mA (sink)
High-side floating section supply
52
2
Ω
Ω
V
BOthON
V
BOthOFF
V
BOhys
I
QBOU
BOOT vs. OUTb
V
BO
UV turn ON threshold
V
BO
V
BO
UV hysteresis
V
BO
undervoltage quiescent supply current
V
BO
= 3.4 V
3.6
4.0
4.4
V
3.4
3.7
4.0
V
0.1
0.3
0.5
V
140 200 μA
I
QBO
I
SBO
I
LK
R
DBoot
RON
H
ROFF
H
BOOT
V
BO
quiescent supply current
BOOT switching supply current
BOOT vs. SGND High voltage leakage current
VCC vs. BOOT Bootstrap diode on resistance
High side turn on resistance (2)
High side turn off resistance (2)
V
BO
= 6 V; LIN = GND;
SD/OD = HIN = 5 V;
V
BO
= 6 V;
SD/OD = 5 V;
VS = 0 V; F
SW
= 500 kHz
BOOT = OUT = 600 V
SD/OD = LIN = 5 V;
HIN = GND = PGND
VCC – BOOT = 0.5 V
I(GH) = 1 mA (source)
I(GH) = 1 mA (sink)
217
1.9
μA mA
11 μA
140 175 Ω
77
2
Ω
Ω
DS13597 - Rev 2.0
page 6/29
DS13597 - Rev 2.0
MASTERGAN2
Driver
Symbol Parameter
Logic inputs
Test condition Min Typ Max Unit
V
V il ih
LIN, HIN, SD/OD
Low level logic threshold
High level logic threshold
T
J
= 25°C 1.1 1.31 1.45
Full Temperature range
0.8
T
J
= 25°C
Full Temperature range
2 2.17 2.5
2.7
V
V
V ihys
I
INh
I
INl
R
PD_IN
I
SDh
I
SDl
LIN, HIN
SD/OD
SD/OD
Logic input threshold hysteresis
Logic ‘1’ input bias current
Logic ‘0’ input bias current
Input pull-down resistor
Logic “1” input bias current
Logic “0” input bias current
LIN, HIN = 5 V
LIN, HIN = GND
LIN, HIN = 5 V
SD/OD = 5 V
SD/OD = 0 V
0.7 0.96 1.2
23
90
11
33 55
1
150 220
15 20
1
V
μA
μA kΩ
μA
μA
R
R
I
PD_SD
V
TSD
ON_OD
OL_OD
SD/OD
SD/OD
SD/OD
SD/OD
Pull-down resistor
Thermal shutdown unlatch threshold
Open drain ON resistance
Open Drain low level sink current
SD/OD = 5 V
OpenDrain OFF
T
J
= 25°C
T
J
= 25°C;
I
OD
= 400 mV
T
J
= 25°C;
V
OD
= 400 mV
T d_GL
T d_GH
LIN,GL
HIN,GH
Prop. delay from LIN to GL
Prop. delay from HIN to GH
Overtemperature protection
T
TSD
T
HYS
Shutdown temperature
Temperature hysteresis
1. VCC UVLO is referred to VCC - GND
2. Turn on and turn off total resistances include the values of the gate resistors and the driver Rdson
3. V
BO
= V
BOOT
- V
OUT
4. R
BD(on)
is tested in the following way:
R
BD(on)
= [(VCC - V
BOOTa
) - (VCC - V
BOOTb
)] / [I a
- I b
]
Where: I a
is BOOT pin current when V
BOOT
= V
BOOTa
; I b
is BOOT pin current when V
BOOT
= V
BOOTb
5. Range estimated by characterization, not tested in production.
6. Tested at wafer level.
250 330 450 kΩ
0.5 0.75
8
22
-
-
10
40
46
46
175
20
1
18
50
-
-
V
Ω mA
°C
°C page 7/29
4.2
MASTERGAN2
GaN power transistor
GaN power transistor
Table 6. GaN power transistor electrical characteristics
V
GS
= 6 V; T
J
= 25°C, unless otherwise specified
Symbol Parameter Test condition
R
R
I
I
V
I
I
(BR)DS
DSS_LS
DSS_HS
V
GS(th)
GS_LS
GS_HS
DS(on)_LS
DS(on)_HS
Drain-source blocking voltage
Gate threshold voltage
GaN on/off states
Zero gate voltage drain current - low side
Zero gate voltage drain current - high side
Low side I
DSS
< 18 µA
High side I
DSS
V
GS
= 0 V
V
DS
= 600 V
V
GS
= 0 V
V
DS
= 600 V
V
GS
= 0 V
V
DS
= V
GS
Low side, I
D
= 2.5 mA
High side, I
D
Gate to source current - Low side
Gate to source current - High side
V
DS
= 0 V
V
DS
Static drain-source on-resistance - Low side
Static drain-source on-resistance - High side I
I
D
D
= 3.2 A
= 2.2 A
T
J
= 25°C
T
J
T
J
= 25°C
T
J
1. Tested at wafer level.
2. Value estimated by characterization, not tested in production.
Min Typ Max Unit
650
0.7
0.5
1.7
V
µA
µA
V
57
40
150 220
330
225 300
495
µA
µA mΩ mΩ
DS13597 - Rev 2.0
page 8/29
5
MASTERGAN2
Device characterization values
Device characterization values
The information in
Table 7 and Table 8 represents typical values based on characterization and simulation results
and are not subject to the production test.
Table 7. GaN power transistor characterization values
Symbol
Q
G
Total gate charge
Parameter Test condition
V
GS
= 6 V, T
J
= 25°C
V
DS
= 0 to 400 V - Low side
V
GS
= 6 V, T
J
= 25°C
V
DS
= 0 to 400 V - High side
Min Typ Max Unit
2
1.5
nC nC
Q
E
C
OSS
OSS
OSS
Output charge - Low side
Output charge - High side
Output capacitance stored energy - Low side
Output capacitance stored energy - High side
Output capacitance - Low side
Output capacitance - High side
V
V
GS
DS
= 0 V,
= 400 V
20
14
2.7
1.7
20
14.2
C
O(ER)
C
O(TR)
Effective output capacitance energy related - Low side
Effective output capacitance energy related - High side
Effective output capacitance time related - Low side
Effective output capacitance time related - High side (2)
V
DS
V
GS
= 0 V,
= 0 to 400 V
31
21
50
34 pF pF pF pF
Q
RR
I
RRM
Reverse recovery charge
Reverse recovery current
0
0 nC
1. C
O(ER)
is the fixed capacitance that would give the same stored energy as C
OSS
V
DS
while V
DS
is rising from 0 V to the stated
2. C
O(TR)
is the fixed capacitance that would give the same charging time as C
V
DS
OSS
while V
DS
is rising from 0 V to the stated
A nC nC
µJ
µJ pF pF
Symbol t
(on)
t
C(on)
t
C(off)
t
SD
E on
Table 8. Inductive load switching characteristics
Parameter
Turn-on time - Low side
Turn-on time - High side
Crossover time (on) - Low side
Crossover time (on) - High side
Turn-off time - Low side
Turn-off time - High side
Crossover time (off) - Low side
Crossover time (off) - High side
Shutdown to high/low-side propagation delay
Turn-on switching losses - Low side
Turn-on switching losses - High side
Test condition
V
S
= 400 V,
V
GS
= 6 V,
I
D_LS
= 3.2 A,
I
D_HS
= 2.2 A
Min Typ Max Unit
70
70
15
25
70
70
15
10 ns ns ns ns ns ns ns ns
70
12.5
10 ns
µJ
µJ
DS13597 - Rev 2.0
page 9/29
MASTERGAN2
Device characterization values
Symbol
E off
Turn-off switching losses
Parameter Test condition
V
S
= 400 V,
V
GS
= 6 V,
I
D_LS
= 3.2 A,
I
D_HS
= 2.2 A
Min Typ
2.5
Max
1. t
(on) and t
(off)
include the propagation delay time of the internal driver
2. t
C(on)
and t
C(off)
are the switching times of GaN transistor itself under the internally given gate driving conditions
Unit
µJ
Figure 3. Switching time definition
V
DS
I
D
I
D
V
DS
DS13597 - Rev 2.0
10%I
D
V
IN t
(ON) t
C(ON)
(a) turn-on
10%V
DS
10%V
DS
V
IN t
(OFF) t
C(OFF)
(b) turn-off
10%I
D
10
5
0
0
Figure 4. Typ I
D_LS
vs. V
DS
at T
J
=25°C
30
T
J
=25°C
6V
25
5V
20
4V
15
1 2
V
DS
(V)
3 4 5
4
2
0
0
Figure 5. Typ I
D_LS
vs. V
DS
at T
J
=125°C
12
T
J
=125°C 6V
5V
10
4V
8
6
1 2
V
DS
(V)
3 4 5 page 10/29
DS13597 - Rev 2.0
12
10
8
6
4
2
0
0
Figure 6. Typ I
D_HS
vs. V
DS
at T
J
=25°C
20
T
J
=25°C
18
V
GS
=6V
16
14
V
GS
=5V
1 2
V
DS
(V)
3 4
V
GS
=4V
5
0.17
0.16
0.15
0.14
0
Figure 8. Typ R
DS(on)_LS
vs. I
D
at T
J
=25°C
0.22
T
J
=25°C
4V 5V
0.21
0.20
6V
0.19
0.18
5 10 15
I
D
(A)
20 25 30
MASTERGAN2
Device characterization values
6
5
4
3
2
1
0
0
Figure 7. Typ I
D_HS
vs. V
DS
at T
J
=125°C
10
T
J
=125°C
9
V
GS
=6V
8
7
V
GS
=5V
1 2
V
DS
(V)
3 4
V
GS
=4V
5
Figure 9. Typ R
DS(on)_LS vs. I
D
at T
J
=125°C
0.47
T
J
=125°C
0.45
4V
0.43
0.41
0.39
5V
0.37
0.35
0.33
0.31
0 2 4 6
I
D
(A)
8 10
6V
12 page 11/29
DS13597 - Rev 2.0
Figure 10. Typ R
DS(on)_HS
vs. I
D
at T
J
=25°C
0.38
T
J
=25°C
4V
0.36
0.34
0.32
0.30
5V
0.28
0.26
6V
0.24
0.22
0 2 4 6 8 10
I
D
(A)
12 14 16 18 20
MASTERGAN2
Device characterization values
Figure 11. Typ R
DS(on)_HS
vs. I
D
at T
J
=125°C
0.69
T
J
=125°C
4V
0.66
0.63
5V
0.60
0.57
6V
0.54
0.51
0.48
0.45
0 1 2 3 4 5
I
D
(A)
6 7 8 9 10
Figure 12. Typ I
D_LS
vs. V
DS
30
V
GS
=6V
25
T
J
=25°C
20
15
T
J
=50°C
T
J
=75°C
T
J
=100°C
T
J
=125°C
10
5
0
0 1 2
V
DS
(V)
3 4 5
12
10
8
6
16
14
4
2
0
0
Figure 13. Typ I
D_HS
vs. V
DS
20
18
V
GS
=6V
1 2
V
DS
(V)
3 4
T
J
=25°C
T
J
=50°C
T
J
=75°C
T
J
=100°C
T
J
=125°C
5 page 12/29
DS13597 - Rev 2.0
MASTERGAN2
Device characterization values
Figure 14. Typ R
DS(on)
vs. T
J
normalized at 25°C
3.0
2.5
2.0
1.5
1.0
0.5
0
-50 -10 30 70
Temperature (°C)
110 150
30
25
20
15
10
5
Figure 15. Typ I
SD_LS
vs. V
SD_LS
at T
J
=25°C
50
T
J
=25°C
45
40
V
GS
=6V
35
V
GS
=0V
0
0 1 2 3 4 5 6 7 8 9 10
V
SD
(V)
Figure 16. Typ I
SD_LS
vs. V
SD_LS
at T
J
=125°C
24
T
J
=125°C
22
V
GS
=6V
20
18
16
V
GS
=0V
14
12
10
8
4
6
2
0
0 1 2 3 4 5 6 7 8 9 10
V
SD
(V) page 13/29
DS13597 - Rev 2.0
MASTERGAN2
Device characterization values
Figure 17. Typ I
SD_HS
vs. V
SD_HS
at T
J
=25°C
40
T
J
=25°C
36
32
V
GS
=6V
28
24
20
16
12
8
V
GS
=0V
4
0
0 1 2 3 4 5 6 7 8 9 10
V
SD
(V)
12
10
8
6
4
2
Figure 18. Typ I
SD_HS
vs. V
SD_HS
at T
J
=125°C
20
T
J
=125°C
18
16
V
GS
=6V
14
V
GS
=0V
0
0 1 2 3 4 5 6 7 8 9 10
V
SD
(V)
Figure 19. Safe Operating Area (LS) at T
J
=25°C
10
0.2 μs
50 μs
1
DC
0.1
Figure 20. Safe Operating Area (HS) at T
J
=25°C
0.2 μs
10
1
0.1
50 μs
DC
0.01
1 10
Vds (V)
100 1000
0.01
1 10
Vds (V)
100 1000 page 14/29
DS13597 - Rev 2.0
MASTERGAN2
Device characterization values
Figure 21. Typical Gate Charge (LS) at T
J
=25°C
7
400 V
6
100 V
5
2
1
0
0
4
3
0.5
1 1.5
Q
G
(nC)
2 2.5
Figure 22. Typical Gate Charge (HS) at T
J
=25°C
7
400 V
6
100 V
5
2
1
0
0
4
3
0.5
1 1.5
Q
G
(nC)
2 2.5
70
Figure 23. LS Derating curve
60
50
40
30
20
10
0
0 25 50 75 100
T
CB
(°C)
125 150
20
10
0
0
70
Figure 24. HS Derating curve
60
50
40
30
25 50 75 100
T
CB
(°C)
125 150 page 15/29
300
Figure 25. Typ R
Dboot
vs. T
J
250
200
150
100
50
0
-50 -10 30 70 110
Temperature (°C)
150
MASTERGAN2
Device characterization values
DS13597 - Rev 2.0
page 16/29
6
6.1
6.2
6.3
MASTERGAN2
Functional description
Functional description
Logic inputs
The MASTERGAN2 features a half-bridge gate driver with three logic inputs to control the internal high-side and low-side GaN transistors.
The devices are controlled through the following logic inputs:
• SD/OD: Shutdown input, active low
• LIN: low-side driver inputs, active high
• HIN: high-side driver inputs, active high
SD/OD
H
H
L
H
H
1. X: Don’t care
2. Interlocking
Table 9. Inputs truth table (applicable when device is not in UVLO)
Input pins
LIN
L
L
H
H
HIN
X
L
H
L
H
LS
OFF
OFF
OFF
ON
OFF
GaN transistors status
HS
OFF
OFF
ON
OFF
OFF
The logic inputs have internal pull-down resistors. The purpose of these resistors is to set a proper logic level in case, for example, there is an interruption in the logic lines or the controller outputs are in tri-state conditions.
If logic inputs are left floating, the gate driver outputs are set to low level and the correspondent GaN transistors are turned off.
The minimum duration of the on time of the pulses applied to LIN is T
IN_MIN
= 120ns; shorter pulses shall be either extended to T
IN_MIN
or blanked, when shorter than 30ns (typ).
The minimum duration of the off time of the pulses applied to HIN is T
IN_MIN
= 120ns; shorter pulses shall be either extended to T
IN_MIN
or blanked, when shorter than 30ns (typ).
Interlocking feature interrupts running T
IN_MIN
to avoid unexpected cross-conduction.
Matched, short propagation delay between low side and high side are there.
Bootstrap structure
A bootstrap circuitry is typically used to supply the high-voltage section. MASTERGAN2 integrates this structure, realized by a patented integrated high-voltage DMOS, to reduce the external components.
The Boostrap integrated circuit is connected to VCC pin and is driven synchronously with the low-side driver.
The use of an external bootstrap diode in parallel to the integrated structure is possible, in particular if the operating frequency is approximately higher than 500 kHz.
VCC supply pins and UVLO function
The VCC pin supplies current to the logic circuit, level-shifters in the low-side section and the integrated bootstrap diode.
The PVCC pin supplies low-side output buffer. During output commutations the average current used to provide gate charge to the high-side and low-side GaN transistors flows through this pin.
DS13597 - Rev 2.0
page 17/29
6.4
MASTERGAN2
VBO UVLO protection
The PVCC pin can be connected either to the same supply voltage of the VCC pin or to a separate voltage source. In case the same voltage source is used, it is suggested to connect VCC and PVCC pins by means of a small decoupling resistance. The use of dedicated bypass ceramic capacitors located as close as possible to each supply pin is highly recommended.
The MASTERGAN2 VCC supply voltage is continuously monitored by under-voltage lockout (UVLO) circuitry that turns both the high-side and low-side GaN transistors off when the supply voltage goes below the V
CC_thOFF threshold. The UVLO circuitry turns on the GaN, according to LIN and HIN status, approximately 20 µs (typ) after the supply voltage goes above the V
CCthON
voltage. A V
CChys
hysteresis is provided for noise rejection purposes.
Figure 26. VCC UVLO and Low Side
VCC = PVCC
VCC rise Tdelay_VCC
UVLO VCC
VCC thON
VCC thOFF
Tdelay_VCC
0V
LIN
GL-PGND
0V
PVCC
0V
V
BO
UVLO protection
Dedicated undervoltage protection is available on the bootstrap section between BOOT and OUTb supply pins. In order to avoid intermittent operation, a hysteresis sets the turn-off threshold with respect to the turn-on threshold.
Approximately 5 µs (typ) after V
BO
voltage falls below V
BOthOFF
threshold, the high-side GaN transistor is switched off. When V
BO
voltage reaches the V
BOthON
threshold, the device returns to normal operation and the output remains off until the next input pin transition that requests the high-side to turn on.
Figure 27. V
BO
UVLO and High Side
VCC
VCC thON
VCC thOFF
0V
V
BO
V
BOthON
V
BOthOFF
0V
UVLO VBO
V
BO rise
HIN
(GH-OUTB)
0V
V
BO
0V
DS13597 - Rev 2.0
page 18/29
6.5
MASTERGAN2
Thermal shutdown
Thermal shutdown
The integrated gate driver has a thermal shutdown protection.
When junction temperature reaches the T
TSD
temperature threshold, the device turns off both GaN transistors, leaving the half-bridge in 3-state and signaling the state forcing SD/OD pin low. SD/OD pin is released when junction temperature is below T
TSD
-T
HYS
and SD/OD is below V
TSD
.
GaN are driven again according to inputs when SD/OD rises above V ih
.
The thermal smart shutdown system provides the possibility to increase the time constant of the external RC network (that determines the disable time after the overtemperature event) up to very large values without delaying the protection.
Figure 28. Thermal shutdown timing waveform
T
TSD
T
J
T
TSD -
T
HYS
Fast shut down
the driver outputs are switched off immediately after overtemperature
GH/GL
SD/OD
V
OD
V ih
V
TSD
0 V
1
OD gate
(internal)
2 t
1 disable time t
2
THERMAL SHUTDOWN CIRCUIT
FROM / TO
CONTROLLER
V
PU
R
OD_ext
SD/OD
C
OD R
PD_SD
R
ON_OD
THERMAL
SHUTDOWN
LOGIC
DS13597 - Rev 2.0
page 19/29
7
Typical application diagrams
Figure 29. Asymmetrical Active clamp flyback
H.V.
C
BOOT
C
C
BOOT OUTb GH
V
CC
+
FROM/TO CONTROLLER
R
C
FROM/TO CONTROLLER
R
C
V
PU
FROM/TO CONTROLLER
R
C
VCC
VCC
HIN
LIN
SD/OD
GND
VCC UVLO
Logic, interlocking, overtemp
Level Shifter
Vbo
UVLO
Driver
HON
HOFF
RON
H
ROFF
H
Level Shifter Driver
LON
RON
L
LOFF
ROFF
L
R
BLEED
PVCC PGND
V
CC
TO CONTROLLER
C
PVCC
GL
VS
OUT
SENSE
Cbu
S
MASTERGAN2
Typical application diagrams
VOUT
DS13597 - Rev 2.0
page 20/29
8
8.1
Note:
MASTERGAN2
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
QFN 9 x 9 x 1 mm, 31 leads, pitch 0.6 mm package information
Symbol e
K
L
N aaa bbb ccc ddd eee
E
D1
E1
D2
E2
D3
E3
A
A3 b
D
Table 10. QFN 9 x 9 x 1 mm package dimensions
Min.
0.90
2.06
1.76
3.10
1.70
3.10
0.25
8.96
8.96
3.30
0.35
Dimensions (mm)
0.60
0.24
0.45
31
0.10
0.10
0.10
0.05
0.08
2.16
1.86
3.20
1.80
3.20
Typ.
0.95
0.10
0.30
9.00
9.00
3.40
1.
Dimensioning and tolerances conform to ASME Y14.5-2009.
2.
All dimensions are in millimeters.
3.
N total number of terminals.
4.
Dimensions do not include mold protrusion, not to exceed 0.15 mm.
5.
Package outline exclusive of metal burr dimensions.
Max.
1.00
2.26
1.96
3.30
1.90
3.30
0.35
9.04
9.04
3.50
0.55
DS13597 - Rev 2.0
page 21/29
DS13597 - Rev 2.0
MASTERGAN2
QFN 9 x 9 x 1 mm, 31 leads, pitch 0.6 mm package information
Figure 30. QFN 9 x 9 x 1 mm package dimensions
BOTTOM VIEW
SIDE
VIEW
TOP VIEW
page 22/29
9
MASTERGAN2
Suggested footprint
Suggested footprint
The MASTERGAN2 footprint for the PCB layout is usually defined based on several design factors such as assembly plant technology capabilities and board component density. For easy device usage and evaluation, ST provides the following footprint design, which is suitable for the largest variety of PCBs.
The following footprint indicates the copper area that should be free of solder mask, and shall extend beyond the indicated areas, especially for EP2 and EP3. To aid thermal dissipation, it is recommended to add thermal vias under these EPADs to transfer and dissipate device heat to the other PCB copper layers. A PCB layout example is available with the MASTERGAN2 evaluation board.
Figure 31. Suggested footprint (top view drawing)
TOP VIEW
Dimensions in mm
DS13597 - Rev 2.0
page 23/29
10
MASTERGAN2
Ordering information
Ordering information
Order code
MASTERGAN2
MASTERGAN2TR
Table 11. Order codes
Package
QFN 9 x 9 x 1 mm
QFN 9 x 9 x 1 mm
Package Marking
MASTERGAN2
MASTERGAN2
Packaging
Tray
Tape and Reel
DS13597 - Rev 2.0
page 24/29
MASTERGAN2
Revision history
Table 12. Document revision history
Date
01-Dec-2020
Version
1
21-Jun-2021 2
Changes
Initial release.
Corrected Table 2 : CGL, CGH test conditions; Added Lines in
Table 5 : Td_GL and Td_GH; Added
.
DS13597 - Rev 2.0
page 25/29
MASTERGAN2
Contents
Contents
DS13597 - Rev 2.0
page 26/29
MASTERGAN2
List of tables
List of tables
DS13597 - Rev 2.0
page 27/29
MASTERGAN2
List of figures
List of figures
Figure 19. Safe Operating Area (LS) at T
Figure 20. Safe Operating Area (HS) at T
Figure 21. Typical Gate Charge (LS) at T
Figure 22. Typical Gate Charge (HS) at T
DS13597 - Rev 2.0
page 28/29
MASTERGAN2
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks . All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2021 STMicroelectronics – All rights reserved
DS13597 - Rev 2.0
page 29/29
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