STMicroelectronics PWD5F60 Datasheet
تبلیغات
تبلیغات
PWD5F60
Datasheet
High density power driver - high voltage full bridge with integrated comparators
VFQFPN 15 x 7 x 1 mm
Product status link
PWD5F60
Product summary
Marking PWD5F60
Package VFQFPN 15x7x1mm
PWD5F60
Order codes
Tray
PWD5F60TR Tape and Reel
Features
• Power system-in-package integrating gate drivers and high-voltage power
MOSFETs
– R
DS(ON)
= 1.38 Ω
– BV
DSS
= 600 V
• Suitable for operating as
– full bridge
– dual independent half bridges
• UVLO protection on low-side and high-side
• 3.3 V to 15 V compatible inputs with hysteresis and pull-down
• Internal bootstrap diode
• Uncommitted comparators
• Adjustable dead-time
• Bill of material reduction
• Very compact and simplified layout
• Flexible, easy and fast design
Applications
• Industrial fans and pumps
• Cooking hoods and gas heaters
• Blowers
• Industrial drives and factory automation
• Power supply units
Description
The PWD5F60 is an advanced power system-in package integrating gate drivers and four N-channel power MOSFETs in dual half-bridge configuration.
The integrated power MOSFETs have R
DS(ON)
of 1.38 Ω and 600 V drain-source breakdown voltage, while the embedded gate drivers high side can be easily supplied by the integrated bootstrap diode. The high integration of the device allows to efficiently drive loads in a tiny space.
The PWD5F60 accepts a supply voltage (VCC) extending over a wide range (10 V to
20 V) and also features UVLO protection on both the lower and upper driving sections, preventing the power switches from operating in low efficiency or dangerous conditions.
The input pins extended range allows easy interfacing with microcontrollers, DSP units or Hall effect sensors.
The PWD5F60 embeds two uncommitted comparators available for protections against overcurrent, overtemperature, etc.
The PWD5F60 operates in the industrial temperature range, -40 °C to 125 °C.
The device is available in a compact VFQFPN package.
DS12543 - Rev 1 - July 2018
For further information contact your local STMicroelectronics sales office.
www.st.com
1
Block diagram
Figure 2. Block diagram
PWD5F60
Block diagram
DS12543 - Rev 1 page 2/26
2
Pin description and connection diagram
Figure 3. Pin connection (top view)
PWD5F60
Pin description and connection diagram
CP+2 1
CP-2 2
SENSE2 3
GND2 4
OUT2 5
OUT2 6
OUT2 7
OUT2 8
OUT2
EPAD2
GND2
EPAD1
37 IN2
36 reserved
35 BOOT2
34 OUTB2
VS
EPAD6
33 VS
32 VS
31 VS
VS 9
VS 10
VS 11
VS
EPAD3
OUT1
EPAD5
30 OUT1
29 OUT1
28 OUT1
27 OUT1
OUTB1 12
BOOT1 13
IN1 14
GND1
EPAD4
26 GND1
25 SENSE1
24 CP-1
23 CP+1
DS12543 - Rev 1 page 3/26
2.1
PWD5F60
Pin list
Pin list
Table 1. Pin description
Pin number
9, 10, 11, 31, 32, 33, EPAD3,
EPAD6
27, 28, 29, 30, EPAD5
5, 6, 7, 8, EPAD2
16, 22, 26, EPAD4
4, 40, 46, EPAD1
14
37
15
38
17
41
19
43
21
45
23
1
24
2
36, 39, EPAD7
20, 44,
13
35
18
42
12
34
25
3
Pin name
VS
Type Function
Power Supply High voltage supply (high-side MOSFET Drain)
IN1
IN2
SD1
SD2
PWM1
PWM2
DT1
DT2
CPOUT1
CPOUT2
CP+1
CP+2
CP-1
CP-2 reserved
NC
OUT1 Power Output Half-bridge 1 output
OUT2 Power Output Half-bridge 2 output
OUTB1
Power supply Half-bridge 1 output connection for high-side supply capacitor (2)
OUTB2
Power supply Half-bridge 2 output connection for high-side supply capacitor (3)
SENSE1 Power Supply Half-bridge 1 sense (low-side MOSFET Source)
SENSE2 Power Supply Half-bridge 2 sense (low-side MOSFET Source)
BOOT1 Power Supply Gate driver 1 high-side supply voltage
BOOT2 Power Supply Gate driver 2 high-side supply voltage
VCC1 Power Supply Gate driver 1 supply voltage
VCC2 Power Supply Gate driver 1 supply voltage
GND1 Power Supply Gate driver 1 ground
GND2 Power Supply Gate driver 2 ground
Logic Input Driver 1 logic input
Logic Input Driver 2 logic input
Logic Input Driver 1 shut down input (active low)
Logic Input Driver 2 shut down input (active low)
Logic Input Driver 1 PWM input
Logic Input Driver 2 PWM input
Input Driver 1 dead time setting
Input
Output
Output
Input
Input
Input
Input
Driver 2 dead time setting
Comparator 1 output (open drain)
Comparator 2 output (open drain)
Comparator 1 positive input
Comparator 2 positive input
Comparator 1 negative input
Comparator 2 negative input
Reserved Not connected
Reserved Not connected
1. EPAD3 is internally connected with EPAD6. No connection is required at PCB level.
2. Pin 12 is internally connected to OUT1. No connection is required at PCB level.
3. Pin 34 is internally connected to OUT2. No connection is required at the PCB level. Use pin 34 for bootstrap capacitor connection only.
DS12543 - Rev 1 page 4/26
PWD5F60
Electrical data
3
Electrical data
3.1
3.2
Absolute maximum ratings
Table 2. Absolute maximum ratings
Symbol Parameter
V
DS
MOSFET Drain-to-Source Voltage
VCC1
,
VCC2 Drivers supply voltage
VCCx-SENSEx VCCx to SENSEx pin voltage
V
BOOTx
V
BO1,
V
BO2
V
CP+x,
V
CP-x
V
CPOUTx
Bootstrap voltage
BOOTx to OUTx pin voltage
Comparator input pin voltage
Comparator open-drain output voltage
I
D
T
J
= 25 °C
Test Condition
-
-
-
-
Drain current (per MOSFET)
DC @ T
CB
DC @ T
CB
Peak @ T
CB
= 25 °C
Full-bridge outputs slew rate (10% - 90%)
SR
OUT
V i
T
J
T s
Logic inputs voltage range
Junction temperature
Storage temperature
-
-
-
-
P tot
Total power dissipation
-
T
CB
= 25 °C for each MOSFET
T amb
= 25 °C, whole device, device mounted on an FR4 2s2p board as per
.
ESD
Human body model
Charged device model -
-
Value
600
-0.3 to 20
-0.3 to 25
GNDx-0.3 to 600
-0.3 to 20
-0.3 to V
CCx
+0.3
V
-0.3 to 15
3.5
2
14
40
-0.3 to 15
-40 to 150
-40 to 150
43
5
±1500
±500
1. T
CB
is temperature of case bottom pad.
2. Characterized, not tested in production.
3. The value specified by design factor, pulse duration limited by max junction temperature and SOA.
4. Value calculated based on thermal resistance, power uniformly distributed over the four power MOSFETs, still air.
5. Actual applicative board max dissipation could be higher or lower depending on layout and cooling techniques.
Unit
V
V
V
V
V
V
A
A
A
V/ns
V
°C
°C
W
W
V
V
Recommended operating conditions
Symbol
VCC1, VCC2
V
BO1,
V
BO2
V
CP-x
Table 3. Recommended operating conditions
Pin Parameter
VCCx -GNDx Driver Supply voltage
BOOTx -OUTx BOOTx to OUTx pin voltage
CP-x Comparator negative input voltage
Test Condition Min.
-
-
V
CP+
≤ 2.5 V
10
9.8
-
Max.
20
20
V
CCx
Unit
V
V
V
DS12543 - Rev 1 page 5/26
3.3
PWD5F60
Thermal data
Symbol
V
CP+x
T
J
Pin
CP+x
-
Parameter
Comparator positive input voltage
Junction temperature
Test Condition
V
CP-
≤ 2.5 V
-
1. At least one of the comparator inputs must be lower than 2.5 V to guarantee proper operation.
Min.
-
-40
Max.
V
CCx
125
Unit
V
°C
Thermal data
Table 4. Thermal data
Symbol Parameter Value Unit
R th(J-CB)
R th(J-A)
Thermal resistance junction to each MOSFET exposed pad, typical
Thermal resistance junction-to-ambient
2.85
25
°C/W
°C/W
1. The junction to ambient thermal resistance is obtained simulating the device mounted on a 2s2p (4-layer) FR4 board as per
JESD51-5,7 with 4 thermal vias for each MOSFET pad. Power dissipation is uniformly distributed over the four power
MOSFETs.
DS12543 - Rev 1 page 6/26
PWD5F60
Electrical characteristics
4
Electrical characteristics
4.1
Driver
VCCx = 15 V; T
J
= 25 °C, unless otherwise specified.
Symbol
VCC
_hys
VCC
_thON
VCC
_thOFF
I qccu
I qcc
V
BO_hys
V
BO_thON
V
BO_thOFF
BOOTx vs. OUTx
I
QBOU
I
QBO
R
BD(on)
VCCx vs. BOOTx
V il
V ih
I ih
I il
R in_pd
V io
I ib
Pin
VCCx vs. GNDx
INx, PWMx, SDx
CP-x, CP+x vs.
GNDx
Table 5. Driver electrical characteristics
Parameter Test condition
Low supply voltage section
VCC UV hysteresis
VCC UV turn ON threshold
-
-
VCC UV turn OFF threshold -
Undervoltage quiescent supply current
Quiescent current
VCC = 7 V;
SD = 5 V; IN = PWM = GND;
R
DT
= 0 Ω;
CP+ = GND; CP- = 0.5 V
VCC = 15 V;
SD = 5 V; IN = PWM = GND;
R
DT
= 0 Ω;
CP+ = GND; CP- = 0.5 V
Bootstrapped supply voltage section
V
BO
UV hysteresis
V
BO
UV turn ON threshold
V
BO
UV turn OFF threshold
Undervoltage V
BO current
quiescent
V
BO
= 7 V
-
-
-
V
Bootstrap driver on resistance
BO
quiescent current
Logic inputs
Logic level Low threshold voltage
Logic level High threshold voltage
V
BO
= 15 V
IN = PWM = SD = 5 V;
IN = GND;
PWM = SD = 5 V;
-
-
Logic ‘1’ input bias current
Logic ‘0’ input bias current
IN = PWM = SD = 15 V
IN = PWM = SD = GND
Logic Inputs pull-down resistor IN = PWM = SD = 15 V
Input offset voltage
Input bias current
Comparator
V
CP-
= 0.5 V
V
CP+
= 1 V, V
CP-
= 1 V
Min. Typ. Max Unit
1.2
1.5
1.8
V
9 9.5
10 V
7.6
8 8.4
V
110 150 μA
600 1000 μA
0.8
1.0
1.2
V
8.2
9
7.3
8
9.8
8.7
V
V
40 100 μA
-
140 220 μA
120 Ω
0.8
1.1
V
1.9
2.3
V
10 40 100 μA
1 μA
0.18 0.37
1.5
MΩ
-16
-
+16 mV
1 µA
DS12543 - Rev 1 page 7/26
DS12543 - Rev 1
PWD5F60
Driver
Symbol t d_comp
SR
I
I
OD
ODlk
CPOUT
DT
MDT
DTx
Pin
CP+x to CPOUTx
CPOUTx
CPOUTx
Parameter
Comparator delay
Test condition
R pu
= 100 kΩ to 5 V
V
CP-
= 0.5 V;
Voltage step on CP+ = 0 to 3.3 V;
50% CP+ to 90% CPOUT
Min. Typ. Max Unit
90 130 ns
Open-drain low level sink current
Open-drain leakage current
Comparator output slew rate
CPOUT = 400 mV,
V
CP+
= 1 V, V
CP-
= 0.5 V
CPOUT = 15 V,
V
CP+
= 0 V, V
CP-
= 0.5 V
C
L
= 180 pF
R pu
= 5 kΩ to 5 V
CPOUT from 90% to 10%
Dead time
R
DT
= 0
Dead time setting range .
R
DT
= 37 kΩ, C
DT
= 100 nF
R
DT
= 136 kΩ, C
DT
= 100 nF
Matching dead time
R
DT
= 260 kΩ, C
DT
= 100 nF
R
DT
= 0
R
DT
= 37 kΩ, C
DT
= 100 nF
R
DT
= 136 kΩ, C
DT
= 100 nF
R
DT
= 260 kΩ, C
DT
= 100 nF
2.4
0.1 0.18 0.25
0.48 0.6
1.35 1.6
2.6
-
-
-
-
-
60
3.0
-
-
-
-
-
-
-
1
-
0.72
1.85
3.4
80
120
250
400 mA
µA
V/µs
µs ns
1. R
BD(on)
is tested in the following way: R
BD(on)
= [(VCC - V
BOOTa
) - (VCC - V
BOOTb when V
BOOT
= V
BOOTa
; Ib is BOOT pin current when V
BOOT
= V
BOOTb
.
)] / [Ia - Ib], where: Ia is BOOT pin current
2. The comparator is disabled when VCC is in UVLO condition.
3. Tested at wafer level before packaging
4. MDT = | DTLH – DTHL |.
page 8/26
4.2
PWD5F60
Power MOSFET
2.5
2.0
1.5
1.0
0.5
0
0
Figure 4. Typical dead time vs. R
DT
resistor value
3.5
Formula for approximate R
DT
calculation (typ.):
R
DT
[kΩ] = 92.2 x DT[µs] - 16.6
3.0
50 100 150
R
DT
(kΩ)
200 250 300
Power MOSFET
VCCx = 15 V; T
J
= 25 °C, unless otherwise specified.
Table 6. Power MOSFET electrical characteristics
Symbol
V
V
R
I
(BR)DS
GS(th)
DS(on)
I
DSS
E
V
AS
AS
SD
Parameter Test condition
Drain-source breakdown voltage
Zero gate voltage drain current
MOSFET on/off states
I
D
= 1 mA
V
DS
= 600 V
SD = SENSE = GND
Gate threshold voltage
Static drain-source on-resistance
Diode forward on voltage
V
DS
= V
GS
, I
D
I
D
= 1.75 A;
V
GS
= 10 V;
MOSFET Avalanche
Avalanche current, repetitive or not repetitive
Single pulse avalanche energy pulse width limited by T
J
Starting T
J
= 25 °C,
I
D
= I
AS
, V
DD
= 50 V
Source-Drain diode
SD = SENSE = GND
I
SD
= 3.5 A;
1. Tested at the wafer level before packaging.
Min Typ Max Unit
600
-
3
-
-
4
-
1
5
V
µA
V
1.38
1.75
Ω
-
-
-
1 A
132 mJ
1.6
V
DS12543 - Rev 1 page 9/26
5
PWD5F60
Device characterization values
Device characterization values
,
and the electrical characteristics curves (from
) represent typical values based on characterization and simulation results and are not subject to production tests.
t rr
Q rr
I
RRM t rr
Q rr
I
RRM
Symbol
Q g
Table 7. Power MOSFET characterization values
Parameter
Total gate charge
Diode reverse recovery time
Diode reverse recovery charge
Diode reverse recovery current
Diode reverse recovery time
Diode reverse recovery charge
Diode reverse recovery current
Test condition
MOSFET Dynamic
V
GS
= 10 V, T
J
= 25 °C
V
DS
= 480 V, I
D
= 3.5 A
Source-Drain diode
I
SD
= 3.5 A, T
J
= 25 °C di/dt = 100 A/µs,
V
DS
= 60 V
I
SD
= 3.5 A, T
J
= 150 °C di/dt = 100 A/µs,
V
DS
= 60 V
Min Typ Max
-
-
-
-
-
-
5.3
58
109
4
109
309
5
-
-
-
-
-
-
-
Unit nC ns
µC
A ns
µC
A
Table 8. Inductive load switching characteristics
Symbol Parameter t
(on)
Turn-on time t
C(on)
t
C(off)
Crossover time (on) t
(off)
Turn-off time
Crossover time (off) t
SD
E on
E off
Shutdown to high/low-side propagation delay
Turn-on switching losses
Turn-off switching losses
Test condition
VS = 300 V,
VCC = V
BO
= 15 V,
I
D
= 1.75 A
Min
-
-
-
-
-
-
-
Typ
450
67
171
25
165
51
3
1. t
(on)
and t
(off)
include the propagation delay time of the internal driver
2. t
C(on)
and t
C(off)
are the switching times of MOSFET itself under the internally given gate driving conditions
Max
-
-
-
-
-
-
-
Unit ns ns ns ns ns
µJ
µJ
DS12543 - Rev 1 page 10/26
Figure 5. Switching time definition
PWD5F60
Device characterization values
Figure 6. Normalized gate threshold voltage vs temperature
V
GS(th)
(norm.)
1.1
I
D
= 250 µA
1.0
0.9
0.8
0.7
0.6
-75 -25 25 75 125 T j
(°C)
Figure 7. Normalized drain-source breakdown voltage vs.
temperature
V
(BR)DSS
(norm.)
1.08
I
D
= 1 mA
1.04
1.00
0.96
0.92
0.88
-75 -25 25 75 125 T j
(°C)
DS12543 - Rev 1 page 11/26
PWD5F60
Device characterization values
Figure 8. Static drain-source on-resistance
R
DS(on)
(Ω)
1.5
V
GS
=10 V
1.46
1.42
1.38
1.34
1.3
1.26
0.5
1.0
1.5
2.0
2.5
3.0
3.5
I
D
(A)
2
1
0
0
I
D
(A)
6
Figure 10. Transfer characteristics
V
DS
= 20 V
5
4
3
2 4 6 8 V
GS
(V)
Figure 12. Static source-drain diode forward characteristics
V
SD
(V)
1.0
T j
= -50 °C
0.9
0.8
T j
= 25 °C
0.7
T j
= 150 °C
0.6
0.5
0.5
1.0
1.5
2.0
2.5
3.0
3.5
I
SD
(A)
Figure 9. Normalized on-resistance vs temperature
R
DS(on)
(norm.)
2.2
V
GS
= 10 V
1.8
1.4
1.0
0.6
0.2
-75 -25 25 75 125 T j
(°C)
2
1
0
0
I
D
(A)
6
5
4
3
Figure 11. Output characteristics
V
GS
=8, 9, 10 V
V
GS
=7 V
V
GS
=6 V
4 8 12
V
GS
=5 V
16 V
DS
(V)
Figure 13. Gate charge vs. gate-source voltage
V
GS
(V)
20
V
DS
V
DD
= 480 V
I
D
= 3.5 A
V
DS
(V)
500
16 400
Q g
12
8
Q gs
Q gd
300
200
4
0
0 2 4 6 8
100
Q
0 g
(nC)
DS12543 - Rev 1 page 12/26
Figure 14. MOSFET capicatance variations
C
(pF)
10 3
C
ISS
10 2
10 1 f = 1 MHz
10 0
10 -1 10 0 10 1 10 2
C
OSS
C
RSS
V
DS
(V)
PWD5F60
Device characterization values
Figure 15. MOSFET output capacitance stored energy
E
OSS
(µJ)
1.6
1.2
0.8
0.4
0
0 100 200 300 400 500 600 V
DS
(V)
DS12543 - Rev 1 page 13/26
PWD5F60
Functional description
6
Functional description
6.1
6.2
Logic inputs
The PWD5F60 full bridge features two identical half-bridge sections. Each section has three logic inputs to control the internal high-side and low-side MOSFETs.
Table 9. Truth table
SD
0
1
1
1
1
0
0
1
1
IN
X
Inputs
PWM
X
0
1
0
1
HS
OFF
OFF
OFF
OFF
ON
Outputs
LS
OFF
ON
ON
ON
OFF
The logic inputs have internal pull-down resistors. The purpose of these resistors is to set a defined logic level if, for example, there is an interruption on the logic lines or the controller outputs are in tri-state conditions.
Bootstrap structure
Bootstrap circuitry is typically used to supply the high-voltage section. This function is normally accomplished with a high-voltage fast recovery diode, as shown in
In the PWD5F60, a patented integrated structure replaces the external diode. The structure consists of a series of low-voltage diodes and a high-voltage DMOS, driven synchronously by the low-side driver (LVG), as shown in
(side b). An internal bootstrap provides the DMOS driving voltage. The integrated diode structure is
actively turned on and guarantees best performance only when the low-side driver is on.
In applications where the control strategy requires recharging the bootstrap capacitor even when the low-side driver is off, the use of an external bootstrap diode in parallel to the integrated structure is possible.
Figure 16. Bootstrap structure
D
BOOT
VCC BOOT
VS
VCC
BOOT
VS
HVG HVG
C
BOOT
C
BOOT
OUT
OUT
TO LOAD TO LOAD
LVG LVG a b
DS12543 - Rev 1 page 14/26
6.3
6.4
PWD5F60
Supply pins and UVLO function
Supply pins and UVLO function
The VCCx supply pin supplies current to the low-side section of the gate driver and to the integrated bootstrap diode used to charge the bootstrap capacitor. During output commutations, the average current used to provide gate charge to the high-side and low-side MOSFETs flow through these pins.
The VCC1 and VCC2 pins separately supply power to the two drivers, even if they are usually connected together at the power supply in final applications.
The PWD5F60 VCCx supply voltage is continuously monitored by undervoltage lockout (UVLO) circuits that turn the high-side and low-side MOSFETs off when the supply voltage falls below the VCC
_thOFF
threshold. The VCCx
UVLO circuitry turns on the high-side or low-side MOSFET according to the input status as soon as the supply voltage rises above the VCC
_thON
voltage. VCC
_hys
hysteresis is provided for noise rejection purposes.
Two separate UVLO circuits monitor VCC1 and VCC2 so that when a UVLO occurs on a single rail, only the corresponding half bridge MOSFETs are turned off.
The PWD5F60 V
BO
supply voltages are also continuously monitored by two dedicated V
BO
UVLO circuits that turn the corresponding high-side MOSFET off when the supply voltage falls below the V
BO_thOFF
threshold. The
UVLO circuitry allows turning the high-side MOSFET on again, according to input edges, as soon as the V
BO supply voltage rises above the V
BO_thON
voltage. A V
BO_hys
hysteresis is provided for noise rejection purposes.
Dead time
The PWD5F60 automatically inserts a DT dead time on each half bridge. This avoids shoot-through as a
MOSFET gate discharges completely before charging starts on the other MOSFET gate.
The DT value is set by the resistor placed between the DTx pin and GNDx, as shown in Figure 4.
.
The minimum dead time value set with a 0 Ω resistor is normally sufficient to avoid shoot-through between high side and low side.
Some applications, like those operating with soft turn-on commutations at low current seeking maximum efficiency, might benefit from a longer dead time. The PWD5F60 lets you set the dead time for each half bridge for maximum flexibility.
DS12543 - Rev 1 page 15/26
7
PWD5F60
Typical application diagrams
Typical application diagrams
Cbulk
Cboot1
Figure 17. Generic application
HVbus
LOAD
Cs1 Cs2 Cboot2 from CONTROLLER
VCC
R DT
VCC1
GND1
HS
IN1
PWM1
SD1
GATE DRIVER
LS
DT1
BOOT1 OUTB1 to CONTROLLER
CPOUT1
CP-1 CP+1 SENSE1
VS OUT1 OUT2 VS OUTB2 BOOT2
VCC2
GND2
HS
GATE DRIVER
IN2
PWM2
SD2
LS
DT2
VCC
R DT from CONTROLLER
SENSE2
CP+2 CP-2
CPOUT2 to CONTROLLER
Rsense Rsense
Figure 18. Current mode motor control
HVbus
Cbulk M
Cboot1 Cs1 Cs2 Cboot2
Hall effect sensor
Shutdown
DIR
PWM
SD
12V
R DT
12V
VCC1
GND1
HS
IN1
PWM1
SD1
GATE DRIVER
LS
DT1
BOOT1 OUTB1
DIR CPOUT1
CP-1
2.5V
CP+1
DIR
SENSE1
VS OUT1 OUT2 VS OUTB2 BOOT2
VCC2
GND2
HS
GATE DRIVER
IN2
PWM2
SD2
LS
DT2
12V
R DT
DIR
12V
PWM
SD
SENSE2
CP+2 CP-2
CPOUT2
C Toff
Rsense Rsense
Speed control voltage reference
DS12543 - Rev 1 page 16/26
8
8.1
PWD5F60
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
. ECOPACK ® is an ST trademark.
VFQFPN 15 x 7 x 1 mm package information
The package outline CAD file is available upon request.
Figure 19. VFQFPN 15 x 7 x 1 mm package dimensions – drawing top and side view
D
DS12543 - Rev 1 page 17/26
DS12543 - Rev 1
PWD5F60
VFQFPN 15 x 7 x 1 mm package information
D1 2X
20
19
22
21
18
17
16
15
Figure 20. VFQFPN 15 x 7 x 1 mm package dimensions – drawing bottom view
D2 2X
D4 2X
23 24 25 26 27 28 29 30 31 32 33 34
D3 2X
35 36 37
14
D11
13
D9 6X
12
D7 2X
D10
11 10 9
45
46
43
44
38
39
40
41
42 b1 b
8 7 6
D8 2X
5
D6 2x
4 3 2 1
D5 2x
L 25x page 18/26
4
PWD5F60
VFQFPN 15 x 7 x 1 mm package information
Figure 21. VFQFPN 15 x 7 x 1 mm package dimensions – exposed pads details
32 33 34
28 29 30 31
47
23
(116°)
27
DS12543 - Rev 1
Symbol b1
D
E
D1
A
A1
A3 b
Table 10. VFQFPN 15 x 7 x 1 mm package mechanical data
Min.
0.80
0.00
Dimensions (mm)
Typ.
0.85
0.20
0.14
14.90
6.90
0.20
0.30
0.24
15.00
7.00
0.865
Max.
0.90
0.05
0.40
0.34
15.10
7.10
page 19/26
PWD5F60
VFQFPN 15 x 7 x 1 mm package information
Note:
Symbol
L e
E5
E6
R1
R2
E2
E3
E4
D11
D12
D13
D14
E1
R3 aaa bbb ccc ddd eee
D6
D7
D8
D9
D10
D2
D3
D4
D5
Min.
1.89
1.70
0.50
2.17
0.70
0.85
0.20
0.90
3.13
0.505
2.75
3.70
0.40
Dimensions (mm)
Typ.
1.455
3.23
0.605
2.85
3.80
0.50
0.65
0.33
0.20
2.985
4.01
2.85
0.345
1.00
0.15
0.10
0.10
0.10
0.05
0.08
1.99
5.10
1.86
1.945
0.60
8.30
2.27
0.80
0.95
•
•
•
•
•
•
•
VFQFPN stands for Thermally Enhanced Very thin Fine pitch Quad Flat Packages No lead.
Dimensioning and tolerances comply with ASME Y14.5-2009.
All dimensions are in millimetres.
A variable pitch is applied on leads. Please refer to
for lead position details.
The leads size is comprehensive of the thickness of the leads finishing material.
Dimensions do not include mold protrusion, not to exceed 0.15 mm.
Package outline does not include eventual metal burr dimensions.
0.40
1.10
3.33
0.705
2.95
3.90
0.60
Max.
2.09
1.90
0.70
2.37
0.90
1.05
DS12543 - Rev 1 page 20/26
PWD5F60
Ordering information
9
Ordering information
Order code
PWD5F60
PWD5F60TR
Table 11. Device summary
Package
VFQFPN 15 x 7 x 1 mm
VFQFPN 15 x 7 x 1 mm
Packaging
Tray
Tape and Reel
DS12543 - Rev 1 page 21/26
Revision history
Date
03-Jul-2018
Table 12. Document revision history
Version
1
Changes
Initial release.
PWD5F60
DS12543 - Rev 1 page 22/26
PWD5F60
Contents
Contents
DS12543 - Rev 1 page 23/26
PWD5F60
List of figures
List of figures
Figure 4. Typical dead time vs. R
DS12543 - Rev 1 page 24/26
PWD5F60
List of tables
List of tables
DS12543 - Rev 1 page 25/26
PWD5F60
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2018 STMicroelectronics – All rights reserved
DS12543 - Rev 1 page 26/26
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