STMicroelectronics STELPD01 Datasheet
Advertisement
Advertisement
DFN10L (3x3 mm)
Maturity status link
STELPD01
STELPD01
Datasheet
Electronic load switch for power line
Features
• Wide input voltage range: 4 V to 18 V
• 17.5 V typical output overvoltage clamp
• Absolute maximum voltage of 23.5 V
• 5 A maximum continuous current
• Adjustable current limit with circuit breaker functionality
• Thermal protection
• Input undervoltage lockout
• Low inrush current during startup
• Integrated 40 mΩ Power FET
• EN/Fault pin
• Adjustable slew rate for output voltage
• Gate control pin for reverse current blocking FET
• Latch or auto-retry
• Available in DFN10L (3x3 mm) package
Applications
• Hot-Swap, Hot-Plug protection
• Industrial Systems
• VBUS management for Type-C and USB PD applications
Description
The STELPD01 is an integrated electronic power switch for power rail protection applications.
It is able to precisely detect and react to overcurrent and overvoltage conditions.
When an overload condition occurs, the device goes into an open state, disconnecting the load from the power supply. An external power MOSFET can be driven to manage the power loss protection in case of fault condition.
In case of overvoltage on the input, the device regulates the output to a preset 17.5 V value.
Undervoltage lockout prevents the load from malfunction, keeping the device off if the rail voltage is too low.
The STELPD01 features an adjustable turn-on slew-rate, which is useful to keep the in-rush current under control during startup and hot-swap operations.
DS13254 - Rev 1 - January 2022
For further information contact your local STMicroelectronics sales office.
www.st.com
1
Diagram
Figure 1. Block diagram
V
G
V
IN dV/dt dV/dt control
EN/Fault
V
IN
UVLO
ENABLE
Logic
GND
CONTROL
LOGIC
CHARGE
PUMP
GATE
Driver
CURRENT
CONTROL
VOLTAGE
CONTROL
Thermal
Protection
Exp V
OUT
I
LIM
STELPD01
Diagram
DS13254 - Rev 1 page 2/27
2
STELPD01
Pin configuration
Pin configuration
Figure 2. Pin connection (top view)
V
IN
V
IN
V
OUT
V
OUT
1
2
3
4
NC 5
Exp
10
9
8
V
G
I
LIM
EN/Fault
7
6
dV/dt
GND
Table 1. Pin description
Pin n°
1-2
3-4
5
6
7
8
9
10
Symbol
I
V
V
V
IN
OUT
NC
GND dV/dt
EN/Fault
LIM
G
Exp
Positive input voltage.
Function
Connected to the source of the internal power MOSFET.
Not connected.
Ground.
Soft-start adjustment pin. The internal dV/dt circuit controls the slew rate of the output voltage at turn-on. The internal capacitor allows a fixed ramp-up time but an external capacitor can be added to this pin to increase the ramp time. If an additional capacitor is not required, this pin should be left open.
The EN/Fault pin is a tri-state, bi-directional interface.
During normal operation the pin can be left floating, it is internally pulled up to 5 V. It can be used to disable the output of the device by pulling it to ground using an open drain or open collector device.
,
Section 6.6 and Section 6.7 for other specific
functions of this pin according to the device versions.
An R
LIM
resistor between this pin and the V threshold.
OUT
pin sets the overload current limit
External gate driver pin. An external power MOSFET can be connected to implement the reverse current protection.
The device’s package uses the center pad as a thermal conduit. This pad should be connected to an adequate spread of copper. GND connection is suggested.
1. Important: missing or shorted R
LIM
causes current limit circuit malfunction and may lead to device damage.
DS13254 - Rev 1 page 3/27
3
STELPD01
Application circuits
Application circuits
V
CC
C
IN
C dV/dt
Figure 3. Typical application circuit
V
IN
V
OUT
STELPD01
I
LIM dV/dt
EN/Fault
GND Exp
V
G
R
LIM
C
OUT
V
OUT
LOAD
V
CC
Figure 4. Typical application circuit with reverse current protection
M
1
C
IN
V
IN
STELPD01
V
OUT
I
LIM
R
LIM
C
OUT
C
LOAD
LOAD
C dV/dt dV/dt
EN/Fault
GND Exp
V
G
Symbol
C
IN
C dV/dt
R
LIM
C
OUT
Value
1 µF
560 pF
51 Ω
10 µF
Table 2. Typical application components
Description
Input capacitor
Soft-start capacitor
Current limitation resistor
Note
This value should be increased depending on input inductance and load current.
This value depends on the desired soft-start time.
This value depends on the desired current limit threshold.
Output capacitor
DS13254 - Rev 1 page 4/27
4
Note:
STELPD01
Maximum ratings
Maximum ratings
Table 3. Absolute maximum ratings
Symbol
V
IN
V
OUT
I
LIM
EN/Fault dV/dt
V
G
T
J-OP
T
J-MAX
T
STG
T
LEAD
Output voltage
EN/Fault pin voltage dV/dt pin voltage
Parameter
Power supply input voltage
Current limit resistor pin voltage
External gate driver pin voltage
Operating junction temperature range
Maximum junction temperature
Storage temperature range
Lead temperature (soldering) 10 sec
Value
-0.3 to 23.5
-0.3 to V
IN
+ 0.3
-0.3 to 23.5
-0.3 to 7
-0.3 to 7
-0.3 to 23.5
-40 to 125
125
-55 to 150
260
Unit
V
V
°C
°C
°C
°C
1. The thermal limit is set above the maximum thermal rating. It is not recommended to operate the device at temperatures greater than the maximum ratings for extended periods.
V
V
V
V
Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All values are referred to GND.
Table 4. Thermal data
Symbol
R thJA
R thJC
1. Based on JESD51-7, 4-layer PCB.
Parameter
Thermal resistance junction-ambient
Thermal resistance junction-case
Symbol
ESD
Table 5. ESD performance
Parameter
ESD protection voltage
Test conditions
HBM
CDM
Value
53
18
Value
2
500
Unit
°C/W
°C/W
Unit kV
V
Table 6. Recommended operating condition
Symbol
V
IN
I
D
C
IN
C
OUT
Parameter
Operating power supply input voltage
Maximum continuous current T
A
Minimum input capacitor
Minimum output capacitor
Value
4 to 16.8
5
1
1
Unit
V
A
µF
µF
1. The maximum allowable power dissipation is a function of the maximum junction temperature T
J(MAX) ambient thermal resistance θ
JA
, and the ambient temperature T
A
and can be estimated by: P
D(MAX)
, the junction-to-
= (T
J(MAX)
Exceeding the maximum allowable power dissipation produces overheating that may cause thermal shutdown.
-T
A
) / θ
JA
.
DS13254 - Rev 1 page 5/27
5
DS13254 - Rev 1
STELPD01
Electrical characteristics
Electrical characteristics
V
IN
= 5 V, V
EN/Fault
= 5 V, C
IN
= 10 µF, C
OUT
= 10 µF, C dV/dt
= floating, R
LIM
= 22 Ω; T
J
= 25 °C; unless otherwise specified.
Table 7. Electrical characteristics
Symbol Parameter Test conditions
Under/Overvoltage protection
V
V
CLAMP
UVLO
Clamping voltage
V
IN
undervoltage lockout
I
OUT
= 10 mA
Turn-on, V
IN
rising
Hysteresis
Power MOSFET
T
R
DELAY
V
DSon
OFF
Delay time
Off-state output voltage
Enabling of chip to soft-start beginning
(10% of V
OUT
), No C dV/dt
T
J
= 25 °C, I
OUT
= 500 mA
T
J
= 85 °C
V
IN
= 15 V, T
J
= 25 °C, I
OUT
= 500 mA
V
IN
= 15 V, T
J
V
IN
= 18 V, R
L
= infinite, EN/Fault connected to ground
Current limit
I
LIM
Overcurrent limit threshold
R
LIM
= 22 Ω
R
LIM
= 51 Ω dV/dt circuit dV/dt Output voltage ramp time
Blocking FET gate driver
V
R
I
FET
FETmax
FETdisch
T
PLP
From 10% to 90% of V
OUT
, No CdV/dt
External FET charging current
Device on
External FET clamp voltage V
IN
= 9 V, V
G
-V
OUT
External FET discharging current
V
EN/Fault
= 0 V, V
G
= V
IN
PLP intervention time
From EN/Fault = 0 V or V
IN
< V
UVLO
to
V
G
< 1 V
EN/Fault
V
V
IL
I(INT)
V
IH
I(MAX)
I
V
I
IL
IH
Low level input voltage threshold
Intermediate level input voltage
High level input voltage threshold
Output disabled
Thermal fault, output disabled
High state maximum voltage
V
IN
= 5 V
V
IN
= 15 V
Low level input current (sink) V
EN/Fault
= 0 V
High level leakage current for external switch
V
EN/Fault
= 5 V
Min.
16.8
2.85
750
2.55
Typ.
17.5
2.9
150
5.15
3
500
30
4.6
7.5
1
165
42
50
40
48
1
825
4.9
4.95
-100
1
Max.
18.2
2.95
52
50
3
0.4
900
-140
Unit
V mV
V
V
µA
µA
V
V mV
µs mΩ mV
A
µs
µA
V mA
µs page 6/27
STELPD01
Electrical characteristics
Symbol
Thermal protection
Parameter
T
SHDN
T
SHDN_HYS
Hysteresis
Current consumption
Test conditions Min.
Typ.
165
20
Max.
I
BIAS
Bias current, device operational
Bias current, fault mode
Bias current, off mode
V
IN
= 5 V
V
IN
= 15 V
V
IN
= 5 V
V
IN
= 15 V
V
IN
= 5 V, V
EN/Fault
= 0 V
V
IN
= 15 V, V
EN/Fault
= 0 V
300
350
115
135
200
225
1. Pulsed test.
2. Values across temperature range are guaranteed by design/correlation and tested in production only at ambient temperature.
3. Guaranteed by design, but not tested in production.
Unit
°C
°C
µA
µA
µA
DS13254 - Rev 1 page 7/27
6
6.1
STELPD01
Functional description
Functional description
Turn-on and soft start-up feature
When the input voltage is applied and it reaches V
UVLO
(undervoltage lockout threshold) value, the EN/Fault pin goes up to the high state (if left floating) and the internal control circuitry is enabled to perform the output start-up ramp. See the figure below.
Figure 5. Typical startup sequence for STELPD01 and STELPD01A
DS13254 - Rev 1
The start-up procedure starts with an initial delay time of typically 165 µs , then the output voltage is supplied with a slope defined by the internal dV/dt circuitry. If no additional capacitor is connected to dV/dt pin, the ramp-up time
(V
OUT
from 10% to 90%) is around 500 µs with V
IN
= 5 V.
The inrush current profile can be controlled through a dedicated soft-start circuit. Connecting a capacitor between the C dV/dt pin and GND allows the modification of the output voltage ramp-up time. Given the desired time interval
Δt during which the output voltage goes from 10% to 90% of V
OUT
, the capacitance to be added on the C dV/dt
pin can be calculated using the following theoretical formula.
Δt ms = 0.0024 × VIN V × CdV/dt pF + 0.1 × VIN V (1) page 8/27
Note:
6.2
6.3
6.4
6.5
STELPD01
Maximum load at startup
Figure 6. Delay time and V
OUT
ramp-up time
6
4
2
0
12
10
8 delay time ramp -up time
En/Fault
VOUT
Time
C dV/dt
[pF]
Rise time [ms]
0
0.5
Table 8. Rise time vs. C dV/dt
, V
IN
= 5 V
22
0.76
33
0.89
47
1.06
100
1.7
180
2.66
270
3.74
470
6.14
1000
12.5
Above table shows typical rise times obtained with available capacitor values. Values with C dv/dt
≠ 0 are guaranteed by design/correlation and not tested in production.
Maximum load at startup
Depending on supply voltage, load and output capacitance, it is possible that during startup the power dissipation reaches the maximum power protection and the output is shut down before the startup is completed. Increasing soft-start time, the inrush current is reduced and overtemperature fault is avoided.
Adjustable soft-start time is very useful in those applications where a single power supply serves several loads connected to the same rail with a big equivalent capacitive load. Therefore, it is important to determine the right start-up time and in-rush current to limit the dynamic power stresses and avoid thermal shutdown during startup.
Normal operating condition
The STELPD01 behaves like a power switch, buffering the circuitry on its output with the same voltage shown at its input, except for a small voltage fall due to the N-channel MOSFET R
DSon
.
Output voltage clamp
This internal protection circuit clamps the output voltage to a maximum safe value, typically 17.5 V, if the input voltage exceeds the V
CLAMP
threshold. In this condition, the device regulates the output voltage, therefore power dissipation increases and according to load current, the thermal shutdown can occur.
Current limiting
During operation, if the load current reaches the I
LIM
overload threshold, an overload is detected.
The current limiting circuit opens the power MOSFET disconnecting the load.
Typical reaction time of overcurrent control loop is 1.5 µs. This time considers the delay between the instant when output current reaches I
LIM
threshold and the activation of current control loop that acts on the gate of integrated
FET to open the power path.
On the latched versions (STELPD01), the EN/Fault pin of the device is automatically set to the intermediate voltage V
I(INT)
, during V out
falling edge, in order to signal the overload event to the system controller.
The device can be reset from this condition either by cycling the supply voltage or by pulling down the EN pin below the V
IL
threshold and then releasing it.
DS13254 - Rev 1 page 9/27
Note:
Note:
6.6
6.7
STELPD01
Thermal shutdown function
On the auto-retry version (STELPD01A), the EN/Fault pin is pulled down and the device attempts to turn on output channel with soft-start ramp after a delay time of 100 µs.
The R
LIM
value for achieving the requested current limitation can be estimated by using the following table together with the graph in
R
LIM
[Ω]
I
LIM
[A]
15
6.45
22
5.15
Table 9. I
LIM
vs. R
LIM
36
3.9
39
3.55
51
3
75
2.4
120
2.1
220
1.55
300
1.4
Missing or shorted R
LIM
causes current limit circuit malfunction and may lead to device damage.
R
LIM
value higher than 300 Ω can be used but as shown in
the I
LIM
vs. R
LIM
relationships is flat.
Thermal shutdown function
If the device temperature exceeds the thermal shutdown threshold (T
SHDN
), typically 165 °C, the power MOSFET is turned off and the load is disconnected.
On the latched version (STELPD01), the EN/Fault pin of the device is automatically set to the intermediate voltage V
I(INT)
, in order to signal the overtemperature event to the system controller.
The device can be reset from this condition either by cycling the supply voltage or by pulling down the EN pin below the V
IL
threshold and then releasing it.
On the auto-retry version (STELPD01A), the EN/Fault pin is set low, and the auto-retry circuit attempts to restart the device with soft-start ramp once the die temperature is reduced to 145 °C typ. (165 °C minus the hysteresis value, 20 °C typ.).
EN/Fault pin
The EN/Fault pin has the dual function of controlling the output of the device and providing information about the device status to the application.
When it is used as a standard Enable pin, it can be connected to an external open-drain or open-collector device.
In this case, when it is pulled at low logic level, the device turns the output off, when it is left floating the device turns on the output, since it has internal pull-up circuitry.
In case of a fault, on the latched versions, this pin is set to the intermediate voltage V
I(INT)
, this signal can be provided to a monitor circuit, informing it that a fault event has occurred or it can be directly connected to the
EN/Fault pins of other devices of the same family on the same application in order to achieve a simultaneous enable/disable feature. In case of UVLO event (V
IN
= V
UVLO order to keep the device in off-state.
- V hyst
) an internal pull-down block is activated in
DS13254 - Rev 1 page 10/27
STELPD01
External gate driver function for reverse blocking
Figure 7. EN/Fault driver circuit
5 V
6.8
Fault signal
V
I(INT) ref
GND
Fault driver
UVLO
30 μA
Pull down block
GND
To the logic control block
STELPD01 ON/OFF Comparator
V
REF
EN/Fault
External gate driver function for reverse blocking
The STELPD01 provides a dedicated gate drive signal on the VG pin which can be used to control an external blocking MOSFET for reverse-current protection (RCP). See
.
When the internal control circuitry is enabled to perform output start-up ramp, the V gate
pin is pulled up by
External FET charging current I
FET the activation of external FET.
to the charge pump voltage referred to the V in
voltage in order to guarantee
If the input voltage reaches V clamp
threshold the V gate
voltage is also clamped to a safe value of V out
+ 5.5 V. See
Reverse current protection is activated in case V
IN
falls below the undervoltage lockout (UVLO), the enable (EN) voltage falls below the low-level threshold, or a fault event occurs.
For example, as V
CC
drops during input power removal, the device turn off internal FET and it sinks current from the gate of the external FET to quickly turn it off, therefore blocking any current flow from the load to the input side.
DS13254 - Rev 1 page 11/27
6.9
STELPD01
External capacitors and application guidelines
Figure 8. External gate driver circuit
V
UP
Pull up block
30 μA
V
G
Maximum clamp voltage
Pull down signal
GND
Pull down block
V
OUT
STELPD01
External capacitors and application guidelines
•
•
•
Input and output capacitors are mandatory to guarantee device control loop stability and reduce the transient effects of stray inductances which may be present on the input and output power paths. In fact, when the
STELPD01 interrupts the current flow, input inductance generates a positive voltage spike on the input, and output inductance generates a negative voltage spike on the output. To reduce the effects of such transients, a C
IN
capacitor of at least 1 μF must be connected between the input pin and GND, and located as close as possible to the device.
For the same reason, a C
OUT
capacitor of at least 1 μF must be connected at the output port.
When the device is powered by a power line made up of very long wires, where input inductance is higher than 1
μH, the input capacitor should be increased.
It is recommended to provide for additional protections and methods for addressing these transients, such as:
• Minimizing inductance of the input and output tracks
TVS diodes on the input to absorb inductive spikes
Schottky diode on the output to absorb negative spikes
Combination of ceramic and electrolytic capacitors on the input and output
DS13254 - Rev 1 page 12/27
7
5
4
3
2
1
0
0
7
6
5 V
12 V
50 100 150 200 250
R
LIM
[Ω]
300 350 400 450 500
STELPD01
Typical characteristics
Typical characteristics
V
IN
= 5 V, V
EN/Fault
= floating, R
LIM
= 51 Ω, C
IN
= 2.2 µF, C
OUT
= 10 μF, C dV/dt otherwise specified.
= 560 pF, T
A
= 25 °C, unless
Figure 9. I
LIM
vs. R
LIM
Figure 10. I
LIM
vs. R
LIM
(magnification)
7
6
5 V
12 V
5
4
3
2
1
0
10 15 20 25 30 35 40 45 50 55 60 65 70
R
LIM
[Ω]
75 80 85 90 95 100 105 110 115 120 125
Figure 11. Bias current vs. temperature (ON Mode)
600
550
500
450
400
350
300
250
200
150
100
50
-50 -25 0 25 50
Temperature [ºC]
75 100
V_IN=5V
V_IN=9V
V_IN=12V
V_IN=15V
125 150
Figure 12. Bias current vs. temperature (Fault Mode)
300
250
200
150
100
50
0
-50 -25 0
V_IN=5V
V_IN=9V
V_IN=12V
V_IN=15V
25 50
Temperature [ºC]
75 100 125 150
DS13254 - Rev 1 page 13/27
Figure 13. Bias current vs. temperature (OFF Mode)
400
350
300
250
200
150
100
50
0
-50 -25 0 25 50
Temperature [ºC]
75 100
V_IN=5V
V_IN=9V
V_IN=12V
V_IN=15V
125 150
Figure 15. I
LIM
vs. temperature
4.20
4.00
3.80
3.60
3.40
3.20
3.00
2.80
2.60
2.40
2.20
2.00
-50
R
LIM
= 51 Ω
-25 0 25 50
Temperature [ºC]
75 100
V_IN = 5 V
V_IN = 9 V
V_IN = 12 V
V_IN = 15 V
125 150
Figure 17. UVLO vs. temperature
3.40
V
IN
= 0 V to 5 V
3.20
3.00
2.80
2.60
2.40
-50 -25 0 25 50
Temperature [ºC]
75 100 125 150
STELPD01
Typical characteristics
Figure 14. R
DS_ON
vs. temperature
70
65
60
55
50
45
40
35
30
25
20
-50
I
OUT
= 500 mA
-25 0 100 25 50
Temperature [ºC]
75
V_IN = 5 V
V_IN = 9 V
V_IN = 12 V
V_IN = 15 V
125 150
Figure 16. Clamping voltage vs. temperature
20.0
19.5
19.0
18.5
18.0
17.5
17.0
16.5
16.0
15.5
15.0
-50
V
IN
= 20 V
-25 0 100 125 25 50
Temperature [ºC]
75 150
Figure 18. UVLO Hysteresis vs. temperature
0.25
0.20
0.15
0.10
0.05
-50 -25 0 25 50
Temperature [ ºC]
75 100 125 150
DS13254 - Rev 1 page 14/27
Figure 19. EN/Fault pin thresholds vs. temperature
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
-50 -25 0
ON
OFF
Fault
25 50
Temperature [ºC]
75 100 125 150
STELPD01
Typical characteristics
Figure 20. EN/Fault pull-up voltage vs. temperature
6.00
V
IN
= 5 V
5.50
5.00
4.50
4.00
3.50
-50 -25 0 25 50
Temperature [ºC]
75 100 125 150
Figure 21. EN/Fault pin current vs. temperature (EN/Fault to GND)
200.00
175.00
150.00
125.00
100.00
75.00
50.00
25.00
0.00
-50 -25 0 25 50
Temperature [ºC]
75 100 125 150
Figure 22. Soft-start time vs. temperature (no Cdv/dt)
1000
900
800
700
600
500
400
300
200
100
0
-50
V
IN
= 5 V
-25 0 100 125 150 25 50
Temperature [ºC]
75
Figure 23. External FET clamp voltage (V
FETmax
) vs. input voltage
3
2
1
0
0
6
5
4
5 20 25 10 15
Input Voltage [V]
Figure 24. Startup with no load
DS13254 - Rev 1 page 15/27
Figure 25. Startup with R
LOAD
= 5 Ω
STELPD01
Typical characteristics
Figure 26. Startup into voltage clamp
Figure 27. Voltage clamp during operation Figure 28. Start-up into output short-circuit
Figure 29. Startup into overload
Figure 30. Overcurrent protection during operation
(latched version)
DS13254 - Rev 1 page 16/27
Figure 31. Output short-circuit during operation (latched version)
STELPD01
Typical characteristics
Figure 32. Power loss protection through UVLO
Figure 33. Power loss protection through EN/Fault
DS13254 - Rev 1 page 17/27
8
8.1
STELPD01
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
DFN10L (3x3 mm) package information
Figure 34. DFN10L (3x3 mm) package outline
DS13254 - Rev 1 page 18/27
Dim.
b
D
D2
E
E2
E3
A
A1
A2
A3
E4 e
L ddd
STELPD01
DFN10L (3x3 mm) package information
Table 10. DFN10L (3x3 mm) mechanical data
Min.
0.80
0.55
mm
Typ.
0.90
0.02
0.65
0.20
0.25
3.00
0.18
2.85
2.20
2.85
1.40
0.230
0.365
3.00
0.30
0.50
0.40
0.30
3.15
2.70
3.15
1.75
Max.
1.00
0.05
0.80
0.50
0.08
Figure 35. DFN10L (3x3 mm) recommended footprint
DS13254 - Rev 1 page 19/27
8.2
STELPD01
DFN10 (3 x 3 mm) packing information
DFN10 (3 x 3 mm) packing information
Figure 36. DFN10 (3 x 3 mm) reel drawing outline
DS13254 - Rev 1 page 20/27
STELPD01
DFN10 (3 x 3 mm) packing information
Figure 37. DFN10 (3 x 3 mm) carrier tape
DS13254 - Rev 1
Figure 38. DFN10 (3 x 3 mm) device orientation in tape page 21/27
STELPD01
Ordering information
9
Ordering information
Table 11. Order codes
Order code Package Packaging
STELPD01PUR
STELPD01APUR
DFN10L-(3x3 mm) Tape and reel
1. Version under development. Contact ST sales offices.
Marking
EPD1
TBD
Response to thermal and overcurrent fault
Latch-off
Auto-retry
EN/Fault at startup
High (Automatic startup)
DS13254 - Rev 1 page 22/27
Revision history
Date
17-Jan-2022
Revision
1
Table 12. Document revision history
Changes
Initial release.
STELPD01
DS13254 - Rev 1 page 23/27
STELPD01
Contents
Contents
DS13254 - Rev 1 page 24/27
STELPD01
List of tables
List of tables
Table 8. Rise time vs. C dV/dt
DS13254 - Rev 1 page 25/27
STELPD01
List of figures
List of figures
Figure 23. External FET clamp voltage (V
) vs. input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DS13254 - Rev 1 page 26/27
STELPD01
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks . All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2022 STMicroelectronics – All rights reserved
DS13254 - Rev 1 page 27/27
Download
Public link updated
The public link to your chat has been updated. You may view and manage your chat links after registration here.
Document public link
Advertisement
