STMicroelectronics STEF12S Datasheet
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TSOT23-8L DFN10 (3x3 mm)
Maturity status link
STEF12S
STEF12S
Datasheet
Electronic fuse for 12 V line
Features
• 15 V typical output overvoltage clamp
• Absolute maximum voltage of 25 V
• Adjustable current limit
• Thermal protection
• Input undervoltage lockout
• Low inrush current during startup
• Integrated 40 mΩ Power FET
• En/fault pin
• Adjustable slew rate for output voltage
• Gate control pin for reverse current blocking FET (DFN10 package)
• TSOT23-8L and DFN10 (3x3 mm) packages
• Latch (STEF12S) or autoretry (STEF12SA) versions
Application
• Hard Disk and SSD drives
• Hard disk array
• Hot-swap board
• Hot-plug protection
Description
The STEF12S is an integrated electronic fuse optimized to monitor the 12 V DC power lines.
When connected in series to the main power rail, it is able to precisely detect and react to overcurrent and overvoltage conditions.
When an overload condition occurs, the device limits the output current to a safe value defined by the user. If the anomalous overload condition persists, the device goes into an open state, disconnecting the load from the power supply.
In case of overvoltage on the input, the device regulates the output to a preset safe value.
Undervoltage lockout prevents the load from malfunction, keeping the device off if the rail voltage is too low.
The STEF12S features the adjustable turn-on slew-rate, which is useful to keep the in-rush current under control during startup and hot-swap operations.
On the DFN10 package a dedicated pin provides a gate control for an external optional N-channel Power FET, used to implement the reverse current blocking in case of input voltage loss.
The STEF05S is a companion chip for the 5 V rails, useful to implement a complete power rail control in data-storage applications.
DS13002 - Rev 4 - October 2021
For further information contact your local STMicroelectronics sales office.
www.st.com
1
STEF12S
Diagram
Diagram
Figure 1. Block diagram
V
CC
V
G
EN/Fault
5 V
I
IL
20 µA
ENABLE UVLO
CHARGE
PUMP AND
GATE DRIVER dV/dt dV/ dt control
Voltage
Control
Thermal
Protection
CURRENT
LIMIT
V
OUT
I
LIM
Note: Gate driver pin V
G
is available on DFN10 version only.
GND
DS13002 - Rev 4 page 2/32
2
STEF12S
Pin configuration
Pin configuration
Figure 2. Pin connection (top view)
I
Lim
En/Fault dV/dt
GND
Vcc
Vcc
Source
Source
GND dV / dt
En /Fault
I
Lim
V
G
Vcc
Source
Source
Source
Source
Source
TSOT23-8L DFN10 3x3
Table 1. Pin description
TSOT23-8L
Pin #
DFN10
Symbol Function
1
2
3
4
5-6
-
7-8
4
3
2
1
6-10
5
Exposed pad
I
Lim
En/Fault dV/dt
GND
Source/V
V
G
V
CC
OUT
An R
Lim
resistor between this pin and the Source pin sets the overload and short-circuit current limit levels.
The En/Fault pin is a tri-state, bi-directional interface. During the normal operation, the pin must be left floating, or it can be used to disable the output of the device by pulling it to ground using an open drain or open collector device.
If a thermal fault occurs, the voltage on this pin goes into an intermediate state to signal a monitor circuit that the device is in thermal shutdown. It can be connected to another device of this family to cause a simultaneous shutdown during thermal events.
The internal dV/dt circuit controls the slew rate of the output voltage at turn-on. The internal capacitor allows a ramp-up time of around 0.85 ms. An external capacitor can be added to this pin to increase the ramp time. If an additional capacitor is not required, this pin should be left open.
Ground connection.
Connected to the source of the internal power MOSFET and to the output terminal of the fuse.
Gate driver output for the optional external reverse-blocking power MOS.
Leave floating if not used.
Positive input voltage of the eFuse.
1. Important: missing or shorted R
Lim
causes current limit circuit malfunction and may lead to device damage.
DS13002 - Rev 4 page 3/32
3
STEF12S
Typical application
Typical application
V
IN
C
IN
C dv /dt
Figure 3. Typical application circuit
Vcc dV/dt
STEF12S
V
OUT
I
LIM
EN/Fault
GND
R
LIM
V
OUT
C
OUT
V
IN
C
IN
Figure 4. Application with external reverse current blocking MOSFET
M
1
C dv/dt
Vcc
V
OUT dV/dt
STEF12S
I
LIM
EN/Fault V
G
GND
R
LIM
C
OUT
V
OUT_R
DS13002 - Rev 4 page 4/32
STEF12S
Maximum ratings
4
Maximum ratings
Table 2. Absolute maximum ratings
Symbol
V
CC
V
OUT
/source
V
G
I
Lim
En/Fault dV/dt
T
J-OP
T
STG
T
LEAD
HBM
CDM
Positive power supply voltage
Output voltage
Gate driver pin voltage
Parameter
Current limit resistor pin voltage
En/Fault pin voltage dV/dt pin voltage
Operating junction temperature range
Storage temperature range
Lead temperature (soldering) 10 s
ESD protection - human body model
ESD protection - charged device model (TSOT23-8L package)
ESD protection - charged device model (DFN10-3x3 package)
Value
-0.3 to 25
-0.3 to V
CC
+ 0.3
-0.3 to V
OUT
+ 5
-0.3 to 25
-0.3 to 7
-0.3 to 7
-40 to 125
-65 to 150
1. The thermal limit is set above the maximum thermal ratings. It is not recommended to operate the device at temperatures greater than the maximum ratings for extended periods of time.
260
2
500
500
Note: Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All values are referred to GND.
V
V
V
V
°C
°C
°C kV
V
V
Unit
V
V
Table 3. Thermal data (TSOT23-8L)
Symbol
R thJA
R thJC
Parameter
Thermal resistance junction-ambient
Thermal resistance junction-case
1. Based on JESD51-7, 4-layer PCB.
Value
140
35
Table 4. Recommended operating condition
Symbol
V
CC
I
D
C
IN
C
OUT
R
Lim
Operating power supply voltage
Maximum continuous current T
Suggested input capacitor
Minimum output capacitor
Current limit resistor range
Parameter
A
= 25°C
Value
10 to 13.8
3.5
1
1
15.4 to 300
1. The maximum allowable power dissipation is a function of the maximum junction temperature T
J-OP
=125°C, the junction-to-ambient thermal resistance R thJA
, and the ambient temperature T
A
and can be estimated by:
P
D(MAX)
= (125 °C - T
A
) / R thJA
. Exceeding the maximum allowable power dissipation produces overheating that may cause thermal shutdown.
Unit
°C/W
°C/W
µF
µF
Ω
Unit
V
A
DS13002 - Rev 4 page 5/32
STEF12S
Electrical characteristics
5
Electrical characteristics
V
CC
= 12 V, V
En/Fault
= 5 V, C
I
= 10 µF, C
O
= 10 µF, T
J
= 25 °C (unless otherwise specified).
Table 5. Electrical characteristics
Symbol Parameter
Under/Overvoltage protection
V
Clamp
V
UVLO
Average output clamping voltage
Undervoltage lockout
V
Hyst
UVLO hysteresis
Power MOSFET
V
CC
= 17 V
Test conditions
Turn-on, voltage rising
R t dly
DSon
Delay time
On-resistance
Enabling of chip to soft start beginning
(10 % of V
OUT
), No C dv/dt
T
J
= 25 °C
T
J
V
CC
= 18 V, V
GS
= 0, R
L
= infinite V
OFF
Off-state output voltage
Current Limit
I
Short
I
Lim
I
Short
I
Lim
Short-circuit current limit
Overload current limit
Short-circuit current limit
Overload current limit
I
Short
I
Lim dv/dt circuit
Short-circuit current limit
Overload current limit
R
R
R
R
R
R
Lim
Lim
Lim
Lim
Lim
Lim
= 22 Ω, STEF12SGR
= 22 Ω, STEF12SGR
= 22 Ω, STEF12SPUR
= 22 Ω, STEF12SPUR
= 39 Ω, STEF12SGR
= 39 Ω, STEF12SGR dv/dt
En/Fault
V
IL
V
I(INT)
V
IH
V
I(MAX)
I
IL
Output voltage ramp time
Low level input voltage
Intermediate level input voltage
High level input voltage
High state maximum voltage
Low level input current (sink)
From 10% to 90% of V
Output disabled
OUT
, no Cdv/dt
Thermal fault, output disabled
Output enabled
V
En/Fault
= 0 V
I
I
High level leakage current for external switch
V
En/Fault
= 5 V
Maximum fan-out for fault signal
Total numbers of chips that can be connected to this pin for simultaneous shutdown
Current consumption
I
Bias
Bias current Thermal shutdown
Off mode, V
En/Fault
= 0 V
External MOSFET gate driver (DFN10 package only)
I
G
Sourcing current
Device operational
Device On
Min.
13.8
7.7
1.2
2.5
Typ.
15
8.5
0.8
0.85
1.3
4.9
-20
0.37
0.16
0.12
30
4.6
1.9
3.8
2.8
5.5
2.4
250
40
48
1
Max.
Unit
16.2
9.3
50
10
1.8
1.45
-50
1
3 mΩ mV
V
µA
V
V
V
µA
Units
V
V
V
µs
A
A
A
A
A
A ms mA
µA
DS13002 - Rev 4 page 6/32
Symbol Parameter
I
P
V
G
Pull-down current
Gate driver voltage
Thermal protection
T
SHDN
Thermal shutdown
Hysteresis
V
V
En/fault
G
- V
= 0 V
OUT
Test conditions
1. Pulsed test.
2. Guaranteed by design and correlation but not tested in production.
STEF12S
Electrical characteristics
Min.
Typ.
8
5
Max.
Unit mA
V
165
20
°C
DS13002 - Rev 4 page 7/32
6
6.1
6.2
6.3
STEF12S
Application information
Application information
Turn-on and soft startup feature
When the input voltage is applied, the En/Fault pin goes up to the high state and the internal control circuitry is enabled.
After an initial delay time of typically 250 µs, the output voltage is ramped up with a slope defined by the internal dv/dt circuitry. If no additional capacitor is connected to dV/dt pin, the ramp-up time (V
OUT
from 10% to 90%) is around 0.85 ms.
Connecting a capacitor between the C dv/dt
pin and GND allows the modification of the output voltage ramp-up time. Given the desired time interval Δt during which the output voltage goes from zero to its maximum value, the capacitance to be added on the C dv/dt
pin can be calculated using the following theoretical formula.
Δt ms = 0.85 + Cdv/dt pF × 0.021
Where C dv/dt
is expressed in farads and the time in seconds.
Figure 5. Delay time and V
OUT
ramp-up time
8
6
4
2
0
12
10
delay time ramp-up time
10%
90% En/Fault
Vout
Time
C dvdt
(pF)
Rise time
(ms)
0
0.85
22
1.3
33
Table 6. Rise time vs. C dvdt
47 100 180
1.56
1.9
3 4.7
270
6.6
470
11
1000
22
Maximum load at startup
Depending on supply voltage and load, it is possible that during startup the power dissipation is such that the maximum power protection is triggered and the output is shut down before the startup is complete. The EN/Fault
signal is set according to Figure 6. En/Fault driver circuit
. En/Fault pin behavior during thermal protection events.
In case of strong capacitive loads, the total start-up time may be longer than the programmed start-up time, since it is dependent also on the limitation current, the output load and the output capacitance value. In such a situation, the foldback current limit could activate, so that the startup is longer or interrupted by the intervention of thermal protection. To avoid this occurrence, a longer start-up time should be set by the appropriate selection of the C dv/dt capacitor.
Normal operating conditions
The STEF12S eFuse behaves like a mechanical fuse, supplying the circuitry on its output with the same voltage shown on its input, with a small voltage fall due to the internal N-channel MOSFET R
DS(on)
.
DS13002 - Rev 4 page 8/32
6.4
6.5
Note:
6.6
STEF12S
Output voltage clamp
Output voltage clamp
This internal protection circuit clamps the output voltage to a maximum safe value, typically 15 V, if the input voltage exceeds the V
CLAMP
threshold. In this condition, the device regulates the output voltage, therefore the power dissipation increases. Thermal shutdown can occur if the overvoltage persists.
Current limiting
During the operation, if the load current reaches the I
LIM
threshold, an overload is detected. The current limiting circuit reduces the conductivity of the power MOSFET, in order to clamp the output current at the I
SHORT value. The overload threshold and current limit can be customized by the limiting resistor R
Lim
Figure 3. Typical application circuit
.
, the device uses an internal N-channel sense FET with a fixed ratio, to monitor the output current and limit it at the level set by the user.
To achieve the requested current limitation, the R
Lim with the graph in
value can be selected by using the following table, together
- (STEF12SGR) and Figure 11. I
. Higher resistor values can be used, but due to the current limit trend shown in the before mentioned graphs, the minimum values of I
LIM
and I
SHORT
are asymptotically limited.
R
Lim
(Ω)
I
LIM
(A)
I
SHORT
(A)
15.4
8
5.1
22
5.5
2.8
Table 7. I
LIM
/ I
SHORT
vs. R
Lim
STEF12SGR
24.9
5.1
2.6
30
4.4
2.3
39
3.8
1.9
49.9
3.2
1.5
100
2.4
0.8
200
1.7
0.4
300
1.5
0.3
R
Lim
(Ω)
I
LIM
(A)
I
SHORT
(A)
15.4
5.9
3.2
22
4.6
2.4
Table 8. I
LIM
/ I
SHORT
vs. R
Lim
STEF12SPUR
24.9
4.4
2.2
30
3.8
1.9
39
3.2
1.7
49.9
2.8
1.5
100
2
0.8
200
1.5
0.4
300
1.3
0.3
Missing or shorted R
Lim
causes current limit circuit malfunction and may lead to the device damage.
Thermal shutdown
If the device temperature exceeds the thermal shutdown threshold (T
SHDN is turned off and the load disconnected.
), typically 165 °C, the power MOSFET
On the STEF12S latch version, the EN/Fault pin of the device is automatically set to an intermediate voltage
(typically 1.3 V), in order to signal the overtemperature event to the system controller.
The device can be reset from this condition either by cycling the supply voltage or by pulling down the EN pin below the V il
threshold and then releasing it.
On the autoretry version (STEF12SA), the EN/Fault pin is set to a low logic level and the autoretry circuit attempts to restart the device with soft-start once the die temperature is reduced to 145 °C typ. (165 °C minus the hysteresis value, 20 °C typ.).
DS13002 - Rev 4 page 9/32
6.7
STEF12S
En/Fault pin
En/Fault pin
The EN/Fault pin has the dual function of controlling the output of the device and providing information about the device status to the application. A simplified diagram of this circuit is depicted in
.
When it is used as a standard Enable pin, it can be connected to an external open drain or open-collector device.
In this case, when it is pulled to a low logic level, it turns the output of the eFuse off.
High and low logic levels are defined as V
IH
and V
IL
in
.
If this pin is left floating, since it has an internal pull-up circuitry, the eFuse is turned on.
Pull-up current is 20 µA clamped to 5 V (V
I(MAX)
).
On the STEF12S (latch version), in case of thermal fault, the pin is pulled to an intermediate state (V
I(INT)
) as shown in
thermal shutdown has occurred, or it can be directly connected to the EN/Fault pins of other eFuse devices on the same application in order to achieve a simultaneous enable/disable feature.
When a thermal fault occurs, the device can be reset either by cycling the supply voltage or by pulling down the
Enable pin below the V il
threshold and then releasing it.
On the STEF12SA autoretry version, once the thermal shutdown is triggered, the EN/Fault pin of the device is set to low state. It goes back to high level once the autoretry occurs.
Figure 6. En/Fault driver circuit
DS13002 - Rev 4 page 10/32
6.8
STEF12S
Reverse blocking function
Figure 7. En/Fault pin status
6
5
4
1
0
3
2
Device ON
Thermal fault
OFF/Reset
Latch
Autoretry time
Reverse blocking function
Many applications require reverse current blocking, to allow the completion of pending system activities (such as writing the data on SSD or parking the head in HDD) in case of power loss or during brownout. The STEF12S provides a dedicated gate drive signal on the V
G
pin, which can be used to control an external blocking MOSFET,
. As V
CC
drops during input power removal, the signal on V g
falls, and both the internal pass element and M1 MOSFET are turned off, therefore blocking any current flow from the load to the input of the eFuse. By appropriate selection of C
OUT
the required load current can be guaranteed to complete the power-down sequence.
Figure 8. External gate driver circuit (only on DFN10 version)
V
IN
Charge Pump
V
UP
Pull up block
30 μA
V
G
Maximum clamp voltage
Pull down signal
Pull down block
GND
V
OUT
STEF12S
DS13002 - Rev 4 page 11/32
6.9
STEF12S
Application suggestions and PCB layout guidelines
Application suggestions and PCB layout guidelines
Input and output capacitors are mandatory to guarantee the device control loop stability and reduce the transient effects of stray inductances, which may be present on the input and output power paths. In fact, when the
STEF12S interrupts the current flow, input inductance generates a positive voltage spike on the input, and output inductance generates a negative voltage spike on the output.
To reduce the effects of such transients, a C
IN
capacitor of at least 1 μF (including voltage and temperature derating) is recommended between the input pin and GND, and located as close as possible to the device.
For the same reason, a C
OUT connected to the output port.
capacitor of at least 1 μF (including voltage and temperature derating) must be
•
•
When the device is powered by a power line made up of very long wires, the input inductance is higher than few
μH, so the input capacitor should be increased in order to guarantee the proper operation of the device.
It is suggested to provide for additional protections and methods to address these transients, such as:
Minimizing inductance of the input and output tracks
TVS diodes on the input to absorb inductive spikes
•
•
Schottky diode on the output to absorb negative spikes. The negative AMR of V
OUT
pin is - 0.3 V (see
.), nevertheless, negative transient up to - 0.6 V with a maximum duration of 50 μs are tolerated by the device. Schottky diode must be selected to satisfy the above requirements.
Combination of ceramic and electrolytic capacitors on the input and output.
•
The PCB layout is critical for a stable and reliable operation. Refer to the typical PCB layout example shown in
and to the following guidelines:
• Defining the high current input and output copper traces as short as possible and adequately sized to sustain at least the overload current
Placing the R
Lim
resistor close to the ILim pin and connect the other terminal of the component to V
OUT
with the shortest possible trace. In fact, parasitic effects on the R
Lim accuracy.
connection trace can affect the current limit
•
•
Placing the C dv/dt
capacitor close to the dV/dt pin and connect the other terminal to GND with the shortest possible trace. Use low-leakage components for C dvdt
.
The TSOT23-8L package dissipates the thermal power mainly through the leads, so providing large enough copper areas around the PCB soldering pads is recommended.
Figure 9. PCB layout example
GND
V
CC
V
OUT
/Source
Top layer Bottom layer
DS13002 - Rev 4 page 12/32
STEF12S
Typical characteristics
7
Typical characteristics
V
CC
= 12 V, V specified.
En/Fault
= floating, R
Lim
= 22 Ω, C
OUT
= 10 μF, C dV/dt
= floating, T
A
= 25°C, unless otherwise
Figure 10. I
Lim
and I
Short
vs. R
Lim
- (STEF12SGR)
5
4
3
2
1
0
0
9
8
7
6
50 100 150
Rlim [ Ω]
200
Ilim
Ishort
250 300
Figure 11. I
Lim
and I
Short
vs. R
Lim
- (STEF12SPUR)
4
3
2
1
0
0
7
6
5
50 100 150
Rlim [ Ω]
200
Ilim
Ishort
250 300
Figure 12. Bias current vs. temperature
0.700
0.600
0.500
0.400
0.300
0.200
0.100
0.000
-50 -25 0
Device On
Device Off
25 50
Temperature [ºC]
75 100 125 150
Figure 13. Bias current vs. temperature (thermal shutdown)
0.500
0.450
0.400
0.350
0.300
0.250
0.200
0.150
0.100
0.050
0.000
-50 -25 0 25 50
Temperature [ºC]
75 100 125 150
DS13002 - Rev 4 page 13/32
Figure 14. R
DS_ON
vs. temperature
45
40
35
30
25
-50
60
55
50
70
65
I
OUT
= 500 mA
-25 0 25 50
Temperature [ºC]
75 100 125 150
Figure 16. I
Short
vs. temperature
2.4
2.2
2.0
1.8
1.6
3.0
2.8
2.6
1.4
1.2
1.0
-50 -25 0 25 50
Temperature [° C]
75 100 125 150
Figure 18. UVLO vs. temperature
10.00
9.50
9.00
8.50
8.00
7.50
7.00
-50 -25 0 25 50
Temperature [ºC]
75 100 125 150
STEF12S
Typical characteristics
Figure 15. I
LIM
vs. temperature
4.4
4.2
4.0
3.8
3.6
3.4
3.2
3.0
-50
R
LIM
= 39Ω
-25 0 25 50
Temperature [ºC]
75 100 125 150
Figure 17. Clamping voltage vs. temperature
18
17
16
15
14
13
12
-50 -25 0 25 50
Temperature [ºC]
75 100 125 150
Figure 19. UVLO hysteresis vs. temperature
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
-50 -25 0 25 50
Temperature [ºC]
75 100 125 150
DS13002 - Rev 4 page 14/32
Figure 20. En/Fault pin thresholds vs. temperature
3.50
3.00
2.50
2.00
1.50
1.00
-50 -25 0
ON
OFF
Thermal fault
25 50
Temperature [ºC]
75 100 125 150
STEF12S
Typical characteristics
Figure 21. En/Fault pull-up voltage vs. temperature
6.00
5.50
5.00
4.50
4.00
3.50
-50 -25 0 25 50
Temperature [ºC]
75 100 125 150
Figure 22. En/Fault pin current vs. temperature (En/Fault to GND)
26.00
24.00
22.00
20.00
18.00
16.00
14.00
12.00
10.00
-50
V
En/Fault
= 0 V
-25 0 25 50
Temperature [ºC]
75 100 125 150
Figure 23. Soft-start time vs. temperature (no C dvdt
)
2.00
From 10% to 90% of
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
-50 -25 0
V
OUT
, No C dv/dt
25 50
Temperature [ºC]
75 100 125 150
Figure 24. Start-up via input voltage (no load) Figure 25. Start-up via En/Fault pin (no load)
DS13002 - Rev 4 page 15/32
Figure 26. Start-up via input voltage (5 Ω load)
STEF12S
Typical characteristics
Figure 27. Start-up via input voltage (C
OUT
= 1500 µF)
Figure 28. Start-up into voltage clamp
Figure 29. Voltage clamp during operation
Figure 30. Start-up into output short-circuit Figure 31. Start-up into overload
DS13002 - Rev 4 page 16/32
Figure 32. Overcurrent protection during operation
STEF12S
Typical characteristics
Figure 33. Output short-circuit during operation
Figure 34. Thermal shutdown (latched version)
Figure 35. Thermal shutdown (autoretry version)
DS13002 - Rev 4 page 17/32
8
8.1
STEF12S
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
TSOT23-8L package information
Figure 36. TSOT23-8L package outline
SIDE VIEW
TOP VIEW
DS13002 - Rev 4 page 18/32
DS13002 - Rev 4
Dim.
e e1
L
L1
L2
R
R1
Θ
Θ1 b1 c c1
D
E
E1
A
A1
A2 b aaa bbb ccc ddd
N
ND
Table 9. TSOT23-8L mechanical data
Min.
mm
Typ.
0.01
0.84
0.22
0.22
0.12
0.08
-
-
-
0.3
-
-
-
-
0.1
0.1
0.65 BSC
1.95 BSC
0.4
0.60 BSC
0.25 BSC
-
-
0 4°
4° 10°
Tolerance of form and position
0.15
0.25
0.1
0.13
8
4
0.05
0.87
-
0.26
0.15
0.13
2.90 BSC
2.80 BSC
1.60 BSC
STEF12S
TSOT23-8L package information
0.5
-
-
-
-
-
0.25
8°
12°
Max.
1
0.1
0.9
0.36
0.16
-
-
-
0.3
0.2
page 19/32
Figure 37. TSOT23-8L recommended footprint
STEF12S
TSOT23-8L package information
DS13002 - Rev 4 page 20/32
8.2
STEF12S
DFN10 (3 x 3 mm) package information
DFN10 (3 x 3 mm) package information
Figure 38. DFN10 (3 x 3 mm) package outline
DS13002 - Rev 4
7426335 page 21/32
Dim.
b
D
D2
E
E2
E3
A
A1
A2
A3
E4 e
L ddd
STEF12S
DFN10 (3 x 3 mm) package information
Table 10. DFN10 (3 x 3 mm) mechanical data
Min.
0.80
0.18
2.85
2.23
2.85
1.49
0.230
0.365
mm
Typ.
0.90
0.02
0.70
0.20
0.23
3.00
2.38
3.00
1.64
0.30
0.50
0.40
Max.
1.00
0.30
3.15
2.52
3.15
1.75
0.50
0.08
Figure 39. DFN10 (3 x 3 mm) recommended footprint
DS13002 - Rev 4 page 22/32
8.3
TSOT23-8L packing information
Figure 40. TSOT23-8L reel drawing outline
STEF12S
TSOT23-8L packing information
DS13002 - Rev 4 page 23/32
DS13002 - Rev 4
Figure 41. TSOT23-8L carrier tape
STEF12S
TSOT23-8L packing information
Figure 42. TSOT23-8L device orientation in tape page 24/32
8.4
STEF12S
DFN10 (3 x 3 mm) packing information
DFN10 (3 x 3 mm) packing information
Figure 43. DFN10 (3 x 3 mm) reel drawing outline
DS13002 - Rev 4 page 25/32
STEF12S
DFN10 (3 x 3 mm) packing information
Figure 44. DFN10 (3 x 3 mm) carrier tape
DS13002 - Rev 4
Figure 45. DFN10 (3 x 3 mm) device orientation in tape page 26/32
9
STEF12S
Ordering information
Ordering information
Order code
STEF12SGR
STEF12SAGR
STEF12SPUR
STEF12SAPUR
Package
Table 11. Order codes
Packaging
TSOT23-8
DFN10-3x3
Tape and reel
Marking
12SL
12HA
12SLP
12HA
Thermal protection
Latch-off
Autoretry
Latch-off
Autoretry
DS13002 - Rev 4 page 27/32
STEF12S
Revision history
Date
17-Dec-2019
29-May-2020
25-Aug-2020
06-Oct-2021
Revision
1
2
3
4
Table 12. Document revision history
Changes
Initial release.
Updated Figure 1, V
I(INT)
max. value in Table 5, Section 6.7 En/Fault pin, Section 6.9 Application suggestions and PCB layout guidelines and Figure 33.
Added row R
Lim
parameter in Table 4 and new order code STEF12SAPUR in Table 11.
Updated Table 11. Order codes.
Added new
Section 8.3 TSOT23-8L packing information and
Section 8.4 DFN10 (3 x 3 mm) packing information .
DS13002 - Rev 4 page 28/32
STEF12S
Contents
Contents
DS13002 - Rev 4 page 29/32
STEF12S
List of tables
List of tables
DS13002 - Rev 4 page 30/32
STEF12S
List of figures
List of figures
Figure 23. Soft-start time vs. temperature (no C dvdt
Figure 27. Start-up via input voltage (C
DS13002 - Rev 4 page 31/32
STEF12S
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DS13002 - Rev 4 page 32/32
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