STMicroelectronics M95M04-A145 Datasheet
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TSSOP8
169 mil width
SO8N
150 mil width
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M95M04-A125
M95M04-A145
M95M04-A125 M95M04-A145
Datasheet
Automotive 4 Mbit serial SPI bus EEPROM
Features
• AEC-Q100 grade 0 conform qualification
• Compatible with the serial peripheral interface (SPI) bus
• Memory array
– 4 Mbits (512 Kbytes) of EEPROM
– Page size: 512 bytes
– Write protection by block: 1/4, 1/2 or whole memory
• Additional write lockable page (identification page)
• Extended temperature and voltage range
– Up to 145 °C (V
CC
from 2.9 V to 5.5 V)
• Maximum clock frequency
– 10 MHz full range of V
CC
• Schmitt trigger inputs for noise filtering
• Short write cycle time
– Byte write within 4 ms
– Page write within 4 ms
• ESD Protection (human body model)
– 4000 V
• Packages
– RoHS-compliant and halogen-free (ECOPACK2)
– TSSOP8 package ECOPACK2
– SO8N package ECOPACK2
DS11938 - Rev 3 - April 2021
For further information contact your local STMicroelectronics sales office.
www.st.com
1
M95M04-A125 M95M04-A145
Description
Description
The M95M04-A125 and M95M04-A145 are 4 Mbit serial EEPROM automotive grade devices operating up to
145 °C. They are compliant with the very high level of reliability defined by the automotive standard AEC-Q100 grade 0.
The devices are accessed by a simple serial SPI compatible interface running at up to 10 MHz.
The memory array is based on advanced true EEPROM technology (electrically erasable programmable memory). The M95M04-A125 and M95M04-A145 are byte-alterable memories (524288 × 8 bits) organized as
1024 pages of 512 bytes in which the data integrity is significantly improved with an embedded Error Correction
Code logic.
The M95M04-A125 and M95M04-A145 offer an additional identification page (512 bytes) in which the ST device identification can be read. This page can also be used to store sensitive application parameters that can later be permanently locked in read-only mode.
Figure 1. Logic diagram
S
Q
DATA REGISTER
+
ECC
SENSE AMPLIFIERS
PAGE LATCHES X DECODER
W
ARRAY
I/O
STATUS
REGISTER
D
C
HOLD
CONTROL
LOGIC
CUSTOM AREA
HV GENERATOR
+
SEQUENCER
ADDRESS
REGISTER
DS11938 - Rev 3 page 2/42
DS11938 - Rev 3
M95M04-A125 M95M04-A145
Description
Figure 2. 8-pin package connections
W
VSS
S
Q
3
4
1
2
6
5
8
7
C
D
VCC
HOLD
1.
See Section 9 Package information
section for package dimensions and how to identify pin-1.
Table 1. Signal names
Signal name
Q
S
C
D
W
HOLD
V
CC
V
SS
Description
Serial clock
Serial data input
Serial data output
Chip select
Write protect
Hold
Supply voltage
Ground page 3/42
2.6
2.7
2.8
2
2.1
2.2
2.3
2.4
2.5
M95M04-A125 M95M04-A145
Signal description
Signal description
All input signals must be held high or low (according to voltages of V
IH
or V
IL
). These signals are described below.
Serial data output (Q)
This output signal is used to transfer data serially out of the device during a read operation. Data is shifted out on the falling edge of serial clock (C), most significant bit (MSB) first. In all other cases, the serial data output is in high impedance.
Serial data input (D)
This input signal is used to transfer data serially into the device. D input receives instructions, addresses, and the data to be written. Values are latched on the rising edge of serial clock (C), most significant bit (MSB) first.
Serial clock (C)
This input signal allows to synchronize the timing of the serial interface. Instructions, addresses, or data present at serial data input (D) are latched on the rising edge of serial clock (C). Data on serial data output (Q) changes after the falling edge of serial clock (C).
Chip select (S)
Driving chip select (S) low selects the device in order to start communication. Driving chip select (S) high deselects the device and serial data output (Q) enters the high impedance state.
Hold (HOLD)
The hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device.
Write protect (W)
This pin is used to write-protect the status register.
V
SS
ground
V
SS
is the reference for all signals, including the V
CC
supply voltage.
V
CC
supply voltage
V
CC
is the supply voltage pin. Refer to
Section 3.1 Active power and standby power modes and to
Section 5.1 Supply voltage (VCC)
.
DS11938 - Rev 3 page 4/42
3
3.1
3.2
M95M04-A125 M95M04-A145
Operating features
Operating features
Active power and standby power modes
When chip select (S) is low, the device is selected and in the active power mode.
When chip select (S) is high, the device is deselected. If a write cycle is not currently in progress, the device then goes in to the standby power mode, and the device consumption drops to I
CC1
.
SPI modes
The device can be driven by a microcontroller with its SPI peripheral running in either of the two following modes:
• CPOL=0, CPHA=0
• CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of serial clock (C), and output data is available from the falling edge of serial clock (C).
The difference between the two modes, as shown in
, is the clock polarity when the bus master is in stand-by mode and not transferring data:
• C remains at 0 for (CPOL=0, CPHA=0)
• C remains at 1 for (CPOL=1, CPHA=1)
Figure 3. SPI modes supported
CPOL CPHA
0 0 C
1 1 C
D
Q
MSB
MSB
DS11938 - Rev 3 page 5/42
3.3
3.4
3.4.1
M95M04-A125 M95M04-A145
Hold mode
Hold mode
The hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence.
The hold mode starts when the hold (HOLD) signal is driven low and the serial clock (C) is low (as shown in
). During the hold mode, the serial data output (Q) is high impedance, and the signals present on serial data input (D) and serial clock (C) are not decoded. The hold mode ends when the hold (HOLD) signal is driven high and the serial clock (C) is or becomes low.
Figure 4. Hold mode activation
HOLD
C
Hold condition
Hold condition
Deselecting the device while it is in hold mode resets the paused communication.
Protocol control and data protection
•
•
•
Protocol control
The chip select (S) input offers a built-in safety feature, as the S input is edge-sensitive as well as level-sensitive: after power-up, the device is not selected until a falling edge has first been detected on chip select (S). This ensures that chip select (S) must have been high prior to going low, in order to start the first operation.
For Write commands (WRITE, WRSR, WRID, LID) to be accepted and executed:
• the write enable latch (WEL) bit must be set by a write enable (WREN) instruction
• a falling edge and a low state on chip select (S) during the whole command must be decoded instruction, address and input data must be sent as multiple of eight bits the command must include at least one data byte chip select (S) must be driven high exactly after a data byte boundary
•
•
Write command can be discarded at any time by a rising edge on chip select (S) outside of a byte boundary.
To execute read commands (READ, RDSR, RDID, RDLS), the device must decode: a falling edge and a low level on chip select (S) during the whole command instruction and address as multiples of eight bits (byte)
From this step, data bits are shifted out until the rising edge on chip select (S).
DS11938 - Rev 3 page 6/42
3.4.2
M95M04-A125 M95M04-A145
Protocol control and data protection
Status register and data protection
The status register format is shown in
and the status and control bits of the status register are as follows:
Figure 5. Status register format
Note:
Note:
Bits b6, b5, and b4 are always read as 0.
WIP bit
The WIP bit (write in progress) is a read-only flag that indicates the ready/busy state of the device. When a write command (WRITE, WRSR, WRID) has been decoded and a write cycle (t
W
) is in progress, the device is busy and the WIP bit is set to 1. When WIP=0, the device is ready to decode a new command.
During a write cycle, reading continuously the WIP bit allows to detect when the device becomes ready (WIP=0) to decode a new command.
During a write lock ID, the device is busy but the WIP bit stays stable set to 0.
WEL bit
•
•
The WEL bit (write enable latch) bit is a flag that indicates the status of the internal write enable latch. When WEL is set to 1, the Write instructions (WRITE, WRSR, WRID, LID) are executed; when WEL is set to 0, any decoded
Write instruction is not executed.
The WEL bit is set to 1 with the WREN instruction. The WEL bit is reset to 0 after the following events:
•
Write disable (WRDI) instruction completion
Write instructions (WRITE, WRSR, WRID, LID) completion including the write cycle time t
W
Power-up
BP1, BP0 bits
The block protect bits (BP1, BP0) are non-volatile. BP1,BP0 bits define the size of the memory block to be
protected against write instructions, as defined in Figure 5
. These bits are written with the write status register
”).
DS11938 - Rev 3 page 7/42
3.5
Note:
M95M04-A125 M95M04-A145
Identification page
Table 2. Write-protected block size
Status register bits
BP1 BP0
0
0
1
1
0
1
0
1
Protected block
None
Upper quarter
Upper half
Whole memory
Protected array addresses
None
6.00.00h - 7.FF.FFh
4.00.00h - 7.FF.FFh
0.00.00h - 7.FF.FFh plus Identification page
SRWD bit and W input signal
The status register write disable (SRWD) bit is operated in conjunction with the write protect pin (W) signal. When the SRWD bit is written to 0, it is possible to write the status register, regardless of whether the pin write protect
(W) is driven high or low.
When the SRWD bit is written to 1, two cases have to be considered, depending on the state of the W input pin:
• Case 1: if pin W is driven high, it is possible to write the status register.
• Case 2: if pin W is driven low, it is not possible to write the status register (WRSR is discarded) and therefore
SRWD,BP1,BP0 bits cannot be changed (the size of the protected memory block defined by BP1,BP0 bits is frozen).
Case 2 can be entered in either sequence:
• Writing SRWD bit to 1 after driving pin W low, or
• Driving pin W low after writing SRWD bit to 1.
The only way to exit case 2 is to pull pin W high.
Note: if pin W is permanently tied high, the status register cannot be write-protected.
The protection features of the device are summarized in Table 3
.
SRWD bit
0
1
1
W signal
X
1
0
Table 3. Protection modes
Status
Status register is writable
Status Register is write-protected
Identification page
The M95M04-A125 and M95M04-A145 offer an identification page (512 bytes) in addition to the 4 Mbits memory.
The identification page contains two fields:
• Device identification: the three first byte are programmed by STMicroelectronics with the device identification code, as shown in
.
• Application parameters: the bytes after the device identification code are available for application specific data.
If the end application does not need to read the device identification code, this field can be overwritten and used to store application-specific data. Once the application-specific data are written in the Identification page, the whole Identification page should be permanently locked in Read-only mode.
The read, write, lock identification page instructions are detailed in Section 4 Instructions .
DS11938 - Rev 3 page 8/42
Address in identification page
00h
01h
02h
M95M04-A125 M95M04-A145
Identification page
Table 4. Device identification bytes
Content
ST manufacturer code
SPI family code
Memory density code
Value
20h
00h
13h (4 Mbit)
DS11938 - Rev 3 page 9/42
M95M04-A125 M95M04-A145
Instructions
4
Instructions
Each command is composed of bytes (MSBit transmitted first), initiated with the instruction byte, as summarized
If an invalid instruction is sent (one not contained in
), the device automatically enters a Wait state until deselected.
Instruction
WREN
WRDI
RDSR
WRSR
READ
WRITE
RDID
WRID
RDLS
LID
Table 5. Instruction set
Description
Write enable
Write disable
Read status register
Write status register
Read from memory array
Write to memory array
Read identification page
Write identification page
Reads the identification page lock status.
Locks the identification page in read-only mode.
Instruction format
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
1000 0011
1000 0010
1000 0011
1000 0010
For read and write commands to memory array and identification page, the address is defined by three bytes as explained in
.
Table 6. Significant bits within the address bytes
Instruction
Upper address byte Middle address byte Lower address byte b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
READ or WRITE
RDID or WRID
RDLS or LID
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A18
X
X
A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
X A8 A7 A6 A5 A4 A3 A2 A1 A0
X X X X X X X X X X
1. X: bit is Don’t care
2. A: Significant address bit
DS11938 - Rev 3 page 10/42
4.1
M95M04-A125 M95M04-A145
Write enable (WREN)
Write enable (WREN)
The WREN instruction must be decoded by the device before a write instruction (WRITE, WRSR, WRID or LID).
byte are shifted in (MSB first) on serial data input (D) after what the chip select (S) input is driven high and the
WEL bit is set (status register bit).
Figure 6. Write enable (WREN) sequence
S
C
D
Q
0 1 2 3 4 5 6 7
Instruction
High Impedance
4.2
Write disable (WRDI)
One way of resetting the WEL bit (in the status register) is to send a write disable instruction to the device.
instruction byte are shifted in (MSB first), on serial data input (D), after what the chip select (S) input is driven high and the WEL bit is reset (status register bit).
If a write cycle is currently in progress, the WRDI instruction is decoded and executed and the WEL bit is reset to
0 with no effect on the ongoing write cycle.
Figure 7. Write disable (WRDI) sequence
S
C
D
Q
0 1 2 3 4 5 6 7
Instruction
High Impedance
DS11938 - Rev 3 page 11/42
4.3
M95M04-A125 M95M04-A145
Read status register (RDSR)
Read status register (RDSR)
The read status register (RDSR) instruction is used to read the content of the status register.
instruction byte are shifted in (MSB first) on serial data Input (D), the status register content is then shifted out
(MSB first) on serial data output (Q).
If chip select (S) continues to be driven low, the status register content is continuously shifted out.
The status register can always be read, even if a Write cycle (t
W
) is in progress. The status register functionality is
detailed in Section 3.4.2 Status register and data protection .
Figure 8. Read status register (RDSR) sequence
S
C
D
Q
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction
High Impedance
Status Register Out Status Register Out
7 6 5 4 3 2 1 0
MSB
7 6 5 4 3 2 1 0
MSB
7
DS11938 - Rev 3 page 12/42
4.4
M95M04-A125 M95M04-A145
Write status register (WRSR)
Write status register (WRSR)
The write status register (WRSR) instruction allows new values to be written to the status register. Before it can be accepted, a write enable (WREN) instruction must previously have been executed.
The write status register (WRSR) instruction is entered (MSB first) by driving chip select (S) low, sending the instruction code followed by the data byte on serial data input (D), and driving the chip select (S) signal high.
The contents of the SRWD and BP1, BP0 bits are updated after the completion of the WRSR instruction, including the write cycle (t
W
).
The write status register (WRSR) instruction has no effect on the b6, b5, b4, b1 and b0 bits in the status register
(see
The status register functionality is detailed in Section 3.4.2 Status register and data protection .
The instruction is not accepted, and is not executed, if a write cycle is currently in progress.
Figure 9. Write status register (WRSR) sequence
S
C
D
Q
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction
High Impedance
StatusRegister In
7 6 5 4 3 2 1 0
MSB
DS11938 - Rev 3 page 13/42
4.5
M95M04-A125 M95M04-A145
Read from memory array (READ)
Read from memory array (READ)
The READ instruction is used to read the content of the memory.
, to send this instruction to the device, chip select (S) is first driven low.
The bits of the instruction byte and address bytes are shifted in (MSB first) on serial data input (D) and the addressed data byte is then shifted out (MSB first) on serial data output (Q). The first addressed byte can be any byte within any page.
If chip select (S) continues to be driven low, the internal address register is automatically incremented, and the next byte of data is shifted out. The whole memory can therefore be read with a single READ instruction.
When the highest address is reached, the address counter rolls over to zero, allowing the read cycle to be continued indefinitely.
The read cycle is terminated by driving chip select (S) high at any time when the data bits are shifted out on serial data output (Q).
The instruction is not accepted, and is not executed, if a write cycle is currently in progress.
Figure 10. Read from memory array (READ) sequence
1.
DS11938 - Rev 3 page 14/42
4.6
Note:
Note:
M95M04-A125 M95M04-A145
Write to memory array (WRITE)
Write to memory array (WRITE)
The WRITE instruction is used to write new data in the memory.
, to send this instruction to the device, chip select (S) is first driven low. The bits of the instruction byte, address byte, and at least one data byte are then shifted in (MSB first), on serial data input (D).
The instruction is terminated by driving chip select (S) high at a data byte boundary.
write.
Figure 11. Byte write (WRITE) sequence
S
C
D
Q
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
Instruction 24-bit address Data byte
23 22 21 3 2 1 0 7 6 5 4 3 2 1 0
High impedance
Depending on the memory size, as shown in Table 6
, the most significant address bits are "Don’t Care".
A page write is used to write several bytes inside a page, with a single internal write cycle.
For a page write, chip select (S) has to remain low, as shown in
Figure 12 , so that the next data bytes are
shifted in. Each time a new data byte is shifted in, the least significant bits of the internal address counter are incremented. If the address counter exceeds the page boundary (the page size is 512 bytes), the internal address pointer rolls over to the beginning of the same page where next data bytes will be written. If more than 512 byte are received, only the last 512 bytes are written.
For both byte write and page write, the self-timed write cycle starts from the rising edge of chip select (S), and continues for a period t
W
(as specified in
).
•
•
The instruction is discarded, and is not executed, under the following conditions:
• if a write cycle is already in progress if the addressed page is in the region protected by the block protect (BP1 and BP0) bits if one of the conditions defined in
Section 3.4.1 Protocol control is not satisfied
The self-timed write cycle t
W
is internally executed as a sequence of two consecutive events: [erase addressed byte(s)], followed by [program addressed byte(s)]. An erased bit is read as “0” and a programmed bit is read as
“1”.
DS11938 - Rev 3 page 15/42
M95M04-A125 M95M04-A145
Write to memory array (WRITE)
Figure 12. Page write (WRITE) sequence
S
C
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
Instruction 24-bit address Data byte 1
23 22 21 3 2 1 0 7 6 5 4 3 2 1 0
D
S
C
D
Data byte 2 Data byte 3 Data byte N
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 6 5 4 3 2 1 0
Note:
Depending on the memory size, as shown in Table 6
, the most significant address bits are "Don’t Care".
DS11938 - Rev 3 page 16/42
4.7
M95M04-A125 M95M04-A145
Read identification page (RDID)
Read identification page (RDID)
The read identification page instruction is used to read the identification page (additional page of 512 bytes which can be written and later permanently locked in read-only mode).
The chip select (S) signal is first driven low, the bits of the instruction byte and address bytes are then shifted in
(MSB first) on serial data input (D). Address bit A10 must be 0 and the other upper address bits are Don't Care (it might be easier to define these bits as 0. The data byte pointed to by the lower address bits [A8:A0] is shifted out
(MSB first) on serial data output (Q).
The first byte addressed can be any byte within the identification page.
If chip select (S) continues to be driven low, the internal address register is automatically incremented and the byte of data at the new address is shifted out.
Note that there is no roll over feature in the identification page. The address of bytes to read must not exceed the page boundary.
The read cycle is terminated by driving chip select (S) high. The rising edge of the chip select (S) signal can occur at any time when the data bits are shifted out.
The instruction is not accepted, and is not executed, if a write cycle is currently in progress.
Figure 13. Read identification page sequence
D
Q
S
C
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
Instruction
High impedance
24-bit address
23 22 21
MSB
3 2 1 0
Data Out 1
7 6 5 4 3
MSB
2 1 0
Data Out 2
7
The first three bytes of the identification page offer information about the device itself. Refer to
Section 3.5 Identification page
for more information.
DS11938 - Rev 3 page 17/42
4.8
Note:
M95M04-A125 M95M04-A145
Write identification page (WRID)
Write identification page (WRID)
The write identification page instruction is used to write the identification page (additional page of 512 bytes, which can also be permanently locked in read-only mode).
The chip select signal (S) is first driven low, and then the bits of the instruction byte, address bytes, and at least one data byte are shifted in (MSB first) on serial data input (D). Address bit A10 must be 0 and the other upper address bits are "Don't Care" (it might be easier to define these bits as 0. The lower address bits [A8:A0] define the byte address inside the identification page.
The self-timed write cycle starts from the rising edge of chip select (S), and continues for a period t
W
).
(as specified
Figure 14. Write identification page sequence
S
C
D
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
Instruction 24-bit address Data byte
23 22 21 3 2 1 0 7 6 5 4 3 2 1 0
High impedance
Q
•
•
The first three bytes of the identification page offer the device identification code (refer to
Section 3.5 Identification page
for more information). Using the WRID command on these first three bytes overwrites the device identification code.
The instruction is discarded, and is not executed, under the following conditions:
• If a write cycle is already in progress
If the block protect bits (BP1,BP0) = (1,1)
If one of the conditions defined in
Section 3.4.1 Protocol control
is not satisfied.
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4.9
M95M04-A125 M95M04-A145
Read lock status (RDLS)
Read lock status (RDLS)
The read lock status instruction is used to read the lock status.
To send this instruction to the device, chip select (S) first has to be driven low. The bits of the instruction byte and address bytes are then shifted in (MSB first) on serial data input (D). Address bit A10 must be 1; all other address bits are "Don't Care" (it might be easier to define these bits as 0. The lock bit is the LSB (least significant bit) of the byte read on serial data output (Q). It is at ‘1’ when the lock is active and at ‘0’ when the lock is not active. If chip select (S) continues to be driven low, the same data byte is shifted out.
.
The read lock status instruction is not accepted and not executed if a write cycle is currently in progress.
Figure 15. Read lock status sequence
S
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction 24-bit address
D
Q
High impedance
23 22 21
MSB
3 2 1 0
Data Out 1
7 6 5 4 3
MSB
2 1 0
Data Out 2
7
4.10
Lock identification page (LID)
The lock identification page (LID) command is used to permanently lock the identification page in read-only mode.
The LID instruction is issued by driving chip select (S) low, sending (MSB first) the instruction code, the address and a data byte on serial data input (D), and driving chip select (S) high. In the address sent, A10 must be equal to 1. All other address bits are "Don't Care" (it might be easier to define these bits as 0. The data byte sent must have the b0 bit equal to 1 (b0 = 1) and the others value of the bits b7 to b1 are "Don't Care". The data byte sent must be equal to the binary value xxxx xxx1, where x = Don't care. The LID instruction is terminated by driving chip select (S) high at a data byte boundary, otherwise, the instruction is not executed.
Figure 16. Lock ID sequence
S
C
D
Q
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
Instruction 24-bit address Data byte
23 22 21 3 2 1 0 7 6 5 4 3 2 1 0
High impedance
DS11938 - Rev 3 page 19/42
M95M04-A125 M95M04-A145
Lock identification page (LID)
•
•
Driving chip select (S) high at a byte boundary of the input data triggers the self-timed write cycle which duration is t
W
(specified in
). The instruction sequence is shown in Figure 16
.
The instruction is discarded, and is not executed, under the following conditions:
• If a write cycle is already in progress
If the block protect bits (BP1,BP0) = (1,1)
If one of the conditions defined in
Section 3.4.1 Protocol control
is not satisfied.
DS11938 - Rev 3 page 20/42
5
5.1
5.1.1
5.1.2
M95M04-A125 M95M04-A145
Application design recommendations
Application design recommendations
Supply voltage (V
CC
)
Operating supply voltage (V
CC
)
Prior to selecting the memory and issuing instructions to it, a valid and stable V
CC
voltage within the specified
[V
CC(min)
, V
CC(max)
] range must be applied (see Table 9 and Table 10 ).
This voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until the completion of the internal Write cycle (t
W
). In order to secure a stable DC supply voltage, it is recommended to decouple the V
CC
line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the V
CC
/V
SS
package pins.
•
•
Power-up conditions
When the power supply is turned on, V
CC
continuously rises from V
SS
to V
CC
. During this time, the chip select (S) line is not allowed to float but should follow the V
CC
voltage. The S line must be connected to V
CC
via a suitable
pull-up resistor (see Figure 17
).
The V
CC
voltage has to rise continuously from 0 V up to the minimum V
CC
operating voltage defined in
In order to prevent inadvertent write operations during power-up, a power-on-reset (POR) circuit is included.
•
•
At power-up, the device does not respond to any instruction until V
CC
reaches the internal threshold voltage (this
threshold is defined in the Table 14
as VRES).
When V
CC
passes over the POR threshold, the device is reset and in the following state: in the standby power mode deselected
Status register values:
– Write enable Latch (WEL) bit is reset to 0.
– Write in progress (WIP) bit is reset to 0.
– SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits).
not in the hold condition
As soon as the V
CC
voltage has reached a stable value within [V operation.
CC
(min), V
CC
(max)] range, the device is ready for
DS11938 - Rev 3 page 21/42
5.1.3
5.2
M95M04-A125 M95M04-A145
Implementing devices on SPI bus
Power-down
At power down, the power-on-reset (POR) circuit resets and locks the device as soon as the V
CC
reached the internal threshold voltage.
During power-down (continuous decrease in the V
CC
supply voltage below the minimum V
CC
operating voltage
), the device must be:
•
• deselected (chip select (S) should be allowed to follow the voltage applied on V
CC in standby power mode (there should not be any internal write cycle in progress).
),
Implementing devices on SPI bus
time, so that only the selected device drives the serial data output (Q) line. All the other devices outputs are then in high impedance.
Figure 17. Bus master and memory devices on the SPI bus
V
CC
SPI interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDO
SDI
SCK
SPI bus master
CS3 CS2 CS1
R
C Q D V
CC
SPI memory device
S W HOLD
R
C Q D V
CC
SPI memory device
S W HOLD
R
C Q D V
CC
SPI memory device
S W HOLD
Note:
V
SS
The write protect (W) and hold (HOLD) signals must be driven high or low as appropriate.
A pull-up resistor connected on each S input (represented in Figure 17
) ensures that each device is not selected if the bus master leaves the S line in the high impedance state.
DS11938 - Rev 3 page 22/42
5.3
M95M04-A125 M95M04-A145
Cycling with error correction code (ECCx4)
Cycling with error correction code (ECCx4)
The error correction code (ECC) is an internal logic function which is transparent for the SPI communication protocol.
The ECC logic is implemented on each group of four EEPROM bytes (a group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer).
Even if the ECC function is performed on groups of four bytes, a single byte can be written/cycled independently.
In this case, the ECC function also writes/cycles the three other bytes located in the same group (a group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer). As a consequence, the maximum cycling budget is defined at group level and the cycling can be distributed over the 4 bytes of the group: the sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain below the maximum
DS11938 - Rev 3 page 23/42
6
M95M04-A125 M95M04-A145
Delivery state
Delivery state
The device is delivered with:
•
•
• the memory array set to all 1s (each byte = FFh),
The status register bits set to '0' (byte = 00h),
Identification page: the first three bytes define the device identification code (value defined in content of the following bytes is "Don’t care".
). The
DS11938 - Rev 3 page 24/42
7
M95M04-A125 M95M04-A145
Absolute maximum ratings
Absolute maximum ratings
Stressing the device outside the ratings listed in
may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 7. Absolute maximum ratings
Symbol
T
STG
T
AMR
T
LEAD
V
O
V
I
I
OL
I
OH
V
CC
V
ESD
Storage temperature
Parameter
Ambient operating temperature
Lead temperature during soldering
Voltage on Q pin
Input voltage
DC output current (Q = 0)
DC output current (Q = 1)
Supply voltage
Electrostatic pulse (human body model) (2)
Min.
-65
-40
-0.50
-0.50
-
-
- 0.50
-
Max.
150
150
See note
V
CC
+ 0.5
6.5
5
5
6.5
4000
Unit
°C
°C
°C
V
V mA mA
V
V
1. Compliant with JEDEC Std J-STD-020 (for small body, Sn-Pb or Pb-free assembly), the ST ECOPACK 7191395 specification, and the European directive on Restrictions of Hazardous Substances (RoHS directive 2011/65/EU of July
2011).
2. Positive and negative pulses applied on pin pairs, in accordance with AEC-Q100-002 (compliant with ANSI/ESDA/JEDEC
JS-001, C1=100 pF, R1=1500 Ω, R2=500 Ω)
DS11938 - Rev 3 page 25/42
M95M04-A125 M95M04-A145
DC and AC parameters
8
DC and AC parameters
This section summarizes the operating conditions and the DC/AC characteristics of the device.
Table 8. Cycling performance by groups of 4 bytes
Symboil
NCycle
Parameter
Write cycles endurance
Conditions
TA ≤ 25 °C, 2.9 V ≤ V
CC
≤ 5.5 V
TA ≤ 85 °C, 2.9 V ≤ V
CC
≤ 5.5 V
TA ≤ 125 °C, 2.9 V ≤ V
CC
≤ 5.5 V
, 2.9 V ≤ V
CC
≤ 5.5 V
Min.
-
-
-
-
Max.
1 000 000
500 000
200 000
100 000
Unit
1. The write cycle endurance is defined for groups of four data bytes located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3] where
N is an integer, or for the status register byte (refer also to Cycling with error correction code (ECCx4)). The write cycle endurance is evaluated by characterization – not tested in production.
2. In case of intensive write status register in the application, contact you local ST sales
3. A write cycle is executed when either a page write, a byte write, a WRSR, or a WRID instruction is decoded. When using the byte write, the page write or the WRID, refer also to Cycling with error correction code (ECCx4).
4. For temperature range 4 only.
Symbol
V
CC
T
A f
C
Table 9. Operating conditions (voltage range W, temperature range 4)
Parameter
Supply voltage
Ambient operating temperature
Operating clock frequency
Conditions
-
-
5.5 V ≥ V
CC
≥ 2.9 V, capacitive load on Q pin ≤ 100 pF
Min.
2.9
-40
-
Max.
5.5
145
10
Unit
V
°C
MHz
Symbol
V
CC
T
A f
C
Table 10. Operating conditions (voltage range W, temperature range 3)
Parameter
Supply voltage
Ambient operating temperature
Operating clock frequency
Conditions
-
-
5.5 V ≥ V
CC
≥ 2.9 V, capacitive load on Q pin ≤ 100 pF
Min.
2.9
-40
-
Max.
5.5
125
10
Unit
V
°C
MHz
Symbol
C
L
-
-
-
Table 11. AC measurement conditions
Parameter
Load capacitance
Input rise and fall times
Input pulse voltages
Input and output timing reference voltages
Min.
-
Max.
100
25
0.2 V
CC
to 0.8 V
CC
0.3 V
CC
to 0.7 V
CC
Unit pF ns
V
V
DS11938 - Rev 3 page 26/42
DS11938 - Rev 3
M95M04-A125 M95M04-A145
DC and AC parameters
Input Levels
0.8 ₓ V
CC
Figure 18. AC measurement I/O waveform
Input and Output
Timing Reference Levels
0.7 ₓ V
CC
0.3 ₓ V
CC
0.2 ₓ V
CC
Table 12. Memory cell data retention
Parameter
Test conditions
2.9 V ≤ V
CC
≤ 5.5 V
Data retention performance per cell
10 years at 55 °C after max cycling
1. The data retention endurance is evaluated by characterization – not tested in production.
Table 13. Capacitance
Symbol
C
OUT
C
IN
Parameter
Output capacitance (Q)
Input capacitance (D)
Input capacitance (other pins)
V
OUT
= 0 V
V
IN
= 0 V
V
IN
= 0 V
1. Sampled only, not 100% tested, at TA = 25 °C and at a frequency of 5 MHz.
Min.
-
-
-
Max.
8
8
6
Unit pF pF pF page 27/42
M95M04-A125 M95M04-A145
DC and AC parameters
Table 14. DC characteristics
Symbol Parameter
Specific test conditions (in addition to conditions specified in
)
I
I
I
I
I
LI
LO
CC
CC0
CC1
Input leakage current
Output leakage current
Supply current (Read)
Supply current (Write)
Supply current
(Standby power mode)
V
IL
V
IH
V
OL
V
OH
V
RES
Input low voltage
1. Average value during the write cycle (t
W
)
2. Characterized only, not 100% tested.
V
IN
= V
SS
or V
CC
S = V
CC
, V
OUT
= V
SS
or V
CC
V
CC
= 3.6 V, f
C
= 10 MHz,
C = 0.1 V
CC
/0.9 V
CC,
Q = open
V
CC
= 5.5 V, f
C
= 10 MHz,
C = 0.1 V
CC
/0.9 V
CC,
Q = open
2.9 V < V
CC
< 5.5 V, during t
W
,
S = V
CC t° = amb, V
CC
= 3.6 V, S = V
CC
V
IN
= V
SS
or V
CC t° = amb, V
CC
= 5.5 V, S = V
CC
V
IN
= V
SS
or V
CC
t° = 125 °C, V
CC
= 3.6 V, S = V
CC
V
IN
= V
SS
or V
CC t° = 125 °C, V
CC
= 5.5 V, S = V
CC
V
IN
= V
SS
or V
CC t° = 145 °C, V
CC
= 3.6 V, S = V
CC
V
IN
= V
SS
or V
CC t° = 145 °C, V
CC
= 5.5 V, S = V
CC
V
IN
= V
SS
or V
CC
Input high voltage
Output low voltage
Output high voltage
Internal reset threshold voltage -
-
I
OL
= 2 mA
I
OH
= –2 mA
Min.
-
-
-
-
Max.
Unit
2
3
µA
2 mA
3
-
-
-
-
-
2
mA
2
3
10
15
20
µA
30
–0.45
0.3 V
CC
0.7 V
CC
V
CC
+1
0.4
0.8 V
CC
0.5
-
1.5
V
DS11938 - Rev 3 page 28/42
DS11938 - Rev 3
M95M04-A125 M95M04-A145
DC and AC parameters
Table 15. AC characteristics (5 MHz) t
CH
t
CL
t
CLCH
t
CHCL
t
DVCH t
CHDX t
HHCH t
HLCH t
CLHL t
CLHH
Symbol f
C t
SLCH t
SHCH t
SHSL t
CHSH t
CHSL t
SHQZ
t
CLQV
t
CLQX t
QLQH
t
QHQL
t
HHQV t
HLQZ
t
W f
SCK t
CSS1 t
CSS2 t
CS t t t
CSH t t t
Alt.
t
-
CLH
CLL
RC
FC
DSU
DH
-
-
-
-
Clock frequency
S active setup time
S not active setup time
S deselect time
S active hold time
S not active hold time
Clock high time
Clock low time
Clock rise time
Clock fall time
Data in setup time
Data in hold time
Parameter
Clock low hold time after HOLD not active
Clock low hold time after HOLD active
Clock low set-up time before HOLD active
Clock low set-up time before HOLD not active
Min.
-
60
60
90
60
60
80
80
-
-
20
20
60
60
0
0
Max.
5
-
-
-
-
-
-
2
2
-
-
-
-
-
-
-
Unit
MHz ns
µs t
DIS t
V t
HO t
RO t
FO t
LZ t
HZ t
WC
Output disable time
Clock low to output valid
Output hold time
Output rise time
Output fall time
HOLD high to output valid
HOLD low to output high-Z
Write time
-
-
0
-
-
-
-
-
80
80
-
80
80
80
80
4
ns ms
1. t
CH
+ t
CL
must never be lower than the shortest possible clock period, 1/f
C
(max).
2. Value evaluated by characterization – not tested in production.
3. t
CLQV
must be compatible with t
CL
(or greater than) t
CLQV
+t
SU
.
(clock low time): if t
SU
is the Read setup time of the SPI bus master, t
CL
must be equal to
4. Write time for LID instruction is 10 ms.
page 29/42
DS11938 - Rev 3
M95M04-A125 M95M04-A145
DC and AC parameters
Table 16. AC characteristics (10 MHz) t
CH
t
CL
t
CLCH
t
CHCL
t
DVCH t
CHDX t
HHCH t
HLCH t
CLHL t
CLHH
Symbol f
C t
SLCH t
SHCH t
SHSL t
CHSH t
CHSL t
SHQZ
t
CLQV
t
CLQX t
QLQH
t
QHQL
t
HHQV t
HLQZ
t
W f
SCK t
CSS1 t
CSS2 t
CS t t t
CSH t t t
Alt.
t
-
CLH
CLL
RC
FC
DSU
DH
-
-
-
-
Clock frequency
S active setup time
S not active setup time
S deselect time
S active hold time
S not active hold time
Clock high time
Clock low time
Clock rise time
Clock fall time
Data in setup time
Data in hold time
Parameter
Clock low hold time after HOLD not active
Clock low hold time after HOLD active
Clock low set-up time before HOLD active
Clock low set-up time before HOLD not active
Min.
-
30
30
40
30
30
40
40
-
-
10
10
30
30
0
0
Max.
10
-
-
-
-
-
-
2
2
-
-
-
-
-
-
-
Unit
MHz ns
µs t
DIS t
V t
HO t
RO t
FO t
LZ t
HZ t
WC
Output disable time
Clock low to output valid
Output hold time
Output rise time
Output fall time
HOLD high to output valid
HOLD low to output high-Z
Write time
-
-
0
-
-
-
-
-
40
40
-
40
40
40
40
4
ns ms
1. t
CH
+ t
CL
must never be lower than the shortest possible clock period, 1/f
C
(max).
2. Value evaluated by characterization – not tested in production.
3. t
CLQV
must be compatible with t
CL
(or greater than) t
CLQV
+t
SU
.
(clock low time): if t
SU
is the Read setup time of the SPI bus master, t
CL
must be equal to
4. Write time for LID instruction is 10 ms.
page 30/42
DS11938 - Rev 3
S
C
Q t
CLQV t
CLQX
D
ADDR
LSB IN
M95M04-A125 M95M04-A145
DC and AC parameters
Figure 19. Serial input timing
S
C t
CHSL
D
Q t
SLCH t
DVCH
MSB IN
High impedance t
CHCL t
CHDX t
CH t
CL t
CHSH
LSB IN t
CLCH t
SHSL t
SHCH
Figure 20. Hold timing
S t
HLCH
C t
CLHL t
HLQZ t
HHCH t
CLHH t
HHQV
Q
HOLD t
CLCH
Figure 21. Serial output timing t
CH t
CHCL t
CL t
QLQH t
QHQL t
SHSL t
SHQZ page 31/42
9
9.1
M95M04-A125 M95M04-A145
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.
SO8N package information
SO8N is an 8-lead, 4.9 x 6 mm, plastic small outline, 150 mils body width, package.
Figure 22. SO8N – Outline h x 45˚ c
A2 A b e
D
8
1
E1 E ccc
A1
L1
L
0.25 mm
GAUGE PLANE k
1.
Drawing is not to scale.
Table 17. SO8N – Mechanical data
Symbol
D
E
E1 e h k
L
L1 ccc
A
A1
A2 b c
Min.
-
0.100
1.250
0.280
0.170
4.800
5.800
3.800
-
0.250
0°
0.400
-
millimeters
Typ.
-
-
4.900
6.000
3.900
-
-
-
1.270
-
-
-
1.040
-
Max.
5.000
6.200
4.000
-
0.500
1.750
0.250
-
0.480
0.230
8°
1.270
-
0.100
1. Values in inches are converted from mm and rounded to four decimal digits.
Min.
-
0.0039
0.0492
0.0110
0.0067
0.1890
0.2283
0.1496
-
0.0098
0°
0.0157
-
inches
Typ.
0.1929
0.2362
0.1535
0.0500
-
-
-
0.0409
-
-
-
-
-
-
Max.
0.0689
0.0098
-
0.0189
0.0091
0.1969
0.2441
0.1575
-
0.0197
8°
0.0500
-
0.0039
DS11938 - Rev 3 page 32/42
M95M04-A125 M95M04-A145
SO8N package information
Figure 23. SO8N - Recommended footprint
0.6 (x8)
1.
Dimensions are expressed in millimeters.
1.27
DS11938 - Rev 3 page 33/42
9.2
M95M04-A125 M95M04-A145
TSSOP8 package information
TSSOP8 package information
TSSOP8 is an 8-lead thin shrink small outline, 3 x 6.4 mm, 0.65 mm pitch, package.
Figure 24. TSSOP8 – Outline
D
8 5
E1 E
1 4
α
A1
CP
A A2 b e
1.
Drawing is not to scale.
Table 18. TSSOP8 – Mechanical data
Symbol
D e
E
E1
L
L1
α
A
A1
A2 b c
CP
Min.
-
0.050
0.800
0.190
0.090
-
2.900
-
6.200
4.300
0.450
-
0° millimeters
Typ.
-
-
1.000
-
-
-
3.000
0.650
6.400
4.400
0.600
1.000
-
Max.
1.200
0.150
1.050
0.300
0.200
0.100
3.100
-
6.600
4.500
0.750
-
8°
Min.
-
0.0020
0.0315
0.0075
0.0035
-
0.1142
-
0.2441
0.1693
0.0177
-
0°
1. Values in inches are converted from mm and rounded to four decimal digits.
L1
L inches
Typ.
-
-
0.0394
-
-
-
0.1181
0.0256
0.2520
0.1732
0.0236
0.0394
c
Max.
0.0472
0.0059
0.0413
0.0118
0.0079
0.0039
0.1220
-
0.2598
0.1772
0.0295
-
8°
DS11938 - Rev 3 page 34/42
DS11938 - Rev 3
M95M04-A125 M95M04-A145
TSSOP8 package information
Figure 25. TSSOP8 – Recommended footprint
2.3
1.0
7.0
0.65
1.
Dimensions are expressed in millimeters.
0.35
page 35/42
10
Note:
M95M04-A125 M95M04-A145
Ordering information
Ordering information
Table 19. Ordering information scheme
Example:
Device type
M95 = SPI serial access EEPROM
Device function
M04-D = 4 Mbits (512 Kbytes) plus identification page
Operating voltage
W = V
CC
= 2.9 V to 5.5 V
Package
MN = SO8 (150 mil width)
DW = TSSOP8 (169 mil width)
Device grade
3 = -40 to 125 °C. Automotive grade. Device tested with high reliability certified flow
4 = -40 to 145 °C. Automotive grade. Device tested with high reliability certified flow (2)
Option
T = Tape and reel packing blank = tube packing
Planting technology
P or G = ECOPACK2
Process
/V = Manufacturing technology code
M95 M04-D W DW 4 T P /V
1. All packages are ECOPACK2 (RoHS compliant and free of brominated, chlorinated and antimonyoxide flame retardants).
2. The high reliability certified flow (HRCF) is described in quality note QNEE9801. Please ask your nearest ST sales office for a copy.
For a list of available options (speed, package, etc.) or for further information on any aspect of the devices, please contact your nearest ST sales office.
Engineering samples
Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at
ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST
Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity.
DS11938 - Rev 3 page 36/42
M95M04-A125 M95M04-A145
Revision history
Table 20. Document revision history
Date
04-Jan-2017
Revision
1
27-Apr-2020
27-Apr-2021
2
3
Changes
Initial release.
•
•
•
Updated:
Section 3.4.2 Status register and data protection
,
Section 4.10 Lock identification page (LID)
,
Section 5.3 Cycling with error correction code (ECCx4)
Table 6. Significant bits within the address bytes
, Table 7. Absolute maximum ratings ,
Table 14. DC characteristics ,
Table 15. AC characteristics (5 MHz)
,
Table 16. AC characteristics (10 MHz) ,
Table 19. Ordering information scheme
•
Added:
Table 11. AC measurement conditions ,
Table 12. Memory cell data retention
,
Removed: Table 13. DC characteristics (voltage range W, temperature range 3), Table 17. AC characteristics (20 MHz)
•
•
•
Updated:
Section 3.1 Active power and standby power modes
,
Section 4.8 Write identification page (WRID) ,
Section 4.9 Read lock status (RDLS) , Section 4.10 Lock identification page (LID)
, Section 5.3 Cycling with error correction code (ECCx4) ,
note 2 on
Table 7. Absolute maximum ratings
Table 8. Cycling performance by groups of 4 bytes
, Table 12. Memory cell data retention ,
,
Table 15. AC characteristics (5 MHz)
, Table 16. AC characteristics (10 MHz)
DS11938 - Rev 3 page 37/42
M95M04-A125 M95M04-A145
Contents
Contents
DS11938 - Rev 3 page 38/42
M95M04-A125 M95M04-A145
Contents
DS11938 - Rev 3 page 39/42
M95M04-A125 M95M04-A145
List of figures
List of figures
DS11938 - Rev 3 page 40/42
M95M04-A125 M95M04-A145
List of tables
List of tables
DS11938 - Rev 3 page 41/42
M95M04-A125 M95M04-A145
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks . All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2021 STMicroelectronics – All rights reserved
DS11938 - Rev 3 page 42/42
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