STMicroelectronics M95128-DF Datasheet
Werbung
Werbung
SO8N
150 mil width
TSSOP8
169 mil width
UFDFPN8 (MC)
DFN8 - 2x3 mm
WLSCP (CS)
Product status link
M95128-DF
M95128-R
M95128-W
M95128-W M95128-R M95128-DF
Datasheet
128-Kbit serial SPI bus EEPROM with high-speed clock
Features
• Compatible with the serial peripheral interface (SPI) bus
• Memory array
– 128 Kbit (16 Kbytes) of EEPROM
– Page size: 64 bytes
– Additional write lockable page (Identification page)
• Write time
– Byte Write within 5 ms
– Page Write within 5 ms
• Write protect
– quarter array
– half array
– whole memory array
• High-speed clock: 20 MHz
• Single supply voltage:
– 2.5 V to 5.5 V for M95128-W
– 1.8 V to 5.5 V for M95128-R
– 1.7 V to 5.5 V for M95128-DF
• Operating temperature range: from -40 °C up to +85 °C
• Enhanced ESD protection
• More than 4 million Write cycles
• More than 200-year data retention
• Packages
– SO8 (ECOPACK2 ® )
– TSSOP8 (ECOPACK2 ® )
– UFDFPN8 (ECOPACK2 ® )
– WLCSP (ECOPACK2 ® )
DS1356 - Rev 20 - October 2020
For further information contact your local STMicroelectronics sales office.
www.st.com
1
M95128-W M95128-R M95128-DF
Description
Description
The M95128 devices are electrically erasable programmable memories (EEPROMs) organized as 16384 x 8 bits, accessed through the SPI bus.
The M95128-W can operate with a supply voltage from 2.5 V to 5.5 V, the M95128-R can operate with a supply voltage from 1.8 V to 5.5 V and the M95128-DF can operate with a supply voltage from 1.7 V to 5.5 V, over an ambient temperature range of -40 °C / +85 °C.
The M95128-DF offers an additional page, named the Identification page (64 bytes). The Identification page can be used to store sensitive application parameters that can be (later) permanently locked in read-only mode.
Figure 1. Logic diagram
V
CC
D
C
S
W
HOLD
M95xxx Q
V
SS
The SPI bus signals are C, D and Q, as shown in
Figure 1. Logic diagram and Table 1. Signal names . The device
is selected when Chip select (S) is driven low. Communications with the device can be interrupted when the
HOLD is driven low.
C
D
Q
S
W
HOLD
V
CC
V
SS
Signal name
Table 1. Signal names
Function
Serial clock
Serial data input
Serial data output
Chip select
Write protect
Hold
Supply voltage
Ground -
-
Input
Input
Output
Input
Input
Input
Direction
DS1356 - Rev 20 page 2/48
DS1356 - Rev 20
M95128-W M95128-R M95128-DF
Description
Figure 2. 8-pin package connections (top view)
M95xxx
W
V
SS
S
Q
3
4
1
2
6
5
8
7
C
D
V
CC
HOLD
1.
See Section 10 Package information for package dimensions, and how to identify pin 1.
Figure 3. WLCSP connections (top view, marking side, with bumps on the underside)
1 2 3
A
D
E
B
C
HOLD
S
V
CC
C
D
Q
V
SS
W
Position
1
2
3
A
HOLD
-
Q
Table 2. Signals vs. bump position
S
-
B
-
C
V
CC
-
V
SS
D
-
D
-
-
W
E
C page 3/48
2
M95128-W M95128-R M95128-DF
Memory organization
Memory organization
The memory is organized as shown in the following figure.
Figure 4. Block diagram
/S
Q
DATA REGISTER
+
ECC
SENSE AMPLIFIERS
PAGE LATCHES
ARRAY
W
D
C
HOLD
I/O
STATUS
REGISTER
CONTROL
LOGIC
CUSTOM AREA
HV GENERATOR
+
SEQUENCER
X DECODER
ADDRESS
REGISTER
DS1356 - Rev 20 page 4/48
3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
M95128-W M95128-R M95128-DF
Signal description
Signal description
During all operations, V
CC
must be held stable and within the specified valid range: V
CC
(min) to V
CC
(max).
All of the input and output signals must be held high or low (according to voltages of V
IH
, V
OH
, V
IL
or V
OL
, as
specified in Section 9 DC and AC parameters ). These signals are described next.
Serial data output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial clock (C).
Serial data input (D)
This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be written. Values are latched on the rising edge of Serial clock (C).
Serial clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial data input (D) are latched on the rising edge of Serial clock (C). Data on Serial data output (Q) change from the falling edge of Serial clock (C).
Chip select (S)
When this input signal is high, the device is deselected and Serial data output (Q) is at high impedance. The device is in the Standby power mode, unless an internal Write cycle is in progress. Driving Chip select (S) low selects the device, placing it in the Active power mode.
After power-up, a falling edge on Chip select (S) is required prior to the start of any instruction.
Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device.
During the Hold condition, the Serial data output (Q) is high impedance, and Serial data input (D) and Serial clock
(C) are Don’t care.
To start the Hold condition, the device must be selected, with Chip select (S) driven low.
Write protect (W)
The main purpose of this input signal is to freeze the size of the area of memory that is protected against Write instructions (as specified by the values in the BP1 and BP0 bits of the Status register).
This pin must be driven either high or low, and must be stable during all Write instructions.
V
CC supply voltage
V
CC
is the supply voltage.
V
SS
ground
V
SS
is the reference for all signals, including the V
CC
supply voltage.
DS1356 - Rev 20 page 5/48
4
M95128-W M95128-R M95128-DF
Connecting to the SPI bus
Connecting to the SPI bus
All instructions, addresses and input data bytes are shifted in to the device, most significant bit first. The Serial data input (D) is sampled on the first rising edge of the Serial clock (C) after Chip select (S) goes low.
All output data bytes are shifted out of the device, most significant bit first. The Serial data output (Q) is latched on the first falling edge of the Serial clock (C) after the instruction (such as the Read from Memory array and Read
Status register instructions) have been clocked into the device.
Figure 5. Bus master and memory devices on the SPI bus
V
CC
SPI interface with
(CPOL, CPHA) =
(0, 0) or 1, 1)
SDO
SDI
SCK
SPI bus master
C Q D V
CC
C Q D V
CC
C Q D V
CC
CS3 CS2 CS1
R
SPI memory device
S W HOLD
R
SPI memory device
S W HOLD
R
SPI memory device
S W HOLD
(1) (1) (1) (1) (1) (1)
V
SS
1.
The Write protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.
to an SPI bus master. Only one memory device is selected at a given time, so only one memory device drives the
Serial data output (Q) line at that time. The other memory devices are in high impedance state. The pull-up resistor R ensures that a device is not selected if the Bus master leaves the S line in the high impedance state.
In applications where the bus master can enter a state where the whole input/output SPI bus is high-impedance at a given time (for example, if the bus master is reset during the transmission of an instruction), it is advised to connect the clock line (C) to an external pull-down resistor so that, if all inputs/outputs become high-impedance, the C line is pulled low (while the S line is pulled high). This ensures that S and C do not become high at the same time, and so, that the t
SHCH
requirement is met. The typical value of R is 100 kΩ.
DS1356 - Rev 20 page 6/48
4.1
M95128-W M95128-R M95128-DF
SPI modes
SPI modes
•
•
These devices can be driven by a microcontroller with its SPI peripheral running in either of the following two modes:
CPOL = 0, CPHA = 0
CPOL = 1, CPHA = 1
•
•
For these two modes, input data is latched in on the rising edge of Serial clock (C), and output data is available from the falling edge of Serial clock (C).
The difference between the two modes, as shown in
Figure 6. SPI modes supported , is the clock polarity when
the bus master is in Stand-by mode and not transferring data:
C remains at 0 for (CPOL = 0, CPHA = 0)
C remains at 1 for (CPOL = 1, CPHA = 1)
Figure 6. SPI modes supported
CPOL
0
CPHA
0 C
1 1 C
D
Q
MSB
MSB
DS1356 - Rev 20 page 7/48
M95128-W M95128-R M95128-DF
Operating features
5
Operating features
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.2
Supply voltage (V
CC
)
Operating supply voltage (V
CC
)
Prior to selecting the memory and issuing instructions to it, a valid and stable V
CC
voltage within the specified
[V
CC
(min), V
CC
(max)] range must be applied (see Operating conditions in Section 9 DC and AC parameters
).
This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (t
W recommended to decouple the V
CC
). In order to secure a stable DC supply voltage, it is
line with a suitable capacitor (usually in the range between 10 and 100 nF) close to the V
CC
/ V
SS
device pins.
•
Device reset
In order to prevent erroneous instruction decoding and inadvertent Write operations during power ‑ up, a power ‑ on ‑ reset (POR) circuit is included. At power-up, the device does not respond to any instruction until VCC reaches the POR threshold voltage. This threshold is lower than the minimum V
CC
operating voltage (see
Operating conditions in
Section 9 DC and AC parameters ).
•
•
At power-up, when V
CC
passes over the POR threshold, the device is reset and is in the following state: in Standby power mode, deselected,
Status register values:
– the Write enable latch (WEL) bit is reset to 0
– the Write in progress (WIP) bit is reset to 0
– the SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits).
It is important to note that the device must not be accessed until V
CC
reaches a valid and stable level within the specified [V
CC
(min), V
CC
(max)] range, as defined under Operating conditions in Section 9 DC and AC parameters
.
Power-up conditions
When the power supply is turned on, V
CC
rises continuously from V
SS
to V
CC
. During this time, the Chip select (S) line is not allowed to float but should follow the V
CC
voltage. It is therefore recommended to connect the S line to
V
CC
via a suitable pull-up resistor (see
Figure 5. Bus master and memory devices on the SPI bus ).
In addition, the Chip select (S) input offers a built-in safety feature, as the S input is edge-sensitive as well as level-sensitive: after power-up, the device does not become selected until a falling edge has first been detected on Chip select (S). This ensures that Chip select (S) must have been high, prior to going low to start the first operation.
The V
CC
voltage has to rise continuously from 0 V up to the minimum V
Section 9 DC and AC parameters .
CC
operating voltage defined in
Power-down
During power-down (continuous decrease of the V
CC
supply voltage below the minimum V
CC
operating voltage
defined in Section 9 DC and AC parameters ), the device must be:
•
• deselected (Chip select S must be allowed to follow the voltage applied on V
CC in Standby power mode (there must not be any internal write cycle in progress).
)
Active power and Standby power modes
When Chip select (S) is low, the device is selected, and in the Active power mode. The device consumes I
CC
.
When Chip select (S) is high, the device is deselected. If a Write cycle is not currently in progress, the device then goes into the Standby power mode, and the device consumption drops to I
CC1
, as specified in DC characteristics
(see
Section 9 DC and AC parameters ).
DS1356 - Rev 20 page 8/48
M95128-W M95128-R M95128-DF
Hold condition
5.3
Note:
5.4
Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence.
To enter the Hold condition, the device must be selected, with Chip select (S) low.
During the Hold condition, the Serial data output (Q) is high impedance, and the Serial data input (D) and the
Serial clock (C) are Don’t care.
Normally, the device is kept selected for the whole duration of the Hold condition. Deselecting the device while it is in the Hold condition has the effect of resetting the state of the device: this mechanism can be used, if required, to reset the ongoing processes.
This resets the internal logic, except the WEL and WIP bits of the Status register.
In the specific case where the device has moved in a Write command (Inst + Address + data bytes, each data byte being exactly 8 bits), deselecting the device also triggers the Write cycle of this decoded command.
Figure 7. Hold condition activation
C
HOLD
Hold condition
Hold condition
The Hold condition starts when the Hold (HOLD) signal is driven low when Serial clock (C) is already low (as shown in
Figure 7. Hold condition activation
).
Figure 7. Hold condition activation
also shows what happens if the rising and falling edges are not timed to coincide with Serial clock (C) being low.
Status register
The Status register contains a number of status and control bits that can be read or set (as appropriate) by
register bits.
DS1356 - Rev 20 page 9/48
5.5
M95128-W M95128-R M95128-DF
Data protection and protocol control
Data protection and protocol control
The device features the following data protection mechanisms:
• Before accepting the execution of the Write and Write Status register instructions, the device checks whether the number of clock pulses comprised in the instructions is a multiple of eight.
• All instructions that modify data must be preceded by a Write enable (WREN) instruction to set the Write enable latch (WEL) bit.
•
•
The Block protect (BP1, BP0) bits in the Status register are used to configure part of the memory as read ‑ only.
The Write protect (W) signal is used to protect the Block protect (BP1, BP0) bits in the Status register.
For any instruction to be accepted, and executed, Chip select (S) must be driven high after the rising edge of
Serial clock (C) for the last bit of the instruction, and before the next rising edge of Serial clock (C).
Two points to note in the previous sentence:
• The “last bit of the instruction” can be the eighth bit of the instruction code, or the eighth bit of a data byte, depending on the instruction (except for Read Status register (RDSR) and Read (READ) instructions).
• The “next rising edge of Serial clock (C)” might (or might not) be the next bus transaction for some other device on the SPI bus.
Status register bits
BP1 BP0
1
1
0
0
0
1
0
1
Table 3. Write-protected block size
Protected block
None
Upper quarter
Upper half
Whole memory
Protected array addresses
None
3000h - 3FFFh
2000h - 3FFFh
0000h - 3FFFh plus Identification Page
DS1356 - Rev 20 page 10/48
M95128-W M95128-R M95128-DF
Instructions
6
Instructions
Each command is composed of bytes (MSBit transmitted first), initiated with the instruction byte, as summarized
If an invalid instruction is sent (one not contained in
), the device automatically enters in a Wait state until deselected.
Table 4. Instruction set
Instruction
WREN
WRDI
RDSR
WRSR
READ
WRITE
RDID
LID
Write enable
Write disable
Read Status register
Write Status register
Read from Memory array
Write to Memory array
Read Identification page
Write Identification page
Description
Reads the Identification page lock status
Locks the Identification page in read-only mode
1. Instruction available only for the M95128-D device.
Instruction format
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
1000 0011
1000 0010
1000 0011
1000 0010
For read and write commands to memory array and Identification page the address is defined by two bytes as explained in
.
Instruction
READ or WRITE
RDID or WRID
RDLS or LID
Note: b15 x b14 x
0
0
0
0
Table 5. Significant bits within the address bytes b13
MSB address byte b12 b11 b10 b9 b8 b7 b6 b5
LSB address byte b4 b3 b2
A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 b1 b0
A2 A1 A0
0
0
A: Significant address bit.
x: bit is Don’t care.
0
0
0
0
0
1
0
0
0
0
0
0
0 A5 A4 A3 A2 A1 A0
0 0 0 0 0 0 0
DS1356 - Rev 20 page 11/48
6.1
M95128-W M95128-R M95128-DF
Write enable (WREN)
Write enable (WREN)
The Write enable latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to do this is to send a Write enable instruction to the device.
As shown in Figure 8. Write enable (WREN) sequence
, to send this instruction to the device, Chip select (S) is driven low, and the bits of the instruction byte are shifted in, on Serial data input (D). The device then enters a wait state. It waits for the device to be deselected by Chip select (S) being driven high.
Figure 8. Write enable (WREN) sequence
S
0 1 2 3 4 5 6 7
C
Instruction
D
High impedance
Q
MS41478V1
DS1356 - Rev 20 page 12/48
6.2
M95128-W M95128-R M95128-DF
Write disable (WRDI)
Write disable (WRDI)
One way of resetting the Write enable latch (WEL) bit is to send a Write disable instruction to the device.
instruction byte are shifted in, on Serial data input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip select (S) being driven high.
•
•
The Write enable latch (WEL) bit, in fact, becomes reset by any of the following events:
• Power-up
•
WRDI instruction execution
WRSR instruction completion
WRITE instruction completion.
Figure 9. Write disable (WRDI) sequence
S
0 1 2 3 4 5 6 7
C
Instruction
D
High Impedance
Q
DS1356 - Rev 20 page 13/48
M95128-W M95128-R M95128-DF
Read Status register (RDSR)
6.3
6.3.1
6.3.2
6.3.3
Read Status register (RDSR)
The Read Status register (RDSR) instruction is used to read the Status register. The Status register may be read at any time, even while a Write or Write Status register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write in progress (WIP) bit before sending a new instruction to the device. It is also possible to read the Status register continuously, as shown in
Figure 10. Read Status register
.
Figure 10. Read Status register (RDSR) sequence
S
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
C
Instruction
D
Q
High impedance
Status Register Out Status Register Out
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSB MSB
7
MS47548V1
The status and control bits of the Status register are detailed in the following subsections.
WIP bit
The Write in progress (WIP) bit indicates whether the memory is busy with a Write or Write Status Register cycle.
When set to 1, such a cycle is in progress, when reset to 0, no such cycle is in progress.
•
•
WEL bit
The Write enable latch (WEL) bit indicates the status of the internal Write enable latch. When set to 1, the internal
Write enable latch is set. When set to 0, the internal Write enable latch is reset, and no Write or Write Status
Register instruction is accepted.
The WEL bit is returned to its reset state by the following events:
• Power-up
• Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Write (WRITE) instruction completion
BP1, BP0 bits
The Block protect (BP1, BP0) bits are non volatile. They define the size of the area to be software-protected against Write instructions. These bits are written with the Write Status register (WRSR) instruction. When one or both of the Block protect (BP1, BP0) bits is set to 1, the relevant memory area (as defined in
Table 3. Writeprotected block size
) becomes protected against Write (WRITE) instructions. The Block protect (BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set.
DS1356 - Rev 20 page 14/48
M95128-W M95128-R M95128-DF
Write Status register (WRSR)
6.3.4
6.4
SRWD bit
The Status register Write Disable (SRWD) bit is operated in conjunction with the Write protect (W) signal. The
Status register Write Disable (SRWD) bit and Write protect (W) signal enable the device to be put in the Hardware
Protected mode (when the Status register Write Disable (SRWD) bit is set to 1, and Write protect (W) is driven low). In this mode, the non-volatile bits of the Status register (SRWD, BP1, BP0) become read-only bits and the
Write Status register (WRSR) instruction is no longer accepted for execution.
Table 6. Status register format b7
SRWD 0 0 0 BP1 BP0 WEL b0
WIP
Status register Write protect
Block protect bits
Write enable latch bit
Write in progress bit
Write Status register (WRSR)
The Write Status register (WRSR) instruction is used to write new values to the Status register. Before it can be accepted, a Write enable (WREN) instruction must have been previously executed.
The Write Status register (WRSR) instruction is entered by driving Chip select (S) low, followed by the instruction code, the data byte on Serial Data input (D) and Chip select (S) driven high. Chip select (S) must be driven high after the rising edge of Serial clock (C) that latches in the eighth bit of the data byte, and before the next rising edge of Serial clock (C). Otherwise, the Write Status register (WRSR) instruction is not executed.
The instruction sequence is shown in
Figure 11. Write Status register (WRSR) sequence
S
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
C
D
Instruction Status Register In
7 6 5 4 3 2 1 0
MSB
High impedance
Q
MS47556V1
Driving the Chip select (S) signal high at a byte boundary of the input data triggers the self-timed Write cycle that takes t
W
to complete (as specified in AC tables in Section 9 DC and AC parameters
).
While the Write Status register cycle is in progress, the Status register may still be read to check the value of the
Write in progress (WIP) bit: the WIP bit is 1 during the self-timed Write cycle t
W
, and 0 when the Write cycle is complete. The WEL bit (Write enable latch) is also reset at the end of the Write cycle t
W
.
DS1356 - Rev 20 page 15/48
DS1356 - Rev 20
M95128-W M95128-R M95128-DF
Write Status register (WRSR)
The Write Status register (WRSR) instruction enables the user to change the values of the BP1, BP0 and SRWD bits:
• The Block protect (BP1, BP0) bits define the size of the area that is to be treated as read-only, as defined in
Table 3. Write-protected block size .
• The SRWD (Status register Write Disable) bit, in accordance with the signal read on the Write protect pin
(W), enables the user to set or reset the Write protection mode of the Status register itself, as defined in
not executed.
The contents of the SRWD and BP1, BP0 bits are updated after the completion of the WRSR instruction, including the t
W
Write cycle.
The Write Status register (WRSR) instruction has no effect on the b6, b5, b4, b1, b0 bits in the Status register.
Bits b6, b5, b4 are always read as 0.
Table 7. Protection modes
W signal
1
0
1
0
SRWD bit
0
0
1
1
Mode
Softwareprotected
(SPM)
Hardwareprotected
(HPM)
Write protection of the Status register
Memory content
Protected
Status register is writable (if the WREN instruction has set the WEL bit).
The values in the BP1 and BP0 bits can be changed.
Status register is Hardware write-protected.
The values in the BP1 and BP0 bits cannot be changed.
Writeprotected
Writeprotected
Ready to accept
Write instructions
Ready to accept
Write instructions
1. As defined by the values in the Block protect (BP1, BP0) bits of the Status register. See
Table 3. Write-protected block size
.
The protection features of the device are summarized in Table 7
.
When the Status register Write Disable (SRWD) bit in the Status register is 0 (its initial delivery state), it is possible to write to the Status register (provided that the WEL bit has previously been set by a WREN instruction), regardless of the logic level applied on the Write protect (W) input pin.
When the Status register Write Disable (SRWD) bit in the Status register is set to 1, two cases should be considered, depending on the state of the Write protect (W) input pin:
• If Write protect (W) is driven high, it is possible to write to the Status register (provided that the WEL bit has previously been set by a WREN instruction).
• If Write protect (W) is driven low, it is not possible to write to the Status register even if the WEL bit has previously been set by a WREN instruction. (Attempts to write to the Status register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory area, which are Softwareprotected (SPM) by the Block protect (BP1, BP0) bits in the Status register, are also hardware-protected against data modification.
Regardless of the order of the two events, the Hardware-protected mode (HPM) can be entered by:
• either setting the SRWD bit after driving the Write protect (W) input pin low,
• or driving the Write protect (W) input pin low after setting the SRWD bit.
Once the Hardware-protected mode (HPM) has been entered, the only way of exiting it is to pull high the Write protect (W) input pin.
If the Write protect (W) input pin is permanently tied high, the Hardware-protected mode (HPM) can never be activated, and only the Software-protected mode (SPM), using the Block protect (BP1, BP0) bits in the Status register, can be used.
page 16/48
M95128-W M95128-R M95128-DF
Read from Memory array (READ)
6.5
Note:
Read from Memory array (READ)
, to send this instruction to the device, Chip select (S) is first driven low. The bits of the instruction byte and address bytes are then shifted in, on Serial data input (D). The address is loaded into an internal address register, and the byte of data at that address is shifted out, on Serial data output (Q).
Figure 12. Read from Memory array (READ) sequence
S
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction 16-Bit Address
D
Q
High Impedance
15 14 13
MSB
3 2 1 0
Data Out 1
7 6 5 4 3 2
MSB
1 0 7
Data Out 2
Depending on the memory size, as shown in Table 5. Significant bits within the address bytes
, the most significant address bits are Don’t care.
If Chip select (S) continues to be driven low, the internal address register is incremented automatically, and the byte of data at the new address is shifted out.
When the highest address is reached, the address counter rolls over to zero, allowing the Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a single READ instruction.
The Read cycle is terminated by driving Chip select (S) high. The rising edge of the Chip select (S) signal can occur at any time during the cycle.
The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.
DS1356 - Rev 20 page 17/48
M95128-W M95128-R M95128-DF
Write to Memory array (WRITE)
6.6
Note:
Note:
Write to Memory array (WRITE)
, to send this instruction to the device, Chip select (S) is first driven low. The bits of the instruction byte, address byte, and at least one data byte are then shifted in, on Serial data input (D).
The instruction is terminated by driving Chip select (S) high at a byte boundary of the input data. The self-timed
Write cycle, triggered by the Chip select (S) rising edge, continues for a period t
W
(as specified in AC
to 0.
Figure 13. Byte Write (WRITE) sequence
S
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
C
D
Instruction 16-bit address
15 14 13 3 2 1 0
Data byte
7 6 5 4 3 2 1 0
High impedance
Q
Depending on the memory size, as shown in Table 5. Significant bits within the address bytes
, the most significant address bits are Don’t care.
In the case of
indicating that the instruction is being used to write a single byte. However, if Chip select (S) continues to be driven low (as shown in
Figure 14 ), the next byte of input data is shifted in, so that more than a single byte,
starting from the given address towards the end of the same page, can be written in a single internal Write cycle.
Each time a new data byte is shifted in, the least significant bits of the internal address counter are incremented. If more bytes are sent than will fit up to the end of the page, a condition known as “roll-over” occurs. In case of rollover, the bytes exceeding the page size are overwritten from location 0 of the same page.
•
•
The instruction is not accepted, and is not executed, under the following conditions:
• if the Write enable latch (WEL) bit has not been set to 1 (by executing a Write enable instruction just before),
• if a Write cycle is already in progress, if the device has not been deselected, by driving high Chip select (S), at a byte boundary (after the eighth bit, b0, of the last data byte that has been latched in), if the addressed page is in the region protected by the Block protect (BP1 and BP0) bits.
The self-timed write cycle t
W
is internally executed as a sequence of two consecutive events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is read as “0” and a programmed bit is read as
“1”.
DS1356 - Rev 20 page 18/48
DS1356 - Rev 20
M95128-W M95128-R M95128-DF
Write to Memory array (WRITE)
Figure 14. Page Write (WRITE) sequence
S
C
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
Instruction 16-Bit Address Data Byte 1
15 14 13 3 2 1 0 7 6 5 4 3 2 1 0
D
S
C
D
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Data Byte 2 Data Byte 3 Data Byte N
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 6 5 4 3 2 1 0
1.
significant address bits are Don’t care.
page 19/48
M95128-W M95128-R M95128-DF
Read Identification page (available only in M95128-D devices)
6.6.1
6.7
Cycling with error correction code (ECC x4)
M95128 devices offer an error correction code (ECC) logic. The ECC is an internal logic function transparent for the SPI communication protocol.
The ECC logic is implemented on each group of four EEPROM bytes (A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer.). Inside a group, if a single bit out of the four bytes happens to be erroneous during a Read operation, the ECC detects this bit and replaces it with the correct value.
The read reliability is therefore much improved.
Even if the ECC function is performed on groups of four bytes, a single byte can be written/cycled independently.
In this case, the ECC function also writes/cycles the three other bytes located in the same group. As a consequence, the maximum cycling budget is defined at group level and the cycling can be distributed over the four bytes of the group: the sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain below the maximum value defined in
Table 13. Cycling performance by groups of four bytes
.
Read Identification page (available only in M95128-D devices)
The Identification page (64 bytes) is an additional page that can be written and (later) permanently locked in
Read-only mode.
This page is read with the Read Identification page instruction (see Table 4. Instruction set
). The Chip select signal (S) is first driven low, the bits of the instruction byte and address bytes are then shifted in, on Serial data input (D). Address bit A10 must be 0, upper address bits are Don't care, and the data byte pointed to by the lower address bits [A5:A0] is shifted out on Serial data output (Q). If Chip select (S) continues to be low, the internal address register is automatically incremented, and the byte of data at the new address is shifted out.
The number of bytes to read in the ID page must not exceed the page boundary, otherwise unexpected data are read (e.g. when reading the ID page from location 24d, the number of bytes must be lower than or equal to 40d, as the ID page boundary is 64 bytes).
The read cycle is terminated by driving Chip select (S) high. The rising edge of the Chip select (S) signal can occur at any time during the cycle. The first byte addressed can be any byte within any page.
The instruction is not accepted, and is not executed, if a write cycle is currently in progress.
Figure 15. Read Identification page sequence
S
C
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
Instruction 16-bit address
D
Q
High impedance
15
MSB
14 13 3 2 1 0
Data Out 1
7 6 5 4 3
MSB
2 1 0
Data Out 2
7
DS1356 - Rev 20 page 20/48
6.8
6.9
M95128-W M95128-R M95128-DF
Write Identification page (available only in M95128-D devices)
Write Identification page (available only in M95128-D devices)
The Identification page (64 bytes) is an additional page that can be written and (later) permanently locked in
Read-only mode.
). The Chip select signal (S) is first driven low. The bits of the instruction byte, address bytes, and at least one data byte are then shifted in on Serial data input (D). Address bit A10 must be 0, upper address bits are Don't care, the lower address bits [A5:A0] define the byte address within the Identification page. The instruction sequence is shown in
Figure 16. Write Identification page sequence
.
Figure 16. Write Identification page sequence
S
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction 16-bit address Data byte
D
15 14 13 3 2 1 0 7 6 5 4 3 2 1 0
High impedance
Q
Read Lock status (available only in M95128-D devices)
The Read Lock status instruction (see Table 4. Instruction set
) is used to check whether the Identification page is locked or not in Read-only mode. The Read Lock status sequence is defined with the Chip select (S) first driven low. The bits of the instruction byte and address bytes are then shifted in on Serial data input (D). Address bit A10 must be 1, all other address bits are Don't Care. The Lock bit is the LSB (least significant bit) of the byte read on
Serial data output (Q). It is at “1” when the lock is active and at “0” when the lock is not active. If Chip select (S) continues to be driven low, the same data byte is shifted out. The read cycle is terminated by driving Chip select
(S) high.
The instruction sequence is shown in
Figure 17. Read Lock status sequence
.
Figure 17. Read Lock status sequence
S
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction 16-bit address
D
Q
High impedance
15 14 13
MSB
3 2 1 0
7 6 5 4 3
MSB
Data Out 1
2 1 0
Data Out 2
7
DS1356 - Rev 20 page 21/48
M95128-W M95128-R M95128-DF
Lock ID (available only in M95128-D devices)
6.10
Lock ID (available only in M95128-D devices)
The Lock ID instruction permanently locks the Identification page in read-only mode. Before this instruction can be accepted, a Write enable (WREN) instruction must have been executed.
The Lock ID instruction is issued by driving Chip select (S) low, sending the instruction code, the address and a data byte on Serial data input (D), and driving Chip select (S) high. In the address sent, A10 must be equal to 1, all other address bits are Don't Care. The data byte sent must be equal to the binary value xxxx xx1x, where x =
Don't Care.
Chip select (S) must be driven high after the rising edge of Serial clock (C) that latches in the eighth bit of the data byte, and before the next rising edge of Serial clock (C). Otherwise, the Lock ID instruction is not executed.
Driving Chip select (S) high at a byte boundary of the input data triggers the self-timed write cycle whose duration is t
W
(as specified in AC characteristics in
Section 9 DC and AC parameters
). The instruction sequence is shown
in Figure 18. Lock ID sequence .
•
•
The instruction is discarded, and is not executed, under the following conditions:
• If a Write cycle is already in progress
•
If Block protect bits (BP1,BP0) = (1,1)
If a rising edge on Chip select (S) happens outside of a byte boundary.
If the Write enable latch (WEL) bit has not been set to 1 (by executing a Write enable instruction just before)
Figure 18. Lock ID sequence
S
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction 16-bit address Data byte
D
15 14 13 3 2 1 0 7 6 5 4 3 2 1 0
High impedance
Q
DS1356 - Rev 20 page 22/48
7
7.1
7.2
M95128-W M95128-R M95128-DF
Power-up and delivery state
Power-up and delivery state
Power-up state
•
•
After power-up, the device is in the following state:
• Standby power mode
• deselected (after power-up, a falling edge is required on Chip select (S) before any instructions can be started) not in the Hold condition the Write enable latch (WEL) is reset to 0
• Write in progress (WIP) is reset to 0.
The SRWD, BP1 and BP0 bits of the Status register are unchanged from the previous power-down (they are nonvolatile bits).
Initial delivery state
The device is delivered with the memory array and Identification page bits set to all 1s (each byte = FFh). The
Status register Write Disable (SRWD) and Block protect (BP1 and BP0) bits are initialized to 0.
DS1356 - Rev 20 page 23/48
8
M95128-W M95128-R M95128-DF
Maximum ratings
Maximum ratings
Stressing the device outside the ratings listed in
may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 8. Absolute maximum ratings
Symbol
T
AMB
T
STG
T
LEAD
V
O
V
I
V
CC
I
OL
I
OH
V
ESD
Ambient operating temperature
Storage temperature
Output voltage
Input voltage
Supply voltage
DC output current (Q = 0)
DC output current (Q = 1)
Parameter
Lead temperature during soldering
Electrostatic discharge voltage (human body model)
Min.
–40
–65
-
-
-
Max.
130
150
–0.50
–0.50
–0.50
V
CC
+ 0.6
6.5
6.5
5
5
4000
Unit
°C
V mA
V
1. Compliant with JEDEC standard J-STD-020E (for small-body, Sn-Pb or Pb free assembly), the ST ECOPACK 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS directive 2011/65/EU of July
2011).
2. Positive and negative pulses applied on different combinations of pin connections, according to AEC-Q100-002 (compliant with ANSI/ESDA/JEDEC JS-001-2012, C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω).
DS1356 - Rev 20 page 24/48
9
M95128-W M95128-R M95128-DF
DC and AC parameters
DC and AC parameters
This section summarizes the operating conditions and the DC/AC characteristics.
Symbol
V
CC
T
A
Table 9. Operating conditions (M95128-W, device grade 6)
Parameter
Supply voltage
Ambient operating temperature
Min.
2.5
–40
Max.
5.5
85
Unit
V
°C
Symbol
V
CC
T
A
Table 10. Operating conditions (M95128-R, device grade 6)
Parameter
Supply voltage
Ambient operating temperature
Min.
1.8
-40
Max.
5.5
85
Unit
V
°C
Symbol
V
CC
T
A
Table 11. Operating conditions (M95128-DF, device grade 6)
Parameter
Supply voltage
Ambient operating temperature
Min.
1.7
–40
Max.
5.5
85
Unit
V
°C
Symbol
C
L
-
-
-
Table 12. AC measurement conditions
Parameter
Load capacitance
Input rise and fall times
Input pulse voltages
Input and output timing references voltages
Min.
-
Max.
100
50
0.2 V
CC
to 0.8 V
CC
0.3 V
CC
to 0.7 V
CC
Unit pF ns
V
V
Input Levels
0.8 ₓ V
CC
Figure 19. AC measurement I/O waveform
Input and Output
Timing Reference Levels
0.7 ₓ V
CC
0.3 ₓ V
CC
0.2 ₓ V
CC
DS1356 - Rev 20 page 25/48
DS1356 - Rev 20
M95128-W M95128-R M95128-DF
DC and AC parameters
Table 13. Cycling performance by groups of four bytes
Symbol
N cycle
Parameter
Write cycle endurance
Test condition
TA ≤ 25 °C, V
CC
(min) < V
CC
< V
CC
(max)
TA = 85 °C, V
CC
(min) < V
CC
< V
CC
(max)
Min.
-
-
Max.
4,000,000
1,200,000
Unit
1. The Write cycle endurance is defined for groups of four data bytes located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where
N is an integer. The Write cycle endurance is defined by characterization and qualification.
2. A Write cycle is executed when either a Page write, a Byte write, a WRSR, a WRID or an LID instruction is decoded. When using the Byte write, the Page write or the WRID instruction, refer also to
Section 6.6.1 Cycling with error correction code
.
Table 14. Memory cell data retention
Parameter
Test condition
TA = 55 °C
Min.
200
1. The data retention behaviour is checked in production, while the 200-year limit is defined from characterization and qualification results.
Unit
Year
Table 15. Capacitance
Symbol
C
OUT
C
IN
Parameter
Output capacitance (Q)
Input capacitance (D)
Input capacitance (other pins)
1. Sampled only, not 100% tested, at T
A
= 25 °C and a frequency of 5 MHz
V
OUT
= 0 V
V
IN
= 0 V
V
IN
= 0 V
Min.
-
-
-
Max.
8
8
6
Unit pF pF pF page 26/48
DS1356 - Rev 20
M95128-W M95128-R M95128-DF
DC and AC parameters
Table 16. DC characteristics (M95128-W, device grade 6)
Symbol
I
CC0
I
I
I
LI
I
LO
CC
CC1
Parameter
Input leakage current
Output leakage current
Supply current (Read)
Supply current (Write)
Supply current
(Standby)
Test conditions specified in
V
IN
= V
SS
or V
CC
S = V
CC
, V
OUT
= V
SS
or V
CC
V
CC
= 2.5 V, C = 0.1 V
CC
/ 0.9 V
CC at 10 MHz, Q = open
V
CC
= 5.5 V, C = 0.1 V
CC
/ 0.9 V
CC at 20 MHz, Q = open
-
During t
W
, S = V
CC
,
2.5 V < V
CC
< 5.5 V
S = V
CC
, V
CC
= 5.5 V,
V
IN
= V
SS
or V
CC
S = V
CC
, V
CC
= 2.5 V,
V
IN
= V
SS
or V
CC
V
IL
V
V
V
IH
OL
OH
Input low voltage
Input high voltage
Output low voltage
Output high voltage
-
V
CC
= 2.5 V and I
OL
= 1.5 mA or
V
CC
= 5 V and I
OL
= 2 mA
V
CC
= 2.5 V and I
OH
= –0.4 mA or
V
CC
= 5 V and I
OH
= –2 mA
1. Characterized only, not tested in production.
Min.
-
-
-
-
-
-
-
Max.
Unit
± 2 µA
± 2 µA
2
5
3
3
2
–0.45
0.3 V
CC
0.7 V
CC
V
CC
+1
-
0.8 V
CC
0.4
mA mA
µA
V
V
V
V
Table 17. DC characteristics (M95128-R, device grade 6)
Symbol
I
I
I
LI
LO
CC
Parameter
Supply current (Read)
Test conditions in addition to those defined in
and
Input leakage current V
IN
= V
SS
or V
CC
Output leakage current S = V
CC
, voltage applied on Q = V
SS
or V
CC
V
CC
= 1.8 V, C = 0.1 V
CC or 0.9 V
CC at 5 MHz , Q = open
Min
-
-
-
Max
± 2
± 2
2
Unit
µA
µA mA
I
CC0
Supply current (Write) V
CC
= 1.8 V , during t
W
, S = V
CC
I
CC1
Supply current
(Standby)
V
CC
= 1.8 V, S = V
CC
, V
IN
= V
SS
or V
CC
V
IL
V
IH
V
OL
V
OH
Input low voltage
Input high voltage
Output low voltage
Output high voltage
I
I
1.8 V ≤ V
1.8 V ≤ V
OL
OH
CC
CC
< 2.5 V
< 2.5 V
= 0.15 mA, V
= –0.1 mA, V
CC
CC
= 1.8 V
= 1.8 V
-
-
-
0.8 V
CC
3
1
–0.45
0.25 V
CC
0.75 V
CC
V
CC
+1
0.3
mA
µA
1. If the application uses the M95128-R with 2.5 V < V
CC
< 5.5 V and -40 °C < T
A
< +85 °C, refer to
rather then the above table.
2. Characterized only, not tested in production.
V
V
V
V page 27/48
M95128-W M95128-R M95128-DF
DC and AC parameters
Table 18. DC characteristics (M95128-DF, device grade 6)
Symbol
I
I
I
LI
LO
CC
I
CC0
I
CC1
V
IL
V
IH
V
OL
V
OH
Parameter
Input leakage current
Output leakage current
Supply current (Read)
Supply current (Write)
Supply current (Standby)
Input low voltage
Input high voltage
Output low voltage
Output high voltage
V
IN
= V
SS
or V
CC
S = V
CC
, voltage applied on Q = V
SS
or V
CC
V
CC
= 1.7 V, C = 0.1 V
CC
or 0.9 V
CC
, at 5 MHz, Q = open
V
CC
= 1.7 V, during t
W
, S = V
V
CC
= 1.7 V, S = V
CC
, V
IN
= V
SS
or V
CC
1.7 V ≤ V
CC
< 2.5 V
1.7 V ≤ V
CC
< 2.5 V
I
OL
= 0.15 mA, V
CC
= 1.7 V
I
OH
= –0.1 mA, V
CC
= 1.7 V
CC
Min.
-
-
-
-
-
–0.45
0.75 V
-
0.8 V
CC
CC
Max.
± 2
± 2
2
3
1
0.25 V
CC
V
CC
+1
0.3
-
Unit
µA
µA mA mA
µA
V
V
V
V
1. If the application uses the M95128-DF devices at 2.5 V ≤ V
CC
1.8 V ≤ V
CC
< 2.5 V and –40 °C ≤ TA ≤ +85 °C, refer to
Table 17. DC characteristics (M95128-R, device grade 6) , rather
than to the above table.
2. Characterized only, not tested in production.
DS1356 - Rev 20 page 28/48
DS1356 - Rev 20
M95128-W M95128-R M95128-DF
DC and AC parameters
Table 19. AC characteristics (M95128-W, device grade 6)
Test conditions specified in
t
DVCH t
CHDX t
HHCH t
HLCH t
CLHL t
CLHH t
SHQZ
t
CLQV t
CLQX t
HHQV t
HLQZ
t
W
Symbol f
C t
SLCH t
SHCH t
SHSL t
CHSH t
CHSL t
CH
t
CL
t
CLCH
t
CHCL
t t t
Alt.
f
SCK t
CSS1 t
CSS2 t
CS t
CSH t
CLH
CLL
RC
FC t
DSU t
DH
-
-
-
-
t
DIS t
V t
HO t
LZ t
HZ t
WC
Clock frequency
S active setup time
S not active setup time
S deselect time
S active hold time
S not active hold time
Clock high time
Clock low time
Clock rise time
Clock fall time
Data in setup time
Data in hold time
Parameter
Clock low hold time after HOLD not active
Clock low hold time after HOLD active
Clock low setup time before HOLD active
Clock low setup time before HOLD not active
Output disable time
Clock low to output valid
Output hold time
HOLD high to output valid
HOLD low to output High-Z
Write time
1. t
CH
+ t
CL
must never be less than the shortest possible clock period, 1 / f
C
(max).
2. Characterized only, not tested in production.
V ≥ 2.5V
V
CC
≥ 4.5V
Min.
Max.
Min.
Max.
D.C.
10 D.C.
20
30
30
40
30
30
40
40
-
-
10
10
30
30
0
0
-
-
0
-
-
-
-
-
-
-
-
-
-
2
2
-
-
-
-
40
40
-
-
-
40
40
5
15
15
20
15
15
20
20
-
-
5
10
15
15
0
0
-
-
0
-
-
-
-
-
-
-
-
-
-
2
2
-
-
-
20
20
-
20
20
5
-
-
-
Unit ns ns
µs
µs
MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms page 29/48
DS1356 - Rev 20
M95128-W M95128-R M95128-DF
DC and AC parameters
Table 20. AC characteristics (M95128-R, device grade 6)
Symbol Alt.
Test conditions specified in
Parameter
V
CC
≥ 1.8V
V
CC
≥ 2.5V
V
CC
≥ 4.5V
Min.
Max.
Min.
Max.
Min.
Max.
5 10 20 f
C t
SLCH t
SHCH t
SHSL t
CHSH t
CHSL t
CH
t
CL
t
CLCH
t
CHCL
t
DVCH t
CHDX t
HHCH t
HLCH t
CLHL t
CLHH t
SHQZ
t
CLQV t
CLQX t
HHQV t
HLQZ
t
W t t t t f t
CSS1
CSS2 t t t
SCK
CS
CSH
-
CLH
CLL
RC
FC t
DSU t
DH
-
-
-
t
DIS t
V t
HO t
LZ t
HZ t
WC
Clock frequency
S active setup time
S not active setup time
S deselect time
S active hold time
S not active hold time
Clock high time
Clock low time
Clock rise time
Clock fall time
Data in setup time
Data in hold time
Clock low hold time after HOLD not active
Clock low hold time after HOLD active
Clock low setup time before HOLD active
Clock low setup time before HOLD not active
Output disable time
Clock low to output valid
Output hold time
HOLD high to output valid
HOLD low to output High-Z
Write time
60
60
90
60
60
80
80
20
20
60
60
0
0
-
-
-
0
-
-
-
-
1. t
CH
+ t
CL
must never be less than the shortest possible clock period, 1 / f
C
(max).
2. Characterized only, not tested in production.
-
-
-
-
-
-
-
2
2
-
-
-
-
-
-
80
80
-
80
80
5
30
30
40
30
30
40
40
-
-
10
10
30
30
0
0
-
-
0
-
-
-
-
-
-
-
-
-
-
2
2
-
-
-
-
-
-
40
40
-
40
40
5
15
15
20
15
15
20
20
-
-
5
10
15
15
0
0
-
-
0
-
-
-
20
-
-
-
-
-
-
-
-
-
-
-
-
2
2
-
-
20
20
20
5
Unit ns
µs
µs ns ns ns ns
MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ms page 30/48
DS1356 - Rev 20
M95128-W M95128-R M95128-DF
DC and AC parameters
Table 21. AC characteristics (M95128-DF, device grade 6)
Symbol Alt.
Test conditions specified in
Parameter
V
CC
≥ 1.7V
V
CC
≥ 2.5V
V
CC
≥ 4.5V
Min.
Max.
Min.
Max.
Min.
Max.
5 10 20 t
CL
t
CLCH
t
CHCL t
DVCH t
CHDX t
HHCH t
HLCH t
CLHL t
CLHH t
SHQZ
t
CLQV t
CLQX t
HHQV t
HLQZ
t
W f
C t
SLCH t
SHCH t
SHSL t
CHSH t
CHSL t
CH
t t t t f t
CSS1
CSS2 t t t
SCK
CS
CSH
-
CLH
CLL
RC
FC t
DSU t
DH
-
-
-
t
DIS t
V t
HO t
LZ t
HZ t
WC
Clock frequency
S active setup time
S not active setup time
S deselect time
S active hold time
S not active hold time
Clock high time
Clock low time
Clock rise time
Clock fall time
Data in setup time
Data in hold time
Clock low hold time after HOLD not active
Clock low hold time after HOLD active
Clock low setup time before HOLD active
Clock low setup time before HOLD not active
Output disable time
Clock low to output valid
Output hold time
HOLD high to output valid
HOLD low to output High-Z
Write time
60
60
90
60
60
80
80
20
20
60
60
0
0
-
-
-
0
-
-
-
-
1. t
CH
+ t
CL
must never be less than the shortest possible clock period, 1 / f
C
(max).
2. Characterized only, not tested in production.
-
-
-
-
-
-
-
2
2
-
-
-
-
-
-
80
80
-
80
80
5
30
30
40
30
30
40
40
-
-
10
10
30
30
0
0
-
-
0
-
-
-
-
-
-
-
-
-
-
2
2
-
-
-
-
-
-
40
40
-
40
40
5
15
15
20
15
15
20
20
-
-
5
10
15
15
0
0
-
-
0
-
-
-
2
20
-
-
-
-
-
-
-
-
-
-
-
2
-
-
-
20
20
20
5
Unit ns ns ns ns
µs
µs ns ns ns ns ns ns ns ms ns ns ns ns
MHz ns ns ns page 31/48
DS1356 - Rev 20
S
C
Q t
CLQV t
CLQX
D
ADDR
LSB IN
M95128-W M95128-R M95128-DF
DC and AC parameters
Figure 20. Serial input timing
S
C t
CHSL
D
Q t
SLCH t
DVCH
MSB IN t
CHCL t
CHDX
High impedance t
CH t
CL t
CHSH
LSB IN t
CLCH t
SHSL t
SHCH
Figure 21. Hold timing
S t
HLCH
C t
CLHL t
HLQZ t
HHCH t
CLHH t
HHQV
Q
HOLD t
CLCH
Figure 22. Serial output timing t
CH t
CHCL t
CL t
QLQH t
QHQL t
SHSL t
SHQZ page 32/48
M95128-W M95128-R M95128-DF
Package information
10
10.1
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.
SO8N package information
SO8N is an 8-lead, 4.9 x 6 mm, plastic small outline, 150 mils body width, package.
Figure 23. SO8N – Outline h x 45˚
A2 A c ccc b e
D
0.25 mm
GAUGE PLANE k
8
1
E1 E
A1
L1
L
1.
Drawing is not to scale.
Table 22. SO8N – Mechanical data
Symbol
E
E1 e h c
D
A
A1
A2 b k
L
L1 ccc
Min.
-
0.100
1.250
0.280
0.170
4.800
5.800
3.800
-
0.250
0°
0.400
-
millimeters
Typ.
-
-
-
-
-
4.900
6.000
3.900
1.270
-
-
-
1.040
-
Max.
1.750
0.250
-
0.480
0.230
5.000
6.200
4.000
-
0.500
8°
1.270
-
0.100
1. Values in inches are converted from mm and rounded to four decimal digits.
Min.
-
0.0039
0.0492
0.0110
0.0067
0.1890
0.2283
0.1496
-
0.0098
0°
0.0157
-
inches
-
0.1929
0.2362
0.1535
0.0500
-
-
-
0.0409
-
Typ.
-
-
-
-
Max.
0.0689
0.0098
-
0.0189
0.0091
0.1969
0.2441
0.1575
-
0.0197
8°
0.0500
-
0.0039
DS1356 - Rev 20 page 33/48
M95128-W M95128-R M95128-DF
SO8N package information
Figure 24. SO8N - Recommended footprint
0.6 (x8)
1.
Dimensions are expressed in millimeters.
1.27
DS1356 - Rev 20 page 34/48
M95128-W M95128-R M95128-DF
TSSOP8 package information
10.2
TSSOP8 package information
TSSOP8 is an 8-lead thin shrink small outline, 3 x 6.4 mm, 0.65 mm pitch, package.
Figure 25. TSSOP8 – Outline
D
8 5
E1 E
1 4
α
A1
CP
A
A2 b e
1.
Drawing is not to scale.
Table 23. TSSOP8 – Mechanical data
Symbol c
CP
D e
E
A
A1
A2 b
E1
L
L1
α
Min.
-
0.050
0.800
0.190
0.090
-
2.900
-
6.200
4.300
0.450
-
0° millimeters
Typ.
-
-
1.000
-
-
-
3.000
0.650
6.400
4.400
0.600
1.000
-
Max.
1.200
0.150
1.050
0.300
0.200
0.100
3.100
-
6.600
4.500
0.750
-
8°
1. Values in inches are converted from mm and rounded to four decimal digits.
0.1142
-
0.2441
0.1693
0.0177
-
0°
Min.
-
0.0020
0.0315
0.0075
0.0035
-
L1
L inches
0.1181
0.0256
0.2520
0.1732
0.0236
0.0394
-
Typ.
-
-
0.0394
-
-
c
0.1220
-
0.2598
0.1772
0.0295
-
8°
Max.
0.0472
0.0059
0.0413
0.0118
0.0079
0.0039
DS1356 - Rev 20 page 35/48
DS1356 - Rev 20
M95128-W M95128-R M95128-DF
TSSOP8 package information
Figure 26. TSSOP8 – Recommended footprint
2.3
1.0
7.0
0.65
1.
Dimensions are expressed in millimeters.
0.35
page 36/48
M95128-W M95128-R M95128-DF
UFDFPN8 (DFN8) package information
10.3
UFDFPN8 (DFN8) package information
UFDFPN8 is an 8-lead, 2 × 3 mm, 0.55 mm thickness ultra thin profile fine pitch dual flat package.
Figure 27. UFDFPN8 - Outline
N
D A B
Pin #1
ID marking
E ccc C
A
A1 eee C
Seating plane
Side view
A3
C
2x aaa C
1 2
Top view
L3
Pin #1
ID marking
1 2
D2 e b
2x aaa C
L1
E2
K
L
ND-1 x e
Bottom view
See Detail “A”
L L3
Datum A e/2 e
Detail “A”
Even terminal
L1
Terminal tip
1.
Maximum package warpage is 0.05 mm.
2.
Exposed copper is not systematic and can appear partially or totally according to the cross section.
3.
Drawing is not to scale.
4.
The central pad (the area E2 by D2 in the above illustration) must be either connected to V
SS
or left floating
(not connected) in the end application.
DS1356 - Rev 20 page 37/48
DS1356 - Rev 20
M95128-W M95128-R M95128-DF
UFDFPN8 (DFN8) package information
Table 24. UFDFPN8 - Mechanical data
Symbol
K
L
L1
L3 aaa bbb ccc ddd
A
A1 b
D
D2
E
E2 e
Min
0.450
0.000
0.200
0.300
0.300
-
0.300
-
-
-
-
1.900
1.200
2.900
1.200
-
millimeters
Typ
0.550
0.020
0.250
-
-
-
-
-
-
-
-
2.000
-
3.000
-
0.500
-
Max
0.600
0.050
0.300
2.100
1.600
3.100
1.600
-
-
0.500
0.150
-
0.150
0.100
0.100
0.050
0.080
Min
0.0177
0.0000
0.0079
0.0748
0.0472
0.1142
0.0472
0.0197
0.0118
0.0118
-
0.0118
-
-
-
-
-
Typ
0.0217
0.0008
0.0098
0.0787
-
-
-
-
-
-
-
-
-
-
0.1181
-
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from the terminal tip.
3. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from measuring.
Max
0.0236
0.0020
0.0118
0.0827
0.0630
0.1220
0.0630
-
0.0197
0.0059
-
0.0059
0.0039
0.0039
0.0020
0.0031
Figure 28. UFDFPN8 - Recommended footprint
1.400
0.500
0.300
0.600
1.200
1.300
1.
Dimensions are expressed in millimeters.
page 38/48
M95128-W M95128-R M95128-DF
WLCSP8 (CS) package information
10.4
WLCSP8 (CS) package information
WLCSP8 is a 8 bumps, 1.289 x 1.099 mm, 0.4 mm pitch wafer level chip scale package
Figure 29. WLCSP8 - Outline bbb Z
D
X Y
E
Detail A
F e3
Reference
Wafer back side
(4X) aaa
A2
A
Side view e2 e
H
G
Orientation
Bump side e1
Bump eee Z
A1
Ø
Ø ccc M ddd M
Z
Z b
X Y
Detail A
Rotated 90 °
Z
Seating plane
1.
Drawing is not to scale
2.
Primary datum Z and seating plane are defined by the spherical crowns of the bump.
3.
Bump position designation per JESD 95-1, SPP-010.
DS1356 - Rev 20 page 39/48
DS1356 - Rev 20
M95128-W M95128-R M95128-DF
WLCSP8 (CS) package information
Table 25. WLCSP8 - Mechanical data
Symbol aaa bbb ccc ddd eee e2 e3
F
G
H
A
A1
A2
D
E e e1
Min
0.500
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
millimeters
Typ
0.540
0.190
0.350
0.270
1.289
1.099
0.800
0.693
0.400
0.400
0.203
0.245
0.203
0.110
0.110
0.110
0.060
0.060
Max
0.580
-
-
-
1.309
1.119
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Min
0.0197
-
-
-
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
Figure 30. WLCSP8 - Recommended footprint inches
Typ
0.0213
0.0075
0.0138
0.0106
0.0507
0.0433
0.0315
0.0273
0.0157
0.0157
0.0080
0.0096
0.0080
0.0043
0.0043
0.0043
0.0024
0.0024
0.800
0.400
Max
0.0228
-
-
-
-
-
-
-
-
0.0515
0.0441
-
-
-
-
-
-
-
0.400
0.693
8 bumps x Ø 0.270
1.
Dimensions are expressed in millimeters.
page 40/48
M95128-W M95128-R M95128-DF
Ordering information
11
Note:
Ordering information
Table 26. Ordering information scheme
Example:
Device type
M95 = SPI serial access EEPROM
Device function
128 = 128 Kbit (16384 x 8)
Device family
Blank = Without Identification page
D = With additional Identification page
Operating voltage
W = V
CC
= 2.5 to 5.5 V
R = V
CC
= 1.8 to 5.5 V
F = V
CC
= 1.7 to 5.5 V
Package
MN = SO8 (150 mil width)
DW = TSSOP8 (169 mil width)
MC = UFDFPN8 (DFN8)
CS = WLCSP
Device grade
6 = Industrial temperature range, –40 to 85 °C
Device tested with standard test flow
Option
M95 blank = tube packing
T = Tape and reel packing
Plating technology
G or P = RoHS compliant and halogen-free (ECOPACK2®)
Process
/K = Manufacturing technology code
128 -D W MN 6 T P \K
1. All packages are ECOPACK2 ® (RoHS-compliant and free of brominated, chlorinated and antimony-oxide flame retardants).
2. These process letters appear on the device package (marking) and on the shipment box. Please contact your nearest ST
Sales Office for further information
Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST
Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity.
DS1356 - Rev 20 page 41/48
M95128-W M95128-R M95128-DF
Revision history
Table 27. Document revision history
Date
17-Feb-2009
12-Jan-2010
Revision
11
12
Changes
Section 3.8: Supply voltage (VCC) and Section 5.4: Write Status Register (WRSR) updated.
Note added to Section 5.6: Write to Memory Array (WRITE).
ICC modified in Table 12: DC characteristics (M95128, device grade 3).
VRES added to DC characteristics tables 12, 20, 14 and 23.
Note added to Table 36: AC characteristics (M95080-R, M95080-DR device grade 6).
Note added below Figure 20: UFDFPN8, 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, outline.
Small text changes.
Section 5.6.1: ECC (error correction code) and write cycling modified (applies to all devices).
T
LEAD
, I
OL
and I
OH
added to Table 6: Absolute maximum ratings.
Note added to Table 23: DC characteristics (current and new M95080-R and M95080-DR products).
Process modified in Table 45: Ordering information scheme.
All packages are ECOPACK2 compliant.
02-Mar-2010
03 ‑ Jan-2012
13
14
Section 5.6.1: ECC (error correction code) and write cycling and Table 24: Available M95128x products (package, voltage range, temperature grade) updated.
Updated UFDFPN8 package data.
06
19 ‑
‑ Aug
Dec ‑
‑ 2012
2012
15
16
Datasheet revision 14 split into:
- M95128-125 datasheet for automotive products (range 3),
- M95128-W M95128-R M95128-DF (this datasheet) for standard products (range 6).
Updated:
– Cycling: 4 million cycles
– Data retention: 200 years
– Max clock frequency: 5 [email protected] V, 10 [email protected] V, 20 [email protected] V.
Added:
– Identification page (for M95128-D devices)
– 1.7 V/5.5 V range (F suffix)
- Added “Additional Write lockable page (Identification page)” and replaced “(ECOPACK®)” with “(ECOPACK2®)” in
Features.
– Updated Table 2: Write-protected block size.
– Updated Section 7.2: Initial delivery state.
– Replaced Figure 38 and Table 54 (UFDFPN8 package).
– Added Note (1) to Table 25: Ordering information scheme.
20 ‑ May ‑ 2015 17
Replaced “ball” by “bump” in the entire document.
Updated Features and WLCSP package figure on cover page.
Updated Figure 3: WLCSP connections (top view, marking side, with bumps on the underside) and Figure 4: Block diagram.
Removed Caution note on UV exposure in Section 1: Description.
Updated Section 5.1.3: Power-up conditions, Section 5.3: Hold condition and tables in Section 6: Instructions.
Updated Table 7: Absolute maximum ratings and its footnotes.
Updated Table 15: DC characteristics (M95128-W, device grade 6).
Updated Section 10: Package information with changes in each of Sections 10.1: SO8N package information, 10.2:
TSSOP8 package information, 10.3: UFDFN8 package information and Section 10.4: WLCSP package information.
DS1356 - Rev 20 page 42/48
M95128-W M95128-R M95128-DF
21 ‑ Sep ‑ 2015
22 ‑
Date
Feb ‑ 2017
Revision Changes
Updated Table 25: Ordering information scheme and added Note: on Engineering samples.
Updated Disclaimer
18
19
Updated title of Table 8: Operating conditions (M95128-W, device grade 6), Table 19: AC characteristics (M95128-R, device grade 6) and Table 20: AC characteristics (M95128-DF, device grade 6).
Updated title and footnotes of Table 15: DC characteristics (M95128-W, device grade 6) Table 16: DC characteristics (M95128-R, device grade 6), Table 17: DC characteristics (M95128-DF, device grade 6) and Table
18: AC characteristics (M95128-W, device grade 6).
Updated footnote 1 of Table 7: Absolute maximum ratings.
Added footnote 4 to Figure 26.
Updated Section 6.6.1: Cycling with Error Correction Code (ECC) and Section 10.4: WLCSP package information.
Updated Figure 6: SPI modes supported, Figure 8: Write Enable (WREN) sequence and Figure 9: Write Disable
(WRDI) sequence.
Updated caption of Figure 25: TSSOP8 – 8-lead thin shrink small outline, 3 x 4.4 mm, 0.65 mm pitch, package outline and of Figure 22: TSSOP8 – 8-lead thin shrink small outline, 3 x 4.4 mm, 0.65 mm pitch, package mechanical data.
27 ‑ Oct ‑ 2020 20
•
•
•
Added:
Table 2. Signals vs. bump position
Figure 24. SO8N - Recommended footprint
Figure 26. TSSOP8 – Recommended footprint
•
Updated:
DS1356 - Rev 20 page 43/48
M95128-W M95128-R M95128-DF
Contents
Contents
DS1356 - Rev 20 page 44/48
M95128-W M95128-R M95128-DF
Contents
DS1356 - Rev 20 page 45/48
M95128-W M95128-R M95128-DF
List of tables
List of tables
DS1356 - Rev 20 page 46/48
M95128-W M95128-R M95128-DF
List of figures
List of figures
DS1356 - Rev 20 page 47/48
M95128-W M95128-R M95128-DF
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks . All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2020 STMicroelectronics – All rights reserved
DS1356 - Rev 20 page 48/48
Herunterladen
Öffentlicher Link aktualisiert
Der öffentliche Link zu Ihrem Chat wurde aktualisiert. Sie können Ihre Chat-Links nach der Registrierung hier einsehen und verwalten.
Öffentlicher Dokumentenlink
Werbung