STMicroelectronics A6986I Datasheet
जाहिरात
जाहिरात
A6986I
Datasheet
Automotive 38 V, 5 W synchronous iso-buck converter for isolated applications
Maturity status link
A6986I
Features
• AEC-Q100 Grade 1 qualified
• Designed for iso-buck topology
• 4 V to 38 V operating input voltage
• Primary output voltage regulation / no optocoupler required
• 1.9 A typical sink peak primary current capability
• Peak current mode architecture in forced PWM operation
• 300 ns blanking time
• 8 µA I
Q-SHTDWN
• Adjustable f
SW
and synchronization
• Embedded primary output voltage supervisor
• Adjustable soft-start time
• Internal primary current limiting
• Overvoltage protection
• R
DS(on) HS
= 180 mΩ, R
DS(on) LS
= 150 mΩ
• Thermal shutdown
Applications
• Automotive isolated IGBT/SiC MOSFET gate drive supply
• OBC (On-board charger) for HEV/EV
• Electric traction systems
Description
The A6986I is an automotive grade device specifically designed for the isolated buck topology. The 100% duty cycle capability and the wide input voltage range meet the cold crank and load dump specifications for automotive systems. The primary output voltage can be accurately adjusted, whereas the isolated secondary output is derived by using a given transformer ratio. No optocoupler is required. The primary sink capability typically up to 1.9 A (even during soft-start) allows a proper energy transfer to the secondary side as well as enabling a tracked soft-start of the secondary output. The control loop is based on a peak current mode architecture and the device operates in forced PWM. The 300 ns blanking time filters oscillations, generated by the transformer leakage inductance, making the solution more robust.
Pulse-by-pulse current sensing on both power elements implements an effective constant current protection in the primary side. Due to the primary reverse current limit, the secondary output is protected against short-circuit events. A primary output voltage supervisor, which notifies primary output voltage regulation through the
RST open collector output, overvoltage protection, adjustable switching frequency, synchronization and a programmable soft-start are also available. For traditional buck topology in automotive application the A6986 / A6985F / A6986F / A6986H is recommended.
DS13481 - Rev 2 - May 2021
For further information contact your local STMicroelectronics sales office.
www.st.com
1
Application schematic
Figure 1. Application schematic
A6986I
Application schematic
DS13481 - Rev 2 page 2/62
A6986I
Pin connection
2
Pin connection
RST
VCC
SS/INH
SYNCH
FSW
MLF
COMP
DELAY
Figure 2. Pin connection (top view)
1
2
3
4
7
8
5
6
EXPOSED
PAD TO
SGND+PGND
16
15
14
13
12
11
10
9
VBIAS
VIN
LX
LX
PGND
PGND
SGND
FB
6
7
8
16
-
9
10
11
12
13
14
15
3
4
5
N°
1
2
Table 1. Pin description
Pin
RST
VCC
SS / INH
SYNCH
FSW
Description
The RST open collector output is driven low when the output voltage is out of regulation. The
RST is released after an adjustable time DELAY once the primary output voltage is over the active delay threshold.
Connect a ceramic capacitor (≥ 470 nF) to filter internal voltage reference. This pin supplies the embedded analog circuitry.
An open collector stage can disable the device clamping this pin to GND (INH mode).
An internal current generator (4 µA typ.) charges the external capacitor to implement the soft-start.
The pin features master / slave synchronization. Leave this pin floating when it is not used.
A pull-up resistor (E24 series only) to VCC or pull-down to GND selects the switching frequency. Pin strapping is active only before the soft-start phase to minimize the IC consumption.
MLF
COMP
DELAY
FB
SGND
PGND
PGND
Connect this pin to ground either directly or through a pull-down resistor if the RST threshold
should be adjusted (see Table 7
).
Output of the error amplifier. The designed compensation network is connected at this pin.
An external capacitor connected to this pin sets the time DELAY to assert the rising edge of the RST open collector after the output voltage is over the reset threshold. If this pin is left floating, RST is like a Power Good.
Primary output voltage sensing
Signal GND
Power GND
Power GND
LX
LX
VIN
Switching node
Switching node
DC input voltage
VBIAS
Typically connected to the regulated primary output voltage, if it does not exceed 6 V.
Otherwise connect it to GND.
Exposed pad Exposed pad must be connected to SGND, PGND
DS13481 - Rev 2 page 3/62
2.1
A6986I
Maximum ratings
Symbol
V
IN
DELAY
PGND
SGND
V
CC
SS /INH
MLF
COMP
VFB
FSW
SYNCH
V
BIAS
RST
LX
T
J
T
STG
T
LEAD
I
HS
, I
LS
Maximum ratings
Stressing the device above the rating listed in the table below may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability.
See
Table 2. Absolute maximum ratings
Description
Operating temperature range
Storage temperature range
Lead temperature (soldering 10 s.)
High-side / low-side switch current
Min.
-0.3
-0.3
SGND - 0.3
-
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-40
-
-
-
Max.
40
VCC + 0.3
SGND + 0.3
-
(VIN + 0.3) or (max. 4)
VIN + 0.3
VCC + 0.3
VCC + 0.3
10
VCC + 0.3
VIN + 0.3
(VIN + 0.3) or (max. 6)
VIN + 0.3
VIN + 0.3
150
-65 to 150
260
2
°C
°C
A
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
°C
Symbol
R thJA
R thJC
Table 3. Thermal data
Parameter
Thermal resistance junction ambient (device soldered on the STMicroelectronics demonstration board)
Thermal resistance junction to exposed pad for board design (not suggested to estimate TJ from power losses)
Value
40
5
Unit
°C/W
°C/W
Symbol
ESD
Table 4. ESD protection
Test conditions
HBM
CDM
CDM corner pins
Value
2
500
750
Unit kV
V
V
DS13481 - Rev 2 page 4/62
A6986I
Electrical characteristics
3
Electrical characteristics
Table 5. Electrical characteristics (T
J
= -40 to 135°C, V
IN
= 12 V unless otherwise specified).
Typ.
Symbol
V
IN
V
IN_H
V
IN_L
Parameter
Operating input voltage range
V
CC
UVLO rising threshold
V
CC
UVLO falling threshold
Test condition
I
PK
Peak current limit
Duty cycle < 20%
Duty cycle = 100% closed loop operation
I
VY
Valley current limit
I
VY_SNK
R
DS(on)HS
R
DS(on)LS f
SW
I
FSW
I
MLF
D
Reverse current limit
High-side R
Low-side R
DSON
DSON
Selected switching frequency
FSW biasing current
I
T
J
= - 40°C
T
J
= 25°C
T
J
= 135°C
I
SW
= 1 A
SW
= 1 A
FSW pinstrapping before SS
SS ended
I
Q OPVBIAS
V
I
T
ON MIN
V
SWO
SHTDWN
V
CC
INH
INH HYST
I
I
Q OPVIN
SS CH
MLF biasing current SS ended
Duty cycle
Minimum on-time
LDO output voltage
V
BIAS
threshold (3 V < V
BIAS
< 5.5 V)
Switch internal supply from V
IN
to V
BIAS
Switch internal supply from V
BIAS
to V
IN
Power consumption
Shutdown current from V
IN
T
J
= - 40°C
T
J
= 25°C
T
J
= 135°C
V
CC
regulator
V
BIAS
= GND (no switchover)
V
BIAS
= 5 V (switchover)
Quiescent current from V
Quiescent current from V
IN
BIAS
VSS / INH = GND
SWO
V
FB
= GND (NO SLEEP) V
BIAS
= 3.3 V
NO SWO V
FB
GND
= GND (NO SLEEP) V
BIAS
=
SWO V
FB
= GND (NO SLEEP) V
BIAS
= 3.3 V
Soft-start
V
SS
threshold
V
SS
hysteresis
SS rising
C
SS
charging current
V
SS
< V
INH
or t <
TSS SETUP
or V
EA
+ > V
FB
t > T
SS SETUP and V
EA
+ < V
FB
0
267
281
330
2.9
2.9
2.85
2.7
Min.
4
2.7
2.4
2.55
2.1
2.7
1.165
1.285
1.385
4
0.5
2
0.5
200 460
75
1
4
1.9
1.9
1.9
0.18
0.15
0.30
See
0
0
500
325
330
400
500
100
379
383
461
2.755
2.61
2.425
0.36
3.3
3.3
8
1.5
2.8
1.2
3.6
3.6
3.2
3.15
Max.
38
3.5
3.5
15
5
6
5
700
140
Unit
V
A
Ω ns
V
μA mA mA mV
μA nA nA
%
DS13481 - Rev 2 page 5/62
A6986I
Electrical characteristics
Symbol
V
SS START
SS
GAIN
Parameter
Start of internal error amplifier ramp
SS/INH to internal error amplifier gain
Test condition
Error amplifier
V
FB
I
FB
A
V
Voltage feedback
FB biasing current
Error amplifier gain
I
COMP
EA output current capability
Inner current loop g
CS
Current sense transconductance
(VCOMP to inductor current gain) (1)
I pk
= 1 A
V
PP*gCS
Overvoltage protection
V
OVP
V
OVP HYST
Overvoltage trip (V
OVP
Overvoltage hysteresis
/V
REF
) f
SYNCH
Synchronization frequency
Synchronization (fanout: 6 slave devices typ.)
FSW = V
CC
FSW = GND
SYNCH rising
V
V
SYN TH
I
SYN
SYN OUT
SYNCH input threshold
SYNCH pull-down current
High level output
Low level output
V
SYN
= 1.2 V
5 mA sinking load
0.7 mA sourcing load
Reset
MLF pinstrapping before SS V
THR
V
THR HYST
Selected RST threshold
RST hysteresis
I
V
V
RST
THD
D CH
RST open collector output
V
IN
> V
IN
and V
FB
< V
TH4
mA sinking load
2 < V
IN
< V
INH
4 mA sinking load
Delay
RST open collector released as soon as V
DELAY
> V
THD
C
DELAY
charging current
V
FB
> V
THR
V
FB
> V
THR
Thermal shutdown
T
SHDWN
T
HYS
1. Not tested in production.
2. T
J
= -40°C.
3. Measured at f
SW
= 250 kHz.
Min.
0.995
Typ.
1.1
3
Max.
1.150
Unit
V
0.841
± 6
0.85
50
100
±12
0.859
500
±25
V
µA dB
µA
0.45
2.5
0.75
1.1
A/V
A
1.15
0.5
1.2
2
1.25
5 %
275
475
0.70
1.40
0.7
1000
2200
1.2
kHz
V mA
V
0.6
See
2
0.4
0.8
%
V
1.19
1
1.234
2
1.258
3
V
µA
165
30
°C
DS13481 - Rev 2 page 6/62
DS13481 - Rev 2
A6986I
Electrical characteristics
Table 6. f
SW
selection (T
J
= -40 to 135°C, V
IN
= 12 V unless otherwise specified).
Symbol f
SW
R
VCC
(E24 series)
0 Ω
1.8 Ω
3.3 kΩ
5.6 kΩ
10 kΩ
NC
18 kΩ
33 kΩ
56 kΩ
NC
NC
R
GND
(E24 series)
NC
NC
NC
NC
NC
0 Ω
NC
NC
NC
1.8 kΩ
3.3 kΩ
1. Synchronization as slave between 275 kHz and 1000 kHz.
2. Not tested in production.
3. Synchronization as slave between 475 kHz and 1000 kHz.
Tj
450
-
-
-
-
900 f
SW
min.
225
-
-
-
-
500
575
660
755
870
1000 f
SW
typ.
250
285
330
380
435
550
-
-
-
-
1100 f
SW
max.
275
-
-
-
-
Figure 3. Circuit R
VCC
, R
GND
Unit kHz
R
VCC
VCC
FSW
A6986I
VCC
FSW
A6986I
R
GND
SGND SGND
Table 7. RST threshold selection (T
J
= -40 to 135°C, V
IN
= 12 V unless otherwise specified).
Symbol
V
RST
R
GND
(E241%)
0 Ω
8.2 kΩ ±1%
18 kΩ ±1%
V
RST
/V
1. please use the pre-defined resistor values.
2. do not exceed the indicated resistor value.
OUT
(tgt. value)
93%
80%
87%
96%
V
RST min.
0.779
0.670
0.728
0.804
V
RST typ.
0.791
0.680
0.740
0.816
V
RST max.
0.802
0.690
0.751
0.828
Unit
V page 7/62
4
A6986I
Parameters over the temperature range
Parameters over the temperature range
A 100% of the population in the production flow is tested at three different ambient temperatures (-
40°C, + 25°C, + 135°C) to guarantee the datasheet parameters inside the junction temperature range
(- 40°C, + 135°C).
The device operation is guaranteed when the junction temperature is inside the (- 40°C, + 150°C) temperature range. The designer can estimate the silicon temperature increase with respect to the ambient temperature evaluating the internal power losses generated during the device operation.
However, the embedded thermal protection disables the switching activity to protect the device in case the junction temperature reaches the T
SHTDWN
(+ 165°C typ.) temperature.
All the datasheet parameters can be guaranteed to a maximum junction temperature of + 135°C to avoid triggering the thermal shutdown protection during the testing phase because of self-heating.
DS13481 - Rev 2 page 8/62
5
A6986I
Functional description
Functional description
•
•
The iso-buck topology based on the A6986I consists of:
• Primary side, the regulation loop of the peak current mode architecture regulates the primary voltage (blue area in the image below)
A two-windings transformer (in grey)
The secondary side, which generates the isolated output voltage (in green) given the selected transformer ratio
Figure 4. Iso-buck general schematic
5.1
Primary side
The A6986I is based on a “peak current mode”, constant frequency control. The intersection between the error amplifier output and the sensed inductor current generates the PWM control signal to drive the power switch of the primary side, defining so the duty-cycle and regulating the primary output voltage.
The device operates in forced PWM control (MLF pin to GND), allowing negative currents to flow in the synchronous MOSFET, hence transferring energy to the secondary coil during the off-time.
DS13481 - Rev 2 page 9/62
5.1.1
A6986I
Primary side
The main internal blocks shown in the block diagram in figure below are:
Figure 5. Internal block diagram
SS/INH
FB
SS/INH
0
T
SS
V
REF
COMP SYNC FSW
OSCILLATOR
SENSE
P
MOS
PEAK
CL
+
-
SLOPE
LOOP
CONTROL
OVP
DELAY
-
+
RST TH.
ZERO
CROSSING
SENSE
N
Vcc
VIN
POWER
P
POWER
N
MOS
RST
VALLEY
CL
DELAY MLF GND
LX
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Embedded power elements. Thanks to the P-channel MOSFET as high-side switch the device features lowdropout operation
A fully integrated sawtooth oscillator with adjustable frequency
A transconductance error amplifier
An internal feedback divider G
DIV INT
The high-side current sense amplifier to sense the inductor current
A “Pulse Width Modulator” (PWM) comparator and the driving circuitry of the embedded power elements
The soft-start blocks to ramp the error amplifier reference voltage and so decreases the inrush current at power-up. The SS/INH pin inhibits the device when driven low
The switchover capability of the internal regulator to supply a portion of the quiescent current when the V
BIAS pin is connected to an external output voltage
The synchronization circuitry to manage master / slave operation and the synchronization to an external clock
The current limitation circuit to implement the constant current protection, sensing pulse-by-pulse high-side / low-side switch current. In case of heavy short-circuit the current protection is fold back to decrease the stress of the external components
A circuit to implement the thermal protection function
The OVP circuitry to discharge the output capacitor in case of overvoltage event
MLF normally connected to GND through a resistor to set the threshold of the RST comparator
FSW pin strapping sets the switching frequency
The RST open collector output
Power supply and voltage reference
The internal regulator block consists of a start-up circuit, the voltage pre-regulator that provides current to all the blocks and the bandgap voltage reference. The starter supplies the start-up current when the input voltage goes high and the device is enabled (SS/INH pin over the inhibits threshold).
The pre-regulator block supplies the bandgap cell and the rest of the circuitry with a regulated voltage that has a very low supply voltage noise sensitivity.
DS13481 - Rev 2 page 10/62
5.1.2
5.1.3
5.1.4
5.2
5.3
A6986I
Transformer
Switchover feature
The switchover scheme of the pre-regulator block is used to derive the main contribution of the supply current for the internal circuitry from an external voltage (3 V < V
BIAS
< 5.5 V is typically connected to the primary regulated output voltage). This helps to decrease the equivalent quiescent current seen at V
IN
.
Voltage monitor
An internal block continuously senses the V
CC
, V
BIAS
and V
BG
(bandgap). If the monitored voltages are good, the regulator starts operating. There is also a hysteresis on the V
CC
(UVLO).
Error amplifier
The voltage error amplifier is the core of the loop regulation of the primary output voltage. It is a transconductance operational amplifier whose non inverting input is connected to the internal voltage reference (0.85 V), while the inverting input (FB) is connected to the external divider or directly to the output voltage.
Table 8. Uncompensated error amplifier characteristics
Description
Transconductance
Low frequency gain
Value
155 µS
100 dB
The error amplifier output is compared with the inductor current sense information to perform PWM control.
Figure 6. Internal circuit
V
CC
STARTER PREREGULATOR
VREG
BANDGAP
IC BIAS
D00IN1126 VREF
Transformer
The transformer is the key component for the iso-buck, ensuring the desired isolation as well as allowing the energy transfer to the secondary side, hence generating the secondary isolated output voltage.
).
Secondary side
The secondary side includes an LC filter (secondary winding of the transformer and secondary output capacitor) and the rectifying element (Schottky diode).
DS13481 - Rev 2 page 11/62
5.4
A6986I
Iso-buck operation principle
Iso-buck operation principle
The image below describes the operation principle of the iso-buck converter.
When the high-side MOSFET is turned on, the current flows through the primary winding of the transformer and charges the primary output capacitor. Considering the dot convention of the transformer, the voltage at the anode of the Schottky diode is negative, hence the diode is reverse biased and no current flows in the secondary winding. The load connected to the secondary output is supplied by Cout2.
When the low-side MOSFET is turned on, the voltage applied at the transformer windings inverts its polarity. As a consequence, the Schottky diode is now forward biased and allows the current to flow from the secondary winding to Cout and the load. Under this condition the energy transfer from primary to secondary side occurs.
Figure 7. Iso-buck basic operating principle
DS13481 - Rev 2
The waveforms in the figure below reproduce the trend of the current in the two windings according to the switch node transitions.
page 12/62
Figure 8. Iso-buck primary and secondary current waveforms
A6986I
Soft-start and inhibit
5.5
Soft-start and inhibit
The soft-start and inhibit features are multiplexed on the same pin. An internal current source charges the external soft-start capacitor to implement a voltage ramp on the SS/INH pin. The device is inhibited as long as the
SS/INH pin voltage is lower than the V
INH
START. (See the figure below).
threshold and the soft-start takes place when SS/INH pin crosses V
SS
The internal current generator sources 1 µA typ. current when the voltage of the VCC pin crosses the UVLO threshold. The current increases to 4 µA typ. as soon as the SS/INH voltage is higher than the V
INH
threshold.
This feature helps to decrease the current consumption in inhibit mode. An external open collector can be used to set the inhibit operation clamping the SS/INH voltage below V
INH
threshold.
The start-up feature minimizes the inrush current and decreases the stress of the power components during the power-up phase. The ramp implemented on the reference of the error amplifier has a gain three times higher
(SS
GAIN
) than the external ramp present at SS/INH pin.
DS13481 - Rev 2 page 13/62
Figure 9. Soft-start phase
A6986I
Soft-start and inhibit
DS13481 - Rev 2
The C
SS
value is chosen according to equation (1)
CSS = SSGAIN∙
ISSCH∙TSS
VFB = 3∙ where T
SS
is the soft-start time, I
SS CH
the charging current and V
FB
the reference of the error amplifier.
During normal operation a new soft-start cycle takes place in case of:
• Thermal shutdown event
• UVLO event
• The device is driven in INH mode
The soft-start capacitor is discharged with a 0.6 mA typ. current capability for 1 ms time max. For complete and proper capacitor discharge in case of fault conditions, a maximum C
SS
= 67 nF value is suggested.
In case the soft-start should be externally driven by a voltage step (e.g. the signal from ignition switch in
automotive applications), the schematic in Figure 10
can be used.
The secondary output line regulation is defined, similarly to the primary side, as the variation of the secondary output voltage due to the input voltage change at a specific current.
(1) page 14/62
Figure 10. Enable the device with external voltage step
A6986I
Minimum on-time
More details about the component selection can be found in
Secondary side soft-start
As soon as the soft-start begins at the primary circuit, the device already operates in forced PWM and the energy transfer to the secondary coil during the off-time can take place. Consequently, a tracked soft-start at the secondary side takes place too. Therefore, the secondary output voltage reaches its steady-state value in tracking with the primary output voltage, as shown in the figure below.
Figure 11. Tracked soft-start at secondary side
5.6
Minimum on-time
The current sense in the high-side MOSFET is not active (masked) for a certain time at the beginning of the on-time (masking time, from which the parameter T
ON MIN
derives).
This current sense blanking time is implemented to prevent any primary side pulsed current at the high-side turn-on (resonating with transformer drive leakage inductance and secondary side capacitance) overcoming the
EA programmed switch current for the conversion and making conversion unstable (depicted in
DS13481 - Rev 2 page 15/62
DS13481 - Rev 2
Figure 12. Simulation with insufficient masking time (< 100 ns)
A6986I
Minimum on-time
Figure 13. Simulation with appropriate masking time (330 ns)
Despite the masking time, an RC snubber circuit is normally recommended to dampen the oscillations. The figure below shows a typical application where the appropriate masking time is implemented as well as an RC snubber circuit.
Figure 14. Remaining oscillations filtered by the masking time and RC snubber circuit V
IN
= 12 V, N = 1.58,
I
OUTiso
= 100 mA page 16/62
5.7
A6986I
Output voltage line regulation
Output voltage line regulation
All results shown in this section come from measurements performed using the reference schematic depicted in
Figure 15. Schematic used for line and load regulation tests
DS13481 - Rev 2
Primary output line regulation
The regulator features an enhanced primary line regulation due to the peak current mode architecture.
shows negligible output voltage variation (normalized to the value measured at V
IN
= 12 V) over an input voltage range up to 24 V for A6986I with V
OUT
prim = 5.3 V.
Figure 16. Primary line regulation
0.0%
-0.1%
-0.2%
Iout_prim = 0A
Iout_prim = 1A
-0.3%
-0.4%
-0.5%
12 13 14 15 16 17 18
V
IN
[V]
19 20 21 22 23 24 page 17/62
DS13481 - Rev 2
A6986I
Output voltage line regulation
Secondary output line regulation
The secondary output line regulation is defined, similarly to the primary side, as the variation of the secondary output voltage due to the input voltage change at a specific current. The secondary output line regulation is mainly affected by the transformer and in particular by its leakage inductance.
Keeping constant the leakage inductance (i.e. using the same transformer), a higher input voltage allows to slightly increase the isolated output voltage, as shown in
Figure 17. Secondary output line regulation
6%
5%
4%
3%
2%
1%
0%
12 13 14 15 16 17 18
V
IN
[V]
19 20 21 22 23 24
The input voltage value influences the peak current in the secondary winding (see Figure 17
), hence determining the amount of energy delivered to the secondary output and in turn the isolated output voltage value.
Figure 18. Secondary winding current at different input voltages page 18/62
5.8
A6986I
Output voltage load regulation
Output voltage load regulation
Primary output load regulation
Figure 18 shows negligible primary output voltage variation (normalized to the value measured at I
OUT
= 0 A) over the entire output current range for the A6986I with V
OUT
= 5.3 V.
Figure 19. Load regulation of the non isolated output
0.6%
0.5%
0.4%
0.3%
0.2%
0.1%
0.0%
-0.1%
-0.2%
-0.3%
-0.4%
-0.5%
-0.6%
0 0.2
0.4
0.6
0.8
1
I
OUT_prim
[A]
1.2
1.4
1.6
1.8
2
Secondary output load regulation
Since there is not a regulation loop involving the secondary output, its load regulation depends to some extent
on the primary load regulation and is affected by the leakage inductance (see Figure 19
) of the transformer, the voltage drops across to the Schottky diode (diode forward voltage) and the DCR of the secondary coil, as indicated by equation (1) (where only the last two contributions are considered). Minimizing all the mentioned parameters leads to a better load regulation.
Figure 20. Effect of the transformer leakage inductance on the isolated output load regulation
15%
10%
5%
0%
-5%
-10%
-15%
10 20 30 40 70 80
Lleak = 240nH
Lleak = 700nH
50
I
OUT
[mA]
60 90 100
DS13481 - Rev 2 page 19/62
A6986I
Overcurrent protection
As shown in Section 5.7, the input voltage also plays a role in the isolated output regulation.
proves the slight dependency of the isolated output voltage on the input voltage.
Figure 21. Input voltage effect on the load regulation of the isolated voltage
20%
15%
10%
5%
0%
-5%
-10%
-15%
-20%
10 20 30 40 50 60
I
OUT
[mA]
70
VIN = 12V
VIN = 18V
VIN = 24V
80 90 100
5.9
Overcurrent protection
Protection against overcurrent conditions and/or short-circuit at the output is ensured at both primary and secondary side of the iso-buck converter.
Overcurrent protection at the primary side
The current protection circuitry features a constant current protection, so the device limits the maximum peak current (see
) in overcurrent condition.
The A6986I device implements a pulse-by-pulse current sensing on both power elements (high-side and low-side switches), ensuring an effective current protection over the duty cycle range. The high-side current sensing is called “peak” the low-side sensing “valley”.
The internal noise generated during the switching activity makes the current sensing circuitry ineffective for a minimum conduction time of the power element. This time is called “masking time” because the information from the analog circuitry is masked by the logic to prevent an erroneous detection of the overcurrent event.
Consequently, the peak current protection is disabled for a masking time after the high-side switch is turned on, the valley for a masking time after the low-side switch is turned on. In other words, the peak current protection can be ineffective at extremely low duty cycles, the valley current protection at extremely high duty cycles.
Summarizing, in case one of the two current sensing circuitries is ineffective because of the masking time, the device is protected sensing the current on the opposite switch. Thus, the combination of the “peak” and “valley” current limits assures the effectiveness of the overcurrent protection even in extreme duty cycle conditions.
The valley current threshold is designed higher than the peak to guarantee a proper operation. In case the current diverges because of the high-side masking time, the low-side power element is turned on until the switch current level drops below the valley current sense threshold. Under this condition the device can skip some cycle, leading to a switching frequency reduction. The figure below shows an example of valley current limit intervention in a short-circuit event (switching frequency set to 500 kHz, actual switching frequency 250 kHz).
DS13481 - Rev 2 page 20/62
Figure 22. Valley current sense operation in short-circuit
A6986I
Overcurrent protection
low duty cycle (V
IN
= 24 V, f
SW
= 500 kHz short-circuit condition).
In a worst case scenario (like
Figure 22 ) of the overcurrent protection the switch current is limited to:
IMAX= IVALLEYTH+ ∙TMASKHS where I
VALLEY_TH
is the current threshold of the valley sensing circuitry (see masking time of the high-side switch (330 ns typ.).
) and T
MASK_HS
is the
In most of the overcurrent conditions the conduction time of the high-side switch is higher than the masking time and so the peak current protection limits the switch current.
IMAX = IPEAK_TH
(2)
(3)
Figure 23. Peak current sense operation in overcurrent condition
DS13481 - Rev 2
on-time reaches the peak current protection threshold. From this point on, any increase of the output current causes the on-time to be reduced (image on the right) so that the current provided to the output is limited. As a consequence, the output voltage drops, as the purple waveform depicts.
The DC current flowing in the load in overcurrent condition is:
IDCOC (VOUT) = IMAX‐ ∙TON (4) page 21/62
A6986I
Overvoltage protection
Overcurrent protection at the secondary side
The increase of the secondary output current affects the current shape at primary side. In particular, the peak currents in the high-side and low-side MOSFETs rise (in absolute value in the low-side, i.e. the current becomes more negative), in accordance with equations (5) and (6)).
IPEAKHS= IOUT_pri+N∙IOUT_sec+
IPEAKLS= − N∙IOUT_sec∙
2D
1 − D −
∆IL
2 + IOUT_prim
(5)
(6) where I
OUT_pri
and I
OUT_sec
are respectively the primary and secondary output currents, N is the transformer turn ratio, D the duty cycle and ΔI
L
the current ripple in the primary winding.
Figure 23 depicts how these peak currents vary depending on the secondary output current, under the specified conditions.
Normally the negative current during the off-time is more critical and the secondary output is limited by relying on the reverse current limit (typ. 1.9 A), as shown in the figure below.
A current drawn from the primary output helps to reduce the peak current in the low-side MOSFET [as shown by equation (6)], hence allowing a higher current from the secondary output. Nevertheless, attention must be paid to the I
PEAKHS
[equation (5)] that must be lower than the peak current limit.
Figure 24. Peak currents depending on the secondary output current (V
IN
= 12 V, V
OUT_pri
= 5.3, N = 6, f
SW
= 500 kHz, no primary output current)
2.4
2
1.6
1.2
0.8
0.4
0
0
| I
PEAK
LS
| reverse current limit (typ.) exceeded
50 100
Secondary output current [mA]
150
I
PEAK
HS
200
5.10
Reverse current limit
As mentioned in the previous section, the low-side MOSFET is protected against negative currents. This feature limits the negative current in the MOSFETs especially during two events:
- Overvoltage at the primary output. Due to an overvoltage event the low-side MOSFET is kept on to discharge the primary output.
- Overcurrent or short-circuit event at the secondary output, as described in the previous section.
Overvoltage protection
The overvoltage protection monitors the V
FB
pin and enables the low-side MOSFET to discharge the output capacitor if the output voltage is 20% over the nominal value.
DS13481 - Rev 2 page 22/62
A6986I
Thermal shutdown
This is a second level protection and should never be triggered in normal operating conditions if the system is properly dimensioned. In other words, the selection of the external power components and the dynamic performance determined by the compensation network should guarantee an output voltage regulation within the overvoltage threshold even during the worst-case scenario in terms of load transitions.
optimized compensation network. This can be considered as an example for a system with dynamic performance not in line with the load request.
The A6986I device implements a 1.9 A typ. negative current limitation to limit the maximum reversed switch current during the overvoltage operation.
Moreover, the overvoltage protection also activates the internal pull-down on the RST pin. Once OVP is deactivated, the A6986I releases the RST (
). The release of the RST pin can be delayed by connecting a capacitor to the DELAY pin (pin 9). For the selection of the capacitance value, equation (28) can be used.
Figure 25. Overvoltage operation
5.11
Thermal shutdown
The shutdown block disables the switching activity if the junction temperature is higher than a fixed internal threshold (165°C typical). The thermal sensing element is close to the power elements, ensuring fast and accurate temperature detection. A hysteresis of approximately 30°C prevents the device from turning ON and
OFF continuously. When the thermal protection runs away a new soft-start cycle takes place.
DS13481 - Rev 2 page 23/62
6
A6986I
Closing the loop
Closing the loop
The iso-buck, compared to a standard buck, includes the transformer in place of the inductor and all the components connected to the secondary winding (at least the Schottky diode and the secondary output capacitor). Nevertheless, the regulation loop does not include the secondary side components. As a first approximation the control loop of an iso-buck can be assimilated to the one of a standard buck. Therefore, the block diagram in the figure below can still be used (where the inductor symbol identifies the inductance of the primary winding) as well as all the equations and calculations in the following sections.
Figure 26. Block diagram of the loop
6.1
G
CO
(s) control to output transfer function
The accurate control to output transfer function for a buck peak current mode converter can be written as:
GCO(s)= RLOAD∙gCS∙
1+
L
1
∙ mC∙ 1‐D ‐0.5
∙ ∙FH(s (7) where R
LOAD
represents the load resistance, g
CS
the equivalent sensing transconductance of the current sense circuitry, w p
the single pole introduced by the power stage and w z
the zero given by the ESR of the output capacitor.
F
H
(s) accounts for the sampling effect performed by the PWM comparator on the output of the error amplifier that introduces a double pole at one half of the switching frequency.
ωZ=
1
ESR∙COUT
ωp=
1
RLOAD∙COUT∙ mC∙ 1‐D ‐0.5
L∙COUT∙fSW
(8)
(9) where: mC=1+
Se
Sn
Se=VPP∙gCS∙fSW
Sn=
(10)
DS13481 - Rev 2 page 24/62
6.2
A6986I
Error amplifier compensation network
S n
represents the on-time slope of the sensed inductor current, S e
the on-time slope of the external ramp (V
PP peak-to-peak amplitude) that implements the slope compensation to avoid sub-harmonic oscillations at duty cycle over 50%.
S e
can be calculated from the parameter V
PP
× g
CS
The sampling effect contribution F
H
(s) is:
FH s =
1+
1 s
ωn∙Qp + s
2
ωn2
(11) where
ωn=π∙fSW
Qp=
1
π∙mC∙ 1−D − 0.5
(12)
Error amplifier compensation network
The typical compensation network required to stabilize the system is shown in the figure below:
Figure 27. Transconductance embedded error amplifier
DS13481 - Rev 2
R
C
and C
C
introduce a pole and a zero in the open loop gain. C
P
does not significantly affect system stability but it is useful to reduce the noise at the output of the error amplifier.
The transfer function of the error amplifier and its compensation network is:
A0 s =
AV0∙ 1+s∙RC∙CC s2∙R0∙ C0+Cp ∙RC∙CC+s∙ R0∙CC+R0∙ C0+Cp +RC∙CC +1 where A
V0
=G m
∙R
0
.
The poles of this transfer function are (if C
C
>> C
0
+ C
P
) fPHF=
1
2∙π∙R0∙CC
(13)
(14) page 25/62
6.3
A6986I
Voltage divider whereas the zero is defined as: fPHF=
1
2∙π∙R0∙ C0+Cp
(15)
Voltage divider
The contribution of the internal voltage divider for fixed output voltage devices is:
GDIV(s)=
R2
R1+R2=
VFB
VOUT
A small signal capacitor in parallel to the upper resistor (see figure below) of the voltage divider implements a leading network (f zero
< f pole
), sometimes necessary to improve the system phase margin:
(16)
Figure 28. Leading network example
6.4
The Laplace transformer of the leading network is:
GDIV(s)=
R2
R1+R2∙
1+ sfZ where fZ=
1
2∙π∙R1∙CR1 f
P
=
2∙π∙
1
R1∙R2
R1+R2∙CR1 f
Z
< f
P
Total loop gain
In summary, the open loop gain can be expressed as:
G (s)= GDIV(s)∙GC0(s)∙A0(s)
DS13481 - Rev 2
(17)
(18)
(19) page 26/62
6.5
A6986I
Compensation network design
Compensation network design
The maximum bandwidth of the system can be designed up to f
SW
/6, up to 150 kHz maximum to guarantee a valid small signal model
RC=
2∙π∙BW∙COUT∙VOUT
0.85V∙gCS∙gm_typ where:
(20) fPOLE=
ω
P
is defined by eq. (9) , g
CS
represents the current sense transconductance (see Section 3 ) and g
error amplifier transconductance.
m TYP
the
(21)
CC=
5
2∙π∙RC ∙ BW
Example 1:
V
IN
= 12 V, V
OUT_pri
= 5.3 V, R
OUT_pri
= 5.6 Ω (corresponding to almost 1 A load).
Selecting the A6986I with V
OUT_pri
= 5.3 V, f
SW
= 500 kHz, L pri
= 18 µH, C
OUT_pri
= 10 µF and ESR = 3 mΩ,
R
C
= 56 kΩ, C
C
= 680 pF, C
P
= 4.7 pF (please refer to
Table 11 ), the gain and phase bode diagrams are plotted
and Figure 30. Bode plot (phase)
.
(22)
Figure 29. Bode plote (magnitude)
DS13481 - Rev 2 page 27/62
DS13481 - Rev 2
Figure 30. Bode plot (phase)
A6986I
Compensation network design
The blue solid trace represents the transfer function including the sampling effect term (see equation (11)), the dotted blue trace neglects the contribution.
Considering this example, bandwidth and phase margin are:
BW ≈ 50 kHz
Phase Margin → between 53° and 70° page 28/62
7
7.1
A6986I
Application notes
Application notes
Output voltage adjustment
Primary output voltage
The error amplifier reference voltage is 0.85 V typical. The output voltage is adjusted accordingly to the equation below:
VOUT_pri= 0.85∙ 1+
R1
R2
(23) where R
1
and R
2
are the resistors used in the output divider (see figure below).
Figure 31. A6986I application circuit
DS13481 - Rev 2
The integration of a P-channel MOSFET as high-side switch theoretically allows duty cycle up to 100%.
Nevertheless, in an iso-buck architecture some restrictions should be considered. A general recommendation is to keep the duty-cycle below 50-60%. A higher duty cycle would limit off-time, limiting the time in which the energy transfer to the secondary side takes place.
Other restrictions in the duty cycle selection arise due to the minimum on-time (see
Section 7.2 Switching frequency
), generally summarized by the following equation:
D ≥ DMIN = TON MIN∙fSW
Secondary output voltage
In the iso-buck converter, the secondary output voltage is not included in the regulation loop. Nevertheless, a good regulation of the secondary output voltage is achieved by relying on the primary output voltage regulation, the selection of a proper turn ratio of the transformer as well as considering the voltage drops due to the secondary winding resistance and the Schottky diode. That can be summarized by the following equation:
(24)
VOUT_sec=N∙ VOUT_pri+IOUTpri∙ RDS on LS+Rwind_pri ‐Rwind_sec∙IOUT_sec‐VFD1 (25) where N is the turn ratio, R wind_prim respectively and V
FD1
and R wind_sec
are the winding resistances of the primary and secondary side
is the forward voltage of the Schottky diode.
If no current is drawn from the primary output, equation (25) can be simplified as follows:
VOUT_sec=N∙VOUTpri − Rwind_sec∙IOUT_sec − VFD1 (26) page 29/62
A6986I
Switching frequency
Equation (26) emphasizes how the selection of the transformer and, to some extent, the Schottky diode plays a crucial role in the accurate regulation of the secondary output voltage. The figure below shows instead the effect of the current drawn from the primary output on the isolated voltage, as described by equation (9).
Figure 32. Isolated voltage variation due to the primary output current
10%
9%
8%
7%
6%
5%
4%
3%
2%
1%
0%
0 0.2
0.4
0.6
0.8
I
OUT_pri
1
[mA]
1.2
1.4
1.6
1.8
2
Another factor affecting the secondary output voltage regulation comes from the leakage inductance of the transformer. As described later on, the leakage inductance determines the peak current that can be reached in the secondary winding. This peak current defines the maximum current from the secondary isolated output by limiting the amount of charge delivered to the output. When the current demand from the secondary isolated output exceeds the maximum deliverable charge limited by the peak current, the isolated output voltage drops.
Figure 33. Secondary output maximum current
7.2
To some extent also the duty cycle can affect the secondary output voltage. Since the energy transfer from primary to secondary occurs only during the TOFF, a too high duty cycle could reduce the achievable peak current, hence limiting the deliverable current to the secondary output. Under this condition the secondary output could drop.
Switching frequency
A resistor connected to the FSW pin features the selection of the switching frequency. The pinstrapping is performed at power-up, before the soft-start takes place. The FSW pin is pinstrapped and then driven floating in
value.
Setting f
SW
= 250 kHz or f
SW
= 500 kHz does not require any external resistor.
The selection of the switching frequency must take into account the minimum on-time of the device (T
ON MIN
, as indicated in the electrical characteristics table), as described by the following equation.
fSW_max≤
VOUT
TON MIN∙VIN∙η
(27)
The switching frequency affects the selection of the primary inductance as well as the transformer construction.
DS13481 - Rev 2 page 30/62
7.3
A6986I
Voltage supervisor
Voltage supervisor
The embedded voltage supervisor (composed of the RST and the DELAY pins) monitors the regulated output voltage and keeps the RST open collector output in low impedance as long as the V
OUT
is out of regulation (i.e.
lower than 93% of the target output voltage). In order to ensure a proper reset of digital devices with a valid power supply, the device can delay the RST assertion with a programmable time.
Figure 34. Voltage supervisor operation
When the RST comparator detects the output voltage is in regulation, a 2 mA internal current source starts to charge an external capacitor to implement a voltage ramp on the DELAY pin. The RST open collector is then released as soon as V
DELAY
= 1.234 V (see
DELAY
is dimensioned as follows.
CDELAY=
ISSCH∙TDELAY
VDELAY =
(28)
The maximum suggested capacitor value is 270 nF.
The A6986I also activates internal pull-down on the RST pin in case overvoltage protection is triggered. As soon as the output voltage goes below the OVP threshold (20% typ.), the 2 µA internal current source starts to charge an external capacitor to implement a voltage ramp on the DELAY pin. The RST open collector is then released as soon as V
DELAY
= 1.234 V (see figure below).
Figure 35. Voltage supervisor operation during OVP
DS13481 - Rev 2 page 31/62
7.4
7.4.1
A6986I
Synchronization
Synchronization
The synchronization feature helps the hardware designer to prevent beating frequency noise that is an issue when multiple switching regulators populate the same application board.
Embedded master - slave synchronization
The A6986I synchronization circuitry features the same switching frequency for a set of regulators simply connecting their SYNCH pin together, so preventing beating noise. The master device provides the synchronization signal to the others since the SYNCH pin is I/O able to deliver or recognize a frequency signal.
For proper synchronization of multiple regulators, all of them have to be configured with the same switching frequency (see
), so the same resistor connected at the FSW pin.
In order to minimize the RMS current flowing through the input filter, the A6986I device provides a phase shift of
180° between the master and the slaves. If more than two devices are synchronized, all slaves have a common
180° phase shift with respect to the master.
Considering two synchronized A6986Is which regulate the same output voltage (i.e.: operating with the same duty cycle), the input filter RMS current is optimized and is calculated as:
IRMS
IOUT
2 ∙ 2D ∙ 1 − 2D if D < 0.5
(29)
The graphical representation of the input RMS current of the input filter in the case of two devices with 0° phase shift (synchronized to an external signal) or 180° phase shift (synchronized connecting their SYNCH pins) regulating the same output voltage is provided in the figure below. To dimension the proper input capacitor please
refer to the dedicated section ( Section 7.5.1 Input capacitor selection ).
Figure 36. Input RMS current
DS13481 - Rev 2
The figure below shows two not synchronized regulators with unconnected SYNCH pin.
page 32/62
Figure 37. Two regulators not synchronized
A6986I
Synchronization
The figure below shows the same regulators working synchronized having the SYNCH pins connected. The
MASTER regulator (LX_reg2 trace) delivers the synchronization signal to the slave device (LX_reg1). The SLAVE regulator works in phase with the synchronization signal, which is out of phase with the master switching operation.
Figure 38. Two regulators not synchronized
7.4.2
External synchronization signal
Multiple A6986I can be synchronized to an external frequency signal fed to the SYNCH pin. In this case the regulator set is phased to the reference and all the devices work with 0° phase shift.
Considering that the minimum synchronization pulse width coincides with the T
ON MIN
(typ. 340 ns), it is recommended to synchronize with a frequency not higher than 1 MHz.
Since the internal slope compensation contribution that is required to prevent subharmonic oscillations in peak current mode architecture depends on the oscillator frequency, it is important to select the same oscillator frequency for all regulators (all of them operate as slave) as close as possible to the frequency of the reference
to the FSW pin, so the slope compensation is optimized accordingly with the frequency of the synchronization signal. The slope compensation contribution is latched at power-up and so fixed during the device operation.
DS13481 - Rev 2 page 33/62
A6986I
Synchronization
The A6986I normally operates in MASTER mode, driving the SYNCH line at the selected oscillator frequency as shown in
In SLAVE mode the A6986I sets the internal oscillator at 250 kHz typ. (see
) and drives the line accordingly.
Figure 39. A6986I synchronization driving capability
DS13481 - Rev 2
In order to safely guarantee that each regulator recognizes itself in SLAVE mode when synchronized, the external master must drive the SYNCH pin with a clock signal frequency higher than the maximum oscillator spread of the selected line in
for at least 10 internal clock cycles.
Example 1 : selecting R
FSW
= 0 Ω to VCC
Symbol f
SW
Table 9. Example of oscillator frequency selection
R
VCC
(E24 series
NC
R
GND
(E24 series)
0 Ω f
SW
min.
225 f
SW
typ.
250 f
SW
max.
275
The device enters in SLAVE mode after 10 pulses at frequency higher than 275 kHz.
As anticipated above, in SLAVE mode the internal oscillator operates at 250 kHz typ. but the slope compensation is dimensioned accordingly with FSW resistors so it is important to limit the switching operation around a working point close to the selected oscillator frequency (FSW resistor).
As a consequence, to guarantee the full output current capability and to prevent the subharmonic oscillations, the master may limit the driving frequency range within ± 5% of the selected frequency.
A wider frequency range may generate subharmonic oscillation for duty > 50% or limit the peak current capability
(see IPK parameter in
) since the internal slope compensation signal may be saturated.
The device keeps operating in SLAVE mode as far as the master is able to drive the SYNCH pin faster than 275 kHz, otherwise the A6986I goes back into MASTER mode at the programmed RFSW oscillator frequency after successfully driving one pulse 250 kHz typ. (see
Figure 40 ) in the SYNCH line.
page 34/62
DS13481 - Rev 2
Figure 40. Slave-to-master mode transition
A6986I
Synchronization
The external master can force a latched SLAVE mode driving the SYNCH pin low at power-up, before the soft-start begins the switching activity. So the oscillator frequency is 250 kHz typ. fixed until a new UVLO event is triggered regardless of FSW resistor value, that otherwise counts to design the slope compensation. The same considerations above are also valid.
• Low level < V
SYN THL
= 0.7 V sinking 5 mA
• High level > V
SYN THH
= 1.2 V sourcing 0.7 mA
Figure 41. Master driving capability to synchronize the A6986I page 35/62
7.5
7.5.1
A6986I
Design of the external components
Design of the external components
Input capacitor selection
The input capacitor, just like in a standard buck, should limit the input voltage ripple. Key parameters of the input capacitor are, together with its value, the maximum operating voltage and the RMS current capability.
The input capacitor voltage rating must be higher than the maximum input operating voltage of the application.
During the switching activity a pulsed current flows into the input capacitor and so its RMS current capability must be selected according to the application conditions. Internal losses of the input filter depend on the ESR value so usually low ESR capacitors (like multilayer ceramic capacitors) have higher RMS current capability. On the other hand, given the RMS current value, a lower ESR input filter has lower losses and so contributes to higher conversion efficiency.
The maximum RMS input current flowing through the capacitor can be calculated as:
IRMS= IOUT_pri+ ∙ 1‐Dη ∙
D
η
In the ideal case of efficiency η = 1, the RMS current reaches its maximum value when D = 0.5.
In general, the maximum and minimum duty cycles can be calculated as:
(30)
DMAX=
VOUT_pri+ΔVLS
VINmin+ΔVLS − ΔVHS
(31)
DMIN=
VOUT_pri + ΔVLS
VINmax+ΔVLS − ΔVHS
(32) where ΔV
HS
and ΔV
LS
are the voltage drop across the high-side and low-side MOSFETs respectively.
The AC component of the input current (see Figure 41) flows in the input capacitor, generating the input voltage ripple.
Figure 42. Input capacitor AC current
DS13481 - Rev 2
The peak-to-peak voltage across the input capacitor can be calculated as follows:
VPP=
IOUT_pri+IOUT_sec∙
CIN∙fSW
Nsec
Npri
∙Dη∙ 1−
D
η +ESR∙ IOUT_pri+IOUT_sec+
(33)
In the case of negligible ESR (e.g. in case of MLCC capacitors) equation (33) can be simplified. The value of the input capacitor can be then derived:
CIN =
IOUT_pri+IOUT_sec∙
VPP∙fSW
Nsec
Npri
∙Dη∙ 1−
D
η
(34)
Considering the ideal case of η = 1, the equation above reaches its maximum value when D = 0.5. Therefore, the minimum input capacitance value can be defined as follows: page 36/62
A6986I
Design of the external components
CIN≥CINmin =
IOUT_pri+IOUT_sec∙
4∙VPP∙fSW
Nsec
Npri
∙ (35)
Typically, C
IN
is dimensioned to keep the maximum peak-to-peak voltage across the input filter in the order of 5% of V
INmax
.
DS13481 - Rev 2 page 37/62
7.5.2
A6986I
Design of the external components
•
•
Transformer selection
The transformer has two essential tasks:
Providing the isolation between primary and secondary side in accordance with the application requirements
Generating the necessary secondary output voltage from the regulated primary voltage with the most suitable turn ratio
•
•
•
•
•
•
The transformer selection implies defining the following parameters:
• Isolation voltage
Turn ratio
Primary inductance
Peak and RMS currents
Windings resistance
Leakage inductance
Parasitic capacitances
Isolation voltage
The isolation of the transformer in terms of voltage capability (1.5 kV, 4 kV, and so on) and type (functional basic, reinforced, etc.) is mainly driven by the application. Both parameters normally affect the size of the transformer as well as other electrical characteristics (e.g. winding resistance, leakage inductance, etc.).
Turn Ratio
Naming N pri
and N sec
the number of turns of the primary and secondary windings respectively, the turn ratio is so defined:
N =
Npri
Nsec
Considering equation (25), the turn ratio must be defined so that the voltage at the secondary output is the desired one over the whole secondary output current range:
(36)
N ≥
VOUT_sec+ Rwind_sec∙IOUT_sec + VFD1
VOUT_pri+IOUTpri∙ RDS on LS+Rwind_pri
(37)
If no current is drawn from the primary output, the turn ratio should be only chosen to compensate the drops due to the secondary winding resistance and the Schottky diode.
The effect of the leakage inductance on the secondary output voltage regulation (not included in the equation above) should be taken into account too. Figure 17 clearly shows how the secondary output voltage can drift due to the leakage inductance.
Primary inductance
The choice of the primary inductance does not differ so much from a standard buck. The magnetizing current,
(see figure below) which combines the two winding currents, has the same shape of the buck inductor current and can be defined as:
IL_mag = Ipri+N∙Isec (38)
DS13481 - Rev 2 page 38/62
DS13481 - Rev 2
A6986I
Design of the external components
Figure 43. Primary (blue) winding current, secondary (pink) winding current and magnetizing current
(black)
I
Lpri_pos_peak
I
Lpri
I
Lpri_neg_peak
I
Lsec_peak
I
Lsec
LX
Therefore, setting the current ripple ΔI
L
, the inductance is so defined:
Lpri =
VIN − VOUT_pri ∙VOUT_pri
VIN∙fSW∙∆IL
(39)
For example, assuming I
OUT_prim of the total current I
OUT_pri
= 500 mA, I
+ N×I
OUT_sec
OUT_sec
= 100 mA, N= 5, the current ripple can be set around 30%
= 1A, therefore 300 mA. If V
IN
= 12 V, V
OUT_pri
= 5 V and f
SW
= 500 kHz, the inductor value should be 19.4 µH (and 18 µH or 22 µH the closest standardized value).
Peak and RMS current
As any inductor, peak and RMS current for each winding must be calculated in order to define saturation and
RMS currents that the transformer should fulfill.
For the primary winding, the equations below are valid:
Ipri_pos_peak = IOUT_pri+
IOUT_sec
N
+
ΔIpri
2
(40)
Ipri_RMS = IOUT_pri+
IOUT_sec
N
ΔIpri∙N
N∙IOUT_pri+IOUT_sec
For the secondary winding the peak current can change depending on the leakage inductance. In the image below secondary winding current waveforms with different leakage inductances are simulated. It is evident how the peak current can significantly vary. Considering the target leakage inductance value for an iso-buck
(recommended up to 1% of the primary inductance), the waveform can be approximated with a sawtooth shape and the peak and RMS currents can be hence estimated as:
(41)
Isec_pos_peak = (42)
(43)
A duty cycle higher than 50-60% significantly increases the peak current in the secondary winding. Furthermore, this affects the negative peak current at the primary side (see Figure 44).
page 39/62
DS13481 - Rev 2
A6986I
Design of the external components
Figure 44. Secondary winding positive peak current dependency on duty cycle (I
OUT_sec
= 100 mA)
2.5
2
1.5
1
0.5
0
0.1
0.2
0.3
0.4
0.5
Duty cycle
0.6
0.7
0.8
0.9
Figure 45. Primary negative peak current dependency on duty cycle (V
OUT_pri
= 5 V, I
OUT_pri
= 0, I
OUT_sec
=
100 mA, N = 6, f
SW
= 500 kHz, L = 19 µH)
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
0.1
0.2
typ. reverse current limit threhsold
0.3
0.4
Duty cycle
0.5
0.6
Reverse current limit already triggered
0.7
0.8
Windings resistance
Winding resistances should be minimized as much as possible since they affect the secondary output load regulations. They also contribute to power losses, therefore affecting the efficiency of the total solution.
Leakage inductance
The leakage inductance of a transformer can be defined as an undesired inductive component due to the not perfect magnetic linking of the two windings. Leakage inductance is inherent to the transformer construction and can only be reduced but not eliminated.
page 40/62
A6986I
Design of the external components
As shown in Figure 45 (resulting from a simulation), the leakage inductance affects the shape of the secondary winding current. In general, a very low leakage inductance implies that the current in the secondary winding can quickly ramp up, allowing the charge of the secondary output capacitor and supporting the load current demand.
A high leakage inductance slows down the secondary winding current rise, limiting the charge delivery to the output. Comparing solutions with different values of transformer leakage inductance shows that higher leakage inductance transformers are characterized by poorer load regulation performances.
In addition, higher leakage inductance means a reduction of the effective current slope in the primary winding, therefore increasing the duty cycle. As a consequence, the Schottky diode conduction time shortens, and higher peak and RMS current are present at the secondary winding. Higher peaks at light load negatively impact the load regulation.
Figure 46. Secondary winding current according to different leakage inductances (simulation)
L
LEAKAGE
= 50nH
L
LEAKAGE
= 200nH
L
LEAKAGE
= 2µH
•
•
Another effect of the leakage inductance is the ringing observed when the transition from the off-phase to on-phase occurs. These oscillations are due to the LC circuit represented by the leakage inductance and the total parasitic capacitance observed by the primary winding. This capacitance consists of several contributions:
•
Primary winding capacitance
Secondary winding capacitance, reflected in the primary side
Reverse capacitance of the Schottky diode, reflected in the primary side
L
LEAKAGE
= 2µH
The ringing at primary side could affect the regulation loop and falsely trigger the internal comparator, turning off the high-side MOSFET, although it should be kept on. This might result in undesired jitter at switch node.
A proper masking time (T
ON MIN
) filters these oscillations, which otherwise can affect the loop on the primary side.
Nevertheless, a snubber circuit to dump this ringing is always recommended, as shown in the figure below.
Figure 47. Snubber circuit
DS13481 - Rev 2
Capacitance page 41/62
A6986I
Design of the external components
The parasitic capacitance of a real transformer mainly consists of the following contributions:
•
•
Capacitance across each winding (C
P
and C
S
, in the image below) due to the capacitve coupling between the coil and the core. As already mentioned, the winding capacitances are involved in the ringing observed during transition from the off- to on-phase of the primary side
Interwinding capacitance (C
WW
), which is the capacitance between windings. The interwinding capacitance should be reduced in order to limit disturbance on the primary side due to possible steep voltage transitions present in the load connected to the secondary output.
Figure 48. Transformer parasitic capacitances
C
WW
C
P
C
S
7.5.3
7.5.4
•
Schottky diode
•
•
The selection of the Schottky diode should consider the following parameters:
• Maximum forward current, mainly defined by the secondary output current demand (see equation (43));
Forward voltage drop, which affects the secondary output voltage regulation
Maximum peak reverse voltage. During the on-phase of the primary side, when in the secondary side no current flows, the diode is reverse biased and must withstand this voltage:
VD1_rev = N∙ VINmax − VOUT_pri +VOUT_sec
Junction capacitance, which should be as low as possible in order to reduce the ringing described in the previous section
(44)
Output capacitors selection
•
•
Primary output capacitor
As in a standard buck converter, the primary output capacitor is involved in:
•
Determining the output voltage ripple
Supporting load transient
The loop stability, by setting one pole and one zero in the transfer function
Considering the ouput voltage ripple requirement, the primary output capacitance should be selected according to the following equation:
COUT_pri=
ΔIpri
8∙fSW∙ ΔVOUT_pri − ESR∙ΔIpri
Normally, MLCC capacitors are the best choice for the output capacitor, therefore the ESR contribution is negligible and equation (46) can be simplified.
Secondary output capacitor
The secondary output capacitor supplies the secondary output load current during the t
ON
(when diode D1 is reverse biased) and its value defines the secondary output voltage ripple (ΔV
OUT
).
COUT_sec=
IOUT_sec∙D
ΔVOUT_sec∙fSW
(45)
(46)
DS13481 - Rev 2 page 42/62
8
A6986I
Application example
Application example
The target of this section is to show a typical application example as well as to describe the expected performances.
The schematic below depicts a typical application where an isolated voltage (single) together with a not isolated voltage is required.
Figure 49. Typical schematic with load applied to both the isolated and not isolated outputs
This application generates 5 V at the primary output (not isolated) with a switching frequency of 500 kHz. The secondary voltage (isolated) is generated by a transformer with a 1:5.8 turn ratio. The voltage between V
OUT_sec+ and V
OUT_sec-
changes with the current drawn from the load. A post-regulation is necessary to keep this voltage stable.
Maximum deliverable current in an iso-buck topology must take into account equations (5) and (6). According to how much current is drawn from the isolated and not isolated outputs, I
PEAKHS
or I
PEAKLS
is the most stringent parameter.
DS13481 - Rev 2 page 43/62
A6986I
Application example
Considering the schematic above and the components included, the graph below gives an idea about how much current, under these application conditions, can be drawn at the same time from the not isolated and isolated outputs, with different input voltages.
Figure 50. Maximum deliverable currents to the isolated and not isolated outputs
0.5
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
1 10
I
OUT_prim
[mA]
100
VIN = 9 V
VIN = 12 V
VIN = 18 V
VIN = 24 V
1000
DS13481 - Rev 2 page 44/62
9
A6986I
Application board
Application board
The reference evaluation board schematic is shown in the figure below.
Figure 51. STEVAL-A6986IV1 evaluation board schematic
EMI FIlter
R16
VIN
TP5
L4
C20
C18
GNDpri
TP4
L3
C19
R18
R17
4 1 U1
SYNCH
6
3
8
15
2
5
VIN
VCC
FSW
MLF
SS/INH
DELAY
EP SGND
17 10
RST
PGND
11
LX
LX
VBIAS
FB
COMP
PGND
12
13
14
16
9
7
GND1
C5
R3
C4
R2
R1
3
4
1
2
3
4
1
2
U2
8
7
6
5
8
7
6
5
TP6
VOUT1
C11
GND1
TP7
GND1
GND1
C16
GND2
TP12
VOUT2
R8
C15
2
D1
1
C17
R11
U3
GND2
TP11
GND2
D3
Q1 optional circuitry for improved load regulation
VISO+ TP8 VISO+
C21 R12
R13
C13
GNDiso TP9
GNDiso
C12
VISOTP10 VISO-
EMI FIlters
R16
VIN
TP5
GNDpri
TP4
L4
C20
C18
L3
C19
Figure 52. STEVAL-L6986IV1 evaluation board schematic
R18
R17
U1
4 1
15
2
5
6
3
8
17
SYNCH
VIN
VCC
FSW
MLF
SS/INH
DELAY
EP SGND
10
RST
PGND
11
LX
LX
VBIAS
FB
COMP
PGND
12
13
14
16
9
7
C5
R3
GND1
R1
1
4
5
2
3
3
4
1
2
5
U4
10
10
9
8
7
6
TP6
VOUT1
7
6
9
8
C4 R2
C11
GND1
TP7
GND1
GND1
C16
GND2
R8
2
D1
TP12
VOUT2
C15
1
C17
R11
GND2
TP11
GND2
Q1 optional circuitry for improved load regulation
U3
C21
D3
R12
VISO+ TP8 VISO+
R13
C13
GNDiso TP9
GNDiso
C12
VISOTP10 VISO-
EMI FIlter
R16
VIN
TP5
L4
C20
C18
GNDpri
TP4
L3
C19
Figure 53. STEVAL-A6986IV2 evaluation board schematic
R18
R17
4 1 U1
5
6
3
8
15
2
VIN
VCC
FSW
MLF
SS/INH
DELAY
SYNCH
EP
17
SGND
10
RST
PGND
11
LX
LX
VBIAS
FB
COMP
PGND
12
13
14
16
9
7
GND1
C5
R3
C4
R2
R1
3
4
1
2
1
2
3
4
U2
8
7
6
5
8
7
6
5
TP6
VOUT1
C11
GND1
TP7
GND1
C16
GND1 GND2
TP12
VOUT2
R8
C15
2
D1
1
C17
R11
GND2
TP11
GND2
Q1 optional circuitry for improved load regulation
VISO+ TP8 VISO+
U3
C21
R12
R13
C13
GNDiso TP9
GNDiso
The additional input filter (C20, L4, C18, L3, C19) limits the conducted emission on the power supply. In case the filter is not necessary or should be by-passed for any test, a 0 Ω resistor can be placed at R16.
The evaluation board of the iso-buck is available with three different assemblies, mainly differentiated by the isolation of the transformer (3.3 kV / 1.5 kV) and the isolated output options (single or dual voltage), as summarized in the following table.
DS13481 - Rev 2 page 45/62
DS13481 - Rev 2
A6986I
Application board
Assembly
#1
#2
#3
U1
C12
C15
R8
R11
R12
R13
Reference
R1
R2
R3
C16
C17
C18
C19
C20
C1
C2
C4
C5
C8, C11
C9
#1, #3
#2
#1, #2
#3
C13
#1, #2
#3
#1, #2
#3
#1, #2
#3
#1
#2
#3
#1
#2
#3
R16
Board name
STEVAL-A6986IV1
STEVAL-L6986IV1
STEVAL-A6986IV2
Table 10. Type of the evaluation boards
Single/dual isolated output(s)
Dual
Dual
Single
Available isolated voltages
V
ISO+
= 18 V, V
ISO-
= -4.5 V
V
ISO+
= 18 V, V
ISO-
= -4.5 V
V
ISO+
= 5 V
Table 11. BOM of the evaluation boards
Part number
A6986I
L6986I
Description
CGA5L1X7R1H106K160AC
CEU4J2X7R1H104K125AE
CGA4J3X7R1H105K125AB
CGA4J3X7R1H105K125AB
470 nF, 10 V, 0603
68 nF, 10 V, 0603
4.7 pF, 10 V, 0603
680 pF, 10 V, 0603
10 µF, 50 V, 1206
100 nF, 50 V, 0805
1 µF, 50 V, 0805
N/A
1 µF, 50 V, 0805
82 pF, 10 V, 0603
68 pF, 10 V, 0603 not mounted
CNA6P1X7R1H106K250AE
CGA5L3X5R1H475K
CGA5L3X5R1H475K
CGA5L3X5R1H475K
10 µF, 50 V, 1210
4.7 µF, 50 V, 1206
4.7 µF, 50 V, 1206
4.7 µF, 50 V, 1206
6.8 kΩ, 1%
1.3 kΩ, 1%
56 kΩ, 1%
620 Ω, 1%
180 Ω, 1%
430 Ω, 1%
100 Ω, 1%
36 kΩ, 1%
22 kΩ, 1%
10.7 kΩ, 1%
5.6 kΩ, 1%
4.3 kΩ, 1%
11 kΩ, 1%
Not mounted
Manufacturer
STM
TDK
TDK
TDK
TDK
TDK
TDK
TDK
TDK page 46/62
9.1
A6986I
Fine tuning of the evaluation boards
D3
Reference
R17
R18
L3
L4
D1
#1, #2
#3
Q1
#1
U2
#2
#3
U3
Part number
XAL4030-472MEC
MPZ2012S221A
STPS1150AY
BZT52B4V3-HE3-08
-
2STR1215
ZA9668-AE
2106.0007
ZB1175-AE
TL431AIL3T
Description Manufacturer
4.7 µH
Ferrite bead
Schottky diode, 150 V, 1 A
Zener diode 4.3 V
N/A
NPN power transistor
Transformer, N = 5.8,
3.3 kV isolation
Transformer, N = 5.6,
1.5 kV isolation
Transformer, N = 1.53, 3.3
kV isolation
Adjustable voltage reference
Coilcraft
TDK
STM
Vishay Semiconductor
STM
Coilcraft
Magnetica
Coilcraft
STM
Fine tuning of the evaluation boards
The evaluation boards can be customized to better match the user demands.
1.
If a different dual isolated voltage is necessary (e.g. 15 V / - 6 V), the replacement of two components is enough to adapt the board: the Zener diode D3 (with a diode providing the most suitable Zener voltage) and the resistor divider (one of the two resistors) R12 - R13, in accordance with the equation:
VISO+= 2.49V∙
R12+R13
R13
Obviously, the total voltage V
ISO+
+ |V
ISOwinding of the transformer.
| must be compatible with the available voltage at the secondary
(47)
2.
STEVAL-A6986IV1 and STEVAL-L6986IV1 can be also turned into a single isolated voltage board by soldering a 0 Ω resistor in place of the capacitor C12.
Any of the above-mentioned fine tunings could require an adjustment of the resistor R11.
DS13481 - Rev 2 page 47/62
Figure 54. STEVAL-A6986IV1 (top layer)
A6986I
Fine tuning of the evaluation boards
Figure 55. STEVAL-A6986IV1 (bottom layer)
DS13481 - Rev 2 page 48/62
Figure 56. STEVAL-L6986IV1 (top layer)
A6986I
Fine tuning of the evaluation boards
Figure 57. STEVAL-L6986IV1 (bottom layer)
DS13481 - Rev 2 page 49/62
Figure 58. STEVAL-A6986IV2 (top layer)
A6986I
Fine tuning of the evaluation boards
Figure 59. STEVAL-A6986IV2 (bottom layer)
DS13481 - Rev 2 page 50/62
9.2
A6986I
Load regulation of the evaluation boards
Load regulation of the evaluation boards
Figure 60. STEVAL-A6986IV1, V
IN
= 12 V, f
SW
= 500 kHz
19
18.9
18.8
18.7
18.6
18.5
18.4
18.3
18.2
18.1
18
0 20 40 60
Output current [mA]
80 100
4.9
4.8
5
4.7
4.6
4.5
4.4
4.3
4.2
4.1
4
0
Figure 61. STEVAL-A6986IV1, V
IN
= 12 V, f
SW
= 500 kHz
20 40 60
Output current [mA]
80 100
DS13481 - Rev 2 page 51/62
DS13481 - Rev 2
A6986I
Load regulation of the evaluation boards
Figure 62. STEVAL-L6986IV1, V
IN
= 12 V, f
SW
= 500 kHz
19
18.9
18.8
18.7
18.6
18.5
18.4
18.3
18.2
18.1
18
0 20 40 60
Output current [mA]
80 100
5
4.9
4.8
4.7
4.6
4.5
4.4
4.3
4.2
4.1
4
0
Figure 63. STEVAL-L6986IV1, V
IN
= 12 V, f
SW
= 500 kHz
20 40 60
Output current [mA]
80 100
5.25
5.2
5.15
5.1
5.05
5
4.95
4.9
4.85
4.8
4.75
0
Figure 64. STEVAL-A6986IV2, V
IN
= 12 V, f
SW
= 500 kHz
50 100 150 200 250 300
Output current [mA]
350 400 450 500 page 52/62
10
10.1
A6986I
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
HTSSOP16 package information
Figure 65. HTSSOP16 package outline
DS13481 - Rev 2 page 53/62
Symbol
D
D1
E
E1
E2
A
A1
A2 b c e
L
L1
K aaa
Table 12. HTSSOP16 mechanical data
Min.
mm
Typ.
0.80
0.19
0.09
4.90
2.8
6.20
4.30
2.8
0.45
0.00
1.00
5.00
3
6.40
4.40
3
0.65
0.60
1.00
A6986I
HTSSOP16 package information
0.75
8.00
0.10
Max.
5.10
3.2
6.60
4.50
3.2
1.20
0.15
1.05
0.30
0.20
DS13481 - Rev 2 page 54/62
A6986I
Ordering information
11
Ordering information
Part number
A6986I
A6986ITR
Table 13. Ordering information
Package
HTSSOP16
Packing
Tube
Tape and reel
DS13481 - Rev 2 page 55/62
Revision history
Date
26-Mar-2021
26-May-2021
Table 14. Document revision history
Version
1
2
Changes
First release.
Updated Features on the cover page.
A6986I
DS13481 - Rev 2 page 56/62
A6986I
Contents
Contents
DS13481 - Rev 2 page 57/62
A6986I
Contents
DS13481 - Rev 2 page 58/62
A6986I
List of tables
List of tables
Table 5. Electrical characteristics (T
= 12 V unless otherwise specified). . . . . . . . . . . . . . . . . . . . . . 5
= 12 V unless otherwise specified). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 7. RST threshold selection (T
= 12 V unless otherwise specified).. . . . . . . . . . . . . . . . . . . . . . 7
DS13481 - Rev 2 page 59/62
A6986I
List of figures
List of figures
Figure 14. Remaining oscillations filtered by the masking time and RC snubber circuit V
Figure 24. Peak currents depending on the secondary output current (V
Figure 44. Secondary winding positive peak current dependency on duty cycle (I
= 100 mA). . . . . . . . . . . . . . . . 40
Figure 45. Primary negative peak current dependency on duty cycle (V
DS13481 - Rev 2 page 60/62
A6986I
List of figures
DS13481 - Rev 2 page 61/62
A6986I
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks . All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2021 STMicroelectronics – All rights reserved
DS13481 - Rev 2 page 62/62
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