STMicroelectronics R7985A Datasheet
Annons
Annons
R7985A
2 A step-down switching regulator for aerospace applications
HSOP8 exposed pad
Features
General features
– 2 A DC output current
– 4.5 V to 38 V input voltage
– Output voltage adjustable from 0.6 V
– Large ambient temperature range:
-40 °C to 125 °C
– 250 kHz switching frequency, programmable up to 1 MHz
– Internal soft-start and enable
– Low dropout operation: 100% duty cycle
– Voltage feed-forward
– Zero load current operation
– Overcurrent and thermal protection
– HSOP8 package
Aerospace and defense features
– Suitable for use in aerospace and defense applications
– Dedicated traceability and part marking
– Production parts approval documents available
– Adapted extended life time and obsolescence management
– Extended product change notification process
– Designed and manufactured to meet subppm quality goals
– Advanced mold and frame designs for superior resilience in harsh environments
(acceleration, EMI, thermal, humidity)
– Extended screening capability on request
Datasheet
-
target specification
Applications
Dedicated to aerospace applications
Aerospace LED driving
Description
The R7985A is a step-down switching regulator with a 2.5 A (minimum) current limited embedded power MOSFET, so it is able to deliver up to 2 A current to the load depending on the application conditions.
The input voltage can range from 4.5 V to 38 V, while the output voltage can be set starting from
0.6 V to V
IN
.
Requiring a minimum set of external components, the device includes an internal 250 kHz switching frequency oscillator that can be externally adjusted up to 1 MHz. The large ambient temperature range makes it ideal for aerospace and defense applications.
The HSOP8 package with exposed pad allows the reduction of R th(JA)
down to 40 °C/W.
October 2014 DocID026995 Rev 1
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.
1/41 www.st.com
Contents
Contents
R7985A
Oscillator and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Error amplifier and compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Hysteretic thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Type III compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Type II compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2/41 DocID026995 Rev 1
R7985A
Contents
DocID026995 Rev 1 3/41
41
List of tables
List of tables
R7985A
4/41 DocID026995 Rev 1
R7985A
List of figures
List of figures
Sawtooth: voltage and frequency feed-forward; external synchronization . . . . . . . . . . . . . 12
Open loop gain Bode diagram with electrolytic/tantalum output capacitor . . . . . . . . . . . . . 29
Maximum output current according to max. DC switch current (2.0 A): V
O
= 12 V. . . . . . . 34
Maximum output current according to switch max. peak current (2.0 A): V
= -5 V. . . . . . 36
DocID026995 Rev 1 5/41
41
Pin settings R7985A
Figure 1. Pin connection (top view)
6/41
3
4
5
6
7
8
No.
1
2
Type
OUT
SYNCH
EN
COMP
FB
FSW
GND
V
CC
Table 1. Pin description
Description
Regulator output.
Master/slave synchronization. When it is left floating, a signal with a phase shift of half a period in respect to the power turn-on is present at the pin. When connected to an external signal at a frequency higher than the internal one, the device is synchronized by the external signal, with zero phase shift.
Connecting together the SYNCH pins of two devices, the one with the higher frequency works as master and the other as slave; so the two power turn-ons have a phase shift of half a period.
A logical signal (active high) enables the device. With EN higher than
1.2 V the device is ON and with EN lower than 0.63 V the device is OFF.
Error amplifier output to be used for loop frequency compensation.
Feedback input. Connecting the output voltage directly to this pin the output voltage is regulated at 0.6 V. To have higher regulated voltages an external resistor divider is required from V
OUT to the FB pin.
The switching frequency can be increased connecting an external resistor from the FSW pin and ground. If this pin is left floating the device works at its free-running frequency of 250 KHz.
Ground.
Unregulated DC input voltage.
DocID026995 Rev 1
R7985A Maximum ratings
Symbol
Table 2. Absolute maximum ratings
Parameter
V cc
OUT
Input voltage
Output DC voltage
F
SW
, COMP, SYNCH Analog pin
EN Enable pin
FB
P
TOT
T
J
T stg
Feedback voltage
Power dissipation at T
A
< 60 °C
Junction temperature range
Storage temperature range
HSOP8
Value
45
-0.3 to V
CC
-0.3 to 4
-0.3 to V
CC
-0.3 to 1.5
2
-40 to 150
-55 to 150
Unit
V
W
°C
°C
Symbol
Table 3. Thermal data
Parameter
R th(JA)
Maximum thermal resistance junction ambient
1. Package mounted on demonstration board.
(1)
HSOP8
Value
40
Unit
°C/W
DocID026995 Rev 1 7/41
41
Electrical characteristics R7985A
T
J
= -40 °C to 125 °C, V
CC
= 12 V, unless otherwise specified.
Table 4. Electrical characteristics
Symbol Parameter Test conditions
V
CC
V
CCON
V
CCHYS
R
DS(on)
I
LIM
Oscillator
Operating input voltage range
Turn-on V
CC
threshold
V
CC
UVLO hysteresis
MOSFET on-resistance
Maximum limiting current
F
SW
V
FSW
D
F
ADJ
Switching frequency
FSW pin voltage
Duty cycle
Adjustable switching frequency
Dynamic characteristics
V
FB
Feedback voltage
DC characteristics
I
Q
I
QST-BY
Enable
Quiescent current
Total standby quiescent current
R
FSW
= 33 k
4.5 V < V
CC
< 38 V
Duty cycle = 0, V
FB
= 0.8 V
V
EN
I
EN
Soft-start
EN threshold voltage
EN current
Device OFF level
Device ON level
EN = V
CC
FSW pin floating
F
SW
= 1 MHz, R
FSW
= 33 k
T
SS
Soft-start duration
Error amplifier
V
CH
V
CL
I
O SOURCE
I
O SINK
G
V
High level output voltage
Low level output voltage
Source COMP pin
Sink COMP pin
Open loop voltage gain
V
V
FB
FB
V
FB
(1)
< 0.6 V
> 0.6 V
= 0.5 V, V
COMP
V
FB
= 0.7 V, V
COMP
= 1 V
= 0.75 V
1.2
7.3
3
Values
Min.
Typ.
Max.
4.5
0.1
2.5
210
0
200
20
7.5
8.2
2
19
30
100
38
4.5
0.4
2.4
30
0.3
10
9.8
0.1
Unit
V
400 m
3.5
A
250
1.254
1000
275 kHz
V
100 % kHz
0.588
0.6
0.612
V mA
A
V
µA ms
V mA mA dB
8/41 DocID026995 Rev 1
R7985A Electrical characteristics
Symbol
Table 4. Electrical characteristics (continued)
Parameter Test conditions
Values
Min.
Typ.
Max.
Unit
Synchronization function
V
S_IN,HI
V
S_IN,LO
High input voltage
Low input voltage
2 3.3
1
V t
S_IN_PW
Input pulse width
I
SYNCH,LO
V
S_OUT,HI t
S_OUT_PW
Protection
Slave sink current
Master output amplitude
Output pulse width
T
SHDN
Thermal shutdown
Hysteresis
1. Guaranteed by design.
V
S_IN,HI
= 3 V, V
S_IN,LO
= 0 V
V
S_IN,HI
= 2 V, V
S_IN,LO
= 1 V
V
SYNCH
= 2.9 V
I
SOURCE
= 4.5 mA
SYNCH floating
100
300
2
0.7
110
150
30
1 ns mA
V ns
°C
DocID026995 Rev 1 9/41
41
Functional description R7985A
The R7985A device is based on a “voltage mode”, constant frequency control. The output voltage V
OUT
is sensed by the feedback pin (FB) compared to an internal reference (0.6 V) providing an error signal that, compared to a fixed frequency sawtooth, controls the ON and
OFF time of the power switch.
The main internal blocks are shown in the block diagram in
. They are:
A fully integrated oscillator that provides sawtooth to modulate the duty cycle and the synchronization signal. Its switching frequency can be adjusted by an external resistor.
The voltage and frequency feed-forward are implemented
Soft-start circuitry to limit inrush current during the startup phase
Voltage mode error amplifier
Pulse width modulator and the relative logic circuitry necessary to drive the internal power switch
High-side driver for embedded P-channel power MOSFET switch
Peak current limit sensing block, to handle overload and short-circuit conditions
A voltage regulator and internal reference. It supplies internal circuitry and provides a fixed internal reference
A voltage monitor circuitry (UVLO) that checks the input and internal voltages
A thermal shutdown block, to prevent thermal runaway.
Figure 2. Block diagram
CURRENT
LIMIT
SOFT-
START
10/41
FSW GND
DocID026995 Rev 1
R7985A Functional description
5.1 Oscillator synchronization
Figure 3 shows the block diagram of the oscillator circuit. The internal oscillator provides
a constant frequency clock. Its frequency depends on the resistor externally connected to the FSW pin. If the FSW pin is left floating, the frequency is 250 kHz; it can be increased as
by an external resistor connected to ground.
To improve the line transient performance, keeping the PWM gain constant versus the input voltage, the voltage feed-forward is implemented by changing the slope of the sawtooth
according to the input voltage change (see Figure 4
.a).
The slope of the sawtooth also changes if the oscillator frequency is increased by the external resistor. In this way, a frequency feed-forward is implemented (
to keep the PWM gain constant versus the switching frequency (see
for PWM gain expression).
On the SYNCH pin the synchronization signal is generated. This signal has a phase shift of
180 ° with respect to the clock. This delay is useful when two devices are synchronized connecting the SYNCH pin together. When SYNCH pins are connected, the device with the higher oscillator frequency works as master, so the slave device switches at the frequency of the master but with a delay of half a period. This minimizes the RMS current flowing through the input capacitor (see the L5988D datasheet).
Figure 3. Oscillator circuit block diagram
The device can be synchronized to work at a higher frequency feeding an external clock signal. The synchronization changes the sawtooth amplitude, changing the PWM gain
(
Figure 4 .c). This change must be taken into account when the loop stability is studied. To
minimize the change of the PWM gain, the free-running frequency should be set (with a resistor on the FSW pin) only slightly lower than the external clock frequency. This preadjusting of the frequency changes the sawtooth slope in order to render negligible the truncation of sawtooth, due to the external synchronization.
DocID026995 Rev 1 11/41
41
Functional description R7985A
Figure 4. Sawtooth: voltage and frequency feed-forward; external synchronization
Figure 5. Oscillator frequency vs. the FSW pin resistor
12/41
5)6:>N2KPV@
DocID026995 Rev 1
R7985A Functional description where:
Equation 1
R
FSW
=
F
28.5 10
SW
–
9
3
–
F
SW is desired switching frequency.
3
5.2 Soft-start
Soft-start is essential to assure the correct and safe startup of the step-down converter. It avoids inrush current surge and makes the output voltage increase monothonically.
The soft-start is performed by a staircase ramp on the non inverting input (V
REF amplifier. So the output voltage slew rate is:
) of the error
Equation 2
SR
OUT
= SR
VREF
1 +
R1
R2
where SR
VREF
is the slew rate of the non inverting input, while R1 and R2 is the resistor divider to regulate the output voltage (see
Figure 6 ). The soft-start staircase consists of
64 steps of 9.5 mV each, from 0 V to 0.6 V. The time base of one step is of 32 clock cycles.
So the soft-start time and then the output voltage slew rate depend on the switching frequency.
Figure 6. Soft-start scheme
Soft-start time results:
Equation 3
SS
TIME
=
Fsw
For example, with a switching frequency of 250 kHz, the SS
TIME
is 8 ms.
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Functional description
5.3 Error amplifier and compensation
R7985A
The error amplifier (E/A) provides the error signal to be compared with the sawtooth to perform the pulse width modulation. Its non inverting input is internally connected to a 0.6 V voltage reference, while its inverting input (FB) and output (COMP) are externally available for feedback and frequency compensation. In this device the error amplifier is a voltage mode operational amplifier, so with high DC gain and low output impedance.
The uncompensated error amplifier characteristics are shown in
.
Table 5. Uncompensated error amplifier characteristics
Parameter Value
Low frequency gain
GBWP
Slew rate
Output voltage swing
Maximum source/sink current
100 dB
4.5 MHz
7 V/ s
0 to 3.3 V
17 mA/25 mA
In continuous conduction mode (CCM), the transfer function of the power section has two poles due to the LC filter and one zero due to the ESR of the output capacitor. Different kinds of compensation networks can be used depending on the ESR value of the output capacitor. In case the zero introduced by the output capacitor helps to compensate the double pole of the LC filter, a Type II compensation network can be used. Otherwise, a Type
III compensation network must be used (see Section 6.4 on page 21
for details of the compensation network selection).
The methodology to compensate the loop is to introduce zeroes to obtain a safe phase margin.
14/41
The R7985A implements the overcurrent protection sensing current flowing through the power MOSFET. Due to the noise created by the switching activity of the power MOSFET, the current sensing is disabled during the initial phase of the conduction time. This avoids an erroneous detection of a fault condition. This interval is generally known as “masking time” or “blanking time”. The masking time is about 200 ns.
If the overcurrent limit is reached, the power MOSFET is turned off, implementing the pulseby-pulse overcurrent protection. Under an overcurrent condition, the device can skip turn-on pulses in order to keep the output current constant and equal to the current limit. If, at the end of the “masking time”, the current is higher than the overcurrent threshold, the power
MOSFET is turned off and one pulse is skipped. If, at the following switching-on, when the
“masking time” ends, the current is still higher than the overcurrent threshold, the device skips two pulses. This mechanism is repeated and the device can skip up to seven pulses.
While, if at the end of the “masking time” the current is lower than the over current threshold,
the number of skipped cycles is decreased by one unit (see Figure 7
).
So the overcurrent/short-circuit protection acts by switching off the power MOSFET and reducing the switching frequency down to one eighth of the default switching frequency, in order to keep constant the output current around the current limit.
DocID026995 Rev 1
R7985A Functional description
This kind of overcurrent protection is effective if the output current is limited. To prevent the current from diverging, the current ripple in the inductor during the ON-time must not be higher than the current ripple during the OFF-time. That is:
Equation 4
V – V
OUT
– R I
SW
–
OUT
D =
V + V
F
+ R
DSON
I
OUT
+
-----------------------------------------------------------------------------------------------------------
SW
1 D
If the output voltage is shorted, V
OUT
0, I
OUT
= I
LIM
, D/F
SW
= T
ON_MIN
, (1-D)/F
SW
1/F
SW
.
So from the above equation the maximum switching frequency that guarantees to limit the current results:
Equation 5
F
*
SW
=
V
IN
–
V
R
F
+ DCR I
DSON
+
LIM
DCR
I
LIM
T
ON_MIN
With R
DS(on)
= 300 m , DRC = 0.08 , the worst condition is with V
IN
= 38 V, I
LIM
= 2.5 A; the maximum frequency to keep the output current limited during the short-circuit results
74 kHz.
Based on the pulse-by-pulse mechanism, that reduces the switching frequency down to one eighth, the maximum F
SW
, adjusted by the FSW pin, that assures a full effective output current limitation is 74 kHz * 8 = 592 kHz.
If, with V
IN
= 38 V, the switching frequency is set higher than 592 kHz, during short-circuit condition the system finds a different equilibrium with higher current. For example, with
F
SW
= 700 kHz and the output shorted to ground, the output current is limited around:
Equation 6
I
OUT
=
V
IN
F
*
– V
F
T
---------------------------------------------------------------------------------------------------------------= 3.68A
ON_MIN
+ R
DSON
+ DCR F
* where F
SW
* is 700 kHz divided by eight.
DocID026995 Rev 1 15/41
41
Functional description
Figure 7. Overcurrent protection
R7985A
The enable feature allows the device to be put into standby mode. With the EN pin lower than 0.3 V, the device is disabled and the power consumption is reduced to less than 30 A.
With the EN pin lower than 1.2 V, the device is enabled. If the EN pin is left floating, an internal pull-down ensures that the voltage at the pin reaches the inhibit threshold and the device is disabled. The pin is also V
CC
compatible.
The thermal shutdown block generates a signal that turns off the power stage if the junction temperature goes above 150 °C. Once the junction temperature goes back to about 120 °C, the device restarts in normal operation. The sensing element is very close to the PDMOS area, so ensuring an accurate and fast temperature detection.
16/41 DocID026995 Rev 1
R7985A
Figure 8. Application circuit
Application information
6.1 Input capacitor selection
The capacitor connected to the input must be capable of supporting the maximum input operating voltage and the maximum RMS input current required by the device. The input capacitor is subject to a pulsed current, the RMS value of which is dissipated over its ESR, affecting the overall system efficiency.
So the input capacitor must have an RMS current rating higher than the maximum RMS input current and an ESR value compliant with the expected efficiency.
The maximum RMS input current flowing through the capacitor can be calculated as:
Equation 7
I
RMS
= I
O
D –
2
--------------+
D
2
-------
2 where I o
is the maximum DC output current, D is the duty cycle, is the efficiency.
Considering = 1, this function has a maximum at D = 0.5 and it is equal to I o
/2.
In a specific application the range of possible duty cycles must be considered in order to find out the maximum RMS input current. The maximum and minimum duty cycles can be calculated as:
Equation 8
D
MAX
=
V
V
INMIN
+
–
V
V
F
SW
DocID026995 Rev 1 17/41
41
Application information R7985A and
Equation 9
D
MIN
=
V
V
INMAX
+
–
V
V
SW where V
F
is the forward voltage on the freewheeling diode and V
SW
is voltage drop across the internal PDMOS.
The peak-to-peak voltage across the input capacitor can be calculated as:
Equation 10
V
PP
=
C
IN
I
O
F
SW
1 – ----
D +
D
1 D +
O where ESR is the equivalent series resistance of the capacitor.
Given the physical dimension, ceramic capacitors can well meet the requirements of the input filter sustaining a higher input RMS current than electrolytic/tantalum types.
In this case, the equation of C
IN
as a function of the target V
PP
can be written as follows:
Equation 11
C
IN
=
V
PP
I
O
F
SW
1 – ----
D +
D
1 D neglecting the small ESR of ceramic capacitors.
Considering = 1, this function has its maximum in D = 0.5, therefore, given the maximum peak-to-peak input voltage (V
PP_MAX
), the minimum input capacitor (C
IN_MIN
) value is:
Equation 12
C
IN_MIN
=
I
O
PP_MAX
SW
Typically, C
IN of V
INMAX
.
is dimensioned to keep the maximum peak-to-peak voltage in the order of 1%
In
, some multi-layer ceramic capacitors suitable for this device are reported.
Manufacturer
Taiyo Yuden muRata
Table 6. Input MLCC capacitors
Series Cap value ( F)
UMK325BJ106MM-T
GMK325BJ106MN-T
GRM32ER71H475K
10
10
4.7
Rated voltage (V)
50
35
50
A ceramic bypass capacitor, as close to the VCC and GND pins as possible, so that additional parasitic ESR and ESL are minimized, is suggested in order to prevent instability on the output voltage due to noise. The value of the bypass capacitor can go from 100 nF to
1 µF.
18/41 DocID026995 Rev 1
R7985A Application information
The inductance value fixes the current ripple flowing through the output capacitor. So the minimum inductance value in order to have the expected current ripple must be selected.
The rule to fix the current ripple value is to have a ripple at 20% - 40% of the output current.
In continuous current mode (CCM), the inductance value can be calculated by the following equation:
Equation 13
I
L
=
V
IN
–
L
V
OUT
T
ON
=
V
L
+ V
F
T
OFF where T
ON fixed V
OUT
is the conduction time of the internal high-side switch and T
OFF time of the external diode [in CCM, F
SW
, is obtained at maximum T
OFF calculate minimum duty). So by fixing I
= 1/(T
ON
L
+ T
OFF
is the conduction
)]. The maximum current ripple, at
, that is at minimum duty cycle (see minimum inductance value can be calculated:
= 20% to 30% of the maximum output current, the
Equation 14
L
MIN
=
V
OUT
I
+
MAX
V
---------------------------
1 D
F
MIN
SW where F
SW
is the switching frequency, 1/(T
ON
+ T
OFF
).
For example, for V
OUT
= 5 V, V
IN
= 24 V, I inductance value to have I
L
= 30% of I
O
O
= 2 A and F
SW
= 250 kHz, the minimum
is about 28 H.
The peak current through the inductor is given by:
Equation 15
I = I
O
+
I
2
So if the inductor value decreases, then the peak current (that must be lower than the minimum current limit of the device) increases. According to the maximum DC output current for this product family (2 A), the higher the inductor value, the higher the average output current that can be delivered, without triggering the overcurrent protection.
In
some inductor part numbers are listed.
Manufacturer
Coilcraft
Wurth
SUMIDA
Table 7. Inductors
Series Inductor value ( H) Saturation current (A)
MSS1038
MSS1048
PD Type L
PD Type M
CDRH6D226/HP
CDR10D48MN
3.8 to 10
12 to 22
8.2 to 15
2.2 to 4.7
1.5 to 3.3
6.6 to 12
3.9 to 6.5
3.84 to 5.34
3.75 to 6.25
4 to 6
3.6 to 5.2
4.1 to 5.7
DocID026995 Rev 1 19/41
41
Application information
6.3 Output capacitor selection
R7985A
The current in the capacitor has a triangular waveform which generates a voltage ripple across it. This ripple is due to the capacitive component (charge or discharge of the output capacitor) and the resistive component (due to the voltage drop across its ESR). So the output capacitor must be selected in order to have a voltage ripple compliant with the application requirements.
The amount of the voltage ripple can be calculated starting from the current ripple obtained by the inductor selection.
Equation 16
V
OUT
= ESR I
MAX
+
I
MAX
OUT
f
SW
Usually the resistive component of the ripple is much higher than the capacitive one, if the output capacitor adopted is not a multi-layer ceramic capacitor (MLCC) with very low ESR value.
The output capacitor is important also for loop stability: it fixes the double LC filter pole and the zero due to its ESR. In
, how to consider its effect in the system stability is
illustrated.
For example, with V
OUT
= 5 V, V order to have a V
OUT
IN
= 24 V, I
= 0.01 · V
OUT
L
= 0.9 A (resulting by the inductor value), in
, if the multi-layer ceramic capacitors are adopted,
10 µF are needed and the ESR effect on the output voltage ripple can be neglected. In case of not-negligible ESR (electrolytic or tantalum capacitors), the capacitor is chosen taking into account its ESR value. So, in the case of 330 µF with ESR = 70 m the resistive component of the drop dominates and the voltage ripple is 43 mV
The output capacitor is also important to sustain the output voltage when a load transient with high slew rate is required by the load. When the load transient slew rate exceeds the system bandwidth the output capacitor provides the current to the load. So if the high slew rate load transient is required by the application, the output capacitor and system bandwidth must be chosen in order to sustain the load transient.
In
below some capacitor series are listed.
Manufacturer muRata
PANASONIC
SANYO
TDK
Series
GRM32
GRM31
ECJ
EEFCD
TPA/B/C
C3225
Table 8. Output capacitors
Cap value ( F) Rated voltage (V)
22 to 100
10 to 47
10 to 22
10 to 68
100 to 470
22 to 100
6.3 to 25
6.3 to 25
6.3
6.3
4 to 16
6.3
ESR (m )
< 5
< 5
< 5
15 to 55
40 to 80
< 5
20/41 DocID026995 Rev 1
R7985A Application information
The compensation network must assure stability and good dynamic performance. The loop of the R7985A is based on the voltage mode control. The error amplifier is a voltage operational amplifier with high bandwidth. So by selecting the compensation network the E/A is considered as ideal, that is, its bandwidth is much larger than the system one.
The transfer functions of the PWM modulator and the output LC filter are studied (see
). The transfer function of the PWM modulator, from the error amplifier output
(COMP pin) to the OUT pin, results:
Equation 17
G
PW0
=
V
IN s where V
S
is the sawtooth amplitude. As seen in
Section 5.1 on page 11 , the voltage feed-
forward generates a sawtooth amplitude directly proportional to the input voltage, that is:
Equation 18
V
S
=
IN
In this way the PWM modulator gain results constant and equal to:
Equation 19
G
PW0
=
V
V s
=
1
K
= 18
The synchronization of the device with an external clock provided through the SYNCH pin
can modify the PWM modulator gain (see Section 5.1 on page 11 to understand how this
gain changes and how to keep it constant in spite of the external synchronization).
Figure 9. The error amplifier, the PWM modulator and the LC output filter
DocID026995 Rev 1 21/41
41
Application information
6.4.1
R7985A
The transfer function on the LC filter is given by:
Equation 20
G
LC
=
1 +
2 f s
1 +
s
2 Q f
LC
+
2 s f
LC
2 where:
Equation 21 f
LC
=
2 L C
OUT
1 +
R
OUT
f zESR
=
2
1
OUT
Equation 22
Q =
R
OUT
L C
OUT
OUT
R
R
OUT
OUT
+
E SR
ESR
-----------------------------------------------------------------------------------------, R
OUT
=
V
OUT
OUT
As seen in Section 5.3 on page 14
, two different kinds of network can compensate the loop.
In the two following paragraphs the guidelines to select the Type II and Type III compensation network are illustrated.
Type III compensation network
The methodology to stabilize the loop consists in placing two zeroes to compensate the effect of the LC double pole, thereby increasing phase margin; then to place one pole in the origin to minimize the DC error on the regulated output voltage; finally to place other poles far from the zero dB frequency.
If the equivalent series resistance (ESR) of the output capacitor introduces a zero with a frequency higher than the desired bandwidth (that is: 2 ESR C < 1 / BW), the Type
OUT
III compensation network is needed. Multi-layer ceramic capacitors (MLCC) have very low
ESR (< 1 m ), with very high frequency zero, so a Type III network is adopted to compensate the loop.
In
Figure 10 , the Type III compensation network is shown. This network introduces two
zeroes (f
Z1
, f
Z2
) and three poles (f
P0
, f
P1
, f
P2
). They are expressed as:
Equation 23 f
Z1
=
2 C
3
1
R
1
R
3
f
Z2
=
4
4
Equation 24 f
P0
= 0 f
P1
=
2
1
R
3
C
3
f
P2
=
2 R
4
C
4
C
4
+
C
C
5
22/41 DocID026995 Rev 1
R7985A Application information
Figure 10. Type III compensation network
In
Figure 11 the Bode diagram of the PWM and LC filter transfer function [G
PW0 and the open loop gain [G
LOOP
(f) = G
PW0
· G
LC
(f) · G
TYPEIII
(f)] are drawn.
· G
LC
(f)]
Figure 11. Open loop gain: module Bode diagram
The guidelines for positioning the poles and the zeroes and for calculating the component values can be summarized as follows:
1.
Choose a value for R
1
, usually between 1 k and 5 k .
2. Choose a gain (R
4
/R
1
) in order to have the required bandwidth (BW), that means:
Equation 25
R
4
=
BW f
LC
1 where K is the feed-forward constant and 1/K is equal to 18.
DocID026995 Rev 1 23/41
41
Application information R7985A
4
by placing the zero at 50% of the output filter double pole frequency (f
LC
):
Equation 26
C
4
=
R
4
f
LC
5
by placing the second pole at four times the system bandwidth (BW):
Equation 27
C
5
=
2 R
4
C
C
4
4
– 1
5. Set also the first pole at four times the system bandwidth and also the second zero at the output filter double pole:
Equation 28
R
3
=
R
--------------------------
-----------------
LC
– 1
C
3
=
2 R
3
4 BW
The suggested maximum system bandwidth is equal to the switching frequency divided by
3.5 (F
SW
/3.5), so lower than 100 kHz if the F
SW
is set higher than 500 kHz.
For example, with V
OUT
= 5 V, V
IN
= 24 V, I
O
= 2 A, L = 22 H, C
OUT
= 22 F, and
ESR < 1 m , the Type III compensation network is:
Equation 29
R
1
= 4.99k
R
2
= 680 R
3
= 270 R
4
= 1.1k
C
3
= 4.7nF
C
4
= 47nF C
5
= 1pF
In
Figure 12 the module and phase of the open loop gain is shown. The bandwidth is about
32 kHz and the phase margin is 51°.
24/41 DocID026995 Rev 1
R7985A Application information
Figure 12. Open loop gain Bode diagram with ceramic output capacitor
DocID026995 Rev 1 25/41
41
Application information R7985A
If the equivalent series resistance (ESR) of the output capacitor introduces a zero with a frequency lower than the desired bandwidth (that is: 2 ESR C
OUT
> 1 / BW), this zero helps stabilize the loop. Electrolytic capacitors show not-negligible ESR (> 30 m ), so with this kind of output capacitor the Type II network combined with the zero of the ESR allows the stabilizing of the loop.
In
Figure 13 the Type II network is shown.
Figure 13. Type II compensation network
The singularities of the network are:
Equation 30 f
Z1
=
2
1
R
4
4
f
P0
= 0 f
P1
=
2 R
4
C
C
4
4
+
C
5
C
5
26/41 DocID026995 Rev 1
R7985A Application information
In
Figure 14 the Bode diagram of the PWM and LC filter transfer function [G
PW0 and the open loop gain [G
LOOP
(f) = G
PW0
· G
LC
(f) · G
TYPEII
(f)] are drawn.
· G
LC
(f)]
Figure 14. Open loop gain: module Bode diagram
The guidelines for positioning the poles and the zeroes and for calculating the component values can be summarized as follows:
1.
Choose a value for R
1
, usually between 1 k and 5 k , in order to have values of C4 and C5 not comparable with parasitic capacitance of the board.
2. Choose a gain (R
4
/R
1
) in order to have the required bandwidth (BW), that means:
Equation 31
R
4
=
f
------------
LC
2
f
ESR
V
V
IN
R
1 where f
ESR
is the ESR zero:
Equation 32 f
ESR
=
2
OUT and V
S
is the sawtooth amplitude. The voltage feed-forward keeps the ratio V
S
/V
IN
constant.
4
by placing the zero one decade below the output filter double pole:
Equation 33
C
4
=
2
10
R
4
LC
DocID026995 Rev 1 27/41
41
Application information R7985A
3
in order to place the second pole at four times the system bandwidth
(BW):
Equation 34
C
5
=
2 R
4
C
C
4
4
– 1
For example, with V
OUT
= 5 V, V
IN
= 24 V, I
O
= 2 A, L = 22 H, C
OUT
= 330 F, and
ESR = 70 m the Type II compensation network is:
Equation 35
R
1
= 1.1k
R
2
= 150 R
4
= 4.99k
C
4
= 180nF C
5
= 180pF
28/41 DocID026995 Rev 1
R7985A Application information
In
Figure 15 the module and phase of the open loop gain is shown. The bandwidth is about
36 kHz and the phase margin is 53 °.
Figure 15. Open loop gain Bode diagram with electrolytic/tantalum output capacitor
DocID026995 Rev 1 29/41
41
Application information R7985A
The thermal design is important to prevent the thermal shutdown of the device if the junction temperature goes above 150 °C. The three different sources of losses within the device are: a) conduction losses due to the not-negligible R
DS(on) equal to:
of the power switch; these are
Equation 36
P
ON
= R
DS on
I
OUT
2
D where D is the duty cycle of the application and the maximum R
DS(on)
overtemperature is
220 m . Note that the duty cycle is theoretically given by the ratio between V
OUT
and V
IN
, but actually it is quite higher to compensate the losses of the regulator. So the conduction losses increase compared with the ideal case.
b) switching losses due to power MOSFET turn-on and turn-off; these can be calculated as:
Equation 37
P
SW
= V
IN
I
OUT
T +
2
T
Fsw = V
IN
I
OUT
T
SW
F
SW where T
RISE
and T
FALL
are the overlap times of the voltage across the power switch (V
DS and the current flowing into it during turn-on and turn-off phases, as shown in
.
)
T
SW
is the equivalent switching time. For this device the typical value for the equivalent switching time is 40 ns.
Equation 38
P
Q
= V
IN
I
Q where I
Q
is the quiescent current (I
Q
= 2.4 mA).
The junction temperature T
J
can be calculated as:
Equation 39
T
J
= T
A
+ Rth
JA
P
TOT where T
A
is the ambient temperature and P
TOT
is the sum of the power losses just seen.
R th(JA)
is the equivalent thermal resistance junction to ambient of the device; it can be calculated as the parallel of many paths of heat conduction from the junction to the ambient.
For this device the path through the exposed pad is the one conducting the largest amount of heat. The R th(JA)
measured on the demonstration board described in the following paragraph is about 40 °C/W for the HSOP8 package.
30/41 DocID026995 Rev 1
R7985A
Figure 16. Switching losses
Application information
The PC board layout of the switching DC/DC regulator is very important to minimize the noise injected in high impedance nodes and interference generated by the high switching current loops.
In a step-down converter, the input loop (including the input capacitor, the power MOSFET and the freewheeling diode) is the most critical one. This is due to the fact that the high value pulsed current is flowing through it. In order to minimize the EMI, this loop must be as short as possible.
The feedback pin (FB) connection to the external resistor divider is a high impedance node, so the interference can be minimized by placing the routing of the feedback node as far as possible from the high current paths. To reduce the pick-up noise, the resistor divider must be placed very close to the device.
To filter the high frequency noise, a small bypass capacitor (220 nF - 1 µF) can be added as close as possible to the input voltage pin of the device.
Thanks to the exposed pad of the device, the ground plane helps to reduce the thermal resistance junction to ambient; so a large ground plane enhances the thermal performance of the converter allowing high power conversion.
DocID026995 Rev 1 31/41
41
Application information
In
Figure 17 a layout example is shown.
Figure 17. Layout example
R7985A
32/41 DocID026995 Rev 1
R7985A Application ideas
The R7985A can implement the step-up/down converter with a positive output voltage.
shows the schematic: one power MOSFET and one Schottky diode are added to the standard buck topology to provide a 12 V output voltage with input voltage from 4.5 V to
38 V.
Figure 18. Positive buck-boost regulator
The relationship between input and output voltage is:
Equation 40
V
OUT
= V
IN
so the duty cycle is:
Equation 41
D =
V
OUT
+ V
IN
The output voltage isn’t limited by the maximum operating voltage of the device (38 V), because the output voltage is sensed only through the resistor divider. The external power
MOSFET maximum drain to source voltage, must be higher than output voltage; the maximum gate to source voltage must be higher than the input voltage (in
, if V
IN higher than 16 V, the gate must be protected through a Zener diode and resistor).
is
The current flowing through the internal power MOSFET is transferred to the load only during the OFF time, so according to the maximum DC switch current (2.0 A), the maximum output current for the buck boost topology can be calculated from Equation 42 .
DocID026995 Rev 1 33/41
41
Application ideas R7985A
Equation 42
I
SW
=
I
OUT
1 D
2 A where I
SW
is the average current in the embedded power MOSFET in the ON time.
To chose the right value of the inductor and to manage transient output current, which, for a short time, can exceed the maximum output current calculated by Equation 42 , also the peak current in the power MOSFET must be calculated. The peak current, shown in
Equation 43 , must be lower than the minimum current limit (2.5 A).
Equation 43
I
SW,PK
=
I
OUT
1 D
1 +
2
3.7A
where r is defined as the ratio between the inductor current ripple and the inductor DC current.
Therefore, in the buck boost topology the maximum output current depends on the application conditions (firstly input and output voltage, secondly switching frequency and inductor value).
the maximum output current for the above configuration is depicted, varying the input voltage from 4.5 V to 38 V.
The dashed line considers a more accurate estimation of the duty cycles given Equation 44 , where power losses across diodes, the external power MOSFET, and the internal power
MOSFET are taken into account.
Figure 19. Maximum output current according to max. DC switch current (2.0 A):
V
O
= 12 V
34/41 DocID026995 Rev 1
R7985A Application ideas
Equation 44
D =
V
IN
– V
SW
V
– V
+
SWE
+
D
V
OUT
+ 2 V
D where V
D
is the voltage drop across the diodes, V
SW and V
SWE
across the internal and external power MOSFET.
The R7985A device can implement the step-up/down converter with a negative output voltage.
shows the schematic to regulate -5 V: no further external components are added to the standard buck topology.
The relationship between input and output voltage is:
Equation 45
V
OUT
= – V
IN
so the duty cycle is:
Equation 46
D =
V
OUT
V
OUT
V
IN
As in the positive one, in the inverting buck-boost the current flowing through the power
MOSFET is transferred to the load only during the OFF time. So according to the maximum
DC switch current (2.0 A), the maximum output current can be calculated from Equation 42 , where the duty cycle is given by Equation 46 .
Figure 20. Inverting buck-boost regulator
The GND pin of the device is connected to the output voltage so, given the output voltage, the input voltage range is limited by the maximum voltage the device can withstand across
VCC and GND (38 V). Therefore, if the output is -5 V, the input voltage can range from 4.5 V to 33 V.
DocID026995 Rev 1 35/41
41
Application ideas R7985A
As in the positive buck-boost, the maximum output current according to application conditions is shown in
. The dashed line considers a more accurate estimation of the duty cycles given by Equation 47 , where power losses across diodes and the internal power MOSFET are taken into account.
Equation 47
D =
– V
IN
–
V
V
OUT
SW
+
–
V
V
OUT
– V
D
Figure 21. Maximum output current according to switch max. peak current (2.0 A):
V
O
= -5 V
36/41 DocID026995 Rev 1
R7985A Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK is an ST trademark.
Figure 22. HSOP8 package outline
' PP7\S
( PP7\S
$0Y
DocID026995 Rev 1 37/41
41
Package information
Symbol
E1 e h
L k ccc
D
E b c
A
A1
A2
Table 9. HSOP8 package mechanical data
Dimensions (mm)
Min.
Typ.
0.00
1.25
0.31
0.17
4.80
5.80
3.80
0.25
0.40
0.00
4.90
6.00
3.90
1.27
Max.
1.70
0.150
0.50
1.27
8.00
0.10
0.51
0.25
5.00
6.20
4.00
R7985A
38/41 DocID026995 Rev 1
R7985A Ordering information
Order code
R7985A
R7985ATR
Table 10. Ordering information
Package
HSOP8
HSOP8
Packaging
Tube
Tape and reel
DocID026995 Rev 1 39/41
41
Revision history
Date
06-Oct-2014
Table 11. Document revision history
Revision Changes
1 Initial release.
R7985A
40/41 DocID026995 Rev 1
R7985A
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Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.
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ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2014 STMicroelectronics – All rights reserved
DocID026995 Rev 1 41/41
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