STMicroelectronics H3LIS331DL Datasheet

H3LIS331DL

MEMS motion sensor:

low-power high-g 3-axis digital accelerometer

Datasheet

-

production data

TFLGA 3x3x1.0 mm

3

16L

Features

 Wide supply voltage, 2.16 V to 3.6 V

 Low-voltage compatible IOs, 1.8 V

 Ultra-low power consumption down to 10 μ A in low-power mode

 ±100 g /±200 g /±400 g dynamically selectable full scales

 I

2

C/SPI digital output interface

 16-bit data output

 Sleep-to-wakeup function

 10000 g high-shock survivability

 ECOPACK

®

, RoHS and “Green” compliant

Description

The H3LIS331DL is a low-power highperformance 3-axis linear accelerometer belonging to the “nano” family, with digital I 2 C/SPI serial interface standard output.

The device features ultra-low power operational modes that allow advanced power saving and smart sleep-to-wakeup functions.

The H3LIS331DL has dynamically userselectable full scales of ±100 g /±200 g /±400 g and it is capable of measuring accelerations with output data rates from 0.5 Hz to 1 kHz.

The H3LIS331DL is available in a small thin plastic land grid array package (LGA) and it is guaranteed to operate over an extended temperature range from -40 °C to +85 °C.

Applications

 Shock detection

 Impact recognition and logging

 Concussion detection

Order codes

H3LIS331DL

H3LIS331DLTR

Table 1. Device summary

Temperature range [  C] Package

-40 to +85

-40 to +85

TFLGA 3x3x1.0 mm

3

16L

TFLGA 3x3x1.0 mm

3

16L

Packaging

Tray

Tape and reel

September 2013

This is information on a product in full production.

DocID023111 Rev 3 1/38 www.st.com

Contents

Contents

1

2

3

4

5

6

H3LIS331DL

Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.1

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.2

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1

Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3

Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3.1

2.3.2

SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

I 2

C - inter-IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.4

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.5

Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.5.1

2.5.2

2.5.3

Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Sleep-to-wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.1

Sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.2

IC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.3

Factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.1

Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.1

I 2

C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.1.1

I

2

C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.2

SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.2.1

5.2.2

5.2.3

SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

SPI read in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2/38 DocID023111 Rev 3

8

9

H3LIS331DL

7

Contents

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.1

WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.2

CTRL_REG1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.3

CTRL_REG2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.4

CTRL_REG3 [interrupt CTRL register] (22h) . . . . . . . . . . . . . . . . . . . . . . 27

7.5

CTRL_REG4 (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.6

CTRL_REG5 (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.7

HP_FILTER_RESET (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.8

REFERENCE (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.9

STATUS_REG (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.10

OUT_X_L (28h), OUT_X_H (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.11

OUT_Y_L (2Ah), OUT_Y_H (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.12

OUT_Z_L (2Ch), OUT_Z_H (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.13

INT1_CFG (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.14

INT1_SRC (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.15

INT1_THS (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.16

INT1_DURATION (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.17

INT2_CFG (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.18

INT2_SRC (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.19

INT2_THS (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.20

INT2_DURATION (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

DocID023111 Rev 3 3/38

38

List of tables

List of tables

H3LIS331DL

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

I

Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2

C slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 9.

Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 10.

SAD+Read/Write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 11.

Transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 12.

Transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 13.

Transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 19

Table 14.

Transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 19

Table 15.

Register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 16.

WHO_AM_I register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 17.

CTRL_REG1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 18.

CTRL_REG1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 19.

Power mode and low-power output data rate configurations . . . . . . . . . . . . . . . . . . . . . . . 25

Table 20.

Normal mode output data rate configurations and low-pass cutoff frequencies . . . . . . . . . 25

Table 21.

CTRL_REG2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 22.

CTRL_REG2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 23.

High-pass filter mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 24.

High-pass filter cutoff frequency configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 25.

CTRL_REG3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 26.

CTRL_REG3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 27.

Data signal on INT 1 and INT 2 pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 28.

CTRL_REG4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 29.

CTRL_REG4 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 30.

CTRL_REG5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 31.

CTRL_REG5 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 32.

Sleep-to-wake configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 33.

REFERENCE register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 34.

REFERENCE description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 35.

STATUS_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 36.

STATUS_REG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 37.

INT1_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 38.

INT1_CFG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 39.

Interrupt 1 source configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 40.

INT1_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 41.

INT1_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 42.

INT1_THS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 43.

INT1_THS description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 44.

INT1_DURATION register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 45.

INT2_DURATION description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 46.

INT2_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 47.

INT2_CFG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 48.

Interrupt mode configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4/38 DocID023111 Rev 3

H3LIS331DL List of tables

Table 49.

INT2_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 50.

INT2_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 51.

INT2_THS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 52.

INT2_THS description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 53.

INT2_DURATION register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 54.

INT2_DURATION description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 55.

TFLGA 3x3x1.0 mm

3 16L mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 56.

Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

DocID023111 Rev 3 5/38

38

List of figures

List of figures

H3LIS331DL

Figure 1.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 2.

Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3.

SPI slave timing diagram

(2)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 4.

I

2

C slave timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 5.

H3LIS331DL electrical connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 6.

Read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 7.

SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 8.

Multiple byte SPI read protocol (2-byte example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 9.

SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 10.

Multiple byte SPI write protocol (2-byte example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 11.

SPI read protocol in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 12.

TFLGA 3x3x1.0 mm

3

16L mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6/38 DocID023111 Rev 3

H3LIS331DL

1

Block diagram and pin description

Block diagram and pin description

a

Figure 1. Block diagram

Z-

Y-

X-

X+

Y+

Z+

MUX

CHARGE

AMPLIFIER

A/D

CONVERTER

CONTROL LOGIC

I

2

C

SPI

CS

SCL/SPC

SDA/SDO/SDI

SDO/SA0

REFERENCE

TRIMMING

CIRCUITS

CLOCK

CONTROL LOGIC

&

INTERRUPT GEN.

INT 1

INT 2

AM12624V1

X

Y

1

Z

Figure 2. Pin connections

(TOP VIEW)

DIRECTION OF THE

DETECTABLE

ACCELERATIONS

13

9

(BOTTOM VIEW)

5

Pin 1 indicator

1

AM12625V1

DocID023111 Rev 3 7/38

38

Block diagram and pin description

Pin#

1

2

3

4

5

6

7

8

12

13

14

15

16

9

10

11

H3LIS331DL

CS

INT 2

Reserved

INT 1

GND

GND

Vdd

Reserved

GND

Name

Vdd_IO

NC

NC

SCL

SPC

GND

SDA

SDI

SDO

SDO

SA0

Table 2. Pin description

Function

Power supply for I/O pins

Not connected

Not connected

I

2

C serial clock (SCL)

SPI serial port clock (SPC)

0 V supply

I

2

C serial data (SDA)

SPI serial data input (SDI)

3-wire interface serial data output (SDO)

SPI serial data output (SDO)

I

2

C less significant bit of the device address (SA0)

SPI enable

I

2

C/SPI mode selection (1: I

2

C mode; 0: SPI enabled)

Inertial interrupt 2

Connect to GND

Inertial interrupt 1

0 V supply

0 V supply

Power supply

Connect to Vdd

0 V supply

8/38 DocID023111 Rev 3

H3LIS331DL

2

Mechanical and electrical specifications

Mechanical and electrical specifications

@ Vdd = 2.5 V, T = 25 °C unless otherwise noted

(a)

.

Symbol Parameter

Table 3. Mechanical characteristics

Test conditions

FS

So

Measurement range

Sensitivity

(3)

(2)

FS bit set to 00

FS bit set to 01

FS bit set to 11

FS bit set to 00

12-bit representation

FS bit set to 01

12-bit representation

FS bit set to 11

12-bit representation

TCSo

TyOff

TCOff

Sensitivity change vs. temperature

Typical zerog level offset accuracy

(4)

Zerog level change vs. temperature

Acceleration noise density

FS bit set to 00

FS bit set to 00

Max. delta from 25 °C

An

NL Non-linearity

FS bit set to 00

FS bit set to 00

Range -70g .. +70g

Top

Wh

Operating temperature range

Product weight

1. Typical specifications are not guaranteed.

2. Verified by wafer level test and measurement of initial offset and sensitivity.

3. Factory calibrated at s 1 g

4. Offset can be eliminated by enabling the built-in high-pass filter.

Min.

-40

±0.01

±1

±5

15

2

Typ.

(1)

±100

±200

±400

49

98

195

Max.

20 m

Unit g g

/digit

%/°C g

+85 m g /°C m g / Hz

%FS

°C mgram a. The product is factory calibrated at 2.5 V. The operational power supply range is from 2.16 V to 3.6 V. The product calibration is done at s 1 g .

DocID023111 Rev 3 9/38

38

Mechanical and electrical specifications H3LIS331DL

Symbol

@ Vdd = 2.5 V, T = 25 °C unless otherwise noted

(b)

.

Parameter

Table 4. Electrical characteristics

Test conditions Min.

Typ.

(1)

Max.

Unit

Vdd Supply voltage

Vdd_IO I/O pins supply voltage

(2)

Idd

IddLP

Current consumption in normal mode

Current consumption in lowpower mode

IddPdn

VIH

VIL

Current consumption in power-down mode

Digital high-level input voltage

Digital low-level input voltage

VOH

VOL

High-level output voltage

Low-level output voltage

ODR

ODR

BW

Ton

Top

LP

Output data rate in normal mode

Output data rate in low-power mode

DR bit set to 00

DR bit set to 01

DR bit set to 10

DR bit set to 11

PM bit set to 010

PM bit set to 011

PM bit set to 100

PM bit set to 101

PM bit set to 110

System bandwidth

(3)

Turn-on time

(4)

Operating temperature range

ODR = 100 Hz

2.16

1.71

0.8*Vdd_IO

0.9*Vdd_IO

2.5

300

10

1

50

100

400

1000

0.5

1

2

5

10

ODR/2

1/ODR+1ms

3.6

Vdd+0.1

0.2*Vdd_IO

V

V

0.1*Vdd_IO V

-40 +85

1. Typical specifications are not guaranteed.

2. It is possible to remove Vdd maintaining Vdd_IO without blocking the communication busses; in this condition the measurement chain is powered off.

3. Refer to Table 20 for filter cutoff frequency.

4. Time to obtain valid data after exiting power-down mode.

μ

μ

μ

A

A

A

V

V

V

Hz

Hz

Hz s

° C

10/38 b. The product is factory calibrated at 2.5 V. The operational power supply range is from 2.16 V to 3.6 V.

DocID023111 Rev 3

H3LIS331DL Mechanical and electrical specifications

2.3 Communication interface characteristics

2.3.1 SPI - serial peripheral interface

Subject to general operating conditions for Vdd and Top.

Table 5. SPI slave timing values

Value

(1)

Symbol Parameter Unit

Min.

Max.

t c(SPC) f c(SPC) t su(CS) t h(CS) t su(SI) t h(SI) t v(SO) t h(SO) t dis(SO)

SPI clock cycle

SPI clock frequency

CS setup time

CS hold time

SDI input setup time

SDI input hold time

SDO valid output time

SDO output hold time

SDO output disable time

100

6

8

5

15

9

10

50

50 ns

MHz ns

1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production.

Figure 3. SPI slave timing diagram (2)

2. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output ports.

3. When no communication is ongoing, data on CS, SPC, SDI and SDO are driven by internal pull-up resistors.

DocID023111 Rev 3 11/38

38

Mechanical and electrical specifications H3LIS331DL

2.3.2 I

2

C - inter-IC control interface

Subject to general operating conditions for Vdd and Top.

Symbol Parameter

Table 6. I 2 C slave timing values

I

2

C standard mode

(1)

Min.

Max.

f

(SCL) t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t r(SDA) t r(SCL) t f(SDA) t f(SCL) t h(ST)

SCL clock frequency

SCL clock low time

SCL clock high time

SDA setup time

SDA data hold time

SDA and SCL rise time

SDA and SCL fall time

0

4.7

4.0

250

0.01

100

3.45

1000

300 t su(SR)

START condition hold time

Repeated START condition setup time

4

4.7

t su(SP)

STOP condition setup time 4 t w(SP:SR)

Bus free time between STOP and START condition

4.7

1. Data based on standard I

2

C protocol requirement, not tested in production.

2. C b

= total capacitance of one bus line, in pF.

I

2

C fast mode

(1)

Min.

Max.

400 0

1.3

0.6

100

0.01

20 + 0.1C

b

(2)

20 + 0.1C

b

( 2)

0.6

0.9

300

300

0.6

0.6

1.3

Figure 4. I

2

C slave timing diagram

μ s

Unit

KHz

μ s ns

μ s ns

REPEATED

START

START

START

SDA f(SD A) t h(SDA)

STO P

SCL

Note: t w (SCLH) t r(SCL)

Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.

12/38 DocID023111 Rev 3

H3LIS331DL

2.4

Mechanical and electrical specifications

Absolute maximum ratings

Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Symbol

Table 7. Absolute maximum ratings

Ratings

Vdd Supply voltage

Vdd_IO I/O pins supply voltage

Vin

Input voltage on any control pin

(CS, SCL/SPC, SDA/SDI/SDO, SDO/SA0)

Maximum value

-0.3 to 4.8

-0.3 to 4.8

-0.3 to Vdd_IO +0.3

A

POW

A

UNP

T

OP

T

STG

ESD

Acceleration (any axis, powered, Vdd = 2.5 V)

Acceleration (any axis, unpowered)

Operating temperature range

Storage temperature range

Electrostatic discharge protection

3000 g for 0.5 ms

10000 g for 0.1 ms

3000 g for 0.5 ms

10000 g for 0.1 ms

-40 to +85

-40 to +125

4 (HBM)

1.5 (CDM)

200 (MM)

Unit

V

V

V

°C

°C kV kV

V

Note: Supply voltage on any pin should never exceed 4.8 V.

This device is sensitive to mechanical shock, improper handling can cause permanent damage to the part.

This is an electrostatic-sensitive device (ESD), improper handling can cause permanent damage to the part.

DocID023111 Rev 3 13/38

38

Mechanical and electrical specifications H3LIS331DL

2.5 Terminology

2.5.1 Sensitivity

Sensitivity describes the gain of the sensor and can be determined by applying 1 g acceleration to it. As the sensor can measure DC accelerations this can be done easily by pointing the axis of interest towards the center of the Earth, noting the output value, rotating the sensor by 180 degrees (pointing to the sky) and noting the output value again. By doing so, ±1 g acceleration is applied to the sensor. Subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This value changes very little over temperature and time. The sensitivity tolerance describes the range of sensitivities of a large population of sensors.

2.5.2 Zerog level

The zerog level offset (TyOff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. A sensor in a steady-state on a horizontal surface measures 0 g for the X-axis and 0 g for the Y-axis whereas the Z-axis measures 1 g .

The output is ideally in the middle of the dynamic range of the sensor (content of OUT registers 00h, data expressed as two’s complement number). A deviation from the ideal value in this case is called zerog offset. Offset is, to some extent, a result of stress to the

MEMS sensor and therefore can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes little over temperature, refer to “Zerog level change vs. temperature” (see TCOff in

Table 3

). The zerog level tolerance (TyOff) describes the standard deviation of the range of zerog levels of a population of sensors.

2.5.3 Sleep-to-wakeup

The “sleep-to-wakeup” function, in conjunction with low-power mode, allows to further reduce the system power consumption and develop new smart applications.

The H3LIS331DL may be set in a low-power operating mode, characterized by lower date rate refreshments. In this way the device, even if sleeping, continues to sense acceleration and generate interrupt requests.

When the “sleep-to-wakeup” function is activated, the H3LIS331DL is able to automatically wake up as soon as the interrupt event has been detected, increasing the output data rate and bandwidth.

With this feature the system may be efficiently switched from low-power mode to full performance, depending on user-selectable positioning and acceleration events, therefore ensuring power saving and flexibility.

14/38 DocID023111 Rev 3

H3LIS331DL

3 Functionality

Functionality

The H3LIS331DL is a “nano”, low-power, digital output 3-axis linear accelerometer housed in an LGA package. The complete device includes a sensing element and an IC interface able to take the information from the sensing element and to provide a signal to the external world through an I 2 C/SPI serial interface.

A proprietary process is used to create a surface micromachined accelerometer. The technology allows processing suspended silicon structures, which are attached to the substrate in a few points called anchors and are free to move in the direction of the sensed acceleration. To be compatible with traditional packaging techniques, a cap is placed on top of the sensing element to avoid blocking the moving parts during the molding phase of the plastic encapsulation.

When an acceleration is applied to the sensor, the proof mass displaces from its nominal position, causing an imbalance in the capacitive half bridge. This imbalance is measured using charge integration in response to a voltage pulse applied to the capacitor.

At steady-state the nominal value of the capacitors are a few pF and when an acceleration is applied, the maximum variation of the capacitive load is in the fF range.

The complete measurement chain is composed of a low-noise capacitive amplifier which converts the capacitive unbalancing of the MEMS sensor into an analog voltage that will be available to the user through an analog-to-digital converter.

The acceleration data may be accessed through an I 2 C/SPI interface, making the device particularly suitable for direct interfacing with a microcontroller.

The H3LIS331DL features a data-ready signal (RDY) which indicates when a new set of measured acceleration data is available, therefore simplifying data synchronization in the digital system that uses the device.

The IC interface is factory calibrated for sensitivity (So) and zerog level (TyOff).

The trim values are stored inside the device in non-volatile memory. Any time the device is turned on, the trim parameters are downloaded into the registers to be used during active operation. This allows the device to be used without further calibration.

DocID023111 Rev 3 15/38

38

Application hints H3LIS331DL

Vdd

Figure 5. H3LIS331DL electrical connections

10µF

Vdd_IO

100nF

1

16 14

TOP VIEW

13

6 8

INT 1

INT 2

16/38

GND

Digital signal from/to signal controller. Signal levels are defined by proper selection of Vdd_IO

AM12626V1

The device core is supplied through the Vdd line while the I/O pads are supplied through the

Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 μ F aluminum) should be placed as near as possible to pin 14 of the device (common design practice).

All the voltage and ground supplies must be present at the same time to have proper behavior of the IC (refer to

Figure 5

). It is possible to remove Vdd maintaining Vdd_IO without blocking the communication bus, in this condition the measurement chain is powered off.

The functionality of the device and the measured acceleration data are selectable and accessible through the I

2

C or SPI interfaces. When using the I

2

C, CS must be tied high.

The functions, the threshold and the timing of the two interrupt pins (INT 1 and INT 2) can be completely programmed by the user through the I

2

C/SPI interface.

The LGA package is compliant with the ECOPACK ® , RoHS and “Green” standards.

It is qualified for soldering heat resistance according to JEDEC J-STD-020C.

Leave “pin 1 indicator” unconnected during soldering.

Land pattern and soldering recommendations are available at www.st.com

.

DocID023111 Rev 3

H3LIS331DL Digital interfaces

The registers embedded inside the H3LIS331DL may be accessed through both the I 2 C and

SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode.

The serial interfaces are mapped onto the same pads. To select/exploit the I 2 C interface, the

CS line must be tied high (i.e. connected to Vdd_IO).

Pin name

CS

SCL

SPC

SDA

SDI

SDO

SA0

SDO

Table 8. Serial interface pin description

Pin description

SPI enable

I

2

C/SPI mode selection (1: I

2

C mode; 0: SPI enabled)

I

2

C serial clock (SCL)

SPI serial port clock (SPC)

I

2

C serial data (SDA)

SPI serial data input (SDI)

3-wire interface serial data output (SDO)

I

2

C less significant bit of the device address (SA0)

SPI serial data output (SDO)

5.1 I 2 C serial interface

The H3LIS331DL I 2 C is a bus slave. The I content can also be read back.

2 C is employed to write data into registers whose

The relevant I 2 C terminology is given in the table below.

Term

Transmitter

Receiver

Master

Slave

Table 9. Serial interface pin description

Description

The device which sends data to the bus

The device which receives data from the bus

The device which initiates a transfer, generates clock signals and terminates a transfer

The device addressed by the master

There are two signals associated with the I

2

C bus: the serial clock line (SCL) and the serial data line (SDA). The latter is a bi-directional line used for sending and receiving the data to/from the interface. Both the lines are connected to Vdd_IO through a pull-up resistor embedded inside the H3LIS331DL. When the bus is free both lines are high.

The I

2

C interface is compliant with fast mode (400 kHz) I

2

C standards as well as with normal mode.

DocID023111 Rev 3 17/38

38

Digital interfaces H3LIS331DL

5.1.1 I

2

C operation

The transaction on the bus is started through a START (ST) signal. A START condition is defined as a high-to-low transition on the data line while the SCL line is held high. After this has been transmitted by the master, the bus is considered busy. The next byte of data transmitted after the START condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the first seven bits after a START condition with its address. If they match, the device considers itself addressed by the master.

The slave address (SAD) associated to the H3LIS331DL is 001100xb. The SDO / SA0 pad can be used to modify the less significant bit of the device address. If the SA0 pad is connected to the voltage supply, LSB is ‘1’ (address 0011001b) or else, if the SA0 pad is connected to ground, the LSB value is ‘0’ (address 0011000b). This solution allows the connection and addressing of two different accelerometers to the same I 2 C lines.

Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line low so that it remains stable low during the high period of the acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each byte of data received.

The I 2 C embedded inside the H3LIS331DL behaves like a slave device and the following protocol must be adhered to. After the START condition (ST) a slave address is sent, once a slave acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) is transmitted: the

7 LSB represent the actual register address while the MSB enables address auto increment.

If the MSB of the SUB field is ‘1’, the SUB (register address) is automatically increased to allow multiple data read/write.

The slave address is completed with a Read/Write bit. If the bit is ‘1’ (read), a repeated

START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (write),

the master transmits to the slave with the direction unchanged. Table 10

explains how the

SAD+Read/Write bit pattern is composed, listing all the possible configurations.

Command

Read

Write

Read

Write

Table 10. SAD+Read/Write patterns

SAD[6:1] SAD[0] = SA0 R/W

001100

001100

001100

001100

0

0

1

1

1

0

1

0

SAD+R/W

00110001 (31h)

00110000 (30h)

00110011 (33h)

00110010 (32h)

Master

Slave

Table 11. Transfer when master is writing one byte to slave

ST SAD + W SUB DATA

SAK SAK SAK

SP

18/38 DocID023111 Rev 3

H3LIS331DL Digital interfaces

Master

Slave

ST

Table 12. Transfer when master is writing multiple bytes to slave

SAD + W SUB DATA DATA

SAK SAK SAK SAK

SP

Master

Table 13. Transfer when master is receiving (reading) one byte of data from slave

ST SAD + W SUB SR SAD + R NMAK

Slave SAK SAK SAK DATA

SP

Table 14. Transfer when master is receiving (reading) multiple bytes of data from slave

Master ST SAD+W SUB SR SAD+R MAK MAK NMAK SP

Slave SAK SAK SAK DATA

DAT

A

DAT

A

Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the most significant bit

(MSB) first. If a receiver can’t receive another complete byte of data until it has performed some other function, it can hold the clock line SCL low to force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and releases the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to receive because it is performing some real-time function) the data line must be left high by the slave. The master can then abort the transfer. A low-to-high transition on the SDA line while the SCL line is high is defined as a STOP condition. Each data transfer must be terminated by the generation of a STOP (SP) condition.

In order to read multiple bytes, it is necessary to assert the most significant bit of the subaddress field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the address of first register to be read.

In the presented communication format MAK is master acknowledge and NMAK is no master acknowledge.

5.2 SPI bus interface

The H3LIS331DL SPI is a bus slave. The SPI allows the writing and reading of the device registers.

The serial interface interacts with the outside world with 4 wires: CS , SPC , SDI and SDO .

DocID023111 Rev 3 19/38

38

Digital interfaces H3LIS331DL

Figure 6. Read and write protocol

CS

SPC

SDI

RW

MS AD5 AD4 AD3 AD2 AD1 AD0

DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

SDO

DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of the transmission and goes back high at the end. SPC is the serial port clock and it is controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and

SDO are respectively the serial port data input and output. Those lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC .

Both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in the case of multiple read/write bytes. Bit duration is the time between two falling edges of SPC . The first bit (bit 0) starts at the first falling edge of SPC after the falling edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the rising edge of CS .

bit 0 : RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is read. In the latter case, the chip drives SDO at the start of bit 8.

bit 1 : MS bit. When 0, the address remains unchanged in multiple read/write commands.

When 1, the address is auto-incremented in multiple read/write commands.

bit 2-7 : address AD(5:0). This is the address field of the indexed register.

bit 8-15 : data DI(7:0) (write mode). This is the data that is written into the device (MSB first).

bit 8-15 : data DO(7:0) (read mode). This is the data that is read from the device (MSB first).

In multiple read/write commands further blocks of 8 clock periods are added. When the MS bit is ‘0’, the address used to read/write data remains the same for every block. When the

MS bit is ‘1’ the address used to read/write data is increased at every block.

The function and the behavior of SDI and SDO remain unchanged.

20/38

Figure 7. SPI read protocol

CS

SPC

SDI

SDO

RW

MS AD5 AD4 AD3 AD2 AD1 AD0

DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

DocID023111 Rev 3

H3LIS331DL Digital interfaces

The SPI read command is performed with 16 clock pulses. A multiple byte read command is performed by adding blocks of 8 clock pulses to the previous one.

bit 0 : READ bit. The value is 1.

bit 1 : MS bit. When 0, does not increment the address. When 1, increments the address in multiple reads.

bit 2-7 : address AD(5:0). This is the address field of the indexed register. bit 8-15 : data DO(7:0) (read mode). This is the data that is read from the device (MSB first).

bit 16-...

: data DO(...-8). Further data in multiple byte reads.

Figure 8. Multiple byte SPI read protocol (2-byte example)

CS

SPC

SDI

RW

MS AD5 AD4 AD3 AD2 AD1 AD0

SDO

DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DO15DO14DO13DO12DO11DO10DO9 DO8

Figure 9. SPI write protocol

CS

SPC

SDI

RW

MS AD5 AD4 AD3 AD2 AD1 AD0

DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

The SPI write command is performed with 16 clock pulses. A multiple byte write command is performed by adding blocks of 8 clock pulses to the previous one.

bit 0 : WRITE bit. The value is 0.

bit 1 : MS bit. When 0, does not increment the address. When 1, increments the address in multiple writes.

bit 2 -7 : address AD(5:0). This is the address field of the indexed register. bit 8-15 : data DI(7:0) (write mode). This is the data that is written inside the device (MSB first).

bit 16-...

: data DI(...-8). Further data in multiple byte writes.

DocID023111 Rev 3 21/38

38

Digital interfaces

Figure 10. Multiple byte SPI write protocol (2-byte example)

H3LIS331DL

CS

SPC

SDI

RW

MS

AD5 AD4 AD3 AD2 AD1 AD0

DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8

5.2.3 SPI read in 3-wire mode

3-wire mode is entered by setting bit SIM (SPI serial interface mode selection) to ‘1’ in

CTRL_REG4.

Figure 11. SPI read protocol in 3-wire mode

CS

SPC

SDI/O

RW

MS AD5 AD4 AD3 AD2 AD1 AD0

DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

The SPI read command is performed with 16 clock pulses: bit 0 : READ bit. The value is 1.

bit 1 : MS bit. When 0, does not increment the address. When 1, increments the address in multiple reads.

bit 2-7 : address AD(5:0). This is the address field of the indexed register. bit 8-15 : data DO(7:0) (read mode). This is the data that is read from the device (MSB first).

The multiple read command is also available in 3-wire mode.

22/38 DocID023111 Rev 3

H3LIS331DL Register mapping

Table 15

provides a listing of the 8-bit registers embedded in the device and the related addresses.

Name

Reserved (do not modify)

WHO_AM_I

Reserved (do not modify)

CTRL_REG1

CTRL_REG2

CTRL_REG3

CTRL_REG4

CTRL_REG5

HP_FILTER_RESET

REFERENCE

STATUS_REG

OUT_X_L

OUT_X_H

OUT_Y_L

OUT_Y_H

OUT_Z_L

OUT_Z_H

Reserved (do not modify)

INT1_CFG

INT1_SRC

INT1_THS

INT1_DURATION

INT2_CFG

INT2_SRC

INT2_THS

INT2_DURATION

Reserved (do not modify) r r r r r r rw r rw r rw rw rw rw

Table 15. Register address map

Register address

Type

Hex Binary

Default r rw r rw rw rw r rw rw

2D

2E - 2F

30

31

32

33

34

35

36

37

38 - 3F

29

2A

2B

2C

25

26

27

28

00 - 0E

0F

10 - 1F

20

21

22

23

24

Comment

Reserved

000 1111 00110010 Dummy register

Reserved

010 0000 00000111

010 0001 00000000

010 0010 00000000

010 0011 00000000

010 0100 00000000

010 0101

010 0110 00000000

010 0111 00000000

010 1000 Output

010 1001 Output

010 1010 Output

010 1011 Output

010 1100 Output

010 1101 Output

Dummy register

Reserved

011 0000 00000000

011 0001 00000000

011 0010 00000000

011 0011 00000000

011 0100 00000000

011 0101 00000000

011 0110 00000000

011 0111 00000000

Reserved

Registers marked as Reserved must not be changed as they contain the factory calibration values. Their content is automatically restored when the device is powered up. Writing to those registers may change calibration data and thus lead to improper functioning of the device.

DocID023111 Rev 3 23/38

38

Register description H3LIS331DL

The device contains a set of registers which are used to control its behavior and to retrieve acceleration data. The register address, consisting of 7 bits, is used to identify them and to write the data through the serial interface.

0 0 1

Table 16. WHO_AM_I register

1 0 0 1

Device identification register.

This register contains the device identifier that for the H3LIS331DL is set to 32h.

0

24/38

PM2 PM1

Table 17. CTRL_REG1 register

PM0 DR1 DR0 Zen Yen Xen

PM2 - PM0

DR1, DR0

Zen

Yen

Xen

Table 18. CTRL_REG1 description

Power mode selection. Default value: 000

(000: power-down; Others: refer to Table 19 )

Data rate selection. Default value: 00

(00:50 Hz; Others: refer to Table 20 )

Z-axis enable. Default value: 1

(0: Z-axis disabled; 1: Z-axis enabled)

Y-axis enable. Default value: 1

(0: Y-axis disabled; 1: Y-axis enabled)

X-axis enable. Default value: 1

(0: X-axis disabled; 1: X-axis enabled)

The PM bits allow the user to select between power-down and two operating active modes.

The device is in power-down mode when the PD bits are set to “000” (default value after

boot). Table 19

shows all the possible power mode configurations and respective output data rates. Output data in the low-power mode are computed with the low-pass filter cutoff frequency defined by the DR1, DR0 bits.

The DR bits, in normal mode operation, select the data rate at which acceleration samples are produced. In low-power modes they define the output data resolution.

Table 20 shows

all the possible configurations for the DR1 and DR0 bits.

DocID023111 Rev 3

H3LIS331DL Register description

0

1

0

0

1

1

PM2

0

Table 19. Power mode and low-power output data rate configurations

PM1

0

PM0

0

Power mode selection

Power-down

Output data rate [Hz]

ODR

LP

--

1

0

0

1

0

1

1

0

1

0

1

0

Normal mode

Low power

Low power

Low power

Low power

Low power

ODR

0.5

1

2

5

10

0

0

1

1

Table 20. Normal mode output data rate configurations and low-pass cutoff frequencies

DR1 DR0

Output data rate [Hz]

ODR

Low-pass filter cutoff frequency [Hz]

0

1

0

1

50

100

400

1000

37

74

292

780

BOOT HPM1

Table 21. CTRL_REG2 register

HPM0 FDS HPen2 HPen1 HPCF1 HPCF0

BOOT

HPM1, HPM0

FDS

HPen2

Table 22. CTRL_REG2 description

Reboot memory content. Default value: 0

(0: normal mode; 1: reboot memory content)

High-pass filter mode selection. Default value: 00

(00: normal mode; Others: refer to

Table 23 )

Filtered data selection. Default value: 0

(0: internal filter bypassed; 1: data from internal filter sent to output register)

High-pass filter enabled for interrupt 2 source. Default value: 0

(0: filter bypassed; 1: filter enabled)

DocID023111 Rev 3 25/38

38

Register description H3LIS331DL

HPen1

HPCF1,

HPCF0

Table 22. CTRL_REG2 description (continued)

High-pass filter enabled for interrupt 1 source. Default value: 0

(0: filter bypassed; 1: filter enabled)

High-pass filter cutoff frequency configuration. Default value: 00

(00: HPc=8; 01: HPc=16; 10: HPc=32; 11: HPc=64)

The BOOT bit is used to refresh the content of the internal registers stored in the Flash memory block. At device power-up, the content of the Flash memory block is transferred to the internal registers related to trimming functions in order to permit correct operation of the device itself. If for any reason the content of the trimming registers is changed, it is sufficient to use this bit to restore the correct values. When the BOOT bit is set to ‘1’, the content of the internal Flash is copied inside the corresponding internal registers and it is used to calibrate the device. These values are factory trimmed and they are different for every accelerometer. They permit correct operation of the device and normally they do not have to be changed. At the end of the boot process the BOOT bit is set again to ‘0’.

HPM1

0

0

1

Table 23. High-pass filter mode configuration

HPM0 High-pass filter mode

0

1

0

Normal mode (reset reading HP_RESET_FILTER)

Reference signal for filtering

Normal mode (reset reading HP_RESET_FILTER)

HPCF[1:0] . These bits are used to configure the high-pass filter cutoff frequency f t given by:

which is f t

= ln





1

– ------------





 f

2 s



The equation can be simplified to the following approximated equation: f t

= f s

HPcoeff2,1

00

01

10

11

Table 24. High-pass filter cutoff frequency configuration f t

[Hz]

Data rate = 50 Hz f t

[Hz]

Data rate = 100 Hz f t

[Hz]

Data rate = 400 Hz f t

[Hz]

Data rate = 1000 Hz

1

0.5

0.25

0.125

2

1

0.5

0.25

2

1

8

4

20

10

5

2.5

26/38 DocID023111 Rev 3

H3LIS331DL

7.4 CTRL_REG3 [interrupt CTRL register] (22h)

IHL PP_OD

Table 25. CTRL_REG3 register

LIR2 I2_CFG1 I2_CFG0 LIR1

Register description

I1_CFG1 I1_CFG0

IHL

PP_OD

LIR2

I2_CFG1,

I2_CFG0

LIR1

I1_CFG1,

I1_CFG0

Table 26. CTRL_REG3 description

Interrupt active high, low. Default value: 0

(0: active high; 1: active low)

Push-pull/open drain selection on interrupt pad. Default value 0.

(0: push-pull; 1: open drain)

Latch interrupt request on INT2_SRC register, with INT2_SRC register cleared by reading INT2_SRC itself. Default value: 0.

(0: interrupt request not latched; 1: interrupt request latched)

Data signal on INT 2 pad control bits. Default value: 00.

(see Table 27 )

Latch interrupt request on the INT1_SRC register, with the INT1_SRC register cleared by reading the INT1_SRC register. Default value: 0.

(0: interrupt request not latched; 1: interrupt request latched)

Data signal on INT 1 pad control bits. Default value: 00.

(see Table 27 )

I1(2)_CFG1

1

1

0

0

Table 27. Data signal on INT 1 and INT 2 pad

I1(2)_CFG0 INT 1(2) Pad

0

1

0

1

Interrupt 1 (2) source

Interrupt 1 source OR interrupt 2 source

Data ready

Boot running

BDU BLE

Table 28. CTRL_REG4 register

FS1 FS0 0 0 0 SIM

DocID023111 Rev 3 27/38

38

Register description H3LIS331DL

BDU

BLE

FS1, FS0

SIM

Table 29. CTRL_REG4 description

Block data update. Default value: 0

(0: continuous update; 1: output registers not updated between MSB and LSB reading)

Big/little endian data selection. Default value 0.

(0: data LSB @ lower address; 1: data MSB @ lower address)

Full scale selection. Default value: 00.

(00: ±100 g ; 01: ±200 g ; 11: ±400 g )

SPI serial interface mode selection. Default value: 0.

(0: 4-wire interface; 1: 3-wire interface)

The BDU bit is used to inhibit output register updates between the reading of upper and lower register parts. In default mode (BDU = ‘0’), the lower and upper register parts are updated continuously. When the BDU is activated (BDU = ‘1’), the content of the output registers is not updated until both MSB and LSB are read which avoids reading values related to different sample times.

0 0 0

Table 30. CTRL_REG5 register

0 0 0 TurnOn1 TurnOn0

TurnOn1,

TurnOn0

Table 31. CTRL_REG5 description

Turn-on mode selection for sleep-to-wake function. Default value: 00.

Turn-on bits are used for turning on the sleep-to-wake function.

TurnOn1

0

1

TurnOn0

Table 32. Sleep-to-wake configuration

Sleep-to-wake status

0

1

Sleep-to-wake function is disabled

Turned on: The device is in low-power mode (ODR is defined in

CTRL_REG1)

Setting TurnOn[1:0] bits to 11, the “sleep-to-wake” function is enabled. When an interrupt event occurs, the device is turned to normal mode, increasing the ODR to the value defined in CTRL_REG1. Although the device is in normal mode, CTRL_REG1 content is not automatically changed to “normal mode” configuration.

28/38 DocID023111 Rev 3

H3LIS331DL Register description

Dummy register. Reading at this address zeroes instantaneously the content of the internal high-pass filter. If the high-pass filter is enabled, all three axes are instantaneously set to

0 g.

This allows the settling time of the high-pass filter to be overcome.

Ref7 Ref6

Table 33. REFERENCE register

Ref5 Ref4 Ref3 Ref2 Ref1 Ref0

Table 34. REFERENCE description

Ref7 - Ref0 Reference value for high-pass filter. Default value: 00h.

This register sets the acceleration value taken as a reference for the high-pass filter output.

When the filter is turned on (at least one of the FDS, HPen2, or HPen1 bits is equal to ‘1’) and the HPM bits are set to “01”, filter-out is generated, taking this value as a reference.

ZYXOR ZOR

Table 35. STATUS_REG register

YOR XOR ZYXDA ZDA YDA XDA

ZYXOR

ZOR

YOR

XOR

ZYXDA

Table 36. STATUS_REG description

X, Y and Z-axis data overrun. Default value: 0

(0: no overrun has occurred;

1: new data has overwritten the previous data before it was read)

Z-axis data overrun. Default value: 0

(0: no overrun has occurred;

1: new data for the Z-axis has overwritten the previous data)

Y-axis data overrun. Default value: 0

(0: no overrun has occurred;

1: new data for the Y-axis has overwritten the previous data)

X-axis data overrun. Default value: 0

(0: no overrun has occurred;

1: new data for the X-axis has overwritten the previous data)

X, Y and Z-axis new data available. Default value: 0

(0: a new set of data is not yet available; 1: a new set of data is available)

DocID023111 Rev 3 29/38

38

Register description

ZDA

YDA

XDA

Table 36. STATUS_REG description (continued)

Z-axis new data available. Default value: 0

(0: new data for the Z-axis is not yet available;

1: new data for the Z-axis is available)

Y-axis new data available. Default value: 0

(0: new data for the Y-axis is not yet available;

1: new data for the Y-axis is available)

X-axis new data available. Default value: 0

(0: new data for the X-axis is not yet available;

1: new data for the X-axis is available)

7.10 OUT_X_L (28h), OUT_X_H (29h)

X-axis acceleration data. The value is expressed as two’s complement.

7.11 OUT_Y_L (2Ah), OUT_Y_H (2Bh)

Y-axis acceleration data. The value is expressed as two’s complement.

7.12 OUT_Z_L (2Ch), OUT_Z_H (2Dh)

Z-axis acceleration data. The value is expressed as two’s complement.

H3LIS331DL

30/38

AOI

AOI

ZHIE

ZLIE

YHIE

YLIE

0 ZHIE

Table 37. INT1_CFG register

ZLIE YHIE YLIE XHIE XLIE

Table 38. INT1_CFG description

AND/OR combination of interrupt events. Default value: 0.

(See

Table 39 )

Enable interrupt generation on Z high event. Default value: 0

(0: disable interrupt request;

1: enable interrupt request on measured accel. value higher than preset threshold)

Enable interrupt generation on Z low event. Default value: 0

(0: disable interrupt request;

1: enable interrupt request on measured accel. value lower than preset threshold)

Enable interrupt generation on Y high event. Default value: 0

(0: disable interrupt request;

1: enable interrupt request on measured accel. value higher than preset threshold)

Enable interrupt generation on Y low event. Default value: 0

(0: disable interrupt request;

1: enable interrupt request on measured accel. value lower than preset threshold)

DocID023111 Rev 3

H3LIS331DL

XHIE

XLIE

Register description

Table 38. INT1_CFG description (continued)

Enable interrupt generation on X high event. Default value: 0

(0: disable interrupt request;

1: enable interrupt request on measured accel. value higher than preset threshold)

Enable interrupt generation on X low event. Default value: 0

(0: disable interrupt request;

1: enable interrupt request on measured accel. value lower than preset threshold)

Configuration register for interrupt 1 source.

AOI

0

1

Table 39. Interrupt 1 source configurations

Interrupt mode

OR combination of interrupt events

AND combination of interrupt events

YL

XH

XL

ZL

YH

IA

ZH

0 IA ZH

Table 40. INT1_SRC register

ZL YH YL XH XL

Table 41. INT1_SRC description

Interrupt active. Default value: 0

(0: no interrupt has been generated; 1: one or more interrupts have been generated)

Z high. Default value: 0

(0: no interrupt, 1: Z high event has occurred)

Z low. Default value: 0

(0: no interrupt; 1: Z low event has occurred)

Y high. Default value: 0

(0: no interrupt, 1: Y high event has occurred)

Y low. Default value: 0

(0: no interrupt, 1: Y low event has occurred)

X high. Default value: 0

(0: no interrupt, 1: X high event has occurred)

X low. Default value: 0

(0: no interrupt, 1: X low event has occurred)

Interrupt 1 source register. Read-only register.

Reading at this address clears the INT1_SRC IA bit (and the interrupt signal on the INT 1 pin) and allows the refreshment of data in the INT1_SRC register if the latched option is chosen.

DocID023111 Rev 3 31/38

38

Register description H3LIS331DL

0 THS6 THS5

Table 42. INT1_THS register

THS4 THS3 THS2

Table 43. INT1_THS description

THS6 - THS0 Interrupt 1 threshold. Default value: 000 0000

THS1 THS0

0 D6

Table 44. INT1_DURATION register

D5 D4 D3 D2 D1 D0

D6 - D0

Table 45. INT2_DURATION description

Duration value. Default value: 000 0000

The D6 - D0 bits set the minimum duration of the interrupt 2 event to be recognized.

Duration steps and maximum values depend on the ODR chosen.

32/38

AOI

AOI

ZHIE

ZLIE

YHIE

YLIE

0 ZHIE

Table 46. INT2_CFG register

ZLIE YHIE YLIE XHIE XLIE

Table 47. INT2_CFG description

AND/OR combination of interrupt events. Default value: 0.

(See

Table 48 )

Enable interrupt generation on Z high event. Default value: 0

(0: disable interrupt request;

1: enable interrupt request on measured accel. value higher than preset threshold)

Enable interrupt generation on Z low event. Default value: 0

(0: disable interrupt request;

1: enable interrupt request on measured accel. value lower than preset threshold)

Enable interrupt generation on Y high event. Default value: 0

(0: disable interrupt request;

1: enable interrupt request on measured accel. value higher than preset threshold)

Enable interrupt generation on Y low event. Default value: 0

(0: disable interrupt request;

1: enable interrupt request on measured accel. value lower than preset threshold)

DocID023111 Rev 3

H3LIS331DL

XHIE

XLIE

Register description

Table 47. INT2_CFG description (continued)

Enable interrupt generation on X high event. Default value: 0

(0: disable interrupt request;

1: enable interrupt request on measured accel. value higher than preset threshold)

Enable interrupt generation on X low event. Default value: 0

(0: disable interrupt request;

1: enable interrupt request on measured accel. value lower than preset threshold)

Configuration register for interrupt 2 source.

AOI

0

1

Table 48. Interrupt mode configuration

Interrupt mode

OR combination of interrupt events

AND combination of interrupt events

YL

XH

XL

ZL

YH

IA

ZH

0 IA ZH

Table 49. INT2_SRC register

ZL YH YL XH XL

Table 50. INT2_SRC description

Interrupt active. Default value: 0

(0: no interrupt has been generated; 1: one or more interrupts have been generated)

Z high. Default value: 0

(0: no interrupt, 1: Z high event has occurred)

Z low. Default value: 0

(0: no interrupt; 1: Z low event has occurred)

Y high. Default value: 0

(0: no interrupt, 1: Y high event has occurred)

Y low. Default value: 0

(0: no interrupt, 1: Y low event has occurred)

X high. Default value: 0

(0: no interrupt, 1: X high event has occurred)

X Low. Default value: 0

(0: no interrupt, 1: X low event has occurred)

Interrupt 2 source register. Read-only register.

Reading at this address clears the INT2_SRC IA bit (and the interrupt signal on the INT 2 pin) and allows the refreshment of data in the INT2_SRC register if the latched option is chosen.

DocID023111 Rev 3 33/38

38

Register description H3LIS331DL

0 THS6 THS5

Table 51. INT2_THS register

THS4 THS3 THS2

THS6 - THS0

Table 52. INT2_THS description

Interrupt 1 threshold. Default value: 000 0000

THS1 THS0

0 D6

Table 53. INT2_DURATION register

D5 D4 D3 D2

Table 54. INT2_DURATION description

Duration value. Default value: 000 0000

D1

D6 - D0

The D6 - D0 bits set the minimum duration of the interrupt 2 event to be recognized.

Duration time steps and maximum values depend on the ODR chosen.

D0

34/38 DocID023111 Rev 3

H3LIS331DL Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com.

ECOPACK is an ST trademark.

DocID023111 Rev 3 35/38

38

Package information H3LIS331DL

P2

T1

T2 d k

N1

N2

M

P1

D1

E1

L1

L2

A1

A2

A3

Dim.

Table 55. TFLGA 3x3x1.0 mm 3 16L mechanical data mm

Min.

Typ.

Max.

1

2.850

2.850

0.040

0.290

0.190

0.100

0.875

1.275

0.350

0.250

0.150

0.050

0.785

0.200

3.000

3.000

1.000

2.000

0.500

1.000

Figure 12. TFLGA 3x3x1.0 mm

3

16L mechanical drawing

3.150

3.150

1.060

2.060

0.160

0.410

0.310

36/38 DocID023111 Rev 3

7983231_L

H3LIS331DL Revision history

Date

20-Apr-2012

16-Jul-2013

16-Sep-2013

Revision

1

2

3

Table 56. Document revision history

Changes

Initial release

Document status promoted from preliminary data to production data

Updated Table 3

Minor textual updates

Updated Company information appearing on last page of document

DocID023111 Rev 3 37/38

38

H3LIS331DL

Please Read Carefully:

Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice.

All ST products are sold pursuant to ST’s terms and conditions of sale.

Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.

UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED

WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED

WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS

OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

ST PRODUCTS ARE NOT DESIGNED OR AUTHORIZED FOR USE IN: (A) SAFETY CRITICAL APPLICATIONS SUCH AS LIFE

SUPPORTING, ACTIVE IMPLANTED DEVICES OR SYSTEMS WITH PRODUCT FUNCTIONAL SAFETY REQUIREMENTS; (B)

AERONAUTIC APPLICATIONS; (C) AUTOMOTIVE APPLICATIONS OR ENVIRONMENTS, AND/OR (D) AEROSPACE APPLICATIONS

OR ENVIRONMENTS. WHERE ST PRODUCTS ARE NOT DESIGNED FOR SUCH USE, THE PURCHASER SHALL USE PRODUCTS AT

PURCHASER’S SOLE RISK, EVEN IF ST HAS BEEN INFORMED IN WRITING OF SUCH USAGE, UNLESS A PRODUCT IS

EXPRESSLY DESIGNATED BY ST AS BEING INTENDED FOR “AUTOMOTIVE, AUTOMOTIVE SAFETY OR MEDICAL” INDUSTRY

DOMAINS ACCORDING TO ST PRODUCT DESIGN SPECIFICATIONS. PRODUCTS FORMALLY ESCC, QML OR JAN QUALIFIED ARE

DEEMED SUITABLE FOR USE IN AEROSPACE BY THE CORRESPONDING GOVERNMENTAL AGENCY.

Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST.

ST and the ST logo are trademarks or registered trademarks of ST in various countries.

Information in this document supersedes and replaces all information previously supplied.

The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.

© 2013 STMicroelectronics - All rights reserved

STMicroelectronics group of companies

Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -

Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com

38/38 DocID023111 Rev 3