STMicroelectronics LIS331DLM Datasheet
विज्ञापन
विज्ञापन
LIS331DLM
MEMS digital output motion sensor ultra low-power high performance 3-axes “nano” accelerometer
Features
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■
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Wide supply voltage, 2.16 V to 3.6 V
Low voltage compatible IOs, 1.8 V
Ultra low-power mode consumption down to 10 µA
± 2 g /±4 g / ± 8 g dynamically selectable full-scale
I
2
C/SPI digital output interface
8 bit resolution
2 independent programmable interrupt generators for free-fall and motion detection
Sleep to wake-up function
6D orientation detection
Embedded self-test
10000 g high shock survivability
ECOPACK
®
RoHS and “Green” compliant (see
Applications
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Motion activated functions
Free-fall detection
Intelligent power saving for handheld devices
Pedometer
Display orientation
Gaming and virtual reality input devices
Impact recognition and logging
Vibration monitoring and compensation
Table 1.
Device summary
Order code Temperature range [ ° C]
LIS331DLM
LIS331DLMTR
-40 to +85
-40 to +85
LGA 16 (3x3x1 mm)
Description
The LIS331DLM is an ultra low-power high performance three axes linear accelerometer belonging to the “nano” family, with digital I
2
C/SPI serial interface standard output.
The device features ultra low-power operational modes that allow advanced power saving and smart sleep to wake-up functions.
The LIS331DLM has dynamically user selectable full scales of ±2 g /±4 g /±8 g and it is capable of measuring accelerations with output data rates from 0.5 Hz to 400 Hz.
The self-test capability allows the user to check the functioning of the sensor in the final application.
.
The device may be configured to generate interrupt signal by inertial wake-up/free-fall events as well as by the position of the device itself.
Thresholds and timing of interrupt generators are programmable by the end user on the fly.
The LIS331DLM is available in small thin plastic
Land Grid Array package (LGA) and it is guaranteed to operate over an extended temperature range from -40 °C to +85 °C.
Package
LGA 16
LGA 16
Packaging
Tray
Tape and reel
July 2009 Doc ID 15102 Rev 4 1/38 www.st.com
38
Contents
Contents
LIS331DLM
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . 8
Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 10
SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
I2C - Inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
SPI read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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LIS331DLM
Contents
CTRL_REG3 [Interrupt CTRL register] (22h) . . . . . . . . . . . . . . . . . . . . . . 27
HP_FILTER_RESET (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
INT1_DURATION (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
INT2_DURATION (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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List of tables
List of tables
LIS331DLM
Mechanical characteristics @ Vdd = 2.5 V, T = 25 °C unless otherwise noted . . . . . . . . . . 7
Electrical characteristics @ Vdd = 2.5 V, T = 25 °C unless otherwise noted . . . . . . . . . . . . 8
Transfer when Master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 17
Normal-mode output data rate configurations and low-pass cut-off frequencies . . . . . . . . 24
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LIS331DLM List of tables
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List of figures
List of figures
LIS331DLM
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LIS331DLM
1
Block diagram and pin description
Block diagram and pin description
Figure 1.
Block diagram
X+
Y+
Z+ a
MUX
Z-
Y-
X-
CHARGE
AMPLIFIER
A/D
CONVERTER
CONTROL LOGIC
I 2 C
SPI
CS
SCL/SPC
SDA/SDO/SDI
SDO/SA0
SELF TEST REFERENCE
TRIMMING
CIRCUITS
CLOCK
CONTROL LOGIC
&
INTERRUPT GEN.
INT 1
INT 2
Figure 2.
Pin connection
Z
1
X
Y
(TOP VIEW)
DIRECTION OF THE
DETECTABLE
ACCELERATIONS
13
Pin 1 indicator
1
9
(BOTTOM VIEW)
5
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Block diagram and pin description LIS331DLM
Table 2.
Pin#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin description
Name
Vdd_IO
NC
NC
SCL
SPC
GND
SDA
SDI
SDO
SDO
SA0
CS
INT 2
Reserved
INT 1
GND
GND
Vdd
Reserved
GND
Function
Power supply for I/O pins
Not connected
Not connected
I
2
C serial clock (SCL)
SPI serial port clock (SPC)
0 V supply
I
2
C serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
SPI serial data output (SDO)
I
2
C less significant bit of the device address (SA0)
SPI enable
I
2
C/SPI mode selection (1: I
2
C mode; 0: SPI enabled)
Inertial interrupt 2
Connect to GND
Inertial interrupt 1
0 V supply
0 V supply
Power supply
Connect to Vdd
0 V supply
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LIS331DLM
2
Mechanical and electrical specifications
Mechanical and electrical specifications
Table 3.
Symbol
Mechanical characteristics @ Vdd = 2.5 V, T = 25 °C unless otherwise noted
(1)
Parameter Test conditions Min.
Typ.
(2)
Max.
Unit
FS
So
Dres
Measurement range
Sensitivity
Device resolution
(3)
FS bit set to 00
FS bit set to 01
FS bit set to 11
FS bit set to 00
8 bit representation
FS bit set to 01
8 bit representation
FS bit set to 11
8 bit representation
FS bit set to 00
ODR = 50 Hz
±2.0
±4.0
±8.0
64
32
16
16 g
LSB/ m g g
TCSo
TyOff
TCOff
Sensitivity change vs temperature
Typical zerog
level offset accuracy
(4),(5)
Zerog
level change vs temperature
FS bit set to 00
FS bit set to 00
Max delta from 25 °C
±0.01
±40
±0.5
%/°C m mg g
/°C
Vst
Self-test output change
(6),(7),(8)
FS bit set to 00
X axis
FS bit set to 00
Y axis
FS bit set to 00
Z axis
3
-3
3
17
-17
17
32
-32
32
LSb
LSb
LSb
Top
Wh
Operating temperature range
Product weight
-40
20
+85 °C mgram
1.
The product is factory calibrated at 2.5 V. The operational power supply range is from 2.16 V to 3.6 V.
2.
Typical specifications are not guaranteed
3.
Verified by wafer level test and measurement of initial offset and sensitivity
4.
Typical zero-g level offset value after MSL3 preconditioning
5.
Offset can be eliminated by enabling the built-in high pass filter
6.
The sign of “Self-test output change” is defined by CTRL_REG4 STsign bit (
), for all axes.
7.
Self-test output changes with the power supply. “Self-test output change” is defined as
OUTPUT[LSb]
(CTRL_REG4 ST bit=1)
- OUTPUT[LSb]
(CTRL_REG4 ST bit=0)
. 1LSb=4 g
/256 at 8 bit representation, ±2 g
full-scale
8.
Output data reach 99% of final value after 1/ODR+1 ms when enabling self-test mode, due to device filtering
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Mechanical and electrical specifications LIS331DLM
Table 4.
Symbol
Electrical characteristics @ Vdd = 2.5 V, T = 25 °C unless otherwise noted
(1)
Parameter Test conditions Min.
Typ.
(2)
Max.
Vdd Supply voltage
Vdd_IO I/O pins supply voltage
(3)
Idd
IddLP
Current consumption in normal mode
Current consumption in low-power mode
IddPdn
VIH
VIL
VOH
VOL
Current consumption in power-down mode
Digital high level input voltage
Digital low level input voltage
High level output voltage
Low level output voltage
2.16
1.71
0.8*Vdd_IO
0.9*Vdd_IO
2.5
250
10
1
3.6
Vdd+0.1
0.2*Vdd_IO
0.1*Vdd_IO
ODR
Output data rate in normal mode
DR bit set to 00
DR bit set to 01
DR bit set to 10
PM bit set to 010
50
100
400
0.5
ODR
LP
Output data rate in low-power mode
PM bit set to 011
PM bit set to 100
PM bit set to 101
PM bit set to 110
1
2
5
BW
Ton
System bandwidth
(4)
Turn-on time
(5)
ODR = 100 Hz
10
ODR/2
1/ODR+1ms
Top Operating temperature range -40 +85
1.
The product is factory calibrated at 2.5 V. The operational power supply range is from 2.16 V to 3.6 V.
2.
Typical specification are not guaranteed
3.
It is possible to remove Vdd maintaining Vdd_IO without blocking the communication busses, in this condition the measurement chain is powered off.
4.
5.
Time to obtain valid data after exiting power-down mode
Unit
V
V
µA
µA
µA
V
Hz
Hz
V
V
V
Hz s
° C
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LIS331DLM
2.3 Communication interface characteristics
2.3.1
Table 5.
Symbol tc(SPC) fc(SPC) tsu(CS) th(CS) tsu(SI) th(SI) tv(SO) th(SO) tdis(SO)
SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top.
SPI slave timing values
Parameter
SPI clock cycle
SPI clock frequency
CS setup time
CS hold time
SDI input setup time
SDI input hold time
SDO valid output time
SDO output hold time
SDO output disable time
6
8
5
15
Min.
100
Value
( 1 )
Max.
10
50
9
50
Figure 3.
SPI slave timing diagram
(2)
Mechanical and electrical specifications
Unit ns
MHz ns
CS
(3) (3) t su(CS) t c(SPC) t h(CS)
SPC
(3) (3)
SDI (3) t su(SI) t h(SI)
MSB IN t v(SO)
MSB OUT t h(SO)
LSB IN
LSB OUT t dis(SO)
(3)
(3) SDO (3)
1.
Values are guaranteed at 10MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production
2.
Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both Input and output port
3.
When no communication is on-going, data on CS, SPC, SDI and SDO are driven by internal pull-up resistors
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Mechanical and electrical specifications LIS331DLM
2.3.2 I
2
C - Inter IC control interface
Subject to general operating conditions for Vdd and top.
Table 6.
I
2
C slave timing values
Symbol Parameter f
(SCL) t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t r(SDA) t r(SCL)
SCL clock frequency
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
SDA and SCL rise time
I
2
C standard mode
(1)
Min
0
Max
100
4.7
4.0
250
0.01
3.45
1000 t f(SDA) t f(SCL)
SDA and SCL fall time 300 t h(ST)
START condition hold time 4 t su(SR)
Repeated START condition setup time
4.7
t su(SP)
STOP condition setup time 4 t w(SP:SR)
Bus free time between STOP and START condition
4.7
1.
Data based on standard I
2
C protocol requirement, not tested in production
2.
Cb = total capacitance of one bus line, in pF
I
2
C fast mode
(1)
Min
0
Max
400
1.3
0.6
100
0.01
20 + 0.1C
b
(2)
20 + 0.1C
b
( 2)
0.6
0.9
300
300
0.6
0.6
1.3
Figure 4.
I
2
C Slave timing diagram
(a)
SDA
START
Unit
KHz
µs ns
µs ns
µs t su(SR) t w(SP:SR)
REPEATED
START
START t f(SDA) t r(SDA) t su(SDA) t h(SDA) t su(SP)
STOP
SCL t h(ST) t w(SCLL) t w(SCLH) t r(SCL) t f(SCL) a.
Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both port
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LIS331DLM
2.4
Mechanical and electrical specifications
Absolute maximum ratings
Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Table 7.
Symbol
Absolute maximum ratings
Ratings
Vdd Supply voltage
Vdd_IO I/O pins supply voltage
Vin
Input voltage on any control pin
(CS, SCL/SPC, SDA/SDI/SDO, SDO/SA0)
Maximum value
-0.3 to 6
-0.3 to 6
Unit
V
V
V
A
POW
A
UNP
T
OP
T
STG
ESD
Acceleration (any axis, powered, Vdd = 2.5 V)
Acceleration (any axis, unpowered)
Operating temperature range
Storage temperature range
Electrostatic discharge protection
-0.3 to Vdd_IO +0.3
3000 g
for 0.5 ms
10000 g for 0.1 ms
3000 g
for 0.5 ms
10000 g
for 0.1 ms
-40 to +85
-40 to +125
4 (HBM)
1.5 (CDM)
200 (MM)
°C
°C kV kV
V
Note: Supply voltage on any pin should never exceed 6.0 V
This is a mechanical shock sensitive device, improper handling can cause permanent damages to the part
This is an ESD sensitive device, improper handling can cause permanent damages to the part
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Mechanical and electrical specifications LIS331DLM
2.5 Terminology
2.5.1 Sensitivity
Sensitivity describes the gain of the sensor and can be determined e.g. by applying 1 g acceleration to it. As the sensor can measure DC accelerations this can be done easily by pointing the axis of interest towards the center of the earth, noting the output value, rotating the sensor by 180 degrees (pointing to the sky) and noting the output value again. By doing so, ±1 g acceleration is applied to the sensor. Subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This value changes very little over temperature and also time. The sensitivity tolerance describes the range of sensitivities of a large population of sensors.
2.5.2 Zerog
level
Zerog level offset (TyOff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. A sensor in a steady state on a horizontal surface will measure 0 g in X axis and 0 g in Y axis whereas the Z axis will measure 1 g . The output is ideally in the middle of the dynamic range of the sensor (content of OUT registers 00h, data expressed as 2’s complement number). A deviation from ideal value in this case is called Zerog offset. Offset is to some extent a result of stress to MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes little over temperature, see “Zerog level change vs. temperature”. The Zerog level tolerance (TyOff) describes the standard deviation of the range of Zerog levels of a population of sensors.
2.5.3 Self-test
Self-test allows to check the sensor functionality without moving it. The Self-test function is off when the self-test bit (ST) of CTRL_REG4 (control register 4) is programmed to ‘0‘.
When the self-test bit of CTRL_REG4 is programmed to ‘1‘ an actuation force is applied to the sensor, simulating a definite input acceleration. In this case the sensor outputs will exhibit a change in their DC levels which are related to the selected full scale through the device sensitivity. When self-test is activated, the device output level is given by the algebric sum of the signals produced by the acceleration acting on the sensor and by the electrostatic test-force. If the output signals change within the amplitude specified inside
Table 3 , then the sensor is working properly and the parameters of the interface chip are
within the defined specifications.
2.5.4 Sleep to wake-up
The “sleep to wake-up” function, in conjunction with low-power mode, allows to further reduce the system power consumption and develop new smart applications.
LIS331DLM may be set in a low-power operating mode, characterized by lower date rates refreshments. In this way the device, even if sleeping, keep on sensing acceleration and generating interrupt requests.
When the “sleep to wake-up” function is activated, LIS331DLM is able to automatically wake-up as soon as the interrupt event has been detected, increasing the output data rate and bandwidth.
With this feature the system may be efficiently switched from low-power mode to fullperformance depending on user-selectable positioning and acceleration events, thus ensuring power saving and flexibility.
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LIS331DLM
3 Functionality
Functionality
The LIS331DLM is a “nano”, low-power, digital output 3-axis linear accelerometer packaged in a LGA package. The complete device includes a sensing element and an IC interface able to take the information from the sensing element and to provide a signal to the external world through an I
2
C/SPI serial interface.
A proprietary process is used to create a surface micro-machined accelerometer. The technology allows to carry out suspended silicon structures which are attached to the substrate in a few points called anchors and are free to move in the direction of the sensed acceleration. To be compatible with the traditional packaging techniques a cap is placed on top of the sensing element to avoid blocking the moving parts during the moulding phase of the plastic encapsulation.
When an acceleration is applied to the sensor the proof mass displaces from its nominal position, causing an imbalance in the capacitive half-bridge. This imbalance is measured using charge integration in response to a voltage pulse applied to the capacitor.
At steady state the nominal value of the capacitors are few pF and when an acceleration is applied the maximum variation of the capacitive load is in the fF range.
The complete measurement chain is composed by a low-noise capacitive amplifier which converts the capacitive unbalancing of the MEMS sensor into an analog voltage that is finally available to the user by an analog-to-digital converter.
The acceleration data may be accessed through an I
2
C/SPI interface thus making the device particularly suitable for direct interfacing with a microcontroller.
The LIS331DLM features a data-ready signal (RDY) which indicates when a new set of measured acceleration data is available thus simplifying data synchronization in the digital system that uses the device.
The LIS331DLM may also be configured to generate an inertial wake-up and free-fall interrupt signal accordingly to a programmed acceleration event along the enabled axes.
Both free-fall and wake-up can be available simultaneously on two different pins.
The IC interface is factory calibrated for sensitivity (So) and Zerog level (TyOff).
The trimming values are stored inside the device in a non volatile memory. Any time the device is turned on, the trimming parameters are downloaded into the registers to be used during the active operation. This allows to use the device without further calibration.
Doc ID 15102 Rev 4 15/38
Application hints
Figure 5.
LIS331DLM electrical connection
Vdd
10µF
Vdd_IO
100nF
1
16 14
TOP VIEW
13
6 8
INT 1
INT 2
LIS331DLM
16/38
GND
Digital signal from/to signal controller.Signal’s levels are defined by proper selection of Vdd_IO
The device core is supplied through Vdd line while the I/O pads are supplied through
Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 µF Aluminum) should be placed as near as possible to the pin 14 of the device (common design practice).
All the voltage and ground supplies must be present at the same time to have proper
behavior of the IC (refer to Figure 5
). It is possible to remove Vdd maintaining Vdd_IO without blocking the communication bus, in this condition the measurement chain is powered off.
The functionality of the device and the measured acceleration data is selectable and accessible through the I
2
C or SPI interfaces.When using the I
2
C, CS must be tied high.
The functions, the threshold and the timing of the two interrupt pins (INT 1 and INT 2) can be completely programmed by the user through the I
2
C/SPI interface.
The LGA package is compliant with the ECOPACK
®
, RoHS and “Green” standard.
It is qualified for soldering heat resistance according to JEDEC J-STD-020C.
Leave “pin 1 indicator” unconnected during soldering.
Land pattern and soldering recommendations are available at www.st.com
.
Doc ID 15102 Rev 4
LIS331DLM Digital interfaces
The registers embedded inside the LIS331DLM may be accessed through both the I
2
C and
SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode.
The serial interfaces are mapped onto the same pads. To select/exploit the I
2
C interface, CS line must be tied high (i.e. connected to Vdd_IO).
Table 8.
Serial interface pin description
Pin name Pin description
CS
SCL
SPC
SDA
SDI
SDO
SA0
SDO
SPI enable
I
2
C/SPI mode selection (1: I
2
C mode; 0: SPI enabled)
I
2
C serial clock (SCL)
SPI serial port clock (SPC)
I
2
C serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
I
2
C less significant bit of the device address (SA0)
SPI serial data output (SDO)
5.1 I
2
C serial interface
The LIS331DLM I
2
C is a bus slave. The I
2
C is employed to write data into registers whose content can also be read back.
The relevant I
2
C terminology is given in the table below.
Table 9.
Term
Serial interface pin description
Transmitter
Receiver
Master
Slave
Description
The device which sends data to the bus
The device which receives data from the bus
The device which initiates a transfer, generates clock signals and terminates a transfer
The device addressed by the master
There are two signals associated with the I
2
C bus: the serial clock line (SCL) and the serial data line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both the lines are connected to Vdd_IO through a pull-up resistor embedded inside the LIS331DLM. When the bus is free both the lines are high.
The I
2
C interface is compliant with fast mode (400 kHz) I
2
C standards as well as with the normal mode.
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Digital interfaces LIS331DLM
5.1.1 I
2
C operation
The transaction on the bus is started through a START (ST) signal. A START condition is defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After this has been transmitted by the Master, the bus is considered busy. The next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the Master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the Master.
The slave address (SAD) associated to the LIS331DLM is 000100xb. SDO / SA0 pad can be used to modify less significant bit of the device address. If SA0 pad is connected to voltage supply, LSb is ‘1’ (address 0001001b) else if SA0 pad is connected to ground, LSb value is
‘0’ (address 0001000b). This solution permits to connect and address two different accelerometers to the same I
2
C lines.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each byte of data received.
The I
2
C embedded inside the LIS331DLM behaves like a slave device and the following protocol must be adhered to. After the start condition (ST) a slave address is sent, once a slave acknowledge (SAK) has been returned, a 8-bit sub-address (SUB) is transmitted: the
7 LSb represent the actual register address while the MSB enables address auto increment.
If the MSb of the SUB field is ‘1’, the SUB (register address) is automatically incremented to allow multiple data read/write.
The slave address is completed with a Read/Write bit. If the bit was ‘1’ (Read), a repeated
START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (Write) the Master will transmit to the slave with direction unchanged. Table explains how the
SAD+Read/Write bit pattern is composed, listing all the possible configurations.
Table 10.
SAD+Read/Write patterns
Command SAD[6:1] SAD[0] = SA0
Read
Write
Read
Write
000100
000100
000100
000100
1
1
0
0
R/W
1
0
1
0
SAD+R/W
00010001 (11h)
00010000 (10h)
00010011 (13h)
00010010 (12h)
Table 11.
Transfer when master is writing one byte to slave
Master ST SAD + W SUB DATA
Slave SAK SAK SAK
SP
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LIS331DLM Digital interfaces
Table 12.
Transfer when master is writing multiple bytes to slave:
Master ST SAD + W SUB DATA DATA
Slave SAK SAK SAK SAK
SP
Table 13.
Transfer when master is receiving (reading) one byte of data from slave:
Master ST SAD + W SUB SR SAD + R NMAK SP
Slave SAK SAK SAK DATA
Table 14.
Transfer when Master is receiving (reading) multiple bytes of data from slave
Master ST SAD+W SUB SR SAD+R MAK MAK NMAK SP
Slave SAK SAK SAK DATA DATA DATA
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit
(MSb) first. If a receiver can’t receive another complete byte of data until it has performed some other function, it can hold the clock line, SCL LOW to force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and releases the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to receive because it is performing some real time function) the data line must be left HIGH by the slave. The Master can then abort the transfer. A LOW to HIGH transition on the SDA line while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be terminated by the generation of a STOP (SP) condition.
In order to read multiple bytes, it is necessary to assert the most significant bit of the subaddress field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the address of first register to be read.
In the presented communication format MAK is Master Acknowledge and NMAK is no
Master acknowledge.
The LIS331DLM SPI is a bus slave. The SPI allows to write and read the registers of the device.
The serial interface interacts with the outside world with 4 wires: CS , SPC , SDI and SDO .
Doc ID 15102 Rev 4 19/38
Digital interfaces LIS331DLM
Figure 6.
Read and write protocol
CS
SPC
SDI
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of the transmission and goes back high at the end. SPC is the serial port clock and it is controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and
SDO are respectively the serial port data input and output. Those lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC .
Both the Read register and Write register commands are completed in 16 clock pulses or in multiple of 8 in case of multiple bytes read/write. Bit duration is the time between two falling edges of SPC . The first bit (bit 0) starts at the first falling edge of SPC after the falling edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the rising edge of CS .
bit 0
: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is read. In latter case, the chip will drive SDO at the start of bit 8.
bit 1
: MS bit. When 0, the address will remain unchanged in multiple read/write commands.
When 1, the address is auto incremented in multiple read/write commands.
bit 2-7
: address AD(5:0). This is the address field of the indexed register.
bit 8-15
: data DI(7:0) (write mode). This is the data that is written into the device (MSb first).
bit 8-15
: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
In multiple read/write commands further blocks of 8 clock periods will be added. When MS bit is ‘0’ the address used to read/write data remains the same for every block. When MS bit is ‘1’ the address used to read/write data is incremented at every block.
The function and the behavior of SDI and SDO remain unchanged.
20/38
Figure 7.
SPI read protocol
CS
SPC
SDI
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
Doc ID 15102 Rev 4
LIS331DLM Digital interfaces
The SPI Read command is performed with 16 clock pulses. Multiple byte read command is performed adding blocks of 8 clock pulses at the previous one.
bit 0 : READ bit. The value is 1.
bit 1 : MS bit. When 0 do not increment address, when 1 increment address in multiple reading.
bit 2-7 : address AD(5:0). This is the address field of the indexed register. bit 8-15 : data DO(7:0) (read mode). This is the data that will be read from the device (MSb first).
bit 16-...
: data DO(...-8). Further data in multiple byte reading.
Figure 8.
Multiple bytes SPI read protocol (2 bytes example)
CS
SPC
SDI
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
Figure 9.
SPI write protocol
CS
SPC
SDI
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
The SPI Write command is performed with 16 clock pulses. Multiple byte write command is performed adding blocks of 8 clock pulses at the previous one.
bit 0
: WRITE bit. The value is 0.
bit 1
: MS bit. When 0 do not increment address, when 1 increment address in multiple writing.
bit 2 -7
: address AD(5:0). This is the address field of the indexed register. bit 8-15
: data DI(7:0) (write mode). This is the data that is written inside the device (MSb first).
bit 16-...
: data DI(...-8). Further data in multiple byte writing.
Doc ID 15102 Rev 4 21/38
22/38
Digital interfaces
Figure 10.
Multiple bytes SPI write protocol (2 bytes example)
CS
SPC
SDI
LIS331DLM
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8
5.2.3 SPI read in 3-wires mode
3-wires mode is entered by setting to ‘1’ bit SIM (SPI serial interface mode selection) in
CTRL_REG4.
Figure 11.
SPI read protocol in 3-wires mode
CS
SPC
SDI/O
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
The SPI Read command is performed with 16 clock pulses: bit 0 : READ bit. The value is 1.
bit 1 : MS bit. When 0 do not increment address, when 1 increment address in multiple reading.
bit 2-7 : address AD(5:0). This is the address field of the indexed register. bit 8-15 : data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
Multiple read command is also available in 3-wires mode.
Doc ID 15102 Rev 4
LIS331DLM Register mapping
The table given below provides a listing of the 8 bit registers embedded in the device and the related addresses:
Reserved (do not modify)
WHO_AM_I
Reserved (do not modify)
CTRL_REG1
CTRL_REG2
CTRL_REG3
CTRL_REG4
CTRL_REG5
HP_FILTER_RESET
REFERENCE
STATUS_REG
--
OUT_X
--
OUT_Y
--
OUT_Z
Reserved (do not modify)
INT1_CFG
INT1_SOURCE
INT1_THS
INT1_DURATION
INT2_CFG
INT2_SOURCE
INT2_THS
INT2_DURATION
Reserved (do not modify)
Table 15.
Register address map
Name rw r rw rw rw r rw rw r r r r r r rw rw rw rw rw r rw r
Type r
Hex
2E - 2F
30
31
32
33
34
35
36
37
38 - 3F
28
29
2A
2B
2C
2D
00 - 0E
0F
10 - 1F
20
21
22
23
24
25
26
27
Register address
Default Comment
Binary
Reserved
000 1111 00010010 Dummy register
Reserved
010 0000 00000111
010 0001 00000000
010 0010 00000000
010 0011 00000000
010 0100 00000000
010 0101
010 0110 00000000
Dummy register
010 0111 00000000
010 1000 00000000 Not used
010 1001 output
010 1010 00000000 Not used
010 1011 output
010 1100 00000000 Not used
010 1101 output
Reserved
011 0000 00000000
011 0001 00000000
011 0010 00000000
011 0011 00000000
011 0100 00000000
011 0101 00000000
011 0110 00000000
011 0111 00000000
Reserved
Doc ID 15102 Rev 4 23/38
Register mapping LIS331DLM
Registers marked as Reserved must not be changed. The writing to those registers may cause permanent damages to the device.
The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered-up.
24/38 Doc ID 15102 Rev 4
LIS331DLM Register description
The device contains a set of registers which are used to control its behavior and to retrieve acceleration data. The registers address, made of 7 bits, is used to identify them and to write the data through serial interface.
Table 16.
WHO_AM_I register
0 0 0 1 0 0 1
Device identification register.
This register contains the device identifier that for LIS331DLM is set to 12h.
0
Table 17.
CTRL_REG1 register
PM2 PM1 PM0 DR1 DR0 Zen Yen Xen
Table 18.
CTRL_REG1 description
PM2 - PM0
Power mode selection. Default value: 000
(000: Power-down; Others: refer to
)
DR1, DR0
Zen
Data rate selection. Default value: 00
(00:50 Hz; Others: refer to Table 20 )
Z axis enable. Default value: 1
(0: Z axis disabled; 1: Z axis enabled)
Yen
Xen
Y axis enable. Default value: 1
(0: Y axis disabled; 1: Y axis enabled)
X axis enable. Default value: 1
(0: X axis disabled; 1: X axis enabled)
PM bits allow to select between power-down and two operating active modes. The device is in power-down mode when PD bits are set to “000” (default value after boot).
shows all the possible power mode configurations and respective output data rates. Output data in the low-power modes are computed with low-pass filter cut-off frequency defined by
DR1, DR0 bits.
DR bits, in the normal-mode operation, select the data rate at which acceleration samples
are produced. In low-power mode they define the output data resolution. Table 20 shows all
the possible configuration for DR1 and DR0 bits.
Doc ID 15102 Rev 4 25/38
Register description LIS331DLM
Table 19.
Power mode and low-power output data rate configurations
PM2
0
0
PM1
0
0
PM0
0
1
Power mode selection
Power-down
Normal mode
Output data rate [Hz]
ODR
LP
-
ODR
1
1
0
0
1
0
0
1
1
1
0
1
0
1
0
Low-power
Low-power
Low-power
Low-power
Low-power
0.5
1
2
5
10
Table 20.
Normal-mode output data rate configurations and low-pass cut-off frequencies
DR1
(1)
DR0
(1)
Output data rate [Hz]
ODR
Low-pass filter cut-off frequency [Hz]
0
0
1
0
1
0
50
100
400
1.
“11” bit configuration is not allowed and may cause incorrect device functionality.
37
74
292
Table 21.
CTRL_REG2 register
BOOT HPM1 HPM0 FDS HPen2 HPen1 HPCF1 HPCF0
Table 22.
CTRL_REG2 description
BOOT
Reboot memory content. Default value: 0
(0: normal mode; 1: reboot memory content)
HPM1, HPM0
FDS
HPen2
High pass filter mode selection. Default value: 00
(00: normal mode; Others: refer to
)
Filtered data selection. Default value: 0
(0: internal filter bypassed; 1: data from internal filter sent to output register)
High pass filter enabled for Interrupt 2 source. Default value: 0
(0: filter bypassed; 1: filter enabled)
26/38 Doc ID 15102 Rev 4
LIS331DLM Register description
Table 22.
CTRL_REG2 description (continued)
HPen1
High pass filter enabled for Interrupt 1 source. Default value: 0
(0: filter bypassed; 1: filter enabled)
HPCF1,
HPCF0
High pass filter cut-off frequency configuration. Default value: 00
(00: HPc=8; 01: HPc=16; 10: HPc=32; 11: HPc=64)
BOOT bit is used to refresh the content of internal registers stored in the flash memory block. At the device power up the content of the flash memory block is transferred to the internal registers related to trimming functions to permit a good behavior of the device itself.
If for any reason the content of trimming registers was changed it is sufficient to use this bit to restore correct values. When BOOT bit is set to ‘1’ the content of internal flash is copied inside corresponding internal registers and it is used to calibrate the device. These values are factory trimmed and they are different for every accelerometer. They permit a good behavior of the device and normally they have not to be changed. At the end of the boot process the BOOT bit is set again to ‘0’.
Table 23.
High-pass filter mode configuration
HPM1 HPM0 High-pass filter mode
0
0
1
0
1
0
Normal mode (reset reading HP_RESET_FILTER)
Reference signal for filtering
Normal mode (reset reading HP_RESET_FILTER)
HPCF[1:0] . These bits are used to configure high-pass filter cut-off frequency f t
which is given by: f t
= ln
⎛
⎝
1
– ------------
HPc
⎠
⎞
⋅ s
2 π
The equation can be semplified to the following approximated equation: f t
= f
----------------------
6 ⋅ HPc
Table 24.
High-pass filter cut-off frequency configuration
HPcoeff2,1 f t
[Hz]
Data rate = 50 Hz f t
[Hz]
Data rate = 100 Hz
00
01
10
11
1
0.5
0.25
0.125
2
1
0.5
0.25
f t
[Hz]
Data rate = 400 Hz
8
4
2
1
Doc ID 15102 Rev 4 27/38
Register description LIS331DLM
Table 25.
CTRL_REG3 register
IHL PP_OD LIR2 I2_CFG1 I2_CFG0 LIR1 I1_CFG1 I1_CFG0
Table 26.
CTRL_REG3 description
IHL
Interrupt active high, low. Default value: 0
(0: active high; 1: active low)
PP_OD
LIR2
Push-pull/Open drain selection on interrupt pad. Default value 0.
(0: push-pull; 1: open drain)
Latch interrupt request on INT2_SRC register, with INT2_SRC register cleared by reading INT2_SRC itself. Default value: 0.
(0: interrupt request not latched; 1: interrupt request latched)
I2_CFG1,
I2_CFG0
LIR1
I1_CFG1,
I1_CFG0
Data signal on INT 2 pad control bits. Default value: 00.
(see table below)
Latch interrupt request on INT1_SRC register, with INT1_SRC register cleared by reading INT1_SRC register. Default value: 0.
(0: interrupt request not latched; 1: interrupt request latched)
Data signal on INT 1 pad control bits. Default value: 00.
(see table below)
Table 27.
Data signal on INT 1 and INT 2 pad
I1(2)_CFG1 I1(2)_CFG0
0
0
1
1
0
1
0
1
INT 1(2) Pad
Interrupt 1 (2) source
Interrupt 1 source OR interrupt 2 source
Data ready
Boot running
Table 28.
CTRL_REG4 register
0 0 FS1 FS0 STsign 0 ST SIM
28/38 Doc ID 15102 Rev 4
LIS331DLM
Table 29.
CTRL_REG4 description
FS1, FS0
Full-scale selection. Default value: 00.
(00: ±2 g; 01: ±4 g; 11: ±8 g)
STsign
ST
SIM
Self-test sign. Default value: 00.
(0: self-test plus; 1 self-test minus)
Self-test enable. Default value: 0.
(0: self-test disabled; 1: self-test enabled)
SPI serial interface mode selection. Default value: 0.
(0: 4-wire interface; 1: 3-wire interface)
Register description
Table 30.
CTRL_REG5 register
0 0 0 0 0 0 TurnOn1 TurnOn0
Table 31.
CTRL_REG5 description
TurnOn1,
TurnOn0
Turn-on mode selection for sleep to wake function. Default value: 00.
TurnOn bits are used for turning on the sleep to wake function.
Dummy register. Reading at this address zeroes instantaneously the content of the internal high pass-filter. If the high pass filter is enabled all three axes are instantaneously set to 0 g .
This allows to overcome the settling time of the high pass filter.
Table 32.
REFERENCE register
Ref7 Ref6 Ref5 Ref4 Ref3 Ref2 Ref1 Ref0
Table 33.
REFERENCE description
Ref7 - Ref0 Reference value for high-pass filter. Default value: 00h.
This register sets the acceleration value taken as a reference for the high-pass filter output.
When filter is turned on (at least one of FDS, HPen2, or HPen1 bit is equal to ‘1’) and HPM bits are set to “01”, filter out is generated taking this value as a reference.
Doc ID 15102 Rev 4 29/38
Register description LIS331DLM
Table 34.
STATUS_REG register
ZYXOR ZOR YOR XOR ZYXDA ZDA YDA
Table 35.
STATUS_REG description
ZYXOR
X, Y and Z axis data overrun. Default value: 0
(0: no overrun has occurred;
1: new data has overwritten the previous one before it was read)
ZOR
YOR
XOR
ZYXDA
ZDA
YDA
XDA
Z axis data overrun. Default value: 0
(0: no overrun has occurred;
1: a new data for the Z-axis has overwritten the previous one)
Y axis data overrun. Default value: 0
(0: no overrun has occurred;
1: a new data for the Y-axis has overwritten the previous one)
X axis data overrun. Default value: 0
(0: no overrun has occurred;
1: a new data for the X-axis has overwritten the previous one)
X, Y and Z axis new data available. Default value: 0
(0: a new set of data is not yet available; 1: a new set of data is available)
Z axis new data available. Default value: 0
(0: a new data for the Z-axis is not yet available;
1: a new data for the Z-axis is available)
Y axis new data available. Default value: 0
(0: a new data for the Y-axis is not yet available;
1: a new data for the Y-axis is available)
X axis new data available. Default value: 0
(0: a new data for the X-axis is not yet available;
1: a new data for the X-axis is available)
XDA
X-axis acceleration data. The value is expressed as two’s complement with 8 bit data representation right justified.
Y-axis acceleration data. The value is expressed as two’s complement with 8 bit data representation right justified.
30/38
Z-axis acceleration data. The value is expressed as two’s complement with 8 bit data representation right justified.
Doc ID 15102 Rev 4
LIS331DLM Register description
Table 36.
INT1_CFG register
AOI 6D ZHIE ZLIE YHIE YLIE XHIE XLIE
Table 37.
INT1_CFG description
AOI
AND/OR combination of Interrupt events. Default value: 0.
6D
ZHIE
6 direction detection function enable. Default value: 0.
Enable interrupt generation on Z high event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value higher than preset threshold)
ZLIE
YHIE
YLIE
XHIE
XLIE
Enable interrupt generation on Z low event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value lower than preset threshold)
Enable interrupt generation on Y high event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value higher than preset threshold)
Enable interrupt generation on Y low event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value lower than preset threshold)
Enable interrupt generation on X high event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value higher than preset threshold)
Enable interrupt generation on X low event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value lower than preset threshold)
Configuration register for interrupt 1 source.
Table 38.
Interrupt 1 source configurations
AOI 6D
0
0
1
1
0
1
0
1
Interrupt mode
OR combination of interrupt events
6 direction movement recognition
AND combination of interrupt events
6 direction position recognition
Doc ID 15102 Rev 4 31/38
Register description LIS331DLM
Table 39.
INT1_SRC register
0 IA ZH ZL YH YL XH XL
Table 40.
INT1_SRC description
IA
Interrupt Active. Default value: 0
(0: no interrupt has been generated; 1: one or more interrupts have been generated)
ZH
ZL
YH
Z high. Default value: 0
(0: no interrupt, 1: Z High event has occurred)
Z low. Default value: 0
(0: no interrupt; 1: Z Low event has occurred)
Y high. Default value: 0
(0: no interrupt, 1: Y High event has occurred)
YL
XH
XL
Y low. Default value: 0
(0: no interrupt, 1: Y Low event has occurred)
X high. Default value: 0
(0: no interrupt, 1: X High event has occurred)
X low. Default value: 0
(0: no interrupt, 1: X Low event has occurred)
Interrupt 1 source register. Read only register.
Reading at this address clears INT1_SRC IA bit (and the interrupt signal on INT 1 pin) and allows the refreshment of data in the INT1_SRC register if the latched option was chosen.
Table 41.
INT1_THS register
0 THS6 THS5 THS4 THS3
Table 42.
INT1_THS description
THS6 - THS0 Interrupt 1 threshold. Default value: 000 0000
THS2 THS1 THS0
Table 43.
INT1_DURATION register
0 D6 D5 D4 D3 D2 D1 D0
32/38 Doc ID 15102 Rev 4
LIS331DLM Register description
Table 44.
INT2_DURATION description
D6 - D0 Duration value. Default value: 000 0000
D6 - D0 bits set the minimum duration of the Interrupt 2 event to be recognized. Duration steps and maximum values depend on the ODR chosen.
Table 45.
INT2_CFG register
AOI 6D ZHIE ZLIE YHIE YLIE XHIE XLIE
Table 46.
INT2_CFG description
AOI
AND/OR combination of Interrupt events. Default value: 0.
(See table below)
6D
6 direction detection function enable. Default value: 0.
(See table below)
ZHIE
ZLIE
YHIE
YLIE
XHIE
XLIE
Enable interrupt generation on Z high event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value higher than preset threshold)
Enable interrupt generation on Z low event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value lower than preset threshold)
Enable interrupt generation on Y high event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value higher than preset threshold)
Enable interrupt generation on Y low event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value lower than preset threshold)
Enable interrupt generation on X high event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value higher than preset threshold)
Enable interrupt generation on X low event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value lower than preset threshold)
Configuration register for Interrupt 2 source.
Table 47.
Interrupt mode configuration
AOI 6D
0
0
0
1
Interrupt mode
OR combination of interrupt events
6 direction movement recognition
Doc ID 15102 Rev 4 33/38
Register description LIS331DLM
Table 47.
Interrupt mode configuration (continued)
AOI 6D Interrupt mode
1
1
0
1
AND combination of interrupt events
6 direction position recognition
Table 48.
INT2_SRC register
0 IA ZH ZL YH YL XH XL
Table 49.
INT2_SRC description
IA
Interrupt active. Default value: 0
(0: no interrupt has been generated; 1: one or more interrupts have been generated)
ZH
ZL
YH
YL
XH
Z high. Default value: 0
(0: no interrupt, 1: Z high event has occurred)
Z low. Default value: 0
(0: no interrupt; 1: Z low event has occurred)
Y high. Default value: 0
(0: no interrupt, 1: Y high event has occurred)
Y low. Default value: 0
(0: no interrupt, 1: Y low event has occurred)
X high. Default value: 0
(0: no interrupt, 1: X high event has occurred)
XL
X low. Default value: 0
(0: no interrupt, 1: X low event has occurred)
Interrupt 2 source register. Read only register.
Reading at this address clears INT2_SRC IA bit (and the interrupt signal on INT 2 pin) and allows the refreshment of data in the INT2_SRC register if the latched option was chosen.
Table 50.
INT2_THS register
0 THS6 THS5 THS4 THS3
Table 51.
INT2_THS description
THS6 - THS0 Interrupt 1 threshold. Default value: 000 0000
THS2 THS1 THS0
34/38 Doc ID 15102 Rev 4
LIS331DLM Register description
Table 52.
INT2_DURATION register
0 D6 D5 D4 D3
Table 53.
INT2_DURATION description
D6 - D0 Duration value. Default value: 000 0000
D2 D1 D0
D6 - D0 bits set the minimum duration of the interrupt 2 event to be recognized. Duration time steps and maximum values depend on the ODR chosen.
Doc ID 15102 Rev 4 35/38
Package information LIS331DLM
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
Figure 12.
LGA16: mechanical data and package dimensions
Ref.
M
P1
P2
T1
T2 d k
E1
L1
L2
N1
N2
A1
A2
A 3
D1 mm
Dimensions inch
Min. Typ. Max. Min.
Typ.
Max.
1.000
0.0
39 4
0.7
8 5
0.200
0.0
3 0
0.007
9
9
2.
8 50 3 .000
3 .150 0.1122 0.11
8 1 0.1240
2.
8 50 3 .000
3 .150 0.1122 0.11
8 1 0.1240
1.000
1.060
0.0
39 4 0.0417
2.000
2.060
0.500
1.000
0.07
0.01
0.0
8
9
39
7 0.0
7
4
8 11
0.040
0.100
0.160 0.0016 0.00
39 0.006
3
0.
8 75 0.0
3 44
1.275
0.0502
0.2
9 0 0.
3 50 0.410 0.0114 0.01
38 0.0161
0.1
9 0 0.250
0.
3 10 0.0075 0.00
98 0.0122
0.150
0.050
0.005
9
0.0020
Outline and mechanical data
LGA16 (
3
x
3
x1.0mm)
Land Grid Array Packa
g
e
36/38 Doc ID 15102 Rev 4
7 983 2 3 1
LIS331DLM Revision history
Table 54.
Document revision history
Date Revision
16-Oct-2008
03-Nov-2008
21-Nov-2008
10-Jul-2009
1
2
3
4
Changes
Initial release
Table
,
have been updated
Updated
,
,
Minor text changes to improve readability
Doc ID 15102 Rev 4 37/38
LIS331DLM
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