STMicroelectronics S2-LPTX Datasheet

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S2-LPTX

S2-LPTX

Datasheet

Sub-1 GHz proprietary radio transmitter

Features

• Frequency bands:

– 413-479 MHz

– 826-958 MHz

• Modulation schemes:

– 2(G)FSK, 4(G)FSK

– OOK, ASK

• Air data rate from 0.1 to 500 kbps

• Ultra-low power consumption:

– 10 mA TX @ +10 dBm

• Programmable RF output power up to +16 dBm

• Programmable channel spacing

• Fast start-up and frequency synthesizer settling time

• Battery indicator and low battery detector

• TX 128 bytes FIFO buffers

• 4-wire SPI interface

• ST companion integrated filter chips are available

• Fully integrated ultra-low power RC oscillator

• Wake-up driven by internal timer or external event

• Flexible packet length with dynamic payload length

• IEEE 802.15.4g hardware packet support with whitening, FEC, CRC

• Wireless M-BUS supported

• Enables operations in the SIGFOX™ network

• Suitable to build systems targeting:

– Europe: ETSI EN 300 220, ETSI EN 303 131

– US: FCC part 15 and part 90

– Japan: ARIB STD T67, T108

– China: SRRC

• Operating temperature range: -40 °C to +105 °C

Applications

• Sensors to Cloud

• Smart metering

• Home energy management systems

• Wireless alarm systems

• Smart home

• Building automation

• Industrial monitoring and control

• Smart lighting systems

DS13100 - Rev 1 - September 2019

For further information contact your local STMicroelectronics sales office.

www.st.com

S2-LPTX

Description

The S2-LPTX is a high performance ultra-low power RF transmitter, intended for RF wireless applications in the sub-1 GHz band. It is designed to operate in both the license-free ISM and SRD frequency bands at 433, 868 and 920 MHz, but can also be programmed to operate at other additional frequencies in the 413-479 MHz,

826-958 MHz.

The S2-LPTX supports different modulation schemes: 2(G)FSK, 4(G)FSK, OOK and

ASK. The air data rate is programmable from 0.1 to 500 kbps.

The S2-LPTX meets the regulatory requirements applicable in territories worldwide, including Europe, Japan, China and the USA.

DS13100 - Rev 1 page 2/64

1

S2-LPTX

Detailed functional description

Detailed functional description

The S2-LPTX integrates a configurable baseband modulator with proprietary fully programmable packet format allowing also:

• IEEE 802.15.4g applications

•

– The hardware packet supports whitening, CRC, FEC

Wireless M-Bus applications

•

•

•

•

•

•

Transmitted data bytes are buffered in a 128 bytes FIFO accessible via SPI interface for host processing.

In addition, the reduced number of external components enables a cost effective solution permitting a compact

PCB footprint.

The S2-LPTX targets volume applications like:

•

Sensors to Cloud

Smart metering

Home energy management systems

Wireless alarm systems

Smart home

Building automation

Industrial monitoring and control

Figure 1. Simplified S2-LPTX block diagram

RADIO CONTROL

TX

VDD TX/VCO

VDD ANA/SYNTH

POWER

CONTROL

PA

SDN

TEMP SENS

CENTRAL

BIAS

BLD

BOD

(acc)

LP Domain

Digital LDOs

POR

BOD

(raw)

LDO

(1V5)

RCO

(34k)

XO

(52M)

FREQ

SYNTH

SD

RM

( SD )

VDD DIG

GPIO0

GPIO1

GPIO2

GPIO3

CSn

SCLK

SDI

SDO

DIV LDO

SYNTH LDO

VCO LDO

DIG LDO

SMPS

VR SYNTH

VR VCO

VR DIG

SMPS2

The transmitter of the S2-LPTX is based on direct synthesis of the RF frequency. The power amplifier (PA) input is the LO generated by the RF synthesizer, while the output level can be configured between -30 dBm and +14 dBm

(+16 dBm in boost mode), at antenna level with 0.5 dB steps.

The data to be transmitted can be provided by an external MCU either through the 128-byte TX FIFO writable via

SPI, or directly using a programmable GPIO pin. The S2-LPTX supports frequency hopping.

DS13100 - Rev 1 page 3/64

S2-LPTX

Detailed functional description

The S2-LPTX has a very efficient power management (PM) system. An integrated switched mode power supply

(SMPS) regulator allows operation from a battery voltage ranging from +1.8 V to +3.6 V, and with power conversion efficiency of 90%.

A crystal must be connected between XIN and XOUT. It is digitally configurable to operate with different crystals.

As an alternative, an external clock signal can be used to feed XIN for proper operation. The S2-LPTX also has an integrated low-power RC oscillator, generating the 34.7 kHz signal used as a clock for the slowest timeouts.

A standard 4-pin SPI bus is used to communicate with the external MCU. Four configurable general purpose I/Os are available.

DS13100 - Rev 1 page 4/64

2

S2-LPTX

Typical application diagram and pin description

Typical application diagram and pin description

This section describes three different application diagrams for the S2-LPTX. Two main configurations are available:

• HPM (high performance mode) configuration

• LPM (low power mode) configuration

In the LPM operating mode the LDOs are bypassed and the SMPS provides the regulator voltage at 1.2 V. Note that in LPM the PA is supplied from SMPS at 1.2 V (instead of 1.5 V as in HPM), so the max. output power is lower than HPM. The figure below shows the suggested configuration with discrete matching network and SMPS-

ON.

Figure 2. Suggested application diagram (embedded SMPS used)

Digital interface

C1

VSMPS2

L0

C2

XTAL

C3

SHUTDOWN

C0

U2

VBATT

3

4

1

2

5

6

VDDSMPS

SMPS1

SMPS2

XOUT

XIN

SDN

SCLK

SDI

SDO

VDDDIG

GND

GND

18

17

16

15

14

13

VBATT

S2-LPTX

C4 C5

C29

C6

L7

L8

C30

VSMPS2

L9

C31

C28

L10

C21

C32

Figure 3. Suggested application diagram (embedded SMPS not used)

shows the suggested configuration with discrete matching network and SMPS-OFF mode.

DS13100 - Rev 1 page 5/64

DS13100 - Rev 1

S2-LPTX

Typical application diagram and pin description

Figure 3. Suggested application diagram (embedded SMPS not used)

Digital interface

C1

VSMPS2

L0

C2

XTAL

C3

SHUTDOWN

C0

U2

VBATT

3

4

1

2

5

6

VDDSMPS

SMPS1

SMPS2

XOUT

XIN

SDN

SCLK

SDI

SDO

VDDDIG

GND

GND

18

17

16

15

14

13

VBATT

S2-LPTX

C4 C5

C29

C6

L7

L8

C30

VSMPS2

L9

C31

C28

L10

C21

C32

Figure 4. Suggested application diagram HPM/LPM (integrated balun, embedded SMPS used)

Digital interface

C0

C2

EXT 1.2-1.8V = VSMPS2

XTAL

C3

SHUTDOWN

U3

VBATT

3

4

1

2

5

6

VDDSMPS

SMPS1

SMPS2

XOUT

XIN

SDN

S2-LPTX

SCLK 18

SDI

SDO

17

16

VDDDIG 15

GND 14

GND 13

VBATT

C4 C5

C29

C6

L7

L8

C30

VSMPS2

L9

C31

C28

L10

C32

C21 page 6/64

2.1

S2-LPTX

Pin diagram

Table 1. Description of the external components of the typical application diagrams

Components

HPM/LPM discrete balun

SMPS ON SMPS OFF

HPM/LPM integrated balun

Description

C0

C1

C2, C3

C4

C5

C6

C10

C16

C21

C28

C29, C30, C31, C32

L0

L7

L8, L9, L10

XTAL

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

Decoupling capacitor for on-chip voltage regulator to digital part

SMPS LC filter capacitors

Crystal loading capacitors

Load capacitor for on-chip voltage regulator to synthesizer (LF part)

Load capacitor for on-chip voltage regulator to VCO

Load capacitor for on-chip voltage regulator

Matching capacitors

Decoupling capacitor

Decoupling capacitor

Notch filter capacitor

Matching capacitors

SMPS LC filter inductor

RF choke inductor or resonating inductor (upon RF network topology)

LC filter/matching inductors

Crystal

Pin diagram

Figure 5. Pin diagram, QFN24 (4x4 mm) package

24 23 22 21 20 19

VDD SMPS

1

SMPS1

2

SMPS2

3

XOUT

4

XIN

5

SDN

6

S2-LPTX

25-GND

7 8 9 10 11 12

SCLK

18

SDI

17

SDO

16

VDD DIG

15

GND

14

GND

13

DS13100 - Rev 1 page 7/64

2.2

S2-LPTX

Pin description

Pin description

6

7

12

13

14

15

16

8

9

10

11

23

24

25

17

18

19

20

21

22

Number

1

2

3

4

5

Pin name

VDD SMPS

SMPS1

SMPS2

XOUT

XIN

SDN

VDD ANA/

SYNTH

VR SYNTH

VREF VCO

VDD VCO/TX

TX

VR RF

GND

GND

VDDDIG

SDO

SDI

SCLK

CSn

GPIO0

GPIO1

GPIO2

GPIO3

VR DIG

GND

Table 2. Pinout

Pin type

Power

Description

1.8 V to 3.6 V analog power supply for SMPS only.

Analog out 1.1 V to 1.8 V SMPS regulator output to be externally filtered

Analog in 1.1 V to 1.8 V SMPS voltage input after LC filtering applied to SMPS1 output

Analog out

Analog in

Crystal oscillator output. Connect to an external crystal or leave floating if driving the XIN pin with an external clock source

Crystal oscillator input. Connect to an external crystal or to an external clock source. If using an external clock source, DC coupling with a minimum 0.2 VDC level is recommended and minimum AC amplitude of 400 mVpp (however, the instantaneous level at input cannot exceed the 0 – 1.4 V range)

Digital in Shutdown input pin. SDN should be = ‘0’ in all modes, except shutdown mode

Power 1.8 V to 3.6 V power

Analog in/out 1.2 V SYNTH-LDO output for decoupling

Analog out 1.2 V VCO-LDO band-gap reference voltage decoupling

Power 1.8 V to 3.6 V power supply

RF output RF output signal

Analog in/out 1.2 V LDO output for decoupling

Ground

Ground of the application board

Ground

Power 1.8 V to 3.6 V power supply

Digital out SPI slave data output

Digital in SPI slave data input

Digital in SPI slave clock input

Digital in SPI chip select

Digital I/O

Digital I/O

Digital I/O

General purpose I/O that may be configured through the SPI registers to perform various functions

Digital I/O

Analog in/out 1.2 V digital power supply output for decoupling

Ground Exposed pad connected to the ground of the application board

DS13100 - Rev 1 page 8/64

3

3.1

3.2

3.3

S2-LPTX

Specifications

Specifications

Absolute maximum ratings

Absolute maximum ratings are those values above which damage to the device may occur. Functional operation under these conditions is not implied. All voltages refer to GND.

Parameter

Supply and SMPS pins

DC voltage on VREG pins

DC voltage on digital input pins

DC voltage on digital output pins

DC voltage on ground pins

DC voltage on analog pins

DC voltage on TX pin

Storage temperature range

VESD-HBM

Table 3. Absolute maximum ratings

Min.

-0.3

-0.3

-0.3

-0.3

-0.3

-0.3

-0.3

-40

-500

Operating range

Typ.

Max.

+3.9

+3.9

+3.9

+3.9

+3.9

+1.8

+3.9

+125

+500

Unit

V

°C

V

Table 4. Operating range

Parameter

Operating battery supply voltage (V

BAT

)

Operating ambient temperature range

1. 2 V when the device works in boost mode with SMPS ON.

Thermal properties

Min.

1.8

(1)

-40

Table 5. Thermal data

Parameter

Thermal resistance junction-ambient

Typ.

3.0

25

QFN24

66

Max.

3.6

+105

Unit

V

°C

Unit

°C/W

DS13100 - Rev 1 page 9/64

3.4

S2-LPTX

Power consumption

Power consumption

Characteristics measured over recommended operating conditions unless otherwise specified. Typical values are referred to 25 °C temperature, V

BAT

= 3.3 V.

Parameter

Supply current

Table 6. Low-power state power consumption

Test conditions

Shutdown

Standby

Sleep

Sleep (FIFOs retained)

Ready

Min.

-

Typ.

2.5

500

700

0.95

350

Max.

-

Unit nA

µA

Table 7. Power consumption fc= 915 MHz

Parameter

Supply current

Test conditions

TX CW @ 14 dBm

TX CW @ 10 dBm

(1)

TX CW @ 16 dBm in Boost

(2)

1. SMPS output voltage 1.2 V, LDOs disable.

2. SMPS output voltage 1.8 V.

Min.

-

Table 8. Power consumption fc= 840-868 MHz

Parameter

Supply current

Test conditions

TX CW @ 14 dBm

TX CW @ 10 dBm

(1)

TX CW @ 16 dBm in Boost

(2)

1. SMPS output voltage 1.2 V, LDOs disable.

2. SMPS output voltage 1.8 V.

Min.

-

Table 9. Power consumption fc= 434 MHz

Parameter

Supply current

1. SMPS output voltage 1.6 V.

2. SMPS output voltage 1.2 V, LDOs disable.

Test conditions

TX CW @ 14 dBm

(1)

TX CW @ 10 dBm

(2)

Min.

-

Typ.

21

11.5

Typ.

22

12.5

32

Max.

-

Typ.

20

11.5

29

Max.

-

Max.

-

Unit mA

Unit mA

Unit mA

DS13100 - Rev 1 page 10/64

3.5

3.6

S2-LPTX

General characterization

General characterization

Data rate DR

Parameter

Table 10. General characteristics

Frequency range

2-(G)FSK

4-(G)FSK

OOK/ASK

Data rate accuracy

Frequency deviation FDEV

Typ.

413 - 479

826 - 958

0.1 - 250

0.2 - 500

0.1 -125

±100

0.15 - 500

If "Manchester" or "3-out-of-6" or FEC coding options are enabled the actual bit rate is affected as follows:

Coding option

NRZ

FEC

Manchester

3-out-of-6

Frequency synthesizer

Table 11. Data rate with different coding options

4(G)FSK data rate [kbps]

500

250

250

333.3

Parameter

Frequency step size

Table 12. Frequency synthesizer parameters

RF carrier phase noise 433 MHz

RF carrier phase noise 868 MHz

RF carrier phase noise 915 MHz

Test conditions

Out-loop divider ratio = 4

10 kHz

100 kHz

1 MHz

10 MHz

10 kHz

100 kHz

1 MHz

10 MHz

10 kHz

100 kHz

1 MHz

10 MHz

50 MHz

-141

-102

-103

-117

-138

-102

-102

-117

-138

23.8

-109

-110

-124

Unit

Hz dBc/Hz

Unit

MHz kbps ppm kHz

DS13100 - Rev 1 page 11/64

3.7

S2-LPTX

Crystal oscillator

Crystal oscillator

Characteristics measured over recommended operating conditions unless otherwise specified. All typical values are referred to 25 °C temperature, V

BAT

= 3.0 V.

The device supports crystals in the range [24-26] MHz and [48-52] MHz.

If the crystal is in the [24–26] MHz range, both the analog and the digital parts must work at this frequency.

Otherwise, if a crystal in the [48-52] MHz range is used, the analog part must work at this frequency and the digital part at this frequency divided by 2. From now on in this document the XTAL oscillator will be indicated with f

XO

and the digital clock with f dig

The divider for the digital part can be set by the PD_CLKDIV bit of the XO_RCO_CONFIG1 in the following way:

• if a [48 – 52] MHz crystal is used, this bit must be 0 (digital divider enabled):

• fdig =   fxo

2 if a [24 – 26] MHz crystal is used, this bit must be 1 (digital divider disabled):

(1) fdig =  fxo

The safest procedure to disable the divider without any risk of glitches in the digital clock is to switch into

STANDBY mode, hence, disable the divider through register setting, and then come back to the READY state.

In order to avoid potential RF performance degradations, the crystal frequency should be chosen to satisfy the following equation: nFCH − ROUND n

FCH fXO fXO ≥ 1MHz where n is an integer in the set [1-7, B] (B is the synthesizer’s divider ratio).

(2)

(3)

Table 13. Crystal oscillator characteristics

Parameter

Crystal frequency

Test conditions Min. Typ. Max.

Unit

24 26

MHz

48 52

± 40 ppm

Frequency tolerance (1)

Minimum requirement on external reference phase noise mask fXO = 26 MHz , to avoid degradation on synthesizer phase/noise

Programmable trans-conductance of the oscillator at start-up

10 kHz

100 kHz

1 MHz

10 MHz

13

-135

-140

-140

-140

43 dBc/Hz mS

Start-up time (2)

VBAT=1.8 V, fXO = 26 MHz

100 µs

1. Including initial tolerance, crystal loading, aging, and temperature dependence. The acceptable crystal tolerance depends on RF frequency and channel spacing/bandwidth.

2. Start-up times are crystal dependent. The crystal oscillator trans-conductance can be tuned to compensate the variation of crystal oscillator series resistance.

Table 14. Ultra-low power RC oscillator

Parameter

Calibrated frequency

Test conditions

Calibrated RC oscillator frequency is derived from crystal oscillator frequency.

Frequency accuracy after calibration

1. Depending on the crystal frequency, the reported value is referring to 50 MHz

Typ.

Unit

33.3 (1)

kHz

±1 %

DS13100 - Rev 1 page 12/64

3.8

S2-LPTX

RF transmitter

RF transmitter

Characteristics measured over recommended operating conditions unless otherwise specified. All typical values are referred to 25 °C temperature, V

BAT

= 3.3 V.

Parameter

Maximum output power

Maximum output power in boost mode

Minimum output power

Output power step

Output power step (1)

1. In this case the register 0x64 is set to 0x4A.

Table 15. RF transmitter characteristics

Test conditions

CW @ antenna level

CW @ antenna level

CW @ antenna level

-10<=output power<=+10 dBm

Output power>+10 dBm

HPM typ.

14

16

-30

0.5

1 (1)

LPM typ.

Unit

10

12

-30

0.5

dBm dB

Parameter

Optimum load impedance

Table 16. PA impedance

Max. permitted VSWR @ antenna level

Test conditions

433 MHz

868 MHz

920 MHz

433 MHz

868 MHz

920 MHz

Typ.

56+25j

30+24j

29+23j

2

5

5

Unit

Ω

Frequency band

413 - 479 MHz

826 - 958 MHz

Table 17. Regulatory standards

Suitable for compliance with:

ETSI EN300 220 category 1.5

FCC part 15, FCC part 90

ARIB STD-T67

Chinese SRRC

ETSI EN300 220-2 category 1.5

FCC part 15

ARIB STD-T108

DS13100 - Rev 1 page 13/64

S2-LPTX

Digital interface specification

3.8.1

3.8.2

3.8.3

3.9

Harmonic emission at 433 MHz

Parameter

H4

H5

H6

H7

H1

H2

H3

Harmonic emission at 840-868 MHz

Table 18. Harmonic emission at 433 MHz

Test conditions

CW

CW

CW

CW

CW

CW

CW

SMPS on

-39

-34

-46

-44

14

-51

-56

Parameter

H1

H2

H3

H4

H5

H6

H7

Harmonic emission at 915 MHz

Table 19. Harmonic emission at 840-868 MHz

Test conditions

CW

CW

CW

CW

CW

CW

CW

HPM/LPM/SMPS on

14

-38

-54

-52

-52

-43

-51

Unit dBm

Unit dBm

Parameter

H1

H2

H3

H4

H5

H6

H7

Digital interface specification

Table 20. Harmonic emission at 915 MHz

Test conditions

CW

CW

CW

CW

CW

CW

CW

HPM/LPM/SMPS on

14

-46

-55

-46

-49

-48

-51

Unit dBm

Parameter

SPI clock frequency

Port I/O capacitance

Table 21. Digital SPI input, output and GPIO specification

Test conditions Min.

Typ.

Max.

Unit

8 10 MHz

1.4

pF

DS13100 - Rev 1 page 14/64

S2-LPTX

Battery indicator

3.10

Note:

Rise time

Fall time

Parameter Test conditions

From 0.1*VDD to 0.9*VDD, CL=20 pF (low output current programming)

From 0.1*VDD to 0.9*VDD, CL=20 pF (high output current programming)

From 0.1*VDD to 0.9*VDD, CL=20 pF (low output current programming)

From 0.1*VDD to 0.9*VDD, CL=20 pF (high output current programming)

Min.

Typ.

Max.

Unit

6.0

ns

2.5

7.0

2.5

ns

Logic high level input voltage

VDD/2

+0.3

V

Logic low level input voltage

VDD/8

+0.3

V

High level output voltage

IOH = -2.4 mA (-4.2 mA into high output current mode).

(5/8)*

VDD+

0.1

V

Low level output voltage

CSn low to positive edge on SCLK in low power mode state

CSn low to positive edge on SCLK in ready state

IOL = +2.0 mA (+4.0 mA into high output current mode).

30

40

0.5

V

µs ns

Battery indicator

Characteristics measured over recommended operating conditions unless otherwise specified. All typical values are referred to 25 °C temperature, V

BAT

= 3.0 V.

Parameter

Battery level thresholds #1

Battery level thresholds #2

Battery level thresholds #3

Battery level thresholds #4

Table 22. Battery indicator and low battery detector

Test conditions

Brownout threshold

Brownout threshold hysteresis

Measured in slow battery variation (static) conditions (inaccurate mode)

Measured in slow battery variation (static) conditions (accurate mode)

Min. Typ. Max. Unit

2.1

2.3

2.5

2.7

V

1.5

1.7

70 mV

For battery-powered equipment, the TX does not transmit at a wrong frequency under low battery voltage conditions. It remains on either channel or stops transmitting. The latter can of course be realized by using a lock detect and/or by switching off the PA under control of the battery monitor. For testing reasons this control is enabled/disabled by SPI.

DS13100 - Rev 1 page 15/64

4

4.1

S2-LPTX

Block description

Block description

Power management

The S2-LPTX integrates a high efficiency step-down converter cascaded with LDOs meant to supply both analog and digital parts. However, an LDO directly fed by the external battery provides a controlled voltage to the data interface block.

The S2-LPTX power management (PM) strategy, besides the basic functionality of providing different blocks with proper supplies, faces two main constraints: the first one is to implement such a power distribution with maximum efficiency, and the second one is to guarantee the isolation among critical blocks.

The efficiency target is obtained by using a switch mode power supply (SMPS) which converts the battery voltage

(1.8 V - 3.6 V) to a lower voltage (settable from 1.2 V to 1.8 V) with efficiency higher than 90%.

The SMPS output voltage can be controlled by the SET_SMPS_LVL field in the PM_CONF0 register. The relation between the SET_SMPS_LVL and the V

OUT

of the SMPS is given by the following table:

SET_SMPS_LVL

001b

010b

011b

100b

101b

110b

111b

Table 23. SMPS output voltage

SMPS output voltage

1.2 V

1.3 V

1.4 V

1.5 V

1.6 V

1.7 V

1.8 V

The SMPS switching frequency is settable by the 2 registers PM_CONF3 and PM_CONF2.

If the KRM_EN is 0, then the digital divider by 4 enabled. In this case SMPS' switching frequency is:

Fsw = fdig

4

If the KRM_EN is 1, the SMPS' switching frequency can be set by the KRM word according to the formula:

(4)

Fsw = Krm fdig

215

As f dig

is the digital domain frequency ( f

XO

if it is 24, 25 or 26 MHz) and ( fXO

2

if f

XO

is 48, 50 or 52 MHz).

The isolation target is reached by using, for each critical block, a dedicated linear low-dropout regulator (LDO), which provides typically 1.2 V output voltage, either from battery level or from SMPS level, depending from the operating mode.

(5)

The S2-LPTX PM can be configured by SPI (BYPASS_LDO field in PM_CONFIG [1] register) in two main modes:

1.

High performance mode (HPM)

2.

Low power mode (LPM)

In HPM all available LDOs supplied from SMPS are used, to get the best possible isolation and minimum lowfrequency noise level and SMPS ripple. SMPS must be set to 1.4 V at least.

In LPM the LDOs connected to the SMPS are by-passed and SMPS must be configured to provide 1.2 V output level to increase the regulation efficiency but with reduced isolation and higher low-frequency noise and SMPS ripple.

The load inductor of the SMPS has to have the following characteristics:

• A typical 10 µH nominal value +/-10%

DS13100 - Rev 1 page 16/64

4.2

S2-LPTX

Power-On-Reset

•

•

A rated current of 100 mA minimum

A DC resistance as low as possible (to guarantee maximum efficiency of the SMPS block), around 1 Ω is a typically good value, but the lower the better

Power-On-Reset

The Power-On-Reset (POR) circuit generates a reset pulse upon power-up which is used to initialize the entire digital logic. Power-on-reset senses V

BAT

voltage.

The S2-LPTX provides an automatic POR circuit, which generates an internal RESETN (active low) level for a time T

RESET

, after the V

BAT

reaches the reset release voltage threshold V

RRT

, as shown in Figure 6. Power-On-

Reset timing and limits . The same reset pulse is generated after a step-down on the input pin SDN (VDD>V

RRT

).

This signal is available on the GPIO0 pin.

Figure 6. Power-On-Reset timing and limits

DS13100 - Rev 1

The parameters VRRT and TRESET are fixed by design in order to guarantee a reliable reset procedure of the state machine. In addition, all the registers are initialized to their default values.

A software command SRES is also available, it generates an internal but partial resetting of the S2-LPTX.

Table 24. POR parameters

Comment Parameter

Reset start-up threshold voltage

Hold pulse width (T hold

, figure below)

Reset pulse width (T reset

, figure below)

Power-on VDD slope

For SDN to be effective

Min.

Typ.

0.5

Max.

1

0.7

2.0

2

Unit

V

µs ms

V/ms

The following picture shows how the S2-LPTX must be controlled, i.e. the SDN signal must be tied to VBAT pin in order to avoid two potential issues during the start-up phase:

1.

A cross conduction can appear on the GPIO until an available command is present on it.

2.

The ESD protection diode from the SDN pad can sink current from the external driver connected to the SDN.

Also the SDN signal generates an internal signal (POC), which disables the digital I/Os when set to 1.

page 17/64

Figure 7. Start-up phase

S2-LPTX

RF synthesizer

Examples of possible connections

Figure 8. Examples of possible connections for SDN pin

4.3

RF synthesizer

A crystal connected to XIN and XOUT provides a clock signal to the frequency synthesizer. The allowed clock signal frequency is either 24, 25, 26, 48, 50, or 52 MHz.

As an alternative, an external clock signal feeds XIN for proper operation. In this option, XOUT can be left either floating or tied to ground.

Since the digital macro cannot be clocked at that double frequency (48, 50 or 52 MHz), a divided clock is used in this case (see Crystal oscillator).

The integrated phase locked loop (PLL) is capable to synthesize a band of frequencies from 413 to 479 MHz, 826 to 958 MHz, providing the input signal for the PA in the TX chain.

Depending on the RF frequency and channel used, a very high accurate crystal or TCXO can be required.

The RF synthesizer implements fractional sigma delta architecture to allow fast settling and narrow channel spacing. It is fully integrated, and it uses a multi-band VCO to cover the whole frequency range. All internal calibrations are automatic.

DS13100 - Rev 1 page 18/64

S2-LPTX

RF synthesizer

4.3.1

According to the frequency synthesized the user must set the charge pump current according to the LO frequency variations, in order to have a constant loop bandwidth. The charge pump current is controlled by the

PLL_CP_ISEL field (SYNT3 register) and the PLL_PFD_SPLIT_EN (SYNTH_CONFIG2). These fields should be set in the following way:

VCO Freq (MHz)

3760

3760

3460

3460 fxo (MHz)

50

25

50

25

Table 25. Charge pump words

PLL_CP_ISEL

010

001

011

010

PLL_PFD_SPLIT_EN

0

1

0

1

ICP (μA)

120

200

140

240

The S2-LPTX provides an automatic and very fast calibration procedure for the frequency synthesizer. If not disabled, it performs the calibration each time the synthesizer is required to lock to the programmed RF channel frequency (transaction from READY to LOCK/TX/). After completion, the S2-LPTX uses the calibration word and is stored in registers.

In order to get the synthesizer locked with the calibration procedure disabled, the correct calibration words must be previously stored in registers by user. The advantage is reduce the LOCK setting time.

The transition time enables the S2-LPTX for frequency hopping operation due to its reduced response time and very quick programming synthesizer.

RF channel frequency settings

The channel center frequency can be programmed as follows:

Center frequency setting fc = fbase + fxo

215

∙ CHSPACE ∙ CHNUM

The f base

sets the main channel frequency; the value depends on the value of f xo

(the frequency of the XTAL oscillator, typically 24-26 MHz or 48-52 MHz.

Base frequency setting fbase = fxo

B

2 ∙ D

∙ SYNT

220 where:

SYNT is a programmable 28-bits integer (SYNT[3:0] registers).

B is the out-of-loop SYNTH divider (BS field of the SYNT3 register):

PLL divider

(6)

(7)

(8)

B =

4 for tℎe ℎigℎ band          826 MHz to 958 MHz,  BS = 0

8 for tℎe middle band       413 MHz to 479 MHz,  BS = 1  

D is the reference divider (REFDIV bit of XO_RCO_CONFIG0 register)

Reference divider

D =

1 if REFDIV = 0  internal  reference divider is disabled

2 if REFDIV = 1  internal  reference divider is enabled  

The resolution in the programmed value of the base frequency depends on the actual band selected.

(9)

DS13100 - Rev 1 page 19/64

4.4

S2-LPTX

Digital modulator fxo [MHz]

24

25

26

48

50

52

Table 26. Resolution frequency

High band resolution [Hz]

11.4

11.9

12.4

22.9

23.8

24.8

Low band resolution [Hz]

5.7

6.0

6.2

11.4

11.9

12.4

The f c

is the frequency related to the channel specified. RF channels can be defined using the CHSPACE and

CHNUM registers. In this way, it is possible to change faster the channel by changing just an 8-bits register, allowing the setting of 256 channels and frequency-hopping sequences. The actual channel spacing is from 793

Hz to 202342 Hz in 793 Hz steps for the 26 MHz configuration and from 1587 to 404685 Hz in 1587 Hz steps for the 52 MHz configuration.

fxo [MHz]

24

25

26

48

50

52

Table 27. Channel spacing resolution

Channel spacing resolution [Hz]

732.42

762.94

793.45

1464.84

1525.88

1586.91

Digital modulator

The S2-LPTX supports frequency modulation: 2-FSK, 4-FSK, 2-GFSK, 4-GFSK as well amplitude modulation

OOK and ASK. Using register, the user can also program an unmodulated carrier for lab test and measurement. A special mode, direct polar modulation, allows building specific modulation scheme controlling directly the amplitude and the frequency of the carrier synthesized. The register MOD_TYPE is used to select one of the following modulation scheme.

MOD_TYPE

0000b

0001b

0010b

0011b

0101b

0110b

0111b

Table 28. Modulation scheme

Modulation scheme

2-FSK

4-FSK

2-GFSK

4-GFSK

ASK/OOK

Direct polar (TX only)

CW

DS13100 - Rev 1 page 20/64

S2-LPTX

Digital modulator

4.4.1

Frequency modulation

For frequency modulation 2-(G)FSK and 4-(G)FSK the frequency deviation can be tuned in wide range that depends on f xo

(XTAL frequency) according the following formula:

Frequency deviation fXO

219

· round D · FDEV_M · B 8

D · B

                                          if FDEV_E = 0 fdev = fXO

219

· round D · 256 + FDEV_M · 2 FDEV_E − 1 · B 8

D · B

     if FDEV_E  > 0

   (10)

Where f xo

is the XTAL oscillation frequency, D is the reference divider and B is the band selector.

The frequency deviation programmed corresponds to the deviation of the outer constellation symbols. The deviation of the inner symbols is 1/3 of such programmed values, as reported in the table below, where 4 options are available.

Furthermore, since the payload is normally arranged in bytes, the arrangement can change the mapping for both

2-(G)FSK and 4-(G)FSK modulations, by using the CONST_MAP (register MOD1), in the following way:

Format

2-(G)FSK

Table 29. Constellation mapping 2-(G)FSK

Symbol

0

1

0

-FDEV

+FDEV

CONST_MAP coding

1

NA

NA

2

+FDEV

-FDEV

3

NA

NA

Format

4-(G)FSK

Symbol

00

01

10

11

Table 30. Constellation mapping 4-(G)FSK

0

-FDEV/3

-FDEV

+FDEV/3

+FDEV

CONST_MAP coding

1 2

-FDEV

-FDEV/3

+FDEV

+FDEV/3

+FDEV/3

+FDEV

-FDEV/3

-FDEV

3

+FDEV

+FDEV/3

-FDEV

-FDEV/3

4.4.1.1

Furthermore, in the 4-(G)FSK it is also possible to swap the symbols using the 4FSK_SYM_SWAP field (register

PCKTCTRL3) as follows:

(11)

When 4FSK_SYM_SWAP  =  0:

When 4FSK_SYM_SWAP  =  1

S0  =   < b7b6 >

S1  =   < b5b4 >

S2  =   < b3b2 >

S3  =   < b1b0 >

S0  =   < b6b7 >

S1  =   < b4b5 >

S2  =   < b2b3 >

S3  =   < b0b1 >

Gaussian shaping

In 2-GFSK or 4-GFSK mode, the Gaussian filter BT product can be set by using the register BT_SEL to 1 or 0.5.

The Gaussian filtering is implemented by poly-phase filtering with eight taps per symbol time. In order to further smooth the filter shape and improve spectral shaping, the output of the filter can be linearly interpolated by setting the register MOD_INTERP_EN.

DS13100 - Rev 1 page 21/64

S2-LPTX

Digital modulator

Note:

4.4.2

4.4.2.1

A mathematical interpolation factor is applied at each sample of the Gaussian filter output. This factor is 64 for data rates corresponding to DATA_RATE_E < 5, it is automatically scaled as

64

2DATA_RATE_E − 5

for 5 ≤

DATA_RATE_E < 11 and it is automatically disabled for DATA_RATE_E = 11.

The actual interpolation factor achieved may be limited by the minimal frequency resolution of the frequency synthesizer.

Amplitude modulation

Amplitude modulation OOK and ASK are both supported by the S2-LPTX. The ASK selection depends on power ramping enable.

When OOK is selected, a bit '1' is transmitted with a programmed power, set by register

PA_POWER[PA_LEVEL_MAX_INDEX], and a bit '0' is transmitted without output power (PA off) and specified by the register PA_POWER[0].

In case PA_POWER[0] = 0 then the modulation will be OOK, otherwise when PA_POWER[0] is not set to zero the modulation will be ASK. The 0/1 mapping can be reversed by setting the CONST_MAP register to any value other than zero.

When ASK is selected, a bit '1' is transmitted with a power ramp increasing from the minimum value specified by register PA_POWER[0] to specified PA maximum level in register PA_POWER[PA_LEVEL_MAX_INDEX], vice versa for a bit '0'. The duration of each power step is a multiple of 1/8 of the symbol time, configurable with the register PA_RAMP_STEP_WIDTH. If more '1's are transmitted consecutively, the PA power maintains the output power at the programmed value. If more '0's are transmitted consecutively, the PA power remains at minimum power for all '0's following the first one.

In order to improve the spectral emission mask in ASK a digital interpolation optional features have been implemented. When this feature is enabled, thought the register PA_INTERP_EN, the modulator linearly interpolates the power values specified in the PA_POWER registers before being applied to the PA.

The interpolation factor of each ramp step is 64 time the data rate corresponding to DATA_RATE_E < 5 it is automatically scaled as 64/2 (DATA_RATE_E-5)

DATA_RATE_E=11.

for 5 ≤ DATA_RATE_E < 11 and it is automatically disabled for

Note that the number of clock cycles between successive PA ticks, for DATA_RATE_E≥5, is always between 8 and 4 (8 for DATA_RATE_M=0; 4 for DATA_RATE_M=65535).

OOK smoothing

•

•

The OOK can be smoothed using a FIR filter added in the data path. This feature is activated by setting the

FIR_EN bit at 1 inside register PA_CONFIG1.

The FIR filter is not fully customizable but it can be set in 3 different configurations that change the spectrum shape (and thus the bandwidth): filter : it is the proper FIR filtering function of the stream of bits 8 times oversampled; ramp : the FIR filter is optimized to perform a ramping between PA_POWER_MAX and PA_POWER_0 (for

OOK should be set to 0).

• switch : logic 1s and 0s are associated with a single value of power and no transition between the 2 is envisaged.

When the FIR_EN bit is 1, the DIG_SMOOTH_EN (PA_POWER_0 register) must be set to 1.

Finally, a 2 nd order Bessel analog filter can be used to smooth the output signal. The bandwidth of this filter should be set according to the data rate used by setting the PA_FC field of the register PA_CONFIG0 according to the following table:

PA_FC bits

00

01

10

11

Table 31. PA Bessel filter words

Cut-off frequency (kHz)

12.5

25

50

100

Max. data rate (kbit/s)

16

32

62.5

125

DS13100 - Rev 1 page 22/64

S2-LPTX

Digital modulator

Note:

4.4.3

The FIR ramping modes are used in a mutually exclusive way with the digital ramping. When the digital ramping is used, the FIR ramping should be disabled. Vice versa, if the FIR ramping is used, the digital one is not used.

Direct polar mode

The S2-LPTX allows the user to drive the SYNTH and the PA at a very low level. The byte couples written in the

TX_FIFO are sampled with a rate related to the DATARATE chip setting (sampling rate = 8*DATARATE).

The first byte of the couple drives the frequency synthesizer to obtain an instantaneous output frequency deviation given by the formula below:

Frequency deviation in polar mode

(12)

Where fdev_programmed is the frequency deviation programmed in the chip by the registers MOD[1:0] (see

Section 4.4.1 Frequency modulation

), fdev_fifo_sample is the first byte of the bytes couple sampled from the

TX_FIFO.

The fdev_fifo_sample is interpreted as a 2-complement 8-bit number, thus it can be either a positive or a negative value.

The instantaneous frequency is given by the formula:

Instantaneous frequency in polar mode f = fc_programmed +  fdev

The second byte of the TX_FIFO couple drives the PA giving an instantaneous output power.

(13)

The output power will be generated according to this value following the same code as the PA_POWER registers

(see

Section 4.4.6.1 PA configuration

).

Figure 9. Direct polar mode

shows how the byte couples are sampled from the TX FIFO and sent to the SYNTH and PA blocks.

Figure 9. Direct polar mode

4.4.4

4.4.4.1

As for the normal TX operations, the TX_FIFO samples are consumed and a management of the

TX_FIFO_THRESHOLD is needed to perform transmissions longer than 128 samples.

The transmission is never automatically stopped and a specific command SABORT should be given to terminate it.

This function is suitable to implement differential binary phase shift keying modulation (DBPSK) such as the data modulation used by the SigFox protocol.

Test modes

Continuous wave

The device can be programmed to generate a continuous wave carrier without any modulation. In this way, the carrier will be continuously transmitted until a SABORT command is sent to the device.

To set the continuous wave the MOD_TYPE field (of the MOD2 register) must be set to 0x7.

DS13100 - Rev 1 page 23/64

S2-LPTX

Digital modulator

4.4.4.2

4.4.5

4.4.6

4.4.6.1

PN9

It is possible to set a pseudo random binary sequence 9 (PN9) as data source for the modulator. In this way, these data are continuously modulated until a SABORT command is sent to the device.

The TXSOURCE field (of the PCKTCTRL1 register) must be set to 0x03.

Data rate

The data rate programmable is from 0.1 kbps to 500 kbps (see Table 1. Description of the external components of the typical application diagrams

for further details).

The data rate formula that relates the value of the DATARATE_M and DATARATE_E registers to the data rate in symbol per second is the following:

Data rate formula fdig ·

DATARATE_M

                                            if DATARATE_E = 0

232

DataRate =   fdig ·

216 + DATARATE_M ∙ 2DATARATE_E

233

    if DATARATE_E > 0 fdig

8 ∙ DATARATE_M                                                      if DATARATE_E  = 15

(14) where f dig

is the digital clock frequency.

In the cases where DATARATE_E<15, the actual modulator timing is generated by a fractional clock divider hence is affected by a certain amount of jitter. In order to have a jitter free data rate generation a specific mode the last equation must be used, DATARATE_E = 15.

Transmitter

The S2-LPTX contains an integrated PA capable of transmitting at output levels programmable between -30 dBm to +14 dBm (+16 dBm in boost mode), at step of 0.5 dB.

The PA is single-ended and has a dedicated pin (TXOUT). The PA output is ramped up and down to prevent unwanted spectral splatter. In TX mode the PA drives the signal generated by the frequency synthesizer out to the antenna terminal. Delivered power, as well as harmonic content, depends on the external impedance seen by the

PA. It is possible to program TX to send an unmodulated carrier.

The output stage is supplied from the SMPS through an external choke and is loaded with a LC-type network which has the function of transforming the impedance of the antenna and filter out the harmonics.

PA configuration

The PA output power level is programmable in 0.5 dB steps. The user can store up to eight output levels to provide flexible PA power ramp-up and ramp-down at the start and end of a frequency modulation transmission as well as ASK modulation shaping.

With the digital power-ramping enabled (PA_RAMP_EN = 1 in the PA_POWER0 register) the ramp starts from the minimum output power programmed and stops at the programmed maximum value, thus a maximum of 8 steps can be set up as shown in

Figure 10. Output power ramping configuration . The interpolation factor ranges from 64

down to 1 depending on the actual data rate. The assumption is that output power monotonically decrease. Each step is held for a programmable time interval expressed in terms of bit period units (T b

/8), maximum value is 3

(which means 4×T b

/8=T b

/2). Therefore, the PA ramp may last up to 4 T b

(about 3.3 ms if the bit rate is 1.2 kbit/s).

Tramp =

PA_RAMP_STEP_LEN + 1 × PA_LEVEL_MAX_IDX + 1

8 × DataRate where DataRate is the transmission data rate expressed in symbols/s.

(15)

The set of eight levels is used to shape the ASK signal. In this case, the modulator works as a counter that counts when transmitting a one and down when transmitting a zero. The counter counts at a rate equal to 8 times the symbol rate (in this case, the step width is fixed by symbol rate).

For OOK modulation, the signal is abruptly switched between two levels only: no power and maximum. This mode is obtained setting the PA_RAMP_EN=0.

With the digital power-ramping, the digital PA interpolation can be enabled through the PA_INTERP_EN field of the MOD1 register.

When this feature is enabled, the power values specified in the PA_POWER registers are linearly interpolated by the modulator before being applied to the PA.

DS13100 - Rev 1 page 24/64

S2-LPTX

Digital modulator

The mathematical interpolation factor applied at each output sample is 64 for data rates corresponding to

DATA_RATE_E < 5, it is then automatically scaled as

64

2DATA_RATE_E − 5

and it is automatically disabled for

DATA_RATE_E = 11.

Figure 10. Output power ramping configuration

4.4.6.2

4.4.6.3

Transmitter data modes

Direct modes are primarily intended to completely bypass the automatic packet handler, in order to give the user maximum flexibility in the choice of frame formats. In specific:

• Direct through FIFO mode : the packet is written in TX FIFO. The user build the packet according to his need including preamble, payload and soon on. The data are transmitted without any processing.

•

•

Direct through GPIO mode : the packet bits are continuously read from one of the GPIO pins, properly configured, and transmitted without any processing. To allow the synchronization of an external data source, a data clock signal is also provided on one of the GPIO pins. Data are sampled by the device on the rising edge of such clock signal; it is the responsibility of the external data source to provide a stable input at this edge.

PN9 mode : a pseudo-random binary sequence is generated internally. This mode is provided for test purposes only.

Data FIFO

In the S2-LPTX there is a TX FIFO for data to be transmitted of 128 bytes. The SPI interface is used to write to the TX FIFO starting from the address 0xFF.

DS13100 - Rev 1 page 25/64

Figure 11. Threshold in FIFO

S2-LPTX

Digital modulator

4.4.7

The TX FIFO has two programmable thresholds (see figure above). An interrupt event occurs when the data in the TX FIFO reaches any of these thresholds. The first threshold is the “FIFO Almost Full” threshold, TX_AF_THR registers. The value in this field corresponds to the desired threshold value in number of bytes + 2. When empty locations (free) amount inside the TX FIFO reaches this threshold limit, an interrupt to the MCU is generated so it can send a TX command to transmit the contents of the TX FIFO. The second threshold for TX is the “FIFO

Almost Empty” threshold, TX_AE_THR register. When the data being shifted out of the TX FIFO reaches the

Almost Empty threshold, an interrupt will be generated also. The MCU could to switch out of TX mode or fill new data into the TX FIFO.

To enable the TX_FIFO thresholds interrupts the FIFO_GPIO_OUT_MUX_SEL must be set to 0.

The FIFO controller detects overflow or underflow in the TX FIFO. It is the responsibility of the MCU to avoid TX

FIFO overflow since the MCU only can decide to writing on the TX FIFO. A TX FIFO overflow results in an error in the TX FIFO content, while an underflow results in the continuous transmission of the last byte stored in the TX

FIFO.

When an overflow or an underflow is detected, the MCU has to issue a SABORT and a FLUSHTXFIFO command before resuming the normal transmitter activity. Regarding to FIFO, when one of these errors is detected an interrupt is generated to the MCU.

The TX FIFO may be flushed by issuing a FLUSHTXFIFO command (see

Table 1. Description of the external components of the typical application diagrams

).

The full status of FIFO is readable on the bit MC_STATE[10] = TX_FIFO_FULL of the MC_STATE registers, and at the same time, the related IRQs is generated.

In the SLEEP state, the FIFO content is retained only if the SLEEP_B mode is selected (bit

SLEEP_MODE_SEL=1 in the register 0x79).

Integrated RCO

The S2-LPTX contains an ultra-low power RC oscillator with accuracy better than 1%. The RC oscillator frequency is calibrated using as a reference the XO frequency. It depends on two values: raw (4 bits) and fine (5 bits). The raw value is obtained by a linear search algorithm in which for each value a counting of half clock reference inside the period of RCO is done. When the correction is near to the final value, a dichotomy search algorithm starts.

The RCO calibration starts as soon as the RCO_CALIBRATION bit is set to 1. When it finishes, the RC_CAL_OK bit is set and the ERROR_LOCK bit is reset.

Moreover, after a sleep or standby state, if the RCO_CALIBRATION bit is kept to 1, when the device returns to the ready state, an RCO calibration automatically runs to compensate some drift.

It is possible to perform an offline calibration of the RCO using the following procedure:

DS13100 - Rev 1 page 26/64

S2-LPTX

Operating modes

4.4.8

4.4.9

4.5

1.

Enable the RCO CALIB setting the bit to 1

2.

Wait until the RC_CAL_OK becomes 1

3.

Copy the RWT_OUT and RFB_OUT (registers 0x94 and 0x95) out values in the RWT_IN and RFB_IN fields

(registers 0x6E and 0x6F)

4.

Disable the RCO CALIB setting the bit to 0

In this way, the RCO works with these values. It is advisable to repeat the RCO calibration to reject effects related to the variation of temperature. It is recommended to use this procedure if the following SLEEP time (i.e. when using LDC mode) is shorter or comparable to the calibration time.

By default, the calibration is disabled at reset to avoid using an out-of-range reference frequency, after the internal clock divider is correctly configured, the user can enable the RCO calibration by register.

Once calibrated, the RCO generates a clock frequency that depends on the XO frequency used:

Table 32. RCO Frequency

Ref. frequency [MHz]

24 or 48

25 or 50

26 or 52

RCO frequency [kHz]

32

33.33

34.66

Low battery indicator

•

•

The battery indicator can provide the user with an indication of the battery voltage level.

There are two blocks to detect battery level:

Brownout with a fixed threshold

Battery level detector with a programmable threshold

The MCU enables optionally these blocks to provide an early warning of impending power failure. It does not reset the system, but gives the MCU time to prepare for an orderly power-down and provides hardware protection of data stored in the program memory.

The low battery indicator function is available in any of the S2-LPTX operation modes. As this function requires the internal bias circuit operation, the overall current consumption in STANDBY, SLEEP, and READY modes increase by 400 µA.

Voltage reference

This block provides the precise reference voltage needed by the internal circuit.

Operating modes

The S2-LPTX is provided with a built-in main controller which controls the switching to the transmitter (TX) state, driven by SPI commands.

In shutdown condition (the S2-LPTX can be switched on/off with the external pin SDN), no internal supply is generated, and all stored data and configurations are lost.

From shutdown, the S2-LPTX can be switched on going to READY state, where the reference clock signal is available.

From READY state, the S2-LPTX can be moved to LOCK state to generate the high precision LO signal and then in TX mode. At the end of the operations, the S2-LPTX can return to READY state or can go to SLEEP state, having a very low power consumption.

SLEEP state can be configured to retain the FIFO content or not enabling very low power mode. If also no wakeup timer is required, the S2-LPTX can be moved from READY to STANDBY state, which has the lowest possible current consumption.

DS13100 - Rev 1 page 27/64

Figure 12. State diagram

S2-LPTX

Operating modes

DS13100 - Rev 1

Three states: READY, STANDBY and LOCK may be defined as stable state.

All other states are transient, which means that, in a typical configuration, the controller remains in those states, at most for any timeout timer duration. Also the READY and LOCK states behave as transients when they are not directly accessed with the specific commands (for example, when LOCK is temporarily used before reaching the

TX state).

Table 33. States

State code

(1)

NA

0x02

0x01

0x03

0x00

0x0C

0x5C

0x50

State name

SHUTDOWN

STANDBY

SLEEP_A

SLEEP_B

READY

LOCK

TX

SYNTH_SETUP

Digital LDO

OFF

ON

SPI

Off

On

On

On

On

On

On

On

XTAL

Off

Off

Off

Off

On

On

On

On

RF synth.

Off

Off

Off

Off

Off

On

On

On

Wake-up timer

Off

Off

On

On

Do not care

Do not care

Do not care

Do not care

1. Other codes are invalid and are an indication of an error condition due to bad register configuration and/or hardware issue in the application board hosting.

Commands are used in the S2-LPTX to change the operating mode and to use its functionality. A command is sent on the SPI interface and may be followed by any other SPI access without pulling CSn high. A command code is the second byte to be sent on the MOSI pin (the first byte must be 0x80). The commands are immediately valid after SPI transfer completion (no need for any CSn positive edge).

page 28/64

S2-LPTX

Operating modes

4.5.1

4.5.2

Note:

Note:

Command list

Command code

0x60

0x62

0x63

0x64

0x66

0x67

0x68

0x70

0x72

0x73

Command name

TX

READY

STANDBY

SLEEP

LOCKTX

SABORT

LDC_RELOAD

SRES

FLUSHTXFIFO

SEQUENCE_UPDA TE

Table 34. Commands

State for execution

READY

STANDBY, SLEEP,

LOCK

READY

READY

Description

Send the S2-LPTX to TX state for transmission

Go to READY state

READY

TX

ANY

ANY

All

ANY

Go to STANDBY state

Go to SLEEP state

Go to LOCK state by using the TX configuration of the synthesizer

Exit from TX state and go to READY state

Reload the LDC timer with a pre-programmed value stored in registers

Reset the S2-LPTX state machine and registers values

Clean the TX FIFO

Reload the packet sequence counter with the value stored in register

State transaction response time

Initial state

SHUTDOWN

READY

READY

READY

TX

STANDBY/SLEEP

LOCK

Table 35. Response time

Final state

READY

STANDBY/ SLEEP

LOCK with no VCO calibration

LOCK with VCO calibration

READY

READY

TX

Response time [µs]

500

3

70

85

1

100

26

The transition time enables the S2-LPTX for frequency hopping operation due to its reduced response time and very quick programming synthesizer. The response time depends on frequency of the clock in digital domain, from 24 MHz to 26 MHz.

The first bit of preramble is sent after TX state is reached, if PA ramping is not enabled. If PA ramping is

enabled, the first bit is sent after tramp (see Section 4.4.6.1 PA configuration ).

DS13100 - Rev 1 page 29/64

S2-LPTX

Operating modes

4.5.3

•

Sleep states

S2-LPTX provides 2 SLEEP states:

• SLEEP without FIFO retention (SLEEP_A): in this low power state, the device keeps all the register values but not the TX FIFO. This is the device default SLEEP state.

SLEEP with FIFO retention (SLEEP_B): in this low power state, the device keeps the content of the registers and the FIFO.

The responsibility of the SLEEP type to be used is demanded to the user. To select the SLEEP mode, the bit

SLEEP_MODE_SEL (register 0x79) can be used. If this bit is set to 0, SLEEP_A is used each time the device enters SLEEP (by SPI command, LDC flow). If it is 1, SLEEP_B is used instead.

The usage of SLEEP_B mode is mandatory in the configuration like LDC in Tx.

DS13100 - Rev 1 page 30/64

5

5.1

S2-LPTX

Packet handler engine

Packet handler engine

The S2-LPTX offers a highly flexible and fully programmable packet handler (framer) that build the packet according to the user configuration settings. The packet types are available: BASIC format 802.15.4g packet format and UART over the air packet format.

WMBUS format is supported but it can be obtained using the proper features combination.

The device supports 3 different packet formats. The current packet format is set by the PCK_FRMT field of the

PCKTCTRL3 register.

In particular:

• 0: Basic packet format

• 1: 802.15.4g packet format

• 2: UART over the air packet format

BASIC packet format

The packet format BASIC is selected by writing 0b in the register PCK_FRMT. The packet frame is as follows.

Preamble

0:2046 bits

Sync

0:32 bits

Table 36. BASIC packet format

Length

0:2 bytes

Address

0:1 bytes

Payload

0:65535 bytes

CRC

0:4 bytes

Postamble

0:510 bits

• Preamble : each preamble is a pair of ‘01’ or ‘10’ from 0 pair to 2046 pairs, programmed by the register

PREAMBLE_LENGTH. The binary sequences transmitted in the various modulation modes are summarized in the following table (leftmost bit is transmitted first).

PREAMBLE_SEL

0

1

2

3

Table 37. Preamble field selection

2(G)FSK or OOK/ASK

0101

1010

1100

0011

4(G)FSK

0111

0010

1101

1000

•

•

Sync : the pattern that identify the start of the frame can be configured in value with a programmable length from 0 to 32 bits, in steps of 1-bit length. The setting is done by the register SYNC_LENGTH. The S2LP supports dual synchronization with a either a primary or a secondary synchronization word. The binary content of the primary SYNC word is programmable through registers SYNCx (x= 1, 2, 3, 4). The binary content of the secondary SYNC word is programmable through registers SEC_SYNCx (x= 1, 2, 3, 4). Both the primary and the secondary word is transmitted according to the value of the SECONDARY_SYNC_SEL register, in particular if SECONDARY_SYNC_SEL = 0 then the primary synchronization word is transmitted; if SECONDARY_SYNC_SEL = 1 then the secondary synchronization word is transmitted. The binary pattern programmed in SYNCx (or SEC_SYNCx) is transmitted on air starting with the most significant bit of x = 1, to the least significant bit of x = 4 according to the programmed synchronization word length.

Length : The device supports packet length transmission from 0 to 65535 bytes, On the transmitting device, the packet length is always set by using the two registers PCKTLENx (x= 1, 2) as: PCKTLEN1 × 256 +

PCKTLEN0. Furthermore, when packet length is enabled (FIX_VAR_LEN=1b):

– FIX_VAR_LEN = 0 means no LENGTH bit field inside the transmitted frame

– FIX_VAR_LEN=1 means LENGTH in the frame according to PACKTLENx and LEN_WID info

DS13100 - Rev 1 page 31/64

S2-LPTX

802.15.4g packet

5.2

•

•

•

•

Destination address : can be enabled or no by the register ADDRESS_LEN. If enabled,

ADDRESS_LEN=1b, its size is 1 byte.

Payload : the main data from transmitter with a max length up to 65535 supported by the embedded automatic packet handler.

CRC : can optionally be calculated on the transmitted data (Length field, Address field and Payload) and appended at the end of the payload (see

Section 5.7 CRC ).

Postamble : The packet postamble allows inserting a certain number of ‘01’ bit pairs at the end of the data packet. The number of postamble bit pairs can be set through the MBUS_PSTMBL register.

802.15.4g packet

Preamble

0:2046 bits

Sync

0:32 bits

Table 38. 802.15.4g packet

PHR

2 bytes

MHR + MAC payload

2:2047 bytes

CRC

0:4 bytes

•

•

•

Preamble : each preamble is a pair of ‘01’ or ‘10’ from 0 pair to 2046 pairs, programmed by the register

PREAMBLE_LENGTH. The binary sequences transmitted in the various modulation modes are summarized in Table 2 (leftmost bit is transmitted first).

Sync : the pattern that identify the start of the frame can be configured in value with a programmable length from 0 to 32 bits, in steps of 1-bit length. The setting is done by the register SYNC_LENGTH. The S2LPTX supports dual synchronization with a either a primary or a secondary synchronization word. The binary content of the primary SYNC word is programmable through registers SYNCx (x= 1, 2, 3, 4). The binary content of the secondary SYNC word is programmable through registers SEC_SYNCx (x= 1, 2, 3, 4). Both the primary or the secondary word is transmitted according to the value of the SECONDARY_SYNC_SEL register, in particular if SECONDARY_SYNC_SEL = 0, the primary synchronization word is transmitted; if

SECONDARY_SYNC_SEL = 1 then the secondary synchronization word is transmitted. The binary pattern programmed in SYNCx (or SEC_SYNCx) is transmitted on air starting with the most significant bit of x = 1, to the least significant bit of x = 4 according to the programmed synchronization word length. For the

802.15.4g packet format, the secondary synchronization word is automatically selected when FEC is enabled (FEC_EN = 1) and the setting of SECONDARY_SYNC_SEL is ignored.

PHR : The PHR (physical header) field is specific for the 802.15.4g packet format and is automatically built by the packet handler block based on current register configuration.

Bit string index

Bit mapping

Field name

0

MS

Mode switch

Table 39. PHR frame

1-2

R

1

-R

0

Reserved

3

FCS

FSC type

4

DW

Data whitening

5-15

L

10

-L

0

Frame length

In particular:

• MS is always set to 0b (mode switch not supported).

• R

1

-R

0

are always set to 00b.

• FCS is set to:

– 0b if CRC mode 3 is selected.

– 1b if CRC mode 5 is selected.

• DW is set to:

– 0b if whitening is disabled, register WHIT_EN = 0.

– 1b if whitening is enabled, register WHIT_EN = 1.

DS13100 - Rev 1 page 32/64

5.3

5.4

S2-LPTX

UART over the air packet format

•

•

•

L

10

-L

0

are set equal to the 11 bits LSB of the packet length registers set by using the two registers

PCKTLENx (x= 1, 2) as: PCKTLEN1 × 256 + PCKTLEN0. The packet length is from 0 to 65535 bytes (MHR

+ MAC Payload + CRC), then LEN_WID = 1b (2 byte length field transmitted).

Payload : the main data from transmitter with a max length up to 65535 supported by the embedded automatic packet handler.

CRC : can optionally be calculated on the transmitted data (PHR, MHR + MAC Payload) and appended at

the end of the payload (see Section 5.7 CRC

)

• In the 802.5.4g the CRC, named FCS in the standard, is considered part of the PSDU (PHY payload) hence the packet length, must include the 2 or 4 CRC bytes:

– If the packet length programmed in PCKTLEN1 and PCKTLEN0 is L and CRC mode is 3, then L-2 bytes are read from the TX FIFO and interpreted as MHR + MAC Payload, 2 bytes CRC are automatically calculated and inserted at the end of the packet in transmission.

– If the packet length programmed in PCKTLEN1 and PCKTLEN0 is L and CRC mode is 5, then L-4 bytes are read/written from/to the TX FIFO and interpreted as MHR + MAC Payload, 4 byte CRC are automatically calculated and inserted at the end of the packet in transmission.

– If CRC mode is 0, then L bytes are read/written from/to the TX FIFO and interpreted as MHR + MAC

Payload + MCS. In this case no CRC calculation, insertion/stripping is done, and it is the responsibility of the MAC layer to process it.

For CRC mode 3, according to the standard specifications, the CRC output is complemented to 1 before transmission.

For CRC mode 5, if the payload length is less than 4 bytes then the payload is zero-padded to reach a minimum length of 4 bytes. The padding bits are only used to compute the CRC and are not transmitted on-air.

UART over the air packet format

Preamble

0:2046 bits

Table 40. UART over the air packet format

Sync

0:32 bits

Payload

0:65535 bytes

When this format is selected, a start bit and a stop bit can be programmed to be added to each byte of the TX

FIFO. Start and stop bits are not added to the SYNC word.

Also, the BYTE_SWAP bit can be set in order to send the FIFO bytes in LSbit first (default is indeed MSbit first).

The current binary value of the start and stop bit can be set through the START_BIT and the STOP_BIT fields of the PCKTCTRL2 register.

Wireless MBUS packet (W-MBUS, EN13757-4)

The W-MBUS packet structure referred to EN13757 can be obtained through registers setting programming the basic packet to fit the specific sub-mode used.

Preamble Sync 1 st block 2 nd block Opt. blocks Postamble

Preamble : the preamble is fully programmable to fit the W-MBUS protocol. The generic setting is a pair of ‘01’ or

‘10’ from 1 pair to 1024 pairs (max. 256 bytes).

Sync : the pattern that identify the start of the frame is fully programmable to fit the W-MBUS protocol. The generic setting is in value with a programmable length from 1 bit to 64 bytes, in steps of 1-bit length.

Data blocks : the data coding can be fully programmed in NRZ, Manchester or 3-out-of-6.

DS13100 - Rev 1 page 33/64

S2-LPTX

Payload transmission order

5.5

5.6

5.6.1

5.6.1.1

5.6.2

5.6.3

Postamble : The packet postamble allows inserting a certain number of ‘01’ bit pairs at the end of the data packet.

The number of postamble bit pairs can be set through the MBUS_PSTMBL register depending on the chosen sub-mode according to the W-MBUS protocol.

Payload transmission order

The bit order of the data from TX FIFO is controlled by the BYTE_SWAP register. In particular, the transmission is

MSB first if BYTE_SWAP = 0 and LSB first if BYTE_SWAP = 1.

Data coding and integrity check

FEC

The device provides hardware support for error correction.

Error correction can be either enabled or disabled according to link reliability and power consumption needs.

Convolution coding (rate 1/2) and interleaving (FEC) can optionally be applied to the data. FEC can be enabled by setting the FEC_EN register. When FEC is enabled the number of transmitted bits is roughly doubled hence the on-air packet duration in time is roughly double as well. The data rate specified in section always applies to the on-air transmitted data.

FEC is applied to all the fields of BASIC packet format, except Preamble, Sync and Postamble. While is applied to all the fields except Preamble and Sync for the 802.15.4g packet format.

For the 802.15.4g packet format, two different coding schemes can be selected depending on the setting of the

FEC_TYPE_4G register. In particular if FEC_TYPE_4G = 0 then the NRNSC encoder is selected, otherwise the

RSC one is selected.

When FEC is enabled then the transmitter automatically selects the secondary SYNC word.

Use of FEC coding is exclusive with Manchester and Three-out-of-six coding.

Interleaving

In order to improve the effectiveness of convolutional encoding, matrix interleaving is applied to the encoded data at the output of the convolutional encoder.

The symbols from the output of the encoder are written raw-wise into a 4x4 matrix buffer starting from the upperleft cell and read column-wise starting from the lower-right cell.

Each pair of encoded symbols corresponding to one single encoded bit is packet into a single matrix cell. For each encoded symbols pair s o

(n) is transmitted first on air, s

1

(n) is transmitted second.

Note that interleaving is always enabled together with FEC for the Basic packet format while it can be optionally enabled in the case of the 802.15.4g packet format by setting to ‘1’ the INT_EN_4G register.

Manchester coding

Manchester coding can be enabled for the Basic packet format only by setting to ‘1’ the MANCHESTER_EN register.

Use of Manchester coding is exclusive with FEC and Three-out-of-six coding.

When Manchester coding is enabled each bit ‘1’ is actually transmitted on air as a ‘10’ sequence while a bit ‘0’ is transmitted as a ‘01’ sequence. If enabled, Manchester encoding is applied to all bits following the SYNC word.

3-out-of-6 coding

The 3-out-of-6 coding is a form of block coding that can be enabled for the Basic packet format for compatibility with the MBUS standard setting to ‘1’ the MBUS_3OF6_EN bit of PCKTCTRL2. This coding is not expected to be used in other packet formats and is exclusive with FEC and Manchester coding.

Coding is done according to the table below.

NRZ code

0000

0001

NRZ-decimal

0

1

Table 41. 3-out-of-6 coding scheme

6-bit code

010110

001101

6-bit decimal

22

13

N. of transitions

4

3

DS13100 - Rev 1 page 34/64

5.7

5.8

S2-LPTX

CRC

NRZ code

0010

0011

0100

0101

0110

1000

1001

1010

1011

1100

1101

1110

1111

NRZ-decimal

2

3

4

5

6

10

11

12

8

9

13

14

15

6-bit code

001110

001011

011100

011001

011010

101100

100101

100110

100011

110100

110001

110010

101001

6-bit decimal

14

11

28

25

26

44

37

38

35

52

49

50

41

N. of transitions

2

3

2

3

4

3

2

3

3

4

2

3

4

CRC

Error detection is implemented by means of cyclic redundancy check codes. The CRC is calculated over all fields excluding preamble and SYNC word. The length of the checksum is programmable to 8, 16, 24 or 32 bits. The following standard CRC polynomials can be selected:

•

• mode 1: 8 bits: the poly is (0x07) X 8 +X 2 +X+1 mode 2: 16 bits: the poly is (0x8005) X

16

+X

15

+X

2

+1

•

•

• mode 3: 16 bits: the poly is (0x1021) X 16 +X 12 +X 5 +1 mode 4: 24 bits: the poly is (0x864CFB) X 24 +X 23 +X 18 +X 17 +X 14 +X 11 +X 10 +X 7 +X 6 +X 5 +X 4 +X 3 +X+1 mode 5: 32 bits the poly is (0x04C011BB7 ) x 32 +x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 +x+1.

802.15.4g compatible

The initial state of the CRC polynomial is state to all 1b in all cases.

Data whitening

To prevent short repeating sequences (e.g., runs of 0's or 1's) that create spectral lines, which may interfere with other transmissions, the device implements a data whitening feature. Data whitening is implemented with a maximum length LFSR generating a pseudo-random binary sequence used to XOR data before entering the encoding chain. The length of the LSFR is set to 9 bits. The pseudo-random sequence is initialized to all 1's.

When enabled through WHIT_EN register, the data are scrambled before being transmitted in such a way that long sequences of zeros or ones become very unlikely and physical layer algorithms perform better.

Data whitening is always recommended.

Data whitening is applied on all fields excluding the preamble, the SYNC words and the postamble for BASIC packet format according to the following scheme:

DS13100 - Rev 1 page 35/64

Figure 13. Data whitening scheme

S2-LPTX

Data whitening

In the case of 802.15.4g packet format, the use of whitening is signaled by the value, if enabled, is applied to all fields following the PHR field, and is performed according to the following block diagram:

Figure 14. Data whitening scheme 802.15.4g

DS13100 - Rev 1 page 36/64

S2-LPTX

Link layer protocol

6

Link layer protocol

6.1

Timeout protocol engine

The S2-LPTX provides programmable timers to reach the lowest low power consumption while at the same time keeping an efficient communication link.

Timer name

LDC timer

(1)

Table 42. Timer description and duration (the values are related to f dig

of 26 MHz)

Description

Set the wake-up period during LDC operations f source

Frco

4 ,

Frco

8

Time step

[µs]

~29

~58

~116

~232

Max. time

~2s

~4s

~8s

~16s

Formula

1 fsource* PRESCALER + 1 *  COUNTER + 1 

PRESCALER : register 0x48, 0x4A

COUNTER: register 0x49, 0x4B

1. The LDC timer can be scaled by 1, 2, 4 or 8.

6.1.1

Low duty cycle mode

The S2-LPTX provides an embedded low duty cycle mode (LDC), that allows reducing the average power consumption to build a synchronized start network where transmitter can go in low power mode periodically to reduce average power consumption.

The LDC mode is controlled essentially by the LDC timer, which periodically wakes up the S2-LPTX to perform a transmission.

The timer used to wait for the wakeup (T

WU

) is clocked by the signal generated by the RCO circuit (or by an external clock from a GPIO pin), and is programmable with the registers LDC_PRESCALER and

LDC_COUNTER. The internal RC oscillator used by the LDC timer must be calibrated just before the LDC mode is used.

After the wake-up signaling from its internal timer, the S2-LPTX switches to TX state and an interrupt request is issued (if enabled and not masked).

The details about LDC operation for the TX device are the following:

1.

The starting state is READY: as soon as user sets the LDC_MODE bit, LDC counter starts in free running mode.

2.

The first TX operation is triggered by the TX command.

3.

First TX is executed always (even if TX FIFO is empty); the next happens only if TX FIFO is not empty.

4.

At first TX, the LDC counter automatically is reloaded.

5.

If TX FIFO is empty, the current slot is skipped and the device remains in SLEEP state.

6.

The TX FIFO can be written during the SLEEP state also.

7.

When the LDC_MODE bit is reset, the LDC counter continues decrementing and a.

If the LDC_MODE bit is cleared during SLEEP mode, then the LDC timer does not wakes up the device any longer. A READY command is needed from MCU.

b.

If the LDC_MODE bit is cleared during the TX operation (so when still in active mode), then the device enters SLEEP mode at the end of the TX.

However, it is also true that: a.

In case the TX FIFO is empty, the device still remains in SLEEP state until the FIFO is written or a

READY command is provided.

b.

In case the TX FIFO is not empty, a last TX operation is performed before the LDC stops.

For the TX, the bit SLEEP_MODE_SEL should be set to 1, selecting the SLEEP_B mode. In this way, FIFO can be written in SLEEP.

DS13100 - Rev 1 page 37/64

7

7.1

S2-LPTX

MCU interface

MCU interface

•

•

•

•

•

•

•

Communication with the MCU goes through a standard 4-wire SPI interface and 4 GPIOs (plus SHUTDOWN pin).

MCU can performs the following operations:

Program the S2-LPTX in different operating modes by sending commands

Write data into the TX FIFO

Configure the S2-LPTX through the registers

Retrieve information from the S2-LPTX

Get interrupt requests and signals from the GPIO pins

Apply external signals to the GPIO pins

Put the S2-LPTX in SHUTDOWN state or exit from SHUTDOWN state.

Serial peripheral interface

•

•

The four-wire SPI interface consist of:

• SCLK : the SPI clock from MCU to the S2-LPTX

• MOSI : data from MCU to the S2-LPTX

MISO : data from the S2-LPTX to MCU

CSn : chip select signal, active low.

•

•

As the MCU is the master, it always drives the CSn and SCLK. According to the active SCLK polarity and phase, the S2-LPTX SPI can be classified as mode 1 (CPOL=0, CPHA=0), which means that the base value of SCLK is zero, data are read on the clock rising edge and data are changed on the clock falling edge. The MISO is in tristate mode when CSn is high. All transfers are MSB first.

The interface allows the following operations:

• Write data (to registers or TX FIFO)

Read data (from registers)

Send commands.

The SPI communication is supported in all the active states, and also during the low power state: STANDBY and

SLEEP.

When accessing the SPI interface, the two status bytes of the MC_STATE (MC_STATE[1], MC_STATE[0]) registers are sent to the MISO pin.

Figure 15. SPI write sequence

DS13100 - Rev 1 page 38/64

DS13100 - Rev 1

Figure 16. SPI read sequence

S2-LPTX

Serial peripheral interface

Figure 17. SPI command sequence

Concerning the first byte, the MSB is an A/C bit (address/commands: 0 indicates that the following byte is an address, 1 indicates that the following byte is a command code), while the LSB is a W/R bit (write/read: 1 indicates a read operation). All other bits must be zero.

Read and write operations are persistently executed while CSn is kept active (low), the address is automatically incremented (burst mode).

Accessing the FIFO is done as usual with the read and write commands, by putting, as address, the code 0xFF.

Burst mode is available to access the sequence of bytes in the FIFO. Clearly, TX-FIFO is accessed with a write operation.

page 39/64

7.2

7.3

S2-LPTX

Interrupts

I/O selection

0

1

2

3

4

7

11

12

5

6

17

18

Interrupts

In order to notify the MCU of a certain number of events an interrupt signal is generated on a selectable GPIO.

The following events trigger an interrupt to the MCU:

Table 43. Interrupts list

Bit

2

5

7

8

15

Events group Interrupt event

16

17

18

19

Packet oriented

Device status related

TX data sent

TX FIFO underflow/overflow error

TX FIFO almost full

TX FIFO almost empty

Wake-up timeout in LDCR mode

(1)

READY (2)

STANDBY state switching in progress

Low battery level

Power-on reset

1. The interrupt flag n.15 is set (and consequently the interrupt request) only when the XO clock is available for the state machine. This time may be delayed compared to the actual timer expiration. However, the real time event can be sensed putting the end-of-counting signal on a GPIO output.

2. The interrupt flag n.16 is set each time the S2-LPTX goes to READY state and the XO has completed its setting transient

(XO ready condition detected).

All interrupts are reported on a set of interrupt status registers and are individually maskable. The interrupt status register must be cleared upon a read event from the MCU.

The status of all the interrupts are reported in the IRQ_STATUS register: bits are high for the events that have generated any interrupts. The interrupts are individually maskable using the IRQ_MASK registers: if the mask bit related to a particular event is programmed at 0, that event does not generate any interrupt request.

GPIOs

The four GPIOs can be configured as follows:

Table 44. GPIO digital output functions

Output signal nIRQ (interrupt request, active low)

POR inverted (active low)

Wake-up timer expiration: ‘1’ when WUT has expired

Low battery detection: ‘1’ when battery is below threshold setting

TX data internal clock output (TX data are sampled on the rising edge of it)

TX state outputs a command information coming from the RADIO_TX block

TX FIFO almost empty flag

TX FIFO almost full flag

Device in a state other than SLEEP or STANDBY: ‘0’ when in SLEEP/STANDBY

Device in STANDBY state

Reserved

TX mode indicator (to enable an external range extender)

DS13100 - Rev 1 page 40/64

DS13100 - Rev 1

S2-LPTX

GPIOs

I/O selection

19

20

21

22

23

24

25

26

27

28

29

30

31

I/O selection

0

1

2

3

4

From 5 to 31

Output signal

VDD (to emulate an additional GPIO of the MCU, programmable by SPI)

GND (to emulate an additional GPIO of the MCU, programmable by SPI)

External SMPS enable signal (active high)

Device in SLEEP state

Device in READY state

Device in LOCK state

Device waiting for a high level of the lock-detector output signal

TX_DATA_OOK signal (internal control signal generated in the OOK analog smooth mode)

Device waiting for a high level of the READY2 signal from XO

Device waiting for timer expiration to allow PM block settling

Device waiting for end of VCO calibration

Device enables the full circuitry of the SYNTH block

Reserved

Table 45. GPIO digital input functions

Input signal

1 >> TX command

TX data input for direct modulation

Wake-up from external input (sensor output)

External clock @ 34.7 kHz (used for LDC modes timing)

Not used page 41/64

S2-LPTX

Register contents

8

Register contents

Name

GPIO0_CONF

GPIO1_CONF

GPIO2_CONF

GPIO3_CONF

Addr

00

01

02

03

Table 46. Register contents

Default Bit Field name

0A

A2

A2

A2

7:3

2

7:3

2

7:3

2

7:3

2

1:0

1:0

1:0

1:0

GPIO_SELECT

RESERVED

GPIO_MODE

GPIO_SELECT

RESERVED

GPIO_MODE

GPIO_SELECT

RESERVED

GPIO_MODE

GPIO_SELECT

RESERVED

GPIO_MODE

Description

Specify the GPIO0 I/O signal, default setting POR (see

Table 44. GPIO digital output functions

).

-

•

•

•

•

•

•

GPIO0 Mode:

01b: Digital input

10b: Digital output low power

11b: Digital output high power

Specify the GPIO1 I/O signal, default setting digital GND

(see Table 44. GPIO digital output functions ).

-

GPIO1 mode:

01b: Digital input1

0b: Digital output low power

11b: Digital output high power

Specify the GPIO2 I/O signal, default setting digital GND

(see Table 44. GPIO digital output functions ).

-

•

•

•

•

•

•

•

GPIO2 mode:

01b: Digital input

10b: Digital output low power

11b: Digital output high power

Specify the GPIO3 I/O signal, default setting digital GND

(see Table 44. GPIO digital output functions ).

-

GPIO3 mode:

00b: Analog

01b: Digital input

10b: Digital output low power

11b: Digital output high power

DS13100 - Rev 1 page 42/64

Name

SYNT3

SYNT2

SYNT1

SYNT0

CHSPACE

CHNUM

MOD4

MOD3

MOD2

Addr Default Bit

7:5

05

06

07

08

0C

0D

0E

0F

10

42

16

27

62

3F

00

83

2B

77

4

3:0

7:0

7:0

7:0

7:0

7:0

7:0

7:0

7:4

3:0

S2-LPTX

Register contents

Field name

PLL_CP_ISEL

BS

SYNT[27:24]

SYNT[23:16]

SYNT[15:8]

SYNT[7:0]

CH_SPACE

CH_NUM

DATARATE_M[15:8]

DATARATE_M[7:0]

MOD_TYPE

DATARATE_E

Description

Set the charge pump current according to the XTAL frequency (see

Table 34. Commands

).

•

•

Synthesizer band select. This parameter selects the out-of loop divide factor of the synthesizer:

0: 4, band select factor for high band

1: 8, band select factor for middle band (see

Section 4.3.1 RF channel frequency settings

).

MSB bits of the PLL programmable divider.

Intermediate bits of the PLL programmable divider (see

Section 4.3.1 RF channel frequency settings

).

Intermediate bits of the PLL programmable divider (see

Section 4.3.1 RF channel frequency settings

).

LSB bits of the PLL programmable divider (see

Section 4.3.1 RF channel frequency settings

).

Channel spacing setting.

Channel number. This value is multiplied by the channel spacing and added to the synthesizer base frequency to generate the actual RF carrier frequency.

The MSB of the mantissa value of the data rate equation.

The LSB of the mantissa value of the data rate equation.

•

•

•

•

•

•

•

•

•

Modulation type:

0: 2-FSK

1: 4-FSK

2: 2-GFSK BT=1

3: 4-GFSK BT=1

5: ASK/OOK

6: polar mode

7: unmodulated

10: 2-GFSK BT=0.5

11: 4-GFSK BT=0.5

The exponent value of the data rate equation.

DS13100 - Rev 1 page 43/64

Name

MOD1

MOD0

PCKTCTRL6

PCKTCTRL5

PCKTCTRL4

PCKTCTRL3

S2-LPTX

Register contents

12

2B

Addr Default Bit

7

6

11 03

2C

2D

93

80

10

00

5:4

3:0

7:0

7:2

1:0

7:0

7

6:4

3

2:0

7:6

2E 20

5:4

3

2

1:0

Field name

PA_INTERP_EN

MOD_INTERP_EN

CONST_MAP

FDEV_E

FDEV_M

SYNC_LEN

PREAMBLE_LEN[9:8]

PREAMBLE_LEN[7:0]

LEN_WID

RESERVED

ADDRESS_LEN

RESERVED

PCKT_FRMT

RESERVED

FSK4_SYM_SWAP

BYTE_SWAP

PREAMBLE_SEL

Description

1: enable the PA power

interpolator (see Section

4.4.6.1 PA configuration

).

1: enable frequency interpolator for the GFSK

shaping (see Section

4.4.1.1 Gaussian shaping ).

Select the constellation map for 4-(G)FSK or 2-(G)FSK modulations (see

Table 38. 802.15.4g packet and Table 39. PHR frame ).

The exponent value of the frequency deviation equation.

The mantissa value of the frequency deviation equation.

The number of bits used for the SYNC field in the packet.

The MSB of the number of '01 or '10' of the preamble of the packet.

The LSB of the number of '01 or '10' of the preamble of the packet.

•

•

The number of bytes used for the length field:

0: 1 byte

1: 2 bytes.

-

1: include the ADDRESS field in the packet.

-

•

•

•

Format of packet:

0: Basic

1: 802.15.4g

2: UART

(see Section 5 Packet handler engine )

-

Select the symbol mapping for 4(G)FSK.

Select the transmission order between MSB and LSB.

Select the preamble pattern.

DS13100 - Rev 1 page 44/64

Name

PCKTCTRL2

S2-LPTX

Register contents

Addr Default

2F 00

2

1

Bit

7:6

5

4

3

0

Field name

RESERVED

FCS_TYPE_4G

FEC_TYPE_4G/STOP_BIT

INT_EN_4G/START_BIT

MBUS_3OF6_EN

MANCHESTER_EN

FIX_VAR_LEN

Description

-

•

•

•

•

This is the FCS type in header field of 802.15.4g

packet.

–

–

If the 802.15.4 mode is enabled, this is the FCS type in header field of

802.15.4g packet.

Select the FEC type of

802.15.4g packet:

0: NRNSC

1: RSC.

If the UART packet is enabled, this is the value of the STOP_BIT.

If the 802.15.4 mode is enabled, 1: enable the interleaving of

802.15.4g packet.

If the UART packet is enabled, this is the value of the

START_BIT.

1: enable the 3-out-of-6 encoding/decoding.

•

•

1: enable the Manchester encoding/decoding.

Packet length mode:

0: No LENGTH field inserted in the basic packet

1: LENGTH field inserted in the basic data packet according to LEN_WID and

PCKTLEN3 register value

DS13100 - Rev 1 page 45/64

Name

PCKTCTRL1

PCKTLEN1

PCKTLEN0

SYNC3

SYNC2

SYNC1

SYNC0

QI

PCKT_PSTMBL

S2-LPTX

Register contents

Addr Default Bit

30

31

32

33

34

35

36

37

38

2C

00

14

88

88

88

88

01

00

1

0

7:0

7:0

7:0

7:0

7:0

7:0

7:5

4:1

0

7:0

4

3:2

7:5

Field name

CRC_MODE

WHIT_EN

TXSOURCE

SECOND_SYNC_SEL

FEC_EN

PCKTLEN1

PCKTLEN0

SYNC3

SYNC2

SYNC1

SYNC0

Reserved

Reserved

Reserved

PCKT_PSTMBL

•

•

•

•

•

•

Description

CRC field:

0: no CRC field

1: CRC using poly 0x07

2: CRC using poly

0x8005

3: CRC using poly

0x1021

4: CRC using poly

0x864CBF

5: CRC using poly

0x04C011BB7

•

•

•

•

1: enable the whitening mode.

Tx source data:

0: normal mode

1: direct through FIFO

2: direct through GPIO

3: PN9

•

•

0 select the primary

SYNC word

1 select the secondary

SYNC word.

1: enable the FEC encoding in TX

MSB of length of packet in bytes.

LSB of length of packet in bytes.

SYNC word byte 3.

SYNC word byte 2.

SYNC word byte 1.

SYNC word byte 0.

-

-

-

Set the packet postamble length.

DS13100 - Rev 1 page 46/64

S2-LPTX

Register contents

Name

PROTOCOL2

PROTOCOL1

FIFO_CONFIG1

FIFO_CONFIG0

PCKT_FLT_GOALS3

PCKT_FLT_GOALS2

PCKT_FLT_GOALS1

PCKT_FLT_GOALS0

TIMERS3

TIMERS2

TIMERS1

TIMERS0

3E

3F

42

43

44

45

48

49

4A

4B

30

30

00

00

00

00

01

00

01

00

Addr Default

39

3A

40

00

Bit

7

6

5

4:3

6:0

7

6:0

7

0

7

2

1

6

5

4

3

7:0

7:0

7:0

7:0

7:0

7:0

7:0

7:0

2

1:0

Field name

Reserved

Reserved

Reserved

TX_SEQ_NUM_RELOAD

TX sequence number to be used when counting reset is required using the related command.

FIFO_GPIO_OUT_MUX_SEL

1: select the almost empty/full control for TX FIFO.

0: almost empty/full control for

TX FIFO disabled.

LDC_TIMER_MULT

LDC_MODE

•

•

•

•

Set the LDC timer multiplier factor:

00b: x1

01b: x2

10b: x4

11b: x8.

1: enable the low duty cycle mode.

Reserved

Reserved

Description

-

-

-

-

-

-

Reserved

Reserved

Reserved

Reserved

RESERVED

TX_AFTHR

RESERVED

TX_AETHR

DUAL_SYNC3

DUAL_SYNC2

DUAL_SYNC1

DUAL_SYNC0

LDC_TIMER_PRESC

LDC_TIMER_CNTR

LDC_RELOAD_PRSC

LDC_RELOAD_CNTR

-

Set the TX FIFO almost full threshold.

-

Set the TX FIFO almost empty threshold.

If dual sync mode enabled: dual SYNC word byte 3.

If dual sync mode enabled: dual SYNC word byte 2.

If dual sync mode enabled: dual SYNC word byte 1.

If dual sync mode enabled: dual SYNC word byte 0, RX packet destination field.

Prescaler for wake up timer.

Counter for wake up timer.

Prescaler value for reload operation of wake up timer.

Counter value for reload operation of wake up timer.

DS13100 - Rev 1 page 47/64

Name

IRQ_MASK3

IRQ_MASK2

IRQ_MASK1

IRQ_MASK0

PA_POWER8

PA_POWER7

PA_POWER6

PA_POWER5

PA_POWER4

PA_POWER3

PA_POWER2

PA_POWER1

PA_POWER0

S2-LPTX

Register contents

62 47

7:0

7:0

7

6:0

7

6:0

7

6:0

7

6:0

7

6:0

7

6:0

7

6:0

7

6:0

7

Bit

7:0

7:0

6

5

4:3

2:0

5D

5E

5B

5C

5F

Addr

50

51

52

53

5A

Default

00

00

00

00

01

24

30

0C

18

48

60

61

60

00

INT_MASK[7:0]

RESERVED

PA_LEVEL8

RESERVED

PA_LEVEL_7

RESERVED

PA_LEVEL_6

RESERVED

PA_LEVEL_5

RESERVED

PA_LEVEL_4

RESERVED

PA_LEVEL_3

RESERVED

PA_LEVEL_2

RESERVED

PA_LEVEL_1

Field name

INT_MASK[31:24]

INT_MASK[23:16]

INT_MASK[15:8]

DIG_SMOOTH_EN

PA_MAXDBM

PA_RAMP_EN

PA_RAMP_STEP_LEN

PA_LEVEL_MAX_IDX

Description

Enable the routing of the interrupt flag on the configured IRQ GPIO.

Enable the routing of the interrupt flag on the configured IRQ GPIO.

Enable the routing of the interrupt flag on the configured IRQ GPIO.

Enable the routing of the interrupt flag on the configured IRQ GPIO.

-

Output power level for 8 th slot.

-

Output power level for 7 th slot.

-

Output power level for 6 th slot.

-

Output power level for 5 th slot.

-

Output power level for 4 th slot.

-

Output power level for 3 rd slot.

-

Output power level for 2 nd slot.

-

Output power level for 1 st slot.

1: enable the generation of the internal signal TX_DATA which is the input of the FIR.

Needed when FIR_EN=1.

1: configure the PA to send maximum output power.

Power ramping is disable with this bit set to 1.

1: enable the power ramping.

Set the step width (unit: 1/8 of bit period).

Final level for power ramping or selected output power index.

DS13100 - Rev 1 page 48/64

Name

PA_CONFIG1

PA_CONFIG0

SYNTH_CONFIG2

VCO_CONFIG

S2-LPTX

Register contents

Addr Default

63

64

65

68

03

8A

D0

03

1

0

4

3:0

7:3

2

1:0

7:6

5

Bit

7:4

3:2

7:4

3

2

1:0

Field name

RESERVED

FIR_CFG

FIR_EN

RESERVED

PA_DEGEN_TRIM

PA_DEGEN_ON

SAFE_ASK_CAL

PA_FC

RESERVED

PLL_PFD_SPLIT_EN

RESERVED

RESERVED

VCO_CALAMP_EXT_SEL

VCO_CALFREQ_EXT_SEL

RESERVED

•

•

•

Description

-

FIR configuration:

00b: filtering

01b: ramping

10b: switching (see

Section 4.4.2.1 OOK smoothing

)

1: enable FIR (see Section

4.4.2.1 OOK smoothing

-

11xx ® code threshold: 485

10xx ® code threshold: 465

01xx ® code threshold: 439

00xx ® code threshold: 418 xx11 ® clamp voltage: 0.55 V xx10 ® clamp voltage: 0.50 V xx01 ® clamp voltage: 0.45 V xx00 ® clamp voltage: 0.40 V.

Enables the 'degeneration' mode that introduces a predistortion to linearize the power control curve.

During a TX operation, enables and starts the digital

ASK calibrator.

•

•

•

•

PA Bessel filter bandwidth:

00b: 12.5 kHz (data rate

16.2 kbps)

01b: 25 kHz (data rate

32 kbps)

10b: 50 kHz (data rate

62.5 kbps)

11b: 100 kHz (data rate

125 kbps), (see

Section

4.4.2.1 OOK smoothing

).

-

Enables increased DN current pulses to improve linearization of CP/PFD (see

Table 34. Commands

).

-

-

1 → VCO amplitude calibration will be skipped

(external amplitude word forced on VCO).

1 → VCO frequency calibration will be skipped

(external amplitude word forced on VCO).

-

DS13100 - Rev 1 page 49/64

Name

VCO_CALIBR_IN2

VCO_CALIBR_IN1

VCO_CALIBR_IN0

XO_RCO_CONF1

XO_RCO_CONF0

RCO_CALIBR_CONF3

RCO_CALIBR_CONF2

PM_CONF4

6D

6E

6F

75

Addr

69

6A

6B

6C

Default

88

40

40

45

30

70

4D

17

Bit

7:0

7:0

7:0

7:5

4

3:0

7

5:4

3

2

1

0

7:4

3:0

7

6:0

7:6

5

4:0

7

PM_CONF3 76 20

PM_CONF2 77 00

6:0

7:0

S2-LPTX

Register contents

Field name

RESERVED

RESERVED

RESERVED

RESERVED

PD_CLKDIV

RESERVED

EXT_REF

GM_CONF

REFDIV

RESERVED

EXT_RCO_OSC

RCO_CALIBRATION

RWT_IN

RFB_IN[4:1]

RFB_IN[0]

RESERVED

RESERVED

EXT_SMPS

RESERVED

KRM_EN

KRM[14:8]

KRM[7:0]

Description

-

-

-

-

1: disable divider of digital clock (and reference clock for the SMPS).

•

•

-

0: reference signal from

XO circuit

1: reference signal from

XIN pin.

Set the driver gm of the XO at start up.

1: enable the the reference clock divider.

-

1: the 34.7 kHz signal must be supplied from any GPIO.

1: enable the automatic RCO calibration.

RWT word value for the RCO.

MSB part of RFB word value for RCO.

LSB part of RFB word value for RCO.

-

-

1: disable the internal SMPS.

-

•

•

0: divider by 4 enabled

(SMPS' switching frequency is

FSW=Fdig/4)

1: rate multiplier enabled (SMPS' switching frequency is

FSW=KRM*Fdig/(2^15).

Sets the divider ratio (MSB) of the rate multiplier (default:

Fsw=Fdig/4)

Sets the divider ratio (LSB) of the rate multiplier (default:

Fsw=Fdig/4)

DS13100 - Rev 1 page 50/64

Name

PM_CONF1

PM_CONF0

MC_STATE1

MC_STATE0

TX_FIFO_STATUS

RCO_CALIBR_OUT4

RCO_CALIBR_OUT3

8E

8F

94

95

Addr Default

78 39

5:4

3

2

1:0

7

Bit

7

6

79

8D

42

52

07

00

70

00

6:4

3:1

0

7:4

3:0

7

6:0

7:5

4

1

0

3

2

7:1

0

7:0

S2-LPTX

Register contents

Field name

RESERVED

BATTERY_LVL_EN

SET_BLD_TH

Reserved

BYPASS_LDO

RESERVED

RESERVED

SET_SMPS_LVL

RESERVED

SLEEP_MODE_SEL

RESERVED

RCO_CAL_OK

ANT_SEL

TX_FIFO_FULL

Reserved

ERROR_LOCK

STATE

XO_ON

NELEM_TXFIFO

RWT_OUT

RFB_OUT[4:1]

RFB_OUT[0]

RESERVED

•

•

•

•

Description

-

1: enable battery level detector circuit.

Set the BLD threshold:

00b: 2.7 V

01b: 2.5 V

10b: 2.3 V

11b: 2.1 V.

-

Set to 0 (default value)

-

-

•

•

•

•

•

•

•

•

•

•

SMPS output voltage:

000b: not used

001b: 1.2 V

010b: 1.3 V

011b: 1.4 V

100b: 1.5 V

101b: 1.6 V

110b: 1.7 V

111b: 1.8 V

-

0: SLEEP without FIFO retention (SLEEP A)

1: SLEEP with FIFO retention (SLEEP B).

-

RCO calibration successfully terminated.

Currently selected antenna.

1: TX FIFO is full.

1: RCO calibrator error.

Current state.

1: XO is operating.

Number of elements in TX

FIFO.

RWT word from internal RCO calibrator.

RFB word (MSB) from internal RCO calibrator.

RF word (LSB) from internal

RCO calibrator.

-

DS13100 - Rev 1 page 51/64

S2-LPTX

Register contents

Name

VCO_CALIBR_OUT1

Addr

99

Default

00

VCO_CALIBROUT0

TX_PCKT_INFO

DEVICE_INFO1

DEVICE_INFO0

IRQ_STATUS3

IRQ_STATUS2

IRQ_STATUS1

IRQ_STATUS0

9A

9C

F0

F1

FA

FB

FC

FD

00

00

03

C1

00

09

05

00

6:0

7:6

5:4

3:0

7:0

7:0

7:0

7:0

7:0

7:0

Bit

7:4

3:0

7

Field name

RESERVED

VCO_CAL_AMP_OUT

RESERVED

VCO_CAL_FREQ_OUT

RESERVED

TX_SEQ_NUM

RESERVED

PARTNUM

VERSION

INT_LEVEL[31:24]

INT_LEVEL[23:16]

INT_LEVEL[15:8]

INT_LEVEL[7:0]

Description

-

VCO magnitude calibration output word (binary coding internally converted from thermometric coding).

-

VCO Cbank frequency calibration output word

(binary coding internally converted from thermometric coding).

-

Current TX packet sequence number.

-

S2-LPTX part number

S2-LPTX version number

Interrupt status register 3

Interrupt status register 2

Interrupt status register 1

Interrupt status register 0

DS13100 - Rev 1 page 52/64

9

9.1

S2-LPTX

Package information

Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com

. ECOPACK is an ST trademark.

QFN24L (4x4 mm) package information

Figure 18. QFN24L (4x4 mm) package outline

DS13100 - Rev 1 page 53/64

9.2

S2-LPTX

PCB pad pattern

Dim.

D2

E

E2 e

L ddd

A

A1

A2

A3 b

D

Table 47. QFN24L (4x4 mm) package mechanical data

Min.

0.80

0.18

3.85

2.60

3.85

2.60

0.35

0.65

0.20

0.25

4.00

mm

Typ.

0.90

0.02

2.70

4.00

2.70

0.50

0.40

0.30

4.15

2.80

4.15

2.80

Max.

1.00

0.05

1.00

0.45

0.08

PCB pad pattern

•

•

•

In order to design a proper pad pattern, tolerance analysis is required on package and motherboard dimensions.

The tolerance analysis requires consideration of component tolerances, PCB tolerances and the accuracy of the equipment used to place the component.

For the pad dimensioning three different minimum values have been considered:

Minimum toe fillet = JTmin = 0.1 mm

Minimum heel fillet = JHmin = 0.05 mm

Minimum side fillet = JSmin = 0 mm

The PCB thermal pad should at least match the exposed die paddle size. The solder mask opening should be 120 to 150 microns larger than the pad size resulting in 60 to 75 microns clearance between the copper pas and solder mask.

DS13100 - Rev 1 page 54/64

S2-LPTX

QFN recommended profile parameters

Figure 19. QFN24 4x4x1pitch 0.5 mm PCB pad pattern

9.3

QFN recommended profile parameters

The temperature profile is the most important control in the re-flow soldering and it must be fine tuned to establish a robust process. QFN recommended soldering profile for lead-free mounting is shown in the following table and picture.

Figure 20. QFN recommended soldering profiles

270

220

[ °

170

120

70

20

0 30

2.0 ± 0.1 °C/s

(RSS)

60

0.9 ± 0.1 ° C/s

(RtS)

90

2.0 ±1.0 °C/s

120 150

Time [s]

180

240 ± 5 °C

60 ± 15 s

210 240

3.0 ± 2.0 °C/s

270 300

DS13100 - Rev 1 page 55/64

S2-LPTX

QFN recommended profile parameters

Profile

Temperature gradient in preheat

Soak/dwell ( refer to solder paste supplier recommendation)

Temperature gradient in preheat

Peak temperature

Duration above 220 °C

Temperature gradient in cooling

Time from 50 to 220 °C

Table 48. Temperature profiles

Ramp-to-spike

T from 70 °C to 150 °C 0.8 °C/s to 1.0 °C/s

Ramp-soak-spike

T from 70 °C to 150 °C 1 °C/s to 3

°C/s

N/A or temp.: 150 °C to 200 °C, 40 to 80 s Soak 150 °C to 200 °C, 40 to 100 s

Temp.: 200 °C to 225 °C, 1 °C/s to 3 °C/s

235 °C to 245 °C

45 to 75 s

Temp.: 200 °C to 225 °C, 1 °C/s to 3

°C/s

-1 °C to -5 °C

150 to 230 s

DS13100 - Rev 1 page 56/64

S2-LPTX

Ordering information

10

Ordering information

Order code

S2-LPTXQTR

Table 49. Ordering information

Package

QFN24 4x4x1

Packing

Tape and reel

DS13100 - Rev 1 page 57/64

Revision history

Date

19-Sep-2019

Table 50. Document revision history

Version

1 Initial release.

Changes

S2-LPTX

DS13100 - Rev 1 page 58/64

S2-LPTX

Contents

Contents

1 Detailed functional description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

2 Typical application diagram and pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

2.1

Pin diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

3.1

Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.2

Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.3

Thermal properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.4

Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.5

General characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.6

Frequency synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.7

Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.8

RF transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.8.1

3.8.2

3.8.3

Harmonic emission at 433 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Harmonic emission at 840-868 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Harmonic emission at 915 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.9

Digital interface specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.10

Battery indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4 Block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

4.1

Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.2

Power-On-Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.3

RF synthesizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.3.1

RF channel frequency settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.4

Digital modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.4.1

4.4.2

4.4.3

4.4.4

4.4.5

Frequency modulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Amplitude modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Direct polar mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

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Contents

4.4.6

4.4.7

4.4.8

4.4.9

Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Integrated RCO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Low battery indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.5

Operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.5.1

4.5.2

4.5.3

Command list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

State transaction response time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Sleep states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5 Packet handler engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

5.1

BASIC packet format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.2

802.15.4g packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.3

UART over the air packet format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.4

Wireless MBUS packet (W-MBUS, EN13757-4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.5

Payload transmission order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.6

Data coding and integrity check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.6.1

5.6.2

5.6.3

FEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Manchester coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3-out-of-6 coding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.7

CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.8

Data whitening. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6 Link layer protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

6.1

Timeout protocol engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.1.1

Low duty cycle mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7 MCU interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

7.1

Serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.2

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.3

GPIOs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

8 Register contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

9 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

9.1

QFN24L (4x4 mm) package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

9.2

PCB pad pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

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Contents

9.3

QFN recommended profile parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

10 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

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List of tables

List of tables

Table 1. Description of the external components of the typical application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 2. Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 4. Operating range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 5. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 6. Low-power state power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 7. Power consumption fc= 915 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 8. Power consumption fc= 840-868 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 9. Power consumption fc= 434 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 10. General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 11. Data rate with different coding options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 12. Frequency synthesizer parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 13. Crystal oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 14. Ultra-low power RC oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 15. RF transmitter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 16. PA impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 17. Regulatory standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 18. Harmonic emission at 433 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 19. Harmonic emission at 840-868 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 20. Harmonic emission at 915 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 21. Digital SPI input, output and GPIO specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 22. Battery indicator and low battery detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 23. SMPS output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 24. POR parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 25. Charge pump words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 26. Resolution frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 27. Channel spacing resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 28. Modulation scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 29. Constellation mapping 2-(G)FSK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 30. Constellation mapping 4-(G)FSK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 31. PA Bessel filter words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 32. RCO Frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 33. States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 34. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 35. Response time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 36. BASIC packet format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 37. Preamble field selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 38. 802.15.4g packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 39. PHR frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 40. UART over the air packet format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 41. 3-out-of-6 coding scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 42. Timer description and duration (the values are related to f dig

of 26 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 43. Interrupts list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 44. GPIO digital output functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 45. GPIO digital input functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 46. Register contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 47. QFN24L (4x4 mm) package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 48. Temperature profiles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 49. Ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 50. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

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List of figures

List of figures

Figure 1. Simplified S2-LPTX block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Figure 2. Suggested application diagram (embedded SMPS used) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. Suggested application diagram (embedded SMPS not used) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 4. Suggested application diagram HPM/LPM (integrated balun, embedded SMPS used) . . . . . . . . . . . . . . . . . . . 6

Figure 5. Pin diagram, QFN24 (4x4 mm) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 6. Power-On-Reset timing and limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 7. Start-up phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 8. Examples of possible connections for SDN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 9. Direct polar mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 10. Output power ramping configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 11. Threshold in FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 12. State diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 13. Data whitening scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 14. Data whitening scheme 802.15.4g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 15. SPI write sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 16. SPI read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 17. SPI command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 18. QFN24L (4x4 mm) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 19. QFN24 4x4x1pitch 0.5 mm PCB pad pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 20. QFN recommended soldering profiles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

DS13100 - Rev 1 page 63/64

S2-LPTX

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DS13100 - Rev 1 page 64/64