STMicroelectronics Ultra-low power, high performance, sub-1 GHz transceiver Datasheet

-40

Thermal properties

Table 5. Thermal data

Parameter

Thermal resistance junction-ambient

Typ.

3.0

Max.

3.6

+85

QFN24

Unit

°C/W

Power consumption

Characteristics measured over recommended operating conditions unless otherwise specified. Typical values are referred to 25 °C temperature, V

BAT

= 3.3 V. All performance is referred to the STEVAL-FKI433V2 or

STEVAL-FKI868V2 with a 50 Ohm antenna connector.

Unit

°C

DS13831 - Rev 1 page 10/73

DS13831 - Rev 1

S2-LPS

Power consumption

Parameter

Supply current

Table 6. Low-power state power consumption

Test conditions

Shutdown

Standby

Sleep

Sleep (FIFOs retained)

Ready

Min.

Typ.

2.5

500

700

0.95

350

Max.

Unit nA

µA

Table 7. Power consumption in reception T

= 25 °C, VDD = 3.3 V, f c

= 868 MHz

Parameter

Supply current

Test conditions

RX @ sensitivity level

Min.

HPM typ.

8.6

LPM typ.

7.2

Max.

Unit mA

Table 8. Power consumption in transmission f c

= 915 MHz

Parameter

Supply current

Test conditions

TX CW @ 14 dBm

TX CW @ 10 dBm

TX CW @ 16 dBm in Boost

1. SMPS output voltage 1.2 V, LDOs disable.

2. SMPS output voltage 1.8 V.

Min.

Typ.

12.5

Max.

Table 9. Power consumption in transmission f c

= 840-868 MHz

Parameter

Supply current

Test conditions

TX CW @ 14 dBm

TX CW @ 10 dBm

TX CW @ 16 dBm in Boost

1. SMPS output voltage 1.2 V, LDOs disable.

2. SMPS output voltage 1.8 V.

Min.

Typ.

11.5

Max.

Table 10. Power consumption in transmission f c

= 434 MHz

Parameter

Supply current

1. SMPS output voltage 1.6 V.

2. SMPS output voltage 1.2 V, LDOs disable.

Test conditions

TX CW @ 14 dBm

TX CW @ 10 dBm

Min.

Typ.

11.5

Parameter

Supply current

Table 11. Power consumption in transmission f c

= 510 MHz

Test conditions

TX CW @ 14 dBm

TX CW @ 10 dBm

TX CW @ 15 dBm

Min.

Typ.

Max.

Unit mA

page 11/73

3.5

3.6

3.7

S2-LPS

General characterization

1. SMPS output voltage 1.2 V, LDOs disable.

2. SMPS output voltage 1.8 V.

General characterization

Parameter

Table 12. General characteristics

Frequency range

Data rate DR

Data rate accuracy

Frequency deviation FDEV

2-(G)FSK

OOK/ASK

Typ.

413 - 479

826 - 958

0.1 - 250

0.1 -125

±100

0.15 - 500

Unit

MHz kbps ppm kHz

Frequency synthesizer

Parameter

Frequency step size

Table 13. Frequency synthesizer parameters

RF carrier phase noise 433 MHz

RF carrier phase noise 868 MHz

Test conditions

Out-loop divider ratio = 4

10 kHz

100 kHz

1 MHz

10 MHz

10 kHz

100 kHz

1 MHz

10 MHz

50 MHz

23.8

-109

-110

-124

-141

-102

-103

-117

-138

Unit

Hz dBc/Hz

Crystal oscillator

Characteristics measured over recommended operating conditions unless otherwise specified. All typical values are referred to 25 °C temperature, V

BAT

= 3.0 V.

The device supports crystals 26 MHz.

From now on in this document the XTAL oscillator will be indicated with f

and the digital clock with f dig

• if a 26 MHz crystal is used, this bit must be 1 (digital divider disabled): fdig = fxo

In order to avoid potential RF performance degradations, the crystal frequency should be chosen to satisfy the following equation: nFCH − ROUND n

FCH fXO fXO ≥ 1MHz where n is an integer in the set [1-7, B] (B is the synthesizer’s divider ratio).

(1)

(2)

DS13831 - Rev 1 page 12/73

3.8

S2-LPS

RF receiver

Table 14. Crystal oscillator characteristics

Parameter

Crystal frequency

Test conditions Min. Typ. Max.

Unit

24 26 MHz

Frequency tolerance

, as shown in Figure 6. Power-On-Reset timing and limits . The same reset pulse is generated after a step-down on the input pin SDN (VDD>V

10 kHz -

± 40 -

-135 ppm

Minimum requirement on external reference phase noise mask fXO = 26 MHz , to avoid degradation on synthesizer phase/noise

100 kHz

1 MHz

10 MHz

-140

-140 dBc/Hz

Programmable trans-conductance of the oscillator at start-up 43 mS

Start-up time (2)

VBAT=1.8 V, fXO = 26 MHz

100 µs

1. Including initial tolerance, crystal loading, aging, and temperature dependence. The acceptable crystal tolerance depends on RF frequency and channel spacing/bandwidth.

2. Start-up times are crystal dependent. The crystal oscillator trans-conductance can be tuned to compensate the variation of crystal oscillator series resistance.

Table 15. Ultra-low power RC oscillator

Parameter

Calibrated frequency

Frequency accuracy after calibration

Test conditions

Calibrated RC oscillator frequency is derived from crystal oscillator frequency.

1. Depending on the crystal frequency, the reported value is referring to 50 MHz.

Typ.

Unit

33.3 (1)

kHz

±1 %

RF receiver

Characteristics measured over recommended operating conditions unless otherwise specified. All typical values are referred to 25 °C temperature, V

BAT

= 3.3 V, no frequency offset in the RX signal. The whole performance is referred to the STEVAL-FKI433V2, STEVAL-FKI512V1 or STEVAL-FKI868V2 with a 50 Ohm antenna connector.

Table 16. RF receiver characteristics

Parameter Test conditions

Receiver channel bandwidth

CHF

RX input return loss

Saturation 1% BER

Input third order intercept point

RX noise figure

Differential input impedance at

LNA

Max. RX gain, tied (RX + TX) matching networks

2-FSK 1.2 kHz FDEV, DR = 1.2 kbps, CHF = 4 kHz

433 MHz

868 MHz

433 MHz

868 MHz

Interferers are continuous wave @ 6 MHz and 12 MHz offset from carrier

433 MHz

868 MHz

Max. RX gain, tied (RX + TX) matching networks

Max. RX gain

R // C

433 MHz

868 MHz

433 MHz

868 MHz

HPM/LPMSMPS on typ.

1-800

Unit kHz

-15

-25

200 // 1.5

dB dBm dB

Ω//pF

DS13831 - Rev 1 page 13/73

3.8.1

3.8.2

3.8.3

S2-LPS

RF receiver

Blocking and selectivity at 433 MHz

Table 17. Blocking and selectivity at 433 MHz

Parameter Test condition

Selectivity and blocking 1%

BER @ 2-GFSK BT=0.5 20 kHz FDEV, DR = 38.4 kbps, CHF = 100 kHz

+100 kHz (adjacent channel)

-100 kHz (adjacent channel)

+200 kHz (alternate channel)

-200 kHz (alternate channel)

Image rejection

±2 MHz

±10 MHz

HPM

SMPS on

(typ.)

LPM

SMPS ON typ.

Unit

50 37

72 dB

Sensitivity at 433 MHz

Parameter

Sensitivity

1% BER @ 2-GFSK BT = 0.5

Sensitivity

1% BER @ OOK

Table 18. Sensitivity at 433 MHz

Test conditions

DR = 38.4 kbps, FDEV = 20 kHz, CHF = 100 kHz

DR = 0.3 kbps, CHF = 1 kHz

DR = 1.2 kbps, CHF = 4 kHz

DR = 38.4 kbps, CHF = 100 kHz

HPM/LPM SMPS on (typ.) Unit dBm -109

-120

-118

-104 dBm

Blocking and selectivity at 840-868 MHz

Table 19. Blocking and selectivity @ 840-868 MHz

Parameter

Selectivity and blocking 1% BER @ 2-GFSK BT = 0.5, 20 kHz FDEV,

DR = 38.4 kbps, CHF = 100 kHz

Test conditions

+100 kHz (adjacent channel)

-100 kHz (adjacent channel)

+200 kHz (alternate channel)

-200 kHz (alternate channel)

Image rejection

± 2 MHz

± 10 MHz

HPM

SMPS on

(typ.)

LPM

SMPS on

(typ.)

Unit

44 33

73 dB

DS13831 - Rev 1 page 14/73

3.8.4

3.9

S2-LPS

RF transmitter

Sensitivity at 840-868 MHz

Parameter

Sensitivity

1% BER @ 2-GFSK BT = 0.5

Sensitivity

1% BER @ OOK

Table 20. Sensitivity at 840-868 MHz

Test conditions

DR = 38.4 kbps, FDEV = 20 kHz, CHF = 100 kHz

DR = 0.3 kbps, CHF = 1 kHz

DR = 1.2 kbps, CHF = 4 kHz

DR = 38.4 kbps, CHF = 100 kHz

HPM/LPM/SMPS on typ.

Unit

-109 dBm

-120

-118

-104 dBm

RF transmitter

Characteristics measured over recommended operating conditions unless otherwise specified. All typical values are referred to 25 °C temperature, V

BAT

= 3.3 V. All performance is referred to the STEVAL-FKI433V2 or

STEVAL-FKI868V2 with a 50 Ω antenna connector.

Parameter

Maximum output power

Maximum output power in boost mode

Minimum output power

Output power step

Output power step (1)

1. In this case the register 0x64 is set to 0x4A.

Table 21. RF transmitter characteristics

Test conditions

CW @ antenna level

-10<=output power<=+10 dBm

Output power>+10 dBm

HPM typ.

-30

0.5

1 (1)

LPM typ.

Unit

-30

0.5

dBm dB

Parameter

Optimum load impedance

Table 22. PA impedance

Max permitted VSWR @ antenna level

Test conditions

433 MHz

868 MHz

433 MHz

868 MHz

Typ.

56+25j

30+24j

Unit

Ω

Frequency band

413 - 479 MHz

826 - 958 MHz

Table 23. Regulatory standards

Suitable for compliance with:

ETSI EN300 220 category 1.5

FCC part 15, FCC part 90

ETSI EN300 220-2 category 1.5

FCC part 15

ARIB STD-T108

Chinese SRRC

DS13831 - Rev 1 page 15/73

3.9.1

3.9.2

3.10

S2-LPS

Digital interface specification

Harmonic emission at 433 MHz

Parameter

Harmonic emission at 840-868 MHz

Table 24. Harmonic emission at 433 MHz

Test conditions

SMPS on

-51

-56

-39

-34

-46

-44

Parameter

Table 25. Harmonic emission at 840-868 MHz

Test conditions

HPM/LPM/SMPS on

-38

-54

-52

-43

-51

Unit dBm

Digital interface specification

Parameter

SPI clock frequency

Port I/O capacitance

Table 26. Digital SPI input, output and GPIO specification

Test conditions Min.

Rise time

Fall time

From 0.1*VDD to 0.9*VDD, CL=20 pF (low output current programming)

From 0.1*VDD to 0.9*VDD, CL=20 pF (high output current programming)

From 0.1*VDD to 0.9*VDD, CL=20 pF (low output current programming)

From 0.1*VDD to 0.9*VDD, CL=20 pF (high output current programming)

Logic high level input voltage

VDD/2

+0.3

Logic low level input voltage

High level output voltage

IOH = -2.4 mA (-4.2 mA into high output current mode).

(5/8)*

Typ.

Max.

Unit

1.4

10 MHz pF

6.0

2.5

7.0

2.5

VDD/8

+0.3

DS13831 - Rev 1 page 16/73

3.11

Note:

S2-LPS

Battery indicator

Parameter Test conditions

Low level output voltage

CSn low to positive edge on SCLK in low power mode state

CSn low to positive edge on SCLK in ready state

IOL = +2.0 mA (+4.0 mA into high output current mode).

Min.

VDD+

0.1

Typ.

Max.

Unit

0.5

40 µs

30 ns

Battery indicator

Characteristics measured over recommended operating conditions unless otherwise specified. All typical values are referred to 25 °C temperature, V

BAT

= 3.0 V.

Parameter

Battery level thresholds #1

Battery level thresholds #2

Battery level thresholds #3

Battery level thresholds #4

Brownout threshold

Brownout threshold hysteresis

Table 27. Battery indicator and low battery detector

Test conditions

Measured in slow battery variation (static) conditions (inaccurate mode)

Measured in slow battery variation (static) conditions (accurate mode)

Min. Typ. Max. Unit

2.1

2.3

2.5

2.7

1.5

1.7

70 mV

For battery-powered equipment, the TX does not transmit at a wrong frequency under low battery voltage conditions. It remains on either channel or stops transmitting. The latter can of course be realized by using a lock detect and/or by switching off the PA under control of the battery monitor. For testing reasons this control is enabled/disabled by SPI.

DS13831 - Rev 1 page 17/73

S2-LPS

Block description

Block description

4.1

Power management

The S2-LPS integrates a high efficiency step-down converter cascaded with LDOs meant to supply both analog and digital parts. However, an LDO directly fed by the external battery provides a controlled voltage to the data interface block.

S2-LPS’s power management (PM) strategy, besides the basic functionality of providing different blocks with proper supplies, faces two main constraints: the first one is to implement such a power distribution with maximum efficiency, and the second one is to guarantee the isolation among critical blocks.

The efficiency target is obtained by using a switch mode power supply (SMPS) which converts the battery voltage

(1.8 V - 3.6 V) to a lower voltage (settable from 1.2 V to 1.8 V) with efficiency higher than 90%.

The SMPS output voltage can be controlled by the SET_SMPS_LVL field in the PM_CONF0 register. The relation between the SET_SMPS_LVL and the V

OUT

of the SMPS is given by the following table:

SET_SMPS_LVL

001b

010b

011b

100b

101b

110b

111b

Table 28. SMPS output voltage

SMPS output voltage

1.2 V

1.3 V

1.4 V

1.5 V

1.6 V

1.7 V

1.8 V

The SMPS output voltage can be controlled in TX only or for both RX and TX according to the SMPS_LVL_MODE bit of the PM_CONF1 register.

• 1: SMPS output level depends upon the value in PM_CONFIG register just in TX state, while in RX state it is fixed to 1.4 V.

• 0: SMPS output level depends upon the value written in the PM_CONFIG0 register (SET_SMPS_LEVEL field) both in RX and TX state.

The SMPS switching frequency is settable by the 2 registers PM_CONF3 and PM_CONF2.

If the KRM_EN is 0, then the digital divider by 4 enabled. In this case SMPS' switching frequency is:

Fsw = fdig

If the KRM_EN is 1, the SMPS' switching frequency can be set by the KRM word according to the formula:

(3)

Fsw = Krm fdig

215

As f dig

is the digital domain frequency ( f

if it is 26 MHz).

All the RX measurements reported in this datasheet have been taken with a SMPS frequency set to 1.56 MHz.

From the formula reported with fdig = 25 MHz, PM_CONF3 = 0x87, PM_CONF2 = 0xFC, the F sw

is 1.56. It is possible to have a little improvement of the sensitivity reducing the SMPS switching frequency but having as drawback a higher current consumption.

The isolation target is reached by using, for each critical block, a dedicated linear low-dropout regulator (LDO), which provides typically 1.2 V output voltage, either from battery level or from SMPS level, depending from the operating mode.

If the output of the LDO is 1.2 V the minimum value of the SMPS, V out

must be at least 100 mV higher than the

V out

of the LDO. This means that in HPM (SMPS+LDO) the minimum value of the SMPS_VOUT must be 1.3 V.

(4)

DS13831 - Rev 1 page 18/73

4.2

S2-LPS

Power-On-Reset

The S2-LPS PM can be configured by SPI (BYPASS_LDO field in PM_CONFIG [1] register) in two main modes:

High performance mode (HPM)

Low power mode (LPM)

In HPM all available LDOs supplied from SMPS are used, to get the best possible isolation and minimum low-frequency noise level and SMPS ripple. SMPS must be set to 1.4 V at least.

In LPM the LDOs connected to the SMPS are by-passed and SMPS must be configured to provide 1.2 V output level to increase the regulation efficiency but with reduced isolation and higher low-frequency noise and SMPS ripple.

•

The load inductor of the SMPS has to have the following characteristics:

• A typical 10 µH nominal value +/-10%

A rated current of 100 mA minimum

A DC resistance as low as possible (to guarantee maximum efficiency of the SMPS block), around 1 Ohm is a typically good value, but the lower the better

Power-On-Reset

The Power-On-Reset (POR) circuit generates a reset pulse upon power-up which is used to initialize the entire digital logic. Power-on-reset senses V

BAT

voltage.

The S2-LPS provides an automatic POR circuit, which generates an internal RESETN (active low) level for a time

RESET

, after the V

BAT

reaches the reset release voltage threshold V

RRT

RRT

). This signal is available on the GPIO0 pin.

Figure 6. Power-On-Reset timing and limits

DS13831 - Rev 1

The parameters VRRT and TRESET are fixed by design in order to guarantee a reliable reset procedure of the state machine. In addition, all the registers are initialized to their default values.

A software command SRES is also available, it generates an internal but partial resetting of the S2-LPS.

Parameter

Reset start-up threshold voltage

Hold pulse width (T hold

, figure below)

Table 29. POR parameters

Comment

For SDN to be effective

Min.

Typ.

0.5

Max.

Unit

µs page 19/73

S2-LPS

RF synthesizer

Parameter

Reset pulse width (T reset

, figure below)

Power-on VDD slope

Comment Min.

Typ.

0.7

2.0

Max.

Unit ms

V/ms

The following picture shows how the S2-LPS must be controlled, i.e. the SDN signal must be tied to VBAT pin in order to avoid two potential issues during the start-up phase:

A cross conduction can appear on the GPIO until an available command is present on it.

The ESD protection diode from the SDN pad can sink current from the external driver connected to the SDN.

Also the SDN signal generates an internal signal (POC), which disables the digital I/Os when set to 1.

Figure 7. Start-up phase

Examples of possible connections

Figure 8. Examples of possible connections for SDN pin

4.3

RF synthesizer

A crystal connected to XIN and XOUT provides a clock signal to the frequency synthesizer. The allowed clock signal frequency is 26 MHz.

As an alternative, an external clock signal feeds XIN for proper operation. In this option, XOUT can be left either floating or tied to ground.

DS13831 - Rev 1 page 20/73

4.3.1

S2-LPS

RF synthesizer

The integrated phase locked loop (PLL) is capable to synthesize a band of frequencies from 413 to 479 MHz, 826 to 958 MHz, providing the LO signal for the RX chain and the input signal for the PA in the TX chain.

Depending on the RF frequency and channel used, a very high accurate crystal or TCXO can be required.

The RF synthesizer implements fractional sigma delta architecture to allow fast settling and narrow channel spacing. It is fully integrated, and it uses a multi-band VCO to cover the whole frequency range. All internal calibrations are automatic.

According to the frequency synthesized the user must set the charge pump current according to the LO frequency variations, in order to have a constant loop bandwidth. The charge pump current is controlled by the PLL_CP_ISEL field (SYNT3 register) and the PLL_PFD_SPLIT_EN (SYNTH_CONFIG2). These fields should be set in the following way:

VCO Freq (MHz)

3760

3460 fxo (MHz)

Table 30. Charge pump words

PLL_CP_ISEL

001

010

PLL_PFD_SPLIT_EN

ICP (μA)

200

240

The S2-LPS provides an automatic and very fast calibration procedure for the frequency synthesizer. If not disabled, it performs the calibration each time the synthesizer is required to lock to the programmed RF channel frequency (transaction from READY to LOCK/TX/RX or from RX to TX and vice versa). After completion, the

S2-LPS uses the calibration word and is stored in registers.

In order to get the synthesizer locked with the calibration procedure disabled, the correct calibration words must be previously stored in registers by user for TX and RX respectively. The advantage is reduce the LOCK setting time.

The transition time enables the S2-LPS for frequency hopping operation due to its reduced response time and very quick programming synthesizer.

RF channel frequency settings

The channel center frequency can be programmed as follows:

Center frequency setting fc = fbase + fxo

215

∙ CHSPACE ∙ CHNUM

The f base

sets the main channel frequency; the value depends on the value of f xo

(the frequency of the XTAL oscillator, typically 26 MHz.

Base frequency setting fbase = fxo

2 ∙ D where:

SYNT is a programmable 28-bits integer (SYNT[3:0] registers).

B is the out-of-loop SYNTH divider (BS field of the SYNT3 register):

PLL divider

(5)

(6)

(7)

B =

4 for tℎe ℎigℎ band 826 MHz to 1055 MHz, BS = 0

8 for tℎe middle band 413 MHz to 527 MHz, BS = 1

D is the reference divider (REFDIV bit of XO_RCO_CONFIG0 register)

Reference divider

D =

1 if REFDIV = 0 internal reference divider is disabled

2 if REFDIV = 1 internal reference divider is enabled

The resolution in the programmed value of the base frequency depends on the actual band selected.

(8)

DS13831 - Rev 1 page 21/73

4.4

4.4.1

S2-LPS

Digital modulator fxo [MHz]

Table 31. Resolution frequency

High band resolution [Hz]

12.4

Low band resolution [Hz]

6.2

The f c

is the frequency related to the channel specified. RF channels can be defined using the CHSPACE and

CHNUM registers. In this way, it is possible to change faster the channel by changing just an 8-bits register, allowing the setting of 256 channels and frequency-hopping sequences. The actual channel spacing is from 793

Hz to 202342 Hz in 793 Hz steps for the 26 MHz configuration and from 1587 to 404685 Hz in 1587 Hz steps for the 52 MHz configuration.

fxo [MHz]

Table 32. Channel spacing resolution

Channel spacing resolution [Hz]

793.45

Digital modulator

The S2-LPS supports frequency modulation: 2-FSK, 4-FSK, 2-GFSK, 4-GFSK as well amplitude modulation OOK and ASK. Using register, the user can also program an unmodulated carrier for lab test and measurement.

A special mode, direct polar modulation, allows building specific modulation scheme controlling directly the amplitude and the frequency of the carrier synthesized. The register MOD_TYPE is used to select one of the following modulation scheme.

MOD_TYPE

0000b

0001b

0010b

0011b

0101b

0110b

0111b

Table 33. Modulation scheme

Modulation scheme

2-FSK

4-FSK

2-GFSK

4-GFSK

ASK/OOK

Direct polar (TX only)

Frequency modulation

For frequency modulation 2-(G)FSK and 4-(G)FSK the frequency deviation can be tuned in wide range that depends on f xo

(XTAL frequency) according the following formula:

Frequency deviation fXO

219

· round D · FDEV_M · B 8

D · B

if FDEV_E = 0 fdev = fXO

219

· round D · 256 + FDEV_M · 2 FDEV_E − 1 · B 8

D · B

if FDEV_E > 0

Where f xo

is the XTAL oscillation frequency, D is the reference divider and B is the band selector.

(9)

The frequency deviation programmed corresponds to the deviation of the outer constellation symbols. The deviation of the inner symbols is 1/3 of such programmed values, as reported in the table below, where 4 options are available.

Furthermore, since the payload is normally arranged in bytes, the arrangement can change the mapping for both

2-(G)FSK and 4-(G)FSK modulations, by using the CONST_MAP (register MOD1), in the following way:

DS13831 - Rev 1 page 22/73

S2-LPS

Digital modulator

4.4.1.1

Note:

4.4.1.2

4.4.2

Format

2-(G)FSK

Table 34. Constellation mapping 2-(G)FSK

Symbol

-FDEV

+FDEV

CONST_MAP coding

1 2

+FDEV

-FDEV

Format

4-(G)FSK

Symbol

Table 35. Constellation mapping 4-(G)FSK

-FDEV/3

-FDEV

+FDEV/3

+FDEV

CONST_MAP coding

1 2

-FDEV

-FDEV/3

+FDEV

+FDEV/3

+FDEV

-FDEV/3

-FDEV

+FDEV

+FDEV/3

-FDEV

-FDEV/3

Furthermore, in the 4-(G)FSK it is also possible to swap the symbols using the 4FSK_SYM_SWAP field (register

PCKTCTRL3) as follows:

(10)

When 4FSK_SYM_SWAP = 0:

When 4FSK_SYM_SWAP = 1

S0 = < b7b6 >

S1 = < b5b4 >

S2 = < b3b2 >

S3 = < b1b0 >

S0 = < b6b7 >

S1 = < b4b5 >

S2 = < b2b3 >

S3 = < b0b1 >

Gaussian shaping

In 2-GFSK or 4-GFSK mode, the Gaussian filter BT product can be set by using the register BT_SEL to 1 or 0.5.

The Gaussian filtering is implemented by poly-phase filtering with eight taps per symbol time. In order to further smooth the filter shape and improve spectral shaping, the output of the filter can be linearly interpolated by setting the register MOD_INTERP_EN.

A mathematical interpolation factor is applied at each sample of the Gaussian filter output. This factor is 64 for data rates corresponding to DATA_RATE_E < 5, it is automatically scaled as

2DATA_RATE_E − 5

for 5 ≤

DATA_RATE_E < 11 and it is automatically disabled for DATA_RATE_E = 11.

The actual interpolation factor achieved may be limited by the minimal frequency resolution of the frequency synthesizer.

ISI cancellation 4-(G)FSK

Since the 4-(G)FSK modulation format strongly suffers from the effect of inter symbol interference, an ISI cancellation equalizer has been introduced in the demodulator. An equalizer can be enabled, by using the

EQU_CTRL register, with two modes: single pass equalization and dual pass equalization. The best performance is normally achieved using the dual pass equalizer.

Amplitude modulation

Amplitude modulation OOK and ASK are both supported by the S2-LPS. The ASK selection depends on power ramping enable.

When OOK is selected, a bit '1' is transmitted with a programmed power, set by register

PA_POWER[PA_LEVEL_MAX_INDEX], and a bit '0' is transmitted without output power (PA off) and specified by the register PA_POWER[0].

DS13831 - Rev 1 page 23/73

S2-LPS

Digital modulator

4.4.2.1

Note:

4.4.3

In case PA_POWER[0] = 0 then the modulation will be OOK, otherwise when PA_POWER[0] is not set to zero the modulation will be ASK. The 0/1 mapping can be reversed by setting the CONST_MAP register to any value other than zero.

When ASK is selected, a bit '1' is transmitted with a power ramp increasing from the minimum value specified by register PA_POWER[0] to specified PA maximum level in register PA_POWER[PA_LEVEL_MAX_INDEX], vice versa for a bit '0'. The duration of each power step is a multiple of 1/8 of the symbol time, configurable with the register PA_RAMP_STEP_WIDTH. If more '1's are transmitted consecutively, the PA power maintains the output power at the programmed value. If more '0's are transmitted consecutively, the PA power remains at minimum power for all '0's following the first one.

In order to improve the spectral emission mask is ASK a digital interpolation optional features have been implemented. When this feature is enabled, thought the register PA_INTERP_EN, the modulator linearly interpolates the power values specified in the PA_POWER registers before being applied to the PA.

The interpolation factor of each ramp step is 64 time the data rate corresponding to DATA_RATE_E < 5 it is automatically scaled as 64/2 (DATA_RATE_E-5)

DATA_RATE_E=11.

for 5 ≤ DATA_RATE_E < 11 and it is automatically disabled for

Note that the number of clock cycles between successive PA ticks, for DATA_RATE_E≥5, is always between 8 and 4 (8 for DATA_RATE_M=0; 4 for DATA_RATE_M=65535).

OOK/ASK demodulation is controlled by the OOK_PEAK_DECAY parameter ( recommended value is 3) in the

RSSI_FLT register.

OOK smoothing

The OOK can be smoothed using a FIR filter added in the data path. This feature is activated by setting the

FIR_EN bit at 1 inside register PA_CONFIG1.

•

The FIR filter is not fully customizable but it can be set in 3 different configurations that change the spectrum shape (and thus the bandwidth): filter : it is the proper FIR filtering function of the stream of bits 8 times oversampled; ramp : the FIR filter is optimized to perform a ramping between PA_POWER_MAX and PA_POWER_0 (for

OOK should be set to 0).

• switch : logic 1s and 0s are associated with a single value of power and no transition between the 2 is envisaged.

When the FIR_EN bit is 1, the DIG_SMOOTH_EN (PA_POWER_0 register) must be set to 1.

Finally, a 2 nd order Bessel analog filter can be used to smooth the output signal. The bandwidth of this filter should be set according to the data rate used by setting the PA_FC field of the register PA_CONFIG0 according to the following table:

PA_FC bits

Table 36. PA Bessel filter words

Cut-off frequency (kHz)

12.5

100

Max. data rate (kbit/s)

62.5

125

The FIR ramping modes are used in a mutually exclusive way with the digital ramping. When the digital ramping is used, the FIR ramping should be disabled. Vice versa, if the FIR ramping is used, the digital one is not used.

Direct polar mode

The S2-LPS allows the user to drive the SYNTH and the PA at a very low level. The byte couples written in the

TX_FIFO are sampled with a rate related to the DATARATE chip setting (sampling rate = 8*DATARATE).

The first byte of the couple drives the frequency synthesizer to obtain an instantaneous output frequency deviation given by the formula below:

Frequency deviation in polar mode

(11)

DS13831 - Rev 1 page 24/73

S2-LPS

Digital modulator

Where fdev_programmed is the frequency deviation programmed in the chip by the registers MOD[1:0] (see

Section 4.4.1 Frequency modulation

), fdev_fifo_sample is the first byte of the bytes couple sampled from the

TX_FIFO.

The fdev_fifo_sample is interpreted as a 2-complement 8-bit number, thus it can be either a positive or a negative value.

The instantaneous frequency is given by the formula:

Instantaneous frequency in polar mode f = fc_programmed + fdev

The second byte of the TX_FIFO couple drives the PA giving an instantaneous output power.

(12)

The output power will be generated according to this value following the same code as the PA_POWER registers

(see

Section 4.4.6.1 PA configuration

Figure 9. Direct polar mode

shows how the byte couples are sampled from the TX FIFO and sent to the SYNTH and PA blocks.

Figure 9. Direct polar mode

4.4.4

4.4.4.1

4.4.4.2

4.4.4.3

As for the normal TX operations, the TX_FIFO samples are consumed and a management of the

TX_FIFO_THRESHOLD is needed to perform transmissions longer than 128 samples.

The transmission is never automatically stopped and a specific command SABORT should be given to terminate it.

Test modes

Continuous wave

The device can be programmed to generate a continuous wave carrier without any modulation. In this way, the carrier will be continuously transmitted until a SABORT command is sent to the device.

To set the continuous wave the MOD_TYPE field (of the MOD2 register) must be set to 0x77.

PN9

It is possible to set a pseudo random binary sequence 9 (PN9) as data source for the modulator. In this way, these data are continuously modulated until a SABORT command is sent to the device.

The TXSOURCE field (of the PCKTCTRL1 register) must be set to 0x03.

Data rate

The data rate programmable is from 0.1 kbps to 500 kbps (see Table 12. General characteristics ) for further

details).

The data rate formula that relates the value of the DATARATE_M and DATARATE_E registers to the data rate in symbol per second is the following:

Data rate formula

DS13831 - Rev 1 page 25/73

S2-LPS

Digital modulator

4.4.5

4.4.5.1

if DATARATE_E = 0

DataRate = fdig ·

216 + DATARATE_M ∙ 2DATARATE_E

233

if DATARATE_E > 0 fdig

8 ∙ DATARATE_M if DATARATE_E = 15

(13) where f dig

is the digital clock frequency.

In the cases where DATARATE_E<15, the actual modulator timing is generated by a fractional clock divider hence is affected by a certain amount of jitter. In order to have a jitter free data rate generation a specific mode the last equation must be used, DATARATE_E = 15 (for transmission only).

Receiver

The S2-LPS contains a low-power low-IF receiver able to amplify the input signal and provide it to the ADC with a proper signal to noise ratio. The RF antenna signal is converted to a differential one by an external balun, which performs an impedance transformation also. The receiver gain can be programmed to accommodate the

ADC input signal within its dynamic range. After the down-conversion at IF, a first order filter is implemented to attenuate the out-of-band blockers.

Automatic frequency compensation

The automatic frequency compensation (AFC for short) algorithm allows compensating, within certain limits, a relative frequency error between the transmitting device and the receiving one caused by for example from crystal inaccuracies.

The AFC algorithm is operational only for frequency modulation such as 2-(G)FSK and 4-(G)FSK.

Due to the demodulation algorithm employed, any frequency error results in a DC offset in the demodulated signal before slicing.

The basic operating principle of the AFC is that the minimum and maximum signal frequencies are detected and a correction is calculated to remove the aforementioned offset.

Such correction is either applied at the slicer level in the form of offset compensation (default mode) or, optionally, is used to adjust the second IF conversion stage frequency. The former mode allows a quick recovery of the frequency error but does not prevent part of the received signal power to be cut by the channel filter; the latter mode adjusts the signal frequency before entering the channel filter thus avoiding power loss but requires a longer period to settle. The first mode is recommended for normal operation.

The AFC also provides the estimated frequency error through the AFC_CORR register. If the frequency error is known to be constant (for example communication always occurs between the same pair of devices), this value can directly be used to correct the programmed center frequency.

In order to guarantee both fast lock and smooth tracking, the AFC has a fast mode and a slow mode. The

AFC will start in fast mode as soon as the RSSI threshold is passed and will switch to the slow mode after a programmable period.

The AFC is controlled by the following parameters:

• RSSI threshold: this parameter sets the minimum signal power above which the AFC algorithm is started

(RSSI_TH register).

•

AFC fast gain log2: this parameter sets the loop gain in the fast mode (AFC0 register), the range allowed is

0..15.

AFC slow gain log2: this parameter sets the loop gain in the slow mode (AFC0 register), the range allowed is

0..15.

•

AFC fast period: this parameter sets the length of the fast period in number of samples (AFC1 register), the range allowed is 0...255. The recommended setting for this parameter is such that the fast period equals the preamble length. Since the algorithm operates typically on 2 samples per symbol, the programmed value should be twice the number of preamble symbols. If this parameter is set to 0 then the switching from fast to slow mode is controlled by the sync word detection, for example the fast gain is used before the sync detection, the slow gain is used after sync detection.

AFC mode: this parameter sets the AFC correction mode (AFC2 register. 0b: slicer correction, 1b: 2nd IF correction).

AFC enable: this parameter enables the AFC algorithm (AFC2 register).

DS13831 - Rev 1 page 26/73

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Digital modulator

4.4.5.2

4.4.5.3

Automatic gain control

The automatic gain control (AGC for short) algorithm is designed to keep the signal amplitude at the input of the

IF ADC within a specific range by controlling the gain of the RF chain in 6 dB steps, up to a maximum attenuation of 48 dB, starting at a received signal power of about -50 dBm.

From an implementation point of view, the (peak) signal amplitude is measured in the digital domain after the primary decimation filters chain and compared to a low threshold and to a high threshold. If the amplitude is above the high threshold, the attenuation is increased sequentially until the amplitude goes below the threshold; if the amplitude is below the low threshold, the attenuation is decreased sequentially until the amplitude goes above the threshold.

The AGC algorithm is controlled by the following parameters:

High threshold : this value sets the digital signal level above which the RF attenuation is increased (AGCCTRL1 register, allowed values 0...15). The recommended setting for such parameter is 0x5.

Low thresholds : this allows a better tuning of the low thresholds in case the analog attenuation steps have a significant spread around the nominal 6 dB attenuation. The threshold actually used for each step is selected through the bits of the LOW_THRESHOLD_SEL (AGCCTRL3) register. The recommended setting for Low Threshold 0 is 0x5, recommended setting for Low Threshold 1 is 0x4. The recommended value for

LOW_THRESHOLD_SEL is 0x10.

Measure time : this parameter sets the measurement interval during which the signal level is monitored before the AGC attenuation is decreased. In particular, if the signal level is below the low threshold for all the duration of such period, then the attenuation is decreased.

The actual time is T

AGC meas

12 fdig

∙ 2

MEAS_TIME

, ranging from about 0.5 µs to about 15 ms.

For frequency modulation, the measurement time is normally set to a few µs in order to achieve fast settling of the algorithm.

For amplitude, to avoid an unstable behavior, the measure time must be larger than the duration of the longest train of ‘0’ symbols expected during the preamble/synchronization word.

The default value for such parameter is 0x2.

Hold time : this parameter sets a wait time for the algorithm to let the signal level to settle after a change in the attenuation level.

The actual time is T

AGC ℎold

12 fdig

∙ HOLD_TIME , ranging from about 0.5 µs to about 32 µs.

The recommended setting for such parameter is 0x0C.

AGC enable : enables the AGC algorithm.

Freeze on sync : freeze the AGC level after when the sync word has been received.

The AGC algorithm works in the following way:

• If the amplitude is above the high threshold, goes below the threshold. In this case the T the attenuation is increased sequentially until the amplitude meas

is set to 0 and only the hold time is used. Thus, if the signal is above the high threshold, the AGC word is changed each T hold

seconds.

• If the amplitude is below the low threshold, the attenuation is decreased sequentially until the amplitude goes above the threshold. In this case the T meas

is set to the value: T hold

= (12*2MEAS_TIME)/f dig

. Thus, if the signal is below the low threshold, the AGC word is changed each T meas

+ T hold

seconds.

The two operations are repeated in a loop until the input signal strength is between the high and the low threshold.

Symbol timing recovery

The S2-LPS supports two different algorithms for the timing recovery. The selection of the algorithm is done with the register CLOCK_REC_ALGO_SEL.

• If CLOCK_REC_ALGO_SEL = 0, then a simple first order algorithm is used (shortly referred to as DLL).

• If CLOCK_REC_ALGO_SEL = 1, then a second order algorithm is used (shortly referred to as PLL).

Besides the configuration parameters mentioned above, the setting of the following registers also affects the behavior of the clock recovery algorithms.

• Post-filter length: this parameter controls the length of the demodulator post-filter (CLOCKREC register).

Setting this value to 1B may improve demodulation performance but requires a slower recovery. The recommended value for such parameter is 0B.

DS13831 - Rev 1 page 27/73

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Digital modulator

M=0

M=1

M=2

M=3

M=4

M=5

M=6

M=7

M=8

4.4.5.3.1

4.4.5.3.2

4.4.5.4

• RSSI threshold: this parameter sets the minimum signal power above which the timing recovery is started

(RSSI_TH register).

DLL mode

The DLL algorithm, being based on a first order loop, is only able to control the delay of the local bit-timing generator in order to align it to the received bit period. If there is an error between the actual received bit period and the nominal one, the relative edges will drift over time and the algorithm will periodically apply a delay correction to recover. Since in presence of long sequences of zeroes or ones it is not possible to estimate any timing error, the loop tends to lose lock if the period error is large (greater than 3%).

The convergence speed of the loop is controlled by the CLK_REC_P_GAIN_FAST/SLOW parameter (KP) in the

CLOCKREC1 and CLOCKREC2 registers with a smaller value yielding a faster loop. Allowed values for KP are from 0 to 7. The optimal values obtained for all modulations and data rates are KP = 1 or KP = 2.

PLL mode

The PLL algorithm tracks the phase error of the local timing generator relative to received bit period and controls both frequency and phase to achieve the timing lock. Once that the relative period error has been estimated and corrected for example during the preamble phase, then even in presence of long sequences of zeroes or ones, the loop is able to keep lock.

In order to improve the performance of the algorithm, two sets of gain coefficients can be configured to be used before and after the sync word detection.

In particular, CLK_REC_I_GAIN_FAST and CLK_REC_P_GAIN_FAST are used before the SYNC while

CLK_REC_I_GAIN_SLOW and CLK_REC_P_GAIN_SLOW are used after the SYNC detection.

RX channel filter bandwidth

The bandwidth of the receiver channel filter is programmable from 1 kHz to 800 kHz. The setting goes through the register CHFLT according to the following table.

4.4.5.5

E=0

800.1

795.1

768.4

736.8

705.1

670.9

642.3

586.7

541.4

E=1

450.9

425.9

403.2

380.8

362.1

341.7

325.4

294.5

270.3

E=2

224.7

212.4

201.1

190.0

180.7

170.6

162.4

147.1

135.0

Table 37. Channel filter words

E=3

112.3

106.2

100.5

95.0

90.3

85.3

81.2

73.5

67.5

E=4

56.1

53.0

50.2

47.4

45.1

42.6

40.6

36.7

33.7

E=5

28.0

26.5

25.1

23.7

22.6

21.3

20.3

18.4

16.9

E=6

14.0

13.3

12.6

11.9

11.3

10.6

10.1

9.2

8.4

E=7

7.0

6.6

6.3

5.9

5.6

5.3

5.1

4.6

4.2

E=8

3.5

3.3

3.1

3.0

2.8

2.7

2.5

2.3

2.1

The actual filter bandwidth for any digital clock frequency can be obtained by multiplying the values in the table above by the factor fdig

26000000

. The bandwidth values are intended as double-sided.

Intermediate frequency setting

The intermediate frequency (IF) can be tuned and be controlled by the registers IF_OFFSET_ANA and

IF_OFFSET_DIG and can be set as follows:

Intermediate frequency fIF =

IF _OFFSET _ANA + 100

211

IF _OFFSET _DIG + 100

211

(14) where f

is the XTAL oscillator frequency and f about 300 kHz.

dig

is the digital clock frequency. The recommended IF value is

E=9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

DS13831 - Rev 1 page 28/73

S2-LPS

Digital modulator

4.4.5.6

RX timer management

The programmable RX timer used can be configured using quality indicator to avoid unwanted interruption during a valid packet due to RX timer expiration. The quality indicators used to stop the RX timer are SQI, CS and

PQI. More specifically, AND or OR Boolean relationships among any of them can be configured, to suit user application. In particular, it is required to include always SQI valid check, to avoid to stay in RX state for unlimited time, if timeout is stopped but no valid SQI is detected (in such cases, the RX state can be left using a SABORT command).

On timer expiration, reception aborts and the packet is discarded.

Table 38. RX timer stop condition configuration

RX_TIMEOUT_AND_OR_SELECT CS_TIMEOUT_MASK SQI_TIMEOUT_MASK

PQI_TIMEOUT_MASK

Description

The RX timeout never expires and the reception ends at the reception of the packet

The RX timeout cannot be stopped. It starts at the RX state and at the end expires

RSSI above threshold

SQI above threshold (default)

PQI above threshold

Both RSSI AND SQI above threshold

Both RSSI AND PQI above threshold

Both SQI AND PQI above threshold

ALL above threshold

RSSI OR SQI above threshold

RSSI OR PQI above threshold

SQI OR PQI above threshold

ANY above threshold

4.4.5.7

4.4.5.8

Receiver data modes

Direct modes are primarily intended to completely bypass the automatic packet handler, in order to give the user maximum flexibility in the choice of frame formats. Specifically:

• Direct through FIFO mode : the packet bytes are continuously received and written in the RX FIFO without any processing. It is the responsibility of the microcontroller to avoid any overflow conditions on the RX

FIFO.

• Direct through GPIO mode : the packet bits are continuously written to one of the GPIO pins without any processing. To allow the synchronization of an external data sink, a data clock signal is also provided on one of the GPIO pins. Data are updated by the device on the falling edge of such clock signal so the MCU must read it during falling edge of CLK.

Receiver quality indicators

DS13831 - Rev 1 page 29/73

S2-LPS

Digital modulator

4.4.5.8.1

4.4.5.8.2

RSSI

The received signal strength indicator (RSSI) is a measurement of the received signal power at the antenna measured in the channel filter bandwidth. The measured RSSI is in steps of 1 dB, from 0 to 255 (1 byte value) and it is offset in such a way that the number 0 corresponds to -146 dBm, so the register value can be converted in dBm by subtracting 146. Laboratory calibration may be needed for accurate absolute power measurements.

The RSSI value can be read through two registers: RSSI_LEVEL_CAPTURE and RSSI_LEVEL_RUN. In particular RSSI_LEVEL_CAPTURE reports the RSSI value captured at the end of the SYNC word detection, exit from RX state by SABORT command or RX timeout expiration, while RSSI_LEVEL_RUN is the continuous output of the RSSI filter. The last mode supports the continuous fast SPI reading that means if the CSn signal, of the SPI interface, is kept low, after the first 16 bits (S2-LP status register), then a new RSSI value will be available every 8 SPI clock cycles (this mode is the same of the SPI burst mode, but no automatic address increment).

Carrier sense

The carrier sense functionality can be used to detect if any RF signal is being received, the detection is based on the measured RSSI value. There are two operational modes for carrier sensing: static and dynamic carrier sensing.

When static carrier sensing is used (CS_MODE = 0), the carrier sense signal is asserted when the measured

RSSI is above the value specified in the RSSI_TH register and is de-asserted when the RSSI falls 3 dB below the same threshold.

When dynamic carrier sense is used (CS_MODE = 1, 2, 3), the carrier sense signal is asserted if the signal is above the threshold and a fast power increase of 6, 12 or 18 dB is detected; it is de-asserted if a power fall of the same amplitude is detected.

The carrier sense signal is also used internally to the demodulator to start the automatic frequency compensation and timing recovery algorithms.

The carrier sense function is controlled by the following parameters:

•

RSSI threshold: this parameter sets the minimum signal power above which the carrier sense signal is asserted (RSSI_TH register).

CS mode: this parameter controls the carrier sense operational modes.

4.4.5.8.3

4.4.5.8.4

CS_MODE

Table 39. CS mode description

Description

Static carrier sensing

Dynamic carrier sensing with 6 dB dynamic threshold

Dynamic carrier sensing with 12 dB dynamic threshold

Dynamic carrier sensing with 18 dB dynamic threshold

PQI

The preamble quality indicator (PQI) is intended to provide a measurement of the reliability of the preamble detected. The PQI is increased by 1 every time a bit inversion occurs, while it is decreased by 4 every time a bit repetition occurs. The running peak PQI is compared to a threshold value and the preamble valid IRQ is asserted as soon as the threshold is passed. The preamble quality indicator threshold is 4 x PQI_TH (with PQI_TH = 0, 1,

…15).

SQI

The synchronization quality indicator (SQI) is a measurement of the best correlation between the received SYNC word and the expected one. This indicator is calculated as the peak cross-correlation between the received data stream and the expected SYNC word. If the SQI_EN = 1b, the running peak SQI is compared to a threshold value and the SYNC valid IRQ is asserted as soon as the threshold is passed. The SYNC quality threshold is equal to SYNC_LEN – 2 x SQI_TH (with SQI_TH = 0, 1, …7). When SQI_TH = 0b, perfect match is required. It is recommended the SQI check always enabled. The peak SQI value can be read from the register SQI[5:0] and represents the peak value from 0 to 32, while the bit SQI[6], when equal to ‘1’ indicates that the SQI peak value refers to the secondary SYNC word.

DS13831 - Rev 1 page 30/73

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Digital modulator

4.4.5.9

4.4.5.10

4.4.6

4.4.6.1

CS blanking

The CS blanking feature prevents data to be received if the RSSI level on the air is below the RSSI threshold (set by the RSSI_TH field). The feature can be enabled through the CS_BLANKING bit in the ANT_SELECT_CONF register.

Antenna switching

The device implements a switching based antenna diversity algorithm. The antenna switching function allows controlling an external switch in order to select the antenna providing the highest measured RSSI. The switching decision is based on a comparison between the received power level on antenna 1 and antenna 2 during the preamble reception controlling through GPIO an external RF switch in order to select the antenna providing the highest measured RSSI.

When antenna switching is enabled, the two antennas are repeatedly switched during the reception of the preamble of each packet, until the carrier sense threshold is reached (static CS mode must be used). From this point on, the antenna with highest power is selected and switching is frozen. The switch control signal is available on GPIO and in the MC_STATE[1] register.

The algorithm is controlled by the following parameters:

• AS_MEAS_TIME: this register/parameter controls the time interval for RSSI measurement. The actual measurement time is done with the following formula.

Antenna switching measurement time

Tmeas = 24 ∙ 2

CHFLT_E ∙ 2AS_MEAS_TIME fdig

(15)

In case of FSK modulation, the whole T meas

is used to let the signal level settle after the antenna switch and one single measurement is taken at the end of such period.

In case of OOK modulation, after one first interval equal to T meas the antenna switch, one second interval still equal to T meas select the best antenna.

again used to let the signal level settle after

, is used to perform a peak power measurement and

• AS_ENABLE: this parameter enables the antenna switching function.

Transmitter

The S2-LPS contains an integrated PA capable of transmitting at output levels programmable between -30 dBm to

+14 dBm (+16 dBm in boost mode), at step of 0.5 dB.

The PA is single-ended and has a dedicated pin (TXOUT). The PA output is ramped up and down to prevent unwanted spectral splatter. In TX mode the PA drives the signal generated by the frequency synthesizer out to the antenna terminal. Delivered power, as well as harmonic content, depends on the external impedance seen by the

PA. It is possible to program TX to send an unmodulated carrier.

The output stage is supplied from the SMPS through an external choke and is loaded with a LC-type network which has the function of transforming the impedance of the antenna and filter out the harmonics. The TX and RX pins are tied directly to share the antenna. During TX, the LNA inputs are internally shorted to ground to allow for the external network resonance, so minimizing the power loss due to the RX.

PA configuration

The PA output power level is programmable in 0.5 dB steps. The user can store up to eight output levels to provide flexible PA power ramp-up and ramp-down at the start and end of a frequency modulation transmission as well as ASK modulation shaping.

With the digital power-ramping enabled (PA_RAMP_EN = 1 in the PA_POWER0 register) the ramp starts from the minimum output power programmed and stops at the programmed maximum value, thus a maximum of 8 steps can be set up as shown in

Figure 10. Output power ramping configuration . The interpolation factor ranges from 64

down to 1 depending on the actual data rate. The assumption is that output power monotonically decrease. Each step is held for a programmable time interval expressed in terms of bit period units (T b

/8), maximum value is 3

(which means 4×T b

/8=T b

/2). Therefore, the PA ramp may last up to 4 T b

(about 3.3 ms if the bit rate is 1.2 kbit/s).

Tramp =

PA_RAMP_STEP_LEN + 1 × PA_LEVEL_MAX_IDX + 1

8 × DataRate where DataRate is the transmission data rate expressed in symbols/s.

(16)

DS13831 - Rev 1 page 31/73

S2-LPS

Digital modulator

The set of eight levels is used to shape the ASK signal. In this case, the modulator works as a counter that counts when transmitting a one and down when transmitting a zero. The counter counts at a rate equal to 8 times the symbol rate (in this case, the step width is fixed by symbol rate).

For OOK modulation, the signal is abruptly switched between two levels only: no power and maximum. This mode is obtained setting the PA_RAMP_EN=0.

With the digital power-ramping, the digital PA interpolation can be enabled through the PA_INTERP_EN field of the MOD1 register.

When this feature is enabled, the power values specified in the PA_POWER registers are linearly interpolated by the modulator before being applied to the PA.

The mathematical interpolation factor applied at each output sample is 64 for data rates corresponding to

DATA_RATE_E < 5, it is then automatically scaled as

2DATA_RATE_E − 5

and it is automatically disabled for

DATA_RATE_E = 11.

Figure 10. Output power ramping configuration

4.4.6.2

Transmitter data modes

Direct modes are primarily intended to completely bypass the automatic packet handler, in order to give the user maximum flexibility in the choice of frame formats. In specific:

• Direct through FIFO mode : the packet is written in TX FIFO. The user build the packet according to his need including preamble, payload and soon on. The data are transmitted without any processing.

•

Direct through GPIO mode : the packet bits are continuously read from one of the GPIO pins, properly configured, and transmitted without any processing. To allow the synchronization of an external data source, a data clock signal is also provided on one of the GPIO pins. Data are sampled by the device on the rising edge of such clock signal; it is the responsibility of the external data source to provide a stable input at this edge.

PN9 mode : a pseudo-random binary sequence is generated internally. This mode is provided for test purposes only.

DS13831 - Rev 1 page 32/73

S2-LPS

Digital modulator

4.4.6.3

Data FIFO

In the S2-LPS there are two data FIFOs, a TX FIFO for data to be transmitted and an RX FIFO for the received data both of 128 bytes. The SPI interface is used to read from the RX FIFO and write to the TX FIFO starting from the address 0xFF.

Figure 11. Threshold in FIFO

DS13831 - Rev 1

The TX FIFO has two programmable thresholds (see figure above). An interrupt event occurs when the data in the TX FIFO reaches any of these thresholds. The first threshold is the “FIFO Almost Full” threshold, TX_AF_THR registers. The value in this field corresponds to the desired threshold value in number of bytes + 2. When empty locations (free) amount inside the TX FIFO reaches this threshold limit, an interrupt to the MCU is generated so it can send a TX command to transmit the contents of the TX FIFO. The second threshold for TX is the “FIFO

Almost Empty” threshold, TX_AE_THR register. When the data being shifted out of the TX FIFO reaches the

Almost Empty threshold, an interrupt will be generated also. The MCU could to switch out of TX mode or fill new data into the TX FIFO.

The RX FIFO has two programmable thresholds (see figure above). The first threshold is the “FIFO Almost

Full” threshold, RX_AF_THR0 registers. The value in this register corresponds to the desired threshold value in number of bytes. When empty locations (free) amount inside the RX FIFO reaches this threshold limit, an interrupt will be generated to the MCU. The MCU should then start to read the data from the RX FIFO. The second threshold for RX is the “FIFO Almost Empty” threshold, RX_AE_THR register. When the data being shifted out of the RX FIFO reaches the Almost Empty threshold, an interrupt will be generated also. The MCU will need to switch on RX mode to fill with new data the RX FIFO or stop to read after the number of byte indicated by the

RX_AE_THR register.

In order to enable the RX_FIFO thresholds interrupts, the bit FIFO_GPIO_OUT_MUX_SEL (PROTOCOL2 register) must be set to 1. To enable the TX_FIFO thresholds interrupts the FIFO_GPIO_OUT_MUX_SEL must be set to 0.

The FIFO controller detects overflow or underflow in the RX FIFO and overflow or underflow in the TX FIFO. It is the responsibility of the MCU to avoid TX FIFO overflow since the MCU only can decide to writing on the TX

FIFO. A TX FIFO overflow results in an error in the TX FIFO content, while an underflow results in the continuous transmission of the last byte stored in the TX FIFO. Likewise, when reading the RX FIFO the MCU must avoid reading the RX FIFO after its empty condition is reached, since a RX FIFO underflow will result in an error in the data read out of the RX FIFO.

When an overflow or an underflow is detected, the MCU has to issue a SABORT and a FLUSHTXFIFO/

FLUSHRXFIFO command before resuming the normal transceiver activity. For each FIFO, when one of these errors is detected an interrupt is generated to the MCU.

The TX FIFO may be flushed by issuing a FLUSHTXFIFO command (see

Table 42. Commands

). Similarly, a

FLUSHRXFIFO command flushes the RX FIFO.

page 33/73

4.4.7

4.4.8

4.4.9

S2-LPS

Digital modulator

The full / empty status of the TX / RX FIFO is readable on the bits [9:8] of the MC_STATE registers, and at the same time, the related IRQs are generated.

In the SLEEP state, the FIFO content is retained only if the SLEEP_B mode is selected (bit

SLEEP_MODE_SEL=1 in the register 0x79).

Integrated RCO

The S2-LPS contains an ultra-low power RC oscillator with accuracy better than 1%. The RC oscillator frequency is calibrated using as a reference the XO frequency. It depends on two values: raw (4 bits) and fine (5 bits). The raw value is obtained by a linear search algorithm in which for each value a counting of half clock reference inside the period of RCO is done. When the correction is near to the final value, a dichotomy search algorithm starts.

The RCO calibration starts as soon as the RCO_CALIBRATION bit is set to 1. When it finishes, the RC_CAL_OK bit is set and the ERROR_LOCK bit is reset.

Moreover, after a sleep or standby state, if the RCO_CALIBRATION bit is kept to 1, when the device returns to the ready state, an RCO calibration automatically runs to compensate some drift.

It is possible to perform an offline calibration of the RCO using the following procedure:

Enable the RCO CALIB setting the bit to 1

Wait until the RC_CAL_OK becomes 1

Copy the RWT_OUT and RFB_OUT (registers 0x94 and 0x95) out values in the RWT_IN and RFB_IN fields

(registers 0x6E and 0x6F)

Disable the RCO CALIB setting the bit to 0

In this way, the RCO works with these values. It is advisable to repeat the RCO calibration to reject effects related to the variation of temperature. It is recommended to use this procedure if the following SLEEP time (i.e. when using LDC mode) is shorter or comparable to the calibration time.

By default, the calibration is disabled at reset to avoid using an out-of-range reference frequency, after the internal clock divider is correctly configured, the user can enable the RCO calibration by register.

Once calibrated, the RCO generates a clock frequency that depends on the XO frequency used:

Table 40. RCO Frequency

Ref. frequency [MHz]

24 or 48

25 or 50

26 or 52

RCO frequency [kHz]

33.33

34.66

•

Low battery indicator

The battery indicator can provide the user with an indication of the battery voltage level.

There are two blocks to detect battery level:

• Brownout with a fixed threshold

Battery level detector with a programmable threshold

The MCU enables optionally these blocks to provide an early warning of impending power failure. It does not reset the system, but gives the MCU time to prepare for an orderly power-down and provides hardware protection of data stored in the program memory.

The low battery indicator function is available in any of the S2-LPS operation modes. As this function requires the internal bias circuit operation, the overall current consumption in STANDBY, SLEEP, and READY modes increase by 400 µA.

Voltage reference

This block provides the precise reference voltage needed by the internal circuit.

DS13831 - Rev 1 page 34/73

S2-LPS

Operating modes

Operating modes

The S2-LPS is provided with a built-in main controller which controls the switching between the two main operating modes: transmitter (TX) and receiver (RX), driven by SPI commands.

In shutdown condition (the S2-LPS can be switched on/off with the external pin SDN), no internal supply is generated, and all stored data and configurations are lost.

From shutdown, the S2-LPS can be switched on going to READY state, where the reference clock signal is available.

From READY state, the S2-LPS can be moved to LOCK state to generate the high precision LO signal and then in TX or RX modes. Switching from RX to TX and vice versa can happen only by passing through the LOCK state. This operation is managed by the main controller through a single user command (TX or RX). At the end of the operations, the S2-LPS can return to READY state or can go to SLEEP state, having a very low power consumption.

SLEEP state can be configured to retain the FIFOs content or not enabling very low power mode. If also no wake-up timer is required, the S2-LPS can be moved from READY to STANDBY state, which has the lowest possible current consumption.

Figure 12. State diagram

DS13831 - Rev 1

Three states: READY, STANDBY and LOCK may be defined as stable state.

All other states are transient, which means that, in a typical configuration, the controller remains in those states, at most for any timeout timer duration. Also the READY and LOCK states behave as transients when they are not directly accessed with the specific commands (for example, when LOCK is temporarily used before reaching the

TX or RX states).

State code

(1)

0x02

State name

SHUTDOWN

STANDBY

Digital LDO

OFF

Table 41. States

SPI

Off

XTAL

Off

RF synth.

Off

Wake-up timer

Off

Off page 35/73

5.1

5.2

S2-LPS

Command list

State code

0x01

0x03

0x00

0x0C

0x30

0x5C

0x50

(1)

State name

SLEEP_A

SLEEP_B

READY

LOCK

SYNTH_SETUP

Digital LDO SPI

XTAL

Off

RF synth.

Off

Wake-up timer

Do not care

1. Other codes are invalid and are an indication of an error condition due to bad register configuration and/or hardware issue in the application board hosting.

Commands are used in the S2-LPS to change the operating mode and to use its functionality. A command is sent on the SPI interface and may be followed by any other SPI access without pulling CSn high. A command code is the second byte to be sent on the MOSI pin (the first byte must be 0x80). The commands are immediately valid after SPI transfer completion (no need for any CSn positive edge).

Command list

Table 42. Commands

Command code

0x60

0x61

0x62

0x63

0x64

0x65

0x66

0x67

0x68

0x70

0x71

0x72

0x73

Command name

READY

STANDBY

SLEEP

LOCKRX

LOCKTX

SABORT

LDC_RELOAD

SRES

FLUSHRXFIFO

FLUSHTXFIFO

SEQUENCE_UPDA TE

State for execution

READY

STANDBY, SLEEP,

LOCK

READY

TX, RX

ANY

All

ANY

Description

Send the S2-LPS to TX state for transmission

Send the S2-LPS to RX state for reception

Go to READY state

Go to STANDBY state

Go to SLEEP state

Go to LOCK state by using the RX configuration of the synthesizer

Go to LOCK state by using the TX configuration of the synthesizer

Exit from TX or RX states and go to READY state

Reload the LDC timer with a pre-programmed value stored in registers

Reset the S2-LPS state machine and registers values

Clean the RX FIFO

Clean the TX FIFO

Reload the packet sequence counter with the value stored in register

State transaction response time

Initial state

SHUTDOWN

Table 43. Response time

Final state

READY

Response time [µs]

500

DS13831 - Rev 1 page 36/73

Note:

5.3

S2-LPS

Sleep states

Initial state

READY

RX/TX

STANDBY/SLEEP

LOCK

Final state

STANDBY/ SLEEP

LOCK with no VCO calibration

LOCK with VCO calibration

READY

RX/TX

Response time [µs]

100

The transition time enables the S2-LPS for frequency hopping operation due to its reduced response time and very quick programming synthesizer. The response time depends on frequency of the clock in digital domain, from 24 MHz to 26 MHz.

The first bit of preramble is sent after TX state is reached, if PA ramping is not enabled. If PA ramping is

enabled, the first bit is sent after tramp (see Section 4.4.6.1 PA configuration ).

Sleep states

S2-LPS provides 2 SLEEP states:

• SLEEP without FIFO retention (SLEEP_A): in this low power state, the device keeps all the register values but not the TX and RX FIFOs. This is the device default SLEEP state.

• SLEEP with FIFO retention (SLEEP_B): in this low power state, the device keeps the content of the registers and the two FIFOs.

The responsibility of the SLEEP type to be used is demanded to the user. To select the SLEEP mode, the bit

SLEEP_MODE_SEL (register 0x79) can be used. If this bit is set to 0, SLEEP_A is used each time the device enters SLEEP (by SPI command, LDC flow in non-persistent mode). If it is 1, SLEEP_B is used instead.

DS13831 - Rev 1 page 37/73

6.1

S2-LPS

Packet handler engine

Packet handler engine

•

The S2-LPS offers a highly flexible and fully programmable packet handler (framer and de-framer) that build the packet according to the user configuration settings. The packet types are available: BASIC format, and UART over the air packet format.

WMBUS format is supported but it can be obtained using the proper features combination.

The RX packet handler is in charge of treating the raw bits produced by the demodulator. The main functions of the RX packet handler are:

• Detect a valid preamble

Detect a valid synchronization word and start-of-frame

Extract all packet fields according to the selected packet format

Calculate the local CRC and compare to the received one

The device supports 2 different packet formats. The current packet format is set by the PCK_FRMT field of the

PCKTCTRL3 register.

In particular:

• 0: Basic packet format

• 2: UART over the air packet format

BASIC packet format

The packet format BASIC is selected by writing 0b in the register PCK_FRMT. The packet frame is as follows:

•

Preamble

0:2046 bits

Sync

0:32 bits

Table 44. BASIC packet format

Length

0:2 bytes

Address

0:1 bytes

Payload

0:65535 bytes

CRC

0:4 bytes

Postamble

0:510 bits

Preamble : each preamble is a pair of ‘01’ or ‘10’ from 0 pair to 1023 pairs, programmed by the register

PREAMBLE_LENGTH. The binary sequences transmitted in the various modulation modes are summarized in the following table (leftmost bit is transmitted first).

PREAMBLE_SEL

Table 45. Preamble field selection

2(G)FSK or OOK/ASK

0101

1010

1100

0011

DS13831 - Rev 1 page 38/73

6.2

S2-LPS

UART over the air packet format

•

Sync : the pattern that identify the start of the frame can be configured in value with a programmable length from 0 to 32 bits, in steps of 1-bit length. The setting is done by the register SYNC_LENGTH. The S2LP supports dual synchronization with a either a primary or a secondary synchronization word. The binary content of the primary SYNC word is programmable through registers SYNCx (x= 0, 1, 2, 3). The binary content of the secondary SYNC word is programmable through registers SEC_SYNCx (x= 0, 1, 2, 3), note that such registers are in alternate use with address filtering registers. On the transmitter side either the primary or the secondary word is transmitted according to the value of the SECONDARY_SYNC_SEL register, in particular if SECONDARY_SYNC_SEL = 0 then the primary synchronization word is transmitted; if SECONDARY_SYNC_SEL = 1 then the secondary synchronization word is transmitted. On the receiver side, the primary synchronization word is always enabled. The search for the secondary synchronization word can be enabled setting SECONDARY_SYNC_SEL = 1b. In this case, both the binary patterns are searched for and both of them can trigger the start of payload demodulation. The SQI[5:0] value reported in the LINQ_QUALIF register is the maximum between the SQI of the primary and secondary words.

The bit SQI[6] indicates which synchronization word has been detected: in particular, if the secondary synchronization word has been detected then the SQI[6] = 1b otherwise if the primary synchronization word has been detected then SQI[6] = 0b. The binary pattern programmed in SYNCx (or SEC_SYNCx) is transmitted on air starting with the most significant bit of x = 1, to the least significant bit of x = 4 according to the programmed synchronization word length.

Length : The device supports both fixed and variable packet length transmission from 0 to 65535 bytes. On the transmitting device, the packet length is always set by using the two registers PCKTLENx (x= 1, 2) as:

PCKTLEN1 × 256 + PCKTLEN0. On the receiving device, if FIX_VAR_LEN register is set to ‘1’, the packet length is directly extracted from the field Length of the received packet itself. If the register FIX_VAR_LEN

= 0b the Length field of the received packet is not used, because is already known from the registers

PCKTLENx (x= 1, 2) as for the transmitter. For the basic and stack packet formats, the number of address bytes is also counted in the packet length value. CRC is excluded. Furthermore, when variable packet length is used (FIX_VAR_LEN=1b), the width of the binary field transmitted, must be configured through the

LEN_WID register in the following way:

– If the packet length is from 0 to 255 bytes (payload + address field), then LEN_WID = 0b (1 byte length field transmitted).

– If the packet length is from 0 to 65535 bytes (payload + address field), then LEN_WID = 1b (2 bytes length field transmitted).

Destination address : can be enabled or no by the register ADDRESS_LEN. If enabled,

ADDRESS_LEN=1b, its size is 1 byte. The destination address field is read from the register

RX_SOURCE_ADDR (TX only). The receiver uses this field to perform automatic filtering on its value programmed in TX_SOURCE_ADDR (RX only).

Payload : the main data from transmitter with a max length up to 65535 supported by the embedded automatic packet handler.

CRC : can optionally be calculated on the transmitted data (Length field, Address field and Payload) and appended at the end of the payload (see

Section 6.5.1 CRC

Postamble : The packet postamble allows inserting a certain number of ‘01’ bit pairs at the end of the data packet. The number of postamble bit pairs can be set through the MBUS_PSTMBL register.

UART over the air packet format

Preamble

0:2046 bits

Table 46. UART over the air packet format

Sync

0:32 bits

Payload

0:65535 bytes

When this format is selected, a start bit and a stop bit can be programmed to be added to each byte of the TX

FIFO. Such start and stop bits are automatically removed from the received payload before written to the RX

FIFO. Start and stop bits are not added to the SYNC word.

Also, the BYTE_SWAP bit can be set in order to send the FIFO bytes in LSbit first (default is indeed MSbit first).

The actual binary value of the start and stop bit can be set through the START_BIT and the STOP_BIT fields of the PCKTCTRL2 register.

DS13831 - Rev 1 page 39/73

6.3

6.4

6.5

6.5.1

S2-LPS

Wireless MBUS packet (W-MBUS, EN13757-4)

The W-MBUS packet structure referred to EN13757 can be obtained through registers setting programming the basic packet to fit the specific sub-mode used.

Preamble Sync 1 st block 2 nd block Opt. blocks Postamble

Preamble : the preamble is fully programmable to fit the W-MBUS protocol. The generic setting is a pair of ‘01’ or

‘10’ from 1 pair to 1024 pairs (max. 256 bytes).

Sync : the pattern that identify the start of the frame is fully programmable to fit the W-MBUS protocol. The generic setting is in value with a programmable length from 1 bit to 64 bytes, in steps of 1-bit length.

Data blocks : the data coding can be fully programmed in NRZ and Manchester.

Postamble : The packet postamble allows inserting a certain number of ‘01’ bit pairs at the end of the data packet.

The number of postamble bit pairs can be set through the MBUS_PSTMBL register depending on the chosen sub-mode according to the W-MBUS protocol.

Payload transmission order

The bit order of the data from TX FIFO and written into the RX FIFO is controlled by the BYTE_SWAP register. In particular, the transmission is MSB first if BYTE_SWAP = 0 and LSB first if BYTE_SWAP = 1.

•

Automatic packet filtering

The receiver uses the following filtering criteria to reject the received packet. The automatic filtering is supported in BASIC and STack packet format only.

•

CRC : the received packet is discarded if CRC check fails. Both transmitter and receiver must be configured with same CRC polynomial.

Destination address vs my address : the received packet is discarded if the destination address field received does not match the programmed my address of the receiver.

Destination address vs. broadcast address : the received packet is discarded if the destination address field received does not match the programmed broadcast address of the receiver.

Destination address vs. multicast address : the received packet is discarded if the destination address field received does not match the programmed multicast address of the receiver.

Source address : the received packet is discarded if the source address received does not match the programmed source address reference (a bit mask can be included). Supported in STack packet format only.

The automatic filtering can be programmed to discard packet below certain threshold settings. These kind of filtering are general purpose and can be used with any packet format.

• Carrier sense : The carrier sense (CS) functionality detects if any signal is being received, the detection is based on the measured RSSI value. There are 2 operational modes for carrier sensing: static and dynamic.

In static CS mode, the CS is high when the measured RSSI is above the RSSI threshold specified and is low when the RSSI is 3 dB below the threshold. In dynamic CS mode, the CS is high if the signal is above the threshold and a fast power increase of 6, 12, or 18 dB is detected. The CS is also used internally for the demodulator to start the AFC and timing recovery algorithms (static CS mode only).

• PQI : It is possible to set a PQI threshold in such a way that, if PQI is below the threshold, the packet demodulation is automatically aborted.

• SQI : It is possible to set a SQI threshold in such a way that, if SQI is below the threshold, the packet demodulation is automatically aborted. When the SQI threshold is set at 0, a perfect match is required. It is recommended to always enable the SQI check.

CRC

Error detection is implemented by means of cyclic redundancy check codes. The CRC is calculated over all fields excluding preamble and SYNC word. The length of the checksum is programmable to 8, 16, 24 or 32 bits. The following standard CRC polynomials can be selected:

• mode 1: 8 bits: the poly is (0x07) X 8 +X 2 +X+1

DS13831 - Rev 1 page 40/73

6.5.2

S2-LPS

Automatic packet filtering

•

• mode 2: 16 bits: the poly is (0x8005) X 16 +X 15 +X 2 +1 mode 3: 16 bits: the poly is (0x1021) X 16 +X 12 +X 5 +1 mode 4: 24 bits: the poly is (0x864CFB) X 24 +X 23 +X 18 +X 17 +X 14 +X 11 +X 10 +X 7 +X 6 +X 5 +X 4 +X 3 +X+1 mode 5: 32 bits the poly is (0x04C011BB7 ) x 32 +x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 +x+1.

802.15.4g compatible

The initial state of the CRC polynomial is state to all 1b in all cases.

Manchester coding

Manchester coding can be enabled for the Basic and STack packet formats only by setting to ‘1’ the

MANCHESTER_EN register.

Use of Manchester coding is exclusive with FEC and Three-out-of-six coding.

When Manchester coding is enabled each bit ‘1’ is actually transmitted on air as a ‘10’ sequence while a bit ‘0’ is transmitted as a ‘01’ sequence. If enabled, Manchester encoding is applied to all bits following the SYNC word.

DS13831 - Rev 1 page 41/73

7.1

S2-LPS

MCU interface

MCU interface

Communication with the MCU goes through a standard 4-wire SPI interface and 4 GPIOs (plus SHUTDOWN pin).

•

MCU can performs the following operations:

• Program the S2-LPS in different operating modes by sending commands

Read data from the RX FIFO and write data into the TX FIFO

Configure the S2-LPS through the registers

Retrieve information from the S2-LPS

Get interrupt requests and signals from the GPIO pins

Apply external signals to the GPIO pins

Put the S2-LPS in SHUTDOWN state or exit from SHUTDOWN state

Serial peripheral interface

•

The four-wire SPI interface consist of:

• SCLK : the SPI clock from MCU to the S2-LPS

•

MOSI

MISO

CSn

: data from MCU to the S2-LPS

: data from the S2-LPS to MCU

: chip select signal, active low.

•

As the MCU is the master, it always drives the CSn and SCLK. According to the active SCLK polarity and phase, the S2-LPS SPI can be classified as mode 0 (CPOL=0, CPHA=0), which means that the base value of SCLK is zero, data are read on the clock rising edge and data are changed on the clock falling edge. The MISO is in tri-state mode when CSn is high. All transfers are MSB first.

The interface allows the following operations:

Write data (to registers or TX FIFO)

Read data (from registers or RX FIFO)

Send commands.

The SPI communication is supported in all the active states, and also during the low power state: STANDBY and

SLEEP.

When accessing the SPI interface, the two status bytes of the MC_STATE (MC_STATE[1], MC_STATE[0]) registers are sent to the MISO pin.

Figure 13. SPI write sequence

DS13831 - Rev 1 page 42/73

Figure 14. SPI read sequence

S2-LPS

Interrupts

Figure 15. SPI command sequence

7.2

Concerning the first byte, the MSB is an A/C bit (address/commands: 0 indicates that the following byte is an address, 1 indicates that the following byte is a command code), while the LSB is a W/R bit (write/read: 1 indicates a read operation). All other bits must be zero.

Read and write operations are persistently executed while CSn is kept active (low), the address is automatically incremented (burst mode).

Accessing the FIFO is done as usual with the read and write commands, by putting, as address, the code 0xFF.

Burst mode is available to access the sequence of bytes in the FIFO. Clearly, RX-FIFO is accessed with a read operation, TX-FIFO with a write operation.

Bit

Interrupts

In order to notify the MCU of a certain number of events an interrupt signal is generated on a selectable GPIO.

The following events trigger an interrupt to the MCU:

Events group

Packet oriented

Table 47. Interrupts list

Interrupt event

RX data ready

RX data discarded (upon filtering)

TX data sent

Max. re-TX reached

CRC error

TX FIFO underflow/overflow error

RX FIFO underflow/overflow error

DS13831 - Rev 1 page 43/73

7.3

S2-LPS

GPIOs

Bit

Events group

Packet oriented

Signal quality related

Device status related

Timer related

Interrupt event

TX FIFO almost full

TX FIFO almost empty

RX FIFO almost full

RX FIFO almost empty

Max. number of back-off during CCA

Valid preamble detected

Sync word detected

RSSI above threshold (CS)

Wake-up timeout in LDCR mode

READY (2)

STANDBY state switching in progress

Low battery level

Power-on reset

RX timer timeout

Sniff timer timeout

1. The interrupt flag n.15 is set (and consequently the interrupt request) only when the XO clock is available for the state machine. This time may be delayed compared to the actual timer expiration. However, the real time event can be sensed putting the end-of-counting signal on a GPIO output.

2. The interrupt flag n.16 is set each time the S2-LPS goes to READY state and the XO has completed its setting transient (XO ready condition detected).

All interrupts are reported on a set of interrupt status registers and are individually maskable. The interrupt status register must be cleared upon a read event from the MCU.

The status of all the interrupts are reported in the IRQ_STATUS register: bits are high for the events that have generated any interrupts. The interrupts are individually maskable using the IRQ_MASK registers: if the mask bit related to a particular event is programmed at 0, that event does not generate any interrupt request.

GPIOs

The four GPIOs can be configured as follows:

I/O selection

Table 48. GPIO digital output functions

Output signal nIRQ (interrupt request, active low)

POR inverted (active low)

Wake-up timer expiration: ‘1’ when WUT has expired

Low battery detection: ‘1’ when battery is below threshold setting

TX data internal clock output (TX data are sampled on the rising edge of it)

TX state outputs a command information coming from the RADIO_TX block

TX/RX FIFO almost empty flag

TX/RX FIFO almost full flag

RX data output

RX clock output (recovered from received data)

RX state indication: ‘1’ when the S2-LPS is transiting in the RX state

DS13831 - Rev 1 page 44/73

DS13831 - Rev 1

S2-LPS

GPIOs

I/O selection

From 5 to 31

Output signal

Device in a state other than SLEEP or STANDBY: ‘0’ when in SLEEP/STANDBY

Device in STANDBY state

Antenna switch signal used for antenna diversity

Valid preamble detected flag

Sync word detected flag

RSSI above threshold (same indication of CS register)

Reserved

TX or RX mode indicator (to enable an external range extender)

VDD (to emulate an additional GPIO of the MCU, programmable by SPI)

GND (to emulate an additional GPIO of the MCU, programmable by SPI)

External SMPS enable signal (active high)

Device in SLEEP state

Device in READY state

Device in LOCK state

Device waiting for a high level of the lock-detector output signal

TX_DATA_OOK signal (internal control signal generated in the OOK analog smooth mode)

Device waiting for a high level of the READY2 signal from XO

Device waiting for timer expiration to allow PM block settling

Device waiting for end of VCO calibration

Device enables the full circuitry of the SYNTH block

Reserved

Table 49. GPIO digital input functions

Input signal

1 >> TX command

1 >> RX command

TX data input for direct modulation

Wake-up from external input (sensor output)

External clock @ 34.7 kHz (used for LDC modes timing)

Not used page 45/73

S2-LPS

Register contents

Register contents

Name

GPIO0_CONF

Addr

Table 50. Register contents

Default Bit

7:3

00 0A

1:0

GPIO1_CONF

GPIO2_CONF

GPIO3_CONF

7:3

1:0

7:3

1:0

Field name

GPIO_SELECT

RESERVED

GPIO_MODE

GPIO_SELECT

RESERVED

GPIO_MODE

GPIO_SELECT

RESERVED

GPIO_MODE

GPIO_SELECT

RESERVED

GPIO_MODE

Description

•

Specify the GPIO0

I/O signal, default setting POR (see

GPIO0 Mode:

01b: Digital input

10b: Digital output low power

11b: Digital output high power

Specify the GPIO1 I/O signal, default setting digital GND (see

•

GPIO1 Mode:

01b: Digital input1

10b: Digital output low power

11b: Digital

Output High

Power

Specify the GPIO2 I/O signal, default setting digital GND (see

•

GPIO2 mMode:

01b: Digital input

10b: Digital output low power

11b: Digital output high power

Specify the GPIO3 I/O signal, default setting digital GND (see