STMicroelectronics M24LR04E-R Datasheet
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M24LR04E-R
UFDFPN8 (MC)
Dynamic NFC/RFID tag IC with 4-Kbit EEPROM,
energy harvesting, I²C bus and ISO 15693 RF interface
Datasheet
-
production data
SO8 (MN)
150 mils width
Wafer (SB12I)
TSSOP8 (DW)
Features
• Belonging to ST25 family, which includes all
NFC/RF ID tag and reader products from ST
I
2
C interface
• Two-wires I
2
C serial interface supports
400 kHz protocol
• Single supply voltage:
– 1.8 V to 5.5 V
• Byte and Page Write (up to 4 bytes)
• Random and Sequential read modes
• Self-timed programming cycle
• Automatic address incrementing
• Enhanced ESD/latch-up protection
• I²C timeout
Contactless interface
• ISO 15693 and ISO 18000-3 mode 1 compatible
• 13.56 MHz ± 7 kHz carrier frequency
• To tag: 10% or 100% ASK modulation using 1 out of 4 (26 Kbit/s) or 1 out of 256 (1.6 Kbit/s) pulse position coding
• From tag: load modulation using Manchester coding with 423 kHz and 484 kHz subcarriers in low (6.6 kbit/s) or high (26 kbit/s) data rate mode. Supports the 53 kbit/s data rate with
Fast commands
• Internal tuning capacitance: 27.5pF
• 64-bit unique identifier (UID)
• Read Block & Write (32-bit blocks)
Digital output pin
• User configurable pin: RF write in progress or
RF busy mode
Energy harvesting
• Analog pin for energy harvesting
• 4 sink current configurable ranges
Temperature range
• From –40 to 85 °C
Memory
• 4-Kbit EEPROM organized into:
– 512 bytes in I
2
C mode
– 128 blocks of 32 bits in RF mode
• Write time
– I
2
C: 5 ms (max.)
– RF: 5.75 ms including the internal Verify time
• Write cycling endurance:
– 1 million write cycles at 25 °C
– 150k write cycles at 85 °C
• More than 40-year data retention
• Multiple password protection in RF mode
• Single password protection in I
2
C mode
• Package
– SO8 (ECOPACK2 ® )
– TSSOP8 (ECOPACK2 ® )
– UFDFPN8 (ECOPACK2 ® )
July 2017
This is information on a product in full production.
DocID022208 Rev 11 1/146 www.st.com
Contents
Contents
M24LR04E-R
RF Write in progress / RF Busy (RF WIP/BUSY) . . . . . . . . . . . . . . . . . . . 15
Energy harvesting analog output (Vout) . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Antenna coil (AC0, AC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Device reset in RF mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
SS
ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Device reset in I²C mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
User memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
System memory area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
M24LR04E-R block security in RF mode . . . . . . . . . . . . . . . . . . . . . . . . . 23
Example of the M24LR04E-R security protection in RF mode . . . . . . . 25
M24LR04E-R block security in I²C mode (I2C_Write_Lock bit area) . . . . 26
Configuration byte and Control register . . . . . . . . . . . . . . . . . . . . . . . . . . 26
RF WIP/BUSY pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Energy harvesting configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
FIELD_ON indicator bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Configuration byte access in I²C and RF modes . . . . . . . . . . . . . . . . . . 29
Control register access in I²C or RF mode . . . . . . . . . . . . . . . . . . . . . . 29
ISO 15693 system parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
C device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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M24LR04E-R Contents
Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
I²C timeout on Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
I²C timeout on clock period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Minimizing system delays by polling on Ack . . . . . . . . . . . . . . . . . . . . . . 36
Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2 C password security . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2
C present password command description . . . . . . . . . . . . . . . . . . . . . 38
2 C write password command description . . . . . . . . . . . . . . . . . . . . . . . 39
M24LR04E-R memory initial state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
RF communication and energy harvesting . . . . . . . . . . . . . . . . . . . . . . . . 41
Initial dialog for vicinity cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Communication signal from VCD to M24LR04E-R . . . . . . . . . . . . . . . . 44
Data rate and data coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Data coding mode: 1 out of 256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Data coding mode: 1 out of 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
VCD to M24LR04E-R frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
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7
Contents
M24LR04E-R
Communication signal from M24LR04E-R to VCD . . . . . . . . . . . . . . . . 50
Load modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Data rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Bit representation and coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Bit coding using one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Bit coding using two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
M24LR04E-R to VCD frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
SOF when using one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
SOF when using two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
EOF when using one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
EOF when using two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Application family identifier (AFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Data storage format identifier (DSFID) . . . . . . . . . . . . . . . . . . . . . . . . . 60
CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
M24LR04E-R protocol description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
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M24LR04E-R
Contents
Addressed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Non-addressed mode (general request) . . . . . . . . . . . . . . . . . . . . . . . . . 65
Select mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Request processing by the M24LR04E-R . . . . . . . . . . . . . . . . . . . . . . . 72
Explanation of the possible cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Inventory Initiated command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
t1: M24LR04E-R response delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
t2: VCD new request delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
: VCD new request delay when no response is received from the M24LR04E-R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
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Contents M24LR04E-R
C DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
RF electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
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M24LR04E-R Contents
SO8N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
UFDFN8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
TSSOP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Appendix A Anticollision algorithm (informative) . . . . . . . . . . . . . . . . . . . . . . . 139
Algorithm for pulsed slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
CRC error detection method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
CRC calculation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Appendix C Application family identifier (AFI) (informative) . . . . . . . . . . . . . . 143
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List of tables
List of tables
M24LR04E-R
M24LR04E-R sector security protection after a valid presentation of password 1 . . . . . . . 25
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M24LR04E-R List of tables
Get System Info response format when Protocol_extension_flag = 0 and
Get Multiple Block Security Status response format when Error_flag is NOT set . . . . . . . 98
Get Multiple Block Security Status response format when Error_flag is set . . . . . . . . . . . . 99
Write-sector Password response format when Error_flag is NOT set . . . . . . . . . . . . . . . 100
Present-sector Password response format when Error_flag is NOT set . . . . . . . . . . . . . 103
Fast Read Single Block response format when Error_flag is NOT set . . . . . . . . . . . . . . . 105
Fast Read Multiple Block response format when Error_flag is NOT set. . . . . . . . . . . . . . 109
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10
List of tables M24LR04E-R
2 C operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
2
2
C DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
C AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
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M24LR04E-R
List of figures
List of figures
2
2
C Fast mode (f
C
= 400 kHz): maximum R bus
value vs. bus parasitic capacitance (C bus
) 17
C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Write mode sequences with I2C_Write_Lock bit = 1 (data write inhibited). . . . . . . . . . . . . 33
Write mode sequences with I2C_Write_Lock bit = 0 (data write enabled) . . . . . . . . . . . . . 35
2
2
C present password command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
C write password command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
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List of figures M24LR04E-R
Principle of comparison between the mask, the slot number and the UID . . . . . . . . . . . . . 71
M24LR04E-R RF-Busy management following Inventory command . . . . . . . . . . . . . . . . . 79
Stay Quiet frame exchange between VCD and M24LR04E-R . . . . . . . . . . . . . . . . . . . . . . 80
Read Single Block frame exchange between VCD and M24LR04E-R. . . . . . . . . . . . . . . . 82
Write Single Block frame exchange between VCD and M24LR04E-R . . . . . . . . . . . . . . . . 83
M24LR04E-R RF_Busy management following Write command . . . . . . . . . . . . . . . . . . . . 84
M24LR04E RF_Wip management following Write command. . . . . . . . . . . . . . . . . . . . . . . 85
Read Multiple Block frame exchange between VCD and M24LR04E-R . . . . . . . . . . . . . . 87
Reset to Ready frame exchange between VCD and M24LR04E-R . . . . . . . . . . . . . . . . . . 89
Write AFI frame exchange between VCD and M24LR04E-R . . . . . . . . . . . . . . . . . . . . . . . 91
Lock AFI frame exchange between VCD and M24LR04E-R . . . . . . . . . . . . . . . . . . . . . . . 92
Write DSFID frame exchange between VCD and M24LR04E-R . . . . . . . . . . . . . . . . . . . . 94
Lock DSFID frame exchange between VCD and M24LR04E-R. . . . . . . . . . . . . . . . . . . . . 95
Get System Info frame exchange between VCD and M24LR04E-R . . . . . . . . . . . . . . . . . 97
Get Multiple Block Security Status frame exchange between VCD and M24LR04E-R . . . 99
Write-sector Password frame exchange between VCD and M24LR04E-R . . . . . . . . . . . 100
Lock-sector frame exchange between VCD and M24LR04E-R . . . . . . . . . . . . . . . . . . . . 102
Present-sector Password frame exchange between VCD and M24LR04E-R . . . . . . . . . 104
Fast Read Single Block frame exchange between VCD and M24LR04E-R. . . . . . . . . . . 106
Fast Initiate frame exchange between VCD and M24LR04E-R . . . . . . . . . . . . . . . . . . . . 108
Fast Read Multiple Block frame exchange between VCD and M24LR04E-R . . . . . . . . . 110
ReadCfg frame exchange between VCD and M24LR04E-R . . . . . . . . . . . . . . . . . . . . . . 113
WriteEHCfg frame exchange between VCD and M24LR04E-R . . . . . . . . . . . . . . . . . . . . 115
WriteDOCfg frame exchange between VCD and M24LR04E-R. . . . . . . . . . . . . . . . . . . . 116
SetRstEHEn frame exchange between VCD and M24LR04E-R . . . . . . . . . . . . . . . . . . . 118
CheckEHEn frame exchange between VCD and M24LR04E-R. . . . . . . . . . . . . . . . . . . . 119
2 C AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . 132
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M24LR04E-R
1 Description
Description
The M24LR04E-R device is a Dynamic NFC/RFID tag IC with a dual-interface, electrically erasable programmable memory (EEPROM). The logic scheme is shown in
.
It features an I 2 C interface and can be operated from a V
CC
power supply. It is also a contactless memory powered by the received carrier electromagnetic wave. The
M24LR04E-R is organized as 512 × 8 bits in the I 2 C mode and as 128 × 32 bits in RF mode.
The M24LR04E-R also features an energy harvesting analog output, as well as a userconfigurable digital output pin toggling during either RF write in progress or RF busy mode.
Figure 1. Logic diagram
9
&&
6&/
6'$
9
RXW
0/5(5
$&
$&
5):,3%86<
9
66
069
I
2
C uses a two-wire serial interface, comprising a bidirectional data line and a clock line. The devices carry a built-in 4-bit device type identifier code (1010) in accordance with the I
2
C bus definition.
The device behaves as a slave in the I
2
C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a Start condition, generated by the bus master. The Start condition is followed by a device select code and Read/Write bit (RW) (as described in
), terminated by an acknowledge bit.
When writing data to the memory, the device inserts an acknowledge bit during the 9 th
bit time, following the bus master’s 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.
In the ISO15693/ISO18000-3 mode 1 RF mode, the M24LR04E-R is accessed via the
13.56 MHz carrier electromagnetic wave on which incoming data are demodulated from the received signal amplitude modulation (ASK: amplitude shift keying). When connected to an antenna, the operating power is derived from the RF energy and no external power supply is required. The received ASK wave is 10% or 100% modulated with a data rate of 1.6 Kbit/s using the 1/256 pulse coding mode or a data rate of 26 Kbit/s using the 1/4 pulse coding mode.
Outgoing data are generated by the M24LR04E-R load variation using Manchester coding with one or two subcarrier frequencies at 423 kHz and 484 kHz. Data are transferred from the M24LR04E-R at 6.6 Kbit/s in low data rate mode and 26 Kbit/s high data rate mode. The
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Description M24LR04E-R
M24LR04E-R supports the 53 Kbit/s fast mode in high data rate mode using one subcarrier frequency at 423 kHz.
The M24LR04E-R follows the ISO 15693 and ISO 18000-3 mode 1 recommendation for radio-frequency power and signal interface.
The M24LR04E-R provides an Energy harvesting mode on the analog output pin Vout.
When the Energy harvesting mode is activated, the M24LR04E-R can output the excess energy coming from the RF field on the Vout analog pin. In case the RF field strength is insufficient or when Energy harvesting mode is disabled, the analog output pin Vout goes into high-Z state and Energy harvesting mode is automatically stopped.
The M24LR04E-R features a user configurable digital out pin RF WIP/BUSY that can be used to drive a micro controller interrupt input pin (available only when the M24LR04E-R is correctly powered on the Vcc pin).
When configured in the RF write in progress mode (RF WIP mode), the RF WIP/BUSY pin is driven low for the entire duration of the RF internal write operation. When configured in the
RF busy mode (RF BUSY mode), the RF WIP/BUSY pin is driven low for the entire duration of the RF command progress.
The RF WIP/BUSY pin is an open drain output and must be connected to a pull-up resistor.
Signal name
Vout
SDA
SCL
AC0, AC1
V
CC
RF WIP/BUSY
V
SS
Table 1. Signal names
Function
Energy harvesting Output
Serial Data
Serial Clock
Antenna coils
Supply voltage
Digital signal
Ground
Direction
Analog output
I/O
Input
-
I/O
-
Digital output
Figure 2. 8-pin package connections
9
RXW
$&
$&
9
66
9
&&
5):,3%86<
6&/
6'$
1. See
Section 31 for package dimensions, and how to identify pin-1.
069
14/146 DocID022208 Rev 11
M24LR04E-R Signal descriptions
2.1
2.2
2.3
Serial clock (SCL)
This input signal is used to strobe all data in and out of the device. In applications where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor must be connected from Serial Clock
(SCL) to V
CC
. (
Figure 3 indicates how the value of the pull-up resistor can be calculated). In
most applications, though, this method of synchronization is not employed, and so the pullup resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output.
Serial data (SDA)
This bidirectional signal is used to transfer data in or out of the device. It is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from Serial Data (SDA) to V
CC the value of the pull-up resistor can be calculated).
. (
RF Write in progress / RF Busy (RF WIP/BUSY)
This configurable output signal is used either to indicate that the M24LR04E-R is executing an internal write cycle from the RF channel or that an RF command is in progress. RF WIP and signals are available only when the M24LR04E-R is powered by the Vcc pin. It is an open drain output and a pull up resistor must be connected from RF WIP/BUSY to V
CC
.
2.5
2.5.1
This analog output pin is used to deliver the analog voltage Vout available when the Energy harvesting mode is enabled and the RF field strength is sufficient. When the Energy harvesting mode is disabled or the RF field strength is not sufficient, the energy harvesting analog voltage output Vout is in high-Z state.
Antenna coil (AC0, AC1)
These inputs are used to connect the device to an external coil exclusively. It is advised not to connect any other DC or AC path to AC0 or AC1.
When correctly tuned, the coil is used to power and access the device using the ISO 15693 and ISO 18000-3 mode 1 protocols.
Device reset in RF mode
To ensure a proper reset of the RF circuitry, the RF field must be turned off (100% modulation) for a minimum t
RF_OFF
period of time.
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Signal descriptions M24LR04E-R
2.6 V
SS
ground
V
SS
is the reference for the V
CC
supply voltage and Vout analog output voltage.
2.7
Note:
2.7.1
Supply voltage (V
CC
)
This pin can be connected to an external DC supply voltage.
An internal voltage regulator allows the external voltage applied on V
CC
to supply the
M24LR04E-R, while preventing the internal power supply (rectified RF waveforms) to output a DC voltage on the V
CC
pin.
Operating supply voltage V
CC
Prior to selecting the memory and issuing instructions to it, a valid and stable V
CC within the specified [V
CC
(min), V
CC
(max)] range must be applied (see suitable capacitor (usually of the order of 10 nF) close to the V
CC
/V
SS
maintain a stable DC supply voltage, it is recommended to decouple the V
CC
voltage
line with a
package pins.
This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal I²C write cycle (t
W
).
2.7.3
When the power supply is turned on, V
CC vary faster than 1V/µs.
rises from V
SS
to V
CC
. The V
CC
rise time must not
Device reset in I²C mode
In order to prevent inadvertent write operations during power-up, a power-on reset (POR) circuit is included. At power-up (continuous rise of V
CC
I²C instruction until V
CC lower than the minimum V
CC
), the device does not respond to any
has reached the power-on reset threshold voltage (this threshold is
operating voltage defined in
). When V
CC
passes over the POR threshold, the device is reset and enters the Standby power mode. However, the device must not be accessed until V within the specified [V
CC
(min), V
CC
CC
has reached a valid and stable V
(max)] range.
CC
voltage
In a similar way, during power-down (continuous decrease in V
CC
), as soon as V
CC
drops below the power-on reset threshold voltage, the device stops responding to any instruction sent to it.
During power-down (continuous decay of V
CC
), the device must be in Standby power mode
(mode reached after decoding a Stop condition, assuming that there is no internal write cycle in progress).
16/146 DocID022208 Rev 11
M24LR04E-R Signal descriptions
Figure 3. I 2 C Fast mode ( f
C
= 400 kHz): maximum R bus
value vs. bus parasitic capacitance (C bus
)
K ½
2
BUS
(ERE2BUS§#BUSNS
§
#
BUS
NS
P&
"USLINECAPACITORP&
MUSTBEBELOWTHENS
TIMECONSTANTLINEREPRESENTED
ONTHELEFT
6
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2
BUS
)£#BUS
MASTER
3#,
3$!
#
BUS
-XXX
Figure 4. I
2
C bus protocol
AIB
DocID022208 Rev 11 17/146
145
Signal descriptions
Table 2. Device select code
Device type identifier
(1)
Chip Enable address RW
-
Device select code b7
1 b6
0 b5
1 b4
0 b3
E2 (2) b2
1 b1
1 b0
RW
1. The most significant bit, b7, is sent first.
2. E2 is not connected to any external pin. It is however used to address the M24LR04E-R as described in
b15 b14
Table 3. Address most significant byte
b13 b12 b11 b10 b9 b8 b7 b6
Table 4. Address least significant byte
b5 b4 b3 b2 b1
M24LR04E-R
b0
18/146 DocID022208 Rev 11
M24LR04E-R
3 User memory organization
User memory organization
The M24LR04E-R is divided into four sectors of 32 blocks of 32 bits, as shown in
.
Figure 6 shows the memory sector organization. Each sector can be individually read-
and/or write-protected using a specific password command. Read and write operations are possible if the addressed data are not in a protected sector.
The M24LR04E-R also has a 64-bit block that is used to store the 64-bit unique identifier
(UID). The UID is compliant with the ISO 15963 description, and its value is used during the anticollision sequence (Inventory). This block is not accessible by the user in RF device operation and its value is written by ST on the production line.
The M24LR04E-R includes an AFI register that stores the application family identifier, and a
DSFID register that stores the data storage family identifier used in the anticollision algorithm.
The M24LR04E-R has four 32-bit blocks that store an I 2 C password plus three RF password codes.
Figure 5. Circuit diagram
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DocID022208 Rev 11 19/146
145
User memory organization
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Figure 6. Memory sector organization
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Sector details
The M24LR04E-R user memory is divided into four sectors. Each sector contains 1024 bits.
The protection scheme is described in
Section 4: System memory area .
In RF mode, a sector provides 32 blocks of 32 bits. Each read and write access is done by block. Read and write block accesses are controlled by a Sector Security Status byte that defines the access rights to the 32 blocks contained in the sector. If the sector is not protected, a Write command updates the complete 32 bits of the selected block.
In I 2 C mode, a sector provides 128 bytes that can be individually accessed in Read and
Write modes. When protected by the corresponding I2C_Write_Lock bit, the entire sector is write-protected. To access the user memory, the device select code used for any I 2 C command must have the E2 Chip Enable address at 0.
20/146 DocID022208 Rev 11
M24LR04E-R User memory organization
Sector number
0
RF block address
28
29
30
31
24
25
26
27
20
21
22
23
16
17
18
19
12
13
14
15
10
11
8
9
6
7
4
5
2
3
0
1
Table 5. Sector details
I
2
C byte address
Bits [31:24] Bits [23:16] Bits [15:8]
112
116
120
124
96
100
104
108
80
84
88
92
64
68
72
76
48
52
56
60
32
36
40
44
16
20
24
28
8
12
0
4 user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user
Bits [7:0] user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user
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User memory organization M24LR04E-R
Sector number
1
2
3
RF block address
36
37
38
39
32
33
34
35
...
...
...
127
Table 5. Sector details (continued)
I
2
C byte address
Bits [31:24] Bits [23:16] Bits [15:8]
144
148
152
156
128
132
136
140
...
...
...
508 user user user user user user user user
...
...
...
user user user user user user user user user
...
...
...
user user user user user user user user user
...
...
...
user
Bits [7:0] user user user user user user user user
...
...
...
user
22/146 DocID022208 Rev 11
M24LR04E-R
4 System memory area
System memory area
The M24LR04E-R provides a special protection mechanism based on passwords. In RF mode, each memory sector of the M24LR04E-R can be individually protected by one out of three available passwords, and each sector can also have Read/Write access conditions set.
Each memory sector of the M24LR04E-R is assigned with a Sector security status byte including a Sector Lock bit, two Password Control bits and two Read/Write protection bits,
Table 6 describes the organization of the Sector security status byte, which can be read
using the Read Single Block and Read Multiple Block commands with the Option_flag set to 1.
On delivery, the default value of the SSS bytes is set to 00h.
I
2
C byte address
Table 6. Sector security status byte area
Bits [31:24] Bits [23:16] Bits [15:8]
E2 = 1 0 SSS 3 SSS 2 SSS 1
Bits [7:0]
SSS 0 b
7
0 b
6
0
Table 7. Sector security status byte organization b
5
0 b
4 b
3
Password control bits b
2 b
1
Read / Write protection bits b
0
Sector
Lock
When the Sector Lock bit is set to 1, for instance by issuing a Lock-sector command, the two Read/Write protection bits (b
1 as described in
, b
2
) are used to set the Read/Write access of the sector
Sector
Lock
0
1
1
1
1 b
2
, b
1 xx
00
01
10
11
Table 8. Read / Write protection bit setting
Sector access when password presented
Sector access when password not presented
Read
Read
Read
Read
Read
Write
Write
Write
Write
No Write
Read
Read
Read
No Read
No Read
Write
No Write
Write
No Write
No Write
The next two bits of the Sector security status byte (b
3
, b
4
) are the password control bits.
The value of these two bits is used to link a password to the sector, as defined in Table 9 .
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System memory area M24LR04E-R b
4
, b
3
00
01
10
11
Table 9. Password control bits
Password
The sector is not protected by a password.
The sector is protected by password 1.
The sector is protected by password 2.
The sector is protected by password 3.
The M24LR04E-R password protection is organized around a dedicated set of commands, plus a system area of three password blocks where the password values are stored. This system area is described in
1
2
3
Table 10. Password system area
Add
Password 1
Password 2
Password 3
The dedicated commands for protection in RF mode are:
• Write-sector password:
The Write-sector password command is used to write a 32-bit block into the password system area. This command must be used to update password values. After the write cycle, the new password value is automatically activated. It is possible to modify a password value after issuing a valid Present-sector password command. On delivery, the three default password values are set to 0000 0000h and are activated.
• Lock-sector:
The Lock-sector command is used to set the sector security status byte of the selected sector. Bits b
4
to b
1
of the sector security status byte are affected by the Lock-sector command. The sector lock bit, b
0
, is set to 1 automatically. After issuing a Lock-sector command, the protection settings of the selected sector are activated. The protection of a locked block cannot be changed in RF mode. A Lock-sector command sent to a locked sector returns an error code.
24/146 DocID022208 Rev 11
M24LR04E-R
4.1.1
System memory area
• Present-sector password:
The Present-sector password command is used to present one of the three passwords to the M24LR04E-R in order to modify the access rights of all the memory sectors
linked to that password ( Table 8 ) including the password itself. If the presented
password is correct, the access rights remain activated until the tag is powered off or until a new Present-sector password command is issued. If the presented password value is not correct, all the access rights of all the memory sectors are deactivated.
• Sector security status byte area access conditions in I2C mode:
In I
2
C mode, read access to the sector security status byte area is always allowed.
Write access depends on the correct presentation of the I
2
C password (see
Section 5.16.1: I2C present password command description
).
To access the Sector security status byte area, the device select code used for any I 2 C command must have the E2 Chip Enable address at 1.
An I
2
C write access to a sector security status byte re-initializes the RF access condition to the given memory sector.
Example of the M24LR04E-R security protection in RF mode
show the sector security protections before and after a valid
Present-sector password command.
Table 11 shows the sector access rights of an
M24LR04E-R after power-up. After a valid Present-sector password command with password 1, the memory sector access is changed as shown in
0
1
2
3
4
Sector address
Table 11. M24LR04E-R sector security protection after power-up
Sector security status byte
Protection
Protection: standard Read No Write b
7 b
6 b
5 xxx b
4 b
3 b
2 b
1 b
0
0 0 0 0 1
Protection: password 1 Read
Protection: password 1 Read
Protection: password 1 No Read
Protection: password 1 No Read
No Write
Write
No Write
No Write xxx xxx xxx xxx
0 1 0 0 1
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
Table 12. M24LR04E-R sector security protection after a valid presentation of password 1
Sector security status byte
Sector address
Protection
0
1
2
3
4
Protection: standard Read
Protection: password 1 Read
Protection: password 1 Read
Protection: password 1 Read
Protection: password 1 Read
No Write
Write
Write
Write
No Write b
7 b
6 b
5 xxx xxx xxx xxx xxx b
4 b
3 b
2 b
1 b
0
0 0 0 0 1
0 1 0 0 1
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
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System memory area M24LR04E-R
area)
In the I
2
C mode only, it is possible to protect individual sectors against Write operations.
This feature is controlled by the I2C_Write_Lock bits stored in the two bytes of the
I2C_Write_Lock bit area. I2C_Write_Lock bit area starts from location 2048 (see
To access the I2C_Write_Lock bit area, the device select code used for any I
2
C command must have the E2 Chip Enable address at 1.
Using these 16 bits, it is possible to write-protect all the four sectors of the M24LR04E-R memory. Each bit controls the I
2
C write access to a specific sector as shown in Table 13
. It is always possible to unprotect a sector in the I
2
C mode. When an I2C_Write_Lock bit is reset to 0, the corresponding sector is unprotected. When the bit is set to 1, the corresponding sector is write-protected.
In I
2
C mode, read access to the I2C_Write_Lock bit area is always allowed. Write access depends on the correct presentation of the I
2
C password.
On delivery, the default value of the two bytes of the I2C_Write_Lock bit area is reset to 00h.
I
2
C byte address
E2 = 1 2048
Table 13. I2C_Write_Lock bit
Bits [4:15]
Don’t care
Bits [3:0]
Sectors 0-3
4.3 Configuration and Control register
The M24LR04E-R offers an 8-bit non-volatile Configuration byte located at I²C location 2320 of the system area used to store the RF WIP/BUSY pin and the energy harvesting
).
The M24LR04E-R also offers an 8-bit volatile Control register located at I²C location 2336 of the system area used to store the energy harvesting enable bit as well as a FIELD_ON bit
).
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The M24LR04E-R features a configurable open drain output RF WIP/BUSY pin used to provide RF activity information to an external device.
The RF WIP/BUSY pin functionality depends on the value of bit 3 of the Configuration byte.
• RF busy mode
When bit 3 of the Configuration byte is set to 0, the RF WIP/BUSY pin is configured in RF busy mode.
The purpose of this mode is to indicate to the I²C bus master whether the M24LR04E-R is busy in RF mode or not.
In this mode, the RF WIP/BUSY pin is tied to 0 from the RF command Start Of Frame (SOF) until the end of the command execution.
If a bad RF command is received, the RF WIP/BUSY pin is tied to 0 from the RF command
SOF until the reception of the RF command CRC. Otherwise, the RF WIP/BUSY pin is in high-Z state.
DocID022208 Rev 11
M24LR04E-R System memory area
When tied to 0, the RF WIP/BUSY signal returns to high-Z state if the RF field is cut-off.
During execution of I²C commands, the RF WIP/BUSY pin remains in high-Z state.
• RF Write in progress
When bit 3 of the Configuration byte is set to 1, the RF WIP/BUSY pin is configured in RF
Write in progress mode.
The purpose of this mode is to indicate to the I²C bus master that some data have been changed in RF mode.
In this mode, the RF WIP/BUSY pin is tied to 0 for the duration of an internal write operation
(i.e. between the end of a valid RF write command and the beginning of the RF answer).
During execution of I²C write operations, the RF WIP/BUSY pin remains in high-Z state.
The M24LR04E-R features an Energy harvesting mode on the Vout analog output.
The general purpose of the Energy harvesting mode is to deliver a part of the nonnecessary RF power received by the M24LR04E-R on the AC0-AC1 RF input in order to supply an external device. The current consumption on the analog voltage output Vout is limited to ensure that the M24LR04E-R is correctly supplied during the powering of the external device.
When the Energy harvesting mode is enabled and the power delivered on the AC0-AC1 RF input exceeds the minimum required P
AC0-AC1_min
, the M24LR04E-R is able to deliver a limited and unregulated voltage on the Vout pin, assuming the current consumption on the
Vout does not exceed the I sink_max
maximum value.
If one of the condition above is not met, the analog voltage output pin Vout is set in high-Z state.
For robust applications using the Energy harvesting mode, four current fan-out levels can be chosen.
• Vout sink current configuration
The sink current level is chosen by programming EH_cfg1 and EH_cfg0 into the
Configuration byte (see Table 14
).
The minimum power level required on AC0-AC1 RF input P
AC0-AC1_min voltage Vout, as well as the maximum current consumption I sink_max
, the delivered
on the Vout pin corresponding to the <EH_cfg1,EH_cfg0> bit values are described in
.
Table 14. Configuration byte
I
2
C byte address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
E2=1 2320 X (1) X (1) X (1) X (1) RF WIP/BUSY
Bit 2 BIT 1 BIT 0
EH_mode EH_cfg1 EH_cfg0
1. Bit 7 to Bit 4 are don’t care bits.
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System memory area M24LR04E-R
• Energy harvesting enable control
Delivery of Energy harvesting analog output voltage on the Vout pin depends on the value of the EH_enable bit of the volatile Control register (see
I 2 C byte address
E2=1 2336
Bit 7
T-Prog
(1)
1. Bit 7 to Bit 1 are read-only bits.
Table 15. Control register
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
0
(1)
0
(1)
0
(1)
0
(1)
0
(1)
BIT 1
FIELD_ON
(1)
BIT 0
EH_enable
– When set to 1, the EH_enable bit enables the Energy harvesting mode, meaning that the Vout analog output signal is delivered when the P
AC0-AC1_min
and I sink_max conditions corresponding to the chosen sink current configuration bit are met (see
).
– When set to 0, the EH_enable bit disable the Energy harvesting mode and the analog output Vout remains in set in high-Z state.
– The T_Prog flag indicates a correct duration of the I²C write time (tw). This bit is reset to 0 after POR and at the beginning of each writing cycle; it is set to 1 only after a correct completion of the writing cycle.
• Energy harvesting default mode control
At power-up, in I²C or RF mode, the EH_enable bit is updated according to the value of the
EH_mode bit stored in the non-volatile Configuration byte (see Table 16
). In other words, the EH_mode bit is used to configure whether the Energy harvesting mode is enabled or not by default.
Table 16. EH_enable bit value after power-up
EH_mode value EH_enable after power-up
Energy harvesting after power-up
0
1
1
0 enabled disabled
4.3.3
Note:
FIELD_ON indicator bit
The FIELD_ON bit indicator located as Bit 1 of the Control register is a read-only bit used to indicate when the RF power level delivered to the M24LR04E-R is sufficient to execute RF commands.
• When FIELD_ON = 0, the M24LR04E-R is not able to execute any RF commands.
• When FIELD_ON =1, the M24LR04E-R is able to execute any RF commands.
During read access to the Control register in RF mode, the FIELD_ON bit is always read at 1.
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M24LR04E-R System memory area
In I²C mode, read and write accesses to the non-volatile Configuration byte are always allowed. To access the Configuration byte, the device select code used for any I²C command must have the E2 Chip enable address at 1.
The dedicated commands to access the Configuration byte in RF mode are:
• Read configuration byte command (ReadCfg):
The ReadCfg command is used to read the eight bits of the Configuration byte.
• Write energy harvesting configuration command (WriteEHCfg):
The WriteEHCfg command is used to write the EH_mode, EH_cfg1 and EH_cfg0 bits into the Configuration byte.
• Write RF WIP/BUSY pin configuration command (WriteDOCfg):
The WriteDOCfg command is used to write the RF WIP/BUSY bit into the Configuration byte.
After any write access to the Configuration byte, the new configuration is automatically applied.
In I²C mode, read and write accesses to the volatile Control register are always allowed. To access the Control register, the device select code used for any I²C command must have the E2 Chip enable address at 1.
The dedicated commands to access the Control register in RF mode are:
• Check energy harvesting enable bit command (CheckEHEn):
The CheckEHEn command is used to read the eight bits of the Control register. When it is run, the FIELD_ON bit is always read at 1.
• Set/reset energy harvesting enable bit command (SetRstEHEn):
The SetRstEHEn command is used to set or reset the value of the EH_enable bit into the
Control register.
The M24LR04E-R provides the system area required by the ISO 15693 RF protocol, as
.
The first 32-bit block starting from I 2 C address 2304 stores the I 2 C password. This password is used to activate/deactivate the write protection of the protected sector in I 2 C mode. At power-on, all user memory sectors protected by the I2C_Write_Lock bits can be read but cannot be modified. To remove the write protection, it is necessary to use the I 2 C present password described in
. When the password is correctly presented — that is, when all the presented bits correspond to the stored ones — it is also possible to modify the I 2
C password using the I2C write password command described in Figure 13 .
The next three 32-bit blocks store the three RF passwords. These passwords are neither read- nor write- accessible in the I 2 C mode.
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System memory area M24LR04E-R
The next byte stores the Configuration byte, at I²C location 2320. This Control register is used to store the three energy harvesting configuration bits and the RF WIP/BUSY configuration bit.
The next two bytes are used to store the AFI, at I 2 C location 2322, and the DSFID, at I 2 C location 2323. These two values are used during the RF inventory sequence. They are read-only in the I 2 C mode.
The next eight bytes, starting from location 2324, store the 64-bit UID programmed by ST on the production line. Bytes at I 2 C locations 2332 to 2335 store the IC Ref and the Mem_Size data used by the RF Get_System_Info command. The UID, Mem_Size and IC ref values are read-only data.
Table 17. System parameter sector
I 2 C byte address Bits [31:24] Bits [23:16] Bits [15:8] Bits [7:0]
E2 = 1
E2 = 1
E2 = 1
E2 = 1
E2 = 1
E2 = 1
2304 I
2
C password
(1)
2308
2312
RF password 1 (1)
RF password 2
(1)
2316 RF password 3
(1)
2320 DSFID (FFh) AFI (00h) ST reserved (Exh)
(2)
2324 UID UID UID
Configuration byte (F4h)
UID
E2 = 1
E2 = 1
2328
2332
UID (E0h)
RFU
(FFh)
UID (02h)
Mem_Size
(03 7F)
UID
-
UID
IC Ref (5A)
E2 = 1 2336 -
Programming. completion and
Energy harvesting status
(3)
1. Delivery state: I 2 C password= 0000 0000h, RF password = 0000 0000h, Configuration byte = F4h
2. The product revision is the Most significant nibble of the byte located at address 0x911 (2321 d) in the system area (Device select code E2 =1). From Rev 6, the product revision value is 0xE. The Least significant nibble is ST reserved.
3. Address system 2336 (920h, E2=1) is the control register.
Bit 7 is T_Prog (refer to
). When accessed in RF, this bit is not significant and set to 0.
Bits 2-6 are RFU and set to 0.
Bit 1 is FIELD_ON (refer to
Bit 0 is EH_enable (refer to
).
).
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M24LR04E-R
5 I
2
C device operation
I 2 C device operation
The device supports the I 2 C protocol. This is summarized in
Figure 4 . Any device that sends
data to the bus is defined as a transmitter, and any device that reads data is defined as a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which also provides the serial clock for synchronization. The M24LR04E-R device is a slave in all communications.
Start is identified by a falling edge of serial data (SDA) while the serial clock (SCL) is stable in the high state. A Start condition must precede any data transfer command. The device continuously monitors (except during a write cycle) the SDA and the SCL for a Start condition, and does not respond unless one is given.
5.3
Stop is identified by a rising edge of serial data (SDA) while the serial clock (SCL) is stable and driven high. A Stop condition terminates communication between the device and the bus master. A Read command that is followed by NoAck can be followed by a Stop condition to force the device into the Standby mode. A Stop condition at the end of a Write command triggers the internal write cycle.
Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases the serial data (SDA) after sending eight bits of data. During the 9 th
clock pulse period, the receiver pulls the SDA low to acknowledge the receipt of the eight data bits.
During data input, the device samples serial data (SDA) on the rising edge of the serial clock
(SCL). For correct device operation, the SDA must be stable during the rising edge of the
SCL, and the SDA signal must change only when the SCL is driven low.
During the execution of an I²C operation, RF communications are not possible.
To prevent RF communication freezing due to inadvertent unterminated instructions sent to the I²C bus, the M24LR04E-R features a timeout mechanism that automatically resets the
I²C logic block.
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I 2 C device operation M24LR04E-R
I²C communication with the M24LR04E-R starts with a valid Start condition, followed by a device select code.
If the delay between the Start condition and the following rising edge of the Serial Clock
(SCL) that samples the most significant of the Device Select exceeds the t
START_OUT
time
(see Table 122 ), the I²C logic block is reset and further incoming data transfer is ignored
until the next valid Start Condition.
Figure 7. I²C timeout on Start condition
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I²C timeout on clock period
During data transfer on the I²C bus, the serial clock high pulse width High ( t
CHCL clock pulse width Low ( t
CLCH
) exceeds the maximum value specified in
) or serial
logic block is reset and any further incoming data transfer is ignored until the next valid Start condition.
To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the device select code (shown in
) on SDA, most significant bit first).
Only one memory device can be connected on a single I²C bus. In M24LR04E-R, E1 and E0 are internally set to 1.
The eighth bit is the Read/Write bit (RW). It is set to 1 for Read and to 0 for Write operations.
If a match occurs on the device select code, the corresponding device gives an acknowledgment on serial data (SDA) during the ninth bit time. If the device does not match the device select code, it deselects itself from the bus, and goes into Standby mode.
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M24LR04E-R I 2 C device operation
Mode
Current address read
Random address read
Sequential read
Byte write
Page write
1
1
1
0
0
0
Table 18. Operating modes
RW bit Bytes
1
1
≥ 1
1
≤ 4 bytes
Initial sequence
Start, device select, RW = 1
Start, device select, RW = 0, address reStart, device select, RW = 1
Similar to current or random address read
Start, device select, RW = 0
Start, device select, RW = 0
Figure 8. Write mode sequences with I2C_Write_Lock bit = 1 (data write inhibited)
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I 2 C device operation M24LR04E-R
Following a Start condition, the bus master sends a device select code with the Read/Write
bit (RW) reset to 0. The device acknowledges this, as shown in Figure 8
, and waits for two address bytes. The device responds to each address byte with an acknowledge bit, and then waits for the data byte.
Writing to the memory may be inhibited if the I2C_Write_Lock bit = 1. A Write instruction issued with the I2C_Write_Lock bit = 1 and with no I2C_Password presented does not modify the memory contents, and the accompanying data bytes are not acknowledged, as
.
Each data byte in the memory has a 16-bit (two byte wide) address. The most significant byte (
Table 3 ) is sent first, followed by the least significant byte ( Table 4
). Bits b15 to b0 form the address of the byte in memory.
When the bus master generates a Stop condition immediately after the Ack bit (in the tenthbit time slot), either at the end of a byte write or a page write, the internal write cycle is triggered. A Stop condition at any other time slot does not trigger the internal write cycle.
After the Stop condition, the delay t
W
, and the successful completion of a Write operation, the device’s internal address counter is incremented automatically, to point to the next byte address after the last one that was modified.
During the internal write cycle, the serial data (SDA) signal is disabled internally, and the device does not respond to any requests.
After the device select code and the address bytes, the bus master sends one data byte. If the addressed location is write-protected by the I2C_Write_Lock bit (= 1), the device replies with NoAck, and the location is not modified. If the addressed location is not write-protected, the device replies with Ack. The bus master terminates the transfer by generating a Stop condition, as shown in
The Page write mode allows up to four bytes to be written in a single write cycle, provided that they are all located in the same “row” in the memory: that is, the most significant memory address bits (b12-b2) are the same. If more bytes are sent than fit up to the end of the row, a condition known as “roll-over” occurs. This should be avoided, as data starts to become overwritten in an implementation-dependent way.
The bus master sends from one to four bytes of data, each of which is acknowledged by the device if the I2C_Write_Lock bit = 0 or the I2C_Password was correctly presented. If the
I2C_Write_Lock_bit = 1 and the I2C_password are not presented, the contents of the addressed memory location are not modified, and each data byte is followed by a NoAck.
After each byte is transferred, the internal byte address counter (inside the page) is incremented. The transfer is terminated by the bus master generating a Stop condition.
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M24LR04E-R I 2 C device operation
Figure 9. Write mode sequences with I2C_Write_Lock bit = 0 (data write enabled)
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I 2 C device operation M24LR04E-R
5.10 Minimizing system delays by polling on Ack
During the internal write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. The maximum I²C write time (t w
) is
shown in Table 122 , but the typical time is shorter. To make use of this, a polling sequence
can be used by the bus master.
The sequence, as shown in
1. Initial condition: a write cycle is in progress.
2. Step 1: the bus master issues a Start condition followed by a device select code (the first byte of the new instruction).
3. Step 2: if the device is busy with the internal write cycle, no Ack is returned and the bus master goes back to Step 1. If the device has terminated the internal write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1).
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1. The seven most significant bits of the device select code of a random read (in the first and fourth bytes) must be identical.
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M24LR04E-R I 2 C device operation
Read operations are performed independently of the state of the I2C_Write_Lock bit.
After the successful completion of a read operation, the device’s internal address counter is incremented by one, to point to the next byte address.
5.12 Random Address Read
A dummy write is first performed to load the address into this address counter (as shown in
) but without sending a Stop condition. Then, the bus master sends another Start condition, and repeats the device select code, with the Read/Write bit (RW) set to 1. The device acknowledges this, and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a Stop condition.
5.13 Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only sends a device select code with the Read/Write bit (RW) set to 1. The device acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master terminates the transfer with a Stop condition, as shown in
, without acknowledging the byte.
This operation can be used after a Current Address Read or a Random Address Read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in
The output data come from consecutive addresses, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter “rolls-over”, and the device continues to output data from memory address 00h.
5.15 Acknowledge in Read mode
For all Read commands, the device waits, after each byte read, for an acknowledgment during the ninth bit time. If the bus master does not drive Serial Data (SDA) low during this time, the device terminates the data transfer and switches to its Standby mode.
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I 2 C device operation M24LR04E-R
The M24LR04E-R controls I
2
C sector write access using the 32-bit-long I
2
C password and the 64-bit I2C_Write_Lock bit area. The I
2
C password value is managed using two I
2
C commands: I
2
C present password and I
2
C write password.
5.16.1 I
2
C present password command description
The I 2 C present password command is used in I 2 C mode to present the password to the
M24LR04E-R in order to modify the write access rights of all the memory sectors protected by the I2C_Write_Lock bits, including the password itself. If the presented password is correct, the access rights remain activated until the M24LR04E-R is powered off or until a new I 2 C present password command is issued.
Following a Start condition, the bus master sends a device select code with the Read/Write bit (RW) reset to 0 and the Chip Enable bit E2 at 1. The device acknowledges this, as shown in
, and waits for two I 2 C password address bytes 09h and 00h. The device responds to each address byte with an acknowledge bit, and then waits for the four password data bytes, the validation code, 09h, and a resend of the four password data bytes. The most significant byte of the password is sent first, followed by the least significant bytes.
It is necessary to send the 32-bit password twice to prevent any data corruption during the sequence. If the two 32-bit passwords sent are not exactly the same, the M24LR04E-R does not start the internal comparison.
When the bus master generates a Stop condition immediately after the Ack bit (during the tenth bit time slot), an internal delay equivalent to the write cycle time is triggered. A Stop condition at any other time does not trigger the internal delay. During that delay, the
M24LR04E-R compares the 32 received data bits with the 32 bits of the stored I 2 C password. If the values match, the write access rights to all protected sectors are modified after the internal delay. If the values do not match, the protected sectors remains protected.
During the internal delay, the serial data (SDA) signal is disabled internally, and the device does not respond to any requests.
Figure 12. I 2 C present password command
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5.16.2 I
2
C write password command description
The I 2 C write password command is used to write a 32-bit block into the M24LR04E-R I 2 C password system area. This command is used in I 2 C mode to update the I 2 C password
I value. It cannot be used to update any of the RF passwords. After the write cycle, the new
2 C password value is automatically activated. The I 2 after issuing a valid I 2 C present password command.
C password value can only be modified
On delivery, the I 2 C default password value is set to 0000 0000h and is activated.
Following a Start condition, the bus master sends a device select code with the Read/Write bit (RW) reset to 0 and the Chip Enable bit E2 at 1. The device acknowledges this, as shown in
, and waits for the two I 2 C password address bytes, 09h and 00h. The device responds to each address byte with an acknowledge bit, and then waits for the four password data bytes, the validation code, 07h, and a resend of the four password data bytes. The most significant byte of the password is sent first, followed by the least significant bytes.
It is necessary to send twice the 32-bit password to prevent any data corruption during the write sequence. If the two 32-bit passwords sent are not exactly the same, the
M24LR04E-R does not modify the I 2 C password value.
When the bus master generates a Stop condition immediately after the Ack bit (during the tenth bit time slot), the internal write cycle is triggered. A Stop condition at any other time does not trigger the internal write cycle.
During the internal write cycle, the serial data (SDA) signal is disabled internally, and the device does not respond to any requests.
Figure 13. I 2 C write password command
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M24LR04E-R memory initial state
6 M24LR04E-R memory initial state
The device is delivered with all bits set to 1 in the user memory array.
• User Memory content: FFh
• System bits delivery
• I2C write lock bits: 00h
• Sector Security Status: 00h
• I2C Password: 0000 0000h
• RF Password: 0000 0000h
• IC ref: 5Ah
• UID: E0 02 xx xx xx xxh
• DSFID: FFh
• AFI: 00h
• Memory size: 03 7Fh
• Energy Harvesting Configuration byte: F4h
• Bit 7 to bit 4: all set to 1
• Bit 3: set to 0 (RF BUSY mode on RF WIP/BUSY pin)
• Bit 2: set to 1 (Energy harvesting not activated by default)
• Bit 1 and bit 0: set to 0 (fan-out setting)
M24LR04E-R
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7 RF device operation
RF device operation
The M24LR04E-R is divided into four sectors of 32 blocks of 32 bits, as shown in
.
Each sector can be individually read- and/or write-protected using a specific lock or password command.
Read and Write operations are possible if the addressed block is not protected. During a
Write, the 32 bits of the block are replaced by the new 32-bit value.
The M24LR04E-R also has a 64-bit block that is used to store the 64-bit unique identifier
(UID). The UID is compliant with the ISO 15963 description, and its value is used during the anticollision sequence (Inventory). This block is not accessible by the user in RF device operation and its value is written by ST on the production line.
The M24LR04E-R also includes an AFI register in which the application family identifier is stored, and a DSFID register in which the data storage family identifier used in the anticollision algorithm is stored.
The M24LR04E-R has three 32-bit blocks in which the password codes are stored and a 8bit Configuration byte in which the Energy harvesting mode and RF WIP/BUSY pin configuration is stored.
Because current consumption can affect the AC signal delivered by the antenna, RF communications with M24LR04E-R are not guaranteed during voltage delivery on the energy harvesting analog output Vout.
RF communication can disturb and possibly stop Energy Harvesting mode.
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RF device operation M24LR04E-R
7.2 Commands
The M24LR04E-R supports the following commands:
• Inventory , used to perform the anticollision sequence.
• Stay quiet , used to put the M24LR04E-R in quiet mode, where it does not respond to any inventory command.
• Select , used to select the M24LR04E-R. After this command, the M24LR04E-R processes all Read/Write commands with Select_flag set.
• Reset to ready , used to put the M24LR04E-R in the ready state.
• Read block , used to output the 32 bits of the selected block and its locking status.
• Write block , used to write the 32-bit value in the selected block, provided that it is not locked.
• Read multiple blocks , used to read the selected blocks and send back their value.
• Write AFI , used to write the 8-bit value in the AFI register.
• Lock AFI , used to lock the AFI register.
• Write DSFID , used to write the 8-bit value in the DSFID register.
• Lock DSFID , used to lock the DSFID register.
• Get system info , used to provide the system information value
• Get multiple block security status , used to send the security status of the selected block.
• Initiate , used to trigger the tag response to the Inventory initiated sequence.
• Inventory initiated , used to perform the anticollision sequence triggered by the Initiate command.
• Write-sector password , used to write the 32 bits of the selected password.
• Lock-sector , used to write the sector security status bits of the selected sector.
• Present-sector password , enables the user to present a password to unprotect the user blocks linked to this password.
• Fast initiate , used to trigger the tag response to the Inventory initiated sequence.
• Fast inventory initiated , used to perform the anticollision sequence triggered by the
Initiate command.
• Fast read single block , used to output the 32 bits of the selected block and its locking status.
• Fast read multiple blocks , used to read the selected blocks and send back their value.
• ReadCfg, used to read the 8-bit Configuration byte and send back its value.
• WriteEHCfg , used to write the energy harvesting configuration bits into the
Configuration byte.
• WriteDOCfg , used to write the RF WIP/BUSY pin configuration bit into the
Configuration byte.
• SetRstEHEn , used to set or reset the EH_enable bit into the volatile Control register.
• CheckEHEn , used to send back the value of the volatile Control register.
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7.3
RF device operation
Initial dialog for vicinity cards
The dialog between the vicinity coupling device or VCD (commonly the “RF reader”) and the vicinity integrated circuit card or VICC (M24LR04E-R) takes place as follows:
• activation of the M24LR04E-R by the RF operating field of the VCD,
• transmission of a command by the VCD,
• transmission of a response by the M24LR04E-R.
These operations use the RF power transfer and communication signal interface described below (see
and
). This technique is called RTF
(Reader talk first).
Power is transferred to the M24LR04E-R by radio frequency at 13.56 MHz via coupling antennas in the M24LR04E-R and the VCD. The RF operating field of the VCD is transformed on the M24LR04E-R antenna to an AC voltage which is rectified, filtered and internally regulated.
During communications, the amplitude modulation (ASK) on this received signal is demodulated by the ASK demodulator.
7.3.2 Frequency
The ISO 15693 standard defines the carrier frequency ( f
C
13.56 MHz ±7 kHz.
) of the operating field as
The M24LR04E-R operates continuously between the minimum and maximum values of the electromagnetic field H defined in
. The VCD has to generate a field within these limits.
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Communication signal from VCD to M24LR04E-R
8
M24LR04E-R
Communication signal from VCD to M24LR04E-R
Communications between the VCD and the M24LR04E-R takes place using the modulation principle of ASK (Amplitude shift keying). Two modulation indexes are used, 10% and
100%. The M24LR04E-R decodes both. The VCD determines which index is used.
The modulation index is defined as [a – b] / [a + b], where a and b are, respectively the peak signal amplitude and the minimum signal amplitude of the carrier frequency.
Depending on the choice made by the VCD, a “pause” is created as shown in Figure 14
and
.
The M24LR04E-R is operational for the 100% modulation index or for any degree of
modulation index between 10% and 30% (see Table 124
).
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Data rate and data coding
9 Data rate and data coding
M24LR04E-R
The data coding implemented in the M24LR04E-R uses pulse position modulation. Both data coding modes that are described in the ISO15693 are supported by the M24LR04E-R.
The selection is made by the VCD and indicated to the M24LR04E-R within the start of frame (SOF).
9.1
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The value of one single byte is represented by the position of one pause. The position of the pause on 1 of 256 successive time periods of 18.88 µs (256/ f
C
) determines the value of the byte. In this case, the transmission of one byte takes 4.833 ms and the resulting data rate is
1.65 Kbits/s ( f
C
/8192).
illustrates this pulse position modulation technique. In this figure, data E1h (225 decimal) is sent by the VCD to the M24LR04E-R.
The pause occurs during the second half of the position of the time period that determines
the value, as shown in Figure 17 .
A pause during the first period transmits the data value 00h. A pause during the last period transmits the data value FFh (255 decimal).
Figure 16. 1 out of 256 coding mode
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0ULSE
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Data rate and data coding
Figure 17. Detail of a time period
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Data coding mode: 1 out of 4
The value of two bits is represented by the position of one pause. The position of the pause on 1 of 4 successive time periods of 18.88 µs (256/ f
C
) determines the value of the two bits.
Four successive pairs of bits form a byte, where the least significant pair of bits is transmitted first.
In this case, the transmission of one byte takes 302.08 µs and the resulting data rate is
26.48 Kbits/s ( f
C
/512).
illustrates the 1 out of 4 pulse position technique and coding.
Figure 19 shows the transmission of E1h (225d - 1110 0001b) by the VCD.
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Data rate and data coding
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VCD to M24LR04E-R frames
Frames are delimited by a start of frame (SOF) and an end of frame (EOF). They are implemented using code violation. Unused options are reserved for future use.
The M24LR04E-R is ready to receive a new command frame from the VCD 311.5 µs after sending a response frame to the VCD.
The M24LR04E-R takes a power-up time of 0.1 ms after being activated by the powering field. After this delay, the M24LR04E-R is ready to receive a command frame from the VCD.
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M24LR04E-R
9.4
Data rate and data coding
Start of frame (SOF)
The SOF defines the data coding mode the VCD is to use for the following command frame.
The SOF sequence described in Figure 20
selects the 1 out of 256 data coding mode. The
SOF sequence described in Figure 21
selects the 1 out of 4 data coding mode. The EOF
sequence for either coding mode is described in Figure 22 .
Figure 20. SOF to select 1 out of 256 data coding mode
Figure 21. SOF to select 1 out of 4 data coding mode
Figure 22. EOF for either data coding mode
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Communication signal from M24LR04E-R to VCD
10
M24LR04E-R
Communication signal from M24LR04E-R to VCD
The M24LR04E-R has several modes defined for some parameters, owing to which it can operate in various noise environments and meet various application requirements.
The M24LR04E-R is capable of communication to the VCD via an inductive coupling area whereby the carrier is loaded to generate a subcarrier with frequency f
S generated by switching a load in the M24LR04E-R.
. The subcarrier is
The load-modulated amplitude received on the VCD antenna must be of at least 10 mV when measured as described in the test methods defined in International Standard
ISO10373-7.
10.2 Subcarrier
The M24LR04E-R supports the one-subcarrier and two-subcarrier response formats. These formats are selected by the VCD using the first bit in the protocol header. When one subcarrier is used, the frequency f
S1
of the subcarrier load modulation is 423.75 kHz ( f
When two subcarriers are used, the frequency f
S1 is 484.28 kHz ( f
C continuous phase relationship between f
S1
and f
is 423.75 kHz (
S2
.
f
C
C
/32).
/32), and frequency f
S2
/28). When using the two-subcarrier mode, the M24LR04E-R generates a
The M24LR04E-R can respond using the low or the high data rate format. The selection of the data rate is made by the VCD using the second bit in the protocol header. For fast commands, the selected data rate is multiplied by two.
Table 20 shows the different data
rates produced by the M24LR04E-R using the different response format combinations.
Low
High
Data rate
Standard commands
Fast commands
Standard commands
Fast commands
Table 20. Response data rates
One subcarrier
6.62 Kbit/s ( f c
/2048)
13.24 Kbit/s ( f c
/1024)
26.48 Kbit/s ( f c
/512)
52.97 Kbit/s ( f c
/256)
Two subcarriers
6.67 Kbit/s ( f c
/2032)
Not applicable
26.69 Kbit/s ( f c
/508)
Not applicable
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11 Bit representation and coding
Bit representation and coding
Data bits are encoded using Manchester coding, according to the following schemes. For the low data rate, same subcarrier frequency or frequencies is/are used. In this case, the number of pulses is multiplied by four and all times increase by this factor. For the Fast commands using one subcarrier, all pulse numbers and times are divided by 2.
11.1 Bit coding using one subcarrier
A logic 0 starts with eight pulses at 423.75 kHz ( f
C
18.88 µs, as shown in Figure 23 .
/32) followed by an unmodulated time of
Figure 23. Logic 0, high data rate
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AI
For the fast commands, a logic 0 starts with four pulses at 423.75 kHz ( f
C unmodulated time of 9.44 µs, as shown in
.
/32) followed by an
Figure 24. Logic 0, high data rate, fast commands
S
AI
A logic 1 starts with an unmodulated time of 18.88 µs followed by eight pulses at 423.75 kHz
( f
C
Figure 25. Logic 1, high data rate
S
AI
For the Fast commands, a logic 1 starts with an unmodulated time of 9.44 µs followed by four pulses of 423.75 kHz ( f
C
Figure 26. Logic 1, high data rate, fast commands
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Bit representation and coding M24LR04E-R
11.1.2 Low data rate
A logic 0 starts with 32 pulses at 423.75 kHz ( f
C
75.52 µs, as shown in Figure 27 .
/32) followed by an unmodulated time of
Figure 27. Logic 0, low data rate
S
AI
For the Fast commands, a logic 0 starts with 16 pulses at 423.75 kHz ( f
C
unmodulated time of 37.76 µs, as shown in Figure 28 .
/32) followed by an
Figure 28. Logic 0, low data rate, fast commands
S
AI
A logic 1 starts with an unmodulated time of 75.52 µs followed by 32 pulses at 423.75 kHz
(f
C
Figure 29. Logic 1, low data rate
S
AI
For the Fast commands, a logic 1 starts with an unmodulated time of 37.76 µs followed by
16 pulses at 423.75 kHz ( f
C
Figure 30. Logic 1, low data rate, fast commands
S
AI
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11.2 Bit coding using two subcarriers
Bit representation and coding
A logic 0 starts with eight pulses at 423.75 kHz ( f
C
484.28 kHz ( f
/32) followed by nine pulses at
C
/28), as shown in
Figure 31 . Bit coding using two subcarriers is not supported
for the Fast commands.
Figure 31. Logic 0, high data rate ϯϳ͘ϰϲђƐ
ĂŝϭϮϬϳϰ
A logic 1 starts with nine pulses at 484.28 kHz (
423.75 kHz ( f f
C
/32), as shown in
Figure 32 . Bit coding using two subcarriers is not supported
for the Fast commands.
C
/28) followed by eight pulses at
Figure 32. Logic 1, high data rate ϯϳ͘ϰϲђƐ
ĂŝϭϮϬϳϯ
11.2.2 Low data rate
A logic 0 starts with 32 pulses at 423.75 kHz ( f
C
( f
C commands.
/32) followed by 36 pulses at 484.28 kHz
/28), as shown in Figure 33 . Bit coding using two subcarriers is not supported for the Fast
Figure 33. Logic 0, low data rate
A logic 1 starts with 36 pulses at 484.28 kHz ( f
C
( f
C commands.
/28) followed by 32 pulses at 423.75 kHz
/32) as shown in Figure 34 . Bit coding using two subcarriers is not supported for the Fast
Figure 34. Logic 1, low data rate
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M24LR04E-R to VCD frames
12 M24LR04E-R to VCD frames
M24LR04E-R
Frames are delimited by an SOF and an EOF. They are implemented using code violation.
Unused options are reserved for future use. For the low data rate, the same subcarrier frequency or frequencies is/are used. In this case, the number of pulses is multiplied by 4.
For the Fast commands using one subcarrier, all pulse numbers and times are divided by 2.
12.1 SOF when using one subcarrier
The SOF includes an unmodulated time of 56.64 µs, followed by 24 pulses at 423.75 kHz
(f
C
/32), and a logic 1 that consists of an unmodulated time of 18.88 µs followed by eight pulses at 423.75 kHz, as shown in
Figure 35. Start of frame, high data rate, one subcarrier
For the Fast commands, the SOF comprises an unmodulated time of 28.32 µs, followed by
12 pulses at 423.75 kHz (f
C
/32), and a logic 1 that consists of an unmodulated time of
9.44 µs followed by four pulses at 423.75 kHz, as shown in Figure 36 .
Figure 36. Start of frame, high data rate, one subcarrier, fast commands ϱϲ͘ϲϰђƐ ϭϴ͘ϴϴђƐ
ĂŝϭϮϬϳϵ
12.1.2 Low data rate
The SOF comprises an unmodulated time of 226.56 µs, followed by 96 pulses at 423.75 kHz ( f
C
/32), and a logic 1 that consists of an unmodulated time of 75.52 µs followed by 32 pulses at 423.75 kHz, as shown in
Figure 37. Start of frame, low data rate, one subcarrier ϰϱϯ͘ϭϮђƐ ϭϱϭ͘ϬϰђƐ
ĂŝϭϮϬϴϬď
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M24LR04E-R M24LR04E-R to VCD frames
For the Fast commands, the SOF comprises an unmodulated time of 113.28 µs, followed by
48 pulses at 423.75 kHz ( f
C
/32), and a logic 1 that includes an unmodulated time of 37.76
µs followed by 16 pulses at 423.75 kHz, as shown in
.
Figure 38. Start of frame, low data rate, one subcarrier, fast commands
12.2 SOF when using two subcarriers
(
The SOF comprises 27 pulses at 484.28 kHz ( f
C
423.75 kHz, as shown in Figure 39 .
f
C
/28), followed by 24 pulses at 423.75 kHz
/32), and a logic 1 that includes nine pulses at 484.28 kHz followed by eight pulses at
Bit coding using two subcarriers is not supported for the Fast commands.
Figure 39. Start of frame, high data rate, two subcarriers ϭϭϮ͘ϯϵђƐ ϯϳ͘ϰϲђƐ
ĂŝϭϮϬϴϮ
12.2.2 Low data rate
The SOF comprises 108 pulses at 484.28 kHz ( f
C
( f
C
423.75 kHz, as shown in Figure 40 .
/28), followed by 96 pulses at 423.75 kHz
/32), and a logic 1 that includes 36 pulses at 484.28 kHz followed by 32 pulses at
Bit coding using two subcarriers is not supported for the Fast commands.
Figure 40. Start of frame, low data rate, two subcarriers ϰϰϵ͘ϱϲђƐ ϭϰϵ͘ϴϰђƐ
ĂŝϭϮϬϴϯ
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M24LR04E-R to VCD frames
12.3 EOF when using one subcarrier
M24LR04E-R
The EOF comprises a logic 0 that includes eight pulses at 423.75 kHz and an unmodulated time of 18.88 µs, followed by 24 pulses at 423.75 kHz ( f
C
/32), and by an unmodulated time
of 56.64 µs, as shown in Figure 41
.
Figure 41. End of frame, high data rate, one subcarrier
For the Fast commands, the EOF comprises a logic 0 that includes four pulses at
423.75 kHz and an unmodulated time of 9.44 µs, followed by 12 pulses at 423.75 kHz
( f
C
/32) and an unmodulated time of 37.76 µs, as shown in Figure 42 .
Figure 42. End of frame, high data rate, one subcarrier, fast commands
12.3.2 Low data rate
The EOF comprises a logic 0 that includes 32 pulses at 423.75 kHz and an unmodulated time of 75.52 µs, followed by 96 pulses at 423.75 kHz ( f
C
/32) and an unmodulated time of
226.56 µs, as shown in
.
Figure 43. End of frame, low data rate, one subcarrier
56/146
V V
069
For the Fast commands, the EOF comprises a logic 0 that includes 16 pulses at 423.75 kHz and an unmodulated time of 37.76 µs, followed by 48 pulses at 423.75 kHz ( f
C unmodulated time of 113.28 µs, as shown in
/32) and an
Figure 44. End of frame, low data rate, one subcarrier, Fast commands
V
DocID022208 Rev 11
V
069
M24LR04E-R
12.4 EOF when using two subcarriers
M24LR04E-R to VCD frames
The EOF comprises a logic 0 that includes eight pulses at 423.75 kHz and nine pulses at
(
484.28 kHz, followed by 24 pulses at 423.75 kHz ( f
C f
C
/32) and 27 pulses at 484.28 kHz
Bit coding using two subcarriers is not supported for the Fast commands.
Figure 45. End of frame, high data rate, two subcarriers
V V
069
12.4.2 Low data rate
The EOF comprises a logic 0 that includes 32 pulses at 423.75 kHz and 36 pulses at
(
484.28 kHz, followed by 96 pulses at 423.75 kHz ( f
C f
C
/32) and 108 pulses at 484.28 kHz
Bit coding using two subcarriers is not supported for the Fast commands.
Figure 46. End of frame, low data rate, two subcarriers ϭϰϵ͘ϴϰђƐ ϰϰϵ͘ϱϲђƐ
ĂŝϭϮϬϴϵ
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Unique identifier (UID)
13 Unique identifier (UID)
M24LR04E-R
The M24LR04E-R is uniquely identified by a 64-bit unique identifier (UID). This UID complies with ISO/IEC 15963 and ISO/IEC 7816-6. The UID is a read-only code and comprises:
• eight MSBs with a value of E0h,
• the IC manufacturer code “ST 02h” on 8 bits (ISO/IEC 7816-6/AM1),
• a unique serial number on 48 bits.
Table 21. UID format
MSB LSB
63 56 55 48 47 0
0xE0 0x02 Unique serial number
With the UID, each M24LR04E-R can be addressed uniquely and individually during the anticollision loop and for one-to-one exchanges between a VCD and an M24LR04E-R.
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M24LR04E-R
14 Application family identifier (AFI)
Application family identifier (AFI)
The AFI (application family identifier) represents the type of application targeted by the VCD and is used to identify, among all the M24LR04E-Rs present, only the M24LR04E-Rs that meet the required application criteria.
Figure 47. M24LR04E-R decision tree for AFI
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1R
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1R
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<HV
$),YDOXH
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<HV
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The AFI is programmed by the M24LR04E-R issuer (or purchaser) in the AFI register. Once programmed and locked, it cannot be modified any longer.
The most significant nibble of the AFI is used to code one specific or all application families.
The least significant nibble of the AFI is used to code one specific or all application subfamilies. Subfamily codes different from 0 are proprietary.
See ISO 15693-3 documentation.
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Data storage format identifier (DSFID)
15 Data storage format identifier (DSFID)
M24LR04E-R
The data storage format identifier indicates how the data is structured in the M24LR04E-R memory. The logical organization of data can be known instantly using the DSFID. It can be programmed and locked using the Write DSFID and Lock DSFID commands.
15.1 CRC
The CRC used in the M24LR04E-R is calculated as per the definition in ISO/IEC 13239. The initial register contents are all ones: “FFFF”.
The two-byte CRC is appended to each request and response, within each frame, before the EOF. The CRC is calculated on all the bytes after the SOF up to the CRC field.
Upon reception of a request from the VCD, the M24LR04E-R verifies that the CRC value is valid. If it is invalid, the M24LR04E-R discards the frame and does not answer to the VCD.
Upon reception of a response from the M24LR04E-R, it is recommended that the VCD verifies whether the CRC value is valid. If it is invalid, actions to be performed are left to the discretion of the VCD designer.
The CRC is transmitted least significant byte first. Each byte is transmitted least significant bit first.
Table 22. CRC transmission rules
LSByte
LSBit MSBit
MSByte
LSBit MSBit
CRC 16 (8 bits) CRC 16 (8 bits)
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16
M24LR04E-R protocol description
M24LR04E-R protocol description
The transmission protocol (or simply “the protocol”) defines the mechanism used to exchange instructions and data between the VCD and the M24LR04E-R in both directions.
It is based on the concept of “VCD talks first”.
This means that an M24LR04E-R does not start transmitting unless it has received and properly decoded an instruction sent by the VCD. The protocol is based on an exchange of:
• a request from the VCD to the M24LR04E-R,
• a response from the M24LR04E-R to the VCD.
Each request and each response are contained in a frame. The frame delimiters (SOF,
EOF) are described in
Section 12: M24LR04E-R to VCD frames
.
Each request consists of:
• a request SOF (see
and
• flags,
• a command code,
• parameters depending on the command,
• application data,
• a 2-byte CRC,
• a request EOF (see
).
Each response consists of:
•
an answer SOF (see Figure 35 to
• flags,
• parameters depending on the command,
• application data,
• a 2-byte CRC,
•
an answer EOF (see Figure 41 to
The protocol is bit-oriented. The number of bits transmitted in a frame is a multiple of eight
(8), that is an integer number of bytes.
A single-byte field is transmitted least significant bit (LSBit) first. A multiple-byte field is transmitted least significant byte (LSByte) first and each byte is transmitted least significant bit (LSBit) first.
The setting of the flags indicates the presence of the optional fields. When the flag is set (to one), the field is present. When the flag is reset (to zero), the field is absent.
Table 23. VCD request frame format
Request SOF Request_flags
Command code
Parameters Data 2-byte CRC
Request
EOF
Table 24. M24LR04E-R Response frame format
Response
SOF
Response_flags Parameters Data 2-byte CRC
Response
EOF
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M24LR04E-R protocol description
Figure 48. M24LR04E-R protocol timing
VCD
Request frame
(
)
Request frame
(
M24LR04E-R
Response frame
)
Timing <-t
1
-> <-t
2
-> <-t
1
->
M24LR04E-R
Response frame
(
)
<-t
2
->
62/146 DocID022208 Rev 11
M24LR04E-R M24LR04E-R states
An M24LR04E-R can be in one of four states:
• Power-off
• Ready
• Quiet
• Selected
Transitions between these states are specified in
.
The M24LR04E-R is in the Power-off state when it does not receive enough energy from the
VCD.
The M24LR04E-R is in the Ready state when it receives enough energy from the VCD.
When in the Ready state, the M24LR04E-R answers any request where the Select_flag is not set.
When in the Quiet state, the M24LR04E-R answers any request except for Inventory requests with the Address_flag set.
In the Selected state, the M24LR04E-R answers any request in all modes (see
• Request in Select mode with the Select_flag set
• Request in Addressed mode if the UID matches
• Request in Non-Addressed mode as it is the mode for general requests
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M24LR04E-R states M24LR04E-R
Table 25. M24LR04E-R response depending on Request_flags
Address_flag Select_flag
Flags
1
Addressed
0
Non addressed
1
Selected
0
Non selected
M24LR04E-R in Ready or Selected state (devices in Quiet state do not answer)
M24LR04E-R in Selected state
M24LR04E-R in Ready, Quiet or
Selected state (the device that matches the UID)
Error (03h)
-
-
X
X
X
X
-
-
-
X
-
X
X
-
-
X
Figure 49. M24LR04E-R state transition diagram
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1. The M24LR04E-R returns to the Power Off state if the tag is out of the RF field for at least t application note AN4125 for more information.
RF_OFF
. Refer to
2. The intention of the state transition method is that only one M24LR04E-R should be in the Selected state at any given time.
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M24LR04E-R
18 Modes
The term “mode” refers to the mechanism used in a request to specify the set of
M24LR04E-Rs that answers the request.
Modes
When the Address_flag is set to 1 (Addressed mode), the request contains the Unique ID
(UID) of the addressed M24LR04E-R.
Any M24LR04E-R that receives a request with the Address_flag set to 1 compares the received Unique ID to its own. If it matches, then the M24LR04E-R executes the request (if possible) and returns a response to the VCD as specified in the command description.
If the UID does not match, then it remains silent.
18.2 Non-addressed mode (general request)
When the Address_flag is cleared to 0 (Non-Addressed mode), the request does not contain a Unique ID. Any M24LR04E-R receiving a request with the Address_flag cleared to 0 executes it and returns a response to the VCD as specified in the command description.
When the Select_flag is set to 1 (Select mode), the request does not contain an
M24LR04E-R Unique ID. The M24LR04E-R in the Selected state that receives a request with the Select_flag set to 1 executes it and returns a response to the VCD as specified in the command description.
Only M24LR04E-Rs in the Selected state answer a request where the Select_flag set to 1.
The system design ensures in theory that only one M24LR04E-R can be in the Select state at a time.
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Request format M24LR04E-R
The request consists of:
• an SOF
• flags
• a command code
• parameters and data
• a CRC
• an EOF
Table 26. General request format
S
O
F
Request_flags Command code Parameters Data CRC
E
O
F
In a request, the “flags” field specifies the actions to be performed by the M24LR04E-R and whether corresponding fields are present or not.
The flags field consists of eight bits. Bit 3 (Inventory_flag) of the request flag defines the contents of the four MSBs (bits 5 to 8). When bit 3 is reset (0), bits 5 to 8 define the
M24LR04E-R selection criteria. When bit 3 is set (1), bits 5 to 8 define the M24LR04E-R
Inventory parameters.
Bit No.
Flag
Table 27. Definition of request flags 1 to 4
Level Description
Bit 1
Bit 2
Bit 3
Subcarrier_flag
Data_rate_flag
Inventory_flag
(1)
(2)
0
A single subcarrier frequency is used by the
M24LR04E-R
1 Two subcarrier are used by the M24LR04E-R
0 Low data rate is used
1 High data rate is used
0
The meaning of flags 5 to 8 is described in Table 28
1
The meaning of flags 5 to 8 is described in Table 29
0 No Protocol format extension Bit 4 Protocol_extension_flag
(3)
1. Subcarrier_flag refers to the M24LR04E-R-to-VCD communication.
2. Data_rate_flag refers to the M24LR04E-R-to-VCD communication.
3. Protocol_extension_flag must always be set to 0.
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M24LR04E-R Request format
.
Bit No.
Flag
Table 28. Request flags 5 to 8 when Bit 3 = 0
Level Description
Bit 5
Bit 6
Bit 7
Bit 8
Select flag
RFU
(1)
Address flag
Option flag
(1)
0
Request is executed by any M24LR04E-R according to the setting of Address_flag
1 Request is executed only by the M24LR04E-R in Selected state
0
Request is not addressed. UID field is not present. The request is executed by all M24LR04E-Rs.
1
Request is addressed. UID field is present. The request is executed only by the M24LR04E-R whose UID matches the UID specified in the request.
0 Option not activated.
1 Option activated.
0 -
1. If the Select_flag is set to 1, the Address_flag is set to 0 and the UID field is not present in the request.
Bit No.
Bit 5
Bit 6
Bit 7
Bit 8
Flag
AFI flag
Nb_slots flag
Option flag
RFU
Table 29. Request flags 5 to 8 when Bit 3 = 1
Level Description
0 AFI field is not present
1 AFI field is present
0 16 slots
1 1 slot
0 -
0 -
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Response format M24LR04E-R
The response consists of:
• an SOF,
• flags,
• parameters and data,
• a CRC,
• an EOF.
Table 30. General response format
S
O
F
Response_flags Parameters Data CRC
E
O
F
In a response, the flags indicate how actions have been performed by the M24LR04E-R and whether corresponding fields are present or not. The response flags consist of eight bits.
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit No.
Bit 1
Flag
Table 31. Definitions of response flags 1 to 8
Level Description
Error_flag
RFU
RFU
Extension flag
RFU
RFU
RFU
RFU
0
0
0
0
0
0
1
0
0
No error
-
-
Error detected. Error code is in the “Error” field.
-
-
-
-
No extension
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20.2 Response error code
If the Error_flag is set by the M24LR04E-R in the response, the Error code field is present and provides information about the error that occurred.
Error codes not specified in
Table 32 are reserved for future use.
Error code
03h
0Fh
10h
11h
12h
13h
14h
15h
Table 32. Response error code definition
Meaning
The option is not supported.
Error with no information given.
The specified block is not available.
The specified block is already locked and thus cannot be locked again.
The specified block is locked and its contents cannot be changed.
The specified block was not successfully programmed.
The specified block was not successfully locked.
The specified block is read-protected.
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Anticollision
21 Anticollision
M24LR04E-R
The purpose of the anticollision sequence is to inventory the M24LR04E-Rs present in the
VCD field using their unique ID (UID).
The VCD is the master of communications with one or several M24LR04E-Rs. It initiates
M24LR04E-R communication by issuing the Inventory request.
The M24LR04E-R sends its response in the determined slot or does not respond.
When issuing the Inventory Command, the VCD:
• sets the Nb_slots_flag as desired,
• adds the mask length and the mask value after the command field.
• The mask length is the number of significant bits of the mask value.
• The mask value is contained in an integer number of bytes. The mask length indicates the number of significant bits. LSB is transmitted first.
• If the mask length is not a multiple of 8 (bits), as many 0-bits as required are added to the mask value MSB so that the mask value is contained in an integer number of bytes.
• The next field starts at the next byte boundary.
Table 33. Inventory request format
MSB
SOF
Request_flags Command Optional AFI Mask length Mask value
8 bits 8 bits 8 bits 8 bits 0 to 8 bytes
CRC
16 bits
LSB
EOF
In the example provided in
and Figure 50 , the mask length is 11 bits. Five 0-bits
are added to the mask value MSB. The 11-bit mask and the current slot number are compared to the UID.
Table 34. Example of the addition of 0-bits to an 11-bit mask value
(b
15
) MSB
0000 0
LSB (b
0
)
100 1100 1111
0-bits added 11-bit mask value
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M24LR04E-R Anticollision
Figure 50. Principle of comparison between the mask, the slot number and the UID
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The AFI field is present if the AFI_flag is set.
The pulse is generated according to the definition of the EOF in ISO/IEC 15693-2.
The first slot starts immediately after the request EOF is received. To switch to the next slot, the VCD sends an EOF.
The following rules and restrictions apply:
• If no M24LR04E-R answer is detected, the VCD may switch to the next slot by sending an EOF.
• If one or more M24LR04E-R answers are detected, the VCD waits until the complete frame has been received before sending an EOF for switching to the next slot.
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Request processing by the M24LR04E-R
22 Request processing by the M24LR04E-R
M24LR04E-R
Upon reception of a valid request, the M24LR04E-R performs the following algorithm:
• NbS is the total number of slots (1 or 16)
• SN is the current slot number (0 to 15)
• LSB (value, n) function returns the n Less Significant Bits of value
• MSB (value, n) function returns the n Most Significant Bits of value
• “&” is the concatenation operator
• Slot_Frame is either an SOF or an EOF
SN = 0 if (Nb_slots_flag) then NbS = 1
SN_length = 0 endif else NbS = 16
SN_length = 4 endif label1: if LSB(UID, SN_length + Mask_length) =
LSB(SN,SN_length)&LSB(Mask,Mask_length) then answer to inventory request endif wait (Slot_Frame) if Slot_Frame = SOF then Stop Anticollision decode/process request exit endif if Slot_Frame = EOF if SN < NbS-1 then SN = SN + 1 goto label1 exit endif endif
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23
Explanation of the possible cases
Explanation of the possible cases
Note:
summarizes the main possible cases that can occur during an anticollision sequence when the number of slots is 16.
The sequence of steps is as follows:
• The VCD sends an Inventory request, in a frame terminated by an EOF. The number of slots is 16.
• M24LR04E-R_1 transmits its response in Slot 0. It is the only one to do so, therefore no collision occurs and its UID is received and registered by the VCD.
• The VCD sends an EOF in order to switch to the next slot.
• In Slot 1, two M24LR04E-Rs, M24LR04E-R_2 and M24LR04E-R_3 transmit a response, thus generating a collision. The VCD records the event and registers that a collision was detected in Slot 1.
• The VCD sends an EOF in order to switch to the next slot.
• In Slot 2, no M24LR04E-R transmits a response. Therefore the VCD does not detect any M24LR04E-R SOF and switches to the next slot by sending an EOF.
• In Slot 3, another collision occurs due to responses from M24LR04E-R_4 and
M24LR04E-R_5.
• The VCD sends a request (for instance a Read Block) to M24LR04E-R_1 whose UID has already been correctly received.
• All M24LR04E-Rs detect an SOF and exit the anticollision sequence. They process this request and since the request is addressed to M24LR04E-R_1, only M24LR04E-R_1 transmits a response.
• All M24LR04E-Rs are ready to receive another request. If it is an Inventory command, the slot numbering sequence restarts from 0.
The decision to interrupt the anticollision sequence is made by the VCD. It could have continued to send EOFs until Slot 16 and only then sent the request to M24LR04E-R.
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145
9&'
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M24LR04E-R Inventory Initiated command
The M24LR04E-R provides a special feature to improve the inventory time response of moving tags using the Initiate_flag value. This flag, controlled by the Initiate command, allows tags to answer to Inventory Initiated commands.
For applications in which multiple tags are moving in front of a reader, it is possible to miss tags using the standard inventory command. The reason is that the inventory sequence has to be performed on a global tree search. For example, a tag with a particular UID value may have to wait the run of a long tree search before being inventoried. If the delay is too long, the tag may be out of the field before it has been detected.
Using the Initiate command, the inventory sequence is optimized. When multiple tags are moving in front of a reader, the ones which are within the reader field are initiated by the
Initiate command. In this case, a small batch of tags answers to the Inventory Initiated command, which optimizes the time necessary to identify all the tags. When finished, the reader has to issue a new Initiate command in order to initiate a new small batch of tags which are new inside the reader field.
It is also possible to reduce the inventory sequence time using the Fast Initiate and Fast
Inventory Initiated commands. These commands allow the M24LR04E-Rs to increase their response data rate by a factor of 2, up to 53 Kbit/s.
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Timing definition M24LR04E-R
25.1 t
1
: M24LR04E-R response delay
Upon detection of the rising edge of the EOF received from the VCD, the M24LR04E-R waits for a time t
1nom
before transmitting its response to a VCD request or switching to the next slot during an inventory process. Values of t
1 in
.
. The EOF is defined
25.2 t
2
: VCD new request delay
t
2
is the time after which the VCD may send an EOF to switch to the next slot when one or more M24LR04E-R responses have been received during an Inventory command. It starts from the reception of the EOF from the M24LR04E-Rs.
The EOF sent by the VCD may be either 10% or 100% modulated regardless of the modulation index used for transmitting the VCD request to the M24LR04E-R.
t
2
is also the time after which the VCD may send a new request to the M24LR04E-R, as described in
.
Values of t
2
.
25.3 t
3
: VCD new request delay when no response is received from the M24LR04E-R
t
3 is the time after which the VCD may send an EOF to switch to the next slot when no
M24LR04E-R response has been received.
The EOF sent by the VCD may be either 10% or 100% modulated regardless of the modulation index used for transmitting the VCD request to the M24LR04E-R.
From the time the VCD has generated the rising edge of an EOF:
• If this EOF is 100% modulated, the VCD waits for a time at least equal to t
3min sending a new EOF.
before
• If this EOF is 10% modulated, the VCD waits for a time at least equal to the sum of t
3min
+ the M24LR04E-R nominal response time (which depends on the M24LR04E-R data rate and subcarrier modulation mode) before sending a new EOF.
Table 35. Timing values
(1)
Minimum (min) values Nominal (nom) values Maximum (max) values t t t
1
2
3
318.6 µs
309.2 µs t
1max
(2)
+ t
SOF
(3)
320.9 µs
No t nom
No t nom
323.3 µs
No t
No t max max
1. The tolerance of specific timings is ± 32/fC.
2.
t
1max
does not apply for write-alike requests. Timing conditions for write-alike requests are defined in the command description.
3. t
SOF
is the time taken by the M24LR04E-R to transmit an SOF to the VCD. t data rate: High data rate or Low data rate.
SOF
depends on the current
76/146 DocID022208 Rev 11
M24LR04E-R Command codes
The M24LR04E-R supports the commands described in this section. Their codes are given in
Command code standard
29h
2Ah
2Bh
-
-
-
01h
02h
20h
21h
23h
25h
26h
27h
28h
Table 36. Command codes
Function
Inventory
Stay Quiet
Read Single Block
Write Single Block
Read Multiple Block
Select
Reset to Ready
Write AFI
Lock AFI
-
-
-
Write DSFID
Lock DSFID
Get System Info
Command code custom
D2h
A0h
A1h
A2h
A3h
A4h
2Ch
B1h
B2h
B3h
C0h
C1h
C2h
C3h
D1h
Function
Get Multiple Block Security Status
Write-sector Password
Lock-sector
Present-sector Password
Fast Read Single Block
Fast Inventory Initiated
Fast Initiate
Fast Read Multiple Block
Inventory Initiated
Initiate
ReadCfg
WriteEHCfg
SetRstEHEn
CheckEHEn
WriteDOCfg
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Command codes M24LR04E-R
26.1 Inventory
When receiving the Inventory request, the M24LR04E-R runs the anticollision sequence.
The Inventory_flag is set to 1. The meaning of flags 5 to 8 is shown in
The request contains:
• the flags,
• the Inventory command code (see
• the AFI if the AFI flag is set,
• the mask length,
• the mask value,
• the CRC.
The M24LR04E-R does not generate any answer in case of error.
Table 37. Inventory request format
Request
SOF
Request_flags Inventory
Optional
AFI
Mask length
Mask value
8 bits 01h 8 bits 8 bits
CRC16
0 - 64 bits 16 bits
Request
EOF
-
The response contains:
• the flags,
• the Unique ID.
Table 38. Inventory response format
Response
SOF
Response_flags DSFID UID
8 bits 8 bits 64 bits
CRC16
16 bits
Response
EOF
-
During an Inventory process, if the VCD does not receive an RF M24LR04E-R response, it waits for a time t
3
before sending an EOF to switch to the next slot. t
3
starts from the rising edge of the request EOF sent by the VCD.
• If the VCD sends a 100% modulated EOF, the minimum value of t
3
is: t
3min
= 4384/f
C
(323.3µs) + t
SOF
• If the VCD sends a 10% modulated EOF, the minimum value of t
3
is: t
3min
= 4384/f
C
(323.3µs) + t
NRT where:
• t
SOF
is the time required by the M24LR04E-R to transmit an SOF to the VCD,
• t
NRT
is the nominal response time of the M24LR04E-R.
t
NRT
and t
SOF
are dependent on the M24LR04E-R-to-VCD data rate and subcarrier modulation mode.
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF starting the inventory command to the end of the M24LR04E-R response. If the M24LR04E-
R does not receive the corresponding slot marker, the RF WIP/BUSY pin remains at 0 until the next RF power-off.
78/146 DocID022208 Rev 11
M24LR04E-R
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Command codes
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z state.
Figure 52. M24LR04E-R RF-Busy management following Inventory command
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Command code = 0x02
On receiving the Stay Quiet command, the M24LR04E-R enters the Quiet State if no error occurs, and does NOT send back a response. There is NO response to the Stay Quiet command even if an error occurs.
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Command codes M24LR04E-R
When in the Quiet state:
• the M24LR04E-R does not process any request if the Inventory_flag is set,
• the M24LR04E-R processes any Addressed request.
The M24LR04E-R exits the Quiet State when:
• it is reset (power off),
• receiving a Select request. It then goes to the Selected state,
• receiving a Reset to Ready request. It then goes to the Ready state.
Table 39. Stay Quiet request format
Request
SOF
-
Request_flags Stay Quiet
8 bits 02h
UID
64 bits
CRC16
16 bits
Request
EOF
-
The Stay Quiet command must always be executed in Addressed mode (Select_flag is reset to 0 and Address_flag is set to 1).
Figure 53. Stay Quiet frame exchange between VCD and M24LR04E-R
VCD
M24LR04E-R
SOF
Stay Quiet request
EOF
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 during the Stay
Quiet command.
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z state.
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M24LR04E-R Command codes
26.3 Read Single Block
On receiving the Read Single Block command, the M24LR04E-R reads the requested block and sends back its 32-bit value in the response. The Protocol_extension_flag should be set to 0 for the M24LR04E-R to operate correctly.
Request
SOF
Request_ flags
Table 40. Read Single Block request format
Read Single
Block
8 bits 20h
1. Gray means that the field is optional.
UID
(1)
64 bits
Block number
8 bits
CRC16
16 bits
Request
EOF
-
Request parameters:
• Request flags
• UID (optional)
• Block number
Table 41. Read Single Block response format when Error_flag is NOT set
Response
SOF
Response_flags
Sector security status
(1)
Data CRC16
Response
EOF
8 bits
1. Gray means that the field is optional.
8 bits 32 bits 16 bits -
Response parameters:
• Sector security status if Option_flag is set (see
)
• Four bytes of block data b
7 b
6 b
5
Reserved for future use. All at 0.
b
4
Table 42. Sector security status b
3
Password control bits b
2 b
1
Read / Write protection bits b
0
0: Current sector not locked
1: Current sector locked
Table 43. Read Single Block response format when Error_flag is set
Response
SOF
Response_ flags
Error code CRC16
Response
EOF
8 bits 8 bits 16 bits -
Response parameter:
• Error code as Error_flag is set
– 10h: the specified block is not available
– 15h: the specified block is read-protected
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Command codes M24LR04E-R
Figure 54. Read Single Block frame exchange between VCD and M24LR04E-R
VCD
M24LR04E-R
SOF
Read Single Block request
EOF
<-t
1
-> SOF
Read Single Block response
EOF
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the Read Single Block command to the end of the M24LR04E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z state.
82/146
On receiving the Write Single Block command, the M24LR04E-R writes the data contained in the request to the requested block and reports whether the write operation was successful in the response. The Protocol_extension_flag should be set to 0 for the
M24LR04E-R to operate correctly.
During the RF write cycle W t
, there should be no modulation (neither 100% nor 10%), otherwise, the M24LR04E-R may not program correctly the data into the memory. The W t time is equal to t
1nom
+ 18 × 302 µs.
Request
SOF
Request_ flags
Table 44. Write Single Block request format
Write
Single
Block
UID
(1)
Block number
Data
8 bits 21h
1. Gray means that the field is optional.
64 bits 8 bits 32 bits
CRC16
Request
EOF
16 bits -
Request parameters:
• Request flags
• UID (optional)
• Block number
• Data
Table 45. Write Single Block response format when Error_flag is NOT set
Response SOF Response_flags CRC16 Response EOF
8 bits 16 bits -
Response parameter:
• No parameter. The response is send back after the writing cycle.
DocID022208 Rev 11
M24LR04E-R Command codes
Table 46. Write Single Block response format when Error_flag is set
Response
SOF
Response_ flags
Error code CRC16
Response
EOF
8 bits 8 bits 16 bits -
Response parameter:
• Error code as Error_flag is set:
– 0Fh: error with no information given
– 10h: the specified block is not available
– 12h: the specified block is locked and its contents cannot be changed
– 13h: the specified block was not successfully programmed
Figure 55. Write Single Block frame exchange between VCD and M24LR04E-R
VCD
M24LR04E-R
SOF
Write Single
Block request
EOF
<-t
1
-> SOF
Write Single
Block response
EOF
Write sequence when error
M24LR04E-R <------------------- W t
---------------> SOF
Write Single
Block response
EOF
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the Write Single Block command to the end of the M24LR04E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin is tied to 0 for the duration of the internal write cycle (from the end of a valid write single block command to the beginning of the M24LR04E-R response).
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Command codes M24LR04E-R
Figure 56. M24LR04E-R RF_Busy management following Write command
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069
When configuring in the RF Write in progress mode, the RF WIP/BUSY pin is tied to 0 during the Write & verify sequence, as shown in
84/146 DocID022208 Rev 11
M24LR04E-R Command codes
Figure 57. M24LR04E RF_Wip management following Write command
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DocID022208 Rev 11 85/146
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Command codes M24LR04E-R
26.5 Read Multiple Block
When receiving the Read Multiple Block command, the M24LR04E-R reads the selected blocks and sends back their value in multiples of 32 bits in the response. The blocks are numbered from 00h to 1FFh in the request and the value is minus one (–1) in the field. For example, if the “Number of blocks” field contains the value 06h, seven blocks are read. The maximum number of blocks is fixed at 32 assuming that they are all located in the same sector. If the number of blocks overlaps sectors, the M24LR04E-R returns an error code.
The Protocol_extension_flag should be set to 0 for the M24LR04E-R to operate correctly.
Request
SOF
Request_ flags
Table 47. Read Multiple Block request format
Read
Multiple
Block
UID
(1)
First block number
Number of blocks
8 bits 23h
1. Gray means that the field is optional.
64 bits 8 bits 8 bits
CRC16
16 bits
Request
EOF
-
Request parameters:
• Request flags
• UID (optional)
• First block number
• Number of blocks
Table 48. Read Multiple Block response format when Error_flag is NOT set
Response
SOF
Response_ flags
Sector security status
(1)
Data CRC16
Response
EOF
8 bits 8 bits (2) 32 bits (2) 16 bits -
1. Gray means that the field is optional.
2. Repeated as needed.
Response parameters:
• Sector security status if Option_flag is set (see
)
• N blocks of data b
7 b
6 b
5
Reserved for future use. All at 0.
b
4
Table 49. Sector security status b
3
Password control bits b
2 b
1
Read / Write protection bits b
0
0: Current sector not locked
1: Current sector locked
Table 50. Read Multiple Block response format when Error_flag is set
Response SOF Response_flags Error code CRC16 Response EOF
8 bits 8 bits 16 bits -
86/146 DocID022208 Rev 11
M24LR04E-R Command codes
Response parameter:
• Error code as Error_flag is set:
– 0Fh: error with no information given
– 10h: the specified block is not available
– 15h: the specified block is read-protected
Figure 58. Read Multiple Block frame exchange between VCD and M24LR04E-R
VCD
M24LR04E-R
SOF
Read Multiple
Block request
EOF
<-t
1
-> SOF
Read Multiple
Block response
EOF
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the Read Multiple Block command to the end of the M24LR04E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z state.
26.6 Select
When receiving the Select command:
• If the UID is equal to its own UID, the M24LR04E-R enters or stays in the Selected state and sends a response.
• If the UID does not match its own, the selected M24LR04E-R returns to the Ready state and does not send a response.
The M24LR04E-R answers an error code only if the UID is equal to its own UID. If not, no response is generated. If an error occurs, the M24LR04E-R remains in its current state.
Request
SOF
Request_ flags
8 bits
Select
25h
Table 51. Select request format
UID
64 bits
CRC16
16 bits
Request
EOF
-
Request parameter:
• UID
Table 52. Select Block response format when Error_flag is NOT set
Response
SOF
Response_flags CRC16
Response
EOF
8 bits 16 bits -
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Command codes
Response parameter:
• No parameter
Response
SOF
-
Table 53. Select response format when Error_flag is set
Response_ flags
Error code CRC16
8 bits 8 bits 16 bits
M24LR04E-R
Response
EOF
-
Response parameter:
• Error code as Error_flag is set:
– 03h: the option is not supported
Figure 59. Select frame exchange between VCD and M24LR04E-R
VCD
M24LR04E-R
SOF
Select request
EOF
<-t
1
-> SOF
Select response
EOF
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the Select command to the end of the M24LR04E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z state.
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M24LR04E-R Command codes
26.7 Reset to Ready
On receiving a Reset to Ready command, the M24LR04E-R returns to the Ready state if no error occurs. In the Addressed mode, the M24LR04E-R answers an error code only if the
UID is equal to its own UID. If not, no response is generated.
Request
SOF
Request_ flags
Table 54. Reset to Ready request format
Reset to
Ready
UID
(1)
8 bits 26h
1. Gray means that the field is optional.
64 bits
CRC16
16 bits
Request
EOF
-
Request parameter:
• UID (optional)
Table 55. Reset to Ready response format when Error_flag is NOT set
Response
SOF
Response_flags CRC16
Response
EOF
8 bits 16 bits -
Response parameter:
• No parameter
Table 56. Reset to ready response format when Error_flag is set
Response
SOF
Response_flags Error code CRC16
Response
EOF
8 bits 8 bits 16 bits -
Response parameter:
• Error code as Error_flag is set:
– 03h: the option is not supported
Figure 60. Reset to Ready frame exchange between VCD and M24LR04E-R
VCD
M24LR04E-R
SOF
Reset to
Ready request
EOF
<-t
1
-> SOF
Reset to
Ready response
EOF
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Command codes M24LR04E-R
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the Reset to ready command to the end of the M24LR04E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z state.
On receiving the Write AFI request, the M24LR04E-R programs the 8-bit AFI value to its memory. The Option_flag is supported.
During the RF write cycle W t
, there should be no modulation (neither 100% nor 10%), otherwise, the M24LR04E-R may not write correctly the AFI value into the memory. The W t time is equal to t
1nom
+ 18 × 302 µs.
Table 57. Write AFI request format
Request
SOF
Request
_flags
Write
AFI
8 bits 27h
1. Gray means that the field is optional.
UID
(1)
64 bits
AFI
8 bits
CRC16
16 bits
Request
EOF
-
Request parameter:
• Request flags
• UID (optional)
• AFI
Response
SOF
Table 58. Write AFI response format when Error_flag is NOT set
Response_flags CRC16
Response
EOF
8 bits 16 bits -
Response parameter:
• No parameter
Response
SOF
-
Table 59. Write AFI response format when Error_flag is set
Response_ flags
Error code CRC16
8 bits 8 bits 16 bits
Response
EOF
-
Response parameter:
• Error code as Error_flag is set
– 12h: the specified block is locked and its contents cannot be changed
– 13h: the specified block was not successfully programmed
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M24LR04E-R Command codes
Figure 61. Write AFI frame exchange between VCD and M24LR04E-R
VCD
M24LR04E-R
SOF
Write AFI request
EOF
<-t
1
-> SOF
Write AFI response
EOF
Write sequence when error
M24LR04E-R <------------------ W t
--------------> SOF
Write AFI response
EOF
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the Write AFI command to the end of the M24LR04E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin is tied to 0 for the duration of the internal write cycle (from the end of a valid Write AFI command to the beginning of the M24LR04E-R response).
On receiving the Lock AFI request, the M24LR04E-R locks the AFI value permanently. The
Option_flag is supported.
During the RF write cycle W t
, there should be no modulation (neither 100% nor 10%), otherwise, the M24LR04E-R may not Lock correctly the AFI value in memory. The W t equal to t
1nom
+ 18 × 302 µs.
time is
Table 60. Lock AFI request format
Request
SOF
Request_flags Lock AFI UID
(1)
8 bits 28h
1. Gray means that the field is optional.
64 bits
CRC16
16 bits
Request
EOF
-
Request parameter:
• Request Flags
• UID (optional)
Response
SOF
-
Table 61. Lock AFI response format when Error_flag is NOT set
Response_flags
8 bits
CRC16
16 bits
Response
EOF
-
Response parameter:
• No parameter
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Command codes M24LR04E-R
Response
SOF
-
Table 62. Lock AFI response format when Error_flag is set
Response_flags Error code CRC16
8 bits 8 bits 16 bits
Response
EOF
-
Response parameter:
• Error code as Error_flag is set
– 11h: the specified block is already locked and thus cannot be locked again
– 14h: the specified block was not successfully locked
Figure 62. Lock AFI frame exchange between VCD and M24LR04E-R
VCD
M24LR04E-R
SOF
Lock AFI request
EOF
<-t
1
-> SOF
Lock AFI response
EOF
Lock sequence when error
M24LR04E-R <----------------- W t
-----------> SOF
Lock AFI response
EOF
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the Lock AFI command to the end of the M24LR04E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin is tied to 0 for the entire duration of the internal write cycle (from the end of valid Lock AFI command to the beginning of the M24LR04E-R response).
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On receiving the Write DSFID request, the M24LR04E-R programs the 8-bit DSFID value to its memory. The Option_flag is supported.
During the RF write cycle W t
, there should be no modulation (neither 100% nor 10%), otherwise, the M24LR04E-R may not write correctly the DSFID value in memory. The W t time is equal to t
1nom
+ 18 × 302 µs.
Request
SOF
Request_ flags
Table 63. Write DSFID request format
Write
DSFID
UID
(1)
DSFID
8 bits 29h
1. Gray means that the field is optional.
64 bits 8 bits
CRC16
16 bits
Request
EOF
-
Request parameter:
• Request flags
• UID (optional)
• DSFID
Table 64. Write DSFID response format when Error_flag is NOT set
Response
SOF
Response_flags CRC16
Response
EOF
8 bits 16 bits -
Response parameter:
• No parameter
Table 65. Write DSFID response format when Error_flag is set
Response
SOF
Response_flags Error code CRC16
8 bits 8 bits 16 bits
Response
EOF
-
Response parameter:
• Error code as Error_flag is set
– 12h: the specified block is locked and its contents cannot be changed
– 13h: the specified block was not successfully programmed
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Command codes M24LR04E-R
Figure 63. Write DSFID frame exchange between VCD and M24LR04E-R
VCD
M24LR04E-R
SOF
Write DSFID request
EO
F
<-t
1
->
SO
F
Write DSFID response
EO
F
Write sequence when error
M24LR04E-R <---------------- W t
---------->
SO
F
Write DSFID response
EOF
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the Write DSFID command to the end of the M24LR04E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin is tied to 0 for the duration of the internal write cycle (from the end of a valid Write DSFID command to beginning of the M24LR04E-R response).
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On receiving the Lock DSFID request, the M24LR04E-R locks the DSFID value permanently. The Option_flag is supported.
During the RF write cycle W t
, there should be no modulation (neither 100% nor 10%), otherwise, the M24LR04E-R may not lock correctly the DSFID value in memory. The W t time is equal to t
1nom
+ 18 × 302 µs.
Request
SOF
Request_ flags
Table 66. Lock DSFID request format
Lock
DSFID
8 bits 2Ah
1. Gray means that the field is optional.
UID
(1)
64 bits
CRC16
16 bits
Request
EOF
-
Request parameter:
• Request flags
• UID (optional)
Table 67. Lock DSFID response format when Error_flag is NOT set
Response
SOF
Response_flags CRC16
Response
EOF
8 bits 16 bits -
Response parameter:
• No parameter.
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Table 68. Lock DSFID response format when Error_flag is set
Response
SOF
Response_flags Error code CRC16
8 bits 8 bits 16 bits
Response
EOF
-
Response parameter:
• Error code as Error_flag is set:
– 11h: the specified block is already locked and thus cannot be locked again
– 14h: the specified block was not successfully locked
.
Figure 64. Lock DSFID frame exchange between VCD and M24LR04E-R
VCD
M24LR04E-R
SOF
Lock
DSFID request
EOF
<-t
1
-> SOF
Lock DSFID response
EOF
Lock sequence when error
M24LR04E-R <----------------- W t
------------> SOF
Lock
DSFID response
EOF
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the Lock DSFID command to the end of the M24LR04E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin is tied to 0 for the duration of the internal write cycle (from the end of a valid Lock DSFID command to the beginning of the M24LR04E-R response).
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Command codes M24LR04E-R
When receiving the Get System Info command, the M24LR04E-R sends back its information data in the response.The Option_flag is not supported. The Get System Info can be issued in both Addressed and Non Addressed modes.
The Protocol_extension_flag must be set to 0. Table 70
shows the M24LR04E-R response to the Get System Info command depending on the value of the Protocol_extension_flag.
Table 69. Get System Info request format
Request
SOF
Request
_flags
Get System Info UID
(1)
8 bits 2Bh
1. Gray means that the field is optional.
64 bits
CRC16
16 bits
Request
EOF
-
Request parameter:
• Request flags
• UID (optional)
Table 70. Get System Info response format when Protocol_extension_flag = 0 and
Error_flag is NOT set
Response
SOF
Response
_flags
Information flags
UID DSFID AFI
Memory size
IC ref.
CRC
16
Response
EOF
00h 0Fh
64 bits
8 bits 8 bits 037F 5A
16 bits
-
Response parameters:
• Information flags set to 0Fh. DSFID, AFI, Memory Size and IC reference fields are present.
• UID code on 64 bits
• DSFID value
• AFI value
• Memory size. The M24LR04E-R provides 128 blocks (7Fh) of four bytes (03h)
• IC reference: the 8 bits are significant.
Table 71. Get System Info response format when Error_flag is set
Response
SOF
Response_flags Error code CRC16
Response
EOF
01h 8 bits 16 bits -
Response parameter:
• Error code as Error_flag is set:
– 03h: Option not supported
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Figure 65. Get System Info frame exchange between VCD and M24LR04E-R
VCD
M24LR04E-R
SOF
Get System Info request
EOF
<-t
1
-> SOF
Get System Info response
EOF
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the Get System Info command to the end of the M24LR04E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z state.
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Command codes M24LR04E-R
When receiving the Get Multiple Block Security Status command, the M24LR04E-R sends back the sector security status. The blocks are numbered from 00h to 01FFh in the request and the value is minus one (–1) in the field. For example, a value of '06' in the “Number of blocks” field requests to return the security status of seven blocks.
The Protocol_extension_flag should be set to 0 for the M24LR04E-R to operate correctly.
During the M24LR04E-R response, if the internal block address counter reaches 01FFh, it rolls over to 0000h and the Sector Security Status bytes for that location are sent back to the reader.
Table 72. Get Multiple Block Security Status request format
Request
SOF
Request
_flags
Get
Multiple
Block
Security
Status
UID
(1)
First block number
Number of blocks
CRC16
8 bits 2Ch
1. Gray means that the field is optional.
64 bits 8 bits 8 bits 16 bits
Request
EOF
-
Request parameter:
• Request flags
• UID (optional)
• First block number
• Number of blocks
Table 73. Get Multiple Block Security Status response format when Error_flag is NOT set
Response
SOF
Response_ flags
Sector security status
CRC16
Response
EOF
8 bits 8 bits
(1)
16 bits -
1. Repeated as needed.
Response parameters:
•
Sector security status (see Table 74
) b
7 b
6 b
5
Reserved for future use.
All at 0.
Table 74. Sector security status b
4 b
3 b
2 b
1
Password control bits
Read / Write protection bits b
0
0: Current sector not locked
1: Current sector locked
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Table 75. Get Multiple Block Security Status response format when Error_flag is set
Response
SOF
Response_ flags
Error code CRC16
Response
EOF
8 bits 8 bits 16 bits -
Response parameter:
• Error code as Error_flag is set:
– 03h: the option is not supported
– 10h: the specified block is not available
Figure 66. Get Multiple Block Security Status frame exchange between VCD and
M24LR04E-R
VCD
M24LR04E-R
SOF
Get Multiple Block
Security Status
EOF
<-t
1
-> SOF
Get Multiple Block
Security Status
EOF
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the Get Multiple Block Security Status command to the end of the M24LR04E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z state.
On receiving the Write-sector Password command, the M24LR04E-R uses the data contained in the request to write the password and reports whether the operation was successful in the response. The Option_flag is supported.
During the RF write cycle time, W t
, there must be no modulation at all (neither 100% nor
10%), otherwise, the M24LR04E-R may not correctly program the data into the memory.
The W t
time is equal to t
1nom
+ 18 × 302 µs. After a successful write, the new value of the selected password is automatically activated. It is not required to present the new password value until M24LR04E-R power-down.
Request
SOF
Request
_flags
Table 76. Write-sector Password request format
Writesector password
IC Mfg code
UID
(1)
Password number
Data CRC16
8 bits B1h
1. Gray means that the field is optional.
02h 64 bits 8 bits 32 bits 16 bits
Request
EOF
-
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Command codes M24LR04E-R
Request parameter:
• Request flags
• UID (optional)
• Password number (01h = Pswd1, 02h = Pswd2, 03h = Pswd3, other = Error)
• Data
Table 77. Write-sector Password response format when Error_flag is NOT set
Response
SOF
Response_flags CRC16
Response
EOF
8 bits 16 bits -
Response parameter:
• no parameter.
Table 78. Write-sector Password response format when Error_flag is set
Response
SOF
Response_ flags
Error code CRC16
Response
EOF
8 bits 8 bits 16 bits -
Response parameter:
• Error code as Error_flag is set:
– 10h: the password number is incorrect
– 12h: the session was not opened before the password update
– 13h: the specified block was not successfully programmed
– 0Fh: the presented password is incorrect
Figure 67. Write-sector Password frame exchange between VCD and M24LR04E-R
VCD
M24LR04E-R
SOF
Writesector
Password request
EOF
<-t
1
-> SOF
Write-sector
Password response
EOF
Write sequence when error
M24LR04E-R <---------------- W t
-------------> SOF
Writesector
Password response
EOF
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When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the Write-sector Password command to the end of the M24LR04E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin is tied to 0 for the duration of the internal write cycle (from the end of a valid Write sector password command to the beginning of the M24LR04E-R response).
26.15 Lock-sector
On receiving the Lock-sector command, the M24LR04E-R sets the access rights and permanently locks the selected sector. The Option_flag is supported.
A sector is selected by giving the address of one of its blocks in the Lock-sector request
(Sector number field). For example, addresses 0 to 31 are used to select sector 0 and addresses 32 to 63 are used to select sector 1. Care must be taken when issuing the Locksector command as all the blocks belonging to the same sector are automatically locked by a single command.
The Protocol_extension_flag should be set to 0 for the M24LR04E-R to operate correctly.
During the RF write cycle W t
, there should be no modulation (neither 100% nor 10%), otherwise, the M24LR04E-R may not correctly lock the memory block. The W t to t
1nom
+ 18 × 302 µs.
time is equal
Request
SOF
Request
_flags
Table 79. Lock-sector request format
Locksector
IC
Mfg code
UID
(1)
Sector number
Sector security status
CRC16
8 bits B2h
1. Gray means that the field is optional.
02h 64 bits 8 bits 8 bits 16 bits
Request
EOF
-
Request parameters:
• Request flags
• (optional) UID
• Sector number
• Sector security status (refer to
b
7
0 b
6
0 b
5
0
Table 80. Sector security status b
4 b
3 password control bits b
2 b
1
Read / Write protection bits b
0
1
Table 81. Lock-sector response format when Error_flag is NOT set
Response
SOF
Response_flags CRC16
Response
EOF
8 bits 16 bits -
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Command codes M24LR04E-R
Response parameter:
• No parameter
Response
SOF
Table 82. Lock-sector response format when Error_flag is set
Response_ flags
Error code CRC16
Response
EOF
8 bits 8 bits 16 bits -
Response parameter:
• Error code as Error_flag is set:
– 10h: the specified block is not available
– 11h: the specified block is already locked and thus cannot be locked again
– 14h: the specified block was not successfully locked
Figure 68. Lock-sector frame exchange between VCD and M24LR04E-R
VCD
M24LR04E-R
SOF
Lock-sector request
EOF
<-t
1
-> SOF
Lock-sector response
EOF
Lock sequence when error
M24LR04E-R <--------------- W t
-----------> SOF
Lock-sector response
EOF
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the Lock-sector command to the end of the M24LR04E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin is tied to 0 for the duration of the internal write cycle (from the end of a valid Lock sector command to the beginning of the M24LR04E-R response).
On receiving the Present-sector Password command, the M24LR04E-R compares the requested password with the data contained in the request and reports whether the operation has been successful in the response. The Option_flag is supported.
During the comparison cycle equal to W t
, there should be no modulation (neither 100% nor
10%), otherwise, the M24LR04E-R the Password value may not be correctly compared. The
W t
time is equal to t
1nom
+ 18 × 302 µs.
After a successful command, the access to all the memory blocks linked to the password is changed as described in
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Request
SOF
Request
_flags
Table 83. Present-sector Password request format
Presentsector
Password
IC
Mfg code
UID
(1)
Password number
Password CRC16
Request
EOF
8 bits B3h
1. Gray means that the field is optional.
02h 64 bits 8 bits 32 bits 16 bits -
Request parameter:
• Request flags
• UID (optional)
• Password Number (0x01 = Pswd1, 0x02 = Pswd2, 0x03 = Pswd3, other = Error)
• Password
Table 84. Present-sector Password response format when Error_flag is NOT set
Response
SOF
Response_flags CRC16
Response
EOF
8 bits 16 bits -
Response parameter:
• No parameter. The response is send back after the write cycle.
Table 85. Present-sector Password response format when Error_flag is set
Response
SOF
Response_flags Error code CRC16
Response
EOF
8 bits 8 bits 16 bits -
Response parameter:
• Error code as Error_flag is set:
– 10h: the password number is incorrect
– 0Fh: the present password is incorrect
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Command codes M24LR04E-R
Figure 69. Present-sector Password frame exchange between VCD and M24LR04E-R
VCD
M24LR04E-R
SOF
Presentsector password response
OR error
0F (bad password)
EOF
<-t
1
-> SOF
Present-sector password response
EOF
sequence when error
M24LR04E-R <---------------- W t
------------> SOF
Presentsector password response
EOF
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the Present Sector Password command to the end of the M24LR04E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY remains in high-Z state.
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26.17 Fast Read Single Block
On receiving the Fast Read Single Block command, the M24LR04E-R reads the requested block and sends back its 32-bit value in the response. The Option_flag is supported. The data rate of the response is multiplied by 2.
The Protocol_extension_flag should be set to 0 for the M24LR04E-R to operate correctly.
The subcarrier_flag should be set to 0, otherwise the M24LR04E-R answers with an error code.
Request
SOF
Request_ flags
Table 86. Fast Read Single Block request format
Fast Read
Single
Block
IC Mfg code
UID
(1)
Block number
CRC16
8 bits C0h
1. Gray means that the field is optional.
02h 64 bits 8 bits 16 bits
Request
EOF
-
Request parameters:
• Request flags
• UID (optional)
• Block number
Table 87. Fast Read Single Block response format when Error_flag is NOT set
Response
SOF
Response
_flags
Sector security status (1)
Data CRC16
Response
EOF
8 bits 8 bits
1. Gray means that the field is optional.
32 bits 16 bits -
Response parameters:
• Sector security status if Option_flag is set (see
)
• Four bytes of block data b
7 b
6 b
5
Reserved for future used.
All at 0.
Table 88. Sector security status b
4 b
3 b
2 b
1
Password control bits
Read / Write protection bits b
0
0: Current sector not locked
1: Current sector locked
Table 89. Fast Read Single Block response format when Error_flag is set
Response
SOF
Response_flags Error code CRC16
Response
EOF
8 bits 8 bits 16 bits -
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Command codes M24LR04E-R
Response parameter:
• Error code as Error_flag is set:
– 10h: the specified block is not available
– 15h: the specified block is read protected
Figure 70. Fast Read Single Block frame exchange between VCD and M24LR04E-R
VCD
M24LR04E-R
SOF
Fast Read Single
Block request
EOF
<-t
1
-> SOF
Fast Read Single
Block response
EOF
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the Fast Read Single block command to the end of the M24LR04E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z state.
26.18 Fast Inventory Initiated
Before receiving the Fast Inventory Initiated command, the M24LR04E-R must have received an Initiate or a Fast Initiate command in order to set the Initiate_ flag. If not, the
M24LR04E-R does not answer to the Fast Inventory Initiated command.
The subcarrier_flag should be set to 0, otherwise the M24LR04E-R answers with an error code.
On receiving the Fast Inventory Initiated request, the M24LR04E-R runs the anticollision sequence. The Inventory_flag must be set to 1. The meaning of flags 5 to 8 is shown in
Table 29 . The data rate of the response is multiplied by 2.
The request contains:
• the flags,
• the Inventory command code,
• the AFI if the AFI flag is set,
• the mask length,
• the mask value,
• the CRC.
The M24LR04E-R does not generate any answer in case of error.
Request
SOF
Request
_flags
Table 90. Fast Inventory Initiated request format
Fast
Inventory
Initiated
IC Mfg code
Optional
AFI
Mask length
Mask value CRC16
8 bits C1h 02h 8 bits 8 bits 0 - 64 bits 16 bits
Request
EOF
-
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The Response contains:
• the flags,
• the Unique ID.
Table 91. Fast Inventory Initiated response format
Response
SOF
Response
_flags
DSFID UID CRC16
8 bits 8 bits 64 bits 16 bits
Response
EOF
-
During an Inventory process, if the VCD does not receive an RF M24LR04E-R response, it waits for a time t
3
before sending an EOF to switch to the next slot. t
3
starts from the rising edge of the request EOF sent by the VCD.
• If the VCD sends a 100% modulated EOF, the minimum value of t
3
is: t
3min
= 4384/f
C
(323.3µs) + t
SOF
• If the VCD sends a 10% modulated EOF, the minimum value of t
3
is: t
3min
= 4384/f
C
(323.3µs) + t
NRT where:
• t
SOF
is the time required by the M24LR04E-R to transmit an SOF to the VCD
• t
NRT
is the nominal response time of the M24LR04E-R t
NRT
and t
SOF
are dependent on the M24LR04E-R-to-VCD data rate and subcarrier modulation mode.
When configured in the RF busy mode, the RF WIP/BUSY pin is driven to 0 from the SOF starting the inventory command to the end of the M24LR04E-R response.If the M24LR04E-
R does not receive the corresponding slot marker, the RF WIP/BUSY pin remains at 0 till the next RF power-off.
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z state.
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Command codes M24LR04E-R
On receiving the Fast Initiate command, the M24LR04E-R sets the internal Initiate_flag and sends back a response only if it is in the Ready state. The command has to be issued in the
Non Addressed mode only (Select_flag is reset to 0 and Address_flag is reset to 0). If an error occurs, the M24LR04E-R does not generate any answer. The Initiate_flag is reset after a power-off of the M24LR04E-R. The data rate of the response is multiplied by 2.
The subcarrier_flag should be set to 0, otherwise the M24LR04E-R answers with an error code.
The request contains:
• No data
Request
SOF
-
Request_flags
Table 92. Fast Initiate request format
Fast
Initiate
IC Mfg
Code
CRC16
8 bits C2h 02h 16 bits
Request
EOF
-
The response contains:
• the flags,
• the Unique ID.
Table 93. Fast Initiate response format
Response
SOF
Response
_flags
DSFID UID
8 bits 8 bits 64 bits
CRC16
16 bits
Response
EOF
-
Figure 71. Fast Initiate frame exchange between VCD and M24LR04E-R
VCD
M24LR04E-R
SOF
Fast Initiate request
EOF
<-t
1
-> SOF
Fast Initiate response
EOF
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the Fast Initiate command to the end of the M24LR04E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z state.
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26.20 Fast Read Multiple Block
On receiving the Fast Read Multiple Block command, the M24LR04E-R reads the selected blocks and sends back their value in multiples of 32 bits in the response. The blocks are numbered from 00h to 1FFh in the request and the value is minus one (–1) in the field. For example, if the “Number of blocks” field contains the value 06h, seven blocks are read. The maximum number of blocks is fixed to 32 assuming that they are all located in the same sector. If the number of blocks overlaps sectors, the M24LR04E-R returns an error code.
The Protocol_extension_flag should be set to 0 for the M24LR04E-R to operate correctly.
The Option_flag is supported. The data rate of the response is multiplied by 2.
The subcarrier_flag should be set to 0, otherwise the M24LR04E-R answers with an error code.
Request
SOF
Request_ flags
Table 94. Fast Read Multiple Block request format
Fast
Read
Multiple
Block
IC Mfg code
UID
(1)
First block number
Number of blocks
CRC16
Request
EOF
8 bits C3h
1. Gray means that the field is optional.
02h 64 bits 8 bits 8 bits 16 bits -
Request parameters:
• Request flag
• UID (Optional)
• First block number
• Number of blocks
Table 95. Fast Read Multiple Block response format when Error_flag is NOT set
Response
SOF
Response_ flags
Sector security status
(1)
Data CRC16
Response
EOF
8 bits 8 bits
(2)
32 bits
(2)
16 bits -
1. Gray means that the field is optional.
2. Repeated as needed.
Response parameters:
• Sector security status if Option_flag is set (see
)
• N block of data b
7 b
6
Table 96. Sector security status if Option_flag is set b
5
Reserved for future use.
All at 0.
b
4 b
3
Password control bits b
2 b
1
Read / Write protection bits b
0
0: Current sector not locked
1: Current sector locked
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Table 97. Fast Read Multiple Block response format when Error_flag is set
Response SOF Response_flags Error code CRC16 Response EOF
8 bits 8 bits 16 bits -
Response parameter:
• Error code as Error_flag is set:
– 03h: the option is not supported
– 10h: block address not available
– 15h: block read-protected
Figure 72. Fast Read Multiple Block frame exchange between VCD and M24LR04E-R
VCD
M24LR04E-R
SOF
Fast Read
Multiple Block request
EOF
<-t
1
-> SOF
Fast Read
Multiple Block response
EOF
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the Fast Read Multiple Block command to the end of the M24LR04E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z state.
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Before receiving the Inventory Initiated command, the M24LR04E-R must have received an
Initiate or a Fast Initiate command in order to set the Initiate_ flag. If not, the M24LR04E-R does not answer to the Inventory Initiated command.
On receiving the Inventory Initiated request, the M24LR04E-R runs the anticollision sequence. The Inventory_flag must be set to 1. The meaning of flags 5 to 8 is given in
The request contains:
• the flags,
• the Inventory Command code,
• the AFI if the AFI flag is set,
• the mask length,
• the mask value,
• the CRC.
The M24LR04E-R does not generate any answer in case of error.
DocID022208 Rev 11
M24LR04E-R Command codes
Table 98. Inventory Initiated request format
Request
SOF
Request
_flags
Inventory
Initiated
IC
Mfg code
Optional
AFI
Mask length
Mask value
8 bits D1h 02h 8 bits 8 bits 0 - 64 bits
CRC16
Request
EOF
16 bits -
The response contains:
• the flags,
• the Unique ID.
Response
SOF
Response
_flags
Table 99. Inventory Initiated response format
DSFID UID CRC16
8 bits 8 bits 64 bits 16 bits
Response
EOF
-
During an Inventory process, if the VCD does not receive an RF M24LR04E-R response, it waits for a time t
3
before sending an EOF to switch to the next slot. t
3
starts from the rising edge of the request EOF sent by the VCD.
• If the VCD sends a 100% modulated EOF, the minimum value of t
3
is: t
3min
= 4384/f
C
(323.3µs) + t
SOF
• If the VCD sends a 10% modulated EOF, the minimum value of t
3
is: t
3min
= 4384/f
C
(323.3µs) + t
NRT where:
• t
SOF
is the time required by the M24LR04E-R to transmit an SOF to the VCD
• t
NRT
is the nominal response time of the M24LR04E-R t
NRT
and t
SOF
are dependent on the M24LR04E-R-to-VCD data rate and subcarrier modulation mode.
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF starting the inventory command to the end of the M24LR04E-R response. If the M24LR04E-
R does not receive the corresponding slot marker, the RF WIP/BUSY pin remains at 0 till the next RF power-off.
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z state.
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145
Command codes M24LR04E-R
26.22 Initiate
On receiving the Initiate command, the M24LR04E-R sets the internal Initiate_flag and sends back a response only if it is in the ready state. The command has to be issued in the
Non Addressed mode only (Select_flag is reset to 0 and Address_flag is reset to 0). If an error occurs, the M24LR04E-R does not generate any answer. The Initiate_flag is reset after a power-off of the M24LR04E-R.
The request contains:
• No data
Request
SOF
Request_flags
8 bits
Table 100. Initiate request format
Initiate
IC Mfg code
CRC16
D2h 02h 16 bits
Request
EOF
-
.
The response contains:
• the flags,
• the Unique ID.
Table 101. Initiate Initiated response format
Response
SOF
Response
_flags
DSFID UID
8 bits 8 bits 64 bits
CRC16
16 bits
Response
EOF
-
Figure 73. Initiate frame exchange between VCD and M24LR04E-R
VCD
M24LR04E-R
SOF
Initiate request
EOF
<-t
1
-> SOF
Initiate response
EOF
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the Initiate command to the end of the M24LR04E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z state.
112/146 DocID022208 Rev 11
M24LR04E-R Command codes
26.23 ReadCfg
On receiving the ReadCfg command, the M24LR04E-R reads the Configuration byte and sends back its 8-bit value in the response.
The Protocol_extension_flag should be set to 0 for the M24LR04E-R to operate correctly. If the Protocol_extension_flag is at 1, the M24LR04E-R answers with an error code. The
Option_flag is not supported. The Inventory_flag must be set to 0.
Table 102. ReadCfg request format
Request
SOF
Request_ flags
ReadCfg
8 bits A0h
1. Gray means that the field is optional.
IC Mfg code
02h
UID
(1)
64 bits
CRC16
16 bits
Request
EOF
-
Request parameters:
• UID (optional)
Table 103. ReadCfg response format when Error_flag is NOT set
Response SOF Response_flags Data CRC16
Response
EOF
8 bits 8 bits 16 bits -
Response parameters:
• One byte of data: Configuration byte
Response
SOF
-
Table 104. ReadCfg response format when Error_flag is set
Response_ flags
Error code CRC16
8 bits 8 bits 16 bits
Response
EOF
-
Response parameter:
• Error code as Error_flag is set
– 03h: the option is not supported
– 0Fh: error with no information given
Figure 74. ReadCfg frame exchange between VCD and M24LR04E-R
VCD
M24LR04E-R
SOF ReadCfg request EOF
<-t
1
-> SOF ReadCfg response EOF
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145
Command codes M24LR04E-R
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the ReadCfg command to the end of the M24LR04E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z state.
26.24 WriteEHCfg
On receiving the WriteEHCfg command, the M24LR04E-R writes the data contained in the request to the Configuration byte and reports whether the write operation was successful in the response. The Protocol_extension_flag should be set to 0 for the M24LR04E-R to operate correctly. If the Protocol_extension_flag is at 1, the M24LR04E-R answers with an error code.
The Option_flag is supported, the Inventory_flag is not supported.
During the RF write cycle W t
, there should be no modulation (neither 100% nor 10%), otherwise, the M24LR04E-R may not program correctly the data into the Configuration byte.
The W t
time is equal to t
1nom
+ 18 × 302 µs.
Request
SOF
Request_ flags
Table 105. WriteEHCfg request format
WriteEHCfg
IC Mfg code
UID
(1)
Data CRC16
8 bits A1h
1. Gray means that the field is optional.
02h 64 bits 8 bits 16 bits
Request
EOF
-
Request parameters:
• Request flags
• UID (optional)
•
Data: during WriteEHCfg command, bit 3 of the data is ignored (see Table 14
).
Table 106. WriteEHCfg response format when Error_flag is NOT set
Response SOF Response_flags CRC16 Response EOF
8 bits 16 bits -
Response parameter:
• No parameter. The response is send back after the writing cycle.
Response
SOF
Table 107. WriteEHCfg response format when Error_flag is set
Response_ flags
Error code CRC16
Response
EOF
8 bits 8 bits 16 bits -
Response parameter:
• Error code as Error_flag is set:
– 13h: the specified block was not successfully programmed
114/146 DocID022208 Rev 11
M24LR04E-R Command codes
Figure 75. WriteEHCfg frame exchange between VCD and M24LR04E-R
VCD
M24LR04E-R
SOF
WriteEHCfg request
EOF
<-t
1
-> SOF
WriteEHCfg response
EOF
WriteEHCfg sequence when error
M24LR04E-R <------------------- W t
--------------> SOF
WriteEHCfg response
EOF
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the WriteEHCfg command to the end of the M24LR04E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin is tied to 0 for the entire duration of the internal write cycle (from the end of a valid WriteEHCfg command to the beginning of the M24LR04E-R response).
26.25 WriteDOCfg
On receiving the WriteDOCfg command, the M24LR04E-R writes the data contained in the request to the Configuration byte and reports whether the write operation was successful in the response. The Protocol_extension_flag should be set to 0 for the M24LR04E-R to operate correctly. If the Protocol_extension_flag is at 1, the M24LR04E-R answers with an error code.
The Option_flag is supported, the Inventory_flag is not supported.
During the RF write cycle W t
, there should be no modulation (neither 100% nor 10%), otherwise, the M24LR04E-R may not program correctly the data into the Configuration byte.
The W t
time is equal to t
1nom
+ 18 × 302 µs.
Request
SOF
Request_ flags
Table 108. WriteDOCfg request format
WriteDOCfg
8 bits A4h
1. Gray means that the field is optional.
IC Mfg code
02h
UID
(1)
64 bits
Data CRC16
8 bits 16 bits
Request
EOF
-
Request parameters:
• Request flag
• UID (optional)
• Data: during a WriteDOCfg command, bits 2 to 0 of the data are ignored (see
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145
Command codes M24LR04E-R
Table 109. WriteDOCfg response format when Error_flag is NOT set
Response SOF Response_flags CRC16 Response EOF
8 bits 16 bits -
Response parameter:
• No parameter. The response is sent back after the writing cycle.
Response
SOF
Table 110. WriteDOCfg response format when Error_flag is set
Response_ flags
Error code CRC16
Response
EOF
8 bits 8 bits 16 bits -
Response parameter:
• Error code as Error_flag is set:
– 13h: the specified block was not successfully programmed
Figure 76. WriteDOCfg frame exchange between VCD and M24LR04E-R
VCD
M24LR04E-R
SOF
WriteDOCfg request
EOF
<-t
1
-> SOF
WriteDOCfg response
EOF
WriteDOCfg sequence when error
M24LR04E-R <----------------- W t
--------------> SOF
WriteDOCfg response
EOF
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the WriteEHCfg command to the end of the M24LR04E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin is tied to 0 for the entire duration of the internal write cycle (from the end of a valid WriteDOCfg command to the beginning of the M24LR04E-R response).
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M24LR04E-R Command codes
26.26 SetRstEHEn
On receiving the SetRstEHEn command, the M24LR04E-R sets or resets the EH_enable bit in the volatile Control register. The Protocol_extension_flag should be set to 0 for the
M24LR04E-R to operate correctly. If the Protocol_extension_flag is at 1, the M24LR04E-R answers with an error code. The Option_flag and the Inventory_flag are not supported.
Request
SOF
Request_ flags
Table 111. SetRstEHEn request format
SetRstEHEn
IC Mfg code
UID
(1)
Data CRC16
Request
EOF
8 bits A2h
1. Gray means that the field is optional.
02h 64 bits 8 bits 16 bits -
Request parameters:
• Request flags
• UID (optional)
• Data: during a SetRstEHEn command, bits 7 to 1 are ignored. Bit 0 is the EH_enable bit.
Table 112. SetRstEHEn response format when Error_flag is NOT set
Response SOF Response_flags CRC16 Response EOF
8 bits 16 bits -
Response parameter:
• No parameter. The response is sent back after t
1
.
Response
SOF
Table 113. SetRstEHEn response format when Error_flag is set
Response_ flags
Error code CRC16
Response
EOF
8 bits 8 bits 16 bits -
Response parameter:
• Error code as Error_flag is set:
– 03h: the option is not supported
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145
Command codes
Figure 77. SetRstEHEn frame exchange between VCD and M24LR04E-R
M24LR04E-R
VCD
M24LR04E-R
SOF
SetRstEHEn request
EOF
<-t
1
-> SOF
SetRstEHEn response
EOF
WriteEHCfg sequence when no error
M24LR04E-R <-t
1
-> SOF
SetRstEHEn response
EOF
WriteEHCfg sequence when error
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the SetRstEHEn command to the end of the M24LR04E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z state.
26.27 CheckEHEn
On receiving the CheckEHEn command, the M24LR04E-R reads the Control register and sends back its 8-bit value in the response.
The Protocol_extension_flag should be set to 0 for the M24LR04E-R to operate correctly. If the Protocol_extension_flag is at 1, the M24LR04E-R answers with an error code. The
Option_flag is not supported. The Inventory_flag must be set to 0.
Table 114. CheckEHEn request format
Request
SOF
Request_ flags
CheckEHEn IC Mfg code UID
(1)
8 bits A3h
1. Gray means that the field is optional.
02h 64 bits
CRC16
16 bits
Request
EOF
-
Request parameters:
• UID (optional)
Table 115. CheckEHEn response format when Error_flag is NOT set
Response SOF Response_flags Data CRC16
Response
EOF
8 bits 8 bits 16 bits -
Response parameters:
• One byte of data: volatile Control register (see
118/146 DocID022208 Rev 11
M24LR04E-R Command codes
Response
SOF
Table 116. CheckEHEn response format when Error_flag is set
Response_ flags
Error code CRC16
Response
EOF
8 bits 8 bits 16 bits -
Response parameter:
• Error code as Error_flag is set
– 03h: the option is not supported
Figure 78. CheckEHEn frame exchange between VCD and M24LR04E-R
VCD
M24LR04E-R
SOF CheckEHEn request EOF
<-t
1
-> SOF
CheckEHEn response
EOF
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the CheckEHEn command to the end of the M24LR04E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z state.
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145
Maximum ratings M24LR04E-R
120/146
Stressing the device above the rating listed in Table 117
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect the device reliability.
Symbol
Table 117. Absolute maximum ratings
Parameter Min.
Max.
Unit
T
A
T
STG h
STG
,
, t
STG
Ambient operating temperature
Storage conditions
Sawn wafer on UV tape
-40
15
-
85
25
9
(1)
°C
°C months
Kept in its original packing form
V
V
I
T
T
V
STG
LEAD
V
IO
CC
OL_MAX
I
CC
(3)
MAX_1
MAX_2
V
ESD
(3)
(3)
Storage temperature
Lead temperature during soldering
I
2
C input or output range
I
2
C supply voltage
DC output current on pin SDA or
RF WIP/BUSY (when equal to 0)
RF supply current AC0 - AC1
RF input voltage amplitude peak to peak between AC0 and AC1,
GND pad left floating
AC voltage between AC0 and
GND, or AC1 and GND
UFDFPN8 (MLP8),
SO8, TSSOP8
UFDFPN8 (MLP8),
SO8, TSSOP8
-
-
VAC0-VAC1
Electrostatic discharge voltage
(human body model)
(4)
VAC0-GND, or
VAC1-GND
AC0, AC1
Other pads
Electrostatic discharge voltage (Machine model)
Electrostatic discharge voltage on antenna
(5)
AC0, AC1
-65
See note
-0.50
-0.50
-1
-
-
-
-
-
-
-
150
(2)
6.5
6.5
5
50
27
11
1000
3500
400
4000
1. Counted from ST shipment date.
2. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK
2002/95/EU.
®
7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)
3. Based on characterization, not tested in production.
4. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1 = 100 pF, R1 = 1500 Ω , R2 = 500 Ω )
5. Compliant with IEC 61000-4-3 method. (M24LRxxE packaged in S08N is mounted on ST’s reference antenna ANT1- M24LRxxE)
°C
°C
V
V mA mA
V
V
V
DocID022208 Rev 11
M24LR04E-R
28 I
2
C DC and AC parameters
I 2 C DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device in I 2 C mode. The parameters in the DC and AC characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters.
Symbol
V
CC
T
A
Table 118. I 2 C operating conditions
Parameter Min.
Supply voltage
Ambient operating temperature
1.8
-40
Max.
5.5
85
Unit
V
°C
Symbol
C
L t r
, t f
V hi-lo
V ref(t)
Table 119. AC test measurement conditions
Parameter
Load capacitance
Input rise and fall times
Input levels
Input and output timing reference levels
Min.
Max.
100
50
0.2 V
CC
to 0.8 V
CC
0.3 V
CC
to 0.7 V
CC
Figure 79. AC test measurement I/O waveform
)NPUT,EVELS )NPUTAND/UTPUT
4IMING2EFERENCE,EVELS
6##
6##
6##
6##
!)"
Symbol
Table 120. Input parameters
Parameter
C
IN
C
IN t
NS
(1)
Input capacitance (SDA)
Input capacitance (other pins)
Pulse width ignored (Input filter on SCL and SDA)
1. Characterized only.
Min.
-
-
-
Max.
8
6
80
Unit pF ns
V
V
Unit pF pF ns
DocID022208 Rev 11 121/146
145
I 2 C DC and AC parameters M24LR04E-R
Symbol
Table 121. I 2 C DC characteristics
Parameter Test condition Min.
Max.
Unit
I
LO_Vout
I
I
LI
LO
Input leakage current
(SCL, SDA)
Vout output leakage current
Output leakage current
V
IN
= V
SS
or V
CC device in Standby mode external voltage applied on
Vout: V
SS
or V
CC
SDA in Hi-Z, external voltage applied on SDA: V
SS
or V
CC
V
CC
= 1.8 V, f c
= 100 kHz
(rise/fall time < 50 ns)
-
-
-
± 2
± 5
± 2
50
I
CC
Supply current (Read)
(1)
V
CC
= 1.8 V, f c
= 400 kHz
(rise/fall time < 50 ns)
V
CC
= 2.5 V, f c
= 400 kHz
(rise/fall time < 50 ns)
-
100
200
V
CC
= 5.5 V, f c
= 400 kHz
(rise/fall time < 50 ns)
400
I
I
CC0
CC1
V
V
V
IL
IH
OL
Supply current (Write)
Input low voltage
(SDA, SCL)
Input high voltage
(SDA, SCL)
Output low voltage
(1)
Standby supply current
V
CC
= 1.8 - 5.5 V
V
IN
= V
SS
or V
CC
V
CC
= 1.8 V
V
IN
= V
SS
or V
CC
V
CC
= 2.5 V
V
IN
= V
SS
or V
CC
V
CC
= 5.5 V
V
CC
= 1.8 V
V
CC
= 2.5 V
V
CC
= 5.5 V
V
CC
= 1.8 V
V
CC
= 2.5 V
V
CC
= 5.5 V
I
OL
I
= 2.1 mA, V
CC
OL
= 3 mA, V
CC
= 1.8 V or
= 5.5 V
-
-
-
-
-0.45
-0.45
-0.45
0.75V
CC
0.75V
CC
0.7V
-
CC
1. SCL, SDA connected to Ground or V
CC.
SDA connected to V
CC
through a pull-up resistor.
220
30
30
100
0.25V
0.25V
0.4
CC
CC
0.3V
CC
V
V
V
CC
CC
CC
+1
+1
+1
µA
µA
µA
µA
µA
µA
V
V
V
122/146 DocID022208 Rev 11
M24LR04E-R I 2 C DC and AC parameters
Table 122. I 2 C AC characteristics
Test conditions specified in Table 118
Symbol Alt.
Parameter Min.
Max.
Unit f
C t
CHCL t
CLCH t
START_OUT t
XH1XH2
(3) t
XL1XL2
(3) t
DL1DL2 t
DXCX t
CLDX t
CLQX t
CLQV
(4)(5) t
CHDX
(6) t
DLCL t
CHDH t
DHDL f
SCL t
HIGH t
LOW
t
R t
F t
F t
SU:DAT t
HD:DAT t
DH t
AA t
SU:STA t
HD:STA t
SU:STO
Clock frequency
Clock pulse width high
Clock pulse width low
I²C timeout on Start condition
Input signal rise time
Input signal fall time
SDA (out) fall time
Data in set up time
Data in hold time
Data out hold time
Clock low to next data valid (access time)
Start condition set up time
Start condition hold time
Stop condition set up time t
BUF
Time between Stop condition and next Start condition
25
0.6
20000
(1)
1.3
20000
(2)
40
20
20
20
100
0
100
100
600
400
-
300
300
100
-
-
-
900
-
0.6
35000
600
1300 -
-
(7) kHz
µs
µs ms ns ns ns ns ns ns ns ns
µs ns ns t
W
I²C write time 5 ms
1. t
CHCL
timeout
2. t
CLCH
timeout
3. Values recommended by the I²C-bus Fast-Mode specification.
4. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
5. t
CLQV
is the time (from the falling edge of SCL) required by the SDA bus line to reach 0.8V
compatible way with the I
× C bus
2 C specification (which specifies t
time constant is less than 500 ns (as specified in
).
CC
in a
(min) = 100 ns), assuming that the R bus
6. For a reStart condition, or following a write cycle.
7. t
DLCL
timeout
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145
I 2 C DC and AC parameters
T8,8,
Figure 80. I 2 C AC waveforms
T#(#,
T#,#( T8(8(
3#,
3$!)N
T$,#, T8,8,
T#($8
3TART
CONDITION
T8(8(
3$!
)NPUT
T#,$8 3$!
#HANGE
T$8#8
M24LR04E-R
T#($( T$($,
3TOP
CONDITION
3TART
CONDITION
3#,
3$!)N
3#,
3$!/UT
T#($(
3TOP
CONDITION
T#(#,
T#,16
T7
7RITECYCLE
$ATAVALID
T#,18
$ATAVALID
T#($8
3TART
CONDITION
T$,$,
!)E
124/146 DocID022208 Rev 11
M24LR04E-R
29 Write cycle definition
Write cycle definition
Symbol Parameter
Table 123. Write cycle endurance (1)
Test conditions Min Max Unit
N cycle
(2)
Write cycle endurance
(3)
V
T
A
≤ + 25 °C
CC(min)
< V
CC
< V
CC(max)
V
T
A
≤ + 85 °C
CC(min)
< V
CC
< V
CC(max)
-
1000000
150000
Write cycle
1. A write cycle means the simultaneous writing of one byte, two bytes, three bytes or four bytes (one page).
2. Indicates the total number of write/erase cycles for one memory cell or the overall number of write/erase cycles decoded by the whole memory.
3. Write cycle endurance is defined by characterization and qualification.
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RF electrical parameters
30 RF electrical parameters
M24LR04E-R
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device in RF mode.
The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the Measurement Conditions summarized in the relevant tables.
Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters.
Symbol Parameter
Table 124. RF characteristics (1) (2)
Condition Min Typ Max Unit f
CC
H_ISO
MI
CARRIER t
RFR
, t
RFF t
RFSBL
MI
CARRIER t
RFR
, t
RFF t
RFSBL
V
V t
I
MIN CD
V f f t t
SH
SL
1
2
W t
CC_RF
C
TUN
BACK
MAX_1
(3)
MAX_2
(3)
External RF signal frequency
Operating field according to ISO
10% carrier modulation index
MI=(A-B)/(A+B)
(3)
10% rise and fall time
10% minimum pulse width for bit
100% carrier modulation index
100% rise and fall time
100% minimum pulse width for bit
Minimum time from carrier generation to first data
Subcarrier frequency high
Subcarrier frequency low
Time for M24LR04E-R response
Time between commands
RF write time
(including internal Verify)
Operating current (Read)
(5)
Internal tuning capacitor in SO8
(6)
Backscattered level as defined by ISO test
RF input voltage amplitude between AC0 and AC1,
GND pad left floating,
VAC0-VAC1 peak to peak
(7)
AC voltage between AC0 and
GND or between AC1 and GND
-
T
A
= -40 °C to 85 °C
150 mA/m > H_ISO > 1000 mA/m
H_ISO > 1000 mA/m
-
-
MI=(A-B)/(A+B)
-
-
(4)
From H-field min f f
CC
CC
-
-
-
/32
/28
4224/f
4224/f
S
S
VAC0-VAC1 (4 V peak to peak) f = 13.56 MHz
ISO10373-7
13.553 13.56 13.567 MHz
150 5000 mA/m
15
10
0.5
7.1
95
0.5
7
-
-
-
-
24.8
10
-
-1
-
-
-
-
-
-
-
-
423.75
5.75
20
27.5
-
-
-
30
30
3.0
9.44
100
3.5
9.44
1
-
-
-
30.2
-
20
8.5
%
µs
µs
%
µs
µs ms kHz
484.28
kHz
318.6
320.9
323.3
µs
309 311.5
314 µs ms
µA pF mV
V
V
126/146 DocID022208 Rev 11
M24LR04E-R RF electrical parameters
Symbol
Table 124. RF characteristics (1) (2) (continued)
Parameter Condition Min Typ Max Unit
V
MIN_1
(3)
RF input voltage amplitude between AC0 and AC1, GND pad left floating, VAC0-VAC1 peak to peak
(7)
Inventory and Read operations
Write operations -
4
4.5
4.5
5
V
V
V
MIN_2
(3)
AC voltage between AC0 and
GND or between AC1 and GND
Inventory and Read operations
Write operations
-
-
1.8
2
2
2.2
V
V t
RF_OFF
RF OFF time Chip reset 2 ms
1. T
A
= –40 to 85 °C. Characterized only.
2. All timing characterizations were performed on a reference antenna with the following characteristics:
External size: 75 mm x 48 mm
Number of turns: 5
Width of conductor: 0.5 mm
Space between two conductors: 0.3 mm
Value of the tuning capacitor in SO8: 27.5 pF (M24LR04E-R)
Value of the coil: 5 µH
Tuning frequency: 13.56 MHz.
3. 15% (or more) carrier modulation index offers a better signal/noise ratio and therefore a wider operating range with a better noise immunity.
4. Temperature range 0 °C to 90 °C
5. Characterized on bench.
6. Characterized only, at room temperature only, measured at VAC0-VAC1 = 1 V peak to peak.
7. Characterized only, at room temperature only.
Symbol
T
A
Table 125. Operating conditions
Parameter Min.
Ambient operating temperature –40
Max.
85
Unit
°C
shows an ASK modulated signal from the VCD to the M24LR04E-R. The test condition for the AC/DC parameters are:
• Close coupling condition with tester antenna (1 mm)
• M24LR04E-R performance measured at the tag antenna
• M24LR04E-R synchronous timing, transmit and receive
DocID022208 Rev 11 127/146
145
RF electrical parameters M24LR04E-R
Figure 81. ASK modulated signal
Note:
$ %
W5))
W5)5
I&&
W5)6%/
W0,1&'
-36
summarizes respectively the minimum AC0-AC1 input power level P
AC0-AC1_min required for the Energy harvesting mode, the corresponding maximum current consumption
I sink_max
, and variation of the analog voltage V out
for the various Energy harvesting fan-out configurations defined by bits b0 and b1 of the Configuration byte.
Range
00
01
10
11
H min
(3)
3.5 A/m
2.4 A/m
1.6 A/m
1.0 A/m
Table 126. Energy harvesting (1) (2)
P min
(4)
V out
@I=0 V out
@I sink_max
100 mW
60 mW
30 mW
16 mW
2.7 V min
4.5 V max
2.7 V min
4.5 V max
2.7 V min
4.5 V max
2.7 V min
4.5 V max
1.7 V
1.9 V
2.1 V
2.3 V
1. Characterized only
2. Valid from -40 °C to +85 °C
3. H min
characterized according to ISO10373-7 test method
4. P min
calculated from DC measurements
I sink_max
@P min
6 mA
3 mA
1 mA
300 µA
It is recommended to choose the Energy Harvesting Range in respect with the maximum current requested by the application to avoid any disabling of Energy Harvesting mode (for example, choose Range 01 for a max consumption of 2 mA).
128/146 DocID022208 Rev 11
M24LR04E-R
Figure 82. Vout vs. Isink
RF electrical parameters
7PVU
7
7
7
7
7
)DQRXW
$
P$
N" N" N" N" *TJOL
Figure 83. Range 11 domain
:RUNLQJGRPDLQZKHQ
5DQJHLVVHOHFWHG
P$
-36
P$
P$
$P $P $P $P $P
)LHOG
+UPV
069
DocID022208 Rev 11 129/146
145
RF electrical parameters
)DQRXW
$
P$
Figure 84. Range 10 domain
M24LR04E-R
:RUNLQJGRPDLQZKHQ
5DQJHLVVHOHFWHG
P$
P$
P$
$P $P $P $P
Figure 85. Range 01 domain
$P
)LHOG
+UPV
069
)DQRXW
$
P$
:RUNLQJGRPDLQZKHQ
5DQJHLVVHOHFWHG
P$
P$
P$
$P $P $P $P $P
)LHOG
+UPV
069
130/146 DocID022208 Rev 11
M24LR04E-R
)DQRXW
$
P$
RF electrical parameters
Figure 86. Range 00 domain
:RUNLQJGRPDLQZKHQ
5DQJHLVVHOHFWHG
P$
P$
P$
$P $P $P $P $P
)LHOG
+UPV
069
DocID022208 Rev 11 131/146
145
Package information M24LR04E-R
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
31.1 SO8N package information
Figure 87. SO8N – 8-lead plastic small outline, 150 mils body width, package outline
HX
!
!
C
CCC
B
E
$
PP
*$8*(3/$1(
K
% %
!
,
,
62$B9
1. Drawing is not to scale.
Symbol
Table 127. SO8N – 8-lead plastic small outline, 150 mils body width, package mechanical data millimeters inches
(1)
Min.
Typ.
Max.
Min.
Typ.
Max.
D
E b c
A
A1
A2 h k
E1 e
L
-
0.100
1.250
0.280
0.170
4.800
5.800
3.800
-
0.250
0°
0.400
-
-
4.900
6.000
-
-
-
3.900
1.270
-
-
-
1.750
0.250
-
0.480
0.230
5.000
6.200
4.000
-
0.500
8°
1.270
-
0.0039
0.0492
0.0110
0.0067
0.1890
0.2283
0.1496
-
0.0098
0°
0.0157
-
-
-
-
-
0.1929
0.2362
0.1535
0.0500
-
-
-
0.0689
0.0098
-
0.0189
0.0091
0.1969
0.2441
0.1575
-
0.0197
8°
0.0500
132/146 DocID022208 Rev 11
M24LR04E-R Package information
Symbol
Table 127. SO8N – 8-lead plastic small outline, 150 mils body width, package mechanical data (continued) millimeters inches (1)
Min.
Typ.
Max.
Min.
Typ.
Max.
L1 ccc
-
-
1.040
-
-
0.100
-
-
1. Values in inches are converted from mm and rounded to four decimal digits.
0.0409
-
-
0.0039
Figure 88. SO8N – 8-lead plastic small outline, 150 mils body width, package recommended footprint
[
2B621B)3B9
1. Dimensions are expressed in millimeters.
DocID022208 Rev 11 133/146
145
Package information M24LR04E-R
134/146
Figure 89. UFDFN8 - 8-lead, 2 × 3 mm, 0.5 mm pitch ultra thin profile fine pitch dual flat package outline
1
' $ %
3LQ
,'PDUNLQJ
(
$
$
FFF
HHH &
6HDWLQJSODQH
6LGHYLHZ
$
&
[ DDD &
[ DDD &
7RSYLHZ
'
H E
'DWXP$
/
/
/ /
3LQ
,'PDUNLQJ
/
(
.
H
H
'HWDLO³$´
(YHQWHUPLQDO
/
7HUPLQDOWLS
1'[ H
%RWWRPYLHZ 6HH'HWDLO³$´
=:EB0(B9
1. Max. package warpage is 0.05 mm.
2. Exposed copper is not systematic and can appear partially or totally according to the cross section.
3. Drawing is not to scale.
4. The central pad (E2 by D2 in the above illustration) is internally pulled to V
SS
. It must not be connected to any other voltage or signal line on the PCB, for example during the soldering process.
D
D2
E
A
A1 b
(2)
Table 128. UFDFN8 - 8-lead, 2 × 3 mm, 0.5 mm pitch ultra thin profile fine pitch dual flat package mechanical data millimeters inches
(1)
Symbol
Min Typ Max Min Typ Max
0.450
0.000
0.200
1.900
1.200
2.900
0.550
0.020
0.250
2.000
-
3.000
0.600
0.050
0.300
2.100
1.600
3.100
0.0177
0.0000
0.0079
0.0748
0.0472
0.1142
0.0217
0.0008
0.0098
0.0787
-
0.1181
0.0236
0.0020
0.0118
0.0827
0.0630
0.1220
DocID022208 Rev 11
M24LR04E-R Package information
Table 128. UFDFN8 - 8-lead, 2 × 3 mm, 0.5 mm pitch ultra thin profile fine pitch dual flat package mechanical data (continued) millimeters inches (1)
Symbol
Min Typ Max Min Typ Max
E2 e
K
L
L1
L3 aaa bbb ccc ddd eee (3)
1.200
-
0.300
0.300
-
0.300
-
-
-
-
-
-
0.500
-
-
-
-
-
-
-
-
-
1.600
-
-
0.500
0.150
-
0.150
0.100
0.100
0.050
0.080
0.0472
0.0118
0.0118
-
0.0118
-
-
-
-
-
0.0197
-
-
-
-
-
-
-
-
-
0.0630
-
0.0197
0.0059
-
0.0059
0.0039
0.0039
0.0020
0.0031
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from the terminal tip.
3. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from measuring.
Figure 90.TSSOP8 – 8-lead thin shrink small outline, 3 x 6.4 mm, 0.65 mm pitch, package outline
ϴ ϱ ϭ ϭ ϰ
W
1. Drawing is not to scale.
ď Ğ
Ϯ ϭ
>ϭ
> ɲ
Đ
76623$0B9
DocID022208 Rev 11 135/146
145
Package information M24LR04E-R
Table 129. TSSOP8 – 8-lead thin shrink small outline, 3 x 6.4 mm, 0.65 mm pitch, package mechanical data millimeters inches
(1)
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
b c
CP
D
A
A1
A2
-
0.050
0.800
0.190
0.090
-
2.900
-
-
1.000
-
-
-
3.000
1.200
0.150
1.050
0.300
0.200
0.100
3.100
E1
L e
E
-
6.200
4.300
0.450
0.650
6.400
4.400
0.600
-
6.600
4.500
0.750
-
0.2441
0.1693
0.0177
L1 1.000
-
α 0° 8° 0°
1. Values in inches are converted from mm and rounded to four decimal digits.
-
0.0020
0.0315
0.0075
0.0035
-
0.1142
0.0256
0.2520
0.1732
0.0236
0.0394
-
-
-
0.0394
-
-
-
0.1181
-
0.2598
0.1772
0.0295
-
8°
0.0472
0.0059
0.0413
0.0118
0.0079
0.0039
0.1220
136/146 DocID022208 Rev 11
M24LR04E-R Ordering information
Note:
Table 130. Ordering information scheme for bare die devices or packaged devices
Example: M24LR04E-R MN 6 T /2
Device type
M24LR = dynamic NFC/RFID tag IC
04 = memory size in Kbit
E = support for energy harvesting
Operating voltage
R = V
CC
= 1.8 to 5.5 V
Package
MN = SO8N (150 mils width)
MC = UFDFPN8 (MLP8)
DW = TSSOP8
UW20 = inkless, unsawn wafer, with no backgrinding
(1)
SB12I = 120 µm ± 15 µm
bumped and sawn inkless wafer on 8-inch frame
Device grade
(2)
6 = industrial: device tested with standard test flow over –40 to 85 °C
Option (2)
T = Tape and reel packing
Capacitance
/2 = 27.5 pF
1. Delivery type: wafer tested, unsawn, without backgrinding. Wafer thickness: 725 µm ±20 µm.
Bad chip identification by STIF wafer maps provided by STMicroelectronics.
2. For packaged devices only.
Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.
DocID022208 Rev 11 137/146
145
Ordering information M24LR04E-R
Reference
M24LR04E-R
Table 131. Ordering and marking information
First line marking
Package Ordering code
Initial revision 0xF
Actual revision
0xE and below
TSSOP08
MLP
SO8N
Bare die
M24LR04E-RDW6T/2
M24LR04E-RMC6T/2
M24LR04E-RMN6T/2
M24LR04E-RUW20/2
404EU
404E
4BEUB
4BEB
24L04ER 24LBERB
Not applicable Not applicable
138/146 DocID022208 Rev 11
M24LR04E-R Anticollision algorithm (informative)
Appendix A Anticollision algorithm (informative)
The following pseudocode describes how anticollision could be implemented on the VCD, using recursivity.
A.1 Algorithm for pulsed slots
function push (mask, address); pushes on private stack function pop (mask, address); pops from private stack function pulse_next_pause; generates a power pulse function store(M24LR04E-R_UID); stores M24LR04E-R_UID function poll_loop (sub_address_size as integer) pop (mask, address) mask = address & mask; generates new mask
; send the request mode = anticollision send_Request (Request_cmd, mode, mask length, mask value) for sub_address = 0 to (2^sub_address_size - 1) pulse_next_pause if no_collision_is_detected ; M24LR04E-R is inventoried then store (M24LR04E-R_UID) else ; remember a collision was detected push(mask,address) endif next sub_address if stack_not_empty ; if some collisions have been detected and then ; not yet processed, the function calls itself poll_loop (sub_address_size); recursively to process the last stored collision endif end poll_loop main_cycle: mask = null address = null push (mask, address) poll_loop(sub_address_size) end_main_cycle
DocID022208 Rev 11 139/146
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CRC (informative)
Appendix B CRC (informative)
B.1
M24LR04E-R
CRC error detection method
The cyclic redundancy check (CRC) is calculated on all data contained in a message, from the start of the flags through to the end of Data. The CRC is used from VCD to M24LR04E-
R and from M24LR04E-R to VCD.
CRC type Length
ISO/IEC 13239 16 bits
Table 132. CRC definition
CRC definition
Polynomial
X
16
+ X
12
+ X
5
+ 1 = 8408h
Direction Preset
Backward FFFFh
Residue
F0B8h
To add extra protection against shifting errors, a further transformation on the calculated
CRC is made. The one’s complement of the calculated CRC is the value attached to the message for transmission.
To check received messages, the two CRC bytes are often also included in the recalculation, for ease of use. In this case, the expected value for the generated CRC is the residue F0B8h.
B.2 CRC calculation example
This example in C language illustrates one method of calculating the CRC on a given set of bytes comprising a message.
C-example to calculate or check the CRC16 according to ISO/IEC 13239
#define POLYNOMIAL0x8408// x^16 + x^12 + x^5 + 1
#define PRESET_VALUE0xFFFF
#define CHECK_VALUE0xF0B8
#define NUMBER_OF_BYTES4// Example: 4 data bytes
#define CALC_CRC1
#define CHECK_CRC0 void main()
{
unsigned int current_crc_value;
unsigned char array_of_databytes[NUMBER_OF_BYTES + 2] = {1, 2, 3, 4, 0x91,
0x39};
int number_of_databytes = NUMBER_OF_BYTES;
int calculate_or_check_crc;
int i, j;
calculate_or_check_crc = CALC_CRC;
// calculate_or_check_crc = CHECK_CRC;// This could be an other example
140/146 DocID022208 Rev 11
M24LR04E-R CRC (informative)
if (calculate_or_check_crc == CALC_CRC)
{
number_of_databytes = NUMBER_OF_BYTES;
}
else // check CRC
{
number_of_databytes = NUMBER_OF_BYTES + 2;
}
current_crc_value = PRESET_VALUE;
for (i = 0; i < number_of_databytes; i++)
{
current_crc_value = current_crc_value ^ ((unsigned int)array_of_databytes[i]);
for (j = 0; j < 8; j++)
{
if (current_crc_value & 0x0001)
{
current_crc_value = (current_crc_value >> 1) ^ POLYNOMIAL;
}
else
{
current_crc_value = (current_crc_value >> 1);
}
}
}
if (calculate_or_check_crc == CALC_CRC)
{
current_crc_value = ~current_crc_value;
printf ("Generated CRC is 0x%04X\n", current_crc_value);
// current_crc_value is now ready to be appended to the data stream
// (first LSByte, then MSByte)
}
else // check CRC
{
if (current_crc_value == CHECK_VALUE)
{
printf ("Checked CRC is ok (0x%04X)\n", current_crc_value);
}
else
DocID022208 Rev 11 141/146
145
CRC (informative) M24LR04E-R
{
printf ("Checked CRC is NOT ok (0x%04X)\n", current_crc_value);
}
}
}
142/146 DocID022208 Rev 11
M24LR04E-R Application family identifier (AFI) (informative)
Appendix C Application family identifier (AFI)
(informative)
The AFI (application family identifier) represents the type of application targeted by the VCD and is used to extract from all the M24LR04E-Rs present only the M24LR04E-R meeting the required application criteria.
It is programmed by the M24LR04E-R issuer (the purchaser of the M24LR04E-R). Once locked, it cannot be modified.
The most significant nibble of the AFI is used to code one specific or all application families,
.
The least significant nibble of the AFI is used to code one specific or all application subfamilies. Subfamily codes different from 0 are proprietary.
Table 133. AFI coding (1)
AFI most significant nibble
AFI least significant nibble
‘5’
'6
'7
8
'9
'A
‘0’
‘X’
'X
‘0’
‘1
'2
'3
'4
'B
'C
'D
'E
‘F’
1. X = '1' to 'F', Y = '1' to 'F'
‘0’, ‘Y’
'‘0’, ‘Y’
'‘0’, ‘Y’
'‘0’, ‘Y’
'‘0’, ‘Y’
'‘0’, ‘Y’
‘0’
'0
'‘Y’
‘Y’
'‘0’, ‘Y’
'‘0’, ‘Y’
'‘0’, ‘Y’
'‘0’, ‘Y’
'‘0’, ‘Y’
'‘0’, ‘Y’
'‘0’, ‘Y’
'‘0’, ‘Y’
‘0’, ‘Y’
Meaning
VICCs respond from
Examples / Note
All families and subfamilies No applicative preselection
All subfamilies of family X
Only the Y th
subfamily of family X -
Wide applicative preselection
Proprietary subfamily Y only -
Transport Mass transit, bus, airline,...
Financial
Identification
Telecommunication
Medical
Multimedia
Gaming
Data Storage
Item management
Express parcels
-
-
-
-
IEP, banking, retail,...
Access control,...
Public telephony, GSM,...
Internet services....
Portable files,...
Postal services
Airline bags
RFU
RFU
RFU
-
-
-
-
-
DocID022208 Rev 11 143/146
145
Revision history
Revision history
M24LR04E-R
Date
06-Dec-2011
Revision
1
06-Feb-2012
21-Feb-2012
21-May-2012
12-Jun-2012
21-Feb-2013
07-Mar-2013
12-Jun-2013
04-Nov-2015
2
3
4
5
6
7
8
9
Table 134. Document revision history
Changes
Initial release.
Updated
Table 126: Energy harvesting and added note under the table.
Replaced figures
Changed datasheet status to “Full datasheet”.
Updated
Table 122: I2C AC characteristics
and Section 32: Ordering information .
Updated
Figure 49: M24LR04E-R state transition diagram .
Updated
Table 17: System parameter sector
,
Table 117: Absolute maximum ratings
,
Table 121: I2C DC characteristics
and Table 124: RF characteristics
.
Added
Table 131: Ordering and marking information .
Added “Dynamic NFC/RFID tag IC” to the title, Section 1: Description
, and the M24LR definition in
Table 130: Ordering information scheme for bare die devices or packaged devices
.
Updated wafer legend on cover page.
Updated V
ESD and Note 5 in
Table 117: Absolute maximum ratings .
Removed MB package from Figure 88: UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead 2 × 3mm, package outline .
Updated figure on Cover page with wafer code SB12I.
Updated
Figure 7: I²C timeout on Start condition
,
Figure 10: Write cycle polling flowchart using
Figure 14: 100% modulation waveform and
Figure 15: 10% modulation waveform
.
Updated
Table 119: AC test measurement conditions ,
Ordering information scheme for bare die devices or packaged devices
and Table 131: Ordering and marking information
.
Updated
Section 31: Package information and its subsections.
144/146 DocID022208 Rev 11
M24LR04E-R Revision history
Date
10-May-2016
28-Jul-2017
Table 134. Document revision history (continued)
Revision Changes
10
11
Updated
.
Updated
Table 117: Absolute maximum ratings .
Updated
Figure 51: Description of a possible anticollision sequence and
Figure 53: Stay Quiet frame exchange between VCD and M24LR04E-R .
Added
Section 29: Write cycle definition .
Updated
Figure 8: Write mode sequences with I2C_Write_Lock bit = 1
,
Figure 11: Read mode sequences ,
Figure 45: End of frame, high data rate, two subcarriers
,
Figure 47: M24LR04E-R decision tree for AFI
,
Figure 52: M24LR04E-R RF-Busy management following Inventory command
,
Figure 56: M24LR04E-R RF_Busy management following
and Figure 57: M24LR04E RF_Wip management following Write command .
Added footnote
to
Updated caption of Figure 90: TSSOP8 – 8-lead thin shrink small outline,
3 x 6.4 mm, 0.65 mm pitch, package outline and of
8-lead thin shrink small outline, 3 x 6.4 mm, 0.65 mm pitch, package mechanical data
.
Updated title of
Section 32: Ordering information and added Note:
.
DocID022208 Rev 11 145/146
145
M24LR04E-R
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2017 STMicroelectronics – All rights reserved
146/146 DocID022208 Rev 11
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