STMicroelectronics STM32F410CB Datasheet

1. Refer to Table 44 and RM0401 for the possible PLL VCO setting

and RM0401 for the possible PLL VCO setting

2. Guaranteed by characterization, unless otherwise specified

3. When the ADC is ON (ADON bit set in ADC_CR2), an additional power consumption of 1.6 mA must be added.

4. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is ON (ADON bit is set in the ADC_CR2 register)

5. Guaranteed by tests in production.

DocID028094 Rev 6

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118

Electrical characteristics STM32F410x8/B

Table 22. Typical and maximum current consumption, code with data processing (ART accelerator disabled) running from SRAM - V

= 3.6 V

Typ Max

(2)

Symbol Parameter Conditions f

HCLK

(MHz)

Voltage scale

PLL

VCO

(MHz)

(1)

25 °C

85 °C

105 °C

125 °C

Unit

External clock, all peripherals enabled

(3)(4) 50

100

200 17.7 19.1

(5)

168 14.4 15.3

(5)

128 10.1 10.6

(5)

100

8.0

4.4

8.4

4.7

160 off

3.8

2.5

4.1

2.6

19.3

19.7

20.5

(5)

15.7

16.0

16.8

(5)

11.0

11.3

12.0

(5)

8.8

4.9

9.1

5.2

9.8

5.9

4.3

2.9

4.6

3.2

5.3

4.0

Supply current in

Run mode

HSI, PLL off, all peripherals enabled

(3)(4)

External clock, all peripherals disabled

(3)

100

S3 off 0.4

0.5

200 12.1 13.1

(5)

168 9.8

10.6

(5)

128 7.0

7.4

(5)

100 5.6

5.9

100

160 off

3.1

2.8

1.7

3.3

3.0

1.8

0.8

1.2

2.0

13.1

13.5

14.3

(5)

10.7

11.0

11.8

(5)

7.6

7.9

8.6

(5)

6.1

6.4

7.2

3.5

3.2

2.1

3.9

3.5

2.4

4.8

4.4

3.3

HSI, PLL off, all peripherals disabled

(3) 1 S3 off 0.4

0.4

0.7

1.1

1.8

2. Guaranteed by characterization.

3. When the ADC is ON (ADON bit set in ADC_CR2), an additional power consumption of 1.6 mA must be added.

4. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is ON (ADON bit is set in the ADC_CR2 register)

5. Guaranteed by tests in production.

60/143

DocID028094 Rev 6

STM32F410x8/B Electrical characteristics

Table 23. Typical and maximum current consumption in run mode, code with data processing

(ART accelerator enabled except prefetch) running from Flash memory- V

= 1.7 V

Typ Max

(2)

Symbol Parameter Conditions f

HCLK

(MHz)

Voltage scale

PLL

VCO

(MHz)

(1)

25 °C

85 °C

105 °C

125 °C

Unit

External clock, all peripherals enabled

(3)(4) 50

100

200 15.7

16.5

16.9

168 12.7

13.3

13.4

13.8

128 8.8

9.3

9.4

9.7

100

160 off

7.0

3.9

3.4

2.4

7.4

4.1

3.6

2.5

7.5

4.3

3.8

2.8

7.8

4.7

4.2

3.2

17.8

14.6

10.6

8.6

5.6

5.1

4.1

Supply current in

Run mode

HSI, PLL OFF, all peripherals enabled

(3)(4)

External clock, all peripherals disabled

(3)

1 S3 off 0.6

0.7

1.0

1.4

2.3

100

200 10.1

10.7

10.8

11.2

168 8.2

8.6

8.7

9.1

128

100

5.7

4.6

2.6

6.1

4.9

2.8

6.2

5.0

3.0

6.6

5.4

3.4

160 off

2.4

1.7

2.5

1.8

2.8

2.1

3.1

2.4

12.0

10.0

7.4

6.3

4.3

4.0

3.3

HSI, PLL OFF, all peripherals disabled

(3) 1 S3 off 0.6

0.6

1.0

1.4

2.2

1. Refer to Table 44 and RM0401 for the possible PLL VCO setting

2. Guaranteed by characterization, unless otherwise specified.

3. When the ADC is ON (ADON bit set in ADC_CR2), an additional power consumption of 1.6 mA must be added.

4. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is ON (ADON bit is set in the ADC_CR2 register)

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118

Electrical characteristics STM32F410x8/B

Table 24. Typical and maximum current consumption in run mode, code with data processing

(ART accelerator enabled except prefetch) running from Flash memory - V

= 3.6 V

Typ Max

(2)

Symbol Parameter Conditions f

HCLK

(MHz)

Voltage scale

PLL

VCO

(MHz)

(1)

25 °C

85 °C

105 °C

125 °C

Unit

External clock, all peripherals enabled

(3)(4)

100

200 16.3

17.3

(5)

168 13.2

14.1

128 9.3

10.0

100

160 off

7.4

4.2

3.7

2.4

8.0

4.7

4.2

2.8

17.1

14.0

9.9

8.0

4.8

4.3

3.0

17.5

18.4

(5)

14.3

10.2

15.2

11.1

8.3

5.0

4.6

3.4

9.2

5.9

5.5

4.3

Supply current in

Run mode

HSI, PLL

OFF, all peripherals enabled

(3)(4)

External clock, all peripherals disabled

(3)

100

S3 off 0.6

1.0

200 10.6

11.4

(5)

168

128

100

8.7

6.2

5.0

9.4

6.8

5.5

100

160 off

2.9

2.7

1.7

3.4

3.1

2.1

1.2

11.4

9.3

6.8

5.5

3.5

3.2

2.3

1.5

2.4

11.7

12.6

(5)

9.7

7.1

5.8

10.6

7.9

6.8

3.8

3.5

2.6

4.7

4.4

3.5

HSI, PLL

OFF, all peripherals disabled

(3)

1 S3 off 0.6

0.9

1.1

1.5

2.4

1. Refer to

and RM0401 for the possible PLL VCO setting

2. Guaranteed by characterization, unless otherwise specified.

3. When the ADC is ON (ADON bit set in ADC_CR2), an additional power consumption of 1.6 mA must be added.

4. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is ON (ADON bit is set in the ADC_CR2 register)

5. Guaranteed by tests in production.

62/143

DocID028094 Rev 6

STM32F410x8/B Electrical characteristics

Table 25. Typical and maximum current consumption in run mode, code with data processing

(ART accelerator disabled) running from Flash memory - V

= 3.6 V

Typ Max

(2)

Symbol Parameter Conditions f

HCLK

(MHz)

Voltage scale

PLL

VCO

(MHz)

(1)

25 °C

85 °C

105 °C

125 °C

Unit

External clock, all peripherals enabled

(3)(4) 50

100

200 24.7

26.3

168 21.6

23.0

128 15.9

17.0

100 13.1

14.2

100 7.5

8.2

160 off

6.5

4.7

7.1

5.3

26.5

23.2

17.1

14.3

8.3

7.2

5.5

27.0

23.7

17.6

14.7

8.7

7.5

5.9

28.0

24.7

18.6

15.7

9.7

8.5

6.9

Supply current in

Run mode

HSI, PLL OFF, all peripherals enabled

(3)(4)

External clock, all peripherals disabled

(3)

1 S3 off 0.8

1.2

1.6

1.9

2.9

100

200 19.1

20.5

168 17.1

18.3

128 12.8

13.8

100 10.7

11.7

100 6.3

7.0

160 off

5.4

4.0

6.0

4.5

20.7

18.6

14.0

11.8

7.1

6.2

5.0

21.3

19.1

14.5

12.2

7.4

6.5

5.1

22.3

20.1

15.5

13.2

8.3

7.4

6.0

HSI, PLL OFF, all peripherals disabled

(3) 1 S3 off 0.8

1.1

1.5

1.8

2.7

1. Refer to

1. Refer to Table 44 and RM0401 for the possible PLL VCO setting

and RM0401 for the possible PLL VCO setting

2. Guaranteed by characterization, unless otherwise specified.

3. When the ADC is ON (ADON bit set in ADC_CR2), an additional power consumption of 1.6 mA must be added.

4. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is ON (ADON bit is set in the ADC_CR2 register)

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118

Electrical characteristics STM32F410x8/B

Table 26. Typical and maximum current consumption in run mode, code with data processing

(ART accelerator disabled) running from Flash memory - V

= 1.7 V

Typ Max

(2)

Symbol Parameter Conditions f

HCLK

(MHz)

Voltage scale

PLL

VCO

(MHz)

(1)

25 °C

85 °C

105 °C

125 °C

Unit

External clock, all peripherals enabled

(3)(4) 50

100

200 24.2

26.2

25.7

168 20.0

21.8

21.4

128 15.8

17.2

17.0

100 13.3

16.5

14.4

100 7.5

9.5

8.3

160 off

6.7

5.1

8.2

6.4

7.3

5.7

26.5

22.1

17.7

15.0

8.8

7.7

6.2

27.6

23.1

18.7

16.0

9.8

8.6

7.1

Supply current in

Run mode

HSI, PLL OFF, all peripherals enabled

(3)(4)

External clock, all peripherals disabled

(3)

1 S3 off 0.8

1.0

1.3

1.7

2.6

100

200 18.6

23.0

23.4

168 15.5

19.3

19.9

128 12.7

16.1

16.7

100 10.9

13.9

14.3

100 6.3

8.1

8.4

160 off

5.6

4.3

7.2

5.5

7.3

5.8

23.9

20.4

17.0

14.7

8.7

7.6

6.2

24.9

21.4

18.0

15.7

9.7

8.4

7.1

HSI, PLL OFF, all peripherals disabled

(3) 1 S3 off 0.8

1.0

1.3

1.6

2.5

2. Guaranteed by characterization, unless otherwise specified.

3. When the ADC is ON (ADON bit set in ADC_CR2), an additional power consumption of 1.6 mA must be added.

4. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is ON (ADON bit is set in the ADC_CR2 register)

64/143

DocID028094 Rev 6

STM32F410x8/B Electrical characteristics

Table 27. Typical and maximum current consumption in run mode, code with data processing

(ART accelerator enabled with prefetch) running from Flash memory - V

= 3.6 V

Typ Max

(2)

Symbol Parameter Conditions f

HCLK

(MHz)

Voltage scale

PLL

VCO

(MHz)

(1)

25 °C

85 °C

105 °C

125 °C

Unit

External clock, all peripherals enabled

(3)(4) 50

100

200 27.1

28.9

168 23.2

24.8

24.9

128 17.0

18.3

18.4

100 13.6

14.7

100 7.5

8.2

8.3

160 off

6.5

4.7

7.1

5.3

7.2

5.5

29.5

25.5

18.8

15.2

8.7

7.5

5.9

30.5

26.5

19.8

16.2

9.7

8.5

6.9

Supply current in

Run mode

HSI, PLL OFF, all peripherals enabled

(3)(4) 1 S3 off 0.8

1.2

1.4

1.8

2.8

External clock, all peripherals disabled

(3)

100

200 21.5

23.0

23.2

168 18.7

20.0

20.3

128 14.0

15.1

15.2

100 11.2

12.2

12.3

100 6.3

7.0

7.1

160 off

5.4

4.0

6.0

4.5

6.2

4.8

23.8

20.8

15.7

12.7

7.4

6.5

5.1

24.8

21.8

16.7

13.7

8.4

7.5

6.1

HSI, PLL OFF, all peripherals disabled

(3) 1 S3 off 0.8

1.1

1.4

1.7

2.7

1. Refer to

Table 44 and RM0401 for the possible PLL VCO setting

and RM0401 for the possible PLL VCO setting

2. Guaranteed by characterization, unless otherwise specified.

3. When the ADC is ON (ADON bit set in ADC_CR2), an additional power consumption of 1.6 mA must be added.

4. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is ON (ADON bit is set in the ADC_CR2 register) mA

DocID028094 Rev 6

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118

Electrical characteristics STM32F410x8/B

Table 28. Typical and maximum current consumption in Sleep mode - V

= 3.6 V

Symbol Parameter Conditions f

HCLK

(MHz)

Voltage scale

PLL

VCO

(MHz)

(1)

Typ

25 °C

Max

(2)

85 °C

105 °C

125 °C

Unit

Supply current in

Sleep mode

All peripherals enabled

(3)(4)

External clock,

PLL ON, Flash memory in Deep power down mode

All peripherals enabled

(3)(4)

HSI, PLL OFF,

Flash memory in

Deep power down mode

100

200

168

128

100

160 off off

3.7

2.2

2.1

1.1

8.0

8.2

(5)

6.5

4.6

6.7

4.7

3.9

2.3

2.2

1.2

0.3

0.4

4.3

2.6

2.5

1.5

9.0

7.4

5.2

0.7

4.6

2.9

2.8

1.9

9.4

10.2

(5)

7.7

5.5

8.5

6.3

5.4

3.8

3.6

2.7

1.1

1.9

All peripherals enabled

(3)(4)

External clock,

PLL ON, Flash memory ON

All peripherals enabled

(3)

, HSI,

PLL OFF, Flash memory ON

100

200

168

128

100

160 off off

8.4

6.9

4.9

4.0

2.5

2.4

1.4

0.6

8.7

7.1

5.1

4.2

2.6

2.5

1.4

0.6

9.5

7.7

5.5

4.6

2.9

2.7

1.8

1.0

9.9

8.1

5.9

4.9

3.2

3.1

2.2

1.3

10.7

8.9

6.7

5.7

4.0

3.9

3.0

2.0

66/143

DocID028094 Rev 6

STM32F410x8/B Electrical characteristics

Table 28. Typical and maximum current consumption in Sleep mode - V

= 3.6 V (continued)

Symbol Parameter Conditions f

HCLK

(MHz)

Voltage scale

PLL

VCO

(MHz)

(1)

Typ

25 °C

Max (2)

85 °C

105 °C

125 °C

Unit

(continued)

Supply current in

Sleep mode

(continued)

All peripherals disabled,

External clock,

PLL ON, Flash memory in Deep power down mode

All peripherals disabled, HSI,

PLL OFF, Flash memory in Deep power down mode

100

200

168

128

100

160 off off

1.2

0.9

1.0

0.3

2.2

2.3

(5)

1.8

1.4

1.9

1.5

1.3

1.0

1.2

0.4

0.3

1.6

1.3

1.4

0.7

2.6

2.2

1.8

0.7

1.9

1.7

1.1

3.0

2.6

2.1

1.0

3.8

(5)

3.4

2.9

2.7

2.5

1.9

1.8

All peripherals disabled,

External clock,

PLL ON, Flash memory ON

100

200

168

128

100

160 off

2.6

2.2

1.8

1.5

1.2

1.3

0.6

2.7

2.3

1.9

1.6

1.4

0.6

3.0

2.6

2.1

1.9

1.6

1.7

1.0

3.4

3.0

2.5

2.2

2.0

1.3

4.2

3.8

3.3

3.1

2.8

2.0

All peripherals disabled, HSI,

PLL OFF, Flash memory in Deep power down mode

1 S3 off 0.5

0.6

0.9

1.3

2.0

1. Refer to

2. Guaranteed by characterization, unless otherwise specified.

3. When the ADC is ON (ADON bit set in ADC_CR2), an additional power consumption of 1.6 mA must be added.

4. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is ON (ADON bit is set in the ADC_CR2 register)

5. Guaranteed by tests in production.

DocID028094 Rev 6

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118

Electrical characteristics STM32F410x8/B

Table 29. Typical and maximum current consumption in Sleep mode - V

= 1.7 V

Typ Max

(2)

Symbol Parameter Conditions f

HCLK

(MHz)

Voltage scale

PLL

VCO

(MHz)

(1)

25 °C

85 °C

105 °C

125 °C

Unit

All peripherals enabled

(3) (4)

External clock,

PLL ON, Flash memory in

Deep power down mode

100

200

168

128

100

160 off

2.0

1.8

1.1

7.7

6.2

4.3

3.4

2,1

1,9

1,2

7,9

6,4

4,5

3,6

2,4

2,3

1,5

8,8

7,1

5,0

4,0

2,7

2,6

1,9

9,2

7,5

5,3

4,4

10.0

8.3

6.1

5.2

3.5

3.4

2.7

Supply current in

Sleep mode

All peripherals enabled

(3)(4)

HSI, PLL OFF,

Flash memory in Deep power down mode

1 S3 off 0.3

0,4 0,7 1,0 1.8

All peripherals enabled

(3)(4)

External clock,

PLL ON, Flash memory ON

100

200

168

128

100

160 off

8.1

6.6

4.7

3.8

2.3

2.1

1.4

8,4

6,8

4,8

3,9

2,4

2,2

1,5

9,3

7,5

5,4

4,4

2,7

2,6

1,8

9,7

7,9

5,7

4,7

3,1

2,9

2,2

10.5

8.7

6.5

5.5

3.9

3.7

3.0

All peripherals enabled

(3)(4)

HSI, PLL OFF,

Flash memory

1 S3 off 0.5

0,6 1,0 1,3 2.0

68/143

DocID028094 Rev 6

STM32F410x8/B Electrical characteristics

Table 29. Typical and maximum current consumption in Sleep mode - V

= 1.7 V (continued)

Typ Max (2)

Symbol Parameter Conditions f

HCLK

(MHz)

Voltage scale

PLL

VCO

(MHz)

(1)

25 °C

85 °C

105 °C

125 °C

Unit

All peripherals disabled,

External clock,

PLL ON, Flash memory in

Deep power down mode

100

200

168

128

100

160 off

0.7

0.8

0.3

1.9

1.6

1.1

0.9

0,8

0,4

2,0

1,7

1,2

1,0

1,1

1,2

0,7

2,4

2,0

1,5

1,3

1,4

1,5

1,0

2,7

2,4

1,9

1,7

2.2

2.3

1.8

3.5

3.2

2.7

2.5

(continued)

Supply current in

Sleep mode

(continued)

All peripherals disabled, HSI,

PLL OFF, Flash memory in

Deep power down mode

All peripherals disabled,

External clock,

PLL ON, Flash memory ON

100

S3 off

200

168

128

100

0.2

2.3

2.0

1.5

1.3

1.0

0,3

2,4

2,1

1,6

1,4

1,1

0,6

2,9

2,4

1,9

1,7

1,4

1,0

3,3

2,8

2,3

2,0

1,7

1.8

4.0

3.6

3.1

2.8

2.5

All peripherals disabled, HSI,

PLL OFF, Flash memory in

Deep power down mode

160 off off

1.0

0.6

0.5

1,2

0,6

1,5

1,0

0,9

1,8

1,4

1,3

2.6

2.1

2.0

1. Refer to Table 44 and RM0401 for the possible PLL VCO setting

2. Guaranteed by characterization, unless otherwise specified.

3. When the ADC is ON (ADON bit set in ADC_CR2), an additional power consumption of 1.6 mA must be added.

4. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is ON (ADON bit is set in the ADC_CR2 register) mA

DocID028094 Rev 6

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118

Electrical characteristics STM32F410x8/B

Symbol

Table 30. Typical and maximum current consumptions in Stop mode - V

= 1.7 V

Typ Max

Conditions

25 °C

(1)

85 °C

105 °C

(1)

125 °C

(1)

Unit

1270.0

DD_STOP

Flash in Stop mode, all oscillators OFF, no independent watchdog

Main regulator usage 105.6

Low power regulator usage 39.5

117.1

48.7

385.1

287.5

665.7

548.4

Flash in Deep power down mode, all oscillators OFF, no independent watchdog

Main regulator usage

Low power regulator usage

Low power low voltage regulator usage

77.8

11.0

6.1

87.5

351.3

630.1

20.0

254.2

512.0

13.6

217.0

442.5

1. Guaranteed by characterization.

1070.0

1222.0

1006.0

941.0

µA

Symbol

Table 31. Typical and maximum current consumption in Stop mode - V

=3.6 V

Typ Max

Conditions

25 °C

(1)

85 °C

105 °C

(1)

125 °C

(1)

Unit

DD_STOP

Flash in Stop mode, all oscillators OFF, no independent watchdog

Main regulator usage 108.6

126 (2)

Low power regulator usage 41.03

50.31

(2)

Flash in Deep power down mode, all oscillators OFF, no independent watchdog

Main regulator usage 80.32

94.0

(2)

Low power regulator usage 12.41

21.5

(2)

Low power low voltage regulator usage

7.53

15.2

(2)

392.8

675.4

1280.0

(2)

290.9

554.2

1077.0

(2)

357.0

639.5

1232.0

(2)

258.1

518.1

1010.0

(2)

221.6

449.2

947.0

(2)

µA

1. Guaranteed by characterization.

2. Guaranteed by tests in production.

Symbol

Table 32. Typical and maximum current consumption in Standby mode - V

= 1.7 V

Typ Max

Parameter Conditions

25 °C

(1)

85 °C

105 °C

(1)

125 °C

(1)

Unit

DD_STBY

Supply current in Standby mode

Low-speed oscillator (LSE) and RTC ON

RTC and LSE OFF

1. Guaranteed by characterization, unless otherwise specified.

2.1

1.2

2.9

1.9

6.5

5.5

18.2

17.1

60.0

59.0

µA

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STM32F410x8/B Electrical characteristics

Table 33. Typical and maximum current consumption in Standby mode - V

= 3.6 V

Typ Max

Symbol Parameter Conditions

25 °C

(1)

85 °C

105 °C

(1)

125 °C

(1)

Uni t

DD_STBY

Supply current in Standby mode

Low-speed oscillator (LSE) and RTC ON

RTC and LSE OFF

1. Guaranteed by characterization, unless otherwise specified.

2. Guaranteed by tests in production.

3.4

2.5

4.3

3.3

(2)

8.9

7.8

22.8

21.6

65.0

64.0

(2)

µA

Table 34. Typical and maximum current consumptions in V

BAT

(LSE and RTC ON, LSE low- drive mode)

mode

Typ Max

(2)

Symbol Parameter Conditions

(1)

= 25 °C

BAT

1.7 V

BAT

2.4 V

= V

BAT

3.3 V

DD_VBAT

Backup domain supply current

Low-speed oscillator (LSE in low-drive mode) and RTC ON

Low-speed oscillator (LSE in high-drive mode) and RTC ON

RTC and LSE OFF

0.7

1.4

0.8

1.6

1.1

1.9

0.1

1. Crystal used: Abracon ABS07-120-32.768 kHz-T with a C

of 6 pF for typical values.

2. Guaranteed by characterization.

85 °C

105 °C

125 °C

2.8

4.2

2.0

BAT

= 3.6 V

4.2

7.0

4.0

5.6

8.6

5.8

Unit

µA

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118

Electrical characteristics STM32F410x8/B

Figure 16. Typical V

BAT

current consumption (LSE and RTC ON/LSE oscillator in “low power” mode selection

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06Y9

Figure 17. Typical V

BAT

current consumption (LSE and RTC ON/LSE oscillator in “high-drive” mode selection)

72/143

7HPSHUDWXUH&

06Y9

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in

Table 55: I/O static characteristics .

For the output pins, any external pull-down or external load must also be considered to estimate the current consumption.

Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt

DocID028094 Rev 6

STM32F410x8/B Electrical characteristics trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs.

Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode.

I/O dynamic current consumption

In addition to the internal peripheral current consumption (see Table 36: Peripheral current consumption ), the I/Os used by an application also contribute to the current consumption.

When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin:

=

×

C where

is the current sunk by a switching I/O to charge/discharge the capacitive load

is the MCU supply voltage f

is the I/O switching frequency

C is the total capacitance seen by the I/O pin: C = C

INT

+ C

EXT

The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency.

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118

Electrical characteristics STM32F410x8/B

Table 35. Switching output I/O current consumption

Symbol Parameter Conditions

(1)

I/O toggling

frequency (f

)

Typ Unit

= 3.3 V

C = C

INT

2 MHz

8 MHz

25 MHz

50 MHz

60 MHz

84 MHz

90 MHz

C = C

INT

= 3.3 V

EXT

= 0 pF

+ C

EXT

+ C

2 MHz

8 MHz

25 MHz

50 MHz

60 MHz

84 MHz

90 MHz

2 MHz

IDDIO

I/O switching current

C = C

EXT

INT

= 3.3 V

=10 pF

+ C

EXT

+ C

8 MHz

25 MHz

50 MHz

60 MHz

0.65

1.85

2.45

4.70

84 MHz

90 MHz

2 MHz

8 MHz

8.80

10.47

0.25

1.00

= 3.3 V

C = C

EXT

INT

= 22 pF

+ C

EXT

+ C

25 MHz

50 MHz

3.45

7.15

60 MHz

2 MHz

11.55

0.32

= 3.3 V

EXT

= 33 pF

C = C

INT

+ C

EXT

+ C

8 MHz

25 MHz

1.27

3.88

50 MHz

1. CS is the PCB board capacitance including the pad pin. CS = 7 pF (estimated value).

12.34

2.40

3.55

4.23

0.20

0.10

0.35

1.05

2.20

0.05

0.15

0.45

0.85

1.00

1.40

1.67

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STM32F410x8/B Electrical characteristics

On-chip peripheral current consumption

The MCU is placed under the following conditions:

• At startup, all I/O pins are in analog input configuration.

• All peripherals are disabled unless otherwise mentioned.

• The ART accelerator is ON.

• Voltage Scale 2 mode selected, internal digital voltage V12 = 1.26 V.

• HCLK is the system clock at 100 MHz. f

PCLK1

= f

HCLK

/2, and f

PCLK2

= f

HCLK

The given value is calculated by measuring the difference of current consumption

– with all peripherals clocked off

– with only one peripheral clocked on

• Ambient operating temperature is 25 °C and V

=3.3 V.

AHB 1

(up to 100 MHz)

APB1

(up to 50 MHz)

Table 36. Peripheral current consumption

(Typ)

Peripheral

Voltage scale1

Voltage scale2

GPIOA

GPIOB

GPIOC

GPIOH

CRC

DMA1

(1)

DMA2

(1)

RNG

APB1 to AHB

TIM5

TIM6

LPTIM

WWDG

SPI2/I2S2

USART2

I2C1

I2C2

I2C4

PWR

DAC

8,22

0,64

2,42

3,38

3,46

3,50

4,82

0,66

0,84

1.68

1.67

1.63

0.61

0.31

1.67N +

3.12

1.59N +

2.83

0.90

0,78

13,38

2,14

7,88

0,64

2,33

3,29

3,33

3,31

4,64

0,64

0,81

1.62

1.60

1.56

0.61

0.32

1.60N +

2.96

1.52N +

2.65

0.88

0,74

12,76

1,98

Unit

µA/MHz

Voltage scale3

7,06

0,56

2,06

2,91

2,97

4,09

0,62

0,78

1.42

1.41

1.39

0.52

0.25

1.43N +

2.64

1.36N +

2.41

0.75

0,63

11,41

1,75

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118

Electrical characteristics STM32F410x8/B

Table 36. Peripheral current consumption (continued)

(Typ)

Peripheral

Voltage scale1

Voltage scale2

Voltage scale3

APB2

(up to 100 MHz)

APB2 to AHB

TIM1

USART1

USART6

ADC1

SPI1/I2S1

SYSCFG

EXTI

0,22

6,62

3,19

3,10

3,35

1,82

0,83

0,92

0,19

6,36

3,10

2,99

3,25

1,77

0,81

0,88

TIM9

TIM11

2,90

2,13

2,81

2,06

2,48

1,81

Bus matrix

SPI5/I2S5 1,88

1.91

1,83

1.82

1. Valid if all the DMA streams are activated (please refer to the reference manual RM0401).

1,59

1.64

2,88

1,58

0,72

0,80

0,17

5,66

2,77

2,66

Unit

µA/MHz

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STM32F410x8/B

6.3.7 Wakeup time from low-power modes

Electrical characteristics

The wakeup times given in Table 37

are measured starting from the wakeup event trigger up to the first instruction executed by the CPU:

• For Stop or Sleep modes: the wakeup event is WFE.

• WKUP (PA0) pin is used to wakeup from Standby, Stop and Sleep modes.

Figure 18. Low-power mode wakeup

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069

All timings are derived from tests performed under ambient temperature and V

=3.3 V.

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118

Electrical characteristics STM32F410x8/B

Symbol

Table 37. Low-power mode wakeup timings (1)

Parameter Conditions Min Typ Max Unit t t

WUSLEEPFDSM

(2) t

WUSLEEP

(2)

WUSTOP

(2)

Wakeup from Sleep mode

Flash memory in Deep power down mode

Main regulator

Wakeup from Stop mode, code execution from Flash memory

Main regulator, Flash memory in Deep power down mode

Regulator in low-power mode

(3)

Regulator in low-power mode,

Flash memory in Deep power down mode t

WUSTDBY

(2)(4) t

WUFLASH

Wakeup from Stop mode, code execution from RAM

Main regulator, Flash memory in Stop or Deep power down mode

Regulator in low-power mode,

Flash memory in Stop or Deep

power down mode

(3)

Wakeup from Standby mode

Wakeup of Flash memory From Flash_Stop mode

Wakeup of Flash memory

From Flash Deep power down mode

12.9

104.9

20.8

112.9

4.9

12.8

316.8

40,0

15.0

115.0

25.0

120.0

7.0

20.0

350.0

10.0

40.0

CPU clock cycles

µs

1. Guaranteed by characterization.

2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first instruction.

3. The specification is valid for wakeup from regulator in low power mode or in low power low voltage mode, since the timing difference is negligible.

4. t

WUSTDBY maximum value is given at - 40 °C.

High-speed external user clock generated from an external source

In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O. The

external clock signal has to respect the Table 55

. However, the recommended clock input

waveform is shown in Figure 19 .

The characteristics given in

Table 38 result from tests performed using an high-speed

external clock source, and under ambient temperature and supply voltage conditions summarized in

external clock signal has to respect the Table 55

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STM32F410x8/B Electrical characteristics

Symbol

Table 38. High-speed external user clock characteristics

Parameter f

HSE_ext

External user clock source frequency

(1)

HSEH

HSEL t w(HSE) t w(HSE) t r(HSE) t f(HSE)

C in(HSE)

DuCy

(HSE)

OSC_IN input pin high level voltage

OSC_IN input pin low level voltage

OSC_IN high or low time

OSC_IN rise or fall time

(1)

OSC_IN input capacitance

Duty cycle

(1)

OSC_IN Input leakage current

1. Guaranteed by design.

Conditions

≤ V

Min

0.7V

Typ

Max Unit

0.3V

±1

MHz

V ns pF

µA

Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The

. However, the recommended clock input

waveform is shown in Figure 20 .

The characteristics given in

Table 39 result from tests performed using an low-speed

external clock source, and under ambient temperature and supply voltage conditions summarized in

characterization results obtained with typical external components specified in Table 40

Symbol

Table 39. Low-speed external user clock characteristics

Parameter f

LSE_ext

LSEH

User External clock source frequency

(1)

OSC32_IN input pin high level voltage

LSEL t w(LSE) t f(LSE) t r(LSE) t f(LSE)

C in(LSE)

DuCy

(LSE)

OSC32_IN input pin low level voltage

OSC32_IN high or low time

OSC32_IN rise or fall time

(1)

OSC32_IN input capacitance

Duty cycle

(1)

OSC32_IN Input leakage current

1. Guaranteed by design.

Conditions

≤ V

Min

0.7V

450

Typ

32.768

Max

1000

0.3V

±1

Unit kHz

V ns pF

µA

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118

Electrical characteristics STM32F410x8/B

Figure 19. High-speed external clock source AC timing diagram

6(3%(

6(3%,

TR(3%

4(3%

TF(3%

%XTERNAL

CLOCKSOURCE

F(3%?EXT

/3#?).

T7(3%

34-&

T7(3% T

Figure 20. Low-speed external clock source AC timing diagram

9/6(+

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7/6(

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([WHUQDO

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670)

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on

. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

80/143

DocID028094 Rev 6

STM32F410x8/B

Note:

Electrical characteristics

Symbol

Table 40. HSE 4-26 MHz oscillator characteristics (1)

Parameter Conditions Min Typ Max Unit f

OSC_IN

Oscillator frequency

Feedback resistor -

200

MHz k Ω

HSE current consumption

=3.3 V,

ESR= 30 Ω ,

=5 pF @25 MHz

=3.3 V,

ESR= 30 Ω ,

=10 pF @25 MHz

Startup

450

530 -

µA

G m_crit_max t

SU(HSE)

(2)

Maximum critical crystal g

Startup time m

is stabilized -

mA/V ms

1. Guaranteed by design.

2. t

SU(HSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer

For C

and C

, it is recommended to use high-quality external ceramic capacitors in the

5 pF to 25 pF range (Typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see

Figure 21

). C

and C

L2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C

and C

. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing

and C

For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com

Figure 21. Typical application with an 8 MHz crystal

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EXT

value depends on the crystal characteristics.

Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on

characterization results obtained with typical external components specified in Table 41

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118

Electrical characteristics

Note:

STM32F410x8/B

The LSE high-power mode allows to cover a wider range of possible crystals but with a cost of higher power consumption.

Symbol

Table 41. LSE oscillator characteristics (f

LSE

= 32.768 kHz) (1)

Parameter Conditions Min Typ Max Unit

M Ω

Feedback resistor

LSE current consumption

Low-power mode

(default)

High-drive mode

18.4

Startup, low-power mode

0.56

G m

_crit_max Maximum critical crystal g m

Startup, high-drive mode

1.50

SU(LSE)

(2) startup time V

is stabilized 2 -

1. Guaranteed by design.

2. t

SU(LSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized

32.768 kHz oscillation is reached. This value is guaranteed by characterization. It is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

µA

µA/V s

For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com

For information about the LSE high-power mode, refer to the reference manual RM0401.

Figure 22. Typical application with a 32.768 kHz crystal

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STM32F410x8/B

6.3.9 Internal clock source characteristics

Electrical characteristics

The parameters given in

Table 42 and

Table 43 are derived from tests performed under

ambient temperature and V

supply voltage conditions summarized in

Table 15

High-speed internal (HSI) RC oscillator

Symbol

Table 42. HSI oscillator characteristics (1)

Parameter Conditions

I t f

HSI

ACC

HSI su(HSI)

(2)

DD(HSI)

(2)

Frequency -

Accuracy of the HSI oscillator

User-trimmed with the RCC_CR register

(2)

Factorycalibrated

= –40 to 125 °C (3)

= –10 to 85 °C

(3)

= 25 °C

(4)

HSI oscillator startup time

HSI oscillator power consumption

1. V

= 3.3 V, T

= –40 to 125 °C unless otherwise specified.

2. Guaranteed by design.

3. Guaranteed by characterization.

4. Factory calibrated non-soldered parts.

Min Typ Max Unit

–8

–4

–1

2.2

5.5

MHz

µs

µA

Figure 23. ACC

HSI

versus temperature

-IN

-AX

4YPICAL

4! #

-36

1. Guaranteed by characterization.

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118

Electrical characteristics

Low-speed internal (LSI) RC oscillator

Table 43. LSI oscillator characteristics

(1)

Symbol Parameter f

LSI

(2) t su(LSI)

(3)

DD(LSI)

(3)

Frequency

LSI oscillator startup time

LSI oscillator power consumption

1. V

= 3 V, T

= –40 to 125 °C unless otherwise specified.

2. Guaranteed by characterization.

3. Guaranteed by design.

Min

Typ

0.4

Figure 24. ACC

LSI

versus temperature

STM32F410x8/B

Max

0.6

Unit kHz

µs

µA

MAX

AVG

MIN

4EMPERAT URE #

-36

The parameters given in

Table 44 are derived from tests performed under temperature and

supply voltage conditions summarized in

Table 15

Symbol f

PLL_IN f

PLL_OUT f

PLL48_OUT f

VCO_OUT

Table 44. Main PLL characteristics

Parameter Conditions Min

PLL input clock

(1)

PLL multiplier output clock

48 MHz PLL multiplier output clock

PLL VCO output -

0.95

(2)

100

Typ

Max

2.10

100

432

Unit

MHz

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STM32F410x8/B Electrical characteristics

Symbol

Table 44. Main PLL characteristics (continued)

Parameter Conditions Min Typ Max Unit t

LOCK

Jitter

(3)

PLL lock time

Cycle-to-cycle jitter

Period Jitter

VCO freq = 100 MHz

VCO freq = 432 MHz

System clock

100 MHz

RMS peak to peak

100

150

200

300

µs ps

DD(PLL)

(4)

DDA(PLL)

(4)

PLL power consumption on VDD

PLL power consumption on

VDDA

VCO freq = 100 MHz

VCO freq = 432 MHz

0.15

0.45

0.30

0.55

0.40

0.75

0.40

0.85

VCO freq = 100 MHz

VCO freq = 432 MHz

1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared between PLL and PLLI2S.

2. Guaranteed by design.

3. The use of two PLLs in parallel could degraded the Jitter up to +30%.

4. Guaranteed by characterization.

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Electrical characteristics STM32F410x8/B

6.3.11 PLL spread spectrum clock generation (SSCG) characteristics

The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic

interferences (see Table 51: EMI characteristics for LQFP64 ). It is available only on the

main PLL.

Symbol f

Mod md

MODEPER * INCSTEP

1. Guaranteed by design.

Table 45. SSCG parameter constraints

Parameter Min

Modulation frequency

Peak modulation depth

(Modulation period) * (Increment Step)

0.25

Typ

Max

(1)

-1

Unit kHz

Equation 1

The frequency modulation period (MODEPER) is given by the equation below:

MODEPER = [

PLL_IN

⁄ ( 4 × f

Mod

) ] f

PLL_IN and f

Mod must be expressed in Hz.

As an example:

If f

PLL_IN

= 1 MHz, and f

MOD

= 1 kHz, the modulation depth (MODEPER) is given by equation 1:

MODEPER

= round 10

⁄ ( 4 × 10

) ] =

250

Equation 2

Equation 2 allows to calculate the increment step (INCSTEP):

INCSTEP = round [ ( ( 2

– 1 ) × md × PLLN ) ⁄ ( 100 × 5 × MODEPER ) ] f

VCO_OUT must be expressed in MHz.

With a modulation depth (md) = ± 2 % (4 % peak to peak), and PLLN = 240 (in MHz):

INCSTEP

= round [ ( ( 2

–

1 ) × 2 × 240 ) ⁄ ( 100 × 5 × 250 ) ]

126md(quantitazed)%

An amplitude quantization error may be generated because the linear modulation profile is obtained by taking the quantized values (rounded to the nearest integer) of MODPER and

INCSTEP. As a result, the achieved modulation depth is quantized. The percentage quantized modulation depth is given by the following formula: md quantized

% = ( MODEPER × INCSTEP × 100 × 5 ) ⁄ ( ( 2

– 1 ) × PLLN )

As a result: md quantized

( 250 × 126 × 100 × 5 ) ⁄ ( ( 2

–

1 ) × 240 )

2.002%(peak)

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STM32F410x8/B Electrical characteristics

Figure 25

and

Figure 26 show the main PLL output clock waveforms in center spread and

down spread modes, where:

F0 is f

PLL_OUT

nominal.

T mode

is the modulation period.

md is the modulation depth.

Figure 25. PLL output clock waveforms in center spread mode

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TMODE XTMODE

4IME

Figure 26. PLL output clock waveforms in down spread mode

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Symbol

Flash memory

The characteristics are given at T

= – 40 to 125 °C unless otherwise specified.

The devices are shipped to customers with the Flash memory erased.

Parameter

Supply current

Table 46. Flash memory characteristics

Conditions Min

Write / Erase 8-bit mode, V

= 1.7 V

Write / Erase 16-bit mode, V

= 2.1 V

Write / Erase 32-bit mode, V

= 3.3 V -

Typ

Max

Unit mA

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Electrical characteristics STM32F410x8/B

Symbol

Table 47. Flash memory programming

Parameter Conditions t t t prog

ERASE16KB

ERASE64KB

V t

ME prog

Word programming time

Sector (16 KB) erase time

Sector (64 KB) erase time

Mass erase time

Programming voltage

Program/erase parallelism

(PSIZE) = x 8/16/32

Program/erase parallelism

(PSIZE) = x 8

Program/erase parallelism

(PSIZE) = x 16

Program/erase parallelism

(PSIZE) = x 32

Program/erase parallelism

(PSIZE) = x 8

Program/erase parallelism

(PSIZE) = x 16

Program/erase parallelism

(PSIZE) = x 32

Program/erase parallelism

(PSIZE) = x 8

Program/erase parallelism

(PSIZE) = x 16

Program/erase parallelism

(PSIZE) = x 32

32-bit program operation

16-bit program operation

8-bit program operation

1. Guaranteed by characterization.

2. The maximum programming time is measured after 100K erase operations.

Min

(1)

2.7

2.1

1.7

Typ Max

(1)

Unit

16 100

(2)

400

300

250

1.4

800

600

500

1200 2400

700 1400

550 1100

2.8

3.6

µs ms ms s

Symbol

Table 48. Flash memory programming with V

PP voltage

Parameter Conditions Min

(1)

Typ Max

(1) t prog t

ERASE16KB t

ERASE64KB t

ERASE128KB t

V prog

PP t

VPP

(3)

Double word programming

Sector (16 KB) erase time

Sector (64 KB) erase time

Sector (128 KB) erase time

Mass erase time

Programming voltage

voltage range

Minimum current sunk on the V

Cumulative time during which V

PP is applied

= 0 to +40 °C

= 3.3 V

= 8.5 V

2.7

230

490

875

3.50

100 (2)

3.6

Unit

µs ms s

V mA hour

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STM32F410x8/B Electrical characteristics

1. Guaranteed by design.

2. The maximum programming time is measured after 100K erase operations.

3. V

should only be connected during programming/erasing.

Symbol

Table 49. Flash memory endurance and data retention

Value

Parameter Conditions

Min (1)

END tRET

Endurance

Data retention

= - 40 to +85 °C (6 suffix versions)

= - 40 to +105 °C (7 suffix versions)

= - 40 to +125 °C (3 suffix versions)

1 kcycle

(2)

at T

= 85 °C

1 kcycle

(2)

at T

= 105 °C

1 kcycle

(2)

at T

= 125 °C

10 kcycle

(2)

at T

= 55 °C

1. Guaranteed by characterization.

2. Cycling performed over the whole temperature range.

Unit

Kcycle

Years

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

• FTB : A burst of fast transient voltage (positive and negative) is applied to V

and V

SS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed.

The test results are given in

Table 51

. They are based on the EMS levels and classes defined in application note AN1709.

Symbol

Table 50. EMS characteristics

Parameter Conditions

Level/

Class

FESD

EFTB

Voltage limits to be applied on any I/O pin to induce a functional disturbance

Fast transient voltage burst limits to be applied through 100 pF on V

and V

SS pins to induce a functional disturbance f

= 3.3 V, LQFP64, T

HCLK

IEC 61000-4-2

= +25 °C,

= 100 MHz, conforms to

= 3.3 V, LQFP64, T

A f

HCLK

IEC 61000-4-4

= +25 °C,

= 100 MHz, conforms to

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Electrical characteristics STM32F410x8/B

In noisy environments, it is recommended to avoid pin exposition to disturbances. The pins showing a middle range robustness are PA14 and PA15.

As a consequence, it is recommended to add a serial resistor (1 k Ω maximum) located as close as possible to the MCU pins exposed to noise (connected to tracks longer than 50 mm on PCB).

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

• Corrupted program counter

• Unexpected reset

• Critical Data corruption (control registers...)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application, executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2 standard which specifies the test board and the pin loading.

Table 51. EMI characteristics for LQFP64

Symbol Parameter

EMI

Conditions

Monitored frequency band

Peak level

= 3.6 V, T

= 25 °C, conforming to

IEC61967-2

0.1 to 30 MHz

30 to 130 MHz

130 MHz to 1 GHz

SAE EMI Level

Max vs.

HSE

CPU

]

8/100 MHz

2.5

Unit dBµV

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6.3.14 Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.

Symbol

ESD(HBM)

ESD(CDM)

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard.

Table 52. ESD absolute maximum ratings

(1)

Ratings Conditions Class

Maximum value

(2)

Unit

Electrostatic discharge voltage (human body model)

= +25 °C conforming to

ANSI/JEDEC JS-001

2 2000

Electrostatic discharge voltage (charge device model)

= +25 °C conforming to

ANSI/ESD STM5.3.1

UFQFPN48

WLCSP36

LQFP48

LQPF64

UFBGA64

TBD

500

250

500

TBD

1. TBD stands for “to be defined”.

2. Guaranteed by characterization.

Symbol

Static latchup

Two complementary static tests are required on six parts to assess the latchup performance:

• A supply overvoltage is applied to each power supply pin

• A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD 78A IC latchup standard.

Parameter

Static latch-up class

Table 53. Electrical sensitivities

Conditions

= +125 °C conforming to JESD78A

Class

II level A

As a general rule, current injection to the I/O pins, due to external voltage below V

SS above V

(for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.

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Electrical characteristics

Note:

STM32F410x8/B

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (>5

LSB TUE), out of conventional limits of induced leakage current on adjacent pins

(out of –5 µA/+0 µA range), or other functional failure (for example reset, oscillator frequency deviation).

Negative induced leakage current is caused by negative injection and positive induced leakage current by positive injection.

The test results are given in

Table 54

Symbol

Table 54. I/O current injection susceptibility (1)

Functional susceptibility

Description

Negative injection

Positive injection

- 0

INJ

Injected current on BOOT0 pin

Injected current on NRST pin

Injected current on PB3, PB4, PB5, PB6,

PB7, PB8, PB9, PC13, PC14, PC15, PH1,

PDR_ON, PC0, PC1, PC2, PC3

Injected current on any other FT pin

Injected current on any other pins

1. NA = not applicable .

- 0

- 5

+ 5

Unit mA

It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.

General input/output characteristics

Unless otherwise specified, the parameters given in Table 55

are derived from tests

performed under the conditions summarized in Table 15

. All I/Os are CMOS and TTL compliant.

Symbol

Table 55. I/O static characteristics

Parameter

FT, TC and NRST I/O input low level voltage

Conditions

1.7 V ≤ V

≤ 3.6 V

Min

BOOT0 I/O input low level voltage

1.75 V ≤ V

- 40 °C ≤ T

≤

3.6 V,

125 °C

1.7 V ≤ V

0 °C ≤ T

≤

3.6 V,

125 °C

Typ Max

0.3V

(1)

0.1V

+0.1

(2)

Unit

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Symbol

Table 55. I/O static characteristics (continued)

Parameter Conditions Min Typ Max

FT, TC and NRST I/O input high level voltage (5)

1.7 V ≤ V

≤ 3.6 V 0.7V

(1)

BOOT0 I/O input high level voltage

1.75 V ≤ V

≤ 3.6 V,

-40 °C ≤ T

≤ 125 °C

1.7 V ≤ V

0 °C ≤ T

≤

3.6 V,

125 °C

0.17V

0.7

FT, TC and NRST I/O input hysteresis

1.7 V ≤ V

≤ 3.6 V 10% V

(3)

HYS

I lkg

BOOT0 I/O input hysteresis

I/O input leakage current

(4)

I/O FT/TC input leakage current

(5)

1.75 V ≤ V

- 40 °C ≤ T

≤

3.6 V,

125 °C

1.7 V ≤ V

0 °C ≤ T

≤

3.6 V,

125 °C

≤ V

= 5 V -

100

± 1

Unit

V mV

µA

Weak pull-up equivalent resistor

(6)

All pins except for

PA10

(OTG_FS_ID)

= V

30 40 50

PA10

(OTG_FS_ID)

7 10 14 k Ω

Weak pull-down equivalent resistor

(7)

All pins except for

PA10

(OTG_FS_ID)

= V

30 40 50

PA10

(OTG_FS_ID)

7 10 14

(8) I/O pin capacitance 5 -

1. Guaranteed by tests in production.

2. Guaranteed by design.

3. With a minimum of 200 mV.

4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins, Refer to Table 54: I/O current injection susceptibility

5. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled. Leakage could be

higher than the maximum value, if negative current is injected on adjacent pins.Refer to Table 54: I/O current injection susceptibility

6. Pull-up resistors are designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimum (~10% order).

7. Pull-down resistors are designed with a true resistance in series with a switchable NMOS. This NMOS contribution to the series resistance is minimum (~10% order).

8. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization.

All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The

coverage of these requirements for FT and TC I/Os is shown in Figure 27

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Electrical characteristics

Figure 27. FT/TC I/O input characteristics

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Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ± 8 mA, and sink or source up to ± 20 mA (with a relaxed V

) except PC13, PC14 and PC15 which can sink or source up to ± 3mA. When using the PC13 to PC15 GPIOs in output mode, the speed should not exceed 2 MHz with a maximum load of 30 pF.

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in

Section 6.2

. In particular:

• The sum of the currents sourced by all the I/Os on V

DD, consumption of the MCU sourced on V

Σ I

VDD

(see

Table 13 ).

DD, plus the maximum Run cannot exceed the absolute maximum rating

• The sum of the currents sunk by all the I/Os on V

SS consumption of the MCU sunk on V

Σ I

VSS

(see

Table 13 ).

plus the maximum Run

cannot exceed the absolute maximum rating

Output voltage levels

Unless otherwise specified, the parameters given in Table 56

are derived from tests performed under ambient temperature and V

supply voltage conditions summarized in

Table 15 . All I/Os are CMOS and TTL compliant.

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Symbol

Table 56. Output voltage characteristics

Parameter Conditions Min Max Unit

(1)

(3)

(1)

(3)

(1)

(3)

(1)

(3)

(1)

(3)

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

CMOS port

(2)

= +8 mA

2.7 V ≤ V

≤

TTL port

(2)

=+8 mA

2.7 V ≤

1.8 V

1.7 V

3.6 V

= +20 mA

2.7 V ≤

3.6 V

= +6 mA

≤

3.6 V

= +4 mA

≤

3.6 V

2.4

–0.4

–1.3

(4)

–0.4

(4)

–0.4

(5)

0.4

1.3

0.4

(4)

(5)

1. The I

current sunk by the device must always respect the absolute maximum rating specified in Table 13

. and the sum of I

(I/O ports and control pins) must not exceed I

VSS

2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

3. The I

current sourced by the device must always respect the absolute maximum rating specified in

Table 13

and the sum of I

(I/O ports and control pins) must not exceed I

VDD

4. Guaranteed by characterization results.

5. Guaranteed by design.

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in

Figure 28 and

Table 57 , respectively.

Unless otherwise specified, the parameters given in Table 57

are derived from tests performed under the ambient temperature and V

DD in

Unless otherwise specified, the parameters given in Table 58

supply voltage conditions summarized

Table 57. I/O AC characteristics

(1)(2)

OSPEEDRy

[1:0] bit value

(1)

Symbol Parameter Conditions Min Typ Max Unit

00 f max(IO)out

Maximum frequency

(3)

= 50 pF, V

≥ 2.70 V

= 50 pF, V

≥ 1.7 V

= 10 pF, V

≥ 2.70 V

= 10 pF, V

≥ 1.7 V

MHz t f(IO)out t r(IO)out

Output high to low level fall time and output low to high level rise time

= 50 pF, V

= 1.7 V to 3.6 V 100 ns

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Electrical characteristics STM32F410x8/B

Table 57. I/O AC characteristics (1)(2) (continued)

OSPEEDRy

[1:0] bit value

(1)

Symbol Parameter Conditions Min Typ Max Unit

01 f max(IO)out

Maximum frequency

(3) t f(IO)out t r(IO)out

Output high to low level fall time and output low to high level rise time f max(IO)out

Maximum frequency

(3)

= 50 pF, V

= 10 pF, V

= 50 pF, V

= 10 pF, V

= 40 pF, V

≥ 2.70 V

≥ 1.7 V

≥ 2.70 V

≥ 1.7 V

≥ 2.7 V

≥ 1.7 V

≥ 2.70 V

≥ 1.7 V

≥ 2.70 V

≥ 1.7 V

12.5

(4)

100

(

MHz ns

MHz

= 10 pF, V

≥ 2.70 V -

10 t f(IO)out t r(IO)out

Output high to low level fall time and output low to high level rise time

= 10 pF, V

= 40 pF, V

= 10 pF, V

≥ 1.7 V

≥ 2.70 V

≥ 1.7 V

≥ 2.70 V

≥ 1.7 V

(4)

100

( ns

F max(IO)out

Maximum frequency

(3)

= 30 pF, V

≥ 2.70 V -

MHz

11 t f(IO)out t r(IO)out

Output high to low level fall time and output low to high level rise time

= 30 pF, V

≥ 1.7 V

= 30 pF, V

≥ 2.70 V

= 30 pF, V

≥ 1.7 V

= 10 pF, V

≥ 2.70 V

= 10 pF, V

≥ 1.7 V

(4)

2.5

4 ns

EXTIpw

Pulse width of external signals detected by the EXTI controller

10 -

1. Guaranteed by characterization.

2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F4xx reference manual for a description of the GPIOx_SPEEDR GPIO port output speed register.

3. The maximum frequency is defined in

Figure 28

4. For maximum frequencies above 50 MHz and V

> 2.4 V, the compensation cell should be used.

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STM32F410x8/B Electrical characteristics

Figure 28. I/O AC characteristics definition

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DLG

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, R

(see

Table 55 ).

are derived from tests performed under the ambient temperature and V

supply voltage conditions summarized in

Table 15 . Refer to

Table 55: I/O static characteristics for the values of VIH and VIL for

NRST pin.

Symbol Parameter

Table 58. NRST pin characteristics

Conditions Min Typ Max

F(NRST)

(2)

NF(NRST)

(2)

Weak pull-up equivalent resistor

(1)

NRST Input filtered pulse

NRST Input not filtered pulse

NRST_OUT

Generated reset pulse duration

= V

> 2.7 V

Internal Reset source

300

100

1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order)

2. Guaranteed by design.

Unit k Ω ns ns

µs

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Electrical characteristics STM32F410x8/B

Figure 29. Recommended NRST pin protection

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1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the V

Table 58 . Otherwise the reset is not taken into account by the device.

IL(NRST)

max level specified in

The parameters given in

Table 59 are guaranteed by design.

Refer to Section 6.3.16: I/O port characteristics for details on the input/output alternate

function characteristics (output compare, input capture, external clock, PWM output).

Symbol

Table 59. TIMx characteristics

(1)(2)

Parameter Conditions

(3)

Min Max Unit t res(TIM)

Timer resolution time

AHB/APBx prescaler=1 or 2 or 4, f

TIMxCLK

= 100 MHz

AHB/APBx prescaler>4, f

TIMxCLK

100 MHz

11.9

t t

TIMxCLK ns

TIMxCLK ns f

EXT

Timer external clock frequency on CH1 to

CH4

Timer resolution

TIMxCLK

= 100 MHz

0 f

TIMxCLK

/2 MHz

MHz

Res

TIM

16/32 bit t

COUNTER

16-bit counter clock period when internal clock is selected f

TIMxCLK

= 100 MHz 0.0119

780 µs t

MAX_COUNT

Maximum possible count with 32-bit counter

TIMxCLK

= 100 MHz -

65536 ×

65536

51.1

TIMxCLK

1. TIMx is used as a general term to refer to the TIM1 to TIM11 timers.

2. Guaranteed by design.

3. The maximum timer frequency on APB1 is 50 MHz and on APB2 is up to 100 MHz, by setting the TIMPRE bit in the RCC_DCKCFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = HCKL, otherwise

TIMxCLK >= 4x PCLKx.

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I

C interface characteristics

The I

C interface meets the requirements of the standard I

C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” opendrain. When configured as open-drain, the PMOS connected between the I/O pin and V

DD disabled, but is still present.

The I

C characteristics are described in

Table 60

. Refer also to

Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (SDA

and SCL).

The I 2 C bus interface supports standard mode (up to 100 kHz) and fast mode (up to 400 kHz). The I 2 C bus frequency can be increased up to 1 MHz. For more details about the complete solution, please contact your local ST sales representative.

Symbol Parameter

Table 60. I 2 C characteristics

Standard mode

(1)(2)

Min Max

Fast mode I

(1)(2)

Unit

Min Max t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t r(SDA) t r(SCL) t f(SDA) t f(SCL) t h(STA)

SCL clock low time

SCL clock high time

SDA setup time

SDA data hold time

SDA and SCL rise time

SDA and SCL fall time

4.7

4.0

250

3450

(3)

1000

300

1.3

0.6

100

900

(4)

300

µs ns t t t su(STA) su(STO) w(STO:STA) t

Start condition hold time

Repeated Start condition setup time

Stop condition setup time

Stop to Start condition time

(bus free)

Pulse width of the spikes that are suppressed by the analog filter for standard fast mode

4.0

4.7

4.0

4.7

0 50

(5)

0.6

0.6 -

0.6

1.3

0 50

(5)

µs

µs ns

C b

Capacitive load for each bus line

400 400 pF

1. Guaranteed by design.

2. f

PCLK1

must be at least 2 MHz to achieve standard mode I

2 achieve fast mode I clock.

C frequencies. It must be at least 4 MHz to

C frequencies, and a multiple of 10 MHz to reach the 400 kHz maximum I

C fast mode

3. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL.

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118

Electrical characteristics STM32F410x8/B

4. The maximum data hold time has only to be met if the interface does not stretch the low period of SCL signal.

5. The minimum width of the spikes filtered by the analog filter is above t

(max)

Figure 30. I 2 C bus AC waveforms and measurement circuit

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1. R

= series protection resistor.

2. R

= external pull-up resistor.

3. V

DD_I2C

is the I2C bus power supply.

Table 61. SCL frequency (f

PCLK1

= 50 MHz, V

= V

DD_I2C

= 3.3 V)

(1)(2)

I2C_CCR value f

SCL

(kHz)

= 4.7 k Ω

400

300

200

100

0x8019

0x8021

0x8032

0x0096

50 0x012C

20 0x02EE

1. R

= External pull-up resistance, f

SCL

= I

C speed

2. For speeds around 200 kHz, the tolerance on the achieved speed is of tolerance on the achieved speed is ± 2%. These variations depend on the accuracy of the external components used to design the application.

± 5%. For other speed ranges, the

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Table 62. SCL frequency (f

PCLK1

= 42 MHz.,V

= V

DD_I2C

= 3.3 V)

(1)(2)

I2C_CCR value f

SCL

(kHz)

= 4.7 k Ω

400 0x8019

300

200

100

0x8021

0x8032

0x0096

0x012C

20 0x02EE

1. R

= External pull-up resistance, f

SCL

= I

C speed,

2. For speeds around 200 kHz, the tolerance on the achieved speed is of tolerance on the achieved speed 2%. These variations depend on the accuracy of the external components used to design the application.

± 5%. For other speed ranges, the

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118

Electrical characteristics STM32F410x8/B

FMPI

C characteristics

The FMPI2C characteristics are described in

Table 63

Refer also to

Section 6.3.16: I/O port characteristics

for more details on the input/output alternate function characteristics (SDA and SCL).

Table 63. FMPI 2 C characteristics (1)

Standard mode Fast mode Fast+ mode

Parameter

Min Max Min Max Min

FMPI2CC

MPI2CCLK

frequency 2 8 t w(SCLL) t w(SCLH) t su(SDA) t

H(SDA) t v(SDA,ACK) t r(SDA) t r(SCL) t f(SDA) t f(SCL) t h(STA)

SCL clock low time

SCL clock high time

SDA setup time

SDA data hold time

Data, ACK valid time

SDA and SCL rise time

SDA and SCL fall time

Start condition hold time t su(STA)

Repeated Start condition setup time

Stop condition setup time t su(STO) t w(STO:STA)

Stop to Start condition time

(bus free) t

C b

Pulse width of the spikes that are suppressed by the analog filter for standard and fast mode

Capacitive load for each bus

Line

4.7

4.0

0.25

4.7

3.45

0.100

0.30

400

1.3

0.6

0.10

0.6

1.3

0.05

0.9

0.30

0.09

400

1. Guaranteed based on test during characterization.

2. When tr(SDA,SCL)<=110 ns.

3. Can be limited. Maximum supported value can be retrieved by referring to the following formulas: t

R p(min)

= 0.8473 x R

= (V

-V

OL(max) p

x C

) / I load

OL(max)

(2)

0.5

0.26

0.05

0.26

0.5

0.05

Max

0.45

0.12

0.09

550

(3)

Unit us pF

102/143

DocID028094 Rev 6

STM32F410x8/B Electrical characteristics

Figure 31. FMPI 2 C timing diagram and measurement circuit

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DocID028094 Rev 6

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118

Electrical characteristics STM32F410x8/B t w(SCKH) t w(SCKL) t su(NSS) t h(NSS) t su(MI) t su(SI) t h(MI) t h(SI)

Symbol f

SCK

1/t c(SCK)

Duty(SCK)

SPI interface characteristics

Unless otherwise specified, the parameters given in Table 64

for the SPI interface are derived from tests performed under the ambient temperature, f

PCLKx

frequency and V

supply voltage conditions summarized in Table 15 , with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 10

• Capacitive load C = 30 pF

• Measurement points are done at CMOS levels: 0.5V

Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate

function characteristics (NSS, SCK, MOSI, MISO for SPI).

Parameter

Table 64. SPI dynamic characteristics

(1)

Conditions

SPI clock frequency

Master full duplex/receiver mode,

2.7 V < V

< 3.6 V

SPI1/4/5

Master full duplex/receiver mode,

3.0 V < V

< 3.6 V

SPI1/4/5

Master transmitter mode

1.7 V < V

< 3.6 V

SPI1/4/5

Master mode

1.7 V < V

< 3.6 V

SPI1/2/3/4/5

Slave transmitter/full duplex mode

2.7 V < V

< 3.6 V

SPI1/4/5

Slave receiver mode,

1.8 V < V

< 3.6 V

SPI1/4/5

Slave mode,

1.8 V < V

< 3.6 V

SPI1/2/3/4/5

Duty cycle of SPI clock frequency

Slave mode

Min

SCK high and low time Master mode, SPI presc = 2

NSS setup time

NSS hold time

Data input setup time

Data input hold time

Slave mode, SPI presc = 2

Master mode

Slave mode

Master mode

Slave mode

PCLK

1.5

PCLK

2.5

7.5

3.5

Typ

PCLK

Max

(2)

PCLK

+1.5

Unit

MHz

% ns ns ns ns ns ns ns

104/143

DocID028094 Rev 6

STM32F410x8/B Electrical characteristics

Symbol

Table 64. SPI dynamic characteristics (1) (continued)

Parameter Conditions Min Typ Max Unit t a(SO

) t dis(SO)

Data output access time Slave mode

Data output disable time Slave mode

12 ns ns t t v(SO) h(SO)

Data output valid time

Slave mode (after enable edge),

2.7 V < V

< 3.6 V

Slave mode (after enable edge),

1.7 V < V

< 3.6 V

Data output hold time

Slave mode (after enable edge),

1.7 V < V

< 3.6 V

Data output valid time Master mode (after enable edge)

18.5

ns ns ns t t v(MO) h(MO)

Data output hold time Master mode (after enable edge)

ns ns

1. Guaranteed by characterization.

2. Maximum frequency in Slave transmitter mode is determined by the sum of t having t su(MI)

= 0 while Duty(SCK) = 50% v(SO)

and t su(MI) which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master

Figure 32. SPI timing diagram - slave mode and CPHA = 0

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118

Electrical characteristics STM32F410x8/B

Figure 33. SPI timing diagram - slave mode and CPHA = 1 (1)

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(1)

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106/143

DocID028094 Rev 6

STM32F410x8/B Electrical characteristics

I

S interface characteristics

Unless otherwise specified, the parameters given in Table 65

for the I 2 S interface are derived from tests performed under the ambient temperature, f

PCLKx frequency and V

supply voltage conditions summarized in Table 15 , with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 10

• Capacitive load C = 30 pF

• Measurement points are done at CMOS levels: 0.5V

Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate

function characteristics (CK, SD, WS).

Symbol Parameter

Table 65. I

S dynamic characteristics

(1)

Conditions f

MCK f

I2S Main clock output

I2S clock frequency

Master data: 32 bits

Slave data: 32 bits

CK t v(WS) t h(WS) t su(WS) t h(WS) t su(SD_MR) t su(SD_SR) t h(SD_MR) t h(SD_SR) t v(SD_ST) t v(SD_MT) t h(SD_ST) t h(SD_MT)

I2S clock frequency duty cycle Slave receiver

WS valid time

WS hold time

WS setup time

WS hold time

Data input setup time

Data input hold time

Data output valid time

Data output hold time

Master mode

Slave mode

Master receiver

Slave receiver

Master receiver

Slave receiver

Slave transmitter (after enable edge)

Master transmitter (after enable edge)

Slave transmitter (after enable edge)

Master transmitter (after enable edge)

1. Guaranteed by characterization.

2. The maximum value of 256xFs is 50 MHz (APB1 maximum frequency).

2.5

1.5

2.5

Min Max

256x8K 256xFs (2)

64xFs

Unit

MHz

% ns

Note: Refer to the I2S section of RM0401 reference manual for more details on the sampling frequency (F

). f

MCK

, f

, and D

values reflect only the digital peripheral behavior. The values of these parameters might be slightly impacted by the source clock precision. D

depends mainly on the value of ODD bit. The digital contribution leads to a minimum value of

(I2SDIV/(2*I2SDIV+ODD) and a maximum value of (I2SDIV+ODD)/(2*I2SDIV+ODD). F

S maximum value is supported for each mode/condition.

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118

Electrical characteristics STM32F410x8/B

Figure 35. I 2 S slave timing diagram (Philips protocol) (1)

1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

Figure 36. I 2 S master timing diagram (Philips protocol) (1)

108/143

1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

DocID028094 Rev 6

STM32F410x8/B Electrical characteristics

Unless otherwise specified, the parameters given in Table 66

are derived from tests performed under the ambient temperature, f

conditions summarized in Table 15

PCLK2 frequency and V

DDA

supply voltage

Symbol

DDA

REF+

REFf

ADC f

TRIG

(2)

AIN

(2)

Parameter

Power supply

Positive reference voltage

Negative reference voltage

ADC clock frequency

External trigger frequency

Table 66. ADC characteristics

Conditions

DDA

− V

REF+

< 1.2 V

Min

1.7

(1)

1.7

(1)

DDA

= 1.7

(1)

to 2.4 V

DDA

= 2.4 to 3.6 V f

ADC

= 30 MHz,

12-bit resolution

0.6

Conversion voltage range

(3)

0 (V

SSA or V

REFtied to ground)

External input impedance

See Equation 1 for details

ADC

(2)(4)

Sampling switch resistance

ADC

(2)

Internal sample and hold capacitor

t lat

(2) t latr

(2) t

STAB

(2) t

CONV

(2)

Injection trigger conversion latency

Regular trigger conversion latency

Sampling time

Power-up time

Total conversion time

(including sampling time)

Typ

Max

3.6

DDA

1764

REF+

7 f

ADC

= 30 MHz

ADC

= 30 MHz f

ADC

= 30 MHz

0.100

ADC

= 30 MHz

12-bit resolution f

ADC

= 30 MHz

10-bit resolution f

ADC

= 30 MHz

8-bit resolution

0.50

0.43

0.37

16.40

16.34

16.27

ADC

= 30 MHz

6-bit resolution

0.30

16.20

9 to 492 (t

for sampling +n-bit resolution for successive approximation)

0.100

3 (5)

0.067

(5)

480

Unit

κΩ

κΩ pF

µs

1/f

ADC

µs

1/f

ADC

µs

1/f

ADC

µs

MHz

MHz kHz

1/f

ADC

µs

1/f

ADC

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118

Electrical characteristics STM32F410x8/B

Symbol Parameter

Table 66. ADC characteristics (continued)

Conditions Min Typ Max Unit f

(2)

Sampling rate

ADC t

= 30 MHz, and

= 3 ADC cycles)

12-bit resolution

Single ADC

12-bit resolution

Interleave Dual ADC mode

12-bit resolution

Interleave Triple ADC mode

3.75

Msps

VREF+

(2)

VDDA

(2)

ADC V

REF

DC current consumption in conversion mode

ADC V

DDA

DC current consumption in conversion mode

300

1.6

500

1.8

1. V

DDA

minimum value of 1.7 V is possible with the use of an external power supply supervisor (refer to Section 3.14.2:

Internal reset OFF ).

2. Guaranteed by characterization.

3. V

REF+

is internally connected to V

DDA

and V

REF-

is internally connected to V

SSA

4. R

ADC

maximum value is given for V

=1.7 V, and minimum value for V

=3.3 V.

5. For external triggers, a delay of 1/f

PCLK2

must be added to the latency specified in

Table 66

µA mA

Equation 1: R

AIN

max formula

AIN

=

ADC

(

C k 0.5

ADC

× ln

)

( 2

N +

)

– R

ADC

The formula above ( Equation 1 ) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the ADC_SMPR1 register.

Table 67. ADC accuracy at f

ADC

= 18 MHz (1)

Parameter Test conditions Typ Max

(2)

Unit Symbol

ET Total unadjusted error ±3

Offset error

Gain error

Differential linearity error

Integral linearity error

V f

ADC

DDA

REF

DDA

=18 MHz

= 1.7 to 3.6 V

− V

REF

< 1.2 V

±2

±1

±2

1. Better performance could be achieved in restricted V

, frequency and temperature ranges.

2. Guaranteed by characterization.

±4

±3

±2

±3

LSB

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STM32F410x8/B Electrical characteristics

Symbol

Table 68. ADC accuracy at f

ADC

= 30 MHz (1)

Parameter Test conditions Typ

Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error f

ADC

AIN

= 30 MHz,

< 10 k Ω ,

DDA

REF

= 2.4 to 3.6 V,

= 1.7 to 3.6 V,

DDA

− V

REF

< 1.2 V

1. Better performance could be achieved in restricted V

, frequency and temperature ranges.

2. Guaranteed by characterization.

±2

±1.5

±1

±1.5

Symbol

Table 69. ADC accuracy at f

ADC

= 36 MHz

(1)

Parameter Test conditions Typ

ET Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error f

ADC

=36 MHz,

DDA

= 2.4 to 3.6 V,

REF

= 1.7 to 3.6 V

DDA

− V

REF

< 1.2 V

1. Better performance could be achieved in restricted V

, frequency and temperature ranges.

2. Guaranteed by characterization.

±4

±2

±3

±2

±3

Max

(2)

±7

±3

±6

±3

±6

Max

(2)

±5

±2.5

±4

±2

±3

Unit

LSB

Unit

LSB

Symbol

Table 70. ADC dynamic accuracy at f

ADC

= 18 MHz - limited test conditions (1)

Parameter Test conditions Min Typ Max Unit bits ENOB

SINAD

SNR

THD

Effective number of bits

Signal-to-noise and distortion ratio

Signal-to-noise ratio

Total harmonic distortion

1. Guaranteed by characterization.

ADC

=18 MHz

DDA

= V

REF+

= 1.7 V

Input Frequency = 20 KHz

Temperature = 25 °C

10.3

10.4

64.2

-72

-67 dB

Symbol

Table 71. ADC dynamic accuracy at f

ADC

= 36 MHz - limited test conditions

(1)

Parameter Test conditions Min Typ Max Unit bits ENOB

SINAD

SNR

THD

Effective number of bits

Signal-to noise and distortion ratio

Signal-to noise ratio

Total harmonic distortion

1. Guaranteed by characterization.

ADC

= 36 MHz

DDA

= V

REF+

= 3.3 V

Input Frequency = 20 KHz

Temperature = 25 °C

10.6

10.8

-72

-70 dB

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118

Electrical characteristics

Note:

STM32F410x8/B

ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.

Any positive injection current within the limits specified for I

INJ(PIN)

Section 6.3.16

does not affect the ADC accuracy.

and Σ I

INJ(PIN)

Figure 37. ADC accuracy characteristics

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1. See also Table 68 .

2. Example of an actual transfer curve.

3. Ideal transfer curve.

4. End point correlation line.

5. E

= Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.

EO = Offset Error: deviation between the first actual transition and the first ideal one.

EG = Gain Error: deviation between the last ideal transition and the last actual one.

ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.

EL = Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line.

AIC

112/143

DocID028094 Rev 6

STM32F410x8/B Electrical characteristics

Figure 38. Typical connection diagram using the ADC

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1. Refer to Table 66 for the values of R

AIN

, R

ADC

and C

ADC

2. C f parasitic

represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 5

ADC

should be reduced.

pF). A high C parasitic

value downgrades conversion accuracy. To remedy this,

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118

Electrical characteristics STM32F410x8/B

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 39 . The 10 nF capacitors

should be ceramic (good quality). They should be placed as close as possible to the chip.

Figure 39. Power supply and reference decoupling

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6.3.21 Temperature sensor characteristics

Table 72. Temperature sensor characteristics

Symbol Parameter Min Typ Max

(1)

Avg_Slope

(1)

(1) t

START

(2)

S_temp

(2)

SENSE

linearity with temperature

Average slope

Voltage at 25 °C

Startup time

ADC sampling time when reading the temperature (1 °C accuracy)

1. Guaranteed by characterization.

2. Guaranteed by design.

2.5

0.76

Unit

°C mV/°C

µs

Symbol

Table 73. Temperature sensor calibration values

Parameter Memory address

TS_CAL1 TS ADC raw data acquired at temperature of 30 °C, V

DDA

= 3.3 V 0x1FFF 7A2C - 0x1FFF 7A2D

TS_CAL2 TS ADC raw data acquired at temperature of 110 °C, V

DDA

= 3.3 V 0x1FFF 7A2E - 0x1FFF 7A2F

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DocID028094 Rev 6

STM32F410x8/B

6.3.22 V

BAT

monitoring characteristics

Symbol

Table 74. V

BAT

monitoring characteristics

Parameter Min

(1)

S_vbat

(2)

Resistor bridge for V

BAT

Ratio on V

BAT

measurement

Error on Q

ADC sampling time when reading the V

BAT

1 mV accuracy

1. Guaranteed by design.

2. Shortest sampling time can be determined in the application by multiple iterations.

–1

Electrical characteristics

Typ

Max

Unit

K Ω

µs

The parameters given in

Table 75 are derived from tests performed under ambient

temperature and V

supply voltage conditions summarized in

Table 15: General operating conditions on page 53 .

Symbol

Table 75. Embedded internal reference voltage

Parameter Conditions Min Typ Max Unit

REFINT

S_vrefint

(1)

Internal reference voltage

ADC sampling time when reading the internal reference voltage

- 40 °C < T

< + 125 °C

RERINT_s

(2)

Internal reference voltage spread over the temperature range

= 3 V ± 10m V

Coeff

(2) t

START

(2)

Temperature coefficient

Startup time -

1. Shortest sampling time can be determined in the application by multiple iterations.

2. Guaranteed by design

1.18

1.21

1.24

µs mV ppm/°C

µs

Symbol

REFIN_CAL

Table 76. Internal reference voltage calibration values

Parameter Memory address

Raw data acquired at temperature of

30 °C V

DDA

= 3.3 V

0x1FFF 7A2A - 0x1FFF 7A2B

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118

Electrical characteristics STM32F410x8/B

Symbol

DDA

REF+

SSA

LOAD

(2)

LOAD

(2)

Parameter

Analog supply voltage

Reference supply voltage

Ground

Resistive load

Table 77. DAC characteristics

Conditions

DAC output buffer ON

LOAD connected to V

SSA

LOAD connected to V

DDA

Min Typ Max Unit

1.7

(1)

1.7

(1)

25 -

3.6

V V

REF+

DDA

V k Ω k Ω -

Comments

Impedance output with buffer OFF

Capacitive load -

50 k Ω pF

When the buffer is OFF, the

Minimum resistive load between DAC_OUT and V

SS to have a 1% accuracy is

1.5 M Ω

Maximum capacitive load at

DAC_OUT pin (when the buffer is ON).

DAC_OUT min

(2)

Lower DAC_OUT voltage with buffer

0.2

DDA

– 0.2

It gives the maximum output excursion of the DAC.

It corresponds to 12-bit input code (0x0E0) to (0xF1C) at

REF+

= 3.6 V and (0x1C7) to (0xE38) at V

REF+

= 1.7 V

DAC_OUT max

(2)

Higher DAC_OUT voltage with buffer

DAC_OUT min

(2)

Lower DAC_OUT voltage with buffer

OFF

DAC_OUT max

(2)

Higher DAC_OUT voltage with buffer

OFF

0.5

REF+

–

1LSB mV

It gives the maximum output excursion of the DAC.

VREF+

(4)

DAC DC V

REF current consumption in quiescent mode

(Standby mode)

170 240

50 75

µA

With no load, worst code

(0x800) at V

REF+

= 3.6 V in terms of DC consumption on the inputs

With no load, worst code

(0xF1C) at V

REF+

= 3.6 V in terms of DC consumption on the inputs

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DocID028094 Rev 6

STM32F410x8/B Electrical characteristics

Symbol

DDA

(4)

Parameter

DAC DC VDDA current consumption in quiescent mode (3)

Table 77. DAC characteristics (continued)

Conditions

Min Typ Max Unit

280 380 µA

475 625 µA

Comments

With no load, middle code

(0x800) on the inputs

With no load, worst code

(0xF1C) at V

REF+

= 3.6 V in terms of DC consumption on the inputs

DNL

(4)

Differential non linearity Difference between two consecutive code-

1LSB)

INL

(4)

Offset

(4)

Integral non linearity (difference between measured value at

Code i and the value at Code i on a line drawn between Code 0 and last Code

1023)

Offset error

(difference between measured value at

Code (0x800) and the ideal value =

REF+

/2) t

Gain error

(4)

Gain error

(

Total Harmonic

Distortion

Buffer ON

±0.5 LSB

Given for the DAC in 10-bit configuration.

±2 LSB

Given for the DAC in 12-bit configuration.

±1 LSB

Given for the DAC in 10-bit configuration.

±4 LSB

Given for the DAC in 12-bit configuration.

±10

±3 LSB

±12 LSB

±0.5

Given for the DAC in 12-bit configuration

Given for the DAC in 10-bit at

REF+

= 3.6 V

Given for the DAC in 12-bit at

REF+

= 3.6 V

Given for the DAC in 12-bit configuration

6 µs

LOAD

≤ 50 pF,

≥ 5 k Ω

THD

(4)

LOAD

≤ 50 pF,

≥ 5 k Ω

Update rate

(2)

Max frequency for a correct

DAC_OUT change when small variation in the input code (from code i to i+1LSB)

MS/ s

LOAD

≤ 50 pF,

≥ 5 k Ω

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118

Electrical characteristics STM32F410x8/B

Symbol Parameter

Table 77. DAC characteristics (continued)

Conditions Min Typ Max Unit Comments t

WAKEUP

(4)

Wakeup time from off state (Setting the ENx bit in the

DAC Control register)

PSRR+

(2)

Power supply rejection ratio (to

DDA

) (static DC measurement)

6.5

10 µs

LOAD

- –67 - 40 dB No R

≤ 50 pF, R

LOAD

, C

LOAD

1. V

DDA

minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to

Section 3.15.2:

Internal reset OFF ).

2. Guaranteed by design.

3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic consumption occurs.

4. Guaranteed based on test during characterization.

≥ 5 k input code between lowest and highest possible ones.

= 50 pF

Figure 40. 12-bit buffered/non-buffered DAC

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1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register.

Symbol

Table 78. RTC characteristics

Parameter Conditions f

PCLK1

/RTCCLK frequency ratio

Any read/write operation from/to an RTC register

Min

Max

118/143

DocID028094 Rev 6

STM32F410x8/B Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com

ECOPACK ® is an ST trademark.

Figure 41. WLCSP36 - 36-pin, 2.553 x 2.579 mm, 0.4 mm pitch wafer level chip scale package outline

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139

Package information STM32F410x8/B

Table 79. WLCSP36 - 36-pin, 2.553 x 2.579 mm, 0.4 mm pitch wafer level chip scale package mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max e2

G aaa bbb ccc ddd eee

E e e1

(2) b

(3)

0.525

0.220

2.518

2.544

0.555

0.170

0.380

0.025

0.250

2.553

2.579

0.400

2.000

0.2765

0.2895

0.585

0.280

2.588

2.614

0.100

0.050

1. Values in inches are converted from mm and rounded to 4 decimal digits.

2. Back side coating.

3. Dimension is measured at the maximum bump diameter parallel to primary datum Z.

0.0207

0.0087

0.1012

0.1050

0.0157

0.0787

0.0119

0.0138

0.0219

0.0069

0.0150

0.0010

0.0098

0.1026

0.1064

0.0039

0.0020

0.0230

0.0110

0.1039

0.1078

Figure 42. WLCSP36 - 36-pin, 2.553 x 2.579 mm, 0.4 mm pitch wafer level chip scale package recommended footprint

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DocID028094 Rev 6

STM32F410x8/B Package information

Pitch

Dpad

Dsm

Table 80. WLCSP36 recommended PCB design rules (0.4 mm pitch)

Dimension Recommended values

Stencil opening

Stencil thickness

0.4 mm

0.225 mm

0.290 mm typ. (depends on the soldermask registration tolerance)

0.250 mm

0.100 mm

WLCSP36 device marking

The following figure gives an example of topside marking orientation versus ball A1 identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 43. WLCSP36 marking example (package top view)

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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity.

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139

Package information

7.2 UFQFPN48 package information

STM32F410x8/B

Figure 44. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package outline

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1. Drawing is not to scale.

2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.

3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this back-side pad to PCB ground.

122/143

DocID028094 Rev 6

STM32F410x8/B Package information

Table 81. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data millimeters inches

(1)

Symbol

Min.

Typ.

Max.

Min.

Typ.

Max.

T b e ddd

0.500

0.000

6.900

5.500

0.300

0.200

0.550

0.020

7.000

5.600

0.400

0.152

0.250

0.500

0.600

0.050

7.100

5.700

0.500

0.300

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.0197

0.0000

0.2717

0.2165

0.0118

0.0079

0.0217

0.0008

0.2756

0.2205

0.0157

0.0060

0.0098

0.0197

0.0236

0.0020

0.2795

0.2244

0.0197

0.0118

0.0031

Figure 45. UFQFPN48 recommended footprint

1. Dimensions are in millimeters.

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139

Package information STM32F410x8/B

UFQFPN48 device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 46. UFQFPN48 marking example (package top view)

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DocID028094 Rev 6

STM32F410x8/B

7.3 LQFP48 package information

Package information

Figure 47. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline

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139

Package information STM32F410x8/B

Symbol

Table 82. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data millimeters inches

(1)

Min Typ Max Min Typ Max e

E3 k ccc b c

0.050

1.350

0.170

0.090

8.800

6.800

8.800

6.800

0.450

0°

1.400

0.220

9.000

7.000

5.500

9.000

7.000

5.500

0.500

0.600

1.000

3.5°

1.600

0.150

1.450

0.270

0.200

9.200

7.200

9.200

7.200

0.750

7°

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.3465

0.2677

0.0177

0°

0.0020

0.0531

0.0067

0.0035

0.3465

0.2677

0.2165

0.3543

0.2756

0.2165

0.0197

0.0236

0.0394

3.5°

0.0551

0.0087

0.3543

0.2756

0.3622

0.2835

0.0295

7°

0.0031

0.0630

0.0059

0.0571

0.0106

0.0079

0.3622

0.2835

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DocID028094 Rev 6

STM32F410x8/B Package information

Figure 48. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package recommended footprint

1. Dimensions are expressed in millimeters.

AID

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139

Package information STM32F410x8/B

LQFP48 device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 49. LQFP48 marking example (package top view)

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DocID028094 Rev 6

STM32F410x8/B

7.4 LQFP64 package information

Package information

Figure 50. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline

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139

Package information STM32F410x8/B

Table 83. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data millimeters inches

(1)

Symbol

Min.

Typ.

Max.

Min.

Typ.

Max.

L1 ccc

D1 b c

0.050

1.350

0.170

0.090

0°

0.450

1.000

1.400

0.220

- 12.000

10.000

7.500

12.000

10.000

7.500

0.500

3.5°

0.600

1. Values in inches are converted from mm and rounded to 4 decimal digits.

7°

0.750

0.080

1.600

0.150

1.450

0.270

0.200

0°

0.0177

0.0020

0.0531

0.0067

0.0035

0.2953

0.4724

0.3937

0.2953

0.0197

3.5°

0.0236

0.0394

0.0551

0.0087

0.4724

0.3937

7°

0.0295

0.0031

0.0630

0.0059

0.0571

0.0106

0.0079

Figure 51. LQFP64 recommended footprint

130/143

1. Dimensions are in millimeters.

DocID028094 Rev 6

STM32F410x8/B Package information

LQFP64 device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 52. LQFP64 marking example (package top view)

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139

Package information

7.5 UFBGA64 package information

STM32F410x8/B

Figure 53. UFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array package outline

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1. Drawing is not to scale.

Table 84. UFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array package mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max

A4 b

E1 e

0.460

0.050

0.400

0.080

0.270

0.170

4.850

3.450

4.850

3.450

0.530

0.080

0.450

0.130

0.320

0.280

5.000

3.500

5.000

3.500

0.500

0.600

0.110

0.500

0.180

0.370

0.330

5.150

3.550

5.150

3.550

0.0181

0.0020

0.0157

0.0031

0.0106

0.0067

0.1909

0.1358

0.1909

0.1358

0.0209

0.0031

0.0177

0.0051

0.0126

0.0110

0.1969

0.1378

0.1969

0.1378

0.0197

0.0236

0.0043

0.0197

0.0071

0.0146

0.0130

0.2028

0.1398

0.2028

0.1398

DocID028094 Rev 6

STM32F410x8/B Package information

Table 84. UFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array package mechanical data (continued) millimeters inches (1)

Symbol

Min Typ Max Min Typ Max

F ddd eee fff

0.460

0.700

0.530

0.750

0.600

0.800

0.080

0.150

0.050

0.0181

0.0276

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.0209

0.0295

0.0236

0.0315

0.0031

0.0059

0.0020

Figure 54. UFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array package recommended footprint

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Table 85. UFBGA64 recommended PCB design rules (0.5 mm pitch BGA)

Dimension Recommended values

Stencil opening

Stencil thickness

Pad trace width

0.5

0.280 mm

0.370 mm typ. (depends on the soldermask registration tolerance)

0.280 mm

Between 0.100 mm and 0.125 mm

0.100 mm

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139

Package information STM32F410x8/B

UFBGA64 device marking

The following figure gives an example of topside marking orientation versus ball A1 identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 55. UFBGA64 marking example (package top view)

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DocID028094 Rev 6

STM32F410x8/B Package information

The maximum chip junction temperature (T

J max) must never exceed the values given in

The maximum chip-junction temperature, T

J using the following equation:

max., in degrees Celsius, may be calculated

max = T

max + (PD max x Θ

)

Where:

• T

max is the maximum ambient temperature in °C,

• Θ

is the package junction-to-ambient thermal resistance, in ° C/W,

• PD max is the sum of P

INT

max and P

I/O max (PD max = P

INT

max + P

I/O max),

• P

INT

max is the product of I

DD and internal power.

, expressed in Watts. This is the maximum chip

I/O

max represents the maximum power dissipation on output pins where:

I/O

max = Σ (V

× I

) + Σ ((V

– V

) × I

), taking into account the actual V

OL application.

/ I

and V

/ I

OH of the I/Os at low and high level in the

Symbol

Table 86. Package thermal characteristics

Parameter Value

Thermal resistance junction-ambient

LQFP48

Thermal resistance junction-ambient

LQFP64

Thermal resistance junction-ambient

UFQFPN48

Thermal resistance junction-ambient

WLCSP36

Thermal resistance junction-ambient

UFBGA64

Unit

°C/W

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural

Convection (Still Air). Available from www.jedec.org.

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139

Part numbering STM32F410x8/B

136/143

Table 87. Ordering information scheme

Example:

Device family

STM32 = Arm

-based 32-bit microcontroller

STM32 F 410 C B Y 6 TR

Product type

F = General-purpose

Device subfamily

410 = 410 line

Pin count

T = 36 pins

C = 48 pins

R = 64 pins

Flash memory size

8 = 64 Kbytes of Flash memory

B = 128 Kbytes of Flash memory

Package

I = UFBGA

T = LQFP

U = UFQFPN

Y = WLCSP

Temperature range

6 = Industrial temperature range, - 40 to 85 °C

7 = Industrial temperature range, - 40 to 105 °C

3 = Industrial temperature range, - 40 to 125 °C

Packing

TR = tape and reel

No character = tray or tube

DocID028094 Rev 6

STM32F410x8/B Recommendations when using the internal reset OFF

Appendix A Recommendations when using the internal reset OFF

When the internal reset is OFF, the following integrated features are no longer supported:

• The integrated power-on-reset (POR)/power-down reset (PDR) circuitry is disabled.

• The brownout reset (BRO) circuitry must be disabled. By default BOR is OFF.

• The embedded programmable voltage detector (PVD) is disabled.

• VBAT functionality is no more available and VBAT pin should be connected to VDD.

Table 88. Limitations depending on the operating power supply range

Operating power supply range

ADC operation

Maximum

Flash memory access frequency with no wait state

Flashmax

)

Maximum

Flash memory access frequency with no wait states

(1) (2)

I/O operation

Possible

Flash memory operations

2.1 V

= 1.7 to

(3)

Conversion time up to

1.2 Msps

20 MHz (4)

100 MHz with

6 wait states

No I/O compensation

8-bit erase and program operations only

1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is required.

2. Thanks to the ART Accelerator and the 128-bit Flash memory, the number of wait states given here does not impact the execution speed from Flash memory since the ART Accelerator allows to achieve a performance equivalent to 0 wait state program execution.

3. V

DDA

minimum value of 1.7 V, with the use of an external power supply supervisor (refer to

Section 3.15.1: Internal reset ON ).

4. Prefetch is not available. Refer to AN3430 application note for details on how to adjust performance and power.

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139

Application block diagrams

Appendix B Application block diagrams

B.1 Sensor Hub application example

Figure 56. Sensor hub application example 1

STM32F410x8/B

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Figure 57. Sensor hub application example 2

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DocID028094 Rev 6

STM32F410x8/B Application block diagrams

Data is transferred through the DMA from interfaces into the internal SRAM while the rest of the MCU is set in low power mode.

• Code execution from RAM before switching off the Flash.

• Flash is set in power down and flash interface (ART accelerator™) clock is stopped.

• The clocks are enabled only for the required interfaces.

• MCU core is set in sleep mode (core clock stopped waiting for interrupt).

• Only the needed DMA channels are enabled and running.

Figure 58. Batch Acquisition Mode (BAM) example

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DocID028094 Rev 6

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139

Revision history

Revision history

STM32F410x8/B

Date

28-Sep-2015

07-Dec-2015

Revision

10-Aug-2016 3

Table 89. Document revision history

Changes

Initial release.

Junction temperature range changed to –40 to + 110 °C for WLCSP49 package.

Updated Figure 7: UFQFPN48 pinout .

Updated:

–

Table 2: STM32F410x8/B features and peripheral counts

–

Table 9: STM32F410x8/B pin definitions

–

Table 14: Thermal characteristics

–

Table 15: General operating conditions

–

Table 20: Embedded reset and power control block characteristics

– Tables from

Table 21: Typical and maximum current consumption, code with data processing (ART accelerator disabled) running from SRAM - V

to Table 34: Typical and maximum current consumptions in V

BAT

mode (LSE and RTC ON, LSE low- drive mode)

–

Table 42: HSI oscillator characteristics

–

Table 43: LSI oscillator characteristics

–

Table 49: Flash memory endurance and data retention

–

Table 52: ESD absolute maximum ratings

–

Table 55: I/O static characteristics

–

Table 66: ADC characteristics

–

Table 75: Embedded internal reference voltage

–

Table 77: DAC characteristics

–

Table 87: Ordering information scheme

–

Figure 16: Typical V

BAT

current consumption (LSE and RTC ON/LSE oscillator in

“low power” mode selection

–

Section 7: Package information

Added:

–

Figure 5: LQFP48 pinout

–

Figure 8: UFBGA64 pinout

–

Figure 49: LQFP48 marking example (package top view)

–

Figure 55: UFBGA64 marking example (package top view)

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DocID028094 Rev 6

STM32F410x8/B

Date

06-Mar-2017

04-Apr-2017

Revision history

Revision

Table 89. Document revision history (continued)

Changes

Updated:

–

Features

–

Section 3.20: Timers and watchdogs

–

Table 9: STM32F410x8/B pin definitions

–

Table 21: Typical and maximum current consumption, code with data processing

Table 22: Typical and maximum current consumption, code with data processing

–

Table 24: Typical and maximum current consumption in run mode, code with data processing (ART accelerator enabled except prefetch) running from Flash memory - V

–

Table 28: Typical and maximum current consumption in Sleep mode - V

–

3.6 V

–

Table 31: Typical and maximum current consumption in Stop mode - V

=3.6 V

–

Table 34: Typical and maximum current consumptions in V

BAT

RTC ON, LSE low- drive mode)

mode (LSE and

The maximum current consumption at 30 °C has been redefined to be in line with the actual silicon performance. For a typical customer application the impact on the average current consumption will be insignificant.

Updated:

–

Table 21: Typical and maximum current consumption, code with data processing

Table 22: Typical and maximum current consumption, code with data processing

–

Table 23: Typical and maximum current consumption in run mode, code with data processing (ART accelerator enabled except prefetch) running from Flash memory- V

–

Table 24: Typical and maximum current consumption in run mode, code with data processing (ART accelerator enabled except prefetch) running from Flash memory - V

–

Table 25: Typical and maximum current consumption in run mode, code with data processing (ART accelerator disabled) running from Flash memory - V

–

Table 26: Typical and maximum current consumption in run mode, code with data processing (ART accelerator disabled) running from Flash memory - V

–

Table 27: Typical and maximum current consumption in run mode, code with data processing (ART accelerator enabled with prefetch) running from Flash memory - V

–

Table 37: Low-power mode wakeup timings

–

–

Figure 30: I

C bus AC waveforms and measurement circuit

–

Figure 31: FMPI 2 C timing diagram and measurement circuit

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142

Revision history STM32F410x8/B

Date

15-Dec-2017

Revision

Table 89. Document revision history (continued)

Changes

Updated:

–

Table 21: Typical and maximum current consumption, code with data processing

Table 22: Typical and maximum current consumption, code with data processing

–

Table 24: Typical and maximum current consumption in run mode, code with data processing (ART accelerator enabled except prefetch) running from Flash memory - V

–