STMicroelectronics STM32L412CB Datasheet

O (7)

(7)

O (7)

(7)

(7)

The clock controller (see Figure 4

(7)

GPIOs

(9)

4 pins

(10)

(11)

4 pins

(10)

1. Legend: Y = Yes (Enable). O = Optional (Disable by default. Can be enabled by software). - = Not available.

2. The Flash can be configured in power-down mode. By default, it is not in power-down mode.

3. The SRAM clock can be gated on or off.

4. SRAM2 content is preserved when the bit RRS is set in PWR_CR3 register.

5. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not need it anymore.

6. LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event.

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Functional overview STM32L412xx

7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.

8. Voltage scaling Range 1 only.

9. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.

10. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5.

11. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode.

In order to improve the consumption under reset, the I/Os state under and after reset is

“analog state” (the I/O schmitt trigger is disable). In addition, the internal reset pull-up is deactivated when the reset source is internal.

Note:

The VBAT pin permits to power the device VBAT domain from an external battery, an external supercapacitor, or from V

when no external battery and an external supercapacitor are present. The VBAT pin supplies the RTC with LSE and the backup registers. Two anti-tamper detection pins are available in VBAT mode.

VBAT operation is automatically activated when V

is not present.

An internal VBAT battery charging circuit is embedded and can be activated when V

DD present.

When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events do not exit it from VBAT operation.

Several peripherals have direct connections between them. This allows autonomous communication between peripherals, saving CPU resources thus power supply consumption. In addition, these hardware connections allow fast and predictable latency.

Depending on peripherals, these interconnections can operate in Run, Sleep, low-power run and sleep, Stop 0, Stop 1 and Stop 2 modes.

Table 6. STM32L412xx peripherals interconnect matrix

Interconnect source

Interconnect destination

Interconnect action

TIMx

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TIMx

ADCx

DMA

COMPx

Timers synchronization or chaining

Conversion triggers

Memory to memory transfer trigger

Comparator output blanking

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Y Y Y Y -

STM32L412xx Functional overview

Table 6. STM32L412xx peripherals interconnect matrix (continued)

Interconnect source

Interconnect destination

Interconnect action

TIM15/TIM16

COMPx

ADCx

RTC

IRTIM

TIM1

TIM2

LPTIMERx

TIM1

TIM16

LPTIMERx

All clocks sources (internal and external)

TIM2

TIM15, 16

CSS

CPU (hard fault)

RAM (parity error)

Flash memory (ECC error)

COMPx

PVD

TIM1

TIM15,16

TIMx

LPTIMERx

GPIO

ADCx

Infrared interface output generation

Timer input channel, trigger, break from analog signals comparison

Low-power timer triggered by analog signals comparison

Timer triggered by analog watchdog

Timer input channel from RTC events

Low-power timer triggered by RTC alarms or tampers

Y Y Y Y Y Y

Y Y Y Y -

Y Y Y Y Y Y

Clock source used as input channel for

RC measurement and trimming

Y Y Y Y -

Timer break

External trigger

Conversion external trigger

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Functional overview STM32L412xx

3.11 Clocks and startup

) distributes the clocks coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness. It features:

• Clock prescaler: to get the best trade-off between speed and current consumption, the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler

• Safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register.

• Clock management: to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory.

• System clock source: four different clock sources can be used to drive the master clock SYSCLK:

– 4-48 MHz high-speed external crystal or ceramic resonator (HSE), that can supply a PLL. The HSE can also be configured in bypass mode for an external clock.

– 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software, that can supply a PLL

– Multispeed internal RC oscillator (MSI), trimmable by software, able to generate

12 frequencies from 100 kHz to 48 MHz. When a 32.768 kHz clock source is available in the system (LSE), the MSI frequency can be automatically trimmed by hardware to reach better than ±0.25% accuracy. The MSI can supply a PLL.

– System PLL which can be fed by HSE, HSI16 or MSI, with a maximum frequency at 80 MHz.

• RC48 with clock recovery system (HSI48) : internal RC48 MHz clock source can be used to drive the USB or the RNG peripherals. This clock can be output on the MCO.

• Auxiliary clock source: two ultralow-power clock sources that can be used to drive the real-time clock:

– 32.768 kHz low-speed external crystal (LSE), supporting four drive capability modes. The LSE can also be configured in bypass mode for an external clock.

– 32 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.

The LSI clock accuracy is ±5% accuracy.

• Peripheral clock sources: Several peripherals (RNG, USARTs, I2Cs, LPTimers) have their own independent clock whatever the system clock. PLL having three independent outputs allowing the highest flexibility, can generate independent clocks for the RNG.

• Startup clock: after reset, the microcontroller restarts by default with an internal 4 MHz clock (MSI). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts.

• Clock security system (CSS): this feature can be enabled by software. If a HSE clock failure occurs, the master clock is automatically switched to HSI16 and a software

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STM32L412xx Functional overview interrupt is generated if enabled. LSE failure can also be detected and generated an interrupt.

• Clock-out capability:

– MCO: microcontroller clock output: it outputs one of the internal clocks for external use by the application. Low frequency clocks (LSI, LSE) are available down to Stop 1 low power state.

– LSCO: low speed clock output: it outputs LSI or LSE in all low-power modes down to Standby mode. LSE can also be output on LSCO in Shutdown mode.

LSCO is not available in VBAT mode.

Several prescalers permit to configure the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the APB domains is 80 MHz.

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Functional overview STM32L412xx

Figure 4. Clock tree to IWDG

LSI RC 32 kHz

LSCO

OSC32_OUT

OSC32_IN

LSE OSC

32.768 kHz

MCO

/ 1→16

LSE

LSI

HSE

SYSCLK

HSI16

HSI48

MSI

PLLCLK

OSC_OUT

OSC_IN

HSE OSC

4-48 MHz

Clock detector

HSI RC

16 MHz

PLL

100 kHz – 48 MHz

/ P

/ Q

/ R

MSI RC

HSI RC

48 MHz

CRS

PLL48M1CLK

PLLCLK

/32 to RTC

HSE

MSI

HSI16

Clock source control

SYSCLK to PWR

AHB PRESC

/ 1,2,..512

HCLK

/ 8 to AHB bus, core, memory and DMA

FCLK Cortex free running clock to Cortex system timer

APB1 PRESC

/ 1,2,4,8,16

PCLK1 to APB1 peripherals x1 or x2 to TIMx x=2,6,7

LSE

HSI16

SYSCLK to USARTx x=2..3

to LPUART1

HSI16

SYSCLK to I2Cx x=1,2,3

LSI

LSE

HSI16 to LPTIMx x=1,2

/ M

MSI

HSI16

HSE

MSI

APB2 PRESC

/ 1,2,4,8,16

PCLK2 to APB2 peripherals x1 or x2 to TIMx x=1,15,16

LSE

HSI16

SYSCLK to

USART1

48 MHz clock to USB, RNG

SYSCLK to ADCx, x=1,2

MSv46900V3

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STM32L412xx Functional overview

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be achieved thanks to their mapping on the AHB2 bus.

The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers.

3.13 Direct memory access controller (DMA)

The device embeds 2 DMAs. Refer to Table 7: DMA implementation for the features

implementation.

Direct memory access (DMA) is used in order to provide high-speed data transfer between peripherals and memory as well as memory to memory. Data can be quickly moved by DMA without any CPU actions. This keeps CPU resources free for other operations.

The two DMA controllers have 14 channels in total, each dedicated to managing memory access requests from one or more peripherals. Each has an arbiter for handling the priority between DMA requests.

The DMA supports:

• 14 independently configurable channels (requests)

• Each channel is connected to dedicated hardware DMA requests, software trigger is also supported on each channel. This configuration is done by software.

• Priorities between requests from channels of one DMA are software programmable (4 levels consisting of very high, high, medium, low) or hardware in case of equality

(example: request 1 has priority over request 2)

• Independent source and destination transfer size (byte, half word, word), emulating packing and unpacking. Source/destination addresses must be aligned on the data size.

• Support for circular buffer management

• 3 event flags (DMA Half Transfer, DMA Transfer complete and DMA Transfer Error) logically ORed together in a single interrupt request for each channel

• Memory-to-memory transfer

• Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral transfers

• Access to Flash, SRAM, APB and AHB peripherals as source and destination

• Programmable number of data to be transferred: up to 65536.

Table 7. DMA implementation

DMA features DMA1

Number of regular channels 7

DMA2

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Functional overview STM32L412xx

3.14.1 Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 67 maskable interrupt channels plus the 16 interrupt lines of the Cortex

M4.

The NVIC benefits are the following:

• Closely coupled NVIC gives low latency interrupt processing

• Interrupt entry vector table address passed directly to the core

• Allows early processing of interrupts

• Processing of late arriving higher priority interrupts

• Support for tail chaining

• Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction overhead

The NVIC hardware block provides flexible interrupt management features with minimal interrupt latency.

3.14.2 Extended interrupt/event controller (EXTI)

The extended interrupt/event controller consists of 37 edge detector lines used to generate interrupt/event requests and wake-up the system from Stop mode. Each external line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests.

The internal lines are connected to peripherals with wakeup from Stop mode capability. The

EXTI can detect an external line with a pulse width shorter than the internal clock period. Up to 52 GPIOs can be connected to the 16 external interrupt lines.

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STM32L412xx Functional overview

3.15 Analog to digital converter (ADC)

The device embeds 2 successive approximation analog-to-digital converter with the following features:

• 12-bit native resolution, with built-in calibration

• 5.33 Msps maximum conversion rate with full resolution

– Down to 18.75 ns sampling time

– Increased conversion rate for lower resolution (up to 8.88 Msps for 6-bit resolution)

• Up to 16 external channels, some of them shared between ADC1 and ADC2.

• 3 internal channels: internal reference voltage, temperature sensor, VBAT/3.

• One external reference pin is available on some package, allowing the input voltage range to be independent from the power supply

• Single-ended and differential mode inputs

• Low-power design

– Capable of low-current operation at low conversion rate (consumption decreases linearly with speed)

• Highly versatile digital interface

– Single-shot or continuous/discontinuous sequencer-based scan mode: 2 groups of analog signals conversions can be programmed to differentiate background and high-priority real-time conversions

– Handles two ADC converters for dual mode operation (simultaneous or interleaved sampling modes)

– Each ADC supports multiple trigger inputs for synchronization with on-chip timers and external signals

– Results stored into 2 data register or in RAM with DMA controller support

– Data pre-processing: left/right alignment and per channel offset compensation

– Built-in oversampling unit for enhanced SNR

– Channel-wise programmable sampling time

– Three analog watchdog for automatic voltage monitoring, generating interrupts and trigger for selected timers

– Hardware assistant to prepare the context of the injected channels to allow fast context switching

The temperature sensor (TS) generates a voltage V

that varies linearly with temperature.

The temperature sensor is internally connected to the ADC1_IN17 input channel which is used to convert the sensor output voltage into a digital value.

The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only.

To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode.

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Functional overview STM32L412xx

Table 8. Temperature sensor calibration values

Calibration value name Description Memory address

TS_CAL1

TS_CAL2

TS ADC raw data acquired at a temperature of 30 °C (± 5 °C),

DDA

= V

REF+

= 3.0 V (± 10 mV)

TS ADC raw data acquired at a temperature of 130 °C (± 5 °C),

DDA

= V

REF+

= 3.0 V (± 10 mV)

0x1FFF 75A8 - 0x1FFF 75A9

0x1FFF 75CA - 0x1FFF 75CB

3.15.2 Internal voltage reference (V

REFINT

)

The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the ADC and Comparators. VREFINT is internally connected to the ADC1_IN0 input channel. The precise voltage of VREFINT is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode.

Table 9. Internal voltage reference calibration values

Calibration value name Description Memory address

VREFINT

Raw data acquired at a temperature of 30 °C (± 5 °C),

DDA

= V

REF+

= 3.0 V (± 10 mV)

0x1FFF 75AA - 0x1FFF 75AB

3.15.3 V

BAT

battery voltage monitoring

This embedded hardware feature allows the application to measure the V

BAT using the internal ADC channel ADC1_IN18 or ADC3_IN18. As the V

BAT higher than V

DDA

battery voltage

voltage may be

, and thus outside the ADC input range, the VBAT pin is internally connected to a bridge divider by 3. As a consequence, the converted digital value is one third the V

BAT

voltage.

The STM32L412xx devices embed one rail-to-rail comparator with programmable reference voltage (internal or external), hysteresis and speed (low speed for low-power) and with selectable output polarity.

The reference voltage can be one of the following:

• External I/O

• Internal reference voltage or submultiple (1/4, 1/2, 3/4).

All comparators can wake up from Stop mode, generate interrupts and breaks for the timers and can be also combined into a window comparator.

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The STM32L412xx embeds one operational amplifier with external or internal follower routing and PGA capability.

DS12469 Rev 8

STM32L412xx

The operational amplifier features:

• Low input bias current

• Low offset voltage

• Low-power mode

• Rail-to-rail input

Functional overview

3.18 Touch sensing controller (TSC)

Note:

The touch sensing controller provides a simple solution for adding capacitive sensing functionality to any application. Capacitive sensing technology is able to detect finger presence near an electrode which is protected from direct touch by a dielectric (such as glass or plastic). The capacitive variation introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle.

The touch sensing controller is fully supported by the STMTouch touch sensing firmware library which is free to use and allows touch sensing functionality to be implemented reliably in the end application.

The main features of the touch sensing controller are the following:

• Proven and robust surface charge transfer acquisition principle

• Supports up to 12 capacitive sensing channels

• Up to 3 capacitive sensing channels can be acquired in parallel offering a very good response time

• Spread spectrum feature to improve system robustness in noisy environments

• Full hardware management of the charge transfer acquisition sequence

• Programmable charge transfer frequency

• Programmable sampling capacitor I/O pin

• Programmable channel I/O pin

• Programmable max count value to avoid long acquisition when a channel is faulty

• Dedicated end of acquisition and max count error flags with interrupt capability

• One sampling capacitor for up to 3 capacitive sensing channels to reduce the system components

• Compatible with proximity, touchkey, linear and rotary touch sensor implementation

• Designed to operate with STMTouch touch sensing firmware library

The number of capacitive sensing channels is dependent on the size of the packages and subject to I/O availability.

3.19 Random number generator (RNG)

All devices embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit.

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Functional overview STM32L412xx

3.20 Timers and watchdogs

The STM32L412xx includes one advanced control timers, up to five general-purpose timers, two basic timers, two low-power timers, two watchdog timers and a SysTick timer. The table below compares the features of the advanced control, general purpose and basic timers.

Timer type

Advanced control

Generalpurpose

Basic

Timer

TIM1

TIM2

TIM15

TIM16

TIM6

Table 10. Timer feature comparison

Counter resolution

Counter type

Prescaler factor

DMA request generation

16-bit

32-bit

16-bit

Up, down,

Up/down

Up, down,

Up/down

Any integer between 1 and 65536

Yes

Capture/ compare channels

Complementary outputs

3.20.1 Advanced-control timer (TIM1)

The advanced-control timer can each be seen as a three-phase PWM multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted deadtimes. They can also be seen as complete general-purpose timers. The 4 independent channels can be used for:

• Input capture

• Output compare

• PWM generation (edge or center-aligned modes) with full modulation capability (0-

100%)

• One-pulse mode output

In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled to turn off any power switches driven by these outputs.

Many features are shared with those of the general-purpose TIMx timers (described in

Section 3.20.2

) using the same architecture, so the advanced-control timer can work

together with the TIMx timers via the Timer Link feature for synchronization or event chaining.

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STM32L412xx Functional overview

There are up to three synchronizable general-purpose timers embedded in the

STM32L412xx (see

Table 10

for differences). Each general-purpose timer can be used to generate PWM outputs, or act as a simple time base.

• TIM2

It is a full-featured general-purpose timers:

– TIM2 has a 32-bit auto-reload up/downcounter and 32-bit prescaler.

This timers feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. They can work with the other general-purpose timers via the

Timer Link feature for synchronization or event chaining.

The counters can be frozen in debug mode.

All have independent DMA request generation and support quadrature encoder.

• TIM15 and 16

They are general-purpose timers with mid-range features:

They have 16-bit auto-reload upcounters and 16-bit prescalers.

– TIM15 has 2 channels and 1 complementary channel

– TIM16 has 1 channel and 1 complementary channel

All channels can be used for input capture/output compare, PWM or one-pulse mode output.

The timers can work together via the Timer Link feature for synchronization or event chaining. The timers have independent DMA request generation.

The counters can be frozen in debug mode.

3.20.3 Basic timer (TIM6)

The basic timer can be used as generic 16-bit timebase.

The devices embed two low-power timers. These timers have an independent clock and are running in Stop mode if they are clocked by LSE, LSI or an external clock. They are able to wakeup the system from Stop mode.

Both LPTIM1 and LPTIM2 are active in Stop 0, Stop 1 and Stop 2 modes.

This low-power timer supports the following features:

• 16-bit up counter with 16-bit autoreload register

• 16-bit compare register

• Configurable output: pulse, PWM

• Continuous/ one shot mode

• Selectable software/hardware input trigger

• Selectable clock source

– Internal clock sources: LSE, LSI, HSI16 or APB clock

– External clock source over LPTIM input (working even with no internal clock source running, used by pulse counter application).

• Programmable digital glitch filter

• Encoder mode (LPTIM1 only)

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Functional overview STM32L412xx

The STM32L412xx includes one infrared interface (IRTIM), which can be used with an infrared LED to perform remote control functions. It uses TIM15 and TIM16 output channels to generate output signal waveforms on IR_OUT pin.

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC (LSI) and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode.

3.20.7 System window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

This timer is dedicated to real-time operating systems, but can also be used as a standard down counter. It features:

• A 24-bit down counter

• Autoreload capability

• Maskable system interrupt generation when the counter reaches 0

• Programmable clock source

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STM32L412xx Functional overview

The RTC is an independent BCD timer/counter. It supports the following features:

• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format.

• Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.

• Two programmable alarms.

• On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master clock.

• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision.

• Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal inaccuracy.

• Two anti-tamper detection pins with programmable filter.

• Timestamp feature, which can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to

VBAT mode.

• 17-bit auto-reload wakeup timer (WUT) for periodic events with programmable resolution and period.

The RTC and the 32 backup registers are supplied through a switch that takes power either from the V

supply when present or from the VBAT pin.

The backup registers are 32-bit registers used to store 128 bytes of user application data when V

power is not present. They are not reset by a system or power reset, or when the device wakes up from Standby or Shutdown mode.

The RTC clock sources can be:

• A 32.768 kHz external crystal (LSE)

• An external resonator or oscillator (LSE)

• The internal low power RC oscillator (LSI, with typical frequency of 32 kHz)

• The high-speed external clock (HSE) divided by 32.

The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the

LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in all low-power modes except Shutdown mode.

All RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt and wakeup the device from the low-power modes.

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Functional overview STM32L412xx

circuit interface (I

2

C)

The device embeds three

I2C. Refer to Table 11: I2C implementation for the features

implementation.

The I

C bus interface handles communications between the microcontroller and the serial

C bus. It controls all I

C bus-specific sequencing, protocol, arbitration and timing.

The I2C peripheral supports:

• I 2 C-bus specification and user manual rev. 5 compatibility:

– Slave and master modes, multimaster capability

– Standard-mode (Sm), with a bitrate up to 100 kbit/s

– Fast-mode (Fm), with a bitrate up to 400 kbit/s

– Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os

– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses

– Programmable setup and hold times

– Optional clock stretching

• System Management Bus (SMBus) specification rev 2.0 compatibility:

– Hardware PEC (Packet Error Checking) generation and verification with ACK control

– Address resolution protocol (ARP) support

– SMBus alert

• Power System Management Protocol (PMBus TM ) specification rev 1.1 compatibility

• Independent clock: a choice of independent clock sources allowing the I2C communication speed to be independent from the PCLK reprogramming. Refer to

Figure 4: Clock tree .

• Wakeup from Stop mode on address match

• Programmable analog and digital noise filters

• 1-byte buffer with DMA capability

Table 11. I2C implementation

I2C features

(1)

Standard-mode (up to 100 kbit/s)

Fast-mode (up to 400 kbit/s)

Fast-mode Plus with 20mA output drive I/Os (up to 1 Mbit/s)

Programmable analog and digital noise filters

SMBus/PMBus hardware support

Independent clock

Wakeup from Stop 1 mode on address match

Wakeup from Stop 2 mode on address match

1. X: supported

I2C1

I2C2

I2C3

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STM32L412xx Functional overview

(USART)

The STM32L412xx devices have three embedded universal synchronous receiver transmitters (USART1, USART2 and USART3).

These interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. They provide hardware management of the CTS and RTS signals, and RS485 Driver Enable, and are able to communicate at speeds of up to

10 Mbit/s.

USART1, USART2 and USART3 also provide Smart Card mode (ISO 7816 compliant) and

SPI-like communication capability.

All USART have a clock domain independent from the CPU clock, allowing the USARTx

(x=1,2,3) to wake up the MCU from Stop mode using baudrates up to 204 Kbaud. The wake up events from Stop mode are programmable and can be:

• Start bit detection

• Any received data frame

• A specific programmed data frame

All USART interfaces can be served by the DMA controller.

Table 12. STM32L412xx USART/UART/LPUART features

USART modes/features (1) USART1 USART2 USART3 LPUART1

Hardware flow control for modem

Continuous communication using DMA

Multiprocessor communication

Synchronous mode

Smartcard mode

Single-wire half-duplex communication

IrDA SIR ENDEC block

LIN mode

Dual clock domain

Wakeup from Stop 0 / Stop 1 modes

Wakeup from Stop 2 mode

Receiver timeout interrupt

Modbus communication

Auto baud rate detection

Driver Enable

LPUART/USART data length

1. X = supported.

X (4 modes)

X X

7, 8 and 9 bits

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Functional overview STM32L412xx

(LPUART)

The device embeds one Low-Power UART. The LPUART supports asynchronous serial communication with minimum power consumption. It supports half duplex single wire communication and modem operations (CTS/RTS). It allows multiprocessor communication.

The LPUART has a clock domain independent from the CPU clock, and can wakeup the system from Stop mode using baudrates up to 220 Kbaud. The wake up events from Stop mode are programmable and can be:

• Start bit detection

• Any received data frame

• A specific programmed data frame

Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while having an extremely low energy consumption. Higher speed clock can be used to reach higher baudrates.

LPUART interface can be served by the DMA controller.

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STM32L412xx Functional overview

3.25 Serial peripheral interface (SPI)

Three SPI interfaces allow communication up to 40 Mbits/s in master and up to 24 Mbits/s slave modes, in half-duplex, full-duplex and simplex modes. The 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits. The SPI interfaces support NSS pulse mode, TI mode and Hardware CRC calculation.

All SPI interfaces can be served by the DMA controller.

3.26 Universal serial bus (USB)

The STM32L412xx devices embed a full-speed USB device peripheral compliant with the

USB specification version 2.0. The internal USB PHY supports USB FS signaling, embedded DP pull-up and also battery charging detection according to Battery Charging

Specification Revision 1.2. The USB interface implements a full-speed (12 Mbit/s) function interface with added support for USB 2.0 Link Power Management. It has softwareconfigurable endpoint setting with packet memory up-to 1 KB and suspend/resume support.

It requires a precise 48 MHz clock which can be generated from the internal main PLL (the clock source must use a HSE crystal oscillator) or by the internal 48 MHz oscillator in automatic trimming mode. The synchronization for this oscillator can be taken from the USB data stream itself (SOF signalization) which allows crystal less operation.

The STM32L412xx devices embed a special block which allows automatic trimming of the internal 48 MHz oscillator to guarantee its optimal accuracy over the whole device operational range. This automatic trimming is based on the external synchronization signal, which could be either derived from LSE oscillator, from an external signal on CRS_SYNC pin or generated by user software. For faster lock-in during startup it is also possible to combine automatic trimming with manual trimming action.

The Quad SPI is a specialized communication interface targeting single, dual or quad SPI

Flash memories. It can operate in any of the three following modes:

• Indirect mode: all the operations are performed using the QUADSPI registers

• Status polling mode: the external Flash memory status register is periodically read and an interrupt can be generated in case of flag setting

• Memory-mapped mode: the external Flash is memory mapped and is seen by the system as if it were an internal memory

Both throughput and capacity can be increased two-fold using dual-flash mode, where two

Quad SPI flash memories are accessed simultaneously.

DS12469 Rev 8 47/192

Functional overview STM32L412xx

The Quad SPI interface supports:

• Three functional modes: indirect, status-polling, and memory-mapped

• Dual-flash mode, where 8 bits can be sent/received simultaneously by accessing two flash memories in parallel.

• SDR and DDR support

• Fully programmable opcode for both indirect and memory mapped mode

• Fully programmable frame format for both indirect and memory mapped mode

• Each of the five following phases can be configured independently (enable, length, single/dual/quad communication)

– Instruction phase

– Address phase

– Alternate bytes phase

– Dummy cycles phase

– Data phase

• Integrated FIFO for reception and transmission

• 8, 16, and 32-bit data accesses are allowed

• DMA channel for indirect mode operations

• Programmable masking for external flash flag management

• Timeout management

• Interrupt generation on FIFO threshold, timeout, status match, operation complete, and access error

48/192 DS12469 Rev 8

STM32L412xx Functional overview

The Arm

SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.

Debug is performed using only two pins instead of the five required by the JTAG (JTAG pins can be reused as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

3.29.2 Embedded Trace Macrocell™

The Arm ® Embedded Trace Macrocell™ provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the

STM32L412xx through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. Real-time instruction and data flow activity be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors.

The Embedded Trace Macrocell™ operates with third party debugger software tools.

DS12469 Rev 8 49/192

Pinouts and pin description

4 Pinouts and pin description

Figure 5. STM32L412Rx LQFP64 pinout (1)

STM32L412xx

VBAT

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

PH0-OSC_IN

PH1-OSC_OUT

NRST

PC0

PC1

PC2

PC3

VSSA/VREF-

VDDA/VREF+

PA0

PA1

PA2

LQFP64

PA9

PA8

PC9

PC8

PC7

PC6

PB15

PB14

PB13

PB12

VDDUSB

VSS

PA13

PA12

PA11

PA10

1. The above figure shows the package top view.

Figure 6. STM32L412Rx, external SMPS, LQFP64 pinout

(1)

MSv46920V1

VBAT

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

PH0-OSC_IN

PH1-OSC_OUT

NRST

PC0

PC1

PC2

PC3

VSSA/VREF-

VDDA/VREF+

PA0

PA1

PA2

LQFP64

50/192

1. The above figure shows the package top view.

DS12469 Rev 8

PA9

PA8

PC9

PC8

PC7

PC6

VDDUSB

VSS

PA13

PA12

PA11

PA10

PB15

PB14

PB13

PB12

MS46959V1

STM32L412xx Pinouts and pin description

Figure 7. STM32L412Rx UFBGA64 ballout (1)

1 2 3 4 5 6 7 8

PC14-

OSC32_IN

PC15-

OSC32_OUT

PC13

VBAT

PB9

PB8

PB4

PH3-BOOT0

PB3

PD2

PA15

PC11

PA14

PC10

PA13

PA12

PB7 PB5 PC12 PA10 PA9 PA11 PH0-OSC_IN VSS

PH1-

OSC_OUT

NRST

VDD

PC1

PB6

PC0

VSS

VDD

VSS

VDDUSB

VSS

VDD

PA8

PC7

PC9

PC8

VSSA/VREFPC2

PC3 PA0

VDDA/VREF+ PA1

PA2

PA3

PA4

PA5

PA6

PA7

PB0

PB1

PC4

PC6

PB2

PC5

PB15

PB10

PB11

PB14

PB13

PB12

MSv46919V1

1. The above figure shows the package top view.

Figure 8. STM32L412Rx UFBGA64, external SMPS, ballout (1)

1 2 3 4 5 6 7 8

PC14-

OSC32_IN

PC15-

OSC32_OUT

PC13

VBAT

PH0-OSC_IN VSS

PH1-

OSC_OUT

NRST

VDD

PC1

PB9

PB8

PB7

PB6

PC0

PB4

PH3-BOOT0 VDD12

PB5

VSS

VDD

PB3

PC12

VSS

VDDUSB

PA15

PC11

PA10

VSS

VDD

PA14

PC10

PA9

PA8

PC7

PA13

PA12

PA11

PC9

PC8

F VSSA/VREFPC2 PA2 PA5 PB0 PC6 PB15 PB14

PC3 PA0

VDDA/VREF+ PA1

PA3

PA4

PA6

PA7

PB1

PC4

PB2

VDD12

PB10

PB11

PB13

PB12

MS53656V1

1. The above figure shows the package top view.

DS12469 Rev 8 51/192

Pinouts and pin description

Figure 9. STM32L412Cx LQFP48 pinout (1)

STM32L412xx

VBAT

PC13

PC14/OSC32_IN

PC15/OSC32_OUT

PH0/OSC_IN

PH1/OSC_OUT

NRST

VSSA

VDDA

PA0/CK_IN

PA1

PA2

LQFP48

VDDUSB

VSS

PA13

PA12

PA11

PA10

PA9

PA8

PB15

PB14

PB13

PB12

1. The above figure shows the package top view.

Figure 10. STM32L412Cx UFQFPN48 pinout

(1)

MSv46916V1

VBAT

PC13

PC14/OSC32_IN

PC15/OSC32_OUT

PH0/OSC_IN

PH1/OSC_OUT

NRST

VSSA

VDDA

PA0/CK_IN

PA1

PA2

UFQFPN48

VDDUSB

VSS

PA13

PA12

PA11

PA10

PA9

PA8

PB15

PB14

PB13

PB12

1. The above figure shows the package top view.

MSv46917V1

52/192 DS12469 Rev 8

STM32L412xx Pinouts and pin description

Figure 11. STM32L412Tx WLCSP36 ballout (1)

1 2 3 4 5 6

PA12 PA14 PB4 PB7 VSS VDD

B PA11 PA13 PB3 PB6 PB8 PC14

C PA9 PA10 PA15 PB5

PH3

BOOT0

PC15

D PA8 PB1 PA6 PA1 PA0 NRST

VDD PB2 PA7 PA5 PA2 VREF+

F VSS PB10 PB0 PA4 PA3 VDDA

MS49688V1

1. The above figure shows the package top view.

Figure 12. STM32L412Tx, external SMPS, WLCSP36 ballout (1)

1 2 3 4 5 6

PA12 PA14 PB4 PB7 VSS VDD

PA11 PA13 PB3 PB6 VDD12 PC14

PA9 PA10 PA15 PB5 PH3 PC15

PA8 PB1 PA6 PA2

VDD PB10 PB0 PA5

VSS VDD12 PB2 PA7

PA1 NRST

PA3

VDDA/

VREF+

PA4 PA0

MS51459V1

1. The above figure shows the package top view.

DS12469 Rev 8 53/192

Pinouts and pin description

Figure 13. STM32L412Kx LQFP32 pinout (1)

STM32L412xx

VDD

PC14-OSC32_IN

PC15-OSC32_OUT

NRST

VDDA/VREF+

PA0-CK_IN

PA1

PA2

LQFP32

PA14

PA13

PA12

PA11

PA10

PA9

PA8

VDD

1. The above figure shows the package top view.

Figure 14. STM32L412Kx UFQFPN32 pinout (1)

MSv46914V1

VDD

PC14-OSC32_IN

PC15-OSC32_OUT

NRST

VDDA/VREF+

PA0-CK_IN

PA1

PA2

UFQFPN32

PA14

PA13

PA12

PA11

PA10

PA9

PA8

VDD

1. The above figure shows the package top view.

MSv46915V1

54/192 DS12469 Rev 8

STM32L412xx Pinouts and pin description

Name

Pin name

Pin type

I/O structure

Table 13. Legend/abbreviations used in the pinout table

Abbreviation Definition

Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name

Supply pin

Input only pin

I/O

RST

Input / output pin

5 V tolerant I/O

3.6 V tolerant I/O

Bidirectional reset pin with embedded weak pull-up resistor

(1)

(2)

(3)

Option for TT or FT I/Os

I/O, Fm+ capable

I/O, with USB function supplied by V

DDUSB

I/O, with Analog switch function supplied by V

DDA

Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset.

Notes

Pin functions

Alternate functions

Functions selected through GPIOx_AFR registers

Additional functions

Functions directly selected/enabled through peripheral registers

DS12469 Rev 8 55/192

Pin Number

Table 14. STM32L412xx pin definitions

Pin name

(function after reset)

Alternate functions Additional functions

E6 E6

11 11 G1 G1

8 8 12 12 F1

VBAT

PC13

I/O

PC14-OSC32_IN

(PC14)

PC15-

OSC32_OUT

(PC15)

PH0-OSC_IN

(PH0)

PH1-OSC_OUT

(PH1)

NRST

I/O

PC0

PC1

PC2

PC3

VSSA/VREF-

VREF+

I/O

EVENTOUT

RST

I/O FT_fa -

I/O FT_a -

FT_a -

EVENTOUT

TRACECK, LPTIM1_IN1,

I2C3_SCL, LPUART1_RX,

LPTIM2_IN1, EVENTOUT

TRACED0, LPTIM1_OUT,

I2C3_SDA, LPUART1_TX,

EVENTOUT

LPTIM1_IN2, SPI2_MISO,

EVENTOUT

LPTIM1_ETR, SPI2_MOSI,

LPTIM2_ETR, EVENTOUT

RTC_TAMP1/RTC_TS/RT

C_OUT1/WKUP2

OSC32_IN

OSC32_OUT

OSC_IN

OSC_OUT

ADC12_IN4

ADC12_IN1

ADC12_IN2

ADC12_IN3

Pin Number

Table 14. STM32L412xx pin definitions (continued)

Pin name

(function after reset)

Alternate functions Additional functions

5 5 E6

9 9 13 13 H1

10 10 14 14 G2 G2

VDDA

VDDA/VREF+

PA0

10 10 F5 F4 14 14 20 20 H3

PA0-CK_IN

PA1

PA2

PA3

VSS

VDD

PA4

I/O

FT_a

TT_a

FT_a -

TIM2_CH1, USART2_CTS,

COMP1_OUT, TIM2_ETR,

EVENTOUT

OPAMP1_VINP,

COMP1_INM, ADC1_IN5,

RTC_TAMP2/WKUP1

TIM2_CH1, USART2_CTS,

COMP1_OUT, TIM2_ETR,

EVENTOUT

OPAMP1_VINP,

COMP1_INM, ADC1_IN5,

RTC_TAMP2/WKUP1,

CK_IN

TIM2_CH2, I2C1_SMBA,

SPI1_SCK,

USART2_RTS_DE,

TIM15_CH1N, EVENTOUT

TIM2_CH3, USART2_TX,

LPUART1_TX,

QUADSPI_BK1_NCS,

TIM15_CH1, EVENTOUT

TIM2_CH4, USART2_RX,

LPUART1_RX,

QUADSPI_CLK,

TIM15_CH2, EVENTOUT

SPI1_NSS, USART2_CK,

LPTIM2_OUT, EVENTOUT

OPAMP1_VINM,

COMP1_INP, ADC1_IN6

ADC12_IN7,

WKUP4/LSCO

OPAMP1_VOUT,

ADC12_IN8

COMP1_INM, ADC12_IN9

Pin Number

Table 14. STM32L412xx pin definitions (continued)

Pin name

(function after reset)

Alternate functions Additional functions

11 11 E4 E4 15 15 21 21 F4 F4

12 12 D3 D3 16 16 22 22 G4 G4

13 13 F4 E3 17 17 23 23 H4 H4

24 24 H5

25 H6

14 14 E3 F3 18 18 25 26 F5 F5

15 15 D2 D2 19 19 26 27 G5 G5

F3 E2 20 20 27 28 G6 G6

PA5

PA6

PA7

PC4

PC5

PB0

PB1

PB2

I/O

TT_a

FT_a

I/O FT_fa

I/O

FT_a

I/O FT_a

I/O

FT_a

TIM2_CH1, TIM2_ETR,

SPI1_SCK, LPTIM2_ETR,

EVENTOUT

TIM1_BKIN, SPI1_MISO,

COMP1_OUT,

USART3_CTS,

LPUART1_CTS,

QUADSPI_BK1_IO3,

TIM16_CH1, EVENTOUT

TIM1_CH1N, I2C3_SCL,

SPI1_MOSI,

QUADSPI_BK1_IO2,

EVENTOUT

COMP1_INM,

ADC12_IN10

ADC12_IN11

ADC12_IN12

USART3_TX, EVENTOUT

USART3_RX, EVENTOUT

COMP1_INM,

ADC12_IN13

COMP1_INP,

ADC12_IN14, WKUP5

TRACED0, TIM1_CH2N,

SPI1_NSS, USART3_CK,

QUADSPI_BK1_IO1,

COMP1_OUT, EVENTOUT

ADC12_IN15

TRACED1, TIM1_CH3N,

USART3_RTS_DE,

LPUART1_RTS_DE,

QUADSPI_BK1_IO0,

LPTIM2_IN1, EVENTOUT

COMP1_INM,

ADC12_IN16

LPTIM1_OUT, I2C3_SMBA,

EVENTOUT

COMP1_INP, RTC_OUT2

Pin Number

Table 14. STM32L412xx pin definitions (continued)

Pin name

(function after reset)

Alternate functions Additional functions

E2 F2 21 21 28 29 G7 G7

22 22 29 30 H7 H7

F2 30 -

16 16 F1 F1 23 23 31 31 D6

17 17 E1 E1 24 24 32 32 E6

25 25 33 33 H8 H8

26 26 34 34 G8 G8

27 27 35 35 F8 F8

PB10

PB11

VDD12

VSS

VDD

PB12

PB13

PB14

I/O

FT_f

TIM2_CH3, I2C2_SCL,

SPI2_SCK, USART3_TX,

LPUART1_RX, TSC_SYNC,

QUADSPI_CLK,

COMP1_OUT, EVENTOUT

TIM2_CH4, I2C2_SDA,

USART3_RX, LPUART1_TX,

QUADSPI_BK1_NCS,

EVENTOUT

TIM1_BKIN, I2C2_SMBA,

SPI2_NSS, USART3_CK,

LPUART1_RTS_DE,

TSC_G1_IO1, TIM15_BKIN,

EVENTOUT

TIM1_CH1N, I2C2_SCL,

SPI2_SCK, USART3_CTS,

LPUART1_CTS,

TSC_G1_IO2, TIM15_CH1N,

EVENTOUT

TIM1_CH2N, I2C2_SDA,

SPI2_MISO,

USART3_RTS_DE,

TSC_G1_IO3, TIM15_CH1,

EVENTOUT

Pin Number

Table 14. STM32L412xx pin definitions (continued)

Pin name

(function after reset)

Alternate functions Additional functions

28 28 36 36 F7

37 37 F6

38 38 E7

18 18 D1 D1 29 29 41 41 D7 D7

19 19 C1 C1 30 30 42 42 C7 C7

20 20 C2 C2 31 31 43 43 C6 C6

21 21 B1 B1 32 32 44 44 C8 C8

22 22 A1 A1 33 33 45 45 B8 B8

PB15

PC6

PC7

PC8

PC9

PA8

PA9

PA10

PA11

PA12

I/O

RTC_REFIN, TIM1_CH3N,

SPI2_MOSI, TSC_G1_IO4,

TIM15_CH2, EVENTOUT

TSC_G4_IO1, EVENTOUT

TSC_G4_IO2, EVENTOUT

FT_f

FT_u -

TSC_G4_IO3, EVENTOUT

TSC_G4_IO4, USB_NOE,

EVENTOUT

MCO, TIM1_CH1,

USART1_CK, LPTIM2_OUT,

EVENTOUT

TIM1_CH2, I2C1_SCL,

USART1_TX, TIM15_BKIN,

EVENTOUT

TIM1_CH3, I2C1_SDA,

USART1_RX,

USB_CRS_SYNC,

EVENTOUT

TIM1_CH4, TIM1_BKIN2,

SPI1_MISO, COMP1_OUT,

USART1_CTS, USB_DM,

TIM1_BKIN2_COMP1,

EVENTOUT

TIM1_ETR, SPI1_MOSI,

USART1_RTS_DE,

USB_DP, EVENTOUT

Pin Number

Table 14. STM32L412xx pin definitions (continued)

Pin name

(function after reset)

Alternate functions Additional functions

51 51 B7

PA13

(JTMS/SWDIO)

VSS

VDDUSB

PA14

(JTCK/SWCLK)

PA15 (JTDI)

PC10

PC11

PC12

PD2

PB3

(JTDO/TRACESW

I/O

FT_a -

JTMS/SWDIO, IR_OUT,

USB_NOE, EVENTOUT

JTCK/SWCLK,

LPTIM1_OUT, I2C1_SMBA,

EVENTOUT

JTDI, TIM2_CH1,

TIM2_ETR, USART2_RX,

SPI1_NSS,

USART3_RTS_DE,

TSC_G3_IO1, EVENTOUT

TRACED1, USART3_TX,

TSC_G3_IO2, EVENTOUT

USART3_RX, TSC_G3_IO3,

EVENTOUT

TRACED3, USART3_CK,

TSC_G3_IO4, EVENTOUT

TRACED2,

USART3_RTS_DE,

TSC_SYNC, EVENTOUT

JTDO/TRACESWO,

TIM2_CH2, SPI1_SCK,

USART1_RTS_DE,

EVENTOUT

Pin Number

Table 14. STM32L412xx pin definitions (continued)

Pin name

(function after reset)

Alternate functions Additional functions

27 27 A3 A3 40 40 55 56 A4 A4 PB4 (NJTRST)

B5 45 45 60 61 B3

46 46 61 62 A3

B5 62 -

32 32 A5 A5 47 47 63 63 D4

1 1 A6 A6 48 48 64 64 E4

PB5

PB6

PB7

PH3-BOOT0

(BOOT0)

PB8

PB9

VDD12

VSS

VDD

I/O

I/O FT_fa -

I/O FT

I/O FT_fa -

NJTRST, I2C3_SDA,

SPI1_MISO, USART1_CTS,

TSC_G2_IO1, EVENTOUT

TRACED2, LPTIM1_IN1,

I2C1_SMBA, SPI1_MOSI,

USART1_CK, TSC_G2_IO2,

TIM16_BKIN, EVENTOUT

TRACED3, LPTIM1_ETR,

I2C1_SCL, USART1_TX,

TSC_G2_IO3, TIM16_CH1N,

EVENTOUT

TRACECK, LPTIM1_IN2,

I2C1_SDA, USART1_RX,

TSC_G2_IO4, EVENTOUT

I/O FT EVENTOUT

FT_f

I2C1_SCL, TIM16_CH1,

EVENTOUT

IR_OUT, I2C1_SDA,

SPI2_NSS, EVENTOUT

PVD_IN

Port

AF0

SYS_AF

AF1

TIM1/TIM2/LPT

IM1

TIM2_CH1

Table 15. Alternate function AF0 to AF7 (1)

AF2 AF3 AF4

TIM1/TIM2

USART2

I2C1/I2C2/I2C3

PA0

PA1

Port A

PA6

PA7

PA8

PA9

PA2

PA3

PA4

PA5

PA10

PA11

MCO

TIM2_CH2

TIM2_CH3

TIM2_CH4

TIM2_CH1

TIM1_BKIN

TIM1_CH1N

TIM1_CH1

TIM1_CH2

TIM1_CH3

TIM1_CH4

PA12 TIM1_ETR

PA13 JTMS/SWDAT IR_OUT

PA14 JTCK/SWCLK LPTIM1_OUT

PA15 JTDI TIM2_CH1

TIM2_ETR

TIM1_BKIN2

TIM2_ETR

USART2_RX

I2C1_SMBA

I2C3_SCL

I2C1_SCL

I2C1_SDA

I2C1_SMBA

AF5

SPI1/SPI2

SPI1_SCK

SPI1_NSS

SPI1_SCK

SPI1_MISO

SPI1_MOSI

SPI1_MISO

SPI1_MOSI

SPI1_NSS

AF6 AF7

COMP1

USART1/USA

RT2/USART3

USART2_CTS

USART2_RTS_

USART2_TX

USART2_RX

USART2_CK

COMP1_OUT USART3_CTS

USART1_CK

USART1_TX

USART1_RX

COMP1_OUT USART1_CTS

USART1_RTS_

USART3_RTS_

Port

AF0

SYS_AF

AF1

Table 15. Alternate function AF0 to AF7 (1) (continued)

AF2 AF3 AF4 AF5

TIM1/TIM2/LPT

IM1

TIM1_CH2N

TIM1/TIM2

USART2

I2C1/I2C2/I2C3

SPI1/SPI2

SPI1_NSS PB0

PB1

TRACED0

TRACED1 TIM1_CH3N

Port B

PB2

PB3

PB4

PB5

PB6

PB7

PB8

PB9

PB10

PB11

PB12

PB13

JTDO/TRACES

NJTRST

TRACED2

TRACED3

TRACECK

LPTIM1_OUT

TIM2_CH2

LPTIM1_IN1

LPTIM1_ETR

LPTIM1_IN2

IR_OUT

TIM2_CH3

TIM2_CH4

TIM1_BKIN

TIM1_CH1N

PB14 TIM1_CH2N

PB15 RTC_REFIN TIM1_CH3N

I2C3_SMBA

I2C3_SDA

I2C1_SMBA

I2C1_SCL

I2C1_SDA

I2C1_SCL

I2C1_SDA

I2C2_SCL

I2C2_SDA

I2C2_SMBA

I2C2_SCL

I2C2_SDA

SPI1_SCK

SPI1_MISO

SPI1_MOSI

SPI2_NSS

SPI2_SCK

SPI2_NSS

SPI2_SCK

SPI2_MISO

SPI2_MOSI

AF6

COMP1

AF7

USART1/USA

RT2/USART3

USART3_CK

USART3_RTS_

USART1_RTS_

USART1_CTS

USART1_CK

USART1_TX

USART1_RX

USART3_TX

USART3_RX

USART3_CK

USART3_CTS

USART3_RTS_

Port

AF0

SYS_AF

Port C

PC7

PC8

PC9

PC10

PC11

PC12

PC13

PC14

PC15

PC0

PC1

PC2

PC3

PC4

PC5

PC6

TRACECK

TRACED0

TRACED1

TRACED3

Port D PD2 TRACED2

Port H

PH0

PH1

PH3 -

1. Refer to

Table 16

for AF8 to AF15.

AF1

Table 15. Alternate function AF0 to AF7 (1) (continued)

AF2 AF3 AF4 AF5

TIM1/TIM2/LPT

IM1

LPTIM1_IN1

LPTIM1_OUT

LPTIM1_IN2

LPTIM1_ETR

TIM1/TIM2 USART2

I2C1/I2C2/I2C3

I2C3_SCL

I2C3_SDA

SPI1/SPI2

SPI2_MISO

SPI2_MOSI

AF6

COMP1

AF7

USART1/USA

RT2/USART3

USART3_TX

USART3_RX

USART3_TX

USART3_RX

USART3_CK

USART3_RTS_

AF8

Port

LPUART1

PA0

PA1

PA2 LPUART1_TX

PA3 LPUART1_RX

PA4

PA5

PA6 LPUART1_CTS

Port A

PA7

PA8

PA9

PA10

PA11

PA12

PA13

PA14

PA15 -

AF9

Table 16. Alternate function AF8 to AF15 (1)

AF10

TSC

TSC_G3_IO1

QUADSPI

QUADSPI_BK1

_NCS

QUADSPI_CLK

QUADSPI_BK1

_IO3

QUADSPI_BK1

_IO2

USB_CRS_SY

USB_DM

USB_DP

USB_NOE

AF11

AF12

COMP1

COMP1_OUT

TIM1_BKIN2_C

OMP1

AF13

AF14 AF15

TIM2/TIM15/

TIM16/LPTIM2

EVENOUT

TIM2_ETR EVENTOUT

TIM15_CH1N EVENTOUT

TIM15_CH1 EVENTOUT

TIM15_CH2 EVENTOUT

LPTIM2_OUT EVENTOUT

LPTIM2_ETR EVENTOUT

TIM16_CH1 EVENTOUT

EVENTOUT

LPTIM2_OUT EVENTOUT

TIM15_BKIN EVENTOUT

EVENTOUT

AF8 AF9

Table 16. Alternate function AF8 to AF15 (1) (continued)

AF10 AF11 AF12 AF13

Port

LPUART1 TSC

PB0 -

Port B

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PB8

LPUART1_RTS

_DE

PB9 -

PB10 LPUART1_RX

TSC_G2_IO2

TSC_G2_IO3

TSC_G2_IO4

TSC_G2_IO1

PB11 LPUART1_TX TSC_SYNC

PB12

LPUART1_RTS

_DE

TSC_G1_IO1

PB13 LPUART1_CTS TSC_G1_IO2

PB14 TSC_G1_IO3

PB15 TSC_G1_IO4

QUADSPI

QUADSPI_BK1

_IO1

QUADSPI_BK1

_IO0

QUADSPI_CLK

QUADSPI_BK1

_NCS

COMP1

COMP1_OUT

AF14

TIM2/TIM15/

TIM16/LPTIM2

AF15

EVENOUT

EVENTOUT

LPTIM2_IN1 EVENTOUT

EVENTOUT

TIM16_BKIN EVENTOUT

TIM16_CH1N EVENTOUT

TIM16_CH1

EVENTOUT

TIM15_BKIN EVENTOUT

TIM15_CH1N EVENTOUT

TIM15_CH1 EVENTOUT

TIM15_CH2 EVENTOUT

AF8 AF9

Table 16. Alternate function AF8 to AF15 (1) (continued)

AF10 AF11 AF12 AF13

Port

LPUART1 TSC QUADSPI

Port C

PC15

Port D PD2

Port H

PH0

PH1

PH3

PC7

PC8

PC9

PC10

PC11

PC12

PC13

PC14

PC0 LPUART1_RX

PC1 LPUART1_TX

PC2 -

PC3

PC4

PC5

PC6

1. Refer to

Table 15

for AF0 to AF7.

TSC_G4_IO1

TSC_G4_IO2

TSC_G4_IO3 -

TSC_G4_IO4 USB_NOE

TSC_G3_IO2 -

TSC_G3_IO3

TSC_G3_IO4

TSC_SYNC

COMP1

AF14 AF15

TIM2/TIM15/

TIM16/LPTIM2

EVENOUT

LPTIM2_IN1

EVENTOUT

LPTIM2_ETR EVENTOUT

EVENTOUT

STM32L412xx Memory mapping

Figure 15. STM32L412xx memory map

0xFFFF FFFF

Cortex™-M4 with FPU

Internal

Peripherals

0xE000 0000

0xC000 0000

QUADSPI registers

0xA000 1000

0xA000 0000

4 0x9000 0000

QUADSPI Flash bank

0x8000 0000

0x6000 0000

0x4000 0000

0x2000 A000

0x2000 8000

0x2000 0000

Peripherals

SRAM2

SRAM1

CODE

0x0000 0000

Reserved

0xBFFF FFFF

0xA000 1400

0xA000 1000

Reserved

QUADSPI registers

0x5FFF FFFF

0x5006 0C00

0x4800 0000

0x4002 4400

0x4002 0000

0x4001 5800

0x4001 0000

0x4000 9800

0x4000 0000

0x1FFF FFFF

Reserved

AHB2

Reserved

AHB1

Reserved

APB2

Reserved

APB1

Reserved

0x1FFF 7810

0x1FFF 7800

0x1FFF 7400

0x1FFF 7000

0x1FFF 0000

0x1000 2000

0x1000 0000

0x0802 0000

0x0800 0000

0x0002 0000

0x0000 0000

Options Bytes

Reserved

OTP area

System memory

Reserved

SRAM2

Reserved

Flash memory

Reserved

Flash, system memory or SRAM, depending on

BOOT configuration

MSv45997V1

DS12469 Rev 8 69/192

Memory mapping STM32L412xx

Table 17. STM32L412xx memory map and peripheral register boundary addresses (1)

Bus Boundary address Size(bytes) Peripheral

AHB2

AHB1

0x5006 0800 - 0x5006 0BFF

0x5006 0400 - 0x5006 07FF

0x5004 0400 - 5006 07FF

0x5004 0000 - 0x5004 03FF

0x5000 0000 - 0x5003 FFFF

0x4800 2000 - 0x4FFF FFFF

0x4800 1C00 - 0x4800 1FFF

0x4800 1000 - 0x4800 1BFF

0x4800 0C00 - 0x4800 0FFF

0x4800 0800 - 0x4800 0BFF

0x4800 0400 - 0x4800 07FF

0x4800 0000 - 0x4800 03FF

0x4002 4400 - 0x47FF FFFF

0x4002 4000 - 0x4002 43FF

0x4002 3400 - 0x4002 3FFF

0x4002 3000 - 0x4002 33FF

0x4002 2400 - 0x4002 2FFF

0x4002 2000 - 0x4002 23FF

0x4002 1400 - 0x4002 1FFF

0x4002 1000 - 0x4002 13FF

0x4002 0800 - 0x4002 0FFF

0x4002 0400 - 0x4002 07FF

0x4002 0000 - 0x4002 03FF

1 KB

3 KB

1 KB

3 KB

1 KB

2 KB

1 KB

128 KB

1 KB

RNG

Reserved

ADC

16 KB Reserved

~127 MB Reserved

1 KB

3 KB

GPIOH

Reserved

1 KB

GPIOD

GPIOC

GPIOB

1 KB GPIOA

~127 MB Reserved

1 KB TSC

Reserved

CRC

Reserved

FLASH registers

Reserved

RCC

Reserved

DMA2

DMA1

70/192 DS12469 Rev 8

STM32L412xx Memory mapping

Table 17. STM32L412xx memory map and peripheral register boundary addresses (1)

(continued)

Bus Boundary address Size(bytes) Peripheral

APB2

APB1

0x4001 4800 - 0x4001 FFFF

0x4001 4400 - 0x4001 47FF

0x4001 4000 - 0x4001 43FF

0x4001 3C00 - 0x4001 3FFF

0x4001 3800 - 0x4001 3BFF

0x4001 3400 - 0x4001 37FF

0x4001 3000 - 0x4001 33FF

0x4001 2C00 - 0x4001 2FFF

0x4001 2000 - 0x4001 2BFF

0x4001 1C00 - 0x4001 1FFF

0x4001 0800- 0x4001 1BFF

0x4001 0400 - 0x4001 07FF

0x4001 0200 - 0x4001 03FF

0x4001 0030 - 0x4001 01FF

0x4001 0000 - 0x4001 002F

0x4000 9800 - 0x4000 FFFF

0x4000 9400 - 0x4000 97FF

0x4000 8400 - 0x4000 93FF

0x4000 8000 - 0x4000 83FF

0x4000 7C00 - 0x4000 7FFF

0x4000 7800 - 0x4000 7BFF

0x4000 7400 - 0x4000 77FF

0x4000 7000 - 0x4000 73FF

0x4000 6C00 - 0x4000 6FFF

0x4000 6800 - 0x4000 6BFF

0x4000 6400 - 0x4000 67FF

0x4000 6000 - 0x4000 63FF

0x4000 5C00- 0x4000 5FFF

0x4000 5800 - 0x4000 5BFF

0x4000 5400 - 0x4000 57FF

0x4000 4C00 - 0x4000 53FF

0x4000 4800 - 0x4000 4BFF

0x4000 4400 - 0x4000 47FF

0x4000 4000 - 0x4000 43FF

1 KB

2 KB

1 KB

3 KB

1 KB

5 KB

1 KB

26 KB

1 KB

4 KB

46 KB

1 KB

LPUART1

LPTIM1

OPAMP

Reserved

PWR

USB SRAM

USB FS

Reserved

CRS

I2C3

I2C2

I2C1

Reserved

USART3

USART2

Reserved

TIM16

TIM15

Reserved

USART1

Reserved

SPI1

TIM1

Reserved

FIREWALL

Reserved

EXTI

COMP

Reserved

SYSCFG

Reserved

LPTIM2

Reserved

DS12469 Rev 8 71/192

Memory mapping STM32L412xx

Table 17. STM32L412xx memory map and peripheral register boundary addresses (1)

(continued)

Bus Boundary address Size(bytes) Peripheral

APB1

0x4000 3C00 - 0x4000 3FFF

0x4000 3800 - 0x4000 3BFF

0x4000 3400 - 0x4000 37FF

0x4000 3000 - 0x4000 33FF

0x4000 2C00 - 0x4000 2FFF

0x4000 2800 - 0x4000 2BFF

0x4000 1400 - 0x4000 27FF

0x4000 1000 - 0x4000 13FF

0x4000 0400- 0x4000 0FFF

0x4000 0000 - 0x4000 03FF

1. The gray color is used for reserved boundary addresses.

1 KB

5 KB

1 KB

3 KB

1 KB

SPI3

SPI2

Reserved

IWDG

WWDG

RTC

Reserved

TIM6

Reserved

TIM2

72/192 DS12469 Rev 8

STM32L412xx Electrical characteristics

6.1.1

Unless otherwise specified, all voltages are referenced to V

Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T

A the selected temperature range).

= 25 °C and T

= T

A max (given by

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ±3 σ ).

Unless otherwise specified, typical data are based on T

A are given only as design guidelines and are not tested.

= 25 °C, V

= V

DDA

= 3 V. They

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ±2 σ )

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

6.1.5

The loading conditions used for pin parameter measurement are shown in

Figure 16

Pin input voltage

The input voltage measurement on a pin of the device is described in

Figure 17 .

Figure 16. Pin loading conditions Figure 17. Pin input voltage

MCU pin MCU pin

C = 50 pF

MS19210V1

MS19211V1

DS12469 Rev 8 73/192

164

Electrical characteristics

6.1.6 Power supply scheme

Figure 18. Power supply scheme

STM32L412xx

VBAT

1.55 – 3.6 V

Power switch

Backup circuitry

(LSE, RTC,

Backup registers)

CORE n x VDD n x 100 nF

+1 x 4.7 μF

GPIOs

Regulator

DDIO1

OUT

IO logic

Kernel logic

(CPU, Digital

& Memories) n x VSS

10 nF

+1 μF

DDA

REF

VDDA

100 nF +1 μF

REF+

REF-

ADCs/

OPAMPs/

COMPs/

VSSA

MS49692V1

Caution: Each power supply pair (V

, V

DDA

SSA

etc.) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device.

74/192 DS12469 Rev 8

STM32L412xx Electrical characteristics

Figure 19. Current consumption measurement scheme with and without external

SMPS power supply

DD_USB

DDUSB

DD_USB

DDUSB

DD_VBAT

BAT

DD_VBAT

BAT

SMPS

DD12

DDA

MSv45729V1

The I

DD_ALL

parameters given in

Table 25 to

Table 47 represent the total MCU consumption

including the current supplying V

, V

DDA

, V

DDUSB

and V

BAT

6.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in

Table 18: Voltage characteristics

Table 19: Current characteristics

and

Table 20: Thermal characteristics may cause

permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 qualification standard, extended mission profiles are available on demand.

Symbol

DDX

- V

DD12

- V

(2)

Table 18. Voltage characteristics

(1)

Ratings Min

External main supply voltage (including

, V

DDA

, V

DDUSB

, V

BAT

)

External SMPS supply voltage

-0.3

Input voltage on FT_xxx pins

Input voltage on TT_xx pins

Input voltage on any other pins

-0.3

Max

4.0

1.32

min (V

, V

+ 4.0

, V

DDUSB

)

4.0

Unit

DS12469 Rev 8 75/192

164

Electrical characteristics STM32L412xx

Symbol

Table 18. Voltage characteristics (1) (continued)

Ratings Min Max Unit

| ∆ V

SSx

DDx

-V

Variations between different V

DDX pins of the same domain

power

Variations between all the different ground pins

(5)

50 mV mV

1. All main power (V , V

DDA

, V supply, in the permitted range.

DDUSB

, V

BAT

) and ground (V

, V

SSA

) pins must always be connected to the external power

2. V

maximum must always be respected. Refer to

Table 19: Current characteristics for the maximum allowed injected

current values.

3. This formula has to be applied only on the power supplies related to the IO structure described in the pin definition table.

4. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.

5. Include VREF- pin.

Symbol

∑ IV

DD(PIN)

SS(PIN)

Table 19. Current characteristics

Ratings

Total current into sum of all V

power lines (source)

(1)(2)

Total current out of sum of all V

ground lines (sink)

Maximum current into each V

power pin (source)

Maximum current out of each V

ground pin (sink)

Total output current sourced by sum of all I/Os and control pins

Output current sunk by any I/O and control pin except FT_f

Max

140

100

Unit

100

20 I

∑

IO(PIN)

Output current sunk by any FT_f pin

Output current sourced by any I/O and control pin

Total output current sunk by sum of all I/Os and control pins

(3)

Table 18: Voltage characteristics

100

100 mA

INJ(PIN)

(4)

Injected current on FT_xxx, TT_xx, RST and B pins, except PA4,

PA5

-5/+0

(5)

∑ |I

INJ(PIN)

Injected current on PA4, PA5

Total injected current (sum of all I/Os and control pins)

(6)

-5/0

1. All main power (V

, V

DDA

, V

DDUSB

, V

BAT

) and ground (V

, V

SSA

) pins must always be connected to the external power

2. Valid also for V

DD12

on SMPS packages.

3. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.

4. Positive injection (when V specified maximum value.

> V

DDIOx

) is not possible on these I/Os and does not occur for input voltages lower than the

5. A negative injection is induced by V

< V

. I

INJ(PIN)

must never be exceeded. Refer also to

for the maximum allowed input voltage values.

6. When several inputs are submitted to a current injection, the maximum ∑ |I injected currents (instantaneous values).

INJ(PIN)

| is the absolute sum of the negative

76/192 DS12469 Rev 8

STM32L412xx

Symbol

STG

Electrical characteristics

Table 20. Thermal characteristics

Ratings

Storage temperature range

Maximum junction temperature

Value

–65 to +150

150

Unit

°C

DS12469 Rev 8 77/192

164

Electrical characteristics STM32L412xx

6.3.1 General operating conditions

Table 21. General operating conditions

Symbol f

HCLK f

PCLK1 f

PCLK2

Parameter

Internal AHB clock frequency

Internal APB1 clock frequency

Internal APB2 clock frequency

Conditions

Min

Standard operating voltage -

1.71

(1)

DDA

DD12

Standard operating voltage

BAT

Analog supply voltage

Backup operating voltage

DDUSB

USB supply voltage

ADC or COMP used

OPAMP used

ADC, OPAMP, COMP not used

Full frequency range

Up to 26 MHz

USB used

USB not used

TT_xx I/O

1.62

1.8

1.08

1.00

1.55

3.0

-0.3

I/O input voltage

All I/O except TT_xx -0.3

Power dissipation at

= 85 °C for suffix 6 or

= 105 °C for suffix 7

(4)

Power dissipation at

= 125 °C for suffix 3

(4)

LQFP64

UFBGA64

LQFP48

UFQFPN48

WLCSP36

LQFP32

UFQFPN32

LQFP64

UFBGA64

LQFP48

UFQFPN48

WLCSP36

LQFP32

UFQFPN32

Max

3.6

1.32

Unit

MHz

3.6

DDIOx

+0.3

Min(Min(V

DDUSB

, V

DDA

5.5 V)

)+3.6 V,

(2)(3)

303

317

294

667

235

294

541

167

135

V mW mW

78/192 DS12469 Rev 8

STM32L412xx Electrical characteristics

Symbol

Table 21. General operating conditions (continued)

Parameter Conditions Min Max Unit

Ambient temperature for the suffix 6 version

Ambient temperature for the suffix 3 version

Junction temperature range

Maximum power dissipation

Low-power dissipation (5)

Maximum power dissipation

Low-power dissipation

(5)

Suffix 6 version

Suffix 3 version

–40

105

125

130

105

130

1. When RESET is released functionality is guaranteed down to V

BOR0

Min.

2. This formula has to be applied only on the power supplies related to the IO structure described by the pin definition table.

Maximum I/O input voltage is the smallest value between Min(V

, V

DDA

, V

DDUSB

)+3.6 V and 5.5V.

3. For operation with voltage higher than Min (V be disabled.

, V

DDA

, V

DDUSB

) +0.3 V, the internal Pull-up and Pull-Down resistors must

4. If T

is lower, higher P

values are allowed as long as T

does not exceed T

Jmax

(see Section 7.8: Thermal characteristics

5. In low-power dissipation state, T

Thermal characteristics

can be extended to this range as long as T

does not exceed T

Jmax

(see Section 7.8:

°C

6.3.3

The parameters given in

Table 22 are derived from tests performed under the ambient

temperature condition summarized in

Table 21 .

Symbol t

VDD t

VDDA t

VDDUSB

Table 22. Operating conditions at power-up / power-down

Parameter Conditions Min Max

rise time rate

fall time rate

DDA

rise time rate

DDA

fall time rate

DDUSB

rise time rate

DDUSB

fall time rate

ULPEN = 0

ULPEN = 1

100

∞

Unit

µs/V ms/V

µs/V

Embedded reset and power control block characteristics

The parameters given in

Table 23 are derived from tests performed under the ambient

temperature conditions summarized in Table 21: General operating conditions

Table 23. Embedded reset and power control block characteristics

Symbol Parameter Conditions

(1)

Min Typ Max t

RSTTEMPO

(2)

Reset temporization after

BOR0 is detected

DD rising 250 400

BOR0

(2)

Brown-out reset threshold 0

Rising edge

Falling edge

1.62

1.6

1.66

1.64

1.7

1.69

Unit

μ s

DS12469 Rev 8 79/192

164

Electrical characteristics STM32L412xx

Table 23. Embedded reset and power control block characteristics (continued)

Symbol Parameter Conditions (1) Min Typ Max Unit

BOR1

BOR2

BOR3

BOR4

PVD0

PVD1

PVD2

PVD3

PVD4

PVD5

PVD6 hyst_BORH0

Brown-out reset threshold 1

Brown-out reset threshold 2

Brown-out reset threshold 3

Brown-out reset threshold 4

Programmable voltage detector threshold 0

PVD threshold 1

PVD threshold 2

PVD threshold 3

PVD threshold 4

PVD threshold 5

PVD threshold 6

Hysteresis voltage of BORH0

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Hysteresis in continuous mode

Hysteresis in other mode

V hyst_BOR_PVD

(BOR_PVD)

(2)

PVM1

Hysteresis voltage of BORH

(except BORH0) and PVD

BOR

(3)

(except BOR0) and

PVD consumption from V

BOR (3) (except BOR0) and

PVD average consumption from V

DD with ENULP = 1

DDUSB

peripheral voltage monitoring

PVM3

DDA

peripheral voltage monitoring

Rising edge

Falling edge

2.1

2.26

2.15

2.41

2.31

2.56

2.47

2.85

2.76

2.06

1.96

2.26

2.16

2.47

2.69

2.59

2.85

2.75

2.92

2.84

1.18

1.61

1.6

2.15

2.05

2.31

2.20

2.46

2.36

2.61

2.52

2.90

2.81

2.1

2.31

2.20

2.52

2.74

2.64

2.91

2.81

2.98

2.90

100

1.1

1.22

1.65

1.64

2.19

2.1

2.36

2.25

2.51

2.41

2.66

2.57

2.95

2.86

2.14

2.04

2.35

2.24

2.57

2.79

2.69

2.96

2.86

3.04

2.96

1.6

1000

1.26

1.69

1.68

V mV mV

µA nA

80/192 DS12469 Rev 8

STM32L412xx Electrical characteristics

Table 23. Embedded reset and power control block characteristics (continued)

Symbol Parameter Conditions (1) Min Typ Max Unit

PVM4

V hyst_PVM3

V hyst_PVM4

(PVM1)

(2)

DDA

peripheral voltage monitoring

PVM3 hysteresis

PVM4 hysteresis

PVM1 consumption from V

Rising edge

Falling edge

1.78

1.77

1.82

1.81

0.2

1.86

1.85

V mV mV

µA

(PVM3/PVM4)

(2)

PVM3 and PVM4 consumption from V

2 µA

1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes.

2. Guaranteed by design.

3. BOR0 is enabled in all modes (except shutdown) and its consumption is therefore included in the supply current characteristics tables.

DS12469 Rev 8 81/192

164

Electrical characteristics STM32L412xx

The parameters given in

Table 24 are derived from tests performed under the ambient

temperature and supply voltage conditions summarized in Table 21: General operating conditions

Symbol

Table 24. Embedded internal voltage reference

Parameter Conditions Min Typ Max

REFINT

Internal reference voltage t t

S_vrefint

(1) start_vrefint

ADC sampling time when reading the internal reference voltage

Start time of reference voltage buffer when ADC is enable

REFINTBUF

)

REFINT

buffer consumption from V

ADC

when converted by

–40 °C < T

< +130 °C

∆ V

REFINT

Internal reference voltage spread over the temperature range

= 3 V

Coeff

DDCoeff

REFINT_DIV1

REFINT_DIV2

REFINT_DIV3

Temperature coefficient

Long term stability

Voltage coefficient

1/4 reference voltage

1/2 reference voltage

3/4 reference voltage

–40°C < T

< +130°C

1000 hours, T = 25°C

3.0 V < V

< 3.6 V

1. The shortest sampling time can be determined in the application by multiple iterations.

2. Guaranteed by design.

1.182

1.212

1.232

(2)

12.5

7.5

(2)

30 50

(2)

300 1000

(2)

250 1200

(2)

Unit

µs

µA mV ppm/°C ppm ppm/V

REFINT

82/192 DS12469 Rev 8

STM32L412xx

1.235

1.23

1.225

1.22

1.215

1.21

1.205

1.2

1.195

1.19

1.185

-40 -20

Electrical characteristics

Figure 20. V

REFINT

versus temperature

0 20

Mean

Min

Max

80 100 120 °C

MSv40169V1

DS12469 Rev 8 83/192

164

Electrical characteristics

6.3.5 Supply current characteristics

STM32L412xx

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code.

The current consumption is measured as described in

Figure 19: Current consumption measurement scheme with and without external SMPS power supply .

Typical and maximum current consumption

The MCU is placed under the following conditions:

• All I/O pins are in analog input mode

• All peripherals are disabled except when explicitly mentioned

• The Flash memory access time is adjusted with the minimum wait states number, depending on the f

HCLK

frequency (refer to the table “Number of wait states according to CPU clock (HCLK) frequency” available in the RM0394 reference manual).

• When the peripherals are enabled f

PCLK

= f

HCLK

The parameters given in

Table 25 to

Table 48 are derived from tests performed under

ambient temperature and supply voltage conditions summarized in

Table 21: General operating conditions

84/192 DS12469 Rev 8

Symbol Parameter

DD_ALL

(Run)

DD_ALL

(LPRun)

Table 25. Current consumption in Run and Low-power run modes, code with data processing running from Flash, ART enable (Cache ON Prefetch OFF)

Conditions TYP MAX

(1)

Voltage scaling f

HCLK

25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C

Unit

26 MHz 2.05

2.10

16 MHz 1.30

1.35

1.40

2.20

1.45

2.35

1.60

2.20

2.25

1.40

1.45

2.30

1.50

2.40

1.60

2.60

1.80

Supply current in

Run mode f

HCLK

= f

HSE

up to

48MHz included, bypass mode

PLL ON above

48 MHz all peripherals disable

Range 2

8 MHz 0.715 0.730 0.780

0.855

1.00

0.76

0.78

4 MHz 0.415 0.430 0.475

0.555

0.710

0.45

0.50

2 MHz 0.265

0.28

0.325

0.400

0.555

0.30

1 MHz 0.190 0.205 0.250

0.325

0.480

0.20

0.25

100 kHz 0.120 0.135 0.180

0.255

0.410

0.15

0.20

80 MHz 7.30

7.35

7.40

7.55

7.70

7.75

7.80

72 MHz 6.60

6.65

6.70

64 MHz 5.90

5.90

6.00

6.80

6.10

7.00

6.30

7.00

6.25

7.00

6.30

Supply current in

Low-power run mode f

HCLK

= f

MSI all peripherals disable

Range 1 48 MHz 4.40

4.40

4.50

32 MHz 3.00

3.00

3.05

24 MHz 2.30

2.30

2.35

16 MHz 1.55

1.60

1.65

2 MHz 190 205

1 MHz 110 120

255

165

400 kHz 55.0

65.5

115

100 kHz 26.0

40.0

87.5

4.60

3.15

2.45

1.75

335

250

195

170

4.80

3.35

2.65

1.90

505

415

360

335

4.70

3.20

2.40

1.70

235

135

75.0

45.0

4.75

3.25

2.40

1.75

230

145

90.5

65.5

455

370

325

290

4.90

3.40

2.60

1.90

0.40

7.90

7.20

6.40

0.96

0.70

0.50

0.44

315

230

180

160

4.80

3.30

2.50

1.80

0.25

7.80

7.10

6.35

0.84

0.55

0.40

0.30

µA

725

645

590

550

5.10

3.60

2.90

2.20

0.60

8.10

7.40

6.65

1.25

0.90

0.80

0.70

1. Guaranteed by characterization results, unless otherwise specified.

Symbol

DD_ALL

(Run)

Table 26. Current consumption in Run modes, code with data processing running from Flash,

ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS

DD12

= 1.10 V)

Conditions

(1)

Parameter

TYP

HCLK

25 °C 55 °C 85 °C 105 °C 125 °C

Unit

Supply current in Run mode f

HCLK

= f

HSE

up to 48MHz included, bypass mode

PLL ON above

48 MHz all peripherals disable

80 MHz 2.62

2.64

72 MHz 2.37

2.39

64 MHz 2.12

2.12

48 MHz 1.58

1.58

32 MHz 1.08

1.08

24 MHz 0.83

0.83

16 MHz 0.56

0.58

8 MHz 0.26

0.26

4 MHz 0.15

0.15

2 MHz 9.53

0.10

1 MHz 0.07

0.07

100 kHz 0.01

0.01

1.10

0.84

0.59

0.28

2.66

2.41

2.16

1.62

0.17

0.12

0.09

0.03

1.13

0.88

0.63

0.31

2.71

2.44

2.19

1.65

0.20

0.14

0.12

0.06

1.20

0.95

0.68

0.36

2.77

2.52

2.26

1.73

0.26

0.20

0.17

0.12

1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%,

DD12

= 1.10 V

Symbol Parameter

Table 27. Current consumption in Run and Low-power run modes, code with data processing running from Flash, ART disable

Conditions TYP MAX

(1)

Voltage scaling f

HCLK

25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C

Unit

DD_ALL

(Run)

DD_ALL

(LPRun)

Supply current in

Run mode f

HCLK

= f

HSE

up to

48MHz included, bypass mode

PLL ON above

48 MHz all peripherals disable

Supply current in

Low-power run f

HCLK

= f

MSI all peripherals disable

Range 2

Range 1

26 MHz 2.40

2.45

2.50

16 MHz 1.70

1.75

1.80

8 MHz 0.970 0.985

1.05

2.55

1.85

1.10

2.75

2.05

1.25

2.60

1.85

1.05

4 MHz 0.570 0.585 0.630

0.710

0.865

0.61

2 MHz 0.340 0.355 0.400

0.475

0.635

0.40

1 MHz 0.230 0.240 0.285

0.365

0.52

0.25

100 kHz 0.125 0.140 0.185

0.260

0.415

0.14

80 MHz 7.65

7.70

7.85

72 MHz 6.95

6.95

7.05

64 MHz 6.90

6.95

7.05

48 MHz 5.85

5.90

6.00

32 MHz 4.20

4.20

4.30

24 MHz 3.15

3.20

3.25

16 MHz 2.25

2.30

2.35

2 MHz 275 290 340

8.00

7.15

7.20

6.15

4.45

3.35

2.50

425

8.20

7.35

7.40

6.35

4.65

3.55

2.65

590

8.20

7.40

6.30

4.50

3.40

2.50

325

1 MHz 155 165 210 295 460 185

400 kHz 69.0

83.0

130

100 kHz 32.0

45.5

92.0

215

175

280

340

90.5

48.0

1. Guaranteed by characterization results, unless otherwise specified.

8.80

7.80

6.90

5.10

3.90

3.00

840

3.00

2.30

1.50

1.10

0.80

0.70

0.60

690

600

570

8.50

7.60

6.65

4.80

3.60

2.70

565

2.80

2.05

1.25

0.80

0.60

0.50

0.40

420

340

300

8.40

7.50

6.50

4.70

3.50

2.60

425

2.70

1.95

1.15

0.70

0.50

0.34

0.25

275

195

155

8.30

7.45

6.35

4.55

3.40

2.50

360

2.65

1.90

1.10

0.63

0.40

0.30

0.20

195

108

69 mA

µA

Symbol

DD_ALL

(Run)

Table 28. Current consumption in Run modes, code with data processing running from Flash,

ART disable and power supplied by external SMPS (V

DD12

= 1.10 V)

Conditions

(1)

Parameter

TYP

HCLK

25 °C 55 °C 85 °C 105 °C 125 °C

Uni t

Supply current in Run mode f

HCLK

= f

HSE

up to 48MHz included, bypass mode

PLL ON above 48 MHz all peripherals disable

80 MHz 2.75

2.77

72 MHz 2.50

2.50

64 MHz 2.48

2.50

48 MHz 2.10

2.12

32 MHz 1.51

1.51

24 MHz 1.13

1.15

16 MHz 0.81

0.83

8 MHz 0.35

0.35

4 MHz 0.20

0.21

2 MHz 12.22

0.13

1 MHz 0.08

0.09

100 kHz 0.01

0.02

1.55

1.17

0.84

0.38

2.82

2.53

2.16

0.23

0.14

0.10

0.03

2.88

2.95

2.57

2.64

2.59

2.66

2.21

2.28

1.60

1.67

1.20

1.28

0.90

0.95

0.40

0.45

0.26

0.31

0.17

0.23

0.13

0.19

0.06

0.12

1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%,

DD12

= 1.10 V

Table 29. Current consumption in Run and Low-power run modes, code with data processing running from SRAM1

Conditions TYP MAX

(1)

Symbol Parameter

Voltage scaling f

HCLK

25 °C 55 °C 85 °C

105

°C

125

°C

25 °C 55 °C 85 °C

DD_ALL

(Run)

DD_ALL

(LPRun)

Supply current in

Run mode

Supply current in low-power run mode f

HCLK

48MHz included, bypass mode

PLL ON above

48 MHz all peripherals disable f

HCLK

= f

HSE

= f

MSI

up to

Range 2

Range 1 all peripherals disable

FLASH in power-down

26 MHz 2.00

2.05

2.10

2.15

2.35

2.20

2.25

2.35

2.55

16 MHz 1.30

1.30

1.35

1.45

1.60

1.40

1.45

1.55

1.80

8 MHz 0.705

0.720

0.765

0.845

1.00

0.75

0.77

0.83

0.94

1.20

4 MHz 0.410

0.425

0.470

0.550

0.700

0.44

0.46

0.52

0.64

0.90

2 MHz 0.265

0.275

0.320

0.395

0.555

0.28

0.30

0.37

0.49

0.75

1 MHz 0.190

0.200

0.245

0.325

0.475

0.21

0.22

0.29

0.42

0.67

100 kHz 0.120

0.135

0.180

0.255

0.410

0.14

0.15

0.23

0.35

0.61

80 MHz 7.15

7.20

7.25

7.45

7.55

7.65

7.75

8.00

72 MHz 6.45

6.50

6.55

6.75

6.85

6.90

6.95

7.00

7.05

7.25

64 MHz 5.75

5.80

5.85

6.05

6.15

6.20

6.25

6.30

6.50

48 MHz 4.20

4.35

4.40

4.50

7.70

4.65

4.70

4.80

5.00

32 MHz 2.95

2.95

3.00

3.10

3.30

3.15

3.20

3.30

3.55

24 MHz 2.25

2.25

2.30

2.40

2.60

2.40

2.50

2.60

2.85

16 MHz 1.55

1.55

1.60

1.70

1.85

1.65

1.70

1.75

1.85

2.10

2 MHz 180 190 240 320 485 215 225 300 450 720

1 MHz 90.5

110 155 235 400 120 135 220 360 640

400 kHz 40.5

56.0

105

100 kHz 17.5

32.0

78.5

185

160

350 60.0

76.5

325 33.5

53.5

165

140

315

285

565

555

1. Guaranteed by characterization results, unless otherwise specified.

105

°C

125

°C

Unit mA

µA

Symbol

Table 30. Current consumption in Run, code with data processing running from

SRAM1 and power supplied by external SMPS (V

DD12

= 1.10 V)

Conditions

(1)

Parameter

HCLK

TYP

25 °C 55 °C 85 °C 105 °C 125 °C

Unit

DD_ALL

(Run) Supply current in Run mode f

HCLK

= f

HSE

up to 48MHz included, bypass mode

PLL ON above

48 MHz all peripherals disable

80 MHz 2.57

2.59

2.61

72 MHz 2.32

2.34

2.35

64 MHz 2.07

2.08

2.10

48 MHz 1.55

1.56

1.58

32 MHz 1.06

1.06

1.08

24 MHz 0.81

0.81

0.83

16 MHz 0.56

0.56

0.58

8 MHz 0.25

0.26

0.28

4 MHz 0.15

0.15

0.17

2 MHz 9.53

0.10

0.12

1 MHz 0.07

0.07

0.09

100 kHz 0.01

0.01

0.03

1.11

0.86

0.61

0.30

2.68

2.43

2.17

1.62

0.20

0.15

0.14

0.06

1.19

0.93

0.67

0.36

2.71

2.46

2.21

1.69

0.25

0.20

0.17

0.12

1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%,

DD12

= 1.10 V

STM32L412xx Electrical characteristics

Table 31. Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART enable (Cache ON Prefetch OFF)

Conditions TYP TYP

Symbol Parameter Unit Unit

Voltage scaling

Code 25 °C 25 °C

Reduced code

(1)

2.05

Coremark 2.30

88 mA µA/MHz

DD_ALL

(Run)

DD_ALL

(LPRun)

Supply current in

Run mode f

HCLK

= f

HSE

up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable

Supply current in

Low-power run f

HCLK

= f

MSI

= 2 MHz all peripherals disable

Dhrystone 2.1

Fibonacci

2.35

2.25

While(1) 1.95

Reduced code

7.30

Coremark

Dhrystone 2.1

Fibonacci

While(1)

Reduced code

1. Reduced code used for characterization results provided in Table 25 ,

Coremark

8.15

8.35

8.10

7.20

Dhrystone 2.1

Fibonacci

While(1)

190

205

220

205

225 mA

µA

102

104

101

103

110

103

113

µA/MHz

Table 32. Typical current consumption in Run, with different codes running from Flash,

ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS

DD12

= 1.10 V)

Conditions

(1)

TYP TYP

Symbol Parameter Unit Unit

Voltage scaling

Code 25 °C 25 °C

DD_ALL

(Run)

Supply current in

Run mode f

HCLK

= f

HSE

up to

48 MHz included, bypass mode PLL

ON above

48 MHz all peripherals disable

Reduced code

(2)

0.88

Coremark 0.99

Dhrystone 2.1

Fibonacci

1.01

0.97

While(1) 0.84

Reduced code

(2)

3.15

Coremark

Dhrystone 2.1

Fibonacci

While(1)

3.52

3.60

3.49

3.11

µA/MHz

DS12469 Rev 8 91/192

164

Electrical characteristics STM32L412xx

1. All values are obtained by calculation based on measurements done without SMPS and using following parameters:

SMPS input = 3.3 V, SMPS efficiency = 85%, V

DD12

= 1.10 V

2. Reduced code used for characterization results provided in

Table 25 ,

Table 33. Typical current consumption in Run, with different codes running from Flash,

ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS

DD12

= 1.00 V)

Conditions

(1)

TYP TYP

Symbol Parameter Unit Unit

Voltage scaling

Code 25 °C 25 °C

DD_ALL

(Run)

Supply current in

Run mode f

HCLK

= f

HSE

up to

48 MHz included, bypass mode PLL

ON above

48 MHz all peripherals disable

Reduced code

(2)

0.73

Coremark 0.82

Dhrystone 2.1

Fibonacci

0.84

0.80

While(1) 0.70

µA/MHz

1. All values are obtained by calculation based on measurements done without SMPS and using following parameters:

SMPS input = 3.3 V, SMPS efficiency = 85%, V

DD12

= 1.00 V

2. Reduced code used for characterization results provided in

Table 25 ,

92/192 DS12469 Rev 8

STM32L412xx Electrical characteristics

Table 34. Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART disable

TYP Conditions TYP

Symbol Parameter

Voltage scaling

Code 25 °C

DD_ALL

(Run)

DD_ALL

(LPRun)

Supply current in

Run mode

Supply current in

Low-power run f f

HCLK HSE

48 MHz included, bypass mode

PLL ON above

48 MHz all peripherals disable

HCLK

= f

MSI

up to

= 2 MHz all peripherals disable

Reduced code

(1)

2.40

Coremark 2.15

Dhrystone 2.1

Fibonacci

While(1)

Reduced code

Coremark

Dhrystone 2.1

Fibonacci

2.20

2.05

1.90

7.65

6.95

7.00

6.60

While(1)

Reduced code

1. Reduced code used for characterization results provided in Table 25 ,

Coremark

Dhrystone 2.1

Fibonacci

While(1)

6.85

275

300

315

305

385

2. Reduced code used for characterization results provided in Table 25 ,

Unit mA mA

µA

25 °C

Unit

µA/MHz

138

150

158

153

193

Table 35. Typical current consumption in Run modes, with different codes running from

Flash, ART disable and power supplied by external SMPS (V

DD12

= 1.10 V)

Conditions

(1)

TYP TYP

Symbol Parameter Unit Unit

Voltage scaling

Code 25 °C 25 °C

DD_ALL

(Run)

Supply current in

Run mode f

HCLK

= f

HSE

up to

48 MHz included, bypass mode

PLL ON above

48 MHz all peripherals disable

Reduced code

(2)

1.04

Coremark

Dhrystone 2.1

Fibonacci

0.93

0.95

0.88

While(1) 0.82

Reduced code

(2)

3.30

Coremark

Dhrystone 2.1

3.00

3.02

Fibonacci

While(1)

2.85

2.95

µA/MHz

1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%, V

DD12

= 1.10 V

2. Reduced code used for characterization results provided in Table 25 ,

DS12469 Rev 8 93/192

164

Electrical characteristics STM32L412xx

Table 36. Typical current consumption in Run modes, with different codesrunning from

Flash, ART disable and power supplied by external SMPS (V

DD12

= 1.00 V)

Conditions (1) TYP TYP

Symbol Parameter Unit Unit

Voltage scaling

Code 25 °C 25 °C

DD_ALL

(Run)

Supply current in

Run mode f

HCLK

= f

HSE

up to

48 MHz included, bypass mode

PLL ON above

48 MHz all peripherals

Reduced code

(2)

0.86

Coremark 0.77

Dhrystone 2.1

Fibonacci

While(1)

0.78

0.73

0.68

µA/MHz

1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%, V

DD12

= 1.00 V

Table 37. Typical current consumption in Run and Low-power run modes, with different codes running from SRAM1

TYP Conditions TYP

Symbol Parameter

Voltage scaling

Code 25 °C

DD_ALL

(Run)

DD_ALL

(LPRun)

Supply current in

Run mode

Supply current in

Low-power run f f

HCLK

48 MHz included, bypass mode

PLL ON above

48 MHz all peripherals disable

HCLK

= f

HSE

up to

= f

MSI

= 2 MHz all peripherals disable

Reduced code

(1)

2.00

Coremark

Dhrystone 2.1

Fibonacci

2.00

2.05

2.00

While(1)

Reduced code

Coremark

Dhrystone 2.1

Fibonacci

While(1)

Reduced code

1. Reduced code used for characterization results provided in Table 25 ,

Coremark

1.85

7.15

7.00

7.15

7.10

6.60

180

Dhrystone 2.1

Fibonacci

While(1)

185

170

2. Reduced code used for characterization results provided in Table 25 ,

Unit mA mA

µA

25 °C

Unit

µA/MHz

µA/MHz 93

94/192 DS12469 Rev 8

STM32L412xx Electrical characteristics

Table 38. Typical current consumption in Run, with different codes running from

SRAM1 and power supplied by external SMPS (V

DD12

= 1.10 V)

Conditions (1) TYP TYP

Symbol Parameter Unit

Voltage scaling

Code 25 °C 25 °C

DD_ALL

(Run)

Supply current in

Run mode f

HCLK

= f

HSE

up to

48 MHz included, bypass mode

PLL ON above

48 MHz all peripherals disable

Reduced code

(2)

0.86

Coremark 0.86

Dhrystone 2.1

Fibonacci

0.88

0.86

While(1) 0.80

Reduced code

(2)

3.08

Coremark 3.02

Dhrystone 2.1

Fibonacci

While(1)

3.08

3.06

2.85

Unit

µA/MHz

1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%, V

DD12

= 1.10 V

2. Reduced code used for characterization results provided in Table 25 ,

Table 39. Typical current consumption in Run, with different codes running from

SRAM1 and power supplied by external SMPS (V

DD12

= 1.00 V)

Conditions

(1)

TYP TYP

Symbol Parameter Unit

Voltage scaling

Code 25 °C 25 °C

DD_ALL

(Run)

Supply current in

Run mode f

HCLK

= f

HSE

up to

48 MHz included, bypass mode

PLL ON above

48 MHz all peripherals disable

Reduced code

(2)

0.71

Coremark

Dhrystone 2.1

Fibonacci

0.71

0.73

0.71

While(1) 0.66

Unit

µA/MHz

1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%, V

DD12

= 1.00 V

3. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 50: Low-power mode wakeup timings .

DS12469 Rev 8 95/192

164

Symbol Parameter

Table 40. Current consumption in Sleep and Low-power sleep modes, Flash ON

Conditions

Voltage scaling f

HCLK

TYP MAX

(1)

25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C

Unit

DD_ALL

(Sleep)

DD_ALL

(LPSleep)

Supply current in sleep mode, f

HCLK

= f

HSE

up to 48 MHz included, bypass mode pll ON above

48 MHz all peripherals disable

Range 2

Range 1

Supply current in low-power sleep mode f

HCLK

= f

MSI all peripherals disable

26 MHz 0.535 0.550 0.600

0.680

0.835

0.58

16 MHz 0.375 0.390 0.435

0.515

0.670

0.41

8 MHz 0.245 0.260 0.305

0.385

0.540

0.27

4 MHz 0.180 0.195 0.240

0.315

0.470

0.20

2 MHz 0.150 0.160 0.205

0.285

0.435

0.17

1 MHz 0.130 0.145 0.190

0.265

0.420

0.15

100 kHz 0.115 0.130 0.175

0.250

0.405

0.13

0.15

80 MHz 1.65

1.70

1.75

1.85

2.00

1.80

72 MHz 1.50

1.55

1.60

64 MHz 1.35

1.40

1.45

1.70

1.55

1.85

1.70

1.60

1.45

1.65

1.50

48 MHz 1.00

1.05

1.10

1.2

1.35

32 MHz 0.725 0.740 0.795

0.885

1.05

1.10

1.15

0.78

0.80

24 MHz 0.575 0.595 0.650

0.740

0.910

0.62

16 MHz 0.425 0.440 0.495

0.585

0.760

0.47

0.64

0.48

2 MHz 52.5

66.5

115 195 360 71.0

91.5

0.60

0.43

0.29

0.22

0.18

0.16

1 MHz 37.0

51.5

97.5

180 345 55.0

73.0

400 kHz 25.5

39.0

85.0

100 kHz 18.5

33.5

80.5

170

165

330

325

41.0

36.0

63.0

57.5

1. Guaranteed by characterization results, unless otherwise specified.

0.60

2.25

2.10

1.95

1.65

1.35

1.15

1.00

600

1.05

0.88

0.74

0.67

0.63

0.62

575

565

560

0.35

1.95

1.80

1.65

1.35

1.05

0.86

0.71

315

0.79

0.62

0.49

0.42

0.38

0.36

295

280

0.22

1.85

1.70

1.55

1.20

0.87

0.72

0.56

175

0.66

0.50

0.36

0.29

0.25

0.24

165

150

145 mA

µA

Symbol

Table 41. Current consumption in Sleep, Flash ON and power supplied by external SMPS

DD12

= 1.10 V)

Conditions

(1)

Parameter

TYP

HCLK

25 °C 55 °C 85 °C 105 °C 125 °C

DD_ALL

(Sleep) Supply current in sleep mode, f

HCLK

= f

HSE

up to 48 MHz included, bypass mode pll ON above

48 MHz all peripherals disable

80 MHz 0.59

0.61

72 MHz 0.54

0.56

64 MHz 0.49

0.50

48 MHz 0.36

0.38

32 MHz

24 MHz

16 MHz

0.26

0.21

0.15

0.27

0.21

0.16

0.63

0.58

0.52

0.40

0.29

0.23

0.18

0.67

0.61

0.56

0.43

0.32

0.27

0.21

8 MHz

4 MHz

2 MHz

1 MHz

0.09

0.06

0.07

5.39

0.06

0.05

0.11

0.09

0.07

0.14

0.11

0.10

0.19

0.17

0.15

100 kHz 0.01

0.01

0.03

0.06

0.12

1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%,

DD12

= 1.10 V

0.72

0.67

0.61

0.49

0.38

0.33

0.27

Unit mA

Symbol Parameter

Table 42. Current consumption in Low-power sleep modes, Flash in power-down

Conditions TYP MAX

(1)

Voltage scaling f

HCLK

25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C

Unit

DD_ALL

(LPSleep)

Supply current in low-power sleep mode f

HCLK

= f

MSI all peripherals disable

2 MHz

1 MHz

400 kHz 20

100 kHz 15

1. Guaranteed by characterization results, unless otherwise specified.

105

89.0

76.5

71.5

185

170

155

150

350

335

320

315

170

150

135

300

285

270

585

570

560

555

µA

Symbol

DD_ALL

(Stop 2)

DD_ALL

(Stop 2 with

RTC)

Parameter

Supply current in

Stop 2 mode,

RTC disabled

ENULP = 1

Table 43. Current consumption in Stop 2 mode

Conditions

RTC clocked by LSI

Supply current in

Stop 2 mode,

RTC enabled

RTC clocked by LSI

ENULP = 1

LPCAL = 1

RTC clocked by LSI

ENULP = 1

LPCAL = 1

LSIPREDIV = 1

TYP MAX

(1)

25 °C 55 °C 85 °C

1.8 V 0.77

2.35

8.60

2.4 V 0.78

2.35

8.75

105 °C 125 °C 25 °C

20.5

21.0

46.0

47.0

2.0

2.1

55 °C

5.6

5.8

85 °C 105 °C 125 °C

21.5

22.0

51.0

52.5

115

120

3 V 0.79

2.40

9.00

3.6 V 0.84

2.55

9.40

1.8 V 0.72

2.35

9.35

2.4 V 0.74

2.35

9.65

21.5

22.5

21.0

22.0

49.0

51.5

46.5

48.0

2.1

2.3

5.9

6.1

22.5

23.0

54.0

56.0

125

130

3 V 0.75

2.65

10.0

3.6 V 0.79

2.90

10.5

1.8 V 1.05

2.70

9.00

2.4 V 1.10

2.90

9.30

3 V 1.20

3.10

9.65

3.6 V 1.30

3.35

10.0

1.8 V 1.00

2.65

9.55

2.4 V 1.05

2.90

10.0

22.5

24.0

21.0

21.5

22.5

23.5

21.5

22.0

50.0

52.5

46.0

47.5

49.5

52.0

46.5

48.5

2.5

2.8

3.0

3.3

6.2

6.4

6.8

7.2

22.0

22.5

23.0

24.5

51.5

53.0

54.5

57.0

125

130

120

3 V 1.10

3.15

10.5

3.6 V 1.20

3.55

11.5

1.8 V 0.86

2.45

9.35

2.4 V 0.88

2.60

9.70

3 V 0.93

2.75

10.0

3.6 V 0.98

3.05

11.0

23.0

24.5

21.5

22.0

23.0

24.0

50.5

53.0

46.5

48.0

50.0

52.5

Unit

µA

DD_ALL

(Stop 2 with

RTC)

Table 43. Current consumption in Stop 2 mode (continued)

Conditions TYP MAX

(1)

Symbol

DD_ALL

(wakeup from

Stop2)

Parameter

Supply current in

Stop 2 mode,

RTC enabled

Supply current during wakeup from Stop 2 mode

RTC clocked by LSE quartz in low drive mode

RTC clocked by LSE quartz

(2)

in low drive mode, ENULP = 1,

LPCAL = 1

RTC clocked by LSE bypassed at 32768 Hz

RTC clocked by LSE bypassed at 32768 Hz,

ENULP = 1,

LPCAL = 1

25 °C 55 °C 85 °C

1.8 V 1.35

2.85

9.15

2.4 V 1.60

3.15

9.60

105 °C 125 °C 25 °C

21.0

22.0

46.0

48.0

55 °C

85 °C 105 °C 125 °C

3 V 2.00

3.85

11.0

3.6 V 3.90

6.60

15.0

1.8 V 1.20

2.80

9.70

2.4 V 1.35

3.10

10.5

24.0

29.5

21.5

22.5

51.5

58.5

46.5

48.5

3 V 1.80

3.90

11.5

3.6 V 3.65

6.75

16.0

1.8 V 1.20

2.65

8.85

2.4 V 1.25

2.75

9.10

3 V 1.35

2.90

9.45

3.6 V 1.50

3.10

9.95

1.8 V 1.00

2.55

9.50

2.4 V 1.10

2.75

9.90

3 V 1.15

3.00

10.5

3.6 V 1.25

3.25

11.0

25.0

30.5

20.5

21.0

22.0

23.0

21.0

22.0

23.0

25.0

52.5

59.5

47.5

49.0

51.0

53.0

48.0

49.5

52.0

54.5

Wakeup clock is

MSI = 48 MHz, voltage Range 1.

See

(3)

Wakeup clock is

MSI = 4 MHz, voltage Range 2.

See

(3)

Wakeup clock is

HSI16 = 16 MHz, voltage Range 1.

See

(3)

3 V

185

155

152 -

Unit

µA mA

1. Guaranteed by characterization results, unless otherwise specified.

2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.

Symbol

DD_ALL

(Stop 1)

DD_ALL

(wakeup from Stop1)

Parameter

Supply current in Stop 1 mode,

RTC disabled

DD_ALL

(Stop 1 with

RTC)

Supply current in stop 1 mode,

RTC enabled

Supply current during wakeup from

Stop 1

Table 44. Current consumption in Stop 1 mode

Conditions

RTC clocked by LSI

RTC clocked by LSE bypassed at 32768 Hz

RTC clocked by LSE quartz

(2) in low drive mode

TYP MAX

(1)

Unit

25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C

1.8 V 3.95

13.0

47.5

2.4 V 3.95

13.0

48.0

3 V 4.00

13.5

48.0

3.6 V 4.10

13.5

48.5

1.8 V 4.40

13.5

48.0

2.4 V 4.60

14.0

48.5

3 V 4.75

14.0

48.5

3.6 V 5.05

14.5

49.5

1.8 V 4.50

13.5

48.5

2.4 V 4.70

14.0

49.0

3 V 5.35

14.5

50.0

3.6 V 7.20

17.5

54.5

1.8 V 4.25

13.5

47.5

2.4 V 4.35

13.5

48.0

3 V 4.40

13.5

48.0

3.6 V 4.50

14.0

49.0

110

115

110

115

120

110

125

230 7.40

24.5

87.0

190

230 7.50

24.5

86.0

190

235

7.30

24.5

87.0

245 26.0

28.0

88.0

195

240 7.85

25.0

90.0

195

230 8.05

24.5

86.5

190

235 8.10

25.0

90.0

195

235 8.20

25.5

89.0

195

240 8.55

27.0

89.5

195

230 11.5

26.5

86.0

190

230 29.0

31.5

90.0

190

240 36.0

31.5

87.5

195

405

395

400

395 µA

395

400

405

395

400

µA

Wakeup clock MSI = 48 MHz, voltage Range 1.

See

(3)

Wakeup clock MSI = 4 MHz, voltage Range 2.

See

(3)

Wakeup clock

HSI16 = 16 MHz, voltage Range 1.

See

(3)

3 V

1.15

1.25

1.20

1. Guaranteed by characterization results, unless otherwise specified.

2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.

3. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 50: Low-power mode wakeup timings .

Symbol

DD_ALL

(Stop 0)

Parameter

Supply current in Stop 0 mode,

RTC disabled

Conditions

1.8 V

2.4 V

3 V

3.6 V

Table 45. Current consumption in Stop 0

25 °C

110

115

1. Guaranteed by characterization results, unless otherwise specified.

55 °C

125

130

TYP

85 °C

165

170

175

105 °C

240

245

250

125 °C

380

385

390

25 °C

130

135

55 °C

145

150

MAX

(1)

85 °C

215

220

105 °C

340

345

125 °C

585

590

595

Unit

µA

Symbol

DD_ALL

(Standby)

Parameter

Supply current in Standby mode (backup registers retained),

RTC disabled

Table 46. Current consumption in Standby mode

Conditions

With independent watchdog

ENULP = 1

TYP MAX

(1)

No independent watchdog

ENULP = 1

25 °C 55 °C 85 °C 105 °C 125 °C 25 °C

1.8 V 95

2.4 V 105

255

290

1150

1300

3200

3600

8350

9500

115

175

55 °C

405

540

85 °C 105 °C 125 °C

2750

3250

7150

8350

19500

23000

3 V 120

3.6 V 150

1.8 V 32

2.4 V 46

354

410

225

315

1550

1850

1400

1800

4350

5050

3850

4500

11500

13000

9000

10500

215

280

115

175

650

835

405

540

3750

4450

2750

3250

9600

8350

26000

11500 29500

7250 19500

23000

3 V 66 430 2400 5450 12500 215

3.6 V 115 570 3050 6350 14500 280

1.8 V 295

2.4 V 350

450

530

1300

1500

3250

3750

8250

9450

3 V 415

3.6 V 505

1.8 V 230

2.4 V 290

3 V 365

3.6 V 460

635

775

415

540

710

915

1800

2200

1450

1950

2550

3300

4450

5350

3900

4600

5500

6600

11500

13500

8850

10550

12500

14500

650

835

3750 9600 26000

4450 11500 29500

Unit nA

Symbol

DD_ALL

(Standby with RTC)

Parameter

Supply current in Standby mode (backup registers retained),

RTC enabled

Table 46. Current consumption in Standby mode (continued)

Conditions

RTC clocked by LSI, no independent watchdog

ENULP = 1

RTC clocked by LSI, with independent watchdog

ENULP = 1

TYP MAX

(1)

25 °C 55 °C 85 °C 105 °C 125 °C 25 °C

1.8 V 480

2.4 V 615

635

800

1500

1800

3450

4050

8400

9700

560

770

55 °C

900

1200

85 °C 105 °C 125 °C

3180

3850

7500

880

19500

23000

3 V 775 995 2150 4850 11500 975 1450 4450 10500 26000

3.6 V 970 1250 2650 5850 14000 1250 1850 5300 12000 29500

1.8 V 330

2.4 V 435

515

690

1600

2100

4000

4750

9000

10500

560

770

900

1200

3180

3850

7500

8800

19500

23000

3 V 565 915 2750 5750 12500 975 1450 4450 10500 26000

3.6 V 725 1200 3600 6900 1500 1250 1850 5300 12000 29500

1.8 V 530

2.4 V 675

680

855

1550

1850

3500

4100

8450

9850

3 V 850 1050 2250 4900 11500

3.6 V 1050 1350 2750 4900 11500

1.8 V 370

2.4 V 495

560

755

1600

2150

4050

4800

9050

10500

3 V 645 985 2850 5800 12500

3.6 V 825 1300 3700 6950 15000

Unit nA

Symbol

DD_ALL

(Standby with RTC)

(cont.)

DD_ALL

(SRAM2)

(3)

DD_ALL

(wakeup from

Standby)

Parameter

Supply current to be added in

Standby mode when SRAM2 is retained

Supply current during wakeup from Standby mode

Table 46. Current consumption in Standby mode (continued)

Conditions

RTC clocked by LSE bypassed at 32768 Hz

Supply current in Standby mode (backup registers retained),

RTC enabled

(cont.)

RTC clocked by LSE bypassed at 32768 Hz

ENULP = 1

RTC clocked by LSE quartz

(2)

in low drive mode

RTC clocked by LSE

quartz

4. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 50: Low-power mode wakeup timings .

in low drive mode

ENULP = 1

LPCAL = 1

Wakeup clock is

MSI = 4 MHz.

See

(4)

25 °C 55 °C 85 °C 105 °C 125 °C 25 °C

1.8 V 480

2.4 V 615

640

800

1500

1800

3450

4000

8100

9300

55 °C

85 °C 105 °C 125 °C

3 V 775 995 2150 4800 11000

3.6 V 960 1250 2650 5800 13000

1.8 V 330

2.4 V 435

510

695

1600

2100

4000

4750

8800

10000

3 V 565 910 2750 5700 12000

3.6 V 730 1200 3600 6900 14500

1.8 V 415

2.4 V 485

575

670

1450

1650

3400

3900

3 V 550

3.6 V 690

1.8 V 245

2.4 V 290

800

985

1950

2400

4600

450 1600 4000

565 2050 4650 -

3 V 355

3.6 V 450

1.8 V 100

2.4 V 100

3 V 100

3.6 V 100

705 2650 5500

915 3400 -

230

235

240

750

1600 3500

1650 3500

1700

3500

Unit nA nA

3 V 1.25

TYP

MAX

(1)

1. Guaranteed by characterization results, unless otherwise specified.

2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.

3. The supply current in Standby with SRAM2 mode is: I

+ RTC) + I

DD_ALL

(SRAM2).

DD_ALL

(Standby) + I

DD_ALL

(SRAM2). The supply current in Standby with RTC with SRAM2 mode is: I

DD_ALL

(Standby

Symbol

DD_ALL

(Shutdown)

Parameter

Supply current in Shutdown mode

(backup registers retained) RTC disabled

Table 47. Current consumption in Shutdown mode

Conditions

3 V

25 °C 55 °C 85 °C

1.8 V 16

2.4 V 22

100

120

155

600

705

870

105 °C 125 °C 25 °C

1850

2150

2650

5450

6250

7700

55 °C

310

365

600

85 °C 105 °C 125 °C

1200

1350

1700

3350

3800

4750

9550

11000

12500

Unit nA

3.6 V 52 220

TYP

1150 3350 9350 95 440

DD_ALL

(Shutdown with RTC)

Supply current in Shutdown mode

(backup registers retained) RTC enabled

RTC clocked by LSE bypassed at 32768 Hz

ENULP = 1

RTC clocked by LSE quartz mode

(2)

in low drive

RTC clocked by LSE quartz

3. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 50: Low-power mode wakeup timings .

in low drive

mode ENULP = 1

1.8 V 210 300 820 2050 5750

2.4 V 315 445 1100 2650 6950

3 V 625 1000 2200 44000 10000

3.6 V 820 1650 3500 5600 14500

1.8 V 210 300 820 2050 5750

2.4 V 315 445 1100 2650 6950

3 V 625 1000 2200 44000 10000

3.6 V 820 1650 3500 5600 14500

1.8 V 325 425 930 2200 -

2.4 V 400 515 1100 2550

3 V 475 630 1350 3100

3.6 V 595 795 1750

1.8 V 230 325 830

2050

2.4 V 270 380

3 V 320 455

975

1200

2400

1950

3.6 V 400 575 1500 -

DD_ALL

(wakeup from

Shutdown)

Supply current during wakeup from Shutdown mode

Wakeup clock is

MSI = 4 MHz.

See

(3)

3 V 0.78

1. Guaranteed by characterization results, unless otherwise specified.

2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.

MAX

(1)

1850 5050 14500

nA mA

Symbol

DD_VBAT

(VBAT)

Parameter

Backup domain supply current

Table 48. Current consumption in VBAT mode

Conditions TYP MAX

(1)

25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C

Unit

RTC disabled

RTC enabled and clocked by LSE quartz

(2)

BAT

1.8 V

2.4 V

3 V

3.6 V

1.8 V

2.4 V

3 V

3.6 V

6 30

300 455

380 515

445 550

495 630

161

460

575

595

820

195

215

265

540

600

730

460

990

1250

1750

1050 1950

1200 2550

1500 2950

1. Guaranteed by characterization results, unless otherwise specified.

2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.

Electrical characteristics STM32L412xx

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in

Table 69: I/O static characteristics

For the output pins, any external pull-down or external load must also be considered to estimate the current consumption.

Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs.

Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode.

I/O dynamic current consumption

In addition to the internal peripheral current consumption measured previously (see

Table 49: Peripheral current consumption ), the I/Os used by an application also contribute

to the current consumption. When an I/O pin switches, it uses the current from the I/O supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load

(internal or external) connected to the pin:

= V

DDIOx

×

C where

is the current sunk by a switching I/O to charge/discharge the capacitive load

DDIOx

is the I/O supply voltage f

is the I/O switching frequency

C is the total capacitance seen by the I/O pin: C = C

INT

+ C

EXT

+ C

is the PCB board capacitance including the pad pin.

The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency.

108/192 DS12469 Rev 8

STM32L412xx Electrical characteristics

AHB

APB1

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in

Table 49 . The MCU is placed

under the following conditions:

• All I/O pins are in Analog mode

• The given value is calculated by measuring the difference of the current consumptions:

– when the peripheral is clocked on

– when the peripheral is clocked off

•

Ambient operating temperature and supply voltage conditions summarized in Table 18:

Voltage characteristics

• The power consumption of the digital part of the on-chip peripherals is given in

Table 49 . The power consumption of the analog part of the peripherals (where

applicable) is indicated in each related section of the datasheet.

Table 49. Peripheral current consumption

Range 1 Range 2 Peripheral

Bus Matrix

(1)

ADC clock domain

CRC

DMA1

DMA2

FLASH

GPIOA

(2)

GPIOB

(2)

)

GPIOC (2)

GPIOH

(2)

QSPI

RNG independent clock domain

RNG clock domain

SRAM1

SRAM2

TSC

All AHB Peripherals

AHB to APB1 bridge

(3)

RTCA

CRS

USB FS independent clock domain

USB FS clock domain

1.5

1.7

0.6

6.9

2.2

0.5

3.0

2.2

0.5

1.3

5.9

1.6

0.7

0.9

1.5

21.9

0.8

1.7

0.3

2.8

2.2

1.4

1.6

0.5

7.0

2.9

1.8

0.3

1.2

4.9

1.5

0.6

0.7

1.3

19.2

0.6

1.1

0.3

Low-power run and sleep

5.6

1.3

1.5

0.6

2.8

1.8

0.2

1.1

5.6

1.3

0.7

0.8

1.3

20.5

0.8

2.1

0.5

Unit

µA/MHz

DS12469 Rev 8 109/192

164

Electrical characteristics

APB1

STM32L412xx

Table 49. Peripheral current consumption (continued)

Peripheral Range 1 Range 2

Low-power run and sleep

I2C1 independent clock domain

I2C1 clock domain

I2C2 independent clock domain

I2C2 clock domain

I2C3 independent clock domain

I2C3 clock domain

LPUART1 independent clock domain

LPUART1 clock domain

LPTIM1 independent clock domain

LPTIM1 clock domain

LPTIM2 independent clock domain

LPTIM2 clock domain

OPAMP

PWR

SPI2

SPI3

TIM2

TIM6

USART2 independent clock domain

USART2 clock domain

USART3 independent clock domain

USART3 clock domain

WWDG

All APB1 on

1.0

2.8

0.9

3.4

1.0

3.4

1.8

0.6

2.8

0.8

2.9

0.8

0.4

1.7

6.2

1.0

4.0

1.3

4.2

1.5

0.5

41.4

1.6

0.6

2.3

0.4

2.6

0.7

0.2

0.1

1.5

1.4

5.0

0.6

0.9

2.3

0.4

2.8

0.9

2.8

3.5

0.8

3.4

1.1

0.5

28.5

0.8

0.4

1.5

5.8

0.9

2.4

0.7

3.3

0.9

3.3

1.7

2.7

0.7

3.8

3.7

1.1

4.1

1.3

0.5

38.9

Unit

µA/MHz

110/192 DS12469 Rev 8

STM32L412xx Electrical characteristics

APB2

Table 49. Peripheral current consumption (continued)

Peripheral Range 1 Range 2

Low-power run and sleep

AHB to APB2 (4)

SPI1

SYSCFG/COMP

TIM1

TIM15

TIM16

USART1 independent clock domain

USART1 clock domain

All APB2 on

ALL

0.6

8.1

3.7

2.6

1.0

0.2

1.7

4.1

1.5

19.2

82.5

0.5

6.4

3.0

2.1

0.9

0.2

1.6

4.1

1.2

16.1

63.8

0.6

7.6

3.4

2.5

0.9

0.2

1.7

4.4

1.6

17.8

77.2

Unit

µA/MHz

1. The BusMatrix is automatically active when at least one master is ON (CPU, DMA).

2. The GPIOx (x= A…H) dynamic current consumption is approximately divided by a factor two versus this table values when the GPIO port is locked thanks to LCKK and LCKy bits in the GPIOx_LCKR register. In order to save the full GPIOx current consumption, the GPIOx clock should be disabled in the RCC when all port I/Os are used in alternate function or analog mode (clock is only required to read or write into GPIO registers, and is not used in AF or analog modes).

3. The AHB to APB1 Bridge is automatically active when at least one peripheral is ON on the APB1.

4. The AHB to APB2 Bridge is automatically active when at least one peripheral is ON on the APB2.

The consumption for the peripherals when using SMPS can be found using STM32CubeMX

PCC tool.

6.3.6

Symbol

Wakeup time from low-power modes and voltage scaling transition times

The wakeup times given in

Table 50 are the latency between the event and the execution of

the first user instruction.

The device goes in low-power mode after the WFE (Wait For Event) instruction.

Table 50. Low-power mode wakeup timings (1)

Parameter Conditions Typ Max Unit t

WUSLEEP

Wakeup time from Sleep mode to Run mode

WULPSLEEP

Wakeup time from Lowpower sleep mode to Lowpower run mode

Wakeup in Flash with Flash in power-down during low-power sleep mode (SLEEP_PD=1 in

FLASH_ACR) and with clock MSI = 2 MHz

8.3

Nb of

CPU cycles

DS12469 Rev 8 111/192

164

Electrical characteristics STM32L412xx

Symbol t

WUSTOP0 t

WUSTOP1

Table 50. Low-power mode wakeup timings (1) (continued)

Parameter

Range 1

Wake up time from Stop 0 mode to Run mode in

Flash

Range 2

Range 1

Wake up time from Stop 0 mode to Run mode in

SRAM1

Range 2

Wake up time from Stop 1 mode to Run in Flash

Range 1

Range 2

Range 1

Wake up time from Stop 1 mode to Run mode in

SRAM1

Range 2

Conditions Typ Max Unit

Wakeup clock MSI = 48 MHz 3.8

5.7

Wakeup clock HSI16 = 16 MHz 4.1

6.9

Wakeup clock MSI = 24 MHz 4.07

6.2

Wakeup clock HSI16 = 16 MHz 4.1

6.8

Wakeup clock MSI = 4 MHz

Wakeup clock MSI = 48 MHz

8.45

11.8

1.5

2.9

Wakeup clock HSI16 = 16 MHz 2.4

2.76

Wakeup clock MSI = 24 MHz 2.4

3.48

Wakeup clock HSI16 = 16 MHz 2.4

2.76

Wakeup clock MSI = 4 MHz 8.16 10.94

Wakeup clock MSI = 48 MHz 6.34

7.86

Wakeup clock HSI16 = 16 MHz 6.84

8.23

Wakeup clock MSI = 24 MHz 6.74

8.1

Wakeup clock HSI16 = 16 MHz 6.89

8.21

Wakeup clock MSI = 4 MHz 10.47 12.1

Wakeup clock MSI = 48 MHz 4.7

5.97

Wakeup clock HSI16 = 16 MHz 5.9

6.92

Wakeup clock MSI = 24 MHz 5.4

6.51

Wakeup clock HSI16 = 16 MHz 5.9

6.92

Wakeup clock MSI = 4 MHz 11.1

12.2

µs

Wake up time from Stop 1 mode to Low-power run mode in Flash

Wake up time from Stop 1 mode to Low-power run mode in SRAM1

Regulator in low-power mode (LPR=1 in PWR_CR1)

Wakeup clock MSI = 2 MHz

16.4 17.73

17.3 18.82

112/192 DS12469 Rev 8

STM32L412xx Electrical characteristics

Symbol t

WUSTOP2 t

WUSTBY

Table 50. Low-power mode wakeup timings (1) (continued)

Parameter

Range 1

Wake up time from Stop 2 mode to Run mode in

Flash

Range 2

Range 1

Wake up time from Stop 2 mode to Run mode in

SRAM1

Range 2

Wakeup time from Standby mode to Run mode

Range 1 t

WUSTBY

SRAM2

Wakeup time from Standby with SRAM2 to Run mode t

WUSHDN

Wakeup time from

Shutdown mode to Run mode

1. Guaranteed by characterization results.

Range 1

Conditions

Wakeup clock MSI = 48 MHz 8.02

9.24

Wakeup clock HSI16 = 16 MHz 7.66

8.95

Wakeup clock MSI = 24 MHz 8.5

9.54

Wakeup clock HSI16 = 16 MHz 7.75

8.95

Wakeup clock MSI = 4 MHz

Wakeup clock MSI = 48 MHz

12.06 13.16

5.45

6.79

Wakeup clock HSI16 = 16 MHz 6.9

7.98

Wakeup clock MSI = 24 MHz 6.3

7.36

Wakeup clock HSI16 = 16 MHz 6.9

7.9

Wakeup clock MSI = 4 MHz 13.1 13.31

Wakeup clock MSI = 8 MHz

Wakeup clock MSI = 4 MHz

12.2 18.35

19.14 25.8

Wakeup clock MSI = 8 MHz

Wakeup clock MSI = 4 MHz

12.1

18.3

19.2 25.87

Wakeup clock MSI = 4 MHz

Typ Max Unit

µs

261.5 315.7

µs

Symbol

Table 51. Regulator modes transition times (1)

Parameter Conditions t

WULPRUN t

VOST

Wakeup time from Low-power run mode to

Run mode

(2)

Code run with MSI 2 MHz

Regulator transition time from Range 2 to

Range 1 or Range 1 to Range 2 (3)

Code run with MSI 24 MHz

1. Guaranteed by characterization results.

2. Time until REGLPF flag is cleared in PWR_SR2.

3. Time until VOSF flag is cleared in PWR_SR2.

Typ

Max

Unit

µs

Symbol

Table 52. Wakeup time using USART/LPUART

(1)

Parameter Conditions

Stop 0 mode t

WUUSART t

WULPUART

Wakeup time needed to calculate the maximum USART/LPUART baudrate allowing to wakeup up from stop mode

when USART/LPUART clock source is

HSI

1. Guaranteed by design.

Stop 1 mode and Stop 2 mode

Typ

Max

1.7

8.5

Unit

µs

DS12469 Rev 8 113/192

164

Electrical characteristics STM32L412xx

High-speed external user clock generated from an external source

In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in Section 6.3.14

. However,

Symbol f

HSE_ext

User external clock source frequency

HSEH

HSEL

Table 53. High-speed external user clock characteristics (1)

Parameter Conditions Min Typ

OSC_IN input pin high level voltage

OSC_IN input pin low level voltage t w(HSEH) t w(HSEL)

OSC_IN high or low time

Voltage scaling

Range 1

Voltage scaling

Range 2

Voltage scaling

Range 1

Voltage scaling

Range 2

0.7 V

DDIOx

1. Guaranteed by design.

Max

DDIOx

0.3 V

DDIOx

Unit

MHz

V ns

Figure 21. High-speed external clock source AC timing diagram tw(HSEH)

VHSEH

VHSEL

90%

10% tr(HSE)

THSE tf(HSE) tw(HSEL) t

MS19214V2

114/192 DS12469 Rev 8

STM32L412xx Electrical characteristics

Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in Section 6.3.14

. However,

Symbol

Table 54. Low-speed external user clock characteristics (1)

Parameter f

LSE_ext

LSEH

LSEL t w(LSEH) t w(LSEL)

User external clock source frequency

OSC32_IN input pin high level voltage

OSC32_IN input pin low level voltage

OSC32_IN high or low time

1. Guaranteed by design.

Conditions

Min

0.7 V

DDIOx

250

Typ

32.768

Max

1000

DDIOx

0.3 V

DDIOx

Unit kHz

V ns

Figure 22. Low-speed external clock source AC timing diagram tw(LSEH)

VLSEH

VLSEL

90%

10% tr(LSE)

TLSE tf(LSE) tw(LSEL) t

MS19215V2

DS12469 Rev 8 115/192

164

Electrical characteristics STM32L412xx

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in

Table 55 . In the

application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics

(frequency, package, accuracy).

Symbol

Table 55. HSE oscillator characteristics (1)

Parameter Conditions

(2)

Min Typ Max Unit

I f

OSC_IN

DD(HSE)

Oscillator frequency

Feedback resistor

HSE current consumption

During startup

(3)

= 3 V,

Rm = 30 Ω ,

CL = 10 pF@8 MHz

= 3 V,

Rm = 45 Ω ,

CL = 10 pF@8 MHz

= 3 V,

Rm = 30 Ω ,

CL = 5 pF@48 MHz

= 3 V,

Rm = 30 Ω ,

CL = 10 pF@48 MHz

200

0.44

0.45

0.68

0.94

5.5

MHz k Ω mA

= 3 V,

Rm = 30 Ω ,

CL = 20 pF@48 MHz

1.77

G m

Maximum critical crystal transconductance

Startup 1.5

mA/V t

SU(HSE)

(4)

Startup time V

is stabilized 2 ms

1. Guaranteed by design.

2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

3. This consumption level occurs during the first 2/3 of the t

SU(HSE) startup time

4. t

SU(HSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer

For C

and C

, it is recommended to use high-quality external ceramic capacitors in the

5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match

the requirements of the crystal or resonator (see Figure 23

). C

and C

L2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C

and C

. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing

and C

116/192 DS12469 Rev 8

STM32L412xx

Note:

Electrical characteristics

For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com

Figure 23. Typical application with an 8 MHz crystal

Resonator with integrated capacitors

OSC_IN f

HSE

8 MHz resonator

EXT

(1) OSC_OUT

Bias controlled gain

MS19876V1

1. R

EXT

value depends on the crystal characteristics.

Low-speed external clock generated from a crystal resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in

Table 56 . In the application, the

resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Symbol

Table 56. LSE oscillator characteristics (f

LSE

= 32.768 kHz)

(1)

Parameter Conditions

(2)

DD(LSE)

Gm critmax t

SU(LSE)

(3)

LSE current consumption

Maximum critical crystal gm

Startup time

LSEDRV[1:0] = 00

Low drive capability

LSEDRV[1:0] = 01

Medium low drive capability

LSEDRV[1:0] = 10

Medium high drive capability

LSEDRV[1:0] = 11

High drive capability

LSEDRV[1:0] = 00

Low drive capability

LSEDRV[1:0] = 01

Medium low drive capability

LSEDRV[1:0] = 10

Medium high drive capability

LSEDRV[1:0] = 11

High drive capability

is stabilized

Min Typ Max Unit

250

315

500

630

0.5

0.75

1.7

2.7

µA/V s

DS12469 Rev 8 117/192

164

Electrical characteristics STM32L412xx

1. Guaranteed by design.

2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for

ST microcontrollers”.

3. t

SU(LSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer

Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com

Figure 24. Typical application with a 32.768 kHz crystal

Resonator with integrated capacitors

OSC32_IN f

LSE

32.768 kHz resonator

Drive programmable amplifier

OSC32_OUT

Note:

MS30253V2

An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one.

118/192 DS12469 Rev 8

STM32L412xx Electrical characteristics

6.3.8 Internal clock source characteristics

The parameters given in

Table 57 are derived from tests performed under ambient

temperature and supply voltage conditions summarized in Table 21: General operating conditions

. The provided curves are characterization results, not tested in production.

High-speed internal (HSI16) RC oscillator

Symbol

Table 57. HSI16 oscillator characteristics (1)

Parameter Conditions

DuCy(HSI16)

(2)

∆

∆ t

Temp

VDD su t stab

DD f

HSI16

TRIM

(HSI16)

HSI16 Frequency

HSI16 user trimming step

=3.0 V, T

=30 °C

Trimming code is not a multiple of 64

Trimming code is a multiple of 64

Duty Cycle

HSI16 oscillator frequency drift over temperature

= 0 to 85 °C

= -40 to 125 °C

HSI16 oscillator frequency drift over V

HSI16 oscillator start-up time

=1.62 V to 3.6 V

HSI16 oscillator stabilization time

HSI16 oscillator power consumption

1. Guaranteed by characterization results.

2. Guaranteed by design.

Min

15.88

0.2

-4

-1

-2

-0.1

Typ

0.3

-6

0.8

155

Max Unit

16.08

MHz

0.4

-8

1.5

0.05

1.2

190

μ s

μ A

DS12469 Rev 8 119/192

164

Electrical characteristics STM32L412xx

MHz

16.4

16.3

16.2

16.1

15.9

15.8

15.7

15.6

-40 -20

Figure 25. HSI16 frequency versus temperature

+2%

+1.5%

+1%

0 min

-1%

-1.5%

-2%

40 mean

60 80 max

100 120 °C

MSv39299V1

120/192 DS12469 Rev 8

STM32L412xx Electrical characteristics

Symbol f

MSI

Multi-speed internal (MSI) RC oscillator

∆

TEMP

(MSI) (2)

Parameter

Table 58. MSI oscillator characteristics

(1)

Conditions

MSI frequency after factory calibration, done at V

=3 V and

=30 °C

MSI oscillator frequency drift over temperature

MSI mode

PLL mode

XTAL=

32.768 kHz

MSI mode

Range 0

Range 1

Range 2

Range 3

Range 4

Range 5

Range 6

Range 7

Range 8

Range 9

Range 10

Range 11

Range 0

Range 1

Range 2

Range 3

Range 4

Range 5

Range 6

Range 7

Range 8

Range 9

Range 10

Range 11

= -0 to 85 °C

= -40 to 125 °C

Min

98.7

197.4

394.8

789.6

0.987

1.974

3.948

7.896

15.79

23.69

31.58

47.38

-3.5

-8

Max Unit

24.31

32.42

48.62

101.3

202.6

405.2

810.4

kHz

1.013

2.026

4.052

8.104

MHz

16.21

kHz

MHz

Typ

98.304

196.608

393.216

786.432

1.016

1.999

100

200

400

800

3.998

7.995

15.991

23.986

32.014

48.005

DS12469 Rev 8 121/192

164

Electrical characteristics

Symbol

VDD

(MSI)

P_USB

(2)

MT_USB

CC jitter(MSI)

(6)

P jitter(MSI) t

∆

∆ t

(MSI)

Jitter(MSI)

(MSI)

STAB

(MSI)

Table 58. MSI oscillator characteristics (1) (continued)

Parameter Conditions Min

MSI oscillator frequency drift over V

(reference is 3 V)

MSI mode

Range 0 to 3

Range 4 to 7

=1.62 V to 3.6 V

=2.4 V to 3.6 V

=1.62 V to 3.6 V

=2.4 V to 3.6 V

Range 8 to 11

=1.62 V to 3.6 V

=2.4 V to 3.6 V

= -40 to 85 °C Frequency variation in sampling mode

(3)

MSI mode

= -40 to 125 °C

Period jitter for

USB clock

(4)

Medium term jitter for USB clock

MSI oscillator

(5) stabilization time

PLL mode

Range 11

PLL mode

Range 11

PLL mode

Range 11

RMS cycle-tocycle jitter

PLL mode Range 11

RMS Period jitter PLL mode Range 11

MSI oscillator start-up time

Range 0

Range 1

Range 2

Range 3

Range 4 to 7

Range 8 to 11 for next transition for paired transition for next transition for paired transition

10 % of final frequency

5 % of final frequency

1 % of final frequency

-1.2

-0.5

-2.5

-0.8

-5

-1.6

STM32L412xx

Typ

2.5

0.25

0.5

Max Unit

0.5

0.7

3.458

3.916

1 ns

0.5

ps ps us

1.25

2.5

122/192 DS12469 Rev 8

STM32L412xx Electrical characteristics

Symbol

Table 58. MSI oscillator characteristics (1) (continued)

Parameter Conditions Min Typ Max Unit

(MSI)

MSI oscillator power consumption

MSI and

PLL mode

Range 0

Range 1

Range 2

Range 3

Range 4

Range 5

Range 6

Range 7

Range 8

Range 9

Range 10

Range 11

0.6

0.8

1.2

1.9

4.7

6.5

18.5

110

155

µA

1. Guaranteed by characterization results.

2. This is a deviation for an individual part once the initial frequency has been measured.

3. Sampling mode means Low-power run/Low-power sleep modes with Temperature sensor disable.

4. Average period of MSI @48 MHz is compared to a real 48 MHz clock over 28 cycles. It includes frequency tolerance + jitter of MSI @48 MHz clock.

5. Only accumulated jitter of MSI @48 MHz is extracted over 28 cycles.

For next transition: min. and max. jitter of 2 consecutive frame of 28 cycles of the MSI @48 MHz, for 1000 captures over 28 cycles.

For paired transitions: min. and max. jitter of 2 consecutive frame of 56 cycles of the MSI @48 MHz, for 1000 captures over

56 cycles.

6. Guaranteed by design.

2.5

1.2

1.7

110

130

190

DS12469 Rev 8 123/192

164

Electrical characteristics STM32L412xx

Figure 26. Typical current consumption versus MSI frequency

High-speed internal 48 MHz (HSI48) RC oscillator

Symbol

Table 59. HSI48 oscillator characteristics

(1)

Parameter Conditions f

HSI48

TRIM

HSI48 Frequency

HSI48 user trimming step

USER TRIM

COVERAGE

HSI48 user trimming coverage

DuCy(HSI48) Duty Cycle

ACC

HSI48_REL

Accuracy of the HSI48 oscillator over temperature (factory calibrated)

VDD

(HSI48)

HSI48 oscillator frequency drift with V

I t su

(HSI48) HSI48 oscillator start-up time

(HSI48)

HSI48 oscillator power consumption

=3.0V, T

±32 steps

=30°C

= 3.0 V to 3.6 V,

= –15 to 85 °C

= 1.65 V to 3.6 V,

= –40 to 125 °C

= 3 V to 3.6 V

= 1.65 V to 3.6 V

Min

±3

(3)

Typ

0.11

(2)

±3.5

(3)

0.025

(3)

0.05

(3)

2.5

340

±4.5

(3)

0.05

(3)

0.1

(3)

380

Max Unit

0.18

MHz

±3

(3)

μ s

124/192 DS12469 Rev 8

STM32L412xx Electrical characteristics

Symbol

Table 59. HSI48 oscillator characteristics (1) (continued)

Parameter Conditions Min

jitter

Next transition jitter

Accumulated jitter on 28 cycles (4)

Paired transition jitter

Accumulated jitter on 56 cycles

(4)

1. V

= 3 V, T

= –40 to 125°C unless otherwise specified.

2. Guaranteed by design.

3. Guaranteed by characterization results.

4. Jitter measurement are performed without clock source activated in parallel.

Typ

+/-0.15

+/-0.25

Table 61 are derived from tests performed under temperature and

Max Unit

Figure 27. HSI48 frequency versus temperature

-2

-4

-6

-50 -30 -10

Avg

10 30 min

50 70 90 max

110 130

°C

MSv40989V1

Low-speed internal (LSI) RC oscillator

Symbol Parameter

Table 60. LSI oscillator characteristics (1)

Conditions Min f

LSI

LSI Frequency

= 3.0 V, T

= 30 °C

= 1.62 to 3.6 V, T

= -40 to 125 °C t t

STAB

(LSI)

(2)

LSI oscillator startup time

LSI oscillator stabilization time

LSI oscillator power consumption

1. Guaranteed by characterization results.

2. Guaranteed by design.

5% of final frequency

31.04

29.5

Typ

125

110

Max Unit

32.96

34 kHz

130 μ s

180 μ s

180 nA

DS12469 Rev 8 125/192

164

Electrical characteristics STM32L412xx

The parameters given in

supply voltage conditions summarized in

Table 21: General operating conditions .

Symbol f

PLL_IN

Parameter

PLL input clock

(2)

PLL input clock duty cycle

Table 61. PLL characteristics

(1)

Conditions

Voltage scaling Range 1 f

PLL_P_OUT

PLL multiplier output clock P f

PLL_Q_OUT

PLL multiplier output clock Q

Voltage scaling Range 2

Voltage scaling Range 1

Voltage scaling Range 2

Voltage scaling Range 1 f

PLL_R_OUT

PLL multiplier output clock R f

VCO_OUT t

LOCK

PLL VCO output

PLL lock time

RMS cycle-to-cycle jitter

Voltage scaling Range 2

Voltage scaling Range 1

Voltage scaling Range 2

Jitter

(PLL)

RMS period jitter

PLL power consumption on

The test results are given in Table 64

System clock 80 MHz

VCO freq = 96 MHz

VCO freq = 192 MHz

VCO freq = 344 MHz

Min

3.0968

Typ Max Unit

40 -

30 -

200 260

300 380

520 650

16 MHz

MHz

344

MHz

128

40 μ s

±ps

μ A

1. Guaranteed by design.

2. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared between the 2 PLLs.

126/192 DS12469 Rev 8

STM32L412xx Electrical characteristics t t

Symbol t prog prog_row prog_page

Table 62. Flash memory characteristics (1)

Parameter

64-bit programming time one row (32 double word) programming time one page (2 Kbyte) programming time t

ERASE

Page (2 KB) erase time t prog_bank t

ME one bank (512 Kbyte) programming time

Mass erase time

(one or two banks)

Conditions

normal programming fast programming normal programming fast programming

normal programming fast programming

Average consumption from V

Maximum current (peak)

Write mode

Erase mode

Write mode

Erase mode

Typ

22.13

3.4

7 (for 2 μ s)

7 (for 41 μ s)

81.69

2.61

1.91

20.91

15.29

22.02

5.35

3.91

1. Guaranteed by design.

Symbol

Table 63. Flash memory endurance and data retention

Parameter Conditions

N t

END

RET

Endurance

Data retention

= –40 to +105 °C

1 kcycle

(2)

at T

= 85 °C

1 kcycle (2) at T

= 105 °C

1 kcycle

(2)

at T

= 125 °C

10 kcycles

(2)

at T

= 55 °C

10 kcycles

(2)

at T

= 85 °C

10 kcycles (2) at T

= 105 °C

1. Guaranteed by characterization results.

2. Cycling performed over the whole temperature range.

Min

(1)

Unit kcycles

Years

Max Unit

90.76

µs

2.90

2.12

23.24

16.98

24.47

5.95

4.35

24.59

DS12469 Rev 8 127/192

164

Electrical characteristics STM32L412xx

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

• FTB : A Burst of Fast Transient voltage (positive and negative) is applied to V

through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard.

and

A device reset allows normal operations to be resumed.

. They are based on the EMS levels and classes defined in application note AN1709.

Symbol

Table 64. EMS characteristics

Parameter Conditions

Level/

Class

FESD

EFTB

Voltage limits to be applied on any I/O pin to induce a functional disturbance

Fast transient voltage burst limits to be applied through 100 pF on V

and V pins to induce a functional disturbance

SS f

= 3.3 V, T

HCLK

= +25 °C,

= 80 MHz, conforming to IEC 61000-4-2 f

= 3.3 V, T

HCLK

= +25 °C,

= 80 MHz, conforming to IEC 61000-4-4

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

• Corrupted program counter

• Unexpected reset

• Critical Data corruption (control registers...)

128/192 DS12469 Rev 8

STM32L412xx Electrical characteristics

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with

IEC 61967-2 standard which specifies the test board and the pin loading.

Table 65. EMI characteristics

Symbol Parameter

EMI

Conditions

Monitored frequency band

Peak level

0.1 MHz to 30 MHz

= 3.6 V, T

= 25 °C,

LQFP64 package compliant with IEC

61967-2

30 MHz to 130 MHz

130 MHz to 1 GHz

1 GHz to 2 GHz

EMI Level

Max vs.

HSE

HCLK

]

8 MHz/ 80 MHz

2.5

Unit dBµV

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the ANSI/JEDEC standard.

Symbol Ratings

Table 66. ESD absolute maximum ratings

Conditions Package Class

Maximum value (1)

Unit

ESD(HBM)

ESD

Electrostatic discharge voltage

(human body model)

= +25 °C, conforming to ANSI/ESDA/JEDEC

JS-001

Electrostatic discharge voltage

(charge device model)

= +25 °C, conforming to

ANSI/ESDA/JEDEC-002

1. Guaranteed by characterization results.

All

BGA64

All others

C2a

2000

500

250

DS12469 Rev 8 129/192

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Electrical characteristics STM32L412xx

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up performance:

• A supply overvoltage is applied to each power supply pin.

• A current injection is applied to each input, output and configurable I/O pin.

These tests are compliant with EIA/JESD 78A IC latch-up standard.

Symbol

Parameter

Table 67. Electrical sensitivities

Conditions

Static latch-up class T

= +105 °C conforming to JESD78A

Class

As a general rule, current injection to the I/O pins, due to external voltage below V

SS above V

DDIOx product operation. However, in order to give an indication of the robustness of the

(for standard, 3.3 V-capable I/O pins) should be avoided during normal microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of the -5 µA/+0 µA range) or other functional failure (for example reset occurrence or oscillator frequency deviation).

The characterization results are given in

Table 68 .

Negative induced leakage current is caused by negative injection and positive induced leakage current is caused by positive injection.

Symbol

INJ

Table 68. I/O current injection susceptibility (1)

Functional susceptibility

Description

Negative injection

Positive injection

Injected current on all pins except PA4, PA5

Injected current on PA4, PA5 pins

-5

N/A

(2)

1. Guaranteed by characterization results.

2. Injection is not possible.

Unit mA

130/192 DS12469 Rev 8

STM32L412xx Electrical characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in

Table 69 are derived from tests

performed under the conditions summarized in Table 21: General operating conditions

. All

I/Os are designed as CMOS- and TTL-compliant.

Symbol

(1)

V hys

(3)

I lkg

(4)

Parameter

Table 69. I/O static characteristics

Conditions Min

I/O input low level voltage

I/O input high level voltage

1.62 V<V

1.08 V<V

1.62 V<V

DDIOx

<3.6 V

<1.62 V

<3.6 V 0.7xV

DDIOx

I/O input high level voltage

1.62 V<V

DDIOx

<3.6 V 0.49xV

DDIOX

+0.26

(3)

I/O input high level voltage

TT_xx, FT_xxx and

NRST I/O input hysteresis

1.08 V<V

1.62 V<V

FT_xx input leakage current

(3)(5)

FT_u and PC3 I/O

TT_xx input leakage current

≤

Max(V

DDXXX

)

(6)(7)

Max(V

DDXXX

Max(V

DDXXX

) ≤ V

)+1 V

≤

Max(V

≤ 5.5 V

)+1 V <

≤

Max(V

DDXXX

)

(6)(7)

Max(V

DDXXX

Max(V

DDXXX

) ≤ V

)+1 V

≤

Max(V

≤ 5.5 V

)+1 V <

≤ Max(V

DDXXX

)

1. Refer to Figure 28: I/O input characteristics .

Max(V

3.6 V

) ≤ V

Weak pull-up equivalent resistor

(8)

= V

DDIOx

<1.62 V 0.61xV

DDIOX

<3.6 V

+0.05

(3)

Weak pull-down equivalent resistor (8)

I/O pin capacitance

= V

DDIOx

Typ

200

0.3xV

0.39xV

0.43xV

Max

DDIOx

(2)

DDIOx

±100

650

200

±150

2500

250

(3)

±150

2000

-0.06

(3)

-0.1

(3)

Unit

V mV nA k Ω k Ω pF

DS12469 Rev 8 131/192

164

Electrical characteristics STM32L412xx

2. Tested in production.

3. Guaranteed by design.

4. This value represents the pad leakage of the IO itself. The total product pad leakage is provided by this formula:

Total_Ileak_max

= 10 µA + [number of IOs where V

is applied on the pad] ₓ I lkg

(Max).

5. All FT_xx GPIOs except FT_u and PC3 I/O.

6. Max(V

DDXXX

) is the maximum value of all the I/O supplies. Refer to Table: Legend/Abbreviations used in the pinout table.

7. To sustain a voltage higher than Min(V disabled.

, V

DDA

, V

DDUSB

) +0.3 V, the internal Pull-up and Pull-Down resistors must be

8. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

PMOS/NMOS contribution to the series resistance is minimal (~10% order).

All I/Os are CMOS- and TTL-compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The

coverage of these requirements is shown in Figure 28

for standard I/Os, and in

Figure 28

for

5 V tolerant I/Os.

Figure 28. I/O input characteristics

TTL requirement Vih min = 2V

min = 0

.7xV

DDIO x

DDIOx

+0.2

6 for V

DDIOx

>1.6

DDIOx

<1.62 or

0.49xV

Teste d in production CMOS requirement Vih on Vi h min = 0.

lation V il max

61xV

DDIOx

=0.43xV

DDIOx

+0.05

for 1.08<V

-0.1 for 1.08

<V DDIOx

<1.62 or 0.39xV

ax = 0.3xVdd

DDIOx

-0.06 for

DDIO x

>1.62

TTL requirement Vil max = 0.8V

Based on simu ction CMOS req uirement Vil m

Tested in produ

MSv37613V1

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source up to ± 20 mA (with a relaxed V

132/192 DS12469 Rev 8

STM32L412xx Electrical characteristics

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in

Section 6.2

• The sum of the currents sourced by all the I/Os on V

DDIOx, consumption of the MCU sourced on V

DD,

Σ I

VDD

(see Table 18: Voltage characteristics ).

plus the maximum cannot exceed the absolute maximum rating

• The sum of the currents sunk by all the I/Os on V

, plus the maximum consumption of the MCU sunk on V

, cannot exceed the absolute maximum rating

Table 18: Voltage characteristics

Σ I

VSS

(see

Output voltage levels

Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in

Table 21: General operating conditions . All I/Os are CMOS- and TTL-compliant (FT OR TT

unless otherwise specified).

Symbol

Table 70. Output voltage characteristics (1)

Parameter Conditions Min Max Unit

(3)

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

CMOS port

DDIOx

(2)

= 8 mA

≥ 2.7 V

Output low level voltage for an I/O pin TTL port

Output high level voltage for an I/O pin

DDIOx

(2)

= 8 mA

≥ 2.7 V

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

DDIOx

= 20 mA

≥ 2.7 V

= 4 mA

≥ 1.62 V

= 2 mA

1.62 V ≥ V

DDIOx

≥ 1.08 V

DDIOx

2.4

DDIOx

-0.4

-1.3

-0.45

0.65

ₓ V

DDIOx

0.35

0.4

0.45

ₓ

1.3

DDIOx

Output low level voltage for an FT I/O pin in FM+ mode (FT I/O with "f" option)

| = 20 mA

DDIOx

≥ 2.7 V

| = 10 mA

DDIOx

≥ 1.62 V

| = 2 mA

1.62 V ≥ V

DDIOx

≥ 1.08 V

0.4

1. The I

current sourced or sunk by the device must always respect the absolute maximum rating specified in

Table 18:

Voltage characteristics

, and the sum of respect the absolute maximum ratings the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always

Σ I

2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

3. Guaranteed by design.

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in

Figure 29

and

Table 71 , respectively.

DS12469 Rev 8 133/192

164

Electrical characteristics STM32L412xx

Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in

Table 21: General operating conditions

Speed Symbol

Table 71. I/O AC characteristics (1)(2)

Parameter Conditions

Fmax Maximum frequency

Tr/Tf Output rise and fall time

Fmax Maximum frequency

Tr/Tf Output rise and fall time

C=50 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=50 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=50 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

C=10 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=10 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=10 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

C=50 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=50 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=50 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

C=10 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=10 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=10 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

C=50 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=50 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=50 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

C=10 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=10 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=10 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

C=50 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=50 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=50 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

C=10 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=10 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=10 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

Unit

MHz ns

Min

Max

1.5

0.1

140

0.1

110

4.5

134/192 DS12469 Rev 8

STM32L412xx Electrical characteristics

Speed Symbol

Table 71. I/O AC characteristics (1)(2) (continued)

Parameter Conditions Min Max Unit

Fmax

Tr/Tf

Fmax

Tr/Tf

Maximum frequency

Output rise and fall time

Maximum frequency

Output rise and fall time

C=50 pF, 2.7 V ≤ V

C=10 pF, 2.7 V ≤ V

C=50 pF, 2.7 V ≤ V

C=10 pF, 2.7 V ≤ V

C=30 pF, 2.7 V ≤ V

C=10 pF, 2.7 V ≤ V

C=30 pF, 2.7 V ≤ V

C=30 pF, 1.08 V ≤

DDIOx

C=50 pF, 1.62 V ≤ V

C=50 pF, 1.08 V ≤ V

DDIOx

C=10 pF, 1.62 V ≤ V

C=10 pF, 1.08 V ≤ V

DDIOx

C=50 pF, 1.62 V ≤ V

C=50 pF, 1.08 V ≤ V

DDIOx

C=10 pF, 1.62 V ≤ V

C=10 pF, 1.08 V ≤ V

DDIOx

C=30 pF, 1.62 V ≤ V

C=30 pF, 1.08 V ≤ V

DDIOx

C=10 pF, 1.62 V ≤ V

C=10 pF, 1.08 V ≤ V

DDIOx

C=30 pF, 1.62 V ≤ V

≤

DDIOx

≤

DDIOx

≤

DDIOx

≤

DDIOx

≤

DDIOx

≤

DDIOx

≤

DDIOx

3.6 V

≤

3.6 V

≤

3.6 V

≤

3.6 V

≤

3.6 V

≤

3.6 V

≤

3.6 V

≤

2.7 V

1.62 V

2.7 V

1.62 V

2.7 V

1.62 V

2.7 V

1.62 V

2.7 V

1.62 V

2.7 V

1.62 V

2.7 V

1.62 V

100

(3)

37.5

5.8

2.5

3.3

MHz ns

Fm+

Fmax Maximum frequency

Tf Output fall time

(4)

C=50 pF, 1.6 V ≤ V

DDIOx

≤ 3.6 V

MHz ns

1. The I/O speed is configured using the OSPEEDRy[1:0] bits. The Fm+ mode is configured in the SYSCFG_CFGR1 register.

Refer to the RM0394 reference manual for a description of GPIO Port configuration register.

2. Guaranteed by design.

3. This value represents the I/O capability but the maximum system frequency is limited to 80 MHz.

4. The fall time is defined between 70% and 30% of the output waveform accordingly to I 2 C specification.

DS12469 Rev 8 135/192

164

Electrical characteristics

Figure 29. I/O AC characteristics definition

(1)

90% 10%

50% 50%

10% 90% t r(IO)out t f(IO)out

STM32L412xx when loaded by the specified capacitance.

MS32132V2

1. Refer to Table 71: I/O AC characteristics .

6.3.15 NRST pin characteristics

The NRST pin input driver uses the CMOS technology. It is connected to a permanent pullup resistor, R

Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in

Table 21: General operating conditions .

Symbol Parameter

Table 72. NRST pin characteristics (1)

Conditions Min Typ Max Unit

IL(NRST)

IH(NRST)

V hys(NRST)

F(NRST)

NF(NRST)

NRST input low level voltage

NRST input high level voltage

NRST Schmitt trigger voltage hysteresis

Weak pull-up equivalent resistor

(2)

NRST input filtered pulse

NRST input not filtered pulse

= V

1.71 V ≤ V

≤ 3.6 V

0.7

ₓ V

DDIOx

350

200

0.3

ₓ V

DDIOx

1. Guaranteed by design.

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimal (~10% order)

V mV k Ω ns ns

136/192 DS12469 Rev 8

STM32L412xx Electrical characteristics

Figure 30. Recommended NRST pin protection

External reset circuit

(1)

0.1 μF

NRST

(2)

Filter

Internal reset

MS19878V3

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the V

IL(NRST)

max level specified in

Table 72: NRST pin characteristics

. Otherwise the reset will not be taken into account by the device.

3. The external capacitor on NRST must be placed as close as possible to the device.

6.3.16 Extended interrupt and event controller input (EXTI) characteristics

The pulse on the interrupt input must have a minimal length in order to guarantee that it is detected by the event controller.

Symbol

Table 73. EXTI Input Characteristics (1)

Parameter

PLEC

Pulse length to event controller

1. Guaranteed by design.

Conditions

Min

Typ

Max

Unit ns

6.3.17 Analog switches booster

Symbol

Table 74. Analog switches booster characteristics (1)

Parameter

DD t

SU(BOOST)

Supply voltage

Booster startup time

DD(BOOST)

Booster consumption for

1.62 V ≤ V

≤ 2.0 V

Booster consumption for

2.0 V ≤ V

≤ 2.7 V

Booster consumption for

2.7 V ≤ V

≤ 3 .6 V

1. Guaranteed by design.

Min

1.62

Typ

Max

3.6

240

250

500

900

Unit

µs

µA

DS12469 Rev 8 137/192

164

Electrical characteristics STM32L412xx

Note:

Symbol

DDA

REF+

REF-

V f

ADC f s f

TRIG

CMIN

AIN

(3)

AIN

ADC

Unless otherwise specified, the parameters given in Table 75

are preliminary values derived from tests performed under ambient temperature, f

PCLK frequency and V

conditions summarized in Table 21: General operating conditions

DDA

supply voltage

It is recommended to perform a calibration after each power-up.

Parameter

Table 75. ADC characteristics

(1) (2)

Conditions Min

Analog supply voltage

Positive reference voltage

DDA

≥ 2 V

DDA

< 2 V

Negative reference voltage

Range 1

ADC clock frequency

Sampling rate for FAST channels

Range 2

Resolution = 12 bits

Resolution = 10 bits

Resolution = 8 bits

Resolution = 6 bits

Resolution = 12 bits

Resolution = 10 bits

Sampling rate for SLOW channels

Resolution = 8 bits

Resolution = 6 bits

External trigger frequency f

ADC

= 80 MHz

Resolution = 12 bits

1.62

Input common mode Differential mode

0.14

Typ

DDA

SSA

Max

3.6

DDA

7.27

8.88

4.21

4.71

5.33

6.15

5.33

6.15

5.33

REF+

REF-

- 0.18

)/2

REF+

REF-

)/2

REF+

REF-

+ 0.18

)/2

Conversion voltage range(2)

External input impedance

Internal sample and hold capacitor

REF+

Unit

MHz

Msps

MHz

1/f

ADC

V k Ω pF t

STAB t

CAL

Power-up time

Calibration time

ADC

= 80 MHz

1.45

116 conversion cycle

µs

1/f

ADC

138/192 DS12469 Rev 8

STM32L412xx Electrical characteristics

Symbol

Table 75. ADC characteristics (1) (2) (continued)

Parameter Conditions Min Typ Max Unit

t

t t

LATR

LATRINJ t s

ADCVREG_STUP

Trigger conversion latency Regular and injected channels without conversion abort

CKMODE = 00

CKMODE = 01

CKMODE = 10

CKMODE = 11

Trigger conversion latency Injected channels aborting a regular conversion

CKMODE = 00

CKMODE = 01

CKMODE = 10

CKMODE = 11

Sampling time f

ADC

= 80 MHz

ADC voltage regulator start-up time

ADC

= 80 MHz

Resolution = 12 bits

Total conversion time

(including sampling time)

Resolution = 12 bits

1.5

2.5

0.03125

2.5

0.1875

2.5

2.0

2.25

2.125

3.5

3.0

3.25

3.125

8.00625

640.5

8.1625

1/f

ADC

µs

ADC

µs

I t

CONV

DDA

(ADC)

DDV_S

DDV_D

(ADC)

ADC consumption from the V

DDA

supply

ADC consumption from the V

REF+ mode

ADC consumption from the V mode

single ended

REF+

differential fs = 5 Msps fs = 1 Msps fs = 10 ksps fs = 5 Msps fs = 1 Msps fs = 10 ksps fs = 5 Msps fs = 1 Msps fs = 10 ksps ts + 12.5 cycles for successive approximation

= 15 to 653

730 830

160

130

0.6

260

1.3

220

160

310

1/f

ADC

µA

1. Guaranteed by design

2. The I/O analog switch voltage booster is enable when V

DDA

< 2.4V). It is disable when V

DDA

≥ 2.4 V.

DDA

< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when

REF+

can be internally connected to V

DDA

and V

Section 4: Pinouts and pin description

REF-

can be internally connected to V

for further details.

SSA

, depending on the package.

The maximum value of R

AIN

can be found in Table 76: Maximum ADC RAIN .

DS12469 Rev 8 139/192

164

Electrical characteristics

Resolution

12 bits

10 bits

8 bits

6 bits

1. Guaranteed by design.

STM32L412xx

Table 76. Maximum ADC R

AIN

(1)(2)

Sampling cycle

@80 MHz

Sampling time [ns]

@80 MHz

AIN

max ( Ω )

Fast channels

(3) channels

(4)

92.5

247.5

640.5

2.5

6.5

12.5

640.5

2.5

6.5

12.5

24.5

47.5

24.5

47.5

92.5

247.5

640.5

2.5

6.5

12.5

24.5

47.5

92.5

247.5

2.5

6.5

12.5

24.5

47.5

92.5

247.5

8006.75

31.25

81.25

156.25

306.25

593.75

1156.25

3093.75

8006.75

31.25

81.25

156.25

8006.75

31.25

81.25

156.25

306.25

593.75

1156.25

3093.75

31.25

81.25

156.25

306.25

593.75

1156.25

3093.75

306.25

593.75

1156.25

3093.75

8006.75

6800

15000

50000

220

560

1200

47000

180

470

1000

1800

2700

39000

120

390

820

1500

2200

5600

12000

100

330

680

1500

2200

4700

12000

2700

3900

8200

18000

50000

5600

12000

50000

N/A

330

1000

39000

N/A

270

680

1500

2200

33000

N/A

180

560

1200

1800

4700

10000

N/A

100

470

1200

1800

3900

10000

2200

3300

6800

15000

50000

140/192 DS12469 Rev 8

STM32L412xx Electrical characteristics

2. The I/O analog switch voltage booster is enable when V

DDA

< 2.4V). It is disable when V

DDA

≥ 2.4 V.

DDA

< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when

3. Fast channels are: PC0, PC1, PC2, PC3, PA0, PA1.

4. Slow channels are: all ADC inputs except the fast channels.

DS12469 Rev 8 141/192

164

Electrical characteristics STM32L412xx

Table 77. ADC accuracy - limited test conditions 1 (1)(2)(3)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

ENOB

SINAD

SNR

Total unadjusted error

Offset error

Gain error

Effective number of bits

Signal-tonoise and distortion ratio

Signal-tonoise ratio

Single ended

Differential

Single ended

Differential

Single ended

Differential

Differential linearity error

Integral linearity error

ADC clock frequency ≤

80 MHz,

Sampling rate ≤ 5.33 Msps,

DDA

= VREF+ = 3 V,

TA = 25 °C

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

1 1.5

1 1.2

1.5

2.5

1.5

2.5

1 2

Slow channel (max speed) 1 2

Fast channel (max speed) 10.4 10.5

Slow channel (max speed) 10.4 10.5

Fast channel (max speed) 10.8 10.9

Slow channel (max speed) 10.8 10.9

Fast channel (max speed) 64.4 65 -

Slow channel (max speed) 64.4 65

Fast channel (max speed) 66.8 67.4

Slow channel (max speed) 66.8 67.4

Fast channel (max speed) 65 66

Slow channel (max speed) 65 66

Fast channel (max speed) 67 68

Slow channel (max speed) 67 68

4 5

3.5

4.5

3.5

4.5

1 2.5

1.5

2.5

1.5

2.5

4.5

2.5

4.5

2.5

3.5

2.5

3.5

1 1.5

LSB bits dB

142/192 DS12469 Rev 8

STM32L412xx Electrical characteristics

Table 77. ADC accuracy - limited test conditions 1 (1)(2)(3) (continued)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

THD

Total harmonic distortion

ADC clock frequency ≤

80 MHz,

Sampling rate ≤ 5.33 Msps,

DDA

= V

REF+

= 3 V,

= 25 °C

Single ended

Differential

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed)

Slow channel (max speed)

-74

-79

-73

-76

-76 dB

1. Guaranteed by design.

2. ADC DC accuracy values are measured after internal calibration.

3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a

Schottky diode (pin to ground) to analog pins which may potentially inject negative current.

4. The I/O analog switch voltage booster is enable when V

DDA

< 2.4 V). It is disable when V

DDA

< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when

≥ 2.4 V. No oversampling.

DS12469 Rev 8 143/192

164

Electrical characteristics STM32L412xx

Table 78. ADC accuracy - limited test conditions 2 (1)(2)(3)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

ENOB

SINAD

SNR

Total unadjusted error

Offset error

Gain error

Effective number of bits

Signal-tonoise and distortion ratio

Signal-tonoise ratio

Single ended

Differential

Single ended

Differential

Single ended

Differential

Differential linearity error

ADC clock frequency ≤

80 MHz,

Sampling rate ≤ 5.33 Msps,

2 V ≤ V

DDA Integral linearity error

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

1 1.5

1 1.2

1.5

3.5

1.5

3.5

1 3

Slow channel (max speed) 1 2.5

Fast channel (max speed) 10 10.5

Slow channel (max speed) 10 10.5

Fast channel (max speed) 10.7 10.9

Slow channel (max speed) 10.7 10.9

Fast channel (max speed) 62 65 -

Slow channel (max speed) 62 65

Fast channel (max speed) 66 67.4

Slow channel (max speed) 66 67.4

Fast channel (max speed) 64 66

Slow channel (max speed) 64 66

Fast channel (max speed) 66.5 68

Slow channel (max speed) 66.5 68

4 6.5

3.5

5.5

3.5

5.5

1 4.5

1 5

1.5

2.5

3.5

2.5

3.5

1 1.5

LSB bits dB

144/192 DS12469 Rev 8

STM32L412xx Electrical characteristics

Table 78. ADC accuracy - limited test conditions 2 (1)(2)(3) (continued)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

THD

Total harmonic distortion

ADC clock frequency ≤

80 MHz,

Sampling rate ≤ 5.33 Msps,

2 V ≤ V

DDA

Single ended

Differential

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

-74 -65

-74 -67

-79 -70

-79 -71 dB

1. Guaranteed by design.

2. ADC DC accuracy values are measured after internal calibration.

Schottky diode (pin to ground) to analog pins which may potentially inject negative current.

4. The I/O analog switch voltage booster is enable when V

DDA

< 2.4 V). It is disable when V

DDA

< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when

≥ 2.4 V. No oversampling.

DS12469 Rev 8 145/192

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Electrical characteristics STM32L412xx

Table 79. ADC accuracy - limited test conditions 3 (1)(2)(3)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

ENOB

SINAD

SNR

Total unadjusted error

Offset error

Gain error

Effective number of bits

Signal-tonoise and distortion ratio

Signal-tonoise ratio

Single ended

Differential

Single ended

Differential

Single ended

Differential

Differential linearity error

Integral linearity error

ADC clock frequency ≤

80 MHz,

Sampling rate ≤ 5.33 Msps,

1.65 V ≤ V

DDA

3.6 V,

= V

REF+

≤

Voltage scaling Range 1

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

1.2

1.5

1 1.2

3 3.5

2.5

3.5

2 2.5

Slow channel (max speed) 2 2.5

Fast channel (max speed) 10 10.4

Slow channel (max speed) 10 10.4

Fast channel (max speed) 10.6 10.7

Slow channel (max speed) 10.6 10.7

Fast channel (max speed) 62 64 -

Slow channel (max speed) 62 64

Fast channel (max speed) 65 66

Slow channel (max speed) 65 66

Fast channel (max speed) 63 65

Slow channel (max speed) 63 65

Fast channel (max speed) 66 67

Slow channel (max speed) 66 67

5.5

7.5

4.5

6.5

4.5

7.5

4.5

5.5

2 5

2.5

2 3.5

2.5

4.5

3.5

1.2

1.5

LSB bits dB

146/192 DS12469 Rev 8

STM32L412xx Electrical characteristics

Table 79. ADC accuracy - limited test conditions 3 (1)(2)(3) (continued)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

THD

Total harmonic distortion

ADC clock frequency ≤

80 MHz,

Sampling rate ≤ 5.33 Msps,

1.65 V ≤ V

DDA

3.6 V,

= V

REF+

≤

Voltage scaling Range 1

Single ended

Differential

Fast channel (max speed)

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

-69 -67

-71 -67

-72 -71

-72 -71 dB

1. Guaranteed by design.

2. ADC DC accuracy values are measured after internal calibration.

Schottky diode (pin to ground) to analog pins which may potentially inject negative current.

4. The I/O analog switch voltage booster is enable when V

DDA

< 2.4 V). It is disable when V

DDA

< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when

≥ 2.4 V. No oversampling.

DS12469 Rev 8 147/192

164

Electrical characteristics STM32L412xx

Table 80. ADC accuracy - limited test conditions 4 (1)(2)(3)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

ENOB

SINAD

SNR

Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error

ADC clock frequency ≤

26 MHz,

1.65 V ≤ V

DDA

3.6 V,

= VREF+ ≤

Voltage scaling Range 2

Effective number of bits

Signal-tonoise and distortion ratio

Signal-tonoise ratio

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

1 1.5

1 1.2

2.5

2 2.5

Slow channel (max speed) 2 2.5

Fast channel (max speed) 10.2 10.5

Slow channel (max speed) 10.2 10.5

Fast channel (max speed) 10.6 10.7

Slow channel (max speed) 10.6 10.7

Fast channel (max speed) 63 65 -

Slow channel (max speed) 63 65

Fast channel (max speed) 65 66

Slow channel (max speed) 65 66

Fast channel (max speed) 64 65

Slow channel (max speed) 64 65

Fast channel (max speed) 66 67

Slow channel (max speed) 66 67

5 5.4

3.5

4.5

2 4

2 3.5

4 4.5

1 1.5

LSB bits dB

148/192 DS12469 Rev 8

STM32L412xx Electrical characteristics

Table 80. ADC accuracy - limited test conditions 4 (1)(2)(3) (continued)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

THD

Total harmonic distortion

ADC clock frequency

26 MHz,

1.65 V ≤ V

DDA

3.6 V,

≤

= VREF+ ≤

Voltage scaling Range 2

Single ended

Differential

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

-71 -69

-73 -72

-73 -72 dB

1. Guaranteed by design.

2. ADC DC accuracy values are measured after internal calibration.

Schottky diode (pin to ground) to analog pins which may potentially inject negative current.

4. The I/O analog switch voltage booster is enable when V

DDA

< 2.4 V). It is disable when V

DDA

< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when

≥ 2.4 V. No oversampling.

Figure 31. ADC accuracy characteristics

SSA

4095

4094

4093

1 LSB

IDEAL

1 2 3 4 5 6

(2)

(3)

(1)

4093 4094 4095 4096

(1) Example of an actual transfer curve

(2) The ideal transfer curve

(3) End point correlation line

= total unajusted error : maximum deviation

between the actual and ideal transfer curves.

= offset error : maximum deviation

between the first actual transition and

the first ideal one.

= gain error : deviation between the last

ideal transition and the last actual one.

= differential linearity error : maximum

deviation between actual steps and the ideal ones.

= integral linearity error : maximum deviation

between any actual transition and the end point

correlation line.

DDA

MS19880V2

DS12469 Rev 8 149/192

164

Electrical characteristics STM32L412xx

Figure 32. Typical connection diagram using the ADC

DDA

AINx

C parasitic

(2)

I lkg

(3)

Sample and hold ADC converter

ADC

12-bit converter

ADC

AIN

(1)

MS33900V5

1. Refer to Table 75: ADC characteristics

for the values of R

AIN

and C

ADC

2. C parasitic

represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

Table 69: I/O static characteristics for the value of the pad capacitance). A high

C parasitic

value will downgrade conversion accuracy. To remedy this, f

ADC

should be reduced.

3. Refer to Table 69: I/O static characteristics for the values of Ilkg.

General PCB design guidelines

Power supply decoupling should be performed as shown in

Figure 18: Power supply scheme

. The 10 nF capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip.

150/192 DS12469 Rev 8

STM32L412xx Electrical characteristics

Symbol Parameter

Table 81. COMP characteristics (1)

Conditions

DDA

Analog supply voltage

Comparator input voltage range

Scaler input voltage

(2)

Scaler offset voltage

BRG_EN=0 (bridge disable)

DDA

(SCALER)

Scaler static consumption from V

DDA t

START_SCALER

Scaler startup time t

START t

(3)

BRG_EN=1 (bridge enable)

Comparator startup time to reach propagation delay specification

Propagation delay with

100 mV overdrive

High-speed mode

DDA

≥ 2.7 V

DDA

< 2.7 V

Medium mode

DDA

≥ 2.7 V

DDA

< 2.7 V

Ultra-low-power mode

High-speed mode

Medium mode

DDA

≥ 2.7 V

DDA

< 2.7 V

V offset

V hys

Comparator offset error

Comparator hysteresis

Ultra-low-power mode

Full common mode range

No hysteresis

Low hysteresis

Medium hysteresis

High hysteresis

Min Typ Max Unit

1.62

3.6

0 V

DDA

0.55

0.8

100

REFINT

±5

200

±10

300

200

100

0.9

µs ns

µs mV nA

µA

µs

±5

±20

mV mV

DS12469 Rev 8 151/192

164

Electrical characteristics STM32L412xx

Symbol

DDA

(COMP)

Table 81. COMP characteristics (1) (continued)

Parameter Conditions Min Typ Max Unit

400 600

Ultra-lowpower mode

Comparator consumption from V

DDA

Medium mode

High-speed mode

Static -

With 50 kHz

±100 mV overdrive square signal

Static -

With 50 kHz

±100 mV overdrive square signal

Static -

With 50 kHz

±100 mV overdrive square signal

1200

100 nA

µA

I bias

Comparator input bias current

1. Guaranteed by design, unless otherwise specified.

2. Refer to Table 24: Embedded internal voltage reference

3. Guaranteed by characterization results.

4. Mostly I/O leakage when used in analog mode. Refer to I lkg

parameter in Table 69: I/O static characteristics .

(4) nA

Symbol

DDA

CMIR

OFFSET

∆ VI

OFFSET

Parameter

Table 82. OPAMP characteristics (1)

Conditions

Analog supply voltage

(2)

Common mode input range

Input offset voltage

Input offset voltage drift

25 °C, No Load on output.

All voltage/Temp.

Normal mode

Low-power mode

TRIMOFFSETP

TRIMLPOFFSETP

TRIMOFFSETN

TRIMLPOFFSETN

Offset trim step at low common input voltage

(0.1 ₓ V

DDA

)

Offset trim step at high common input voltage

(0.9 ₓ V

DDA

)

Min

1.8

Typ

Max

3.6

Unit

±5

±10

DDA

±1.5

±3

V mV

μ V/°C

0.8

1.1

1.35

152/192 DS12469 Rev 8

STM32L412xx

Symbol

LOAD

LOAD_PGA

LOAD

LOAD_PGA

LOAD

CMRR

PSRR

GBW

(3)

OHSAT

OLSAT

φ m

Electrical characteristics

Table 82. OPAMP characteristics (1) (continued)

Parameter Conditions Min

Drive current

Drive current in

PGA mode

Normal mode

Low-power mode

Normal mode

Low-power mode

DDA

≥ 2 V

DDA

≥ 2 V

Resistive load

(connected to

VSSA or to

VDDA)

Normal mode

Low-power mode

DDA

< 2 V

Typ

Max

500

100

450

Unit

µA

Resistive load in PGA mode

(connected to

VSSA or to

DDA

)

Capacitive load

Power supply rejection ratio

Low saturation voltage

Phase margin

Normal mode

Low-power mode

Common mode rejection ratio

Normal mode

Low-power mode

Normal mode

Low-power mode

Normal mode

Gain Bandwidth

Product

Low-power mode

Normal mode

Low-power mode

Slew rate

(from 10 and

90% of output voltage)

Open loop gain

Normal mode

Low-power mode

Normal mode

Low-power mode

Normal mode

Low-power mode

High saturation voltage

Normal mode

Low-power mode

Normal mode

Low-power mode

Normal mode

Low-power mode

DDA

< 2 V

4.5

40 -

-85

-90

LOAD

≤ 50 pf,

≥ 4 k Ω DC

LOAD

≤ 50 pf,

≥ 20 k Ω DC

DDA

≥ 2.4 V

(OPA_RANGE = 1)

DDA

< 2.4 V

(OPA_RANGE = 0)

≥ 2.4 V

< 2.4 V

I load

= max or R load min Input at V

DDA

100

DDA

load

= max or R load min Input at 0.

90 -

550 1600 2200

100 420 600

250

700

180

950

280

700

180

300

80 -

110

110 -

100

k Ω pF dB dB kHz

V/ms dB mV

DS12469 Rev 8 153/192

164

Electrical characteristics STM32L412xx

Symbol

GM t

WAKEUP

I bias

PGA gain

Table 82. OPAMP characteristics (1) (continued)

Parameter Conditions Min

Gain margin

Normal mode

Low-power mode -

Wake up time from OFF state.

Normal mode

Low-power mode

LOAD

≤

≥ follower

50 pf,

4 k Ω configuration

LOAD

≤

≥ follower

50 pf,

20 k Ω configuration

OPAMP input bias current

General purpose input -

Non inverting gain value

PGA Gain = 2

R network

R2/R1 internal resistance values in PGA mode

(5)

PGA Gain = 4

PGA Gain = 8

PGA Gain = 16

Delta R

Resistance variation (R1 or

R2)

PGA gain error PGA gain error

Gain = 2

-15

-1

PGA BW

PGA bandwidth for different non inverting gain

Gain = 4

Gain = 8

Gain = 16 -

Typ

GBW/

80/80

120/

140/

150/

Max

(4)

Unit dB

µs nA

k Ω /k Ω

MHz

154/192 DS12469 Rev 8

STM32L412xx Electrical characteristics

Symbol

Table 82. OPAMP characteristics (1) (continued)

Parameter Conditions Min Typ Max Unit en

Voltage noise density

Normal mode

Low-power mode

Normal mode

Low-power mode at 1 kHz, Output loaded with 4 k Ω at 1 kHz, Output loaded with 20 k Ω at 10 kHz, Output loaded with 4 k Ω at 10 kHz, Output loaded with 20 k Ω

500

600

180

290 -

nV/ √

DDA

(OPAMP)

Table 69: I/O static characteristics

OPAMP consumption from V

DDA

Normal mode

Low-power mode no Load, quiescent mode

120

260

100

1. Guaranteed by design, unless otherwise specified.

2. The temperature range is limited to 0 °C-125 °C when V

DDA

is below 2 V

3. Guaranteed by characterization results.

4. Mostly I/O leakage, when used in analog mode. Refer to I lkg

parameter in

5. R2 is the internal resistance between OPAMP output and OPAMP inverting input. R1 is the internal resistance between

OPAMP inverting input and ground. The PGA gain =1+R2/R1

µA

6.3.21 Temperature sensor characteristics

Symbol

(1)

Avg_Slope (2)

30 t

START

(TS_BUF)

START

Table 83. TS characteristics

Parameter

linearity with temperature

Average slope

Voltage at 30°C (±5 °C)

(3)

Sensor Buffer Start-up time in continuous mode

Start-up time when entering in continuous mode

(4)

Min

2.3

0.742

Typ

±1

2.5

0.76

Max

±2

2.7

0.785

120

Unit

°C mV/°C

µs

µs t

S_temp

Temperature sensor calibration values

ADC sampling time when reading the temperature 5 µs

(TS) (1)

Temperature sensor consumption from V

DD selected by ADC

, when

4.7

7 µA

1. Guaranteed by design.

2. Guaranteed by characterization results.

3. Measured at V = 3.0 V ±10 mV. The V

ADC conversion result is stored in the TS_CAL1 byte. Refer to

Table 8:

4. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes.

DS12469 Rev 8 155/192

164

Electrical characteristics STM32L412xx

6.3.22 V

BAT

monitoring characteristics

Symbol

Table 84. V

BAT

monitoring characteristics

Parameter

(1)

Resistor bridge for V

BAT

Ratio on V

BAT

measurement

Error on Q t

S_vbat

(1) ADC sampling time when reading the VBAT

1. Guaranteed by design.

Min

-10

Typ

Symbol

Table 85. V

BAT

charging characteristics

Parameter Conditions Min Typ

Battery charging resistor

VBRS = 0

VBRS = 1 -

1.5

Max

Unit k Ω

µs

The parameters given in the following tables are guaranteed by design.

Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate

function characteristics (output compare, input capture, external clock, PWM output).

Symbol

Table 86. TIMx (1) characteristics

Parameter Conditions Min Max Unit t res(TIM)

Timer resolution time

TIMxCLK

= 80 MHz

12.5

TIMxCLK ns f

EXT

Res

TIM

Timer external clock frequency on CH1 to CH4

Timer resolution f

TIMxCLK

= 80 MHz

TIMx (except

TIM2)

TIMxCLK

/2 MHz

MHz bit

TIM2 32 t

COUNTER

16-bit counter clock period

1 f

TIMxCLK

= 80 MHz 0.0125

MAX_COUNT

Maximum possible count with 32-bit counter f

TIMxCLK

= 80 MHz -

1. TIMx

, is used as a general term in which x stands for 1,2,3,4,5,6,7,8,15,16 or 17.

65536

819.2

TIMxCLK

µs

65536 × 65536 t

TIMxCLK

53.68

156/192 DS12469 Rev 8

STM32L412xx Electrical characteristics

Table 87. IWDG min/max timeout period at 32 kHz (LSI) (1)

Prescaler divider PR[2:0] bits

Min timeout RL[11:0]=

0x000

Max timeout RL[11:0]=

0xFFF

Unit

/16

/32

/64

/128

/256

6 or 7

0.125

0.250

0.500

1.0

2.0

4.0

8.0

512

1024

2048

4096

8192

16384

32768 ms

1. The exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.

Prescaler

Table 88. WWDG min/max timeout value at 80 MHz (PCLK)

WDGTB Min timeout value Max timeout value

0.0512

0.1024

0.2048

0.4096

3.2768

6.5536

13.1072

26.2144

Unit ms

6.3.24 Communication interfaces characteristics

I

C interface characteristics

The I2C interface meets the timings requirements of the I

C-bus specification and user manual rev. 03 for:

• Standard-mode (Sm): with a bit rate up to 100 kbit/s

• Fast-mode (Fm): with a bit rate up to 400 kbit/s

• Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.

The I2C timings requirements are guaranteed by design when the I2C peripheral is properly configured (refer to RM0394 reference manual).

The SDA and SCL I/O requirements are met with the following restrictions: the SDA and

SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and V

DDIOx

is disabled, but is still present. Only FT_f I/O pins support Fm+ low level output current maximum requirement. Refer to

Section 6.3.14: I/O port characteristics for the I2C I/Os characteristics.

All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog filter characteristics:

DS12469 Rev 8 157/192

164

Electrical characteristics

Symbol

Table 89. I2C analog filter characteristics (1)

Parameter t

Maximum pulse width of spikes that are suppressed by the analog filter

1. Guaranteed by design.

2. Spikes with widths below t

AF(min) are filtered.

3. Spikes with widths above t

AF(max)

are not filtered

Min

(2)

Max

260

(3)

STM32L412xx

Unit ns

158/192 DS12469 Rev 8

STM32L412xx Electrical characteristics

SPI characteristics

Unless otherwise specified, the parameters given in

Table 90

for SPI are derived from tests performed under the ambient temperature, f

PCLKx frequency and supply voltage conditions summarized in

Table 21: General operating conditions .

• Output speed is set to OSPEEDRy[1:0] = 11

• Capacitive load C = 30 pF

• Measurement points are done at CMOS levels: 0.5 ₓ V

Refer to Section 6.3.14: I/O port characteristics

for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI).

Symbol Parameter

Table 90. SPI characteristics

(1)

Conditions

1/t

SCK c(SCK)

SPI clock frequency

Master mode receiver/full duplex

2.7 < V

< 3.6 V

Voltage Range 1

Master mode receiver/full duplex

1.71 < V

< 3.6 V

Voltage Range 1

Master mode transmitter

1.71 < V

< 3.6 V

Voltage Range 1

Slave mode receiver

1.71 < V

< 3.6 V

Voltage Range 1

Slave mode transmitter/full duplex

2.7 < V

< 3.6 V

Voltage Range 1

Slave mode transmitter/full duplex

1.71 < V

< 3.6 V

Voltage Range 1

Voltage Range 2 t su(NSS) t h(NSS) t w(SCKH) t w(SCKL) t su(MI) t su(SI) t h(MI) t h(SI) t a(SO) t dis(SO)

NSS setup time

NSS hold time

SCK high and low time Master mode

Data input setup time

Data input hold time

Slave mode, SPI prescaler = 2

Master mode

Slave mode

Master mode

Slave mode

Data output access time Slave mode

Data output disable time Slave mode

Min

4 ₓ T

PCLK

2 ₓ T

PCLK

1.5

6.5

1.5

Typ

PCLK

-2 T

PCLK

Max

(2)

Unit

MHz ns ns

PCLK

+2 ns ns ns ns ns

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Electrical characteristics STM32L412xx

Symbol Parameter

Table 90. SPI characteristics (1) (continued)

Conditions Min Typ Max Unit t v(SO)

Data output valid time

Slave mode 2.7 < V

Voltage Range 1

< 3.6 V

Slave mode 1.71 < V

Voltage Range 1

< 3.6 V

Slave mode 1.71 < V

Voltage Range 2

< 3.6 V

12.5

13.5

33 ns t v(MO) t h(SO) t h(MO)

Data output hold time

Master mode

Slave mode

Master mode

4.5

1. Guaranteed by characterization results.

2. Maximum frequency in Slave transmitter mode is determined by the sum of t having t su(MI)

= 0 while Duty(SCK) = 50 %.

v(SO)

and t su(MI)

which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master

Figure 33. SPI timing diagram - slave mode and CPHA = 0

NSS input t su(NSS) t w(SCKH) t c(SCK) t r(SCK) t h(NSS)

CPHA=0

CPOL=0

CPHA=0

CPOL=1 t a(SO)

MISO output t w(SCKL)

First bit OUT t h(SI) t v(SO) t h(SO)

Next bits OUT t f(SCK)

Last bit OUT t dis(SO) t su(SI)

MOSI input First bit IN Next bits IN Last bit IN

MSv41658V1

160/192 DS12469 Rev 8

STM32L412xx Electrical characteristics

Figure 34. SPI timing diagram - slave mode and CPHA = 1

NSS input

CPHA=1

CPOL=0

CPHA=1

CPOL=1 t su(NSS) t a(SO)

MISO output t w(SCKH) t c(SCK) t w(SCKL) t v(SO) t su(SI)

First bit OUT t h(SI)

First bit IN t h(SO)

Next bits OUT

MOSI input Next bits IN

1. Measurement points are done at CMOS levels: 0.3 V

and 0.7 V

Figure 35. SPI timing diagram - master mode

High

NSS input tc(SCK)

CPHA= 0

CPOL=0

CPHA= 0

CPOL=1 t f(SCK) t h(NSS) t r(SCK) t dis(SO)

Last bit OUT

Last bit IN

MSv41659V1

CPHA=1

CPOL=0

CPHA=1

CPOL=1

MISO

INP UT

MOSI

OUTPUT tsu(MI) tw(SCKH) tw(SCKL)

MSB IN th(MI)

MSB OUT tv(MO)

BIT6 IN

B I T1 OUT th(MO)

1. Measurement points are done at CMOS levels: 0.3 V

and 0.7 V

tr(SCK) tf(SCK)

LSB IN

LSB OUT ai14136c

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Electrical characteristics STM32L412xx

Quad SPI characteristics

Unless otherwise specified, the parameters given in

Table 91

and Table 92 for Quad SPI

are derived from tests performed under the ambient temperature, f

AHB

frequency and V

supply voltage conditions summarized in Table 21: General operating conditions

, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 11

• Capacitive load C = 15 or 20 pF

• Measurement points are done at CMOS levels: 0.5 ₓ V

Refer to Section 6.3.14: I/O port characteristics

for more details on the input/output alternate function characteristics.

Symbol

1/t

(CK) t w(CKH) t w(CKL) t s(IN) t h(IN) t v(OUT) t h(OUT)

Table 91. Quad SPI characteristics in SDR mode (1)

Parameter Conditions Min

Quad SPI clock frequency

1.71 < V

< 3.6 V, C

LOAD

= 20 pF

Voltage Range 1

1.71 < V

< 3.6 V, C

LOAD

= 15 pF

Voltage Range 1

2.7 < V

< 3.6 V, C

LOAD

= 15 pF

Voltage Range 1

1.71 < V

< 3.6 V C

LOAD

= 20 pF

Voltage Range 2

Quad SPI clock high and low time

Data input setup time

Data input hold time

Data output valid time

Data output hold time f

AHBCLK

= 48 MHz, presc=0

Voltage Range 1

Voltage Range 2

Voltage Range 1

Voltage Range 2

Voltage Range 1

Voltage Range 2

Voltage Range 1

Voltage Range 2

6.5

0 t

(CK)

/2-2 t

(CK)

3.5

1. Guaranteed by characterization results.

Typ

Max

(CK)

/2 t

(CK)

/2+2

Unit

MHz ns

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STM32L412xx Electrical characteristics

Symbol

Table 92. QUADSPI characteristics in DDR mode (1)

Parameter Conditions

1/t

(CK)

Quad SPI clock frequency

1.71 < V

< 3.6 V, C

LOAD

= 20 pF

Voltage Range 1

2 < V

< 3.6 V, C

LOAD

Voltage Range 1

= 20 pF

1.71 < V

< 3.6 V, C

LOAD

= 15 pF

Voltage Range 1

1.71 < V

< 3.6 V C

Voltage Range 2

LOAD

= 20 pF t w(CKH) t w(CKL)

Quad SPI clock high and low time f

AHBCLK

= 48 MHz, presc=0 t t t t sr(IN) sf(IN) hr(IN) hf(IN)

Data input setup time on rising edge

Voltage Range 1

Voltage Range 2

Data input setup time on falling edge

Voltage Range 1

Data input hold time on rising edge

Voltage Range 2

Voltage Range 1

Voltage Range 2

Data input hold time on falling edge

Voltage Range 1

Voltage Range 2 t t vr(OUT) vf(OUT)

Data output valid time on rising edge

Voltage Range 1

Voltage Range 2

Data output valid time on falling edge

Voltage Range 1

Voltage Range 2 t t hr(OUT) hf(OUT)

Data output hold time on rising edge

Voltage Range 1

Voltage Range 2

Data output hold time on falling edge

Voltage Range 1

Voltage Range 2

1. Guaranteed by characterization results.

Min

Typ

Max

26 t

(CK)

/2-2 t

(CK)

/2 t

(CK)

/2+2

3.5

1.5

6.5

5.5

3.5

9.5

5.5

8.5

Unit

MHz ns

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Electrical characteristics STM32L412xx t r(CK)

Figure 36. Quad SPI timing diagram - SDR mode t

(CK) t w(CKH) t w(CKL) t f(CK)

Clock

Data output

Data input t v(OUT) t h(OUT)

D0 t s(IN)

D1 t h(IN)

D2 t r(CLK)

Figure 37. Quad SPI timing diagram - DDR mode t

(CLK) t w(CLKH) t w(CLKL) t f(CLK)

MSv36878V1

Clock t vf(OUT) t hr(OUT) t vr(OUT) t hf(OUT)

Data output IO0 IO1 t sf(IN) t hf(IN)

IO2 IO3 IO4 t sr(IN) t hr(IN)

IO5

Data input IO0 IO1 IO2 IO3 IO4 IO5

MSv36879V3

USB characteristics

The USB interface is fully compliant with the USB specification version 2.0 and is USB-IF certified (for Full-speed device operation).

Symbol

DDUSB

T crystal_less t

STARTUP

(3)

PUI

PUR

DRV