STMicroelectronics VNH3ASP30-E Datasheet

VNH3ASP30-E

Automotive fully integrated H-bridge motor driver

MultiPowerSO-30 ™

Features

Type

VNH3ASP30-E

R

DS(on)

42 m  max

 per leg)

I out

V ccmax

30 A 41 V

 AEC-100 qualified

 5 V logic level compatible inputs

 Undervoltage and overvoltage shutdown

 Overvoltage clamp

 Thermal shut down

 Cross-conduction protection

 Linear current limiter

 Very low standby power consumption

 PWM operation up to 20 kHz

 Protection against loss of ground and loss of

V

CC

 Current-sense output proportional to motor current

 Package: ECOPACK

®

Description

The VNH3ASP30-E is a full-bridge motor driver intended for a wide range of automotive applications. The device incorporates a dual monolithic high-side driver (HSD) and two low-

Datasheet

-

production data side switches. The HSD switch is designed using

STMicroelectronics proprietary VIPower™ M0 technology that efficiently integrates a true Power

MOSFET with an intelligent signal/protection circuit on the same die.

The low-side switches are vertical MOSFETs manufactured using STMicroelectronics proprietary EHD (“STripFET™”) process.The three circuits are assembled in a

MultiPowerSO-30 package on electrically isolated lead frames. This package, specifically designed for the harsh automotive environment, offers improved thermal performance thanks to exposed die pads. Moreover, its fully symmetrical mechanical design provides superior manufacturability at board level. The input signals

IN

A

and IN

B

can directly interface with the microcontroller to select the motor direction and the brake condition. Pins DIAG

DIAG

B

/EN

B

A

/EN

A

or

, when connected to an external pullup resistor, enable one leg of the bridge. They also provide a feedback digital diagnostic signal.

The normal condition operation is explained in the truth table. The CS pin monitors the motor current by delivering a current proportional to its value.

The speed of the motor can be controlled in all possible conditions by the PWM up to 20 kHz. In all cases, a low level state on the PWM pin will turn off both the LS

A and LS

B

PWM rises to a high level, LS switches. When

A or LS

B again depending on the input pin state.

turn on

Table 1. Device summary

Order code

Package

Tape & reel

MultiPowerSO-30 VNH3ASP30TR-E

January 2017

This is information on a product in full production.

DocID10833 Rev 7 1/34 www.st.com

1

2

Contents

Contents

3

4

5

6

VNH3ASP30-E

Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.3

Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.1

Reverse battery protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.1

MultiPowerSO-30 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.1.1

4.1.2

4.1.3

4.1.4

Thermal calculation in clockwise and anti-clockwise operation in

Steady-state mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Thermal resistances definition (values according to the PCB heatsink area) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Thermal calculation in Transient mode . . . . . . . . . . . . . . . . . . . . . . . . . 26

Single pulse thermal impedance definition (values according to the PCB heatsink area) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.1

MultiPowerSO-30 package information . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.2

Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2/34 DocID10833 Rev 7

VNH3ASP30-E

List of tables

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Block description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin functions description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Logic inputs (INA, INB, ENA, ENB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 9.

Switching (V

CC

= 13V, R

LOAD

= 1 W ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 10.

Protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 11.

Current sense (9V < V

CC

< 16V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 12.

Truth table in normal operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 13.

Truth table in fault conditions (detected on OUTA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 14.

Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 15.

Thermal calculation in clockwise and anti-clockwise operation in steady-state mode . . . . 26

Table 16.

Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 17.

MultiPowerSO-30 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 18.

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

DocID10833 Rev 7 3/34

34

List of figures

List of figures

VNH3ASP30-E

Figure 1.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2.

Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3.

Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 4.

Definition of the delay times measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 5.

Definition of the low-side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 6.

Definition of the high-side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 7.

Definition of dynamic cross conduction current during a PWM operation. . . . . . . . . . . . . . 13

Figure 8.

On state supply current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 9.

Off state supply current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 10.

High-level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 11.

Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 12.

Input high-level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 13.

Input low-level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 14.

Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 15.

High-level enable pin current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 16.

Delay time during change of operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 17.

Enable clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 18.

High-level enable voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 19.

Low-level enable voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 20.

PWM high-level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 21.

PWM low-level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 22.

PWM high-level current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 23.

Overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 24.

Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 25.

Current limitation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 26.

On state high-side resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 27.

On state low-side resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 28.

On state high-side resistance vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 29.

On state low-side resistance vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 30.

Output voltage rise time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 31.

Output voltage fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 32.

Typical application circuit for DC to 20 kHz PWM operation short circuit protection . . . . . 20

Figure 33.

Half-bridge configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 34.

Multi-motor configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 35.

Waveforms in full-bridge operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 36.

Waveforms in full-bridge operation (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 37.

MultiPowerSO-30™ PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 38.

Chipset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 39.

Auto and mutual RthJA vs PCB copper area in open box free air condition. . . . . . . . . . . . 26

Figure 40.

MultiPowerSO-30 HSD thermal impedance junction ambient single pulse . . . . . . . . . . . . 27

Figure 41.

MultiPowerSO-30 LSD thermal impedance junction ambient single pulse . . . . . . . . . . . . . 28

Figure 42.

Thermal fitting model of an H-bridge in MultiPowerSO-30 . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 43.

MultiPowerSO-30 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 44.

MultiPowerSO-30 suggested pad layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 45.

MultiPowerSO-30 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4/34 DocID10833 Rev 7

VNH3ASP30-E

1

Block diagram and pin description

Block diagram and pin description

Figure 1. Block diagram

V

CC

OVERTEMPERATURE A

OUT

A

HS

A

CLAMP HS

A

DRIVER

HS

A

CURRENT

LIMITATION A

LS

A

CLAMP LS

A

DRIVER

LS

A

1/K

O

V

+ U

V

LOGIC

OVERTEMPERATURE B

DRIVER

HS

B

CLAMP HS

B

HS

B

CURRENT

LIMITATION B

1/K

DRIVER

LS

B

CLAMP LS

B

LS

B

OUT

B

GND

A

DIAG

A

/EN

A

IN

A

CS PWM IN

B

DIAG

B

/EN

B

GND

B

Name

Table 2. Block description

Description

Logic control

Allows the turn-on and the turn-off of the high-side and the low-side switches according to the truth table

Overvoltage + undervoltage

High-side and lowside clamp voltage

High-side and lowside driver

Linear current limiter

Overtemperature protection

Fault detection

Shuts down the device outside the range [5.5V..16V] for the battery voltage

Protect the high-side and the low-side switches from the high voltage on the battery line in all configurations for the motor

Drives the gate of the concerned switch to allow a good R

DS(on) the bridge

for the leg of

Limits the motor current by reducing the high-side switch gate source voltage when short-circuit to ground occurs

In case of short-circuit with the increase of the junction’s temperature, shuts down the concerned high side to prevent its degradation and to protect the die

Signals an abnormal behavior of the switches in the half-bridge A or B by pulling low the concerned EN x

/DIAG x

pin

DocID10833 Rev 7 5/34

34

Block diagram and pin description

Figure 2. Configuration diagram (top view)

OUT

A

Nc

V

CC

Nc

IN

A

EN

A

/DIAG

A

Nc

PWM

CS

EN

B

/DIAG

B

IN

B

Nc

V

CC

Nc

OUT

B

1

15

V

CC

Heat Slug1

VNH3ASP30-E

OUT

A

Heat Slug3

OUT

B

Heat Slug2

30

16

V

CC

Nc

OUT

B

GND

B

GND

B

GND

B

Nc

OUT

B

OUT

A

Nc

GND

A

GND

A

GND

A

OUT

A

Nc

Pin No.

Table 3. Pin definitions and functions

Symbol Function

5

6

8

9

1, 25, 30 OUT

A

, Heat Slug3 Source of high-side switch A / Drain of low-side switch A

2, 4, 7, 12, 14,

17, 22, 24, 29

NC Not connected

3, 13, 23 V

CC

, Heat Slug1 Drain of high-side switches and power supply voltage

IN

A

Clockwise input

EN

A

/DIAG

PWM

A

Status of high-side and low-side switches A; open drain output

PWM input

CS Output of current sense

10

11

15, 16, 21

26, 27, 28

18, 19, 20

EN

B

/DIAG

B

IN

B

Status of high-side and low-side switches B; open drain output

Counter clockwise input

OUT

B

, Heat Slug2 Source of high-side switch B / Drain of low-side switch B

GND

A

Source of low-side switch A

(1)

GND

B

Source of low-side switch B

(1)

1. GND

A

and GND

B

must be externally connected together.

6/34 DocID10833 Rev 7

VNH3ASP30-E Block diagram and pin description

Name

Table 4. Pin functions description

Description

V

CC

GND

A

, GND

B

OUT

A

, OUT

B

Battery connection

Power grounds; must always be externally connected together

IN

A

,

EN

A

EN

B

IN

PWM

B

/DIAG

A

/DIAG

B

,

Power connections to the motor

Voltage controlled input pins with hysteresis, CMOS compatible: These two pins control the state of the bridge in normal operation according to the truth table (brake to V

CC

, brake to GND, clockwise and counterclockwise).

Voltage controlled input pin with hysteresis, CMOS compatible: Gates of low-side

FETs are modulated by the PWM signal during their ON phase allowing speed control of the motor.

Open drain bidirectional logic pins. These pins must be connected to an external pull up resistor. When externally pulled low, they disable half-bridge A or B. In case of fault detection (thermal shutdown of a high-side FET or excessive ON state voltage drop across a low-side FET), these pins are pulled low by the device (see truth table in fault condition).

CS

Analog current-sense output. This output sources a current proportional to the motor current. The information can be read back as an analog voltage across an external resistor.

DocID10833 Rev 7 7/34

34

Electrical specifications VNH3ASP30-E

Figure 3. Current and voltage conventions

I

S

V

INA

V

INB

I

INA

I

INB

IN

A

I

ENA

IN

B

DIAG

A

/EN

A

I

ENB

V

ENA

V

ENB

DIAG

B

/EN

B

PWM

I pw

V pw

V

CC

GND

A

OUT

A

OUT

B

GND

B

I

CS

GND

GND

I

SENSE

V

SENSE

I

I

OUTA

OUTB

V

OUTB

V

OUTA

V

CC

2.1 Absolute maximum ratings

Symbol

V

CC

I max

I

R

I

IN

I

EN

I

PW

V

CS

V

T

T

ESD

T

J

C stg

Table 5. Absolute maximum ratings

Parameter

Supply voltage

Maximum output current (continuous)

Reverse output current (continuous)

Input current (IN

A

and IN

B

pins)

Enable input current (DIAG

A

/EN

A

and DIAG

B

/EN

B pins)

PWM input current

Current-sense maximum voltage

Electrostatic discharge (R = 1.5k

 , C = 100pF)

– CS pin

– logic pins

– output pins: OUT

A

, OUT

B

, V

CC

Junction operating temperature

Case operating temperature

Storage temperature

Value

+41

30

-30

 10

 10

 10

-3/+15

2

4

5

Internally limited

-40 to 150

-55 to 150

Unit

V

A mA

°C

V kV kV kV

8/34 DocID10833 Rev 7

VNH3ASP30-E Electrical specifications

V

CC

= 9V up to 16 V; -40°C < T

J

< 150°C, unless otherwise specified.

Symbol

R

I

V

I

I

CC

V

S

R

ONHS

ONLS f

L(off)

RM

Parameter

Table 6. Power section

Test conditions

Operating supply voltage

Supply current

Static high-side resistance

Static low-side resistance

High-side freewheeling diode forward voltage

High-side off-state output current

(per channel)

Dynamic crossconduction current

Off state:

IN

A

= IN

B

= PWM = 0; T

J

IN

A

= IN

B

= PWM = 0;

= 25°C; V

CC

= 13V

On state:

IN

A

or IN

B

= 5V, no PWM

I

OUT

= 12A; T

J

= 25°C

I

OUT

= 12A; T

J

= -40 to 150°C

I

OUT

I

OUT

= 12A T

= 12A; T

J

= 25°C

J

= -40 to 150°C

I f

= 12A

T

T

J

J

= 25°C; V

OUTX

= 125°C; V

OUTX

= EN

X

= EN

X

= 0V; V

I

OUT

= 12A (see Figure 7 )

CC

= 13V

= 0V; V

CC

= 13V

Min Typ Max Unit

5.5

12 30 µA

60 µA

10 mA

30

60 m 

12

24 m 

0.8

1.1

V

1.7

16 V

3

5

µA

A

Symbol

V

IL

V

IH

V

Ihys

V

V

I

I

ICL

INL

INH

DIAG

Table 7. Logic inputs (IN

A

, IN

B

, EN

A

, EN

B

)

Parameter Test conditions Min Typ Max Unit

Input low-level voltage

Input high-level voltage

Input hysteresis voltage

Input clamp voltage

Input low current

Input high current

Enable output low-level voltage

1.25

Normal operation (DIAG as an input pin)

X

/EN

X

pin acts

I

IN

= 1mA

I

IN

= -1mA

V

IN

= 1.25 V

V

IN

= 3.25V

Fault operation (DIAG

X an output pin); I

EN

/EN

= 1mA

X

pin acts as

3.25

0.5

5.5 6.3 7.5

-1.0 -0.7 -0.3

1

10

0.4

V

µA

V

DocID10833 Rev 7 9/34

34

Electrical specifications VNH3ASP30-E

Symbol

V

PWL

V

I

V

I

PWL

PWH

PWH

PWhys

Parameter

PWM low-level voltage

PWM low-level pin current

PWM high-level voltage

PWM high-level pin current

PWM hysteresis voltage

Table 8. PWM

Test conditions

V pw

= 1.25 V

V pw

= 3.25V

Min

1

3.25

V

PWCL

PWM clamp voltage

I pw

= 1mA

I pw

= -1mA

Typ Max

1.25

10

0.5

V

CC

+ 0.3

V

CC

+ 0.7

V

CC

+ 1.0

-6.0 -4.5

-3.0

C

INPW

PWM pin input capacitance

V

IN

= 2.5V

25

Symbol f

PW

Table 9. Switching (V

CC

= 13V, R

LOAD

= 1  )

Parameter

PWM frequency

Test conditions Min Typ

0 t d(on) t d(off) t r t f t

DEL t rr

Turn-on delay time

Turn-off delay time

Rise time

Fall time

Delay time during change of operating mode

High-side freewheeling diode reverse recovery time

Input rise time < 1µs

(see

Figure 6 )

Input rise time < 1µs

(see

Figure 6 )

(see Figure 5 )

(see Figure 5 )

(see

Figure 4 )

(see

Figure 7 )

1

1

110

Max

20

250

250

1.6

2.4

300 600 1800

Unit

V

µA

V

µA

V pF

Unit kHz

µs ns

Symbol

Table 10. Protection and diagnostic

Parameter

V

UV(sd)

V

UV(reset)

V

OV(sd)

I

LIM

V

CLP

T th(sd)

T h(reset)

T th(hys)

Undervoltage shutdown

Undervoltage reset

Overvoltage shutdown

High-side current limitation

Total clamp voltage (V

CC

to GND)

Thermal shutdown temperature

Thermal reset temperature

Thermal hysteresis

Test conditions Min Typ Max Unit

I

OUT

= 12A

V

IN

= 3.25V

5.5

4.7

16 19 22

30 50 70

43 48 54

150 175 200

135

7 15

V

A

V

°C

10/34 DocID10833 Rev 7

VNH3ASP30-E Electrical specifications

Symbol

Table 11. Current sense (9V < V

CC

< 16V)

Parameter Test conditions Min Typ Max Unit dK dK

I

1

2

K

K

1

2

/K

/K

1

(1)

2

(1)

SENSEO

I

I

OUT

OUT

/I

/I

SENSE

SENSE

Analog sense current drift

Analog sense current drift

Analog sense leakage current

I

OUT

T

J

= 30A; R

SENSE

= -40 to 150°C

= 700  ;

I

OUT

T

J

= 8A; R

SENSE

= -40 to 150°C

= 700  ;

I

OUT

T

J

= 30A; R

SENSE

= -40 to 150°C

= 700  ;

I

OUT

T

J

= 8A; R

SENSE

= -40 to 150°C

= 700  ;

I

OUT

= 0A; V

SENSE

= 0V;

T

J

= -40 to 150°C

4000

3750

-8

-10

0

4700

4700

1. Analog sense current drift is deviation of factor K for a given device over (-40°C to 150°C and

9V < V

CC

< 16V) with respect to its value measured at T

J

= 25°C, V

CC

= 13V

5400

5650

+8

+10

70

%

µA

DocID10833 Rev 7 11/34

34

Electrical specifications

V

INA

Figure 4. Definition of the delay times measurement

VNH3ASP30-E t

V

INB t

PWM t

I

LOAD t

DEL t

DEL t

Figure 5. Definition of the low-side switching times

PWM t

V

OUTA, B

90% t f

80%

20% 10% t r t

12/34 DocID10833 Rev 7

VNH3ASP30-E Electrical specifications

V

INA

Figure 6. Definition of the high-side switching times t

D(on) t

D(off) t

V

OUTA

90%

10% t

Figure 7. Definition of dynamic cross conduction current during a PWM operation

IN

A

= 1, IN

B

= 0

PWM t

I

MOTOR t

V

OUTB t

I

CC

I

RM t t rr

DocID10833 Rev 7 13/34

34

Electrical specifications VNH3ASP30-E

IN

A

1

0

IN

B

1

0

1

0

Table 12. Truth table in normal operating conditions

DIAG

A

/EN

A

DIAG

B

/EN

B

OUT

A

OUT

B

CS Operating mode

1 1

H

L

H High Imp.

L

H

I

SENSE

= I

OUT

/K

L High Imp.

Brake to V

CC

Clockwise (CW)

Counterclockwise (CCW)

Brake to GND

IN

A

1

0

X

IN

B

Table 13. Truth table in fault conditions (detected on OUT

A

)

DIAG

A

/EN

A

DIAG

B

/EN

B

OUT

A

OUT

B

X

1

0

1

0

1

0

0

1

0

1

OPEN

H

L

H

L

OPEN

H

L

CS

High Imp.

I

OUTB

/K

High Imp.

I

OUTB

/K

High Imp.

Note:

Fault Information Protection Action

Notice that saturation detection on the low side power MOSFET is possible only if the impedance of the short-circuit from the output to the battery is less than 100m  when the device is supplied with a battery voltage of 13.5V.

14/34 DocID10833 Rev 7

VNH3ASP30-E Electrical specifications

ISO T/R - 7637/1 test pulse

3a

3b

1

2

4

5

Table 14. Electrical transient requirements

Test level

I

Test level II

Test level

III

Test level IV

Test level delays and impedance

-25V

+25V

-25V

+25V

-4V

+26.5V

-50V

+50V

-50V

+50V

-5V

+46.5V

-75V

+75V

-100V

+75V

-6V

+66.5V

-100V

+100V

-150V

+100V

-7V

+86.5V

2ms, 10 

0.2ms, 10 

0.1µs, 50 

100ms, 0.01



400ms, 2 

ISO T/R - 7637/1 test pulse

Test levels result

I

Test levels result

II

Test levels result

III

Test levels result

IV

1

2

3a

3b

5

4

(1)

C

C

E

C

E

1. For load dump exceeding the above value a centralized suppressor must be adopted.

Class Contents

C

E

C

E

All functions of the device performed as designed after exposure to disturbance.

One or more functions of the device did not perform as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.

DocID10833 Rev 7 15/34

34

Electrical specifications VNH3ASP30-E

16/34

Figure 8. On state supply current

I

S

(mA)

8

7

6

V

CC

= 13V, no PWM

IN A or IN B = 5V

5

4

3

2

1

0

-50 -25 0 25 50 75 100 125 150 175

T c

(°C)

6

5

4

Figure 10. High-level input current

I

INH

(µA)

8

7

V

CC

= 9V…16V

V

IN

= 3.25V

3

2

1

0

-50 -25 0 25 50 75 100 125 150 175

T c

(°C)

Figure 12. Input high-level voltage

V

IH

(V)

3.6

3.4

V

CC

= 9V…16V

3.2

3.0

2.8

2.6

2.4

2.2

2.0

-50 -25 0 25 50 75 100 125 150 175

T c

(°C)

Figure 9. Off state supply current

I

S

(µA)

50

45

40

35

30

25

20

15

10

5

0

-50 -25

V

CC

= 13V

0 25 50 75 100 125 150 175

T c

(°C)

Figure 11. Input clamp voltage

V

ICL

(V)

8.00

7.75

I

IN

= 1mA

7.50

7.25

7.00

6.75

6.50

6.25

6.00

-50 -25 0 25 50 75 100 125 150 175

T c

(°C)

Figure 13. Input low-level voltage

V

IL

(V)

2.8

2.6

2.4

2.2

2.0

1.8

1.6

V

CC

1.4

1.2

1.0

-50 -25

= 9V…16V

0 25 50 75 100 125 150 175

T c

(°C)

DocID10833 Rev 7

VNH3ASP30-E

Figure 14. Input hysteresis voltage

V

IHYST

(V)

2.0

1.2

1.0

0.8

0.6

1.8

1.6

1.4

V

0.4

0.2

0.0

-50 -25

CC

= 9V…16V

0 25 50 75 100 125 150 175

T c

(°C)

Figure 16. Delay time during change of operation mode t

DEL

(µs)

1000

900

800

700

600

500

400

300

200

100

0

-50 -25

V

CC

= 13V

R

L

= 1ohm

0 25 50 75 100 125 150 175

T c

(°C)

Figure 18. High-level enable voltage

V

ENH

(V)

4.0

3.8

3.6

3.4

V

3.2

3.0

2.8

2.6

2.4

2.2

2.0

-50 -25

CC

= 9V…16V

0 25 50 75 100 125 150 175

T c

(°C)

Electrical specifications

Figure 15. High-level enable pin current

I

ENH

(µA)

8

7

6

5

4

3

2

1

0

-50 -25

V

CC

= 8V…24V

V

EN

= 3.25V

0 25 50 75 100 125 150 175

T c

(°C)

Figure 17. Enable clamp voltage

V

ENCL

(V)

8.00

7.75

7.50

7.25

7.00

6.75

6.50

6.25

6.00

-50 -25

I

EN

= 1mA

0 25 50 75 100 125 150 175

T c

(°C)

Figure 19. Low-level enable voltage

V

ENL

(V)

2.8

2.6

2.4

2.2

2.0

V

1.8

1.6

1.4

1.2

1.0

-50 -25

CC

= 9V…16V

0 25 50 75 100 125 150 175

T c

(°C)

DocID10833 Rev 7 17/34

34

Electrical specifications

Figure 20. PWM high-level voltage

V

PWH

(V)

4.0

3.8

3.6

V

CC

= 9V…16V

3.4

3.2

3.0

2.8

2.6

2.4

2.2

2.0

-50 -25 0 25 50 75 100 125 150 175

T c

(°C)

Figure 22. PWM high-level current

I

PWH

(µA)

8.0

7.0

6.0

5.0

4.0

3.0

V

V

CC

PW

= 9V

= 3.25V

2.0

1.0

-50 -25 0 25 50 75 100 125 150 175

T c

(°C)

Figure 24. Undervoltage shutdown

V

USD

(V)

7.0

6.5

6.0

5.5

5.0

4.5

4.0

3.5

3.0

-50 -25 0 25 50 75 100 125 150 175

T c

(°C)

18/34 DocID10833 Rev 7

VNH3ASP30-E

Figure 21. PWM low-level voltage

V

PWL

(V)

2.8

2.6

V

CC

= 9V…16V

2.4

2.2

2.0

1.8

1.6

1.4

1.2

1.0

-50 -25 0 25 50 75 100 125 150 175

T c

(°C)

Figure 23. Overvoltage shutdown

V

OV

(V)

30

28

26

24

22

20

18

16

14

12

10

-50 -25 0 25 50 75 100 125 150 175

T c

(°C)

I

LIM

(A)

80

Figure 25. Current limitation

75

70

V

CC

= 16V

65

60

55

50

45

40

35

30

-50 -25 0 25 50 75 100 125 150 175

T c

(°C)

VNH3ASP30-E Electrical specifications

Figure 26. On state high-side resistance vs

T case

R

ONHS

(mOhm)

80

70

V

CC

= 13V

I

OUT

= 12A

60

50

40

30

20

10

0

-50 -25 0 25 50 75 100 125 150 175

T c

(°C)

Figure 27. On state low-side resistance vs T

30

25

20

15

R

ONLS

(mOhm)

40

35

V

CC

= 13V

I

OUT

= 12A

10

5

0

-50 -25 0 25 50 75 100 125 150 175

T c

(°C) case

Figure 28. On state high-side resistance vs V

CC

R

ONHS

(mOhm)

80

70

I

LOAD

= 12A

Figure 29. On state low-side resistance vs V

CC

R

ONHS

(mOhm)

40

35

I

LOAD

= 12A

60

50

T c

= 150°C

40

30 T c

= 25°C

T c

= -40°C

20

10

0

8 9 10 11 12 13 14 15 16 17 18 19 20

V

CC

(V)

30

25

20

15

T c

= 150°C

T c

= 25°C

10

5

T c

= -40°C

0

8 9 10 11 12 13 14 15 16 17 18 19 20

V

CC

(V)

0.8

0.7

0.6

0.5

Figure 30. Output voltage rise time t

R

(µs)

1.0

0.9

V

CC

= 13V

R

L

= 1ohm

0.4

0.3

0.2

-50 -25 0 25 50 75 100 125 150 175

T c

(°C)

Figure 31. Output voltage fall time t

F

(µs)

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

-50 -25

V

CC

= 13V

R

L

= 1ohm

0 25 50 75 100 125 150 175

T c

(°C)

DocID10833 Rev 7 19/34

34

Application information VNH3ASP30-E

Note:

20/34

In normal operating conditions the DIAG

X

/EN

X device. This pin must be externally pulled high.

pin is considered as an input pin by the

PWM pin usage: In all cases, a “0” on the PWM pin will turn off both LS

A

When PWM rises back to “1”, LS

A

or LS

B

and LS

B

switches.

turn on again depending on the input pin state.

Figure 32. Typical application circuit for DC to 20 kHz PWM operation short circuit protection

V

CC

Reg 5V

+ 5V

+5V

V

CC 3.3K

 C

3.3K

1K

DIAG

A

/EN

A

1K

PWM

HS

A

OUT

A OUT B

HS

B

DIAG

B

/EN

B

1K

1K IN

A

10K

CS

LS

A

M

LS

B

IN

B

C

1K

33nF

1.5K

GND

A

GND

B

100K G

S b) N MOSFET

D

The value of the blocking capacitor (C) depends on the application conditions and defines voltage and current ripple onto supply line at PWM operation. Stored energy of the motor inductance may fly back into the blocking capacitor, if the bridge driver goes into tristate. This causes a hazardous overvoltage if the capacitor is not big enough. As basic orientation, 500µF per 10A load current is recommended.

In case of a fault condition the DIAG

X

/EN

X

pin is considered as an output pin by the device.

The fault conditions are: overtemperature on one or both high sides short to battery condition on the output (saturation detection on the low-side power

MOSFET)

Possible origins of fault conditions may be:

OUT

A

is shorted to ground



overtemperature detection on high side A

OUT

A

is shorted to V

CC



low-side power MOSFET saturation detection

When a fault condition is detected, the user can know which power element is in fault by monitoring the IN

A

, IN

B

, DIAG

A

/EN

A

and DIAG

B

/EN

B

pins.

In any case, when a fault is detected, the faulty leg of the bridge is latched off. To turn on the respective output (OUT

X

) again, the input signal must rise from low to high level.

DocID10833 Rev 7

VNH3ASP30-E Application information

Three possible solutions can be considered: a Schottky diode D connected to V

CC

pin

an N-channel MOSFET connected to the GND pin (see Figure 32: Typical application circuit for DC to 20 kHz PWM operation short circuit protection on page 20

) a P-channel MOSFET connected to the V

CC

pin

The device sustains no more than -30 A in reverse battery conditions because of the two body diodes of the power MOSFETs. Additionally, in reverse battery condition the I/Os of

Root part number 1 are pulled down to the V

CC

line (approximately -1.5 V). A series resistor must be inserted to limit the current sunk from the microcontroller I/Os. If I maximum target reverse current through µC I/Os, the series resistor is:

Rmax

is the

R =

IRmax

Figure 33. Half-bridge configuration

V

CC

IN

IN

A

B

DIAG

DIAG

PWM

A

/EN

A

B

/EN

B

OUT

A

GND

A

GND

B

OUT

B

M

OUT

A

DIAG

DIAG

A

B

IN

IN

/EN

/EN

A

B

A

B

PWM

OUT

B

GND

A

GND

B

Note: The VNH3ASP30-E can be used as a high power half-bridge driver achieving an On resistance per leg of 21 m  .

DocID10833 Rev 7 21/34

34

Application information VNH3ASP30-E

IN

A

IN

B

DIAG

A

/EN

A

DIAG

PWM

B

/EN

B

OUT

A

GND

A

GND

B

Figure 34. Multi-motor configuration

V

CC

OUT

B

M

2 OUT

A

IN

A

IN

B

DIAG

A

/EN

A

DIAG

B

/EN

B

PWM

OUT

B

GND

A

GND

B

Note:

M

1

M

3

The VNH3ASP30-E can easily be designed in multi-motor driving applications such as seat positioning systems, where only one motor must be driven at a time. The DIAG

X allow the unused half-bridges to be put into high impedance.

/EN

X

pins

22/34 DocID10833 Rev 7

VNH3ASP30-E Application information

Figure 35. Waveforms in full-bridge operation

NORMAL OPERATION (DIAG

A

/EN

A

= 1, DIAG

B

/EN

B

LOAD CONNECTED BETWEEN OUT

A

, OUT

B

= 1)

DIAG

A

/EN

A

DIAG

IN

A

B

/EN

B

IN

B

PWM

OUT

A

OUT

B

I

OUTA

->

OUTB

CS (*) t

DEL

(*) CS behavior during PWM mode will depend on PWM frequency and duty cycle.

t

DEL

NORMAL OPERATION (DIAG

A

/EN

A

= 1, DIAG

B

/EN

B

= 0 and DIAG

A

/EN

A

LOAD CONNECTED BETWEEN OUT

A

, OUT

B

DIAG

A

/EN

A

= 0, DIAG

B

/EN

B

= 1)

DIAG

B

/EN

B

IN

A

IN

B

PWM

OUT

A

OUT

B

I

OUTA

->

OUTB

CS

CURRENT LIMITATION/THERMAL SHUTDOWN or OUT

A

SHORTED TO GROUND

IN

A

IN

B

I

OUTA

->

OUTB

I

LIM

T

TSD

T

TR

T

J

> T

TR T

J

DIAG

A

/EN

A

DIAG

B

/EN

B

CS normal operation OUT

A

shorted to ground normal operation

DocID10833 Rev 7 23/34

34

Application information

Figure 36. Waveforms in full-bridge operation (continued)

OUT

A

shorted to V

CC

and undervoltage shutdown

VNH3ASP30-E

IN

A

IN

B

OUT

A

OUT

B

I

OUTA

->

OUTB

DIAG

B

/EN

B

DIAG

A

/EN

A

CS V < nominal normal operation

OUT

A

shorted to V

CC normal operation undefined undefined undervoltage shutdown

24/34 DocID10833 Rev 7

VNH3ASP30-E

4 Package and PCB thermal data

Package and PCB thermal data

4.1 MultiPowerSO-30 thermal data

Figure 37. MultiPowerSO-30™ PC board

Note: Layout condition of Rth and Zth measurements (PCB FR4 area= 58 mm x 58 mm, PCB thickness=2 mm, Cu thickness=35 µm, Copper areas: from minimum pad lay-out to

16 cm2).

Figure 38. Chipset configuration

HIGH-SIDE

CHIP

HS

AB

LOW-SIDE

CHIP A

LS

A

LOW-SIDE

CHIP B

LS

B

DocID10833 Rev 7 25/34

34

Package and PCB thermal data VNH3ASP30-E

Figure 39. Auto and mutual R thJA

vs PCB copper area in open box free air condition

25

20

15

10

5

0

45

40

°C/W

35

30

0 5 cm

2

10 15

of Cu Area (refer to PCB layout)

RthA

RthB = RthC

RthAB = RthAC

RthBC

20

4.1.1

4.1.2

4.1.3

Thermal calculation in clockwise and anti-clockwise operation in

Steady-state mode

Table 15. Thermal calculation in clockwise and anti-clockwise operation in steadystate mode

HS

A

HS

B

LS

A

LS

B

T

JHSAB

T

JLSA

T

JLSB

ON

OFF

OFF

ON

ON

OFF

P dHSA

x R thHS

+ P dLSB x R thHSLS

+ T

A

P dHSB

x R thHS

+ P dLSA x R thHSLS

+ T

A

P dHSA

P dLSB

x R thHSLS

+

x R thLSLS

+ T

A

P dHSB

P dLSA

x R thHSLS

+

x R thLS

+ T

A

P dHSA

x R thHSLS

+ P dLSB x R thLS

+ T

A

P dHSB

x R thHSLS

+ P dLSA x R thLSLS

+ T

A

Thermal resistances definition (values according to the PCB heatsink area)

R thHS

HS

B

= R thHSA

= R thHSB

= High-Side Chip Thermal Resistance Junction to Ambient (HS

A

or

in ON state)

R thLS

= R thLSA

= R thLSB

= Low-Side Chip Thermal Resistance Junction to Ambient

R thHSLS

= R thHSALSB

= R thHSBLSA

= Mutual Thermal Resistance Junction to Ambient between High-Side and Low-Side Chips

R thLSLS

Chips

= R thLSALSB

= Mutual Thermal Resistance Junction to Ambient between Low-Side

Thermal calculation in Transient mode

(a)

T

JHSAB

= Z thHS

x P dHSAB

+ Z thHSLS

x (P dLSA

+ P dLSB

) + T

A a. Calculation is valid in any dynamic operating condition. P d

values set by user.

26/34 DocID10833 Rev 7

VNH3ASP30-E Package and PCB thermal data

T

JLSA

= Z thHSLS

x P dHSAB

+ Z thLS

x P dLSA

+ Z thLSLS

x P dLSB

+ T

A

T

JLSB

= Z thHSLS

x P dHSAB

+ Z thLSLS

x P dLSA

+ Z thLS

x P dLSB

+ T

A

4.1.4 Single pulse thermal impedance definition (values according to the

PCB heatsink area)

Z thHS

= High-Side Chip Thermal Impedance Junction to Ambient

Z thLS

= Z thLSA

= Z thLSB

= Low-Side Chip Thermal Impedance Junction to Ambient

Z thHSLS

= Z thHSABLSA

= Z thHSABLSB

= Mutual Thermal Impedance Junction to Ambient between High-Side and Low-Side Chips

Z thLSLS

Chips

= Z thLSALSB

= Mutual Thermal Impedance Junction to Ambient between Low-Side

Equation 1: pulse calculation formula

ZTH



= RTH where 

=

 

+ –

 

Figure 40. MultiPowerSO-30 HSD thermal impedance junction ambient single pulse

100

10

Footprint

4 cm

2

8 cm

2

16 cm

2

Footprint

4 cm

2

8 cm

2

16 cm

2

1

0,1

0,001 0,01 0,1 time (sec) 1 10 100 1000

DocID10833 Rev 7 27/34

34

Package and PCB thermal data VNH3ASP30-E

Figure 41. MultiPowerSO-30 LSD thermal impedance junction ambient single pulse

100

10

Footprint

4 cm

2

8 cm

2

16 cm

2

Footprint

4 cm

2

8 cm

2

16 cm

2

Z ls

Z lsls

1

0,1

0,001 0,01 0,1 time (sec) 1 10 100 1000

Figure 42. Thermal fitting model of an H-bridge in MultiPowerSO-30

28/34

Area/island (cm

2

)

R1 = R7 (°C/W)

R2 = R8 (°C/W)

R3 (°C/W)

R4 (°C/W)

R5 (°C/W)

R6 (°C/W)

Table 16. Thermal parameters (1)

Footprint 4

0.05

0.3

0.5

1.3

14

44.7

39.1

DocID10833 Rev 7

8

31.6

16

23.7

VNH3ASP30-E Package and PCB thermal data

R9 = R15 (°C/W)

R10 = R16 (°C/W)

R11 = R17 (°C/W)

R12 = R18 (°C/W)

R13 = R19 (°C/W)

R14 = R20 (°C/W)

R21 = R22 = R23 (°C/W)

C1 = C7 (W.s/°C)

C2 = C8 (W.s/°C)

Table 16. Thermal parameters (1) (continued)

0.11

0.21

0.42

1.5

20

46.9

115

0.005

0.008

C3 0.01

36.1

30.4

C4 = C13 = C19 (W.s/°C)

C5 (W.s/°C)

C6 (W.s/°C)

C9 = C15 (W.s/°C)

C10 = C16 (W.s/°C)

C11 = C17 (W.s/°C)

C12 = C18 (W.s/°C)

C14 = C20 (W.s/°C)

0.3

0.6

5

0.0016

0.0032

0.0053

0.075

2.5

7

3.5

9

4.5

1. The blank space means that the value is the same as the previous one.

20.8

11

5.5

DocID10833 Rev 7 29/34

34

Package information VNH3ASP30-E

5.1

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com

.

ECOPACK ® is an ST trademark.

MultiPowerSO-30 package information

Figure 43. MultiPowerSO-30 package outline

30/34

Symbol

D

E

E1 e

F1

F2

A

A2

A3

B

C

Table 17. MultiPowerSO-30 mechanical data

Millimeters

Min Typ

1.85

0

0.42

0.23

17.1

18.85

15.9

5.55

4.6

17.2

16

1

DocID10833 Rev 7

Max

2.35

2.25

0.1

0.58

0.32

17.3

19.15

16.1

6.05

5.1

VNH3ASP30-E Package information

Symbol

Table 17. MultiPowerSO-30 mechanical data (continued)

Millimeters

Min Typ

F3

L

N

S

9.6

0.8

0 deg

Max

10.1

1.15

10 deg

7 deg

Figure 44. MultiPowerSO-30 suggested pad layout

DocID10833 Rev 7 31/34

34

Package information VNH3ASP30-E

Note: The devices are packed in tape and reel shipments (see the

Device summary on page 1

).

Figure 45. MultiPowerSO-30 tape and reel shipment (suffix “TR”)

Reel dimensions

Dimension

A (max)

B (min)

C (± 0.2)

D (min)

G (+ 2 / -0)

N (min)

T (max) mm

330

1.5

13

20.2

32

100

38.4

Tape dimensions

According to Electronic Industries

Association (EIA) Standard 481 rev. A, Feb

1986

Description

Tape width

Tape Hole Spacing

Component Spacing

Hole Diameter

Hole Diameter

Hole Position

Dimension

W

P0 (± 0.1)

P

D (± 0.1/-0)

D1 (min)

F (± 0.1) mm

32

4

24

1.5

2

14.2

End

Top cover tape

No components

500 mm min

Components No components

500 mm min

Empty components pockets

User direction of feed

Start

32/34 DocID10833 Rev 7

VNH3ASP30-E Revision history

Date

Sep-2004

Dec-2005

11-Feb-2007

01-Jun-2007

06-Feb-2008

23-Sep-2013

11-Jan-2017

Revision

Table 18. Document revision history

Changes

1

2

3

4

5

6

7

First issue

Resistance per leg modification Figure 33: Half-bridge configuration on page 21

Document converted into new ST template.

Changed Datasheet - production data on page 1 to add ECOPACK

® package

Removed Table 7. Thermal Data from page 4

Table 6: Power section on page 9 : Changed test conditions and max values for supply current in Off state and On state

Table 7: Logic inputs (INA, INB, ENA, ENB) on page 9 : Modified parameter descriptions for I

INL

and I

INH

Table 8: PWM on page 10 : Modified parameter descriptions for I

PWL and I

PWH

Table 10: Protection and diagnostic on page 10 : Modified all symbols except I

LIM

and V

CLP

Table 11 on page 11 : Changed test conditions for K

2 current drift

analog sense

Section Table 13.: Truth table in fault conditions (detected on OUTA) on page 14 : Changed first of two fault conditions

Figure 6: Definition of the high-side switching times on page 13 :

Added vertical limitation line to left side of t

D(off)

arrow

Figure 36: Waveforms in full-bridge operation (continued) on page 24 : Added dotted vertical limitation lines

Added Section 2.3: Electrical characteristics curves on page 16

Added Section 4: Package and PCB thermal data on page 25

Added Section 5: Package information on page 30

Updated disclaimer on last page

Document reformatted.

Table 6: Power section on page 9 : changed test conditions and max values for supply current in Off state

Corrected Heat Slug numbers in Table 3: Pin definitions and functions .

Updated Disclaimer.

– Removed all information relative to tube packing of the product

– Modified Section 5: Package information

– Added AEC-Q100 qualified in the Features section

– Minor text edits throughout the document

DocID10833 Rev 7 33/34

34

VNH3ASP30-E

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on

ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2017 STMicroelectronics – All rights reserved

34/34 DocID10833 Rev 7