STMicroelectronics R5974AD Datasheet
Advertisement
Advertisement
R5974AD
Up to 2 A step-down switching regulator for aerospace applications
HSOP8 - exposed pad
Features
General features
– 2 A DC output current
– Operating input voltage from 4 V to 36 V
– 3.3 V / (±2%) reference voltage
– Large ambient temperature range:
-40 °C to 125 °C
– Output voltage adjustable from 1.235 V to
35 V
– Low dropout operation: 100% duty cycle
– 500 kHz internally fixed frequency
– Voltage feed-forward
– Zero load current operation
– Internal current limiting
– Inhibit for zero current consumption
– Synchronization
– Protection against feedback disconnection
– Thermal shutdown
Aerospace and defense features
– Suitable for use in aerospace and defense applications
– Dedicated traceability and part marking
– Production parts approval documents available
– Adapted extended life time and obsolescence management
– Extended product change notification process
Datasheet
-
preliminary data
– Designed and manufactured to meet subppm quality goals
– Advanced mold and frame designs for superior resilience in harsh environments
(acceleration, EMI, thermal, humidity)
– Extended screening capability on request
Application
Dedicated to aerospace applications
Description
The R5974AD is a step-down monolithic power switching regulator with a minimum switch current limit of 2.5 A, it is therefore able to deliver up to
2 A DC current to the load depending on the application conditions. The output voltage can be set from 1.235 V to 35 V. The high current level is also achieved thanks to a HSOP8 package with exposed frame, that allows to reduce the R
THJ-A down to approximately 40 °C/W. The device uses an internal P-channel DMOS transistor (with a typical R
DS(on)
of 250 m ) as switching element to minimize the size of the external components.
An internal oscillator fixes the switching frequency at 500 kHz. The large ambient temperature range makes it ideal for aerospace and defense applications. Pulse-by-pulse current limit with the internal frequency modulation offers an effective constant current short-circuit protection.
October 2014 DocID027026 Rev 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/48 www.st.com
Contents
Contents
R5974AD
Datasheet parameters over the temperature range . . . . . . . . . . . . . . . 10
Power supply and voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Oscillator and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PWM comparator and power stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Additional features and protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Output overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Error amplifier and compensation network . . . . . . . . . . . . . . . . . . . . . . . . 19
2/48 DocID027026 Rev 1
R5974AD
Contents
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Thermal resistance RTHJ-A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
(t) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Positive buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Negative buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Floating boost current generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Synchronization example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Compensation network with MLCC at the output . . . . . . . . . . . . . . . . . . . 40
DocID027026 Rev 1 3/48
48
List of tables
List of tables
R5974AD
4/48 DocID027026 Rev 1
R5974AD
List of figures
List of figures
= 5 V, f
SW
= 500 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
= 12 V, f
SW
= 500 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Measurement of the thermal impedance of the demonstration board . . . . . . . . . . . . . . . . 31
= 12 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
= 24 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
= 36 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Junction temperature vs. output current (V
Junction temperature vs. output current (V
Efficiency vs. output current (V
IN
= 5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Efficiency vs. output current (V
= 5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
= 12 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
= 12 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
DocID027026 Rev 1 5/48
48
Pin settings R5974AD
Figure 1. Pin connection (top view)
$0Y
3
4
No.
1
2
5
6
7
8
Pin
OUT
SYNCH
INH
COMP
FB
V
REF
GND
V
CC
Table 1. Pin description
Description
Regulator output.
Master/slave synchronization.
A logical signal (active high) disables the device. If INH is not used, the pin must be grounded. When it is open, an internal pull-up disable the device.
E/A output for frequency compensation.
Feedback input. Connecting directly to this pin results in an output voltage of 1.23 V. An external resistive divider is required for higher output voltages.
3.3 V V
REF
. No cap is requested for stability.
Ground.
Unregulated DC input voltage.
6/48 DocID027026 Rev 1
R5974AD Electrical data
Symbol
V
8
V
1
I
1
V
4
, V
5
V
3
V
2
P
TOT
T
J
T
STG
Table 2. Absolute maximum ratings
Parameter
Input voltage
OUT pin DC voltage
OUT pin peak voltage at t = 0.1 µs
Maximum output current
Analog pins
INH
SYNCH
Power dissipation at T
A
60 °C
Operating junction temperature range
Storage temperature range
Value
40
-1 to 40
-5 to 40 int. limit.
4
-0.3 to V
CC
-0.3 to 4
2.25
-40 to 150
-55 to 150
Unit
V
V
V
V
V
V
W
°C
°C
Symbol
Table 3. Thermal data
Parameter
R
THJ-A
Maximum thermal resistance junction ambient
1. Package mounted on demonstration board.
Value
40
(1)
Unit
°C/W
DocID027026 Rev 1 7/48
48
Electrical characteristics R5974AD
T
J
= -40 °C to 125 °C, V
CC
= 12 V, unless otherwise specified.
Symbol Parameter
R
V
CC
DS(on)
I
L
Operating input voltage range
MOSFET on-resistance
Maximum limiting current f
SW
Switching frequency
Duty cycle
Dynamic characteristics (see test circuit)
V
5
Voltage feedback
DC characteristics
I
I qop
I q qst-by
V
V
0
= 1.235 V; I
CC
= 5 V
4.4 V < V
CC
0
= 2 A
< 36 V, 20 mA < I
Total operating quiescent current
Quiescent current
Total standby quiescent current
Duty cycle = 0; V
FB
= 1.5 V
V
INH
> 2.2 V
V
CC
= 36 V; V
INH
> 2.2 V
0
4
2.5
425
0
0.250
3.0
500
< 2 A 1.198
1.235
1.272
V
5
50
50
36
0.5
3.5
575
100
7
100
V
A kHz
% mA
2.7
mA
100 µA
µA
Inhibit
INH threshold voltage
Table 4. Electrical characteristics
Test condition
Device ON
Device OFF
Min.
Typ.
Max.
Unit
2.2
0.8
V
V
Error amplifier
V
OH
High level output voltage
V
OL
Low level output voltage
I o source
Source output current
I o sink
I b
Sink output current
Source bias current
DC open loop gain gm Transconductance
V
FB
= 1 V
V
FB
= 1.5 V
V
COMP
= 1.9 V; V
FB
= 1 V
V
COMP
= 1.9 V; V
FB
= 1.5 V
R
L
=
I
COMP
= -0.1 mA to 0.1 mA;
V
COMP
= 1.9 V
3.5
190
1
50
300
1.5
2.5
65
2.3
0.4
4
V
V
µA mA
µA dB mS
Synch function
High input voltage
Low input voltage
Slave synch current
(1)
Master output amplitude
V
CC
= 4.4 to 36 V
V
CC
= 4.4 to 36 V
V synch
= 0.74 V
V synch
= 2.33 V
I source
= 3 mA
2.5
0.11
0.21
2.75
3
V
REF
0.74
0.25
0.45
V
V mA
V
8/48 DocID027026 Rev 1
R5974AD Electrical characteristics
Symbol
Table 4. Electrical characteristics (continued)
Parameter
Output pulse width
Reference section
Test condition
No load, V synch
= 1.65 V
Min.
Typ.
Max.
Unit
0.20
0.35
µs
Reference voltage
Line regulation
Load regulation
Short-circuit current
1. Guaranteed by design.
I
REF
= 0 to 5 mA
V
CC
= 4.4 V to 36 V
I
REF
= 0 mA, V
CC
= 4.4 V to 36 V
I
REF
= 0 mA
3.2
5
3.3
5
8
18
3.399
V
10
15
35 mV mV mA
DocID027026 Rev 1 9/48
48
Datasheet parameters over the temperature range
4
R5974AD
Datasheet parameters over the temperature range
100% of the population in the production flow is tested at three different ambient temperatures (-40 C, +25 C, and +125 C) to guarantee the datasheet parameters inside the junction temperature range (-40 C, +125 C).
The device operation is guaranteed when the junction temperature is inside the (-40 C;
+150 C) temperature range. The user can estimate the silicon temperature increase with respect to the ambient temperature evaluating the internal power losses generated during
device operation (please refer to Section 2.2
).
However, the embedded thermal protection disables the switching activity to protect the device in case the junction temperature reaches the T
SHTDWN temperature.
(+150 C ± 10 C)
All the datasheet parameters can be guaranteed to a maximum junction temperature of
+125 C, to avoid triggering the thermal shutdown protection during the testing phase due to self-heating.
10/48 DocID027026 Rev 1
R5974AD Functional description
The main internal blocks are shown in the device block diagram in
A voltage regulator supplying the internal circuitry. From this regulator, a 3.3 V reference voltage is externally available.
A voltage monitor circuit which checks the input and the internal voltages.
A fully integrated sawtooth oscillator with a frequency of 500 kHz 15%, including also the voltage feed-forward function and an input/output synchronization pin.
Two embedded current limitation circuits which control the current that flows through the power switch. The pulse-by-pulse current limit forces the power switch OFF cycleby-cycle, if the current reaches an internal threshold, while the frequency shifter reduces the switching frequency in order to significantly reduce the duty cycle.
A transconductance error amplifier.
A pulse width modulator (PWM) comparator and the relative logic circuitry necessary to drive the internal power.
A high side driver for the internal P-MOS switch.
An inhibit block for standby operation.
A circuit to implement the thermal protection function
Figure 2. Block diagram
DocID027026 Rev 1
$0Y
11/48
48
Functional description R5974AD
The internal regulator circuit (shown in Figure 3
) consists of a start-up circuit, an internal voltage pre-regulator, the bandgap voltage reference and the bias block that provides current to all the blocks. The starter supplies the start-up currents to the entire device when the input voltage goes high and the device is enabled (inhibit pin connected to ground). The pre-regulator block supplies the bandgap cell with a pre-regulated voltage, V
REG a very low supply voltage noise sensitivity.
, that has
An internal block continuously senses the V
CC
(UVLO).
, V
REF
and V
BG
. If the voltages go higher than their thresholds, the regulator begins operating. There is also a hysteresis on the V
CC
Figure 3. Internal circuit
$0Y
5.3 Oscillator synchronization
Figure 4 shows the block diagram of the oscillator circuit.
The clock generator provides the switching frequency of the device, which is internally fixed at 500 kHz. The frequency shifter block acts to reduce the switching frequency in case of strong overcurrent or short-circuit. The clock signal is then used in the internal logic circuitry and is the input of the ramp generator and synchronizer blocks.
The ramp generator circuit provides the sawtooth signal, used for PWM control and the internal voltage feed-forward, while the synchronizer circuit generates the synchronization signal. The device also has a synchronization pin which can work both as master and slave.
Beating frequency noise is an issue when more than one voltage rail is on the same board.
A simple way to avoid this issue is to operate all the regulators at the same switching frequency.
12/48 DocID027026 Rev 1
R5974AD Functional description
The synchronization feature, of a set of the R5974AD, is simply obtained by connecting together their SYNCH pins. The device with the highest switching frequency is the master, which provides the synchronization signal to the others. Therefore the SYNCH is an I/O pin to deliver or recognize a frequency signal. The synchronization circuitry is powered by the internal reference (V
REF
V
REF
), so a small filtering capacitor ( 100 nF) connected between the
pin and the signal ground of the master device is recommended for its proper operation. However, when a set of synchronized devices populates a board, it is not possible to know in advance the one working as master, so the filtering capacitor must be designed for a whole set of devices.
When one or more devices are synchronized to an external signal, its amplitude must be in compliance with specifications given in
. The frequency of the synchronization signal must be, at a minimum, higher than the maximum guaranteed natural switching frequency of the device (275 kHz, see
) while the duty cycle of the synchronization signal can vary from approximately 10% to 90%. The small capacitor under the V
REF
pin is required for this operation.
Figure 4. Oscillator circuit block diagram
$0Y
DocID027026 Rev 1 13/48
48
Functional description
Figure 5. Synchronization example
R5974AD
14/48
The R5974AD features two types of current limit protection; pulse-by-pulse and frequency foldback.
The schematic of the current limitation circuitry for the pulse-by-pulse protection is shown in
Figure 6 . The output power PDMOS transistor is split into two parallel PDMOS transistors.
The smallest one includes a resistor in series, R
SENSE
R
SENSE
. The current is sensed through
and, if it reaches the threshold, the mirror becomes unbalanced and the PDMOS is switched off until the next falling edge of the internal clock pulse. Due to this reduction of the
ON time, the output voltage decreases. As the minimum switch-on time necessary to sense the current, in order to avoid a false overcurrent signal, is too short to obtain a sufficiently low duty cycle at 500 kHz (see
Section 8.4 on page 31 ), the output current in strong
overcurrent or short-circuit conditions may not be properly limited. For this reason, the switching frequency is also reduced, therefore keeping the inductor current under its maximum threshold. The frequency shifter (
Figure 4 ) functions based on the feedback
voltage. As the feedback voltage decreases (due to the reduced duty cycle), the switching frequency decreases also.
DocID027026 Rev 1
R5974AD
9&&
'5,9(5
,
2))
Figure 6. Current limitation circuitry
56(16(
$ $
287
$$
,
3:0
Functional description
,
127
57+
,
/
$0Y
The voltage error amplifier is the core of the loop regulation. It is a transconductance operational amplifier whose non inverting input is connected to the internal voltage reference (1.235 V), while the inverting input (FB) is connected to the external divider or directly to the output voltage. The output (COMP) is connected to the external compensation network. The uncompensated error amplifier has the following characteristics:
Table 5. Uncompensated error amplifier characteristics
Description Values
Transconductance
Low frequency gain
Minimum sink/source voltage
Output voltage swing
Input bias current
2300 µS
65 dB
1500 µA/300 µA
0.4 V/3.65 V
2.5 µA
The error amplifier output is compared to the oscillator sawtooth to perform PWM control.
DocID027026 Rev 1 15/48
48
Functional description
5.6 PWM comparator and power stage
R5974AD
This block compares the oscillator sawtooth and the error amplifier output signals to generate the PWM signal for the driving stage.
The power stage is a highly critical block, as it functions to guarantee a correct turn-on and turn-off of the PDMOS. The turn-on of the power element, or more accurately, the rise time of the current at turn-on, is a very critical parameter. At the first approach, it appears that the faster the rise time, the lower the turn-on losses.
However, there is a limit introduced by the recovery time of the recirculation diode.
In fact, when the current of the power element is equal to the inductor current, the diode turns off and the drain of the power is able to go high. But, during its recovery time, the diode can be considered a high value capacitor and this produces a very high peak current, responsible for numerous problems:
Spikes on the device supply voltage that cause oscillations (and therefore noise) due to the board parasites.
Turn-on overcurrent leads to a decrease in the efficiency and system reliability.
Major EMI problems.
Shorter free-wheeling diode life.
The fall time of the current during turn-off is also critical, as it produces voltage spikes (due to the parasitic elements of the board) that increase the voltage drop across the PDMOS.
In order to minimize these problems, a new driving circuit topology has been used (the block diagram is shown in
Figure 7 ). The basic idea is to change the current levels used to turn
the power switch on and off, based on the PDMOS and the gate clamp status.
This circuitry allows the power switch to be turned off and on quickly and addresses the free-wheeling diode recovery time problem. The gate clamp is necessary to ensure that V
GS of the internal switch does not go higher than V
GSmax
. The on/off control block protects against any cross conduction between the supply line and ground.
16/48 DocID027026 Rev 1
R5974AD Functional description
Figure 7. Driving circuitry
9&&
9JVPD[
&/$03 *$7(
6723
'5,9(
212))
&21752/
'5$,1
2))
21
,
2))
'5$,1
3'026
/
(65
&
,
21
9287
,
/2$'
$0Y
The inhibit feature is used to put the device in standby mode. With the INH pin higher than
2.2 V, the device is disabled and the power consumption is reduced to less than 100 µA.
With the INH pin lower than 0.8 V, the device is enabled. If the INH pin is left floating, an internal pull-up ensures that the voltage at the pin reaches the inhibit threshold and the device is disabled. The pin is also V
CC
compatible.
The shutdown block generates a signal that turns off the power stage if the temperature of the chip goes higher than a fixed internal threshold (150 ± 10 °C). The sensing element of the chip is very close to the PDMOS area, ensuring fast and accurate temperature detection.
A hysteresis of approximately 20 °C keeps the device from turning on and off continuously.
DocID027026 Rev 1 17/48
48
Additional features and protection
6 Additional features and protection
R5974AD
6.2
If the feedback is disconnected, the duty cycle increases towards the maximum allowed value, bringing the output voltage close to the input supply. This condition could destroy the load.
To avoid this hazardous condition, the device is turned off if the feedback pin is left floating.
Output overvoltage protection
Overvoltage protection, or OVP, is achieved by using an internal comparator connected to the feedback, which turns off the power stage when the OVP threshold is reached. This threshold is typically 30% higher than the feedback voltage.
When a voltage divider is required to adjust the output voltage (
OVP intervention is set at:
Equation 1
V
OVP
= 1.3
R
1
+
R
2
R
2
V
FB where R
1
is the resistor connected between the output voltage and the feedback pin, and R
2 is between the feedback pin and ground.
Due to the fact that the internal power is a PDMOS, no bootstrap capacitor is required and so the device works properly even with no load at the output. In this case it works in burst mode, with a random burst repetition rate.
18/48 DocID027026 Rev 1
R5974AD
7 Closing the loop
Figure 8. Block diagram of the loop
Closing the loop
7.1
$0Y
Error amplifier and compensation network
The output LC filter of a step-down converter contributes with 180-degree phase shift in the control loop. For this reason a compensation network between the COMP pin and
GROUND is added. The simplest compensation network, together with the equivalent circuit of the error amplifier, are shown in
C
and C
C
introduce a pole and a zero in the open loop gain. CP does not significantly affect system stability but it is useful to reduce the noise of the COMP pin.
The transfer function of the error amplifier and its compensation network is:
Equation 2
A
0 s =
2
R
0
p
R c
A
V0
1 s R c
C c
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------s C
0
+ C C c
+ s R
0
C c
+ R
0
C
0
+ C p
+ R c
C c
+ 1 where A vo
= G m
· R o
DocID027026 Rev 1 19/48
48
Closing the loop R5974AD
Figure 9. Error amplifier equivalent circuit and compensation network
($
&203
)%
5
&
&
&
&
3
9 ǻ 9
5
0 ȍ
&
S)
5
&
&
&
&
3
*
P ǻ 9
$0Y
The poles of this transfer function are (if C c
>> C
0
+C
P
):
Equation 3
F
P1
=
2 R
0
C c
Equation 4
F
P2
=
2 R c
1
C
0
+ p
whereas the zero is defined as:
Equation 5
F
Z1
=
c
c
F
P1
is the low frequency which sets the bandwidth, while the zero F
Z1 the frequency of the double pole of the LC filter (see below). F
P2 frequency.
is usually put near to
is usually at a very high
20/48 DocID027026 Rev 1
R5974AD Closing the loop
The transfer function of the LC filter is given by:
Equation 6
A
LC
=
R s
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------s
2
OUT
LOAD
+ s ESR C
OUT
R
LOAD
+ L + R
LOAD where R
LOAD
is defined as the ratio between V
OUT
and I
OUT
.
If R
LOAD
>>ESR, the previous expression of A
LC
can be simplified and becomes:
Equation 7
A
LC
=
1 ESR C
s
2
+
OUT
s
-----------------------------------------------------------------------------------------
L C
OUT
ESR C
OUT
+
The zero of this transfer function is given by:
Equation 8
F
O
=
2
1
OUT
F
0
is the zero introduced by the ESR of the output capacitor and it is very important to increase the phase margin of the loop.
The poles of the transfer function can be calculated through the following expression:
Equation 9
=
–
2
–
In the denominator of A
LC
the typical second order system equation can be recognized:
Equation 10 s
2
+ 2 n
s +
2 n
If the damping coefficient is very close to zero, the roots of the equation become a double root whose value is n
.
Similarly for A
LC
the poles can usually be defined as a double pole whose value is:
Equation 11
F
PLC
=
2
OUT
DocID027026 Rev 1 21/48
48
Closing the loop R5974AD
The PWM gain is given by the following formula:
Equation 12
G
PWM
=
V cc
OSCMAX
– V
OSCMIN
where V
OSCMAX
is the maximum value of a sawtooth waveform and V
OSCMIN
is the minimum value. A voltage feed-forward is implemented to ensure a constant GPWM. This is obtained by generating a sawtooth waveform directly proportional to the input voltage V
CC
.
Equation 13
V
OSCMAX
– V
OSCMIN
=
CC where K is equal to 0.038. Therefore the PWM gain is also equal to:
Equation 14
G
PWM
=
1
K
= const
This means that even if the input voltage changes, the error amplifier does not change its value to keep the loop in regulation, therefore ensuring a better line regulation and line transient response.
In summary, the open loop gain can be expressed as:
Equation 15
G s = G
PWM
R
1
R
+ R
2
A
O s A
LC
Example:
Considering R
C
= 4.7 k , C
C
= 22 nF and C
P
= 150 pF, the poles and zeroes of A
0
are:
F
P1
= 9 Hz
F
P2
= 220 kHz
F
Z1
= 1.6 kHz
If L = 12 µH, C
OUT
= 330 µF and ESR = 25 m , the poles and zeroes of A
LC
become:
F
PLC
= 2.5 kHz
F
ZESR
= 20 kHz
F
0
= 44 kHz
Finally R
1
= 5.6 k and R
2
= 3.3 k .
22/48 DocID027026 Rev 1
R5974AD Closing the loop
The gain and phase bode diagrams are plotted respectively in
and
Figure 10. Module plot
Figure 11. Phase plot
The cut-off frequency and the phase margin are:
Equation 16
F
C
= 38kHz Phase margin = 52°
DocID027026 Rev 1 23/48
48
Application information
Figure 12. Application schematic
R5974AD
24/48
Input capacitor
The input capacitor must be able to support the maximum input operating voltage and the maximum RMS input current.
As step-down converters draw current from the input in pulses, the input current is squared and the height of each pulse is equal to the output current. The input capacitor has to absorb all this switching current, which can be up to the load current divided by two (worst case, with duty cycle of 50%). For this reason, the quality of these capacitors must be very high to minimize the power dissipation generated by the internal ESR, thereby improving system reliability and efficiency. The critical parameter is usually the RMS current rating, which must be higher than the RMS input current. The maximum RMS input current (flowing through the input capacitor) is:
Equation 17
I
RMS
= I
O
D –
2
--------------+
D
2
-------
2 where is the expected system efficiency, D is the duty cycle and I
O
is the output DC current. This function reaches its maximum value at D = 0.5 and the equivalent RMS current is equal to I
O
divided by 2 (considering = 1). The maximum and minimum duty cycles are:
Equation 18
D
MAX
=
V
V
INMIN
+
–
V
V
F
SW
DocID027026 Rev 1
R5974AD Application information and
Equation 19
D
MIN
=
V
V
INMAX
+
–
V
V
SW where V
F
is the freewheeling diode forward voltage and V
SW internal PDMOS. Considering the range D
MIN
to D
MAX
the voltage drop across the
, it is possible to determine the max.
IRMS going through the input capacitor. Capacitors that can be considered are:
Electrolytic capacitors
These are widely used due to their low price and their availability in a wide range of
RMS current ratings.
The only drawback is that, considering ripple current rating requirements, they are physically larger than other capacitors.
Ceramic capacitors
If available for the required value and voltage rating, these capacitors usually have a higher RMS current rating for a given physical dimension (due to very low ESR).
The drawback is the considerably high cost.
Tantalum capacitors
Very good, small tantalum capacitors with very low ESR are becoming more available.
However, they can occasionally burn if subjected to very high current during charge
Therefore, it is better to avoid this type of capacitor for the input filter of the device.
They can, however, be subjected to high surge current when connected to the power supply
Manufacturer
Table 6. List of ceramic capacitors for the R5974AD
Series Capacitor value ( µ F) Rated (V)
TAIYO YUDEN
MURATA
UMK325BJ106MM-T
GRM42-2 X7R 475K 50
10
4.7
50
50
Output capacitor
The output capacitor is very important to meet the output voltage ripple requirement.
Using a small inductor value is useful to reduce the size of the choke but it increases the current ripple. So, to reduce the output voltage ripple, a low ESR capacitor is required. Nevertheless, the ESR of the output capacitor introduces a zero in the open loop gain, which helps to increase the phase margin of the system. If the zero goes to a very high frequency, its effect is negligible. For this reason, ceramic capacitors and very low ESR capacitors in general should be avoided.
Tantalum and electrolytic capacitors are usually a good choice for this purpose. A list of
some tantalum capacitor manufacturers is provided in Table 7 .
DocID027026 Rev 1 25/48
48
Application information R5974AD
Manufacturer
Sanyo POSCAP
(1)
AVX
KEMET
Sprague
Table 7. Output capacitor selection
Series
TAE
TV
TPS
T494/5
595D
Cap. value ( µ F) Rated voltage (V)
47 to 680
68 to 330
100 to 470
100 to 470
220 to 390
2.5 to 10
4 to 6.3
4 to 35
4 to 20
4 to 20
ESR (m )
25 to 35
25 to 40
50 to 200
30 to 200
160 to 650
1. POSCAP capacitors have some characteristics which are very similar to tantalum.
Inductor
The inductor value is very important as it fixes the ripple current flowing through the output capacitor. The ripple current is usually fixed at 20 - 40% of I
Omax
0.6 - 1.2 A with I
Omax following formula:
, which is
= 3 A. The approximate inductor value is obtained using the
Equation 20
L =
V –
V
I
T
ON where T
V
OUT
ON
is the ON time of the internal switch, given by D · T. For example, with
= 3.3 V, V
IN
= 12 V and I
O
= 0.9 A, the inductor value is about 12 µH.
The peak current through the inductor is given by:
Equation 21
I
PK
= I
O
+
I
2 and it can be seen that, if the inductor value decreases, the peak current (which must be lower than the current limit of the device) increases. So, when the peak current is fixed, a higher inductor value allows a higher value for the output current. In
, some inductor manufacturers are listed.
Manufacturer
Coilcraft
Coilcraft
Wurth Elektronik
Table 8. Inductor selection
Series Inductor value ( µ H) Saturation current (A)
DO3316T
MSS1260T
WE-PD L
5.6 to 12
5.6 to 15
4.7 to 27
3.5 to 4.7
3.5 to 8
3.55 to 6
26/48
The layout of the switching DC-DC converters is very important to minimize noise and interference. Power-generating portions of the layout are the main cause of noise and so high switching current loop areas should be kept as small as possible and lead lengths as short as possible.
DocID027026 Rev 1
R5974AD Application information
High impedance paths (in particular the feedback connections) are susceptible to interference, so they should be as far as possible from the high current paths. A layout
example is provided in Figure 13 .
The input and output loops are minimized to avoid radiation and high frequency resonance problems. The feedback pin connections to the external divider are very close to the device to avoid pick-up noise. Another important issue is the ground plane of the board. Since the package has an exposed pad, it is very important to connect it to an extended ground plane in order to reduce the thermal resistance junction to ambient.
Figure 13. Layout example
8.3.1 Thermal resistance R
THJ-A
R
THJ-A
is the equivalent static thermal resistance junction to ambient of the device; it can be calculated as the parallel of many paths of heat conduction from the junction to the ambient.
For this device, the path through the exposed pad is the one conducting the largest amount of heat. The static R
THJ-A
measured on the application is about 40 °C/W.
The junction temperature of device is:
Equation 22
T
J
= T
A
+ R thJA
P
TOT
DocID027026 Rev 1 27/48
48
Application information R5974AD
The dissipated power of the device is tied to three different sources:
Conduction losses due to the not insignificant R
DS(on)
, which are equal to:
Equation 23
P
ON
= R
DS on
I
OUT
2
D where D is the duty cycle of the application. Note that the duty cycle is theoretically given by the ratio between V
OUT
and V
IN
, but in practice it is substantially higher than this value to compensate for the losses in the overall application. For this reason, the switching losses related to the R
DS(on)
increases compared to an ideal case.
Switching losses due to turning on and off. These are derived using the following equation:
Equation 24
P
SW
= V
IN
I
OUT
T +
2
T
OFF
F
SW
= V
IN
I
OUT
T
SW
F
SW where T
RISE
and T
FALL represent the switching times of the power element that cause the switching losses when driving an inductive load (see
). T
SW
is the equivalent switching time.
Figure 14. Switching losses
28/48
Quiescent current losses.
Equation 25 where I
Q
is the quiescent current.
P
Q
= V
IN
I
Q
DocID027026 Rev 1
R5974AD
8.3.2
Application information
Example:
– V
IN
= 12 V
– V
OUT
= 3.3 V
– I
OUT
= 2A
R
DS(on)
has a typical value of 0.25 at 25 °C and increases up to a maximum value of 0.5 at
150 °C. We can consider a value of 0.4 .
T
SW
is approximately 70 ns.
I
Q
has a typical value of 5 mA at V
IN
= 12 V.
The overall losses are:
Equation 26
P
TOT
=
= R
0.4 2
2
DSON
+
I
OUT
2
+
IN
– 9
I
OUT
3
T
SW
+
F
SW
+ V
IN
– 3
I
Q
=
1.38W
The junction temperature of the device is:
Equation 27
T
J
= T
A
+ R thJA
P
TOT
Equation 28
T
J
= + C
Thermal impedance Z
THJ-A
(t)
The thermal impedance of the system, considered as the device in the HSO8 package soldered on the application board, takes on an important rule when the maximum output power is limited by the static thermal performance and not by the electrical performance of the device. Therefore, the embedded power elements could manage a higher current but the system is already taking away the maximum power generated by the internal losses.
In case the output power increases, the thermal shutdown is triggered because the junction temperature triggers the designed thermal shutdown threshold.
The R
TH
is a static parameter of the package; it sets the maximum power loss which can be generated from the system given the operation conditions.
If we suppose, as an example, T
A
= 80 C, 140 before triggering the thermal shutdown and R
TH
C is the maximum operating temperature
= 40 C/W, therefore, the maximum power loss achievable with the thermal performance of the system is:
Equation 29
P
MAX DC
=
T
R
TH
=
T
R
–
TH
T
-------------------------------------=
60
40
= 1.5W
represents the estimation of power losses for different output voltages at
V
IN
= 5 V and T
AMB
= 80 C. The calculations are performed considering the R power element equal to 0.4 A
DS(on)
of the
DocID027026 Rev 1 29/48
48
Application information
Figure 15. Power losses estimation (V
IN
= 5 V, f
SW
= 500 kHz)
R5974AD
The red trace represents the maximum power which can be taken away, as calculated above, whilst the other traces are the total internal losses for different output voltage.
The embedded conduction losses are proportional to the duty cycle required for the conversion. Assuming the input voltage constant, the switching losses are proportional to the output current while the quiescent losses can be considered as constant.
As a consequence, in Figure 15 , the maximum power loss is for V
OUT
= 3.3 V, where the system can manage a continuous output current up to 1.8 A. The device could deliver a continuous output current up to 2 A to the load, however, the maximum power loss of
1.5 W is reached with an output current of 1.8 A, so the maximum output power is derated if
T
AMB
= 80 C.
plots the power losses for V
IN
= 12 V and main output rails.
Figure 16. Power losses estimation (V
IN
= 12 V, f
SW
= 500 kHz)
30/48
At T
AMB
= 80 C and V
IN
= 12 V, the device is thermally limited only when V
OUT
= 5 V (see
).
As a consequence, the calculation of the internal power losses must be done for each specific operating condition given by the final application.
DocID027026 Rev 1
R5974AD Application information
In applications where the current to the output is pulsed, the thermal impedance should be considered instead of the thermal resistance.
The thermal impedance of the system could be much lower than the thermal resistance, which is a static parameter. As a consequence, the maximum power losses can be higher than 1.5 W if a pulsed output power is requested from the load:
Equation 30
P
MAX
=
T
TH t
=
T
J MAX
Z
– T
--------------------------------------
TH t
AMB
Therefore, depending on the pulse duration and its frequency, the maximum output current can be delivered to the load.
The characterization of the thermal impedance is strictly dependent on the layout of the board. In
the measurement of the thermal impedance of the demonstration board of the R5974AD is provided.
Figure 17. Measurement of the thermal impedance of the demonstration board
As can be seen, for example, for load pulses with a duration of 1 second, the actual thermal impedance is lower than 20 C/W. This means that, for short pulses, the device can deliver a higher output current value.
In overcurrent protection mode, when the peak current reaches the current limit, the device reduces the T
ON
down to its minimum value (approximately 250 nsec) and the switching frequency to approximately one third of its nominal value even when synchronized to an
external signal (see Section 5.4: Current protection on page 14
). In these conditions, the duty cycle is strongly reduced and, in most applications, this is enough to limit the current to
I
LIM
. In any event, in case of heavy short-circuit at the output (V
O the application conditions (V
CC
= 0 V) and depending on
value and parasitic effect of external components), the
DocID027026 Rev 1 31/48
48
Application information R5974AD current peak could reach values higher than I
LIM
. This can be understood considering the inductor current ripple during the ON and OFF phases:
On phase
Equation 31
I
L TON
=
V – V out
– DCR
L
+ R
DS(on)
I
T
ON
Off phase
Equation 32
I
L TOFF
=
– V
D
+ V
L
+ DCR I
T
OFF
where V
D
is the voltage drop across the diode, DCR
L
is the series resistance of the inductor.
In short-circuit conditions V
OUT
is negligible, so during T
OFF
the voltage across the inductor is very small, as equal to the voltage drop across parasitic components (typically the DCR of the inductor and the V
FW
of the free-wheeling diode) while during T
ON to the inductor is instead maximized as approximately equal to V
IN
.
, the voltage applied
So, Equation 31 and 32 in overcurrent conditions can be simplified to:
Equation 33
I
L TON
=
V
IN
– DCR
L
L
+ R I
T
ON MIN
V
L
250ns considering T
ON
, which has already been reduced to its minimum.
Equation 34
I
L TOFF
=
– V
D
+ V
L
+ DCR I
SW
– V
D
+ V
L
+ DCR
L
I
12 s considering that f
SW
has already been reduced to one third of the nominal.
In case a short-circuit at the output is applied, and V
IN
= 12 V, the inductor current is controlled in most of the applications (see
). When the application must sustain the short-circuit condition for an extended period, the external components (mainly the inductor and diode) must be selected based on this value.
In case the V
IN
is very high, it could occur that the ripple current during T does not compensate the current increase during T
ON example of a power-up phase with V
IN
= V
IN MAX
OFF
( Equation 33 ).
= 36 V where
IL TON
>
( Equation 34 )
IL TOFF
so the current escalates and the balance between Equation 33 and 34 occurs at a current slightly higher than the current limit. This must be taken into account in particular to avoid the risk of an abrupt inductor saturation.
32/48 DocID027026 Rev 1
R5974AD
Figure 18. Short-circuit current V
IN
= 12 V
Application information
Figure 19. Short-circuit current V
IN
= 24 V
DocID027026 Rev 1 33/48
48
Application information
Figure 20. Short-circuit current V
IN
= 36 V
R5974AD
8.5 Positive buck-boost regulator
The device can be used to implement a step-up/down converter with a positive output voltage.
The output voltage is given by:
Equation 35
V
OUT
= V
IN
where the ideal duty cycle D for the buck-boost converter is:
Equation 36
D =
IN
V
OUT
+ V
OUT
However, due to power losses in the passive elements, the real duty cycle is always higher than this. The real value (that can be measured in the application) should be used in the following formulas.
The peak current flowing in the embedded switch is:
Equation 37
I
SW
=
I
LOAD
+
I
2
=
I
--------------+
V
IN
f
SW
34/48 DocID027026 Rev 1
R5974AD Application information while its average current is equal to:
Equation 38
This is due to the fact that the current flowing through the internal power switch is delivered to the output only during the OFF phase.
The switch peak current must be lower than the minimum current limit of the overcurrent
protection (see Table 4 on page 8 for details) while the average current must be lower than
the rated DC current of the device.
As a consequence, the maximum output current is:
Equation 39
I
SW
=
I
LOAD
I
OUT MAX
I
SW MAX
1 D where I
SW MAX
represents the rated current of the device.
The current capability is reduced by the term (1 - D) and so, for example, with a duty cycle of
0.5, and considering an average current through the switch of 2 A, the maximum output current deliverable to the load is 1 A.
below shows the circuit schematic of this topology for a 12 V output voltage and
5 V input.
Figure 21. Positive buck-boost regulator
DocID027026 Rev 1 35/48
48
Application information R5974AD
In
Figure 22 , the schematic circuit for a standard buck-boost topology is shown. The output
voltage is:
Equation 40
V
OUT
= – V
IN
where the ideal duty cycle D for the buck-boost converter is:
Equation 41
D =
V
–
IN
V
–
OUT
V
OUT
The considerations given in
for the real duty cycle are still valid here. Also
Equation 37 to 39 can be used to calculate the maximum output current. So, for example, considering the conversion V
IN
= 12 V to V
OUT
= -5 V, I
LOAD
= 0.5 A:
Equation 42
D =
5
= 0.706
Equation 43
I
SW
=
I
LOAD
=
0.5
= 1.7A
An important point to take into account is that the ground pin of the device is connected to the negative output voltage. Therefore, the device is subjected to a voltage equal to
V
IN
- V
O
, which must be lower than 36 V (the maximum operating input voltage).
Figure 22. Negative buck-boost regulator
36/48 DocID027026 Rev 1
R5974AD
8.7
Application information
Floating boost current generator
The R5974AD does not support a nominal boost conversion as this topology requires a low side switch, however, a floating boost can be useful in applications where the load can be floating. A typical example is a current generator for LEDs driving, as the LED does not require a connection to the ground.
Figure 23. Floating boost topology
$0Y
DocID027026 Rev 1 37/48
48
Application information
Figure 24. 350 mA LED boost current source
R5974AD
38/48 DocID027026 Rev 1
R5974AD Application information
The device is powered from the output voltage so the maximum voltage drop across the
LEDs and resistor sense is 36 V.
The output voltage is given by:
Equation 44
V
OUT
=
V
IN where the ideal duty cycle D for the boost converter is:
Equation 45
D =
V
OUT
V
–
OUT
V
------------------------------
As for positive and inverting buck-boost (see
) the measured real duty cycle must be used to calculate the switch current level.
The peak current flowing in the embedded switch is:
Equation 46
I
SW
=
I
LOAD
+
I
2 while its average current is equal to:
=
I
--------------+
V
IN
f
SW
Equation 47
I
SW
=
I
LOAD
This is due to the fact that the current flowing through the internal power switch is delivered to the output only during the OFF phase.
The switch peak current must be lower than the minimum current limit of the overcurrent
protection (see Table 4 on page 8 for details) while the average current must be lower than
the rated DC current of the device.
As a consequence, the maximum output current is:
Equation 48
I
OUT MAX
I
SW MAX
where I
SW MAX
represents the rated current of the device.
shows a tested circuit to implement a boost current source for high current LED driving (350 mA). To implement a boost conversion the LED string must be composed of a minimum device number having a total voltage drop larger than maximum input voltage.
The input voltage can be either DC or AC thanks to the input bridge rectifier. In the case of a DC voltage source D1, D2, D3, D4, C1, and C2 can be removed from the circuit and 1 F capacitor value can be used for C5.
DocID027026 Rev 1 39/48
48
Application information
See
Section 5.3 on page 12 for details.
Figure 25. Synchronization example
R5974AD
40/48
The R5974AD standard compensation network (please refer to
) introduces a single zero and a low frequency pole in the system bandwidth, so a high ESR output capacitor must be selected to compensate the 180-degree phase shift given by the LC double pole.
The selection of the output capacitor must guarantee that the zero introduced by this component is inside the designed system bandwidth and close to the frequency of the double pole introduced by the LC filter. A general rule for the selection of this compound for the system stability is provided in Equation 49 .
Equation 49 f
Z ESR
=
2
1
f
LC
f
Z ESR
OUT
bandwidth
LC
MLCCs (multiple layer ceramic capacitor) with values in the range of 10 µF - 22 µF and rated voltages in the range of 10 V-25 V are available today at relatively low cost from many manufacturers.
These capacitors have very low ESR values (a few m ) and are therefore occasionally used for the output filter in order to reduce the voltage ripple and the overall size of the application.
However, the zero given by the output capacitor falls outside the designed bandwidth and so the system becomes unstable with the standard compensation network.
shows the type III compensation network stabilizing the system with ceramic capacitors at the output (the optimum components value depends on the application). This configuration introduces two zeroes and a low frequency pole in the designed bandwidth and so guarantees a proper phase margin.
DocID027026 Rev 1
R5974AD
9729
Figure 26. MLCC compensation network circuit
Application information
95()
9&&
6<1&
9287
&203
,1+
)%
(;3$' *1'
VPDOOVLJQDO
SRZHUSODQH
$0Y
DocID027026 Rev 1 41/48
48
Application information R5974AD
8.10 External soft-start network
At startup, the device can quickly increase the current up to the current limit in order to charge the output capacitor. If soft ramp-up of the output voltage is required, an external
soft-start network can be implemented, as shown in Figure 27 . The capacitor C is charged
up to an external reference through R and the BJT clamps the COMP pin.
This clamps the duty cycle, limiting the slew rate of the output voltage.
Figure 27. Soft-start network example
42/48 DocID027026 Rev 1
R5974AD Typical characteristics
Figure 28. Line regulator
9
9 &
&
Figure 29. Shutdown current vs. junction temperature
$0Y
Figure 30. Output voltage vs. junction temperature
$0Y
Figure 31. Junction temperature vs. output current (V
IN
= 5 V)
$0Y
Figure 32. Junction temperature vs. output current (V
IN
= 12 V)
Figure 33. Efficiency vs. output current
(V
IN
= 5 V) ϳϱ͘ϬϬ ϳϬ͘ϬϬ ϲϱ͘ϬϬ
Ϭ͘Ϭ Ϭ͘ϱ ϭ͘Ϭ ϭ͘ϱ Ϯ͘Ϭ
$0Y
DocID027026 Rev 1 43/48
48
Typical characteristics
Figure 34. Efficiency vs. output current (V
IN
= 12 V)
R5974AD ϳϬ͘ϬϬ ϲϱ͘ϬϬ ϲϬ͘ϬϬ
Ϭ͘Ϭ Ϭ͘ϱ ϭ͘Ϭ ϭ͘ϱ Ϯ͘Ϭ sKhdϭ͘ϴs
$0Y
44/48 DocID027026 Rev 1
R5974AD Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions, and product status are available at: www.st.com
.
ECOPACK is an ST trademark.
DocID027026 Rev 1 45/48
48
Package information
Figure 35. HSOP8 package outline
R5974AD
46/48
Symbol
L k ccc e h
E1
E2 c
D
D1
E
A
A1
A2 b
$
0.00
1.25
0.31
0.17
4.80
3
5.80
3.80
2.31
Min.
0.25
0.40
Table 9. HSOP8 package mechanical data
Dimensions (mm) Dimensions (inch)
Typ.
Min.
Typ.
Max.
1.70
0.10
0.00
Max.
0.0669
0.0039
4.90
3.1
6.00
3.90
2.41
1.27
0.51
0.25
5.00
3.2
6.20
4.00
2.51
0.0492
0.0122
0.0067
0.1890
0.118
0.2283
0.1496
0.091
0.1929
0.122
0.095
0.0201
0.0098
0.1969
0.126
0.2441
0.1575
0.099
0.50
0.0098
1.27
0.0157
0 ° (min.), 8 ° (max.)
0.10
0.0197
0.0500
0.0039
DocID027026 Rev 1
R5974AD Ordering information
Order codes
R5974AD
R5974ADTR
Table 10. Ordering information
Package
HSOP8
Packaging
Tube
Tape and reel
Date
10-Oct-2014
Table 11. Document revision history
Revision Changes
1 Initial release.
DocID027026 Rev 1 47/48
48
R5974AD
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2014 STMicroelectronics – All rights reserved
48/48 DocID027026 Rev 1
Download
Public link updated
The public link to your chat has been updated. You may view and manage your chat links after registration here.
Document public link
Advertisement