STMicroelectronics STW81103 Datasheet
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STW81103
Multi-band RF frequency synthesizer with integrated VCOs
Features
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Integer-N frequency synthesizer
Dual differential integrated VCOs with automatic center frequency calibration:
– 2500 - 3050 MHz (direct output)
– 4350 - 5000 MHz (direct output)
– 1250 - 1525 MHz (internal divider by 2)
– 2175 - 2500 MHz (internal divider by 2)
– 625 - 762.5 MHz (internal divider by 4)
– 1087.5 - 1250 MHz (internal divider by 4)
Excellent integrated phase noise
Fast lock time: 150µs
Dual modulus programmable prescaler
(16/17 or 19/20)
2 programmable counters to achieve a feedback division ratio from 256 to 65551
(prescaler 16/17) and from 361 to 77836
(prescaler 19/20).
Programmable reference frequency divider
(10 bits)
Phase frequency comparator and charge pump
Programmable charge pump current
Digital lock detector
Dual digital bus interface: SPI and I
2
C bus (fast mode) with 3 bit programmable address
(1100A
2
A
1
A
0
)
3.3 V power supply
Power down mode (hardware and software)
Small size exposed pad VFQFPN28 package
5 mm x 5 mm x 1.0 mm
Process: BICMOS 0.35 µm SiGe
Applications
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2.5G and 3G Cellular infrastructure equipment
CATV equipment
Instrumentation and test equipment
Other wireless communication systems
Description
The STMicroelectronics STW81103 is an integrated RF synthesizer with voltage controlled oscillators (VCOs). Showing high performance, high integration, low power, and multi-band performances, STW81103 is a low cost one chip alternative to discrete PLL and VCOs solutions.
STW81103 includes an Integer-N frequency synthesizer and two fully integrated VCOs featuring low phase noise performance and a noise floor of -155dBc/Hz. The combination of wide frequency range VCOs (thanks to centerfrequency calibration over 32 sub-bands) and multiple output options (direct output, divided by 2 or divided by 4) allows to cover the
625 MHz-762.5 MHz, the 1087.5 MHz-1525 MHz, the 2175 MHz-3050 MHz and the
4350 MHz-5000 MHz bands.
The STW81103 is designed with
STMicroelectronics advanced 0.35 µm SiGe process.
March 2008 Rev 3 1/53 www.st.com
1
Contents
Contents
2/53
STW81103
Block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Phase frequency detector (PFD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
VCO frequency calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
VCO voltage amplitude control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Output buffer control mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
STW81103
Contents
START and STOP conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Byte format and acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Single-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Current byte address read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
VCO calibration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
VCO calibration auto-restart feature . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
VCO calibration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
VCO calibration auto-restart feature . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3/53
List of tables
List of tables
STW81103
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4/53
STW81103
List of figures
List of figures
VCO A (direct output) closed loop phase noise at 2.775 GHz
VCO B (direct output) closed loop phase noise at 4.675 GHz
VCO A (div. by 2 output) closed loop phase noise at 1.3876 GHz
VCO B (div. by 2 output) closed loop phase noise at 2.3376 GHz
VCO A (div. by 4 output) closed loop phase noise at 693.8 MHz
VCO B (div. by 4 output) closed loop phase noise at 1168.8 MHz
Settling time (final frequency=2.4 GHz; FPFD=400 kHz; ICP=2.5 mA) . . . . . . . . . . . . . . . 17
Differential/single-ended output network (MATCH_LC_LUMP_4G_DIFF.dsn) . . . . . . . . . 41
LC lumped balun and matching network (MATCH_LC_LUMP_4G.dsn) . . . . . . . . . . . . . . 42
Evaluation board (EVB4G) matching network (MATCH_EVB4G.dsn) . . . . . . . . . . . . . . . . 43
Differential/single-ended output network (MATCH_LC_LUMP_2G_DIFF.dsn) . . . . . . . . . 43
LC lumped balun for divided by 2 output (MATCH_LC_LUMP_2G.dsn) . . . . . . . . . . . . . . 44
Evaluation board (EVB2G) matching network (MATCH_EVB2G.dsn) . . . . . . . . . . . . . . . . 44
LC lumped balun for divided by 4 output (MATCH_LC_LUMP_1G.dsn) . . . . . . . . . . . . . . 45
Evaluation board (EVB1G) matching network (MATCH_EVB1G.dsn) . . . . . . . . . . . . . . . . 46
Application diagram with external VCO (LO output from STW81103) . . . . . . . . . . . . . . . . 49
5/53
Block diagram and pin configuration
1 Block diagram and pin configuration
Figure 1.
Block diagram
STW81103
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6/53
STW81103
Figure 2.
Pin connection (top view)
Block diagram and pin configuration
VDD_VCOA
VDD_DIV2
VDD_OUTBUF
OUTBUFP
OUTBUFN
VDD_DIV4
VDD_VCOB
QFN 2 8
DBU S _ S EL
VDD_BUFVCO
EXTVCO_INP
EXTVCO_INN
VDD_PLL
REF_CLK
TE S T2
7
8
5
6
9
3
4
1
2
Table 1.
Pin No
Pin description
Name Description
VDD_VCOA
VDD_DIV2
VCO A power supply
Divider by 2 power supply
VDD_OUTBUF Output buffer power supply
OUTBUFP LO buffer positive output
OUTBUFN
VDD_DIV4
VDD_VCOB
VDD_ESD
VCTRL
LO buffer negative output
Divider by 4 power supply
VCO B power supply
ESD positive rail power supply
VCO control voltage
Observation
Open collector
Open collector
7/53
Block diagram and pin configuration
Table 1.
Pin No
10 ICP
Pin description (continued)
Name Description
11
12
REXT
VDD_CP
PLL charge pump output
External resistance connection for PLL charge pump
Power supply for charge pump
13 TEST1 Test input 1
STW81103
Observation
14 LOCK_DET Lock detector
For test purposes only; must be connected to
GND
CMOS output
(I
OUT
=4mA)
For test purposes only; must be connected to
GND
15
16
17
TEST2
REF_CLK
VDD_PLL
Test input 2
Reference clock input
PLL digital power supply
18 EXTVCO_INN External VCO negative input
19 EXTVCO_INP External VCO positive input
20
21
22
23
24
VDD_BUFVCO VCO buffer power supply
DBUS_SEL
VDD_DBUS
EXT_PD
Digital Bus Interface select
SPI and I
2
C bus power supply
Power down hardware
‘0’ device ON; ‘1’ device OFF
SDA/DATA I2CBUS/SPI data line
25
26
SCL/CLK
ADD0/LOAD
27 ADD1
I2CBUS/SPI clock line
I2CBUS address select pin/ SPI load line
I2CBUS address select pin
28 ADD2 I2CBUS address select pin
For test purposes only; must be connected to
GND
For test purposes only; must be connected to
GND
CMOS input
CMOS input
CMOS Bidir Schmitt triggered (I
OUT
=4mA)
CMOS input Schmitt triggered
CMOS input
CMOS input; must be connected to GND in SPI mode
CMOS input; must be connected to GND in SPI mode
8/53
STW81103 Electrical specifications
Table 2.
Symbol
Absolute maximum ratings
Parameter
AV
CC
Analog supply voltage
DV
CC
Digital supply voltage
T stg
Storage temperature
ESD
Electrical static discharge
- HBM
(1)
- CDM-JEDEC standard
- MM
1.
The maximum rating of the ESD protection circuitry on pin 4 and pin 5 is 800 V.
Values
0 to 4.6
0 to 4.6
+150
4
1.5
0.2
Unit
V
V
° C kV
Table 3.
Symbol
Operating conditions
(1)
Parameter Test conditions
I
I
AV
T
T
R
R
R j
CC
DV
CC
VDD1
VDD2 amb th j-a th j-b th j-c
Analog supply voltage
Digital supply voltage
V
DD1
current consumption
V
DD2
current consumption
Operating ambient temperature
Maximum junction temperature
Junction to ambient package thermal resistance
Junction to board package thermal resistance
Junction to case package thermal resistance
Multilayer JEDEC board
Multilayer JEDEC board
Multilayer JEDEC board
1.
Refer to
Figure 36: Typical application diagram .
Min.
3.0
3.0
-40
44
26.3
6.3
Typ.
3.3
3.3
90
12
Max.
3.6
3.6
85
125
Units
V
V mA mA
° C
° C
° C/W
° C/W
° C/W
9/53
Electrical specifications STW81103
Table 4.
Symbol
V il
V ih
V hyst
V ol
V oh
Digital logic levels
Parameter
Low-level input voltage
High-level input voltage
Schmitt trigger hysteresis
Low-level output voltage
High-level output voltage
Test conditions Min.
0.8*Vdd
0.8
0.85*Vdd
Typ.
Max.
0.2*Vdd
0.4
Units
V
V
V
V
V
All electrical specifications are intended for a 3.3 V supply voltage.
Table 5.
Symbol
l
Electrical specifications
Parameter Condition
Output frequency range
F
F
OUTA
OUTB
Direct output
Output frequency range with
VCOA
Divider by 2
Divider by 4
Direct output
Output frequency range with
VCOB
Divider by 2
Divider by 4
VCO dividers
N VCO divider ratio
Prescaler 16/17
Prescaler 19/20
Reference clock and phase frequency detector
F
F ref
R
PFD
Reference input frequency
Reference input sensitivity
(1)
Reference divider ratio
PFD input frequency
Prescaler 16/17
F
STEP
Frequency step
(2)
Prescaler 19/20
Min.
2500
1250
625
4350
2175
1087.5
256
361
10
0.35
2
F
OUT
/
65551
F
OUT
/
77836
Typ.
1
Max.
65551
77836
3050
1525
762.5
5000
2500
1250
Unit
200
1.5
1023
16
F
OUT
/
256
F
OUT
/
361
MHz
Vpeak
MHz
Hz
Hz
MHz
MHz
MHz
MHz
MHz
MHz
10/53
STW81103
Table 5.
Symbol
Electrical specifications (continued)
Parameter
Charge pump
I
CP
ICP sink/source
(3)
V
OCP
Output voltage compliance range
Condition
3-bit programmable
Spurious
(4)
Direct output (F
PFD
=200 kHz)
Divider by 2 (F
PFD
=400 kHz)
Divider by 4 (F
PFD
=800 kHz)
VCOs
K
VCOA
K
VCOB
Δ T
LK
VCOA sensitivity
VCOB sensitivity
Lower frequency range
Intermediate frequency range
Higher frequency range
Lower frequency range
Intermediate frequency range
Higher frequency range
VCO A
VCO B
V
CTRL
Maximum temperature variation for continuous lock
(5) (6)
VCOB pushing
VCO control voltage
LO harmonic spurious
I
VCOA
I
VCOB
VCOA current consumption
VCOB current consumption
F
VCO
=2.8 GHz; amplitude[11]
F
VCO
=2.8 GHz; amplitude[00]
F
VCO
=4.7 GHz; amplitude[11]
F
VCO
=4.7 GHz; amplitude[00]
I
VCOBUF
I
DIV2
I
DIV4
VCO buffer consumption
Divider by 2 consumption
Divider by 4 consumption
LO output buffer
P
LO
R
L
Output level
Return loss
I
OUTBUF
Current consumption
Matched to 50 ohms
DIV4 Buff
DIV2 Buff
Direct output
Min.
0.4
0.4
60
85
125
45
60
85
45
95
Electrical specifications
Typ.
Max.
Unit
4
15
13
15
17
14
30
16
24
65
80
105
65
80
100
0
15
26
23
39
-76
-82
-88
5
V dd
-0.3
mA
V dBc dBc dBc
7
21
3
-20
85
105
145
85
100
130
°C
MHz/V
MHz/V
V dBc mA mA mA mA mA mA mA
MHz/V
MHz/V
MHz/V
MHz/V
MHz/V
MHz/V
°C dBm dB mA mA mA
11/53
Electrical specifications STW81103
Table 5.
Symbol
Electrical specifications (continued)
Parameter Condition Min.
Typ.
Max.
Unit
External VCO
Frequency range
Input level
Current consumption VCO internal buffer
0.625
-10
28
5.0
+6
GHz dBm mA
PLL miscellaneous t
I
PLL lock
Current consumption
Lockup time
Input buffer, prescaler, digital dividers, misc.
25 kHz PLL bandwidth; within
1 ppm of frequency error
12
150 mA
μ s
1.
In order to achieve best phase noise performance 1 V peak level is suggested.
2.
The frequency step is related to the PFD input frequency as follows:
- F step
- F step
- F step
= F
PFD
= F
PFD
= F
PFD
for direct output
/2 for divided by 2 output
/4 for divided by 4 output
3.
See relationship between ICP and REXT in
4.
The level of the spurs may change depending on PFD frequency, charge pump current, selected channel and PLL loop
BW.
5.
Guaranteed by design and specification.
6.
When setting a specified output frequency, the VCO calibration procedure must be run in order to select the best sub-range for the VCO covering the desired frequency. Once programmed at the initial temperature T temperature range (-40
°
C to +85
°
C), the synthesizer is able to maintain the lock status only if the temperature drift (in either direction) is within the limit specified by
If higher
Δ
T are required the
Δ
T
0
LK
, provided that the final temperature T
1
is still inside the nominal range.
”VCO calibration auto-restart“
inside the operating
feature can be enabled, thus allowing to re-start the VCO calibration procedure automatically when the part loose the lock condition (trigger on lock detector signal).
7.
Frequency jump from 2250 to 2400 MHz; it includes the time required by the VCO calibration procedure (7 F
PFD
F
PFD
=400 kHz).
cycles with
12/53
STW81103 Electrical specifications
2.5 Phase noise specification
Table 6.
Phase noise specification
(1)
Parameter Test conditions
In-band phase noise floor – closed loop
(2)
Normalized inband phase noise floor
Inband phase noise floor direct output
Inband phase noise floor divider by 2
Inband phase noise floor divider by 4
ICP=4 mA, PLL BW=50 kHz; including reference clock contribution
PLL integrated phase noise – direct output
Min.
Typ.
-222
Max.
Unit dBc/Hz
-222+20log(N)+10log(F
PFD
) dBc/Hz
-228+20log(N)+10log(F
PFD
) dBc/Hz
-234+20log(N)+10log(F
PFD
) dBc/Hz
-34.6
dBc
Integrated phase noise
100 Hz to 40 MHz
F
OUT
=4.675 GHz,
F
PFD
=200 kHz, F
STEP
=200 kHz,
PLL BW = 15 kHz, ICP=3 mA 1.5
° rms
PLL integrated phase noise – divider by 2
Integrated phase noise
100 Hz to 40 MHz
F
OUT
=2.3376 GHz,
F
PFD
=400 kHz, F
STEP
=200 kHz,
PLL BW=25 kHz, ICP=2 mA
PLL integrated phase noise – divider by 4
Integrated phase noise
100 Hz to 40 MHz
F
OUT
=1.1688 GHz,
F
PFD
=800 kHz, F
STEP
=200 kHz,
PLL BW=35 kHz, ICP=1.5 mA
VCO A direct (2500 MHz-3050 MHz) – open loop
(3)
Phase noise @ 1 kHz
Phase noise @ 10 kHz
Phase noise @ 100 kHz
Phase noise @ 1 MHz
Phase noise @ 10 MHz
Phase noise @ 40 MHz
VCO B direct (4350 MHz-5000 MHz) – open loop
(3)
Phase noise @ 1 kHz
Phase noise @ 10 kHz
Phase noise @ 100 kHz
Phase noise @ 1 MHz
Phase noise @ 10 MHz
Phase noise @ 40 MHz
-42.6
0.6
-49.5
0.27
-54
-82
-105
-127
-147
-157
-59
-87
-109
-131
-151
-161 dBc
° rms dBc
° rms dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
13/53
Electrical specifications STW81103
Table 6.
Phase noise specification
(1)
(continued)
Parameter Test conditions
VCO A with divider by 2 (1250 MHz-1525 MHz) – open loop
(3)
Phase noise @ 1 kHz
Phase noise @ 10 kHz
Phase noise @ 100 kHz
Phase noise @ 1 MHz
Phase noise @ 10 MHz
Phase noise floor @ 40 MHz
VCO B with divider by 2 (2175 MHz-2500 MHz) – open loop
(3)
Phase noise @ 1 kHz
Phase noise @ 10 kHz
Phase noise @ 100 kHz
Phase noise @ 1 MHz
Phase noise @ 10 MHz
Phase noise floor @ 40 MHz
VCO A with divider by 4 (625 MHz-762.5 MHz) – open loop
(3)
Phase noise @ 1 kHz
Phase noise @ 10 kHz
Phase noise @ 100 kHz
Phase noise @ 1 MHz
Phase noise @ 10 MHz
Phase noise floor @ 40 MHz
VCO B with divider by 4 (1087.5 MHz-1250 MHz) – open loop
(3)
Phase noise @ 1 kHz
Phase noise @ 10 kHz
Phase noise @ 100 kHz
Phase noise @ 1 MHz
Phase noise @ 10 MHz
Phase noise floor @ 40 MHz
Min.
Typ.
-71
-99
-121
-142
-154
-155
-60
-88
-111
-132
-150
-154
-65
-93
-115
-137
-153
-155
-66
-94
-117
-138
-153
-154
Max.
Unit dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
1.
Phase Noise SSB. VCO amplitude setting to value [11]. All closed-loop performances are specified using a reference clock signal at 76.8 MHz with a phase noise of -135 dBc/Hz @1 kHz offset, -145dBc/Hz @10kHz offset and -149.5 dBc/Hz of noise floor.
2.
Normalized PN = Measured PN – 20log(N) – 10log(F
PFD comparison frequency at the PFD input.
), where N is the VCO divider ratio (N=B*P+A) and F
PFD
is the
3.
Typical phase noise at centre band frequency.
An evaluation kit is available upon request, including a powerful simulation tool
(STWPLLSim) that allows a very accurate estimation of the device’s phase noise according to the desired project parameters (VCO frequency, selected output stage, reference clock,
frequency step, and so on); refer to
Section 8: Application information
14/53
STW81103 Typical performance characteristics
Phase noise is measured with the Agilent E5052A Signal Source Analyzer. All closed-loop measurements are done with F
STEP
=200 kHz, with the F
PFD
and charge pump current
properly set. The loop filter configuration is depicted in
Figure 36: Typical application diagram
, and the reference clock signal is at 76.8 MHz with a phase noise of -135 dBc/Hz
@1 kHz offset, -145 dBc/Hz @10 kHz offset and -149.5 dBc/Hz of noise floor.
Figure 3.
VCO A (direct output) open loop phase noise
Figure 4.
VCO B (direct output) open loop phase noise
Figure 5.
VCO A (direct output) closed loop phase noise at 2.775 GHz
(F
STEP
=200 kHz; F
PFD
=200 kHz;
I
CP
=2 mA)
Figure 6.
VCO B (direct output) closed loop phase noise at 4.675 GHz
(F
STEP
=200 kHz; F
PFD
=200 kHz;
I
CP
=3 mA)
1.0° rms 1.5° rms
15/53
Typical performance characteristics STW81103
Figure 7.
VCO A (div. by 2 output) closed loop phase noise at 1.3876 GHz
(F
STEP
=200 kHz; F
PFD
=400 kHz;
I
CP
=1.5 mA)
Figure 8.
VCO B (div. by 2 output) closed loop phase noise at 2.3376 GHz
(F
STEP
=200 kHz; F
PFD
=400 kHz;
I
CP
=2 mA)
0.4° rms 0.6° rms
Figure 9.
VCO A (div. by 4 output) closed loop phase noise at 693.8 MHz
(F
STEP
=200 kHz; F
PFD
=800 kHz;
I
CP
=1 mA)
Figure 10.
VCO B (div. by 4 output) closed loop phase noise at 1168.8 MHz
(F
STEP
=200 kHz; F
PFD
=800 kHz;
I
CP
=1.5 mA)
0.19° rms 0.27° rms
16/53
STW81103
Figure 11.
PFD frequency spurs (direct output; F
PFD
=200 kHz)
Typical performance characteristics
Figure 12.
PFD frequency spurs (div. by 2 output; F
PFD
=400 kHz)
-76 dBc
@200KHz
-84 dBc
@400KHz
Figure 13.
PFD frequency spurs (div. by 4 output; F
PFD
=800 kHz)
Figure 14.
Settling time (final frequency=2.4
GHz; F
PFD
=400 kHz; I
CP
=2.5 mA)
< -90 dBc
@800KHz
17/53
General description STW81103
Figure 1: Block diagram
shows the separate blocks that, when integrated, form an Integer-N
PLL frequency synthesizer.
The STW81103 consists of two internal low-noise VCOs with buffer blocks, a divider by 2, a divider by 4, a low-noise PFD (phase frequency detector), a precise charge pump, a 10-bit programmable reference divider, two programmable counters and a programmable dualmodulus prescaler. The 5-bit A-counter and 12-bit B-counter, in conjunction with the dualmodulus prescaler P/P+1 (16/17 or 19/20), implement an N integer divider, where N = B*P
+A. The division ratio of both reference and VCO dividers is controlled through the selected digital interface (I
2
C bus or SPI).
The digital interface type is selected through the proper hardware connection of pin
DBUS_SEL (0 V for I
2
C bus, 3.3 V for SPI).
All devices operate with a power supply of 3.3 V, and can be powered down when not in use.
18/53
STW81103 Circuit description
input stage
The reference input stage is shown in
Figure 15
. The resistor network feeds a DC bias at the
F ref
input, while the inverter used as the frequency reference buffer is AC coupled.
Figure 15.
Reference frequency input buffer
VDD
F ref
INV BUF
Power Down
The 10-bit programmable reference counter allows division of the input reference frequency to produce the input clock to the PFD. The division ratio is programmed through the digital interface.
5.3 Prescaler
The dual-modulus prescaler P/P+1 takes the CML clock from the VCO buffer and divides it down to a manageable frequency for the CMOS A and B counters. The modulus P is programmable and can be set to 16 or 19. The prescaler is based on a synchronous 4/5 core whose division ratio depends on the state of the modulus input.
19/53
Circuit description
5.4
STW81103
A and B counters
The 5-bit A-counter and 12-bit B-counter, in conjunction with the selected dual modulus
(16/17 or 19/20) prescaler, allow the generation of output frequencies that are spaced only by the reference frequency divided by the reference division ratio. The division ratio and the
VCO output frequency are given by the following formulas:
N = B x P + A
F
VCO
=
(
B
×
P
R
+ A
)
× F ref where
F
VCO
: output frequency of VCO
P: modulus of dual modulus prescaler (16 or 19 selected through the digital interface)
B: division ratio of the main counter
A: division ratio of the swallow counter
F ref
: input reference frequency
R: division ratio of the reference counter
N: division ratio of the PLL
For the VCO divider to work correctly, B absolutely must be greater than A, which can take any value ranging from 0 to 31. The value range of N is either from 256 to 65551 (if P=16) or from 361 to 77836 (P=19).
Figure 16.
VCO divider diagram
VCOBUF-
Pre s c a ler
16/17 or 1 9 /20
VCOBUF+
To PFD mod u l us
5b it
A-counter
12b it
B-counter
20/53
STW81103
5.5
Circuit description
Phase frequency detector (PFD)
The PFD takes inputs from the reference and the VCO dividers and produces an output proportional to the phase error. The PFD includes a delay gate that controls the width of the anti-backlash pulse. This pulse ensures that there is no dead zone in the PFD transfer function.
Figure 17
is a simplified schematic of the PFD.
Figure 17.
PFD diagram
VDD
D FF Up
Fref
R
Del a y
F ref
VDD
R
D FF
Down
ABL
This signal indicates that the difference between rising edges of both UP and DOWN PFD signals is found to be shorter than the fixed delay (roughly 5 ns). The Lock Detect signal is high when the PLL is locked and low when the PLL is unlocked. Lock Detect consumes current only during PLL transients.
This block drives two matched current sources, I
UP
and I
DOWN
, which are controlled respectively by UP and DOWN PFD outputs. The nominal value of the output current is controlled by an external resistor (connected to the REXT input pin) and a 3-bit word that allows selection among 8 different values.
The minimum value of the output current is: I
MIN
= 2*VBG/REXT (VBG~1.17 V)
21/53
Circuit description
Note:
STW81103
Table 7.
CPSEL2
Current value vs. selection
CPSEL1 CPSEL0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
Current
I
MIN
2*I
MIN
3*I
MIN
4*I
MIN
5*I
MIN
6*I
MIN
7*I
MIN
8*I
MIN
Value for REXT=4.7 K Ω
0.5 mA
1.0 mA
1.5 mA
2.0 mA
2.5 mA
3.0 mA
3.5 mA
4.0 mA
The current is output on pin ICP. During VCO auto-calibration, the ICP and VCTRL pins are forced to VDD/2.
Figure 18.
Loop filter connection
VDD
VCTRL
BUF C 3 R 3
Ch a rge
P u mp
ICP
R1
C1
C2
BUF
C a l b it
22/53
STW81103
5.8 Voltage controlled oscillators
Circuit description
The STW81103 integrates two low-noise VCOs to cover a wide band from:
●
●
●
2500 MHz to 3050 MHz and from 4350 MHz to 5000 MHz (direct output)
1250 MHz to 1525 MHz and from 2175 MHz to 2500 MHz (selecting divider by 2)
625 MHz to 762.5 MHz and from 1087.5 MHz to 1250 MHz (selecting divider by 4)
The frequency range is 2500 MHz-3050 MHz for VCO A, and 4350 MHz-5000 MHz for VCO
B.
5.8.2 VCO frequency calibration
Both VCOs can operate on 32 frequency ranges that are selected by adding or subtracting capacitors from the resonator. These frequency ranges are intended to cover the wide band of operation and compensate for process variation on the VCO center frequency.
The range is automatically selected when the SERCAL bit is set to 1. The charge pump is inhibited, and the ICP and VCTRL pins are at VDD/2 volts. The ranges are then tested with this VCO input voltage to select the one nearest to the desired output frequency
(F
OUT
= N*F ref
/R).
After this selection, the SERCAL bit is automatically reset to 0 and the charge pump is once again enabled. To enable a fast settle, the PLL needs only to perform fine adjustments around VDD/2 on the loop filter to reach F
OUT
.
Figure 19.
VCO sub-bands frequency characteristics
23/53
Circuit description
5.8.3
STW81103
The SERCAL bit should be set to “1” at each division ratio change. The VCO calibration procedure takes approximately 7 periods of the PFD frequency.
The maximum allowed F
PFD
to perform the calibration process is 1 MHz. When using a higher F
PFD
, follow the steps below:
1.
Calibrate the VCO at the desired frequency with an F
PFD
less than 1 MHz.
2. Set the ratio of the A, B and R dividers for the desired F
PFD
.
VCO calibration auto-restart feature
The VCO calibration auto-restart feature, once activated, allows to restart the calibration procedure when the lock detector reports that the PLL has moved to an unlock condition
(trigger on ‘1’ to ‘0’ transition of lock detector signal).
This situation could happen if the device experiences a significant temperature variation.
Once programmed at the initial temperature T
0
inside the operating temperature range
(-40 °C to +85 °C), the synthesizer is able to maintain the lock status only if the temperature drift (in either direction) is within the limit specified by the
Δ
T
LK
parameter, provided that the final temperature T
1
is still inside the nominal range.
Each VCO featured by STW81103 has its specific
Δ
T
LK
parameter reported in
Table 5
is typically lower than the maximum allowable drift (
Δ
T
MAX
=125; from -40 °C to +85 °C and vice versa).
By enabling the VCO calibration auto-restart feature (through the CAL_AUTOSTART_EN bit), the part will be able to select again the proper VCO frequency sub-range if the temperature drift exceeds the
Δ
T
LK
limit, without any external user command.
VCO voltage amplitude control
The voltage swing of the VCOs can be adjusted over four levels by means of two dedicated programming bits (PLL_A1 and PLL_A0). Higher amplitudes provide best phase noise, whereas lower amplitudes save power.
Table 8
gives the voltage swing level expected on the resonator nodes, the current
consumption, and the phase noise at 1 MHz.
Table 8.
VCO A performances versus amplitude setting (Freq = 2.8 GHz)
PLL_A[1:0]
Differential voltage swing (Vp)
Current consumption (mA)
PN @1 MHz (dBc/Hz)
00
01
10
11
1.1
1.3
1.9
2.1
16
19
27
30
-126
-127
-130
-131
24/53
STW81103 Circuit description
Table 9.
VCO B performances vs. amplitude setting (Freq = 4.7 GHz)
PLL_A[1:0]
Differential voltage swing (Vp)
Current consumption (mA)
PN at 1 MHz
(dBc/Hz)
00
01
10
11
1.1
1.3
1.9
2.1
13
15
22
24
-121
-122
-126
-127
5.9.1
The differential output signal of the synthesizer can be selected by software among three different signal paths (direct, divider by 2 and divider by 4) providing multi-band capability.
The selection of the output stage is done by programming properly the PD[4:0] bits.
The output stage is an open-collector structure which is able to meet different requirements over the desired output frequency range by proper connections on the PCB. Refer to
Section 8: Application information
for more details on PCB connections.
Output buffer control mode
This control mode allows to enable/disable the output stage by a hardware control pin
(EXT_PD, pin#23) while the PLL stays locked at the desired frequency; in such a way a very fast switching time is achieved.
This feature can be useful in designing a ping-pong architecture saving the cost of an external RF switch.
The function of pin#23 (EXT_PD) is set with the OUTBUF_CTRL_EN bit as shown in
Table 10.
Table 10.
EXT_PD pin function setting
OUTBUF_CTRL_EN Function of the EXT_PD pin
0
1
Device hardware power down
Output Buffer control
EXT_PD pin settings
EXT_PD = 0 V Î Device ON
EXT_PD = 3.3 V Î Device OFF
EXT_PD = 0 V Î Output Stage ON
EXT_PD = 3.3 V
Î
Output Stage OFF
25/53
Circuit description STW81103
5.10 External VCO buffer
Although the main benefits of the STW81103 are the two wideband and low-noise VCOs, the capability to use an external VCO is also provided.
The external VCO buffer is able to manage a signal coming from an external VCO in order to build a synthesizer using the STW81103 only as PLL IC. The output signal of the synthesizer can also be taken from the output section of the STW81103 (direct, divided by 2 or divided by 4 by) by properly setting the PD[4:0] bits, thus providing additional flexibility.
The external VCO signal can range from 625 MHz up to 5 GHz and its minimum power level must be -10 dBm.
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STW81103
6 I
2
C bus interface
I
2
C bus interface
The I
2
C bus interface is selected by hardware connection of pin #21 (DBUS_SEL) to 0 V.
Data is transmitted from microprocessor to the STW81103 through the 2-wire (SDA and
SCL) I
2
C bus interface. The STW81103 is always a slave device.
The I
2
C bus protocol defines any device that sends data on the bus as a transmitter, and any device that reads the data as a receiver. The device controlling the data transfer is the master, and the others are slaves. The master always initiates the transfer and provides the serial clock for synchronization.
The STW81103 I
2
C bus supports Fast Mode operation (clock frequency up to 1MHz).
Data changes on the SDA line must only occur when the SCL is low. SDA transitions while the clock is high are used to identify a START or STOP condition.
Figure 20.
Data validity
S DA
S CL
D a t a line
S t ab le d a t a
V a lid
Ch a nge d a t a a llowed
6.1.2 START and STOP conditions
START condition
A START condition is identified by a transition of the data bus SDA from high to low while the clock signal SCL is stable in the high state. A START condition must precede any data transfer command.
STOP condition
A STOP condition is identified by a transition of the data bus SDA from low to high while the clock signal SCL is stable in the high state. A STOP condition terminates communications between the STW81103 and the bus master.
27/53
I
2
C bus interface
Figure 21.
START and STOP conditions
STW81103
S CL
S DA
6.1.3
S TART S TOP
Byte format and acknowledge
Every byte put on the SDA line must be 8 bits long, starting with the most significant bit
(MSB), and be followed by an acknowledge bit to indicate a successful data transfer.
The transmitter releases the SDA line after sending 8 bits of data. During the 9th clock pulse, the receiver pulls the SDA line low to acknowledge the receipt of 8 bits of data.
Figure 22.
Byte format and acknowledge
S CL
S DA
S TART
1
M S B
2 3
//
7
//
8 9
Acknowledgement from receiver
The master must first initiate with a START condition to communicate with the STW81103, and then send 8 bits (MSB first) on the SDA line which correspond to the device select address and the read or write mode.
The first seven MSBs are the device address identifier, which corresponds to the I
2
C bus definition. For the STW81103, the address is set at “1100A
2
A
1
A
0
”, 3 bits programmable.
The 8th bit (LSB) is the read or write (RW) operation bit, which is set to 1 in read mode and to 0 in write mode.
Following a START condition, the STW81103 identifies the device address on the bus and, if matched, acknowledges the identification on the SDA bus during the 9th clock pulse.
28/53
STW81103
6.1.5
6.1.6
6.1.7
I
2
C bus interface
Single-byte write mode
Following a START condition, the master sends a device select code with the RW bit set to
0. The STW81103 sends an acknowledge and waits for the 1-byte internal sub-address that provides access to the internal registers.
After receiving the sub-address internal byte, the STW81103 again responds with an acknowledge. A single-byte write to sub-address 00H changes the FUNCTIONAL_MODE register, a single-byte write with sub-address 04H changes the CONTROL register, and so on.
Table 11.
Single-byte write mode
S 1100A
2
A
1
A
0
0 ack sub-address byte ack DATA IN ack P
Multi-byte write mode
The multi-byte write mode can start from any internal address. The master sends the data bytes, and each one is acknowledged. The master terminates the transfer by generating a
STOP condition.
The sub-address decides the starting byte. For example, a multi-byte with sub-address 01H and 2 DATA_IN bytes changes the B_COUNTER and A_COUNTER registers (01H,02H), and a multi-byte with sub-address 00H and 6 DATA_IN bytes changes all the STW81103 registers.
Table 12.
Multi-byte write mode
S 1100A
2
A
1
A
0
0 ack sub-address byte ack DATA IN ack …….
DATA IN ack P
Current byte address read mode
In the current byte address read mode, following a START condition, the master sends the device address with the RW bit set to 1. Note that no sub-address is needed since there is only one read register. The STW81103 acknowledges this and outputs the data byte. The master does not acknowledge the received byte, and terminates the transfer with a STOP condition.
Table 13.
Current byte address read mode
S 1100A
2
A
1
A
0
1 ack DATA OUT No ack P
29/53
I
2
C bus interface
Figure 23.
Data and clock
S DA
S CL
STW81103 t cwl t c s t ch
Table 14.
Data and clock timing specifications
Symbol Parameter t cs t ch t cwh t cwl
Data to clock setup time
Data to clock hold time
Clock pulse width high
Clock pulse width low
Figure 24.
Start and stop t cwh
S DA
Minimum time
2
2
10
5
Units ns ns ns ns
S CL t s t a rt t s top
30/53
STW81103
Table 15.
Start and stop timing specifications
Symbol Parameter t start t stop
Figure 25.
Ack
Clock to data start time
Data to clock down stop time
S DA
I
2
C bus interface
Minimum time
2
2
Units ns ns
S CL
8 9 t d1
Table 16.
Ack timing specifications
Symbol Parameter t d1 t d2
Ack begin delay
Ack end delay t d2
Minimum time
2
2
Units ns ns
31/53
I
2
C bus interface
6.3 I
2
C registers
The STW81103 has 6 write-only registers and 1 read-only register.
STW81103
Table 17
gives a short description of the write-only registers.
Table 17.
Write-only registers
HEX code DEC code
0x00
0x01
0x02
0x03
0x04
0x05
2
3
4
5
0
1
FUNCTIONAL_MODE
Description
FUNCTIONAL_MODE
B_COUNTER
A_COUNTER
REF_DIVIDER
CONTROL
CALIBRATION
MSB b7 b6 b5 b4 b3
OUTBUF_CTRL_EN CAL_AUTOSTART_EN PD4 PD3 PD2 b2 b1
PD1 PD0
LSB b0
B11
OUTBUF_CTRL_EN: Output buffer control mode enable (0 = Off; 1 = ON)
CAL_AUTOSTART_EN: VCO calibration auto-restart enable (0 = Off; 1 = ON)
The bits PD[4:0] allow to select different functional modes for the STW81103 synthesizer according to the
Table 18
Table 18.
Functional modes
Decimal value PD[6:0] Description
0
1
2
3
4
5
6
7
8
9
Power down mode
Enable VCO A, output frequency divided by 2
Enable VCO B, output frequency divided by 2
Enable external VCO, output frequency divided by 2
Enable VCO A, output frequency divided by 4
Enable VCO B, output frequency divided by 4
Enable external VCO, output frequency divided by 4
Enable VCO A, direct output
Enable VCO B, direct output
Enable external VCO, direct output
32/53
STW81103 I
2
C bus interface
B_COUNTER
MSB b7
B10 b6
B9 b5
B8 b4
B7 b3
B6 b2
B5 b1
B4
LSB b0
B3
B[10:3]. B counter value (bit B11 in the previous register, bits B[2:0] in the next register)
A_COUNTER
MSB b7
B2 b6
B1 b5
B0 b4
A4 b3
A3
Bits B[2:0] for B_COUNTER, A_COUNTER values.
REF_DIVIDER
b2
A2
MSB b7
R9 b6
R8 b5
R7 b4
R6 b3
R5 b2
R4
Reference clock divider ratio R[9:1] (bits R1, R0 in the next register).
CONTROL
b1
A1 b1
R3
LSB b0
A0
LSB b0
R2
MSB b7
R1 b6
R0 b5
PLL_A1 b4
PLL_A0
LSB b3 b2 b1 b0
CPSEL2 CPSEL1 CPSEL0 PSC_SEL
The CONTROL register is used to set the charge pump current, the VCO output voltage amplitude and the prescaler modulus:
CPSEL[2:0]: charge pump output current
PSC_SEL: prescaler modulus select ('0' for P=16, '1' for P=19)
The LO output frequency is programmed by setting the proper values for A, B and R according to the following formula:
F
OUT
= D
R
× (
B
×
P + A
) ×
F
REF
R
– CLK where D
R
equals
{ 1 for direct output
0.5
for output divided by 2
0.25 for output divided by 4 and P is the selected prescaler modulus.
33/53
I
2
C bus interface STW81103
CALIBRATION
MSB b7 b6 b5
INITCAL SERCAL SELEXTCAL b4
CAL4 b3
CAL3 b2
CAL2 b1
CAL1
LSB b0
CAL0
This register controls the VCO calibrator using the following values:
INITCAL: for test purposes only, must be set to 0
SERCAL: at 1 starts the VCO auto-calibration (automatically reset to 0 at the end of calibration)
SELEXTCAL: for test purposes only; must be set to 0
CAL[4:0]: for test purposes only; must be set to 0
MSB LSB b7 b6 b5 b4 b3 b2 b1 b0
DEV_ID1 DEV_ID0 LOCK_DET INTCAL4 INTCAL3 INTCAL2 INTCAL1 INTCAL0
This register is automatically addressed in the ‘current byte address read mode’, using the following values:
DEV_ID[1:0]: device identifier bits; returns ‘10’
LOCK_DET: 1 when PLL is locked
INTCAL[4:0]: internal value of the VCO control word
At power on, all the bits are set to '0'. Consequently the part starts in power down mode.
34/53
STW81103
6.4
6.4.1
I
2
C bus interface
VCO calibration procedure
Calibration of the VCO center frequency is activated when the SERCAL bit (CALIBRATION register bit[6]) is set to 1.
To program the device properly while ensuring VCO calibration, perform the following steps before every channel change:
1.
Program all the registers using a multi-byte write sequence with the desired settings
(functional mode, B and A counters, R counter, VCO amplitude, charge pump, prescaler modulus), and all the bits of the CALIBRATION register (05H) set to 0.
2. Program the CALIBRATION register using a single-byte write sequence (subaddress
05H) with the SERCAL bit set to 1.
The maximum allowed PFD frequency (F
PFD
) during calibration is 1 MHz; if you want a F
PFD higher than 1 MHz, perform the following additional steps:
●
●
Perform all the steps of the calibration procedure, making sure to program the desired
VCO frequency with proper settings for the R, B and A counters so that F
PFD
is 1 MHz.
Program the device with the desired VCO and PFD frequency settings according to step 1) above.
VCO calibration auto-restart feature
The VCO calibration auto-restart feature can be enabled in two steps:
1.
set the desired frequency ensuring VCO calibration as described above (section 6.4)
2. program the FUNCTIONAL_MODE register (sub-address 00H) using a single-byte write sequence with the CAL_AUTOSTART_EN bit set to '1' while keeping unchanged the others.
35/53
SPI digital interface
7 SPI digital interface
STW81103
The SPI digital interface is selected by hardware connection of pin #21 (DBUS_SEL) to
3.3 V.
The STW81103 IC is programmed by means of a high-speed serial-to-parallel interface with write option only. The 3-wire bus can be clocked at a frequency as high as 100 MHz to allow fast programming of the registers containing the data for RF IC configuration.
The chip is programmed through serial words with a full length of 26 bits. The first 2 MSBs represent the address of the registers, and the 24 LSBs represent the value of the registers.
Each data bit is stored in the internal shift register on the rising edge of the CLOCK signal.
The outputs of the selected register are sent to the device on the rising edge of the LOAD signal.
Figure 26.
SPI input and output bit order
L as t b it s ent
(L S B)0
DATA
1
2 2 3
24
25(M S B)
A1
LOAD
Addre ss decoder
D2 3 (M S B)
LOAD #4
36/53
D0 (L S B)
Reg.#0
Reg.#1
Reg.#4
STW81103 SPI digital interface
0
0
1
1
Table 19.
SPI data structure (MSB is sent first)
MSB LSB
Address Data for register (24 bits)
A1 A0 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Table 20.
Address decoder and outputs
Address
A1 A0 DATABITS D23-D0 No Name
0
1
0
1
24
24
24
24
0
1
2
3
ST1
ST2
ST3
ST4
Outputs
Function
Reference divider, VCO amplitude, VCO calibration, charge pump current, prescaler modulus
Functional modes, VCO dividers
Reserved
Reserved
Figure 27.
SPI timing specification t s et u p thold
M S B M S B-1 D a t a
Clock
Lo a d tdk
Table 21.
SPI timing specification
Symbol Parameter t setup t hold t clk t load t clk_loadr t clk_loadf
DATA to CLOCK setup time
DATA to CLOCK hold time
CLOCK cycle period
LOAD pulse width
CLOCK to LOAD rising edge
CLOCK to LOAD falling edge
L S B t clk_lo a df t clk_lo a dr tlo a d
Min.
0.8
0.2
10
3
2
0.5
Typ.
Max.
Units ns ns ns ns ns ns
37/53
SPI digital interface
Table 22.
Bits at 00h and ST1
Serial interface address = 00h
Bit
[15]
[14]
[13]
[12]
[11]
[10]
[9]
[23]
[22]
[21]
[20]
[19]
[18]
[17]
[16]
[4]
[3]
[2]
[1]
[0]
[8]
[7]
[6]
[5]
Name
R1
R0
PLL_A1
PLL_A0
CPSEL2
CPSEL1
CPSEL0
R9
R8
R7
R6
R5
R4
R3
R2
PSC_SEL
INITCAL
SERCAL
SELEXTCAL
CAL4
CAL3
CAL2
CAL1
CAL0
Register name = ST1
Description
Reference clock divider ratio
VCO amplitude control
Charge pump output current control
Prescaler modulus select (0 for P=16, 1 for P=19)
For test purposes only; must be set to 0
Enable VCO calibration (see
)
For test purposes only; must be set to ‘0’
For test purposes only; must be set to ‘0’
STW81103
38/53
STW81103 SPI digital interface
[12]
[11]
[10]
[9]
[8]
[16]
[15]
[14]
[13]
[3]
[2]
[1]
[0]
[7]
[6]
[5]
[4]
Table 23.
Bits at 01h and ST2
Serial interface address = 01h
Bit Name
[23]
[22]
[21]
[20]
[19]
[18]
[17]
OUTBUF_CTRL_EN
CAL_AUTOSTART_EN
PD4
PD3
PD2
PD1
PD0
Register name = ST2
Description
Output buffer control mode enable (0 = Off, 1 = On)
VCO calibration auto restart enable (0 = Off, 1 = On)
Device functional modes:
0. Power down
1. Enable VCO A, output frequency divided by 2
2. Enable VCO B, output frequency divided by 2
3. Enable external VCO, output frequency divided by 2
4. Enable VCO A, output frequency divided by 4
5. Enable VCO B, output frequency divided by 4
6. Enable external VCO, output frequency divided by 4
7. Enable VCO A, direct output
8. Enable VCO B, direct output
9. Enable external VCO, direct output
B7
B6
B5
B4
B3
B11
B10
B9
B8
A3
A2
A1
A0
B2
B1
B0
A4
B_COUNTER bits
A_COUNTER bits
39/53
SPI digital interface
The LO output frequency is programmed by setting the proper value for A, B and R according to the following formula:
F
OUT
= D
R
× ( B × P + A ) ×
F
REF
R
– CLK where D
R equals
{ 1 for direct output
0.5
for output divided by 2
0.25 for output divided by 4 and P is the selected prescaler modulus.
STW81103
7.4
7.4.1
At power on, all the bits are set to '0'. Consequently the part starts in power down mode.
VCO calibration procedure
Calibration of the VCO center frequency is activated when the SERCAL bit (ST1 register bit[6]) is set to 1.
To program the device properly while ensuring VCO calibration, perform the following steps before every channel change:
1.
Program the ST2 register with the desired settings (functional mode, B and A counters).
2. Program the ST1 register with the desired settings (R counter, VCO amplitude, charge pump, prescaler modulus) and with the SERCAL bit set to 1.
The maximum allowed PFD frequency (F
PFD
) during calibration is 1 MHz; if you want a F
PFD higher than 1 MHz, perform the following additional steps:
●
●
Perform all the steps (step 1 and 2 above) of the calibration procedure, making sure to program the desired VCO frequency with proper settings of the R, B and A counters so that F
PFD is ≤ 1 MHz.
Program the device with the desired VCO and PFD frequency settings as per steps 1 and 2 above with SERCAL bit set to 0.
VCO calibration auto-restart feature
The VCO calibration auto-restart feature can be enabled in two steps:
1.
Set the desired frequency ensuring VCO calibration as described above (
Section 7.4
)
2. Program the ST2 register with the CAL_AUTOSTART_EN bit set to '1' while keeping unchanged the others.
40/53
STW81103 Application information
The STW81103 features three different alternately selectable bands: direct output (2.5 to
3.05 GHz and 4.35 to 5.0 GHz), divided by 2 (1.25 to 1.525 GHz and 2.175 to 2.5 GHz) and divided by 4 (625 to 762.5 MHz and 1087.5 to 1250 MHz). To achieve a suitable power level, a good matching network is necessary to adapt the output stage to a 50 Ω load. Moreover, since most commercial RF components have single-ended input and output terminations, a differential to single-ended conversion may be required.
The different matching configurations shown below for each of the three bands are suggested as a guideline when designing your own application board.
Inside the evaluation kit is the ADS design for each matching configuration suggested in this chapter. The name of the corresponding ADS design is given in each figure.
The ADS designs provide only a first indication of the output stage matching, and should be reworked according to the choices of layout, board substrate, components and so on.
The ADS designs of the evaluation boards are provided with a complete electromagnetic modelling (board, components, and so on).
If you do not need a differential to single conversion, you can match the output buffer of the
STW81103 in the simple way shown in
Figure 28
. This illustrates the differential to single-
ended output network in the 2.5 - 5.0 GHz range (MATCH_LC_LUMP_4G_DIFF.dsn).
Figure 28.
Differential/single-ended output network
(MATCH_LC_LUMP_4G_DIFF.dsn)
Vcc
100 ohm
RF
OUTP
RF
OUTN
100 ohm
5.5nH
10pF
10pF
50 ohm
50 ohm
5.5nH
Vcc
Since most discrete components for microwave applications are single-ended, you can easily use one of the two outputs and terminate the other one to 50
Ω
with a 3 dB power loss.
41/53
Application information STW81103
Alternatively, you can combine the two outputs in other ways. A first topology for the direct output (2.5 to 5.0 GHz) is suggested in
Figure 29
. It basically consists of a simple LC balun
and a matching network to adapt the output to a 50
Ω
load. The two LC networks shift output signal phase of -90° and +90°, thus combining the two outputs. This topology, designed for a center frequency of 4 GHz, is intrinsically narrow-band since the LC balun is tuned at a single frequency. If the application requires a different sub-band, the LC combiner can be easily tuned to the frequency of interest.
Figure 29.
LC lumped balun and matching network (MATCH_LC_LUMP_4G.dsn)
Vcc
1.
9 nH
0.
8 pF
1.
9 nH
50 ohm
RF
OUTP
0.
8 pF 2.5pF
1.
9 nH
50 ohm
RF
OUTN
50 ohm
0.
8 pF
1.
9 nH
0.
8 pF
Vcc
The 1.9 nH shunt inductor works as a DC feed for one of the open collector terminals as well as a matching element along with the other components. The 1.9 nH series inductors are used to resonate the parasitic capacitance of the chip.
For optimum output matching, it is recommended to use 0402 Murata or AVX capacitors and
0403 or 0604 HQ Coilcraft inductors. It is also advisable to use short interconnection paths to minimize losses and undesired impedance shift.
An alternative topology that permits a more broadband matching as well as balanced to unbalanced conversion, is shown in
Figure 30
.
42/53
STW81103 Application information
Figure 30.
Evaluation board (EVB4G) matching network (MATCH_EVB4G.dsn)
Vcc
50 ohm
RF
OUTP
RF
OUTN
50 ohm
5.5nH
12pF
12pF
2:1
5.5nH
12pF 4.7pF
1pF 1pF 1.2pF
1.2pF
50 ohm
8.2
Vcc
For differential to single conversion, the 50 to 100 Ω Johanson balun is recommended
(3700BL15B100).
Divided by 2 output
If your application does not require a balanced to unbalanced conversion, the output
matching reduces to the simple circuit shown below (
Figure 31
), which illustrates a differential to single-ended output network in the 1.25 - 2.5 GHz range
(MATCH_LC_LUMP_2G_DIFF.dsn). You can easily use this solution to provide one singleended output that terminates the other output at 50 Ω with a 3 dB power loss.
Figure 31.
Differential/single-ended output network
(MATCH_LC_LUMP_2G_DIFF.dsn)
Vcc
50 ohm
RF
OUTP
RF
OUTN
50 ohm
22nH
10pF
10pF
50 ohm
50 ohm
22nH
Vcc
43/53
Application information STW81103
A first solution to combine the differential outputs is the lumped LC type balun tuned in the
2 GHz band (
Figure 32
).
Figure 32.
LC lumped balun for divided by 2 output (MATCH_LC_LUMP_2G.dsn)
Vcc
50 ohm
2.7nH
2pF
2.7nH
RF
OUTP
2pF 3 pF
2.7nH
50 ohm
3 nH
RF
OUTN
50 ohm
2pF
2.7nH
2pF
Vcc
The same recommendation for the SMD components also applies to the divided by 2 output.
Another topology suited to combining the two outputs for the divided by 2 frequencies is represented in
Figure 33
.
Figure 33.
Evaluation board (EVB2G) matching network (MATCH_EVB2G.dsn)
Vcc
50 ohm
RF
OUTP
RF
OUTN
50 ohm
5.5nH
22pF
22pF
2:1
5.5nH
22pF 1.
9 nH
1.2pF
50 ohm
Vcc
44/53
STW81103 Application information
For differential to single conversion, the 50 to 100
Ω
Johanson balun (1600BL15B100) is recommended.
8.3 Divided by 4 output
The topology, components, values and considerations of
Figure 31
by 4 output (MATCH_LC_LUMP_1G_DIFF.dsn).
As for the previous sections, a solution to combine the differential outputs is the lumped LC type balun tuned in the 1 GHz band (
Figure 34
).
Figure 34.
LC lumped balun for divided by 4 output (MATCH_LC_LUMP_1G.dsn)
Vcc
25 ohm
RF
OUTP
5.5nH
4pF
5.5nH
4pF 6pF
5.5nH
14nH
50 ohm
RF
OUTN
25 ohm 5.5nH
4pF
4pF
Vcc
If you prefer to use an RF balun, you can adapt the topology depicted in
Figure 33
change the balun and the matching components (
Figure 35
). The suggested balun for the
0.625 - 1.25 GHz frequency range is the 1:1 Johanson 900BL15C050.
45/53
Application information STW81103
Figure 35.
Evaluation board (EVB1G) matching network (MATCH_EVB1G.dsn)
Vcc
25 ohm
RF
OUTP
RF
OUTN
25 ohm
1 8 nH
8 .2pF
8 .2pF
1:1
1 8 nH
22pF 2.1nH
0.5pF
50 ohm
Vcc
46/53
An evaluation kit can be delivered upon request, including the following:
●
●
●
●
●
●
Evaluation board
GUI (graphical user interface) to program the device
Measured S parameters of the RF output
ADS2005 schematics providing guidelines for application board design
STWPLLSim software for PLL loop filter design and noise simulation
Application programming interface (API)
●
●
●
Three different evaluation kits are available, each optimized for one of the following frequency ranges:
1 GHz
2 GHz
4 GHz
When ordering, please specify one of the following order codes:
Table 24.
Order code of the evaluation kit
Part number
STW81103-EVB1G
STW81103-EVB2G
STW81103-EVB4G
Description
1 GHz frequency range - divider by 4 output optimized
2 GHz frequency range - divider by 2 output optimized
4 GHz frequency range - direct output optimized
The three evaluation kits differ only for the output stage network and can be adapted from one frequency band variant to a different one replacing properly the matching components and the balun.
STW81103 Application diagram
Figure 36.
Typical application diagram
From/to microcontroller
100 100 100
15p 15p 15p
RF O u t
1 n
VDD 1
22 p 10 P
VDD 1
VDD_VCOA
VDD_DIV2
I2C
DBU S _ S EL
VDD_BUFVCO
S PI
VDD_OUTBUF
OUTBUFP
EXTVCO_INP
STW81103
EXTVCO_INN
VDD_PLL OUTBUFN
VDD_DIV4
VDD_VCOB
REF_CLK
TE S T2
1n
VDD
2
22p 10 P
1.
8 n ref clk
51
1n 22p
VDD 1
10 P
VDD
1 loop filter
270p
2.2K
8 .2K
6 8 p
2.7n
4.7K
1n
VDD 1
22p 10 µ to microcontroller
Note: 1 See
Section 8: Application information
for further information on output matching topology.
2 EXT_PD, ADD2, ADD1 (and ADD0 when the I
2
C bus is selected) can be hard wired directly on the board.
3 Loop filter values are for F
STEP
= 200 kHz.
4 For best performance VDD
1
must be a low noise supply (20 µV
RMS
in 10 Hz-100 kHz BW).
47/53
Application diagram
Figure 37.
Ping-pong architecture diagram
ORRSILOWHU
S
Q
S
N
N
WRPLFURFRQWUROOHU
QS M
9''
B
STW81103
5)2XW
9''
9''
QS M
9''
B
9''
9''
9''B9&2%
9''B',9
7(67
5()B&/.
QS M
287%8)1 9''B3//
67:
287%8)3
'HYLFH /RFNHGDW)UHT )
(;79&2B,11
2XWSXW%XIIHU&RQWURO0RGHHQDEOHG
9''B287%8) (;79&2B,13
9''B',9
9''B9&2$
9''B%8)9&2
'%86B6(/ 63,
QS M
Q
9''
B
9''B'%86
,&
QS M
9''
B
PLFURFRQWUROOHU 2XWSXW%XIIHU
+:&RQWURO
9''
B
QS M
9''
B
9''
9''
9''
B
QS M
9''B'%86
,&
QS M
9''B9&2$
9''B',9
'%86B6(/
9''B%8)9&2
63,
QS M
9''B287%8) (;79&2B,13
287%8)3
67:
(;79&2B,11
'HYLFH/RFNHGDW)UHT )
2XWSXW%XIIHU&RQWURO0RGHHQDEOHG
9''B3// 287%8)1
9''B',9
9''B9&2%
5()B&/.
7(67
Q
UHIFON
ORRSILOWHU
S
Q
N
S
N
QS M
9''
B
WRPLFURFRQWUROOHU
Note: 1 See
Section 8: Application information
for further information on output matching topology.
2 EXT_PD, ADD2, ADD1 (and ADD0 when the I
2
C bus is selected) can be hard wired directly on the board.
3 Loop filter values are for F
STEP
= 200 kHz.
4 For best performance VDD
1_1
(20
μ
V
RMS
and VDD
in 10 Hz-100 KHz BW).
1_2
must be low noise supplies
48/53
STW81103 Application diagram
Figure 38.
Application diagram with external VCO (LO output from STW81103)
)URPWR PLFURFRQWUROOHU
QS M
9''
Note:
/22XW
9''
9''
9''
9''
,&
QS M
9''B9&2$
9''B',9
9''B287%8)
'%86B6(/
9''B%8)9&2
(;79&2B,13
287%8)3
67:
(;79&2B,11
287%8)1 9''B3//
9''B',9
9''B9&2%
5()B&/.
7(67
63,
9''
Q
UHIFON
287
9&75/
&
QS M
N
&
9''
QS M
WR PLFURFRQWUROOHU
&
ORRSILOWHU
5
See
Section 8: Application information
for further information on output matching topology.
Figure 39.
Application diagram with external VCO (LO output from VCO)
)URPWR PLFURFRQWUROOHU
QS M
9''
/22XW
,&
9''B9&2$
9''B',9
'%86B6(/
9''B%8)9&2
63,
9''B287%8) (;79&2B,13
287%8)3
67:
(;79&2B,11
9''B3// 287%8)1
9''B',9
9''B9&2%
5()B&/.
7(67
9''
Q
UHIFON
&
287
9&75/
N
QS M
9''
WR PLFURFRQWUROOHU
&
&
ORRSILOWHU
5
49/53
Package mechanical data
10 Package mechanical data
STW81103
In order to meet environmental requirements, ST offers these devices in ECOPACK
® packages, which have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with
JEDEC standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: http://www.st.com.
Figure 40.
VFQFPN28 mechanical drawing
Note: 1 VFQFPN stands for Thermally Enhanced Very thin Fine pitch Quad Flat Package No lead.
(Very thin: A=1.00 Max)
2 Details of the terminal 1 identifier are optional, but if given, must be located on the top surface of the package by using either a mold or marked features.
50/53
STW81103
Table 25.
Package dimensions
Ref.
Min.
0.800
E1
E2 e
L
P
K ddd
A3 b
D
A
A1
A2
D1
D2
E
0.180
4.850
2.950
4.850
2.950
0.350
Typ.
4.750
3.100
5.000
4.750
3.100
0.500
0.550
0.900
0.020
0.650
0.200
0.250
5.000
Max.
1.000
0.050
1.000
0.300
5.150
3.250
5.150
3.250
0.750
0.600
14
0.080
Package mechanical data
Unit mm mm mm mm mm degrees mm mm mm mm mm mm mm mm mm mm
51/53
Ordering information STW81103
Table 26.
Order codes
Part number
STW81103AT
Temp range, ° C
-40 to 85
STW81103ATR -40 to 85
Package
VFQFPN28
VFQFPN28
Packing
Tray
Tape and reel
Table 27.
Document revision history
Date Revision
18-Jul-2007
14-Aug-2007
28-Mar-2008
1
2
3
Changes
Initial release.
Added
Chapter 8: Application information
. Modified
, and pin #23 description in
Updated Table 1: Pin description .
Updated Table 2: Absolute maximum ratings , Table 3: Operating conditions
,
Table 5: Electrical specifications
and Table 6: Phase noise specification .
Updated Section 5.8.2: VCO frequency calibration .
Added
VCO calibration auto-restart feature
.
Updated Section 5.8.3: VCO voltage amplitude control
.
Added
Section 5.10: External VCO buffer .
Added
Section 6.3.3: Default configuration .
Updated Section 6.4: VCO calibration procedure
and added
Section 6.4.1: VCO calibration auto-restart feature .
Updated Table 23: Bits at 01h and ST2
.
Added
Section 7.3.1: Default configuration .
Updated Section 7.4: VCO calibration procedure
and added
Section 7.4.1: VCO calibration auto-restart feature .
Added ‘Application program interface API’ item in
.
Modified notes after
Added
,
.
52/53
STW81103
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