STMicroelectronics STW82103B Datasheet

STW82103B

RF down converter with embedded integer-N synthesizer

Datasheet

−

production data

Features

■

■

■

■

■

■

■

■

■

■ High linearity:

– IIP3: +25 dBm

– 2FRF-2FLO spurious rejection: 80 dBc

■

■

Noise figure:

– NF: 10.5 dB

Conversion gain

– CG: 8 dB

RF range: 2300 MHz to 2700 MHz

Wide IF amplifier frequency range: 70 MHz to

400 MHz

Integrated RF balun with internal matching

■

Dual differential integrated VCOs with automatic center frequency calibration:

– LOA: 2200 to 2550 MHz

– LOB: 2500 to 3000 MHz

Embedded integer-N synthesizer

– Dual modulus programmable prescaler

(16/17 or 19/20)

– Programmable reference frequency divider

(10 bits)

– Adjustable charge pump current

– Digital lock detector

– Excellent integrated phase noise

– Fast lock time: 150 µs

■

Integrated DAC with dual current output

Supply: 3.3 V and 5 V analog,

3.3 V digital

Dual digital bus interface: SPI and I

2

C bus (fast mode) with 3 bit programmable address

(1101A

2

A

1

A

0

)

Process: 0.35 µm BICMOS SiGe

Operating temperature range -40 to +85 o

C

44-lead exposed pad VFQFPN package

7x7x1.0 mm

Applications

■

■

Cellular infrastructure equipment:

– IF sampling receivers

– Digital PA linearization loops

Other wireless communication systems.

Table 1.

Device summary

Part number Package

STW82103B VFQFPN-44

STW82103BTR VFQFPN-44

Packaging

Tray

Tape and reel

Description

The STMicroelectronics STW82103B is an integrated down converter providing 8 dB of gain,

10.5 dB NF, and a very high input linearity by means of its passive mixer.

Embedding two wide band auto calibrating VCOs and an integer-N synthesizer, the STW82103B is suitable for both Rx and Tx requirements for

Cellular infrastructure equipment.

The integrated RF balun and internal matching permit direct 50 ohm single-ended interface to RF port. The IF output is suitable for driving 200-ohm impedance filters.

By embedding a DAC with dual current output to drive an external PIN diode attenuator, the

STW82103B replaces several costly discrete components and offers a significant footprint reduction.

The STW82103B device is designed with

STMicroelectronics advanced 0.35 µm

SiGe process. Its performance is specified over a

-40 °C to +85 °C temperature range.

April 2012

This is information on a product in full production.

Doc ID 018517 Rev 2 1/67 www.st.com

1

7

8

5

6

3

4

1

2

Contents

Contents

STW82103B

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8.1

Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8.1.1

8.1.2

8.1.3

8.1.4

8.1.5

8.1.6

8.1.7

Reference input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Reference divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

A and B counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Phase frequency detector (PFD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Lock detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Mute until lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

8.1.8

8.1.9

Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Voltage controlled oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

8.1.10

Output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8.1.11

External VCO buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8.1.12

Mixer and IF amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

8.1.13

Dual output current DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2/67 Doc ID 018517 Rev 2

STW82103B

9

10

11

Contents

I2C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

9.1

I

2

C general features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

9.1.1

9.1.2

9.1.3

9.1.4

9.1.5

9.1.6

Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

START and STOP conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Byte format and acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Single-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Multi-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

9.1.7

Current byte address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

9.2

I

2

C timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

9.2.1

9.2.2

9.2.3

Data and clock timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

I

2

C START and STOP timing specification . . . . . . . . . . . . . . . . . . . . . . 36

I

2

C acknowledge timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . 37

9.3

I2C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9.3.1

9.3.2

I

2

C register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

I

2

C register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

9.4

Device calibration through the I

2

C interface . . . . . . . . . . . . . . . . . . . . . . . 45

9.4.1

9.4.2

9.4.3

VCO calibration procedure (I

2

C interface) . . . . . . . . . . . . . . . . . . . . . . . 45

Power ON sequence (I

2

C interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

VCO calibration auto-restart procedure (I

2

C interface) . . . . . . . . . . . . . 46

SPI digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

10.1

SPI general features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

10.2

SPI timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

10.2.1

Data, clock and load timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

10.3

SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

10.3.1

SPI register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

10.3.2

SPI register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

10.4

Device calibration through the SPI interface . . . . . . . . . . . . . . . . . . . . . . 53

10.4.1

VCO calibration procedure (SPI interface) . . . . . . . . . . . . . . . . . . . . . . . 53

10.4.2

Power ON sequence (SPI interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

10.4.3

VCO calibration auto-restart procedure (SPI interface) . . . . . . . . . . . . . 54

Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

11.1

Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

11.2

Standard Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Doc ID 018517 Rev 2 3/67

12

13

14

Contents STW82103B

11.3

Diversity mode operation with same LO frequency . . . . . . . . . . . . . . . . . 58

11.4

Diversity mode operation with different LO frequencies . . . . . . . . . . . . . . 59

11.5

External VCO standard mode operation . . . . . . . . . . . . . . . . . . . . . . . . . 60

11.6

External VCO diversity mode operation with same LO . . . . . . . . . . . . . . 61

Evaluation kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

4/67 Doc ID 018517 Rev 2

STW82103B

List of tables

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Digital logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Down converter mixer and IF amplifier electrical characteristics . . . . . . . . . . . . . . . . . . . . 15

Pin diode attenuator driver (dual output current DAC) electrical characteristics. . . . . . . . . 16

Integer-N synthesizer electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 9.

Phase noise performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 10.

Current values for CPSEL[2:0] selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 11.

VCOA performance against amplitude setting (frequency = 4.6 GHz) . . . . . . . . . . . . . . . . 30

Table 12.

VCOB performance against amplitude setting (frequency = 2.8 GHz) . . . . . . . . . . . . . . . . 30

Table 13.

Suggested CAP[2:0] values for LO Frequency range mixer . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 14.

Linearity performance against IFAMP[1:0] configuration (typical condition) . . . . . . . . . . . . 32

Table 15.

I

2

C data and clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 16.

I

2

C START and STOP timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 17.

I

2

C acknowledge timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 18.

I

2

C register list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 19.

Address decoder and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 20.

SPI timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 21.

SPI register list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 23.

Evaluation kit order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 24.

VFQFPN-44 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 25.

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Doc ID 018517 Rev 2 5/67

List of figures

List of figures

STW82103B

Figure 1.

STW82103B block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 2.

STW82103B pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 3.

Conversion gain against RF frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 4.

Noise figure against RF frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 5.

IIP3 against RF frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 6.

2RF-2LO response against RF frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 7.

LOA (VCOA div. by 2) closed-loop phase noise at 2.38 GHz,

(F

STEP

= 200 kHz, ICP = 3 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 8.

LOB (VCOB div. by 2) closed-loop phase noise at 2.75 GHz,

(F

STEP

= 200 kHz, ICP = 3 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 9.

Reference frequency input buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 10.

VCO divider diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 11.

PFD diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 12.

Loop filter connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 13.

VCO typical sub-band characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 14.

Data validity waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 15.

START and STOP condition waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 16.

Byte format and acknowledge waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 17.

I

2

C data and clock waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 18.

I

2

C START and STOP timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 19.

I

2

C acknowledge timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 20.

I2C first programming timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 21.

SPI input and output bit order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 22.

SPI data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 23.

SPI timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 24.

SPI first programming timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 25.

Typical STW82103B application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 26.

Standard mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 27.

Diversity mode operation with same LO frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 28.

Diversity mode operation with different LO frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 29.

External VCO standard mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 30.

External VCO diversity mode operation with same LO. . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 31.

VFQFPN-44 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

6/67 Doc ID 018517 Rev 2

STW82103B

Figure 1.

STW82103B block diagram

Block diagram

VDD_RFESD

VSS_RFESD

RF_IN

RF_VSS

RF_CT

MIXDRV_CT

VDD_MIXDRV

VSS_MIXDRV

VDD_DIV

VSS_DIV

VDD_OUTBUF

VSS_OUTBUF

OUTBUFN

OUTBUFP

EXTVCO_INP

EXTVCO_INN

VDD_VCO

VSS_VCO

VDD_IO

VSS_IO

MIX

DRV

LO

OUT

LO/2xLO

OUT

EXT

LO/VCO

BUF

DIV2

VCO

BUFF

DAC

CAL_VCO

BUF

VCO divider

REF divider

IF

AMP

IF_OUTP

IF_OUTN

VCO calibrator

CAL_VCO

DBUS

DBUS_SEL

SDA/DATA

SCL/CLK

LOAD

ADD0

ADD1

ADD2

VDD_DIG

VSS_DIG

LOCK_DET

BUF

UP

DN

CHP ICP

VDD_PLL

VSS_PLL

Doc ID 018517 Rev 2 7/67

Pin description

Figure 2.

STW82103B pin configuration

44 43 42 41 40 39 38 37 36 35 34

STW82103B

5

6

7

3

4

1

2

10

11

8

9

VDD_DAC

REXT_DAC

VDD_DIV

VDD_VCO

EXTVCO_INN

EXTVCO_INP

EXT_PD

ADD2

ADD1

ADD0

VDD_IO

STW82103B

VFQFPN44

12 13 14 15 16 17 18 19 20 21 22

VDD_IFAMP

IF_OUTP

33

32

IF_OUTN 31

NC

LOAD

30

SCL/CLK

29

28

SDA/DATA

VDD_DIG

27

26

DBUS_SEL

VDD_PLL

REF_CLK

25

24

23

8/67 Doc ID 018517 Rev 2

STW82103B Pin description

7

12

13

14

15

10

11

8

9

16

17

18

19

20

25

26

27

28

21

22

23

24

29

30

31

Table 2.

Pin No

1

2

3

4

5

6

Pin list

Name

VDD_DAC

REXT_DAC

VDD_DIV

VDD_VCO

EXTVCO_INN

EXTVCO_INP

EXT_PD

VDD_CP

LOCK_DET

REF_CLK

VDD_PLL

DBUS_SEL

VDD_DIG

SDA/DATA

SCL/CLK

LOAD

NC

IF_OUTN

ADD2

ADD1

ADD0

VDD_IO

VDD_PSCBUF

NC

NC

VDD_OUTBUF

OUTBUFN

OUTBUFP

VCTRL

ICP

REXT_CP

Description

DAC power supply

External resistance connection for DAC -

Observation

Vsupply analog1= 3.3 V

Divider by 2 power supply Vsupply analog1= 3.3 V

VCOs and External VCO Buffer power supply Vsupply analog1= 3.3 V

External VCO (LO) negative input

External VCO (LO) positive input

Diversity Slave Mode and External

VCO Modes; otherwise it must be connected to GND

Diversity Slave Mode and External

VCO Modes; otherwise it must be connected to GND

Hardware power down:

‘0’ device ON; ‘1’ device OFF

I

2

CBUS address select pin

I

2

CBUS address select pin

I

2

CBUS address select pin

Digital IO power supply

Prescaler input buffer power supply

Not connected

Not connected

Power supply for LO buffer

-

-

CMOS Input

CMOS Input

CMOS Input

CMOS Input

Vsupply digital = 3.3 V

Vsupply analog1= 3.3 V

Vsupply analog1= 3.3 V

LO Output buffer negative output

LO Output buffer positive output

Control voltage for VCOs

PLL charge pump output

External resistance connection for PLL charge pump current

-

-

-

Open collector @ 3.3 V

Open collector @ 3.3 V

Power supply for charge pump

Lock detector

Reference frequency input

PLL digital power supply

Digital Bus Interface select

Power supply for digital bus interface

I

2

CBUS /SPI data line

I

2

CBUS /SPI clock line

-

Vsupply analog1= 3.3 V

CMOS Output

Vsupply analog1= 3.3 V

CMOS Input

Vsupply digital = 3.3 V

CMOS Bidir Schmitt triggered

CMOS Input Schmitt triggered

SPI load line

Not connected

IF amplifier negative output

CMOS Input Schmitt triggered

-

Open collector @ 5 V

(1)

Doc ID 018517 Rev 2 9/67

Pin description

Table 2.

Pin No

32

33

Pin list (continued)

Name

IF_OUTP

VDD_IFAMP

Description

IF Amplifier positive output

IF Amplifier power supply

34 TEST2 Test input 2

35 TEST1 Test input 1

36 TEST_ALC Test output

37

38

39

40

41

42

43

44

RF_CT

RF_IN

VDD_RFESD

MIXDRV_CT

VDD_ALC

VDD_MIXDRV

I_PINDRV1

I_PINDRV2

RF balun central tap

RF input

RF ESD positive rail power supply

Mixer driver balun central tap

ALC power supply

Mixer driver power supply

DAC current output for external PIN Diode attenuator

DAC current output for external PIN Diode attenuator

1.

Supply voltage @ 3.3 V in low-current mode operation

STW82103B

Observation

Open collector @ 5 V

(1)

Vsupply analog1 = 3.3 V

Test purpose only; it must be connected to GND

Test purpose only; it must be connected to GND

-

-

Test purpose only; it must be connected to GND

Vsupply analog1 = 3.3 V

Vsupply analog2 = 5 V

(1)

Vsupply analog1 = 3.3 V

Vsupply analog1 = 3.3 V

PMOS Open drain

PMOS Open drain

10/67 Doc ID 018517 Rev 2

STW82103B

3 Absolute maximum ratings

Table 3.

AVCC1

AVCC2

DVCC

Tstg

Absolute maximum ratings

Symbol

ESD

(Electro-static discharge)

Parameter

Analog supply voltage

Analog supply voltage

Digital supply voltage

Storage temperature

HBM on pins 16, 17, 31, 32

HBM on pin 37, 38, 40

HBM on all remaining pins

CDM-JEDEC Standard on pin 38, 40

CDM-JEDEC Standard on all remaining pins

MM

Absolute maximum ratings

Values

0 to 4.6

0 to 6

0 to 4.6

+150

0.8

1

2

0.25

0.5

0.2

kV

V

V

V

° C

Unit

Doc ID 018517 Rev 2 11/67

Operating conditions STW82103B

Table 4.

Symbol

Operating conditions

Parameter Test conditions Min Typ Max Unit

I

I

AVCC1

AVCC2

DVCC

T

T

CC3.3V

CC5V

Θ

Θ

Θ

Ψ

Ψ

A

J

JA

JB

JC

JB

JT

Analog Supply voltage

Analog Supply voltage

Digital Supply voltage

Current Consumption at 3.3 V

-

-

-

Standard mode

External VCO standard mode

Diversity slave mode

Diversity master mode

External VCO diversity master mode

3.15

3.3

4.75

5

3.15

3.3

-

-

-

-

145

130

110

105

155

-

-

-40

-

160

90

Current Consumption

-

-

High current mode at 5 V

Low current mode at 3.3 V

Operating ambient temperature

Maximum junction temperature

Junction to ambient package thermal resistance

(1)

Multi-layer JEDEC board

Junction to board package thermal resistance

(1)

Junction to case package thermal resistance

(1)

Thermal characterization parameter junction to board

(1)

Thermal characterization parameter junction to top case

(1)

Multi-layer JEDEC board

Multi-layer JEDEC board

Multi-layer JEDEC board

Multi-layer JEDEC board -

-

-

-

33

19

3

18

0.3

3.45

V

5.25

V

3.45

V

150 mA

130 mA

120 mA

180 mA

165

185

105

85

125

-

-

-

-

-

1.

Refer to JEDEC standard JESD 51-12 for a detailed description of the thermal resistances and thermal parameters.

Data here presented are referring to a Multi-layer board according to JEDEC standard.

T

T

T

J

J

J

= T

= T

= T

A

B

T

+

+

Θ

Ψ

JA

J

+

Ψ

J

B

* Pdiss (in order to estimate T

* Pdiss (in order to estimate T

J

T

* Pdiss (in order to estimate T

J

if ambient temperature T

if board temperature T

B

A

J

if top case temperature T

and dissipated power Pdiss are known)

and dissipated power Pdiss are known)

T

and dissipated power Pdiss are known) mA mA mA

°C

°C

°

°

C/W

C/W

°C/W

°C/W

°C/W

12/67 Doc ID 018517 Rev 2

STW82103B

Table 5.

T

Digital logic levels

Symbol

Vil

Parameter

Low level input voltage

Vih

Vhyst

Vol

Voh

High level input voltage

Schmitt trigger hysteresis

Low level output voltage

High level output voltage

Operating conditions

-

-

-

-

-

Test conditions Min

-

0.8*Vdd

0.8

-

0.85*Vdd

Typ

-

-

-

-

-

Max Unit

0.2*Vdd V

-

-

0.4

-

V

V

V

V

Doc ID 018517 Rev 2 13/67

Test conditions

●

●

●

●

●

●

Unless otherwise specified the following test conditions are applied:

Vsupply digital = 3.3 V

Vsupply analog1 = 3.3 V

Vsupply analog2 = 5 V

F

IF

= 150 MHz

MIX = 0111

T ambient = 27 ° C

Refer also to

Section 11: Application information

.

STW82103B

14/67 Doc ID 018517 Rev 2

STW82103B Electrical characteristics

Note: Vsupply digital = 3.3 V, Vsupply analog1 = 3.3 V, Vsupply analog2 = 5V, F

RF

= 2500 MHz,

F

LO

= 2350 MHz, TA = +25*C, RF power = 0 dBm, unless otherwise specified.

Table 6.

-

Symbol

F

RF

F

LO

F

IF

CG

CG

Δ T

IP

1dB

IIP3

IIP3

Δ T

)

Down converter mixer and IF amplifier electrical characteristics

(1)

Parameter

RF Frequency

Conditions

-

VCOA divided by 2

Min Typ Max Unit

2300

2200 -

2700 MHz

2550 MHz

LO Frequency

IF Center Frequency

(2)

Power Conversion Gain

VCOB

F

IF

= ABS(F

LO

-F

RF

)

Rin = 50 ohm, Rout = 200 ohm

RFin = 0 dBm

2500

70

7.5

-

-

8

3000 MHz

400 MHz

8.5

dB

Power Conversion Gain over

Temperature

(3)

T= -40 to +85 °C ±0.7

dB

Input P1dB

Third-order input intercept point

(4)

High current Mode

Low current Mode

High current Mode

Low current Mode

-

14

8

23.5

25

17.5

19 -

-

-

dBm dBm

IIP3 variation over temperature

(3)

T= -40 to +85 °C ±0.5

dB nF

RF

-nF

LO

Spurious rejection at IF

(3)

NF

SSB

-

-

RF

RL

IF

RL

-

Noise figure

LO to IF Leakage

LO to RF Leakage

RF to IF Isolation

RF Return Loss

IF Return Loss

Gain Flatness for TX observation path

(5)

2F

RF

-2F

LO

F

RFin

= -5 dBm,

F

IF

= 150 MHz

3F

RF

-3F

LO

F

RFin

= -5 dBm,

F

IF

= 150 MHz

High-current mode, MIX = 0011

Low-current mode, MIX = 0011

-

-

-

-

1xLO

2xLO

Matched to 50 ohm

Matched to 200 ohm

Maximum deviation from F c

over ±10

MHz. For any F c

within each TX observation path band.

-0.05

Maximum deviation from F c

over ±30

MHz. For any F c

within each TX observation path band.

-0.10

-

-

-

-

-

-

-

80

76

-28

58

20

22

10.5

11 dB

10.5

11 dB

-45

-38

dBm

-

-

-

dBm dB dB dB

-

-

-

dBc dBc

+0.05 dB

+0.10 dB

Doc ID 018517 Rev 2 15/67

Electrical characteristics STW82103B

Table 6.

-

-

-

Symbol

ICC

MD

ICC

IFAM

Down converter mixer and IF amplifier electrical characteristics

(1)

(continued)

Parameter Conditions

Maximum deviation from linear phase at F c

over ±10 MHz. For any F c

within each TX observation path band.

Min Typ Max Unit

-0.3

+0.3

deg

Phase Flatness for TX observation path

(5)

Maximum deviation from linear phase at F c

over ±30 MHz. For any F c

within each TX observation path band.

-0.7

+0.7

deg

Gain Flatness for RX path

(5)

Phase Flatness for RX path

(5)

Mixer Driver Current

Consumption

Mixer Driver Current

Consumption (Low Current

Mode)

Maximum ripple over a 4 MHz band.

For any F c

within each RX path band.

Maximum ripple over a 4 MHz band.

For any F c

within each RX path band.

3.3 V Supply (pin 41, 42)

5 V Supply (pin 40)

3.3 V Supply (pin 41, 42)

3.3 V Supply (pin 40) -

-

-

-

-

-

-

-

45

55

20

35

0.1

0.6

-

-

-

dB pk-pk deg pk-pk mA mA mA mA

IFAMP Current Consumption

IFAMP Current Consumption

(Low Current Mode)

3.3 V Supply (pin 33)

5 V Supply (pin 31, 32)

3.3 V Supply (pin 33)

3.3 V Supply (pin 31, 32) -

-

-

10

107

6

55 -

-

-

mA mA mA mA

1.

All linearity and NF performances are intended at maximum LO amplitude (LO_A[1:0]=[11]), tuning capacitors (CAP[2:0]) programmed according to the selected frequency, mixer bias (MIX[3:0]) set to maximize performance and the device operated in high current mode. The performances of conversion gain, NF and linearity are intended at the SMA connectors of a typical application board.

2.

The IF frequency range supported by the IF Amplifier is from 70 to 400 MHz. The exact IF frequency range supported for a specific RF frequency can be calculated as F

IF

= ABS(F

LO

-F

RF

) where F

LO

is inside the specified LO frequency range.

3.

Guaranteed by design and characterization

4.

RFin = 0 dBm/tone, RF tone spacing = 5 MHz

5.

Guaranteed by design

Table 7.

Symbol

Pin diode attenuator driver (dual output current DAC) electrical characteristics

Parameters

Resolution -

Conditions Min

-

Typ

10

Max

-

Unit

Bit R

DNL

INL

-

I

FS

Differential non linearity

Integral non linearity

Full Scale current

(1)

Current Mismatch

-

-

-

-

-0.05

-0.45

0.28

-

-

-

-

-

0.05

0.45

2.8

2

LSB

LSB mA

%

-

Output voltage compliance range

0 3 V

VR

EXT_DAC

R

EXT_DAC

Icc static

Voltage Reference

REXT DAC Range

Static current consumption

-

-

(Iout = 0 mA; pin 1)

10

-

1.19

-

2.5

1.

See relationship between IDAC and R

EXT_DAC

in the Circuit Description section (Dual Output Current DAC)

V

100 k Ω

mA

16/67 Doc ID 018517 Rev 2

STW82103B Electrical characteristics

Table 8.

Symbol

Integer-N synthesizer electrical characteristics

Parameter Conditions

VCO dividers

N VCO Divider Ratio (N)

-

Reference clock and phase frequency detector

F ref

Reference input frequency

Reference input sensitivity

-

-

R Reference Divider Ratio -

F

PFD

PFD input frequency -

Prescaler 16/17

Prescaler 19/20

Prescaler 16/17

F

STEP

Frequency step

(1)

Prescaler 19/20

I

Charge pump

CP

ICP sink/source

(2)

-

V

OCP

Output voltage compliance range

Spurious

(3)

VCOs

-

-

3bit programmable

-

K

VCOA

K

VCOB

Δ T

LKA

Δ T

LKB

-

V

CTRL

I

VCO

I

DIV

2

VCOA sensitivity

VCOB sensitivity

VCOA Maximum Temperature variation for continuous lock

(4)

VCOB Maximum Temperature variation for continuous lock

(4)

VCO A Pushing

VCO B Pushing

VCO control voltage

LO Harmonic Spurious

VCO and VCO buffer current consumption

DIVIDER by 2 consumption

Higher frequency range

Intermediate frequency range

Lower frequency range

Higher frequency range

Intermediate frequency range

Lower frequency range

-

-

-

-

CALTYPE [0]

CALTYPE [1]

CALTYPE [0]

CALTYPE [1]

Amplitude [11] (pin 4)

(pin 3)

Min

256

361

-

-

-

-

-

-

-

-

0.4

-

-

-

-

-

-

-

Typ

-

-

10

0.35

2

-

F

LO

/

65551

F

LO

/

77836

19.2

1

-

-

-

-

-

0.4

-

Max

65551 -

77836 -

Unit

200 MHz

1.5

1023

Vpeak

16

F

LO

/

256

F

LO

/

361

MHz

Hz

Hz

-

-

-70

5 mA

V dd

-0.3 V

dBc

85

75

65

85

70

60

-

-

-

-

8

14

35

20

-

MHz/V

MHz/V

-

MHz/V

MHz/V

MHz/V

MHz/V

100 ° C

125

°

C

125 ° C

125 ° C

MHz/V

MHz/V

V dd

-0.3 V

-20 dBc

mA

mA

Doc ID 018517 Rev 2 17/67

Electrical characteristics STW82103B

Table 8.

Symbol

I

EXTBUF

Integer-N synthesizer electrical characteristics (continued)

Parameter Conditions Min

2 x LO output buffer (test purpose only)

F

OUT

P

OUT

RL

F

OUT

P

OUT

RL

Frequency range

Output level

Return Loss

I

2LOBUF

Current Consumption

LO output buffer

Frequency range

Output level

Return Loss

I

LOBUF

Current Consumption

External VCO (LO) buffer f

INVCO

P

IN

Frequency range

Input level

Current Consumption

-

-

Matched to 50 ohm

(pin 15, 16, 17)

-

-

Matched to 50ohm

(pin 15, 16, 17)

-

-

External VCO Buffer

(pin 4)

2.2

-

-

-

-

-

4.4

-

2.2

-

-

Typ

-

0

-

0

10

30

10

35

-

0

25

Max

3

-

-

-

-

-

5.1

-

3

-

-

Unit

GHz dBm dB mA

GHz dBm dB mA

GHz dBm mA

PLL miscellaneous

I

PLL

PLL Current Consumption

Input Buffer, Prescaler,

Digital Dividers, misc.

(pin 24)

8 mA

I

PRE

Prescaler input buffer Current

Consumption

(pin 12) 3 mA t

I

CP

LOCK

Charge Pump Current Consumption

Lock up time

(5)

CPSEL=[111], REXT_CP

= 4.7 k

Ω

(pin 21)

25 kHz PLL bandwidth; within 1ppm of frequency error

-

4

150 -

mA

µs

1.

The frequency step is related to the PFD input frequency as follows: F

STEP

=F

PFD

/2)

2.

See relationship between ICP and R

EXT_CP

in the Circuit Description section (Charge Pump)

3.

The level of spurs may change depending on PFD frequency, Charge Pump current, selected channel and PLL loop BW.

4.

When setting a specified output frequency, the VCO calibration procedure must be run first in order to select the best subrange for the VCO covering the desired frequency. Once programmed at the initial temperature T temperature range (-40

°

C to +85

°

C), the synthesizer is able to maintain the lock status if the temperature drift (in either direction) is within the limit specified by

Δ

T

0 inside the operating

LK

, provided that the final temperature T

1 is still inside the nominal range.

5.

Frequency jump form 2450 to 2300 MHz; it includes the time required by the VCO calibration procedure (7 x F

PFD

=17.5 µs with F

PFD

=400 kHz))

cycles

18/67 Doc ID 018517 Rev 2

STW82103B Electrical characteristics

Table 9.

Phase noise performance

(1)

Parameters Conditions

In band phase noise floor, closed loop

(2)

Min.

Typ.

Max.

Unit

Normalized In Band Phase Noise

Floor (LO)

In Band Phase Noise Floor (LO)

VCOA divided by 2

I

CP

=4 mA, PLL BW = 50 kHz

(including reference clock contribution)

In Band Phase Noise Floor (LO)

VCOB direct

PLL integrated phase noise

Integrated Phase Noise

(single sided)

100 Hz to 40 MHz

I

F

LO

=2.200 GHz, F

CP

STEP

=200 kHz,

=3 mA, PLL BW = 25 kHz

-224

-230+20log(N)+10log(F

-224+20log(N)+10log(F

-

-44.9

0.46

-

PFD

PFD

-

-

)

) dBc dBc dBc

/

/

° rms

Hz

Hz

LOA (2200 MHz to 2550 MHz) – open loop

Phase Noise @ 1 kHz

Phase Noise @ 10 kHz

Phase Noise @ 100 kHz

Phase Noise @ 1 MHz

Phase Noise @ 10 MHz

Phase Noise Floor @ 40 MHz

-

-

-

-

-

-

-

-

-

-

-

-

-63

-89

-113

-134

-151

-155

-

-

-

-

-

dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz

LOB (2500 MHz to 3000 MHz) – open loop

Phase Noise @ 1 kHz

Phase Noise @ 10 kHz

Phase Noise @ 100 kHz

Phase Noise @ 1 MHz

Phase Noise @ 10 MHz

Phase Noise Floor @ 40 MHz -

-

-

-

-

-

-

-

-

-

-

-64

-91

-113

-134

-153

-162 -

-

-

-

-

dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz

1.

Phase Noise SSB. VCO amplitude set to maximum value [11]. All the closed-loop performances are specified using a

Reference Clock signal at 76.8 MHz with phase noise of -144 dBc/Hz @1 kHz offset, -157 dBc/Hz @10 kHz offset and

-168 dBc/Hz of noise floor.

2.

Normalized PN = Measured LO PN – 20log(N) – 10log(F

PFD comparison frequency at the PFD input

) where N is the VCO divider ratio (N=B*P+A) and F

PFD

is the

Doc ID 018517 Rev 2 19/67

Typical performance characteristics

7 Typical performance characteristics

Note:

STW82103B

Vsupply digital = 3.3 V, Vsupply analog1 = 3.3 V, Vsupply analog2 = 5 V, F

IF

= 150 MHz,

T

A

= +25 °C, RF power = 0 dBm, unless otherwise specified.

Figure 3.

Conversion gain against RF frequency

Figure 4.

Noise figure against RF frequency

20/67 Doc ID 018517 Rev 2

STW82103B

Figure 5.

IIP3 against RF frequency

Typical performance characteristics

Figure 6.

2RF-2LO response against RF frequency

Doc ID 018517 Rev 2 21/67

Typical performance characteristics

Figure 7.

LOA (VCOA div. by 2) closed-loop phase noise at 2.38 GHz,

(F

STEP

= 200 kHz, ICP = 3 mA)

STW82103B

Figure 8.

LOB (VCOB div. by 2) closed-loop phase noise at 2.75 GHz,

(F

STEP

= 200 kHz, ICP = 3 mA)

22/67 Doc ID 018517 Rev 2

STW82103B General description

The STW82103B (see Figure 1: STW82103B block diagram on page 7

) consists of a high linearity passive CMOS mixer with integrated RF balun, an IF amplifier, a 10-bit current steering DAC with dual output, and an integrated integer-N synthesizer.

The synthesizer embeds 2 internal low-noise VCOs with buffer blocks, a divider by 2, a low noise PFD (Phase Frequency Detector), a precise charge pump, a 10-bit programmable reference divider, two programmable counters and a dual-modulus prescaler. The A-counter

(5 bits) and B counter (12 bits) counters, in conjunction with the dual modulus prescaler

P/P+1 (16/17 or 19/20), implement an N integer divider, where N = B*P+A.

The device is controlled through a digital interface (

I2C bus interface or

SPI digital interface ).

All internal devices operate with a power supply of 3.3 V except for the IF Amplifier output stage and the mixer driver stage operating at 5 V power supply in order to maximize the linearity performance. If the application requires a reduced linearity and noise figure performance the device is programmed in a low-current mode by using the minimum LO amplitude and the minimum biasing current in the IF amplifier. In low-current mode operation the device can use only the 3.3 V power supply thus dissipating less power.

8.1.1 Reference stage

The reference input stage is shown in

Figure 9 . The resistor network feeds a DC bias at the

F ref

input while the inverter used as the frequency reference buffer is AC coupled.

Figure 9.

Reference frequency input buffer

VDD

F ref

Inverter Buffer

Power Down

Doc ID 018517 Rev 2 23/67

General description STW82103B

8.1.3 Prescaler

The dual-modulus prescaler P/P+1 takes the CML clock from the VCO buffer and divides it down to a manageable frequency for the CMOS A and B counters. The modulus (P) is programmable and can be set to 16 or 19. It is based on a synchronous 4/5 core which division ratio depends on the state of the modulus input.

8.1.4

The 10-bit programmable reference counter allows the input reference frequency to be divided to produce the input clock to the PFD. The division ratio is programmed through the digital interface.

A and B counters

The A (5 bits) and B (12 bits) counters, in conjunction with the selected dual modulus (16/17 or 19/20) prescaler make it possible to generate output frequencies which are spaced only by the reference frequency divided by the reference division ratio. Thus, the division ratio and the VCO output frequency are given by the following formulae:

N = B × P + A

F

VCO

=

( B × P +

R

A ) × F

----------------------------------------------where:

F

VCO

: VCO output frequency.

P: modulus of dual modulus prescaler (16 or 19 selected through the digital interface).

B: division ratio of the main counter.

A: division ratio of the swallow counter.

F ref

: input reference frequency.

R: division ratio of the reference counter.

N: division ratio of the PLL

The following points should be noted:

●

●

●

For the VCO divider to work correctly, B

A can take any value from 0 to 31.

Two PLL division ratio (N) ranges are possible, depending on the value of P:

– 256 to 65551 (when P=16) must be higher than A.

– 361 to 77836 (when P=19).

24/67 Doc ID 018517 Rev 2

STW82103B

Figure 10.

VCO divider diagram

VCOBUF-

VCOBUF+

Prescaler

16/17 or 19/20 modulus

5-bit

A counter

General description

12-bit

B counter

To PFD

8.1.5 Phase frequency detector (PFD)

The PFD takes inputs from the reference and the VCO dividers and produces an output proportional to the phase error. The PFD includes a delay gate that controls the width of the anti-backlash pulse. This pulse ensures that there is no dead zone in the PFD transfer function.

Figure 11

is a simplified schematic of the PFD.

Figure 11.

PFD diagram

VDD

F ref_DIV

D

Up

R

Q

Delay

R

F

VCO_div

VDD D Q

Down

ABL

Doc ID 018517 Rev 2 25/67

General description STW82103B

This signal indicates that the difference between rising edges of both UP and DOWN PFD signals is found to be shorter than the fixed delay (roughly 5 ns). The Lock Detect signal is high when the PLL is locked. The Lock Detector consumes current only during PLL transients.

●

●

●

●

This (software controlled) function shuts down the following elements until the PLL achieves the lock status:

RF output stage

LO output buffer mixer

IF amplifier circuitry

Under this setting there is no signal at the IF output stage or the LO output during a frequency jump.

Note:

This block drives two matched current sources, Iup and Idown, which are controlled respectively by the UP and DOWN PFD outputs. The nominal value of the output current is controlled by an external resistor (to be connected to the REXT input pin) and the selection of one of 8 possible values by a 3-bit word.

The minimum value of the output current is: IMIN = 2*VBG/REXT_CP (VBG~1.17 V)

Table 10.

Current values for CPSEL[2:0] selection

CPSEL2 CPSEL1 CPSEL0 Current

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

I

MIN

2*I

MIN

3*I

MIN

4*I

MIN

5*I

MIN

6*I

MIN

7*I

MIN

8*I

MIN

Value for REXT=4.7 k

Ω

0.5 mA

1.00 mA

1.50 mA

2.00 mA

2.50 mA

3.00 mA

3.50 mA

4.00 mA

The current is output on pin ICP. During the VCO auto calibration, ICP and VCTRL pins are forced to VDD/2.

26/67 Doc ID 018517 Rev 2

STW82103B

Figure 12.

Loop filter connection

VDD

Buffer

General description

VCTRL

C3

Charge pump ICP

R3

R1

C1

C2

Buffer

Cal bit

8.1.9 Voltage controlled oscillators

VCO selection

●

●

Within the STW82103B two low-noise VCOs are integrated to cover a wide band from

2200 MHz to 2550 MHz after the division by 2, and from 2500 MHz to 3000 MHz:

VCO A frequency range is 4400 MHz to 5100 MHz

VCO B frequency range is 2500 MHz to 3000 MHz

VCO frequency calibration

Both VCOs can operate on 32 frequency ranges that are selected by adding or subtracting capacitors to the resonator. These frequency ranges are intended to cover the wide band of operation and compensate for process variations on the VCO center frequency.

An automatic range selection is performed when the bit SERCAL rises from ‘0’ to ‘1’ . The charge pump is inhibited and the pins ICP and VCTRL are set at a fixed calibration voltage

(VCAL). The frequency ranges are then tested to select the nearest one to the desired output frequency (F

OUT

= N*F ref

/R) with VCAL input voltage applied. After this selection, the charge pump is once again enabled and the PLL performs a fine adjustment around VCAL on the loop filter voltage to lock F

OUT

, thus enabling a fast settling time.

Two calibration algorithms are selectable by setting the CALTYPE bit.

Setting the CALTYPE bit to ‘1’ guarantees the PLL lock versus temperature variations. Once programmed at the initial temperature, T

0

, within the operating temperature range (-40 °C to

+85 °C), the synthesizer is able to maintain the lock status if the temperature drift (in either direction) is within the limit specified by

Δ

T

LK

, and provided that the final temperature, T

1

, is still inside the nominal range.

Setting the CALTYPE bit to ‘0’ fixes VCAL to the mid point of the charge pump output

(VDD/2). Optimum PLL phase noise performance versus temperature variations with a reduced

Δ

T

LK i s guaranteed in this case.

The

Δ

T

LK parameter, specific to each VCO and calibration type, in the STW82103B is

specified in Table 8: Integer-N synthesizer electrical characteristics

.

Doc ID 018517 Rev 2 27/67

General description

Figure 13.

VCO typical sub-band characteristics

STW82103B

00000

00001

01111

11111

Calibrator lock range

0.00

0.50

1.00

1.50

VCTRL (V)

2.00

2.50

3.00

3.50

The SERCAL bit should be set to ’1’ at each division ratio change. The calibration takes approximately 7 periods of the Comparison Frequency and the SERCAL bit is automatically reset to ’0’ at the end of each calibration.

The maximum allowed F

PFD

to perform the calibration process is 1 MHz. If a higher F used the following procedure should be adopted:

PFD

is

1.

Calibrate the VCO at the desired frequency with an F

PFD

lower than 1 MHz

2. Set the A, B and R dividers ratio for the desired F

PFD

For calibration details refer to Section 9.4.1: VCO calibration procedure (I

2

C interface) or

Section 10.4.1: VCO calibration procedure (SPI interface)

.

28/67 Doc ID 018517 Rev 2

STW82103B General description

VCO calibration auto-restart feature

The VCO Calibration Auto-Restart feature, once activated, allows the calibration procedure to be restarted when the Lock Detector reports that the PLL has moved to an unlock condition (trigger on ‘1’ to ‘0’ transition of Lock Detector signal).

This situation could happen if the device experiences a significant temperature variation and the CALTYPE bit is set for optimum PLL phase noise performance (CALTYPE [0]).By enabling the VCO Calibration Auto-Restart feature (through the AUTO_CAL bit), the device re-selects the proper VCO frequency sub-range, without any external user command.

This feature can be enabled only when the FPFD is lower than 1 MHz.

VCO voltage amplitude control

The voltage swing of the VCOs can be adjusted over 4 levels by means of two dedicated programming bits (PLL_A1 and PLL_A0). This setting trades current consumption with phase noise performances of the VCO. Higher amplitudes provide best phase noise while lower ones save power.

Doc ID 018517 Rev 2 29/67

General description STW82103B

Table 11

and

Table 12 give the current consumption and the phase noise at 1 MHz.

Table 11.

VCOA performance against amplitude setting (frequency = 4.6 GHz)

PLL_A[1:0]

Current

Consumption (mA)

PN @ 1 MHz

00

01

10

11

23

24

32

35

-124

-125

-127

-128

Table 12.

VCOB performance against amplitude setting (frequency = 2.8 GHz)

PLL_A[1:0]

Current

Consumption (mA)

PN @ 1 MHz

00

01

10

11

16

18

27

30

-129

-131

-133

-134

The differential output signal of the synthesizer after the Divider by 2 for VCOA and directly for VCOB is available on pins 16 and 17.

The output stage is selected by programming the PD[4:0] bits.

The output stage is an open-collector structure which is able to meet different requirements

over the desired output frequency range by proper connections on the PCB. See Figure 27:

Diversity mode operation with same LO frequencies .

Although the STW82103B includes two wideband and low-noise VCOs, external VCO use capability is also provided.

The external VCO buffer can be used to manage a signal coming from an external VCO in order to build a local oscillator signal by using the STW82103B internal synthesizer as a

PLL. This is only possible when External VCO standard mode or External VCO diversity master mode operation are selected. See

Figure 29: External VCO standard mode operation

and

Figure 30: External VCO diversity mode operation with same LO

.

If the STW82103B is operated in Diversity slave mode, the external VCO buffer manage the signal coming from the synthesizer output stage of another STW82103B device See

Figure 27: Diversity mode operation with same LO frequencies

and

Figure 30: External

VCO diversity mode operation with same LO

.

The selection of the external VCO buffer is done by setting the PD[4:0] bits.

The external VCO signal can range from 2200 MHz to 3000 MHz and its minimum power level must be -10 dBm.

30/67 Doc ID 018517 Rev 2

STW82103B General description

8.1.12 Mixer and IF amplifier

LO mixer driver

The LO signal is fed through a driver in order to achieve the high power level needed to drive the passive mixer for maximum performance of linearity and NF.

The LO Mixer Driver is coupled to the mixer with an integrated LO balun. The LO signal level is adjusted by means of an Automatic Level Control loop (ALC) controlled by the bits

LO_A[1:0].

In low current mode the configuration LO_A[1:0]=’00’ (minimum LO amplitude) should be selected and the power supply on pin 40 can be set to 3.3 V.

The LO balun resonating frequency can be adjusted by means of the bits CAP[2:0] in order to match the selected LO frequency.

Table 13.

Suggested CAP[2:0] values for LO Frequency range mixer

CAP[2:0] LO frequency range

000

001

010

011

100

101

110

111

2875 MHz ÷ 3000MHz

2750 MHz ÷ 2875 MHz

2640 MHz ÷ 2750 MHz

2530 MHz ÷ 2640 MHz

2435 MHz ÷ 2530 MHz

2350 MHz ÷ 2435 MHz

2280 MHz ÷ 2350 MHz

2200 MHz ÷ 2280 MHz

Mixer

A doubly balanced CMOS passive mixer is internally driven by the high level LO signal in order to achieve high linearity and low noise performance.

The RF integrated balun permits the removal of external components and it is internally matched to 50 ohms.

The gate bias of the CMOS devices in the mixer is programmable with 4 bits (MIX[3:0]) to optimize the input matching and the gain of the signal chain.

Higher values of gate bias (higher decimal values of MIX[3:0]) are suggested to maximize linearity and lower values to maximize the performance of Gain and NF.

Doc ID 018517 Rev 2 31/67

General description STW82103B

IF amplifier

The integrated IF stage permits a 200-ohm load to be driven (typically a SAW filter) ensuring high linearity.

It is an open collector stage (pin 31, 32) and should be biased to 5 V with choke inductors.

The typical output impedance is 200 ohms. The linearity performances are controlled by the bits IFAMP[1:0]. In low current mode the configuration IFAMP[1:0]=’00’ (minimum linearity) should be selected and the open collector stage can be biased to 3.3 V with choke inductors.

Table 14.

Linearity performance against IFAMP[1:0] configuration (typical condition)

IFAMP[1:0] Linearity performance

00

01

10

11

19 dB

21 dB

23 dB

25 dB

8.1.13 Dual output current DAC

The STW82103B embeds a 10-bit Dual Output steering current DAC especially suited to drive an external PIN diode attenuator. This provides power level calibration capability at the

RF input for the TX observation path applications.

The current sourced by the DAC is related to the R

EXT_DAC

resistor according to the following formulae (where VR

EXT_DAC

is approximately 1.19 V):

IDAC

LSB

=

2

×

3 ×

----------------------------------------

R

VR

EXT_DAC

EXT_DAC

×

64

LSB DAC current

IDAC

FS

=

2

×

3 × VR

----------------------------------------

R

EXT_DAC

×

64

Full scale current

With a 10 k Ω R

EXT_DAC

the FS current is approximately 2.8 mA.

32/67 Doc ID 018517 Rev 2

STW82103B

9 I

2

C bus interface

I2C bus interface

The I

2

C bus interface is selected by hardware connection of the pin 25 (DBUS_SEL) to 0 V.

Data transmission from a microprocessor to the STW82103B takes place through the 2 wires (SDA and SCL) I

2

C-bus interface. The STW82103B is always a slave device.

The I

2

C-bus protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as receiver. The device that controls the data transfer is known as the master and the others as slaves. The master always initiates the transfer and provides the serial clock for synchronization.

The STW82103B I

2

C bus supports Fast Mode operation (clock frequency up to 1 MHz).

9.1 I

2

C general features

Data changes on the SDA line must only occur when the SCL is LOW. SDA transitions while the clock is HIGH identify START or STOP conditions.

Figure 14.

Data validity waveform

SDA

SCL

Data line stable data valid

Change data allowed

Doc ID 018517 Rev 2 33/67

I2C bus interface

9.1.2 START and STOP conditions

Figure 15.

START and STOP condition waveform

STW82103B

SCL

SDA

START STOP

9.1.3

START condition

A START condition is identified by a HIGH to LOW transition of the data bus SDA while the clock signal SCL is stable in the HIGH state. A Start condition must precede any command for data transfer.

STOP condition

A STOP condition is identified by a transition of the data bus SDA from LOW to HIGH while the clock signal SCL is stable in the HIGH state.. A STOP condition terminates communications between the STW82103B and the Bus Master.

Byte format and acknowledge

Every byte (8 bits long) transferred on the SDA line must contain bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first.

An acknowledge bit indicates a successful data transfer. The transmitter, either master or slave, releases the SDA bus after sending 8 bits of data. During the 9th clock pulse the receiver pulls the SDA low to acknowledge the receipt of 8 bits of data.

Figure 16.

Byte format and acknowledge waveform

SCL

SDA

START

1

MSB

2 3 7 8 9

Acknowledgement from receiver

STOP

34/67 Doc ID 018517 Rev 2

STW82103B I2C bus interface

9.1.5

9.1.6

9.1.7

To start the communication between the Master and the STW82103B, the master must initiate with a START condition. Following this, the master sends onto the SDA line 8 bits

(MSB first) corresponding to the device select address and read or write mode.

The first 7 MSBs are the device address identifier, corresponding to the I

2

C-Bus definition.

For the STW82103B the address is set as ’1101A

2

A

1

A

0

’, 3-bits programmable. The 8th bit

(LSB) is the read or write operation bit (the RW bit is set to 1 in read mode and to 0 in write mode).

After a START condition the STW82103B identifies the device address on the bus and, if matched, it acknowledge the identification on SDA bus during the 9th clock pulse.

Single-byte write mode

Following a START condition the master sends a device select code with the RW bit set to 0.

The STW82103B gives an acknowledge and waits for the internal sub-address (1 byte). This byte provides access to any of the internal registers.

After reception of the internal byte sub-address the STW82103B again responds with an acknowledge. A single-byte write to sub-address 0x00 would affect DATA_OUT[47:40], a single-byte write with sub-address 0x04 would affect DATA_OUT[15:8] and so on.

S 1101A

2

A

1

A

0

0 ack sub-address byte ack DATA IN ack P

Multi-byte write mode

The multi-byte write mode can start from any internal address. The master sends the data bytes and each one is acknowledged. The master terminates the transfer by generating a

STOP condition.

The sub-address determines the starting byte. For example, a multi-byte write with subaddress 0x01 and 4 DATA_IN bytes affects 4 bytes starting at address 0x01 (registers at addresses 0x01, 0x02, 0x03 and 0x04 are modified).

S 1101A

2

A

1

A

0

0 ack sub-address byte ack DATA IN ack ..

DATA

IN ack P

Current byte address read

In the current byte address read mode, following a START condition, the master sends the device address with the RW bit set to 1 (No sub-address is needed as there is only 1 byte read register). The STW82103B acknowledges this and outputs the data byte. The master does not acknowledge the received byte, but terminates the transfer with a STOP condition.

S 1101A

2

A

1

A

0

1 ack DATA OUT No ack P

Doc ID 018517 Rev 2 35/67

I2C bus interface

9.2 I

2

C timing specifications

9.2.1 Data and clock timing specification

Figure 17.

I

2

C data and clock waveforms

SDA

SCL t ch t cwl t cwh t cs

Table 15.

I

2

C data and clock timing parameters

Symbol

T cs

T ch

T cwh

T cwl

Parameter

Data to clock set up time

Data to clock hold time

Clock pulse width high

Clock pulse width low

9.2.2 I

2

C START and STOP timing specification

Figure 18.

I

2

C START and STOP timing waveforms

SDA

SCL t start t stop

STW82103B

Min

2

2

10

5.5

Unit ns

36/67 Doc ID 018517 Rev 2

STW82103B

Table 16.

I

2

C START and STOP timing parameters

Symbol

Tstart

Tstop

Clock to data start time

Parameter

Data to clock down stop time

9.2.3 I

2

C acknowledge timing specification

Figure 19.

I

2

C acknowledge timing waveforms

SDA

SCL

8 9

I2C bus interface

Min

2

2

Unit ns t d1

Table 17.

I

2

C acknowledge timing parameters

Symbol Parameter

T d1

T d2

Ack begin delay

Ack end delay t d2

Max Unit

2

2 ns

Doc ID 018517 Rev 2 37/67

I2C bus interface

9.3 I

2

C registers

STW82103B has 9 write-only registers and 1 read-only register.

9.3.1 I

2

C register summary

The following table gives a short description of the write-only registers list.

Table 18.

I

2

C register list

Offset Register name

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

FUNCTIONAL_MODE

B_COUNTER

A_COUNTER

REF_DIVIDER

CONTROL

MUTE_&_CALIBRATION

DAC_CONTROL

MIXER_CONTROL

IFAMP_LO_CONTROL

READ_ONLY_REGISTER

Description

Functional mode register

B counter register

A counter register

Reference clock divider ratio register

PLL control register

Mute and calibration control register

DAC control register

Mixer control register

IF amplifier LO control register

Device ID and calibration status register

STW82103B

Page

on page 39

on page 39

on page 40

on page 40

on page 41

on page 42

on page 42

on page 43

on page 43

on page 44

38/67 Doc ID 018517 Rev 2

STW82103B I2C bus interface

9.3.2 I

2

C register definitions

FUNCTIONAL_MODE

7

ALC_PD

W

6

PKD_EN

W

5

Functional mode register

4 3

PD[4:0]

W

2 1 0

B11

W

Address:

Type:

Reset:

0x00

W

0x00

[7] ALC_PD : for test purpose only must be set to ’0’. (ALC ON)

[6] PKD_EN : for test purpose only must be set to ’0’. (Peak detector output on pin 36 OFF)

[5:1] PD[4:0] : bits used to select different functional modes for the STW82103B according to the following table

00000: (0 decimal) Power down mode

00001: (1 decimal) Standard Mode VCOA (VCOA and RX chain ON)

00010: (2 decimal) Standard Mode VCOB (VCOB and RX chain ON)

00011: (3 decimal). Diversity Slave Mode (ExtVCO/LO input buffer and RX Chain ON; internal synthesizer OFF)

00100: (4 decimal) Diversity Master Mode VCOA (VCOA, RX Chain and LO output buffer ON)

00101: (5 decimal) Diversity Master Mode VCOB (VCOB, RX Chain and LO output buffer ON)

00110: (6 decimal) External LO Standard Mode (RX Chain ON; PLL and ExtVCO/LO input buffer ON)

00111: (7 decimal) External LO Diversity Master Mode (RX Chain ON; PLL, ExtVCO/LO input buffer and LO output buffer ON)

[0] B11 : B counter value (bits B[10:0] in the B_COUNTER and A_COUNTER registers)

B counter register B_COUNTER

7

Address:

Type:

Reset:

Description:

6 5 4 3

B[10:3]

W

0x01

W

0x00

Most significant bits of the B counter value

2 1 0

[7:0] B[10:3] : B counter value (bit B11 in the FUNCTIONAL_MODE register, bits B[2:0] in the

A_COUNTER register)

Doc ID 018517 Rev 2 39/67

I2C bus interface STW82103B

A_COUNTER

7 6

B[2:0]

W

Address:

Type:

Reset:

Description:

5

A counter register

4 3 2

A[4:0]

W

1 0

Address:

Type:

Reset:

Description:

0x02

W

0x00

Least significant bits of the B-counter value. A-counter value.

REF_DIVIDER

7 6

[7:5] B[2:0] : B Counter value (bit B11 in the FUNCTIONAL_MODE register, bits B[10:3] in the B_COUNTER register).

[4:0] A[4:0] : A counter value

5

Reference clock divider ratio register

4

R[9:2]

W

3 2 1 0

0x03

W

0x00

Most significant bits of the reference clock divider ratio value.

[7:0] R[9:2] : Reference clock divider ratio (bits R[1:0] in the CONTROL register)

40/67 Doc ID 018517 Rev 2

STW82103B I2C bus interface

CONTROL

7

[R1:0]

W

Address:

Type:

Reset:

Description:

6 5

PLL control register

4 3

PLL_A[1:0]

W

2

CPSEL[2:0]

W

1 0

PSC_SEL

W

0x04

W

0x00

Least significant bits of the reference clock divider ratio value and PLL control bits.

[7:6] R[1:0] : Reference clock divider ratio (bits R[9:2] in the REF_DIVIDER register)

[5:4] PLL_A[1:0] : VCO amplitude

[3:1] CPSEL[2:0] : Charge Pump output current

[0] PSC_SEL : Prescaler Modulus select (‘0’ for P=16, ‘1’ for P=19)

The LO output frequency is programmed by setting the proper value for A, B and R according to the following formula :

F

LO

= D

R

⋅ ( B ⋅ P + A ) ⋅

F

----------

R

Where:

– D

R equals 0.5 for VCOA (VCO output frequency divided by 2) or 1 for VCOB (VCO output frequency)

– P is the selected Prescaler Modulus

Doc ID 018517 Rev 2 41/67

I2C bus interface

MUTE_&_CALIBRATION

7 6 5

Mute and calibration control register

4 3 2 1

STW82103B

0

W

Address:

Type:

Reset:

Description:

W W W W W W W

Address:

Type:

Reset:

Description:

0x05

W

0x00

For test purposes only

DAC_CONTROL

7 6

[7] CALTYPE : Calibration algorithm selection

0: standard calibration to optimize the phase noise versus temperature

1: enhanced calibration to maximize the Δ T

LK

range

[6] SERCAL :

1: starts the VCO auto-calibration (automatically reset to ’0’ at the end of calibration)

[5] SELEXTCAL : test purpose only; must be set to ‘0’

[4] MUTE_EN :

0: mute function disabled

1: mute function enabled

[3] MUTE_TYPE : must be set to '1' while the mute function is enabled (mute the IF output on Unlock state)

[2] MUTE_LOOUT_EN :

To be set to ’1’ to mute the LO output buffer

[1] MUTE_MIX_EN :

To be set to ’1’ mute the Mixer circuitry

[0] MUTE_IFAMP_EN : To be set to '1' to mute the IF amplifier circuitry

5

DAC control register

4 3

DAC[9:2]

W

2 1 0

0x06

W

0x00

Most significant bits of the DAC control word

[7:0] DAC[9:2] : DAC input word for DAC current control (bits DAC[1:0] in the

MIXER_CONTROL register).

42/67 Doc ID 018517 Rev 2

STW82103B

MIXER_CONTROL

7 6 5

Mixer control register

4 3 2 1

I2C bus interface

0

W W W W

Address:

Type:

Reset:

Description:

0x07

W

0x00

Least significant bits of DAC control word and mixer control bit fields

[7:6] DAC[1:0] : DAC input word for DAC current control (bits DAC[9:2] in the DAC_CONTROL register)

[5:2] MIX[3:0] : Mixer bias control value

[1] PD_DAC : DAC power down

[0] CAL_AUTOSTART_EN : VCO calibration auto-restart enable (’1’ active), permits to automatically restart the VCO calibration procedure in case of PLL unlock

IFAMP_ LO_CONTROL

7 6

IFAMP[1:0]

W

5

IF amplifier LO control register

3 2 4

CAP[2:0]

W

LO_A[1:0]

W

1 0

LPMUX_EN

W

Address:

Type:

Reset:

0x08

W

0x00

[7:6] IFAMP[1:0] : power consumption/linearity control

[5:3] CAP[2:0] : Tuning capacitors control

[2:1] LO_A[1:0] : LO amplitude control

[0] LPMUX_EN : for test purpose only (low power mode for MUX); must be set to ’0’

Doc ID 018517 Rev 2 43/67

I2C bus interface STW82103B

READ-ONLY REGISTER

7 6

ID[1:0]

R

5

LOCK_DET

R

Device ID and calibration status register

4 3 2

INTCAL[4:0]

R

1

Address:

Type:

Reset:

Description:

0

0x09

R

0x00

This register is automatically addressed in the ‘current byte address read mode’

[7:6] ID[1:0] : device identification ’11’ for STW82103B

[5] LOCK_DET : ’1’ when PLL is locked

[4:0] INTCAL[4:0] : internal value of the VCO calibration control word

44/67 Doc ID 018517 Rev 2

STW82103B

9.4

9.4.1

9.4.2

I2C bus interface

Device calibration through the I

2

C interface

VCO calibration procedure (I

2

C interface)

The calibration of the VCO center frequency is activated by setting the SERCAL bit of the

MUTE & CALIBRATION register to ’1’.

To program the device ensuring a correct VCO calibration, the following procedure is required before every channel change:

1.

Program all the Registers using a multi-byte write sequence with the desired setting:

– Functional Mode

– B and A counters

– R counter

– VCO amplitude

– Charge Pump

– Prescaler Modulus

– DAC

– Mixer and LO Control

– all bits of the MUTE & CALIBRATION Register (0x05) set to ’0’.

2. Program the MUTE & CALIBRATION register using a single-byte write sequence (subaddress 0x05) with the SERCAL bit set to ’1’.

The maximum allowed PFD frequency (F

PFD

) to perform the calibration process is 1 MHz. If the desired F

PFD

is higher than 1 MHz the following steps are needed:

3. Perform all the step of the above calibration procedure programming the desired VCO frequency with a proper setting of R, B and A counter so that F

PFD

results lower than

1 MHz.

4. Once calibration is completed, program all the Registers by using a multi-byte write sequence (Functional Mode, B and A counters, R counter, VCO amplitude, Charge

Pump, Prescaler Modulus, DAC, Mixer and LO Control) with the proper settings for the desired VCO and PFD frequencies.

Power ON sequence (I

2

C interface)

At power-on the device is configured in power-down mode.

In order to guarantee correct setting of the internal circuitry after the power on, the following steps must be followed:

1.

Power up the device

2. Provide the Reference clock

3. Implement the first programming sequence with a proper delay time between the STOP condition of the multi-byte write sequence and that of the single-byte write sequence

(see Figure 20

). The T delay

value must respect the following condition:

T delay

>

1023

×

F ref

F ref

is the reference clock frequency.

Doc ID 018517 Rev 2 45/67

I2C bus interface

Figure 20.

I2C first programming timing

START STOP START

CLK

STW82103B

STOP

DATA MSB LSB

Tdelay > 1023/F ref

MSB

Single-byte sequence

LSB

Multi-byte sequence

9.4.3 VCO calibration auto-restart procedure (I

2

C interface)

The VCO calibration auto-restart feature is enabled in two steps:

1.

Set the desired frequency ensuring VCO calibration procedure as described above

(

Section 9.4.1

).

2. Program the MIXER_CONTROL register (sub-address 0x07) using a single-byte write sequence with the CAL_AUTOSTART_EN bit set to '1' while keeping the others unchanged.

46/67 Doc ID 018517 Rev 2

STW82103B

10 SPI digital interface

SPI digital interface

10.1 SPI general features

The SPI digital interface is selected by hardware connection of the pin 25 (DBUS_SEL) to

3.3 V.

The STW82103B IC is programmed by means of a high-speed serial-to-parallel interface with write option only. The 3-wires bus can be clocked at a frequency as high as 100 MHz to allow fast programming of the registers containing the data for RF IC configuration.

The programming of the chip is done through serial words with whole length of 26 bits. The first 2 MSB represent the address of the registers. The others 24 LSB represent the value of the registers.

Each data bit is stored in the internal shift register on the rising edge of the CLOCK signal.

On the rising edge of the LOAD signal the outputs of the selected register are sent to the device.

Figure 21.

SPI input and output bit order

Last bit sent

(LSB) 0

1

2 23

24

25 (MSB)

DATA

A1

LOAD

Address decoder

LOAD #4

Reg. #0

Reg. #1

00 (LSB)

Reg. #4

Doc ID 018517 Rev 2 47/67

SPI digital interface

Figure 22.

SPI data structure

STW82103B

MSB

Address Data for register (24 bits)

LSB

A1 A0 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Note: MSB is sent first

Table 19.

Address decoder and outputs

Address

A1

0

A0

0

DATABITS

D23-D0

24

N o

Name

0 ST1

0

1

1

1

0

1

24

24

24

1 ST2

2 ST3

3 ST4

Outputs

Function

DAC, Mixer, Tuning capacitors, LO_amplitude

Reference divider, VCO amplitude, VCO Calibration, Charge

Pump current, Prescaler Modulus, Mute functions

Functional modes, VCO dividers

Reserved

48/67 Doc ID 018517 Rev 2

STW82103B

10.2 SPI timing specification

10.2.1 Data, clock and load timing

Figure 23.

SPI timing waveforms t setup t hold

MSB MSB - 1

DATA

CLOCK t clk

LOAD

LSB t clk_loadr

Table 20.

SPI timing parameters

Parameter Description t setup t hold t clk t load t clk_loadr t clk_loadf

DATA to CLOCK setup time

DATA to clock hold time

CLOCK cycle period

LOAD pulse width

CLOCK to LOAD rising edge

CLOCK to LOAD falling edge

SPI digital interface t load t clk_loadf

Min.

1

0.5

10

3

0.6

2.5

Typ.

-

-

-

-

-

-

Max.

-

-

-

-

-

-

Unit ns ns ns ns ns ns

Doc ID 018517 Rev 2 49/67

SPI digital interface STW82103B

Table 21.

SPI register list

Offset Register name

0x00

0x01

0x10

ST1

ST2

ST3

SPI register 1

SPI register 2

SPI register 3

Description Page

on page 50

on page 51

on page 52

ST1 SPI register 1

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Address:

Type:

Reset:

W

0x00

W

0x00

W W W W

[23:14] DAC[9:0] : DAC input word

[13:10] MIX[3:0] : Mixer bias control

[9] PWD_DAC : DAC power down

[8] CAL_AUTOSTART_EN : VCO calibration auto-restart enable

[7:6] IF[1:0] : Power consumption/linearity control

[5:3] CAP[2:0] : Tuning capacitors control

[2:1] LO_A[1:0] : LO amplitude control

[0] LPMUX_EN : For test purpose only. Must be set to ‘0’

W W W

50/67 Doc ID 018517 Rev 2

STW82103B SPI digital interface

ST2 SPI register 2

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Address:

Type:

Reset:

W

0x01

W

0x00

W W W W W W W W W W W

[23:14] R[9:0] : Reference clock divider ratio

[13:12] PLL_A[1:0] : VCO amplitude control

[11:9] CPSEL[2:0] : Charge pump output current control

[8] PSC_SEL : Prescaler modulus select (‘0’ for P=16, ‘1’ for P=19)

[7] CAL_TYPE : Calibration algorithm selection

0: standard calibration to optimize the phase noise versus temperature

1: enhanced calibration to maximize the

Δ

T

LK

range

[6] SERCAL : at ‘1’ starts the VCO auto-calibration (automatically reset to ‘0’ at the end of calibration)

[5] SELEXTCAL : test purpose only. Must be set to ‘0’

[4] MUTE_EN :

0: mute function disabled

1: mute function enabled

[3] MUTE_TYPE : must be set to '1' while the mute function is enabled (mute IF output on

Unlock state)

[2] MUTE_LOOUT_EN :

To be set to ’1’ to mute the LO output buffer

[1] MUTE_MIX_EN :

To be set to ’1’ to mute the Mixer circuitry

[0] MUTE_IFAMP_EN :

To be set to ’1’ to mute the IF amplifier circuitry

Doc ID 018517 Rev 2 51/67

SPI digital interface STW82103B

ST3 SPI register 3

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

W W

Address:

Type:

Reset:

W

0x10

W

0x00

W W

[23] ALC_PD : Test purpose only; must be set to ‘0’ (ALC ON)

[22] PKD_EN : for test purpose only; must be set to ‘0’

[21:17] PD[4:0] :

00000: (0 decimal) Power down mode

00001: (1 decimal) Standard Mode VCOA (VCOA and RX chain ON)

00010: (2 decimal) Standard Mode VCOB (VCOB and RX chain ON)

00011: (3 decimal). Diversity Slave Mode (ExtVCO/LO input buffer and RX Chain ON; internal synthesizer OFF)

00100: (4 decimal) Diversity Master Mode VCOA (VCOA, RX Chain and LO output buffer ON)

00101: (5 decimal) Diversity Master Mode VCOB (VCOB, RX Chain and LO output buffer ON)

00110: (6 decimal) External LO Standard Mode (RX Chain ON; PLL and ExtVCO/LO input buffer ON)

00111: (7 decimal) External LO Diversity Master Mode (RX Chain ON; PLL, ExtVCO/LO input buffer and LO output buffer ON)

[16:5] B[11:0] : B counter bits

[4:0] A[4:0] : A Counter Bits

52/67 Doc ID 018517 Rev 2

STW82103B SPI digital interface

10.4 Device calibration through the SPI interface

10.4.1 VCO calibration procedure (SPI interface)

The calibration of the VCO center frequency is activated by setting to ’1’ the SERCAL bit

(ST2 Register bit [6]).

In order to program properly the device while ensuring the VCO calibration, the following procedure is required before every channel change:

1.

Program the ST1 Register with the desired setting (DAC, Mixer, LO Control)

2. Program the ST3 Register with the desired setting (Functional mode, B and A counters)

3. Program the ST2 Register with the desired setting (R counter, VCO amplitude, Charge

Pump, Prescaler Modulus) and SERCAL bit set to ’1’

The maximum allowed PFD frequency (F

PFD

) to perform the calibration process is 1 MHz; if the desired F

PFD

is higher than 1 MHz the following steps are needed:

4. Perform all the steps of the above calibration procedure programming the desired VCO frequency with a proper setting of R, B and A counter so that F

PFD

results lower than 1

MHz.

5. Once calibration is completed program the device with the proper setting for the desired

VCO and PFD frequencies according to the following steps: a) Program the ST3 Register with the desired setting (Functional mode, B and A counters) b) Program the ST2 Register with the desired setting (R counter, VCO amplitude,

Charge Pump, Prescaler Modulus) with the SERCAL bit set to ’0’.

At power-on the device is configured in power-down mode.

In order to guarantee correct setting of the internal circuitry after the power on, the following steps must be followed:

1.

Power up the device

2. Provide the reference clock

3. Implement the first programming sequence with a proper delay time between the ST3 and ST2 load rising edges (see

Figure 24

). The T delay

value must respect the following condition:

T delay

> 1023 ×

F ref

F ref

is the reference clock frequency.

Doc ID 018517 Rev 2 53/67

SPI digital interface

Figure 24.

SPI first programming timing

ST3

DATA MSB MSB-1 LSB-1 LSB

STW82103B

ST2

MSB MSB-1

T delay

> 1023/F ref

LSB-1 LSB

LOAD

10.4.3 VCO calibration auto-restart procedure (SPI interface)

The VCO calibration auto-restart feature is enabled in two steps:

1.

Set the desired frequency ensuring VCO calibration as described in

Section 10.4.1

.

2. Program the ST1 register with the CAL_AUTOSTART_EN bit set to '1' while keeping unchanged the others.

54/67 Doc ID 018517 Rev 2

STW82103B Application information

Figure 25.

Typical STW82103B application circuit

C1 C2 C3

C1 C2 C3

3.3V_LN4

5V_1

RF_IN

C19

3.3V_LN1

C1 C2 C3

C1 C2 C3

44 43 42 41 40 39 38 37 36 35 34

3.3V_LN3

C1 C2 C3

External VCO

X1

X2

X3

NC

6

U1

1

5

2

4

3

X4

3.3V_LN1

C1 C2 C3

C4

R1

C5

3.3V_LN1

1

VDD_DAC

2

REXT_DAC

3

VDD_DIV

4

VDD_VCO

5 EXTVCO_INN

6 EXTVCO_INP

7 EXT_PD

8 ADD2

9 ADD1

10 ADD0

11 VDD_IO

3.3V_LN1

C1 C2 C3

VFQFPN-44

VDD_IFAMP 33

IF_OUTP

32

IF_OUTN 31

NC 30

5V_2

C15 C16 C17

L3

L4

C18

6

U3

1

5

4 3

IF_out

2 NC

LOAD

SLC/CLK

SDA/DATA

29

28

27

VDD_DIG 26

DBUS_SEL 25

VDD_PLL

24

REF_CLK 23

C14

LOAD

C13

R10 SLC/CLK

C12

R9

SDA/DATA

R8

3.3V_LN2

C11

SPI

3.3V_LN2

I2C

C1 C2 C3

3.3V_LN2

REF_CLK

C1 C2 C3

R7

12 13 14 15 16 17 18 19 20 21 22

3.3V_LN1

3.3V_LN1

R6

LOCK_DET

3.3V_LN1

C1 C2 C3

C1 C2 C3

R2

L1

R3

L2

R4

C9

C6

C1 C2 C3

C7

X5

3

2

1

U2

6

4

5

X6

NC

C8

R5

C10

X7

X8

LO_Output

Doc ID 018517 Rev 2 55/67

Application information

Table 22.

Application circuit component values

Designation Quantity Description

X3

X4

X5

X6, X8

X7

X9

L1, L2

L3, L4

U3

X1

X2

R6

R8, R9, R10

U1, U2

C1, C15

C2, C11

C3

C4,C5

C6, C7

C8

C9

C10

C12, C13, C14

C16

C17

C18

C19

R1

R2,R3,R7

R4

R5

2

2

2

0

1

1

0

0

1

3

2

1

1

1

1

1

1

3

1

1

1

1

1

3

1

1

2

2

2

2

1

4.7 µF capacitors COG (0402)

1 nF capacitors COG (0402)

10 pF capacitor COG (0402)

3.3 pF capacitors COG (0402)

1.1 pF capacitor COG (0402)

270 pF capacitor COG (0402)

2.7 nF capacitor COG (0402)

68 pF capacitor COG (0402)

15 pF capacitors COG (0402)

100 nF capacitor COG (0402)

100 pF capacitor COG (0402)

180 pF capacitor COG (0402)

6.8 pF capacitor COG (0402)

100 ohm resistors (0402)

50 ohm resistors (0402)

2.2 kohm resistor (0402)

8.2 kohm resistor (0402)

4.7 kohm resistor (0402)

100 ohm resistors (0402)

Balun JTI - 2450BL15K100

Balun ADT4-5WT

7.5 nH inductor CS (0402)

0.2 pF capacitor COG (0402)

10 nH inductor CS (0402)

NC

NC

12 nH inductor CS (0402)

NC

1 pF capacitor COG (0402)

11 nH inductors CS (0402)

220 nH inductors CS (1206)

STW82103B

Supplier

Murata Manufacturing Co., Ltd

Murata Manufacturing Co., Ltd

-

-

-

-

-

-

JOHANSON TECHNOLOGY

Mini Circuits

Coilcraft, Inc

Murata Manufacturing Co., Ltd

-

-

Coilcraft, Inc

-

Coilcraft, Inc

Murata Manufacturing Co., Ltd

Coilcraft, Inc

Note: 1 For optimum performance a low-noise 3.3 V power supply must be used.

2 The 3.3 V and 5 V power supplies are split in order to maximize the isolation between RF,

LO, IF and digital sections.

56/67 Doc ID 018517 Rev 2

STW82103B Application information

The STW82103B can be used in Standard Mode for both RX path and TX observation path

(RX Chain ON and Synthesizer ON).

In such a case the 10-bit internal DAC can drive an external PIN diode attenuator in order to calibrate the signal level at the input of the device.

Figure 26.

Standard mode operation

RF_IN2

I_PINDRV1

I_PINDRV2

RF_IN

RF_IN

RF_VSS

RF_CT

5V

MIXDRV_CT

DAC

MIX

DRV

DIV2

PLL

STW82103B

IF AMP

IF_OUTP

IF_OUTN

DBUS_SEL

SDA/DATA

SCL/CLK

LOAD

5V

DBUS

VCO calibrator

CAL_VCO

REF_CLK

BUF

LOCK_DET

PFD

UP

DN

CHP

REXT_CP

4:1 IF_OUT

50

Ω

VCO

BUFF

VCTRL

CAL_VCO

ICP

Doc ID 018517 Rev 2 57/67

Application information STW82103B

11.3 Diversity mode operation with same LO frequency

The STW82103B supports the Diversity mode with the same LO frequency by using one

STW82103B in Master Mode (RX Chain ON, Synthesizer ON and LO output buffer ON) and the other in Slave Mode (RX Chain ON, Synthesizer OFF and EXT VCO/LO buffer ON). This operation mode is suitable for antenna diversity.

Figure 27.

Diversity mode operation with same LO frequencies

RF_IN_M

RF_IN

RF_VSS

RF_CT

STW82103B Master

IF AMP

IF_OUTP

IF_OUTN

5V

4:1 IF_M

50

Ω

5V

MIXDRV_CT to DAC

DBUS

DBUS_SEL

SDA/DATA

SCL/CLK

LOAD

MIX

DRV

VCO calibrator

CAL_VCO

3.3V

50

Ω

50

Ω

OUTBUFP

OUTBUFN

LO

OUT

DIV2

BUF

REF_CLK

LOCK_DET

PLL PFD

UP

DN

CHP

REXT_CP

VCO

BUFF

VCTRL

CAL_VCO

ICP

EXTVCO_INP

100

Ω

EXTVCO_INN

EXT

LO/VCO

BUF

RF_IN_S

5V

MIXDRV_CT

RF_IN

RF_VSS

RF_CT

58/67

MIX

DRV

STW82103B Slave

Doc ID 018517 Rev 2

DBUS

DBUS_SEL

SDA/DATA

SCL/CLK

LOAD

IF AMP

IF_OUTP

IF_OUTN

5V

4:1 IF_S

50

Ω

STW82103B Application information

11.4 Diversity mode operation with different LO frequencies

The STW82103B is particularly suitable for Diversity schemes using different LO frequencies such as the Interferer Diversity. In these schemes two STW82103Bs are used, each one set in Standard Mode and with different LO frequencies.

Figure 28.

Diversity mode operation with different LO frequencies

RF_IN1 RF_IN

RF_VSS

RF_CT

5V

MIXDRV_CT

LO1

MIX

DRV

STW82103B Master

IF AMP

VCO calibrator

CAL_VCO

DBUS

IF_OUTP

IF_OUTN

5V

DBUS_SEL

SDA/DATA

SCL/CLK

LOAD

4:1 IF_OUT1

50

Ω

REF_CLK

BUF

DIV2

LOCK_DET

PLL PFD

UP

DN

CHP

REXT_CP

VCO

BUFF

RF_IN2

RF_IN

RF_VSS

RF_CT

5V

MIXDRV_CT

VCTRL

CAL_VCO

ICP

LO2

MIX

DRV

DIV2

STW82103B Diversity

PLL

IF AMP

IF_OUTP

IF_OUTN

5V

DBUS_SEL

SDA/DATA

SCL/CLK

LOAD

4:1 IF_OUT2

50 Ω

VCO calibrator

CAL_VCO

DBUS

BUF

REF_CLK

LOCK_DET

PFD

UP

DN

CHP

REXT_CP

VCO

BUFF

VCTRL

CAL_VCO

ICP

Doc ID 018517 Rev 2 59/67

Application information STW82103B

11.5 External VCO standard mode operation

The STW82103B can be used in Ext VCO Mode for both RX path and TX observation path

(RX Chain ON, Synthesizer ON, EXT VCO/LO buffer ON and with an external VCO).

In such a case the 10-bit internal DAC can drive an external PIN diode attenuator in order to calibrate the signal level at the input of the device.

Figure 29.

External VCO standard mode operation

RF_IN2

I_PINDRV1

I_PINDRV2

RF_IN

RF_IN

RF_VSS

RF_CT

5V

MIXDRV_CT

DAC

MIX

DRV

EXTVCO_INP

EXT

LO/VCO

BUF

EXTVCO_INN

EXTERNAL

VCO

STW82103B

PLL

IF AMP

DBUS

IF_OUTP

IF_OUTN

DBUS_SEL

SDA/DATA

SCL/CLK

LOAD

5V

4:1 IF_OUT

50 Ω

REF_CLK

BUF

LOCK_DET

PFD

UP

DN

CHP

REXT_CP

ICP

60/67 Doc ID 018517 Rev 2

STW82103B Application information

11.6 External VCO diversity mode operation with same LO

The STW82103B can be used in Diversity mode using one STW82103B in Master Mode

(RX Chain ON, Synthesizer ON, EXT VCO/LO buffer ON, LO output buffer ON and with an external VCO) and the other one in Slave Mode (RX Chain ON, Synthesizer OFF and EXT

VCO/LO buffer ON).

Figure 30.

External VCO diversity mode operation with same LO

RF_IN_M

RF_IN

RF_VSS

RF_CT

5V

MIXDRV_CT

3.3V

50

Ω 50

Ω

OUTBUFP

OUTBUFN

LO/2xLO

OUT

MIX

DRV

STW82103B Master to DAC

PLL

IF AMP

DBUS

IF_OUTP

IF_OUTN

DBUS_SEL

SDA/DATA

SCL/CLK

LOAD

5V

4:1 IF_M

50

Ω

REF_CLK

BUF

LOCK_DET

PFD

UP

DN

CHP

REXT_CP

VCO

BUFF

EXTVCO_INP EXTVCO_INN

ICP

EXTERNAL

VCO

EXTVCO_INP

100 Ω

EXTVCO_INN

EXT

LO/VCO

BUF

STW82103B Slave

DBUS

DBUS_SEL

SDA/DATA

SCL/CLK

LOAD

MIX

DRV

RF_IN_S

5V

MIXDRV_CT

RF_IN

RF_VSS

RF_CT

IF AMP

IF_OUTP

IF_OUTN

5V

4:1 IF_S

50 Ω

Doc ID 018517 Rev 2 61/67

Evaluation kit STW82103B

●

●

●

An evaluation kit can be delivered upon request, including the following:

Evaluation board

GUI (graphical user interface) to program the device

PLLSim software for PLL loop filter design and noise simulation

When ordering, please specify the following order code:

Table 23.

Evaluation kit order code

Part number

STW82103B-EVB

Description

STW82103B evaluation kit, 2.3 to 2.7 GHz RF frequency range

62/67 Doc ID 018517 Rev 2

STW82103B

13 Package mechanical data

Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK

® specifications, grade definitions and product status are available at: www.st.com.

ECOPACK

®

is an ST trademark.

Figure 31.

VFQFPN-44 package outline

Doc ID 018517 Rev 2 63/67

Package mechanical data STW82103B

Table 24.

VFQFPN-44 package dimensions

Dimensions in mm

Symbol

Min Typ b

D

D1

D2

A

A1

A2

A3

L

P

E2

E3 e

D3

E

E1

K (degree) ddd

-

6.85

-

3.80

-

-

0.35

-

-

-

0.18

6.85

-

3.80

0.80

-

-

-

4.90

7.00

6.750

3.90

4.90

0.50

0.55

-

-

-

0.90

0.02

0.65

0.200

0.25

7.00

6.750

3.90

Max

-

7.15

-

4.00

-

-

0.75

0.60

12

0.08

0.30

7.15

-

4.00

1.00

0.05

1.00

-

Note: 1 VFQFPN stands for Thermally Enhanced Very thin Fine pitch Quad Flat Package No lead.

Very thin: A=1.00 Max.

2 Details of terminal 1 identifier are optional but must be located on the top surface of the package by using either a mold or marked features.

64/67 Doc ID 018517 Rev 2

STW82103B Revision history

Table 25.

Document revision history

Date

11-Mar-2011

19-Apr-2012

Revision

1

2

Changes

First release

Cover page:

– IIP3 value changed to +25 dBm

– 2FRF-2FLO spurious rejection changed to 80 dBc

– Noise figure NF changed to 10.5 dB

– Removed ‘Preliminary Data’ tags.

Table 3 moved to new Section 3: Absolute maximum ratings

Section 2.1 becomes Section 4: Operating conditions

Section 2.2 becomes Section 5: Test conditions

Section 2.3 becomes Section 6: Electrical characteristics

Table 4: Operating conditions updated current consumption:

– I

CC3.3V

. Updated typical values of diversity master modes. Added maximum values.

– I

CC5V

. Updated typical and added maximum values.

Section 6: Electrical characteristics

. Added note about Vsupply, RF frequency range, ambient temperature and RF power conditions.

Table 6: Down converter mixer and IF amplifier electrical characteristics :

updated:

– CG added minimum and max values.

– IP

1dB updated high-current mode value

– IIP3 added minimum values and updated typical values

– nF RF -nF LO modified typical values

– NF

SSB

added maximum values

– LO to RF leakage typical value modified

– RF to IF isolation typical value modified

– IF

RL typical value modified

– ICC

MD

3.3 V on pins 41 and 42, modified typical values

– ICC

IFAM

5 V supply value on pins 31 and 32, modified typical value

Table 8: Integer-N synthesizer electrical characteristics

updated:

– K

VCOA

typical values for high and intermediate frequency ranges

– K

VCOB

typical values for all frequency ranges

– Δ T

LK split into Δ T maximum values.

LK A and Δ T

LK B

(for VCOA and VCOB). Specified as

– modified table footnote 4

Table 9: Phase noise performance updated typical values of:

– Integrated Phase Noise (single sided) 100 Hz to 40 MHz

– LOA open-loop phase noise @ 1 kHz, 10 kHz, 100 kHz, 10 MHz and phase noise floor @ 40 MHz

– LOB open-loop phase noise @ 1 kHz, 10 kHz, 100 kHz, 1 MHz, 10 MHz and phase noise floor @ 40 MHz

Doc ID 018517 Rev 2 65/67

Revision history STW82103B

Table 25.

Document revision history (continued)

Date

19-Apr-2012

Revision

2

Changes

Added Section 7: Typical performance characteristics

.

Section 8.1.9: Voltage controlled oscillators

. Modified :

– VCO frequency calibration

– VCO calibration auto-restart feature

–

Table 12: VCOB performance against amplitude setting (frequency = 2.8

GHz) values of PN @1 MHz

Table 12: VCOB performance against amplitude setting (frequency = 2.8 GHz) ,

modified values of linearity performance.

Section 9.3.2: I

2

C register definitions . Updated description of bitfield CALTYPE

and MUTE_TYPE in registers MUTE_&_CALIBRATION

Added Section 9.4.2: Power ON sequence (I

2

C interface)

– modified

Figure 23: SPI timing waveforms

– modified

Table 20: SPI timing parameters

minimum values of t clk_loadr and t clk_loadf.

Section 10.3.2: SPI register definitions

: updated

– description of bitfields CALTYPE and MUTE_TYPE in register ST2

– description of bitfield PD[4:0] in register ST3

Added Section 10.4.2: Power ON sequence (SPI interface)

Added Section 12: Evaluation kit

.

66/67 Doc ID 018517 Rev 2

STW82103B

Please Read Carefully:

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