STMicroelectronics LEOAD128 Datasheet
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LEOAD128
LEOAD128
Datasheet
Rad-hard plastic 8-channel, 1 Msps 12-bit ADC
Features
• 12-bit SAR architecture
• 1 Msps conversion rate
• 8-to-1-channel input MUX
• 3.3 V operating supply
• SPI, serial digital output
• Power-down function
• Nickel/palladium/gold-lead-finished (NiPdAu), whisker-free
• Gold-wires
• RML <1% and CVCM <0.1% guaranteed outgassing
• 50 krad (Si) total ionizing dose
• SEL-free up to 62.5 MeV.cm²/mg
• Mass: 80 mg
• Compliant with ST-LEO-specification
Application
• Low earth orbit (LEO) applications, telemetry, housekeeping
Description
The LEOAD128 is a low power, multiplexed 8-input pure CMOS 12-bit analog-todigital converter specified for conversion from 50 ksps to 1 Msps. The architecture is based on a successive-approximation register with internal track-and-hold. The output serial data is straight binary and is compatible with SPI™.
The analog and digital power supplies operate from 2.7 V to 3.6 V, drawing a current consumption of only 2 mA maximum.
The LEOAD128 can operate over a large temperature range of -40 °C to +125
°C and it is housed in plastic TSSOP-20, thin-shrink small outline package, 20 leads, using golden bonding and nickel/palladium/golden-lead-finishing to prevent from whiskers.
The LEOAD128 is compliant with the ST-LEO-specification, dedicated specification for space-ready rad-hard plastic products. This AEC-Q100-based specification offers a specific trade-off among footprint size savings, cost of ownership and quality assurance together with radiation hardness and large quantity capability.
DS13668 - Rev 2 - September 2021
For further information contact your local STMicroelectronics sales office.
www.st.com
1
LEOAD128
Functional description
Functional description
Figure 1. Pin connections (top view)
IN0
IN7
NC
/CS
AVCC
AGND
IN0
IN1
IN2
IN3
IN4
NC
6
7
4
5
8
9
1
2
3
10
20
19
18
17
16
15
14
13
12
11
NC
SCLK
DOUT
DIN
DVCC
DGND
IN7
IN6
IN5
NC
NC: not internally connected.
The pin can be externally connected to any potential.
Figure 2. Block diagram
Input
Mux.
T /H
AG ND
12 bit
S AR
ADC
C ontrol
Logic
AVC C
AG ND
DVC C
/C S
S C LK
DIN
DOUT
DG ND
DS13668 - Rev 2 page 2/20
DS13668 - Rev 2
LEOAD128
Functional description
Bit
Symbol
7 (MSB)
Any code except 11
6
Table 1. Control register bits
5
ADD2
4
ADD1
3
ADD0
2 1
Any code except 001
0
Table 2. Control register bit description
Bit Symbol Description
7, 6, 2, 1, 0 DONTC Do not care, except forbidden codes provided in
Table 1. Control register bits
5
4
3
ADD2
ADD1
ADD0
They determine which input channel to be converted, as per
Table 3. Input channel description .
ADD2
1
1
1
1
0
0
0
0
ADD1
0
0
1
1
1
1
0
0
Table 3. Input channel description
ADD0
0
1
0
1
0
1
0
1
Input channel
IN4
IN5
IN6
IN7
IN0
IN1
IN2
IN3 page 3/20
2
Note:
Note:
LEOAD128
Maximum ratings and operating conditions
Maximum ratings and operating conditions
Table 4. Absolute maximum ratings
Symbol Parameter
AVCC
Maximum analog power supply between AVCC and AGND
DVCC
Maximum digital power supply between DVCC and DGND
Vi
li
T stg
T j
Max. voltage on any pin vs. GND
Max input current at any pin
Maximum temperature storage
R th
ESD
Maximum junction temperature
Junction-to-ambient thermal resistance (Ɵja)
Junction-to-case thermal resistance (Ɵjc)
HBM (human body model)
CDM (charged device model)
Value
-0.3 to 4.8
-0.3 to AVCC+0.3 (and 4.8 V max.)
-0.3 to AVCC+0.3 (and 4.8 V max.)
+/-10
-65 to +150
+150
80
17
4 k
1 k
°C
°C/W
°C/W
V
1. All voltages, except differential I/O bus voltage, are with respect to the network ground terminal.
2. When the input voltage at any pin exceeds the power supplies (that is VIN < AGND or VIN > AVCC or DVCC), the current at that pin should be limited to 10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two.
3. Short-circuits can cause excessive heating. Destructive dissipation can result from short-circuits on the amplifiers.
Unit
V
V
V mA
°C
Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All values are referred to GND.
Symbol
AVCC
DVCC
VINA
VIND
SCLK
T a
Table 5. Operating conditions
Parameter
Analog supply voltage
Digital supply voltage
Analog input voltage range
Digital input voltage
Clock frequency
Ambient temperature range
Min.
2.7
AVCC - 0.15 V
0
0
0.8
-40
Max.
3.6
AVCC + 0.15 V
AVCC
AVCC
16
+125
Unit
V
V
V
V
MHz
°C
All unused inputs must be held at VCC or GND to ensure proper device operation.
DS13668 - Rev 2 page 4/20
LEOAD128
Electrical characteristics
3
Electrical characteristics
AVCC = DVCC = +3.3 V, AGND = DGND = 0 V, f
SCLK
= 16 MHz, f
SAMPLE
= 1 Msps, CL = 25 pF, typ. values at
+25 °C, min./max. values at -40 °C and 125 °C, unless otherwise specified.
Table 6. Electrical characteristics
Symbol Parameters Test conditions
Static characteristics
Resolution with no missing codes
INL
Integral non-linearity (end point method)
Differential non-linearity DNL
VOFF
OEM
FSE
FSEM
Offset error
Offset error match
Full scale error
Full scale error match
Dynamic characteristics
ENOB
SINAD
Effective number of bits
Signal-to-noise plus distortion ratio (0 to Fs/2)
SNR
THD
SFDR
ISO
Signal-to-noise ratio (0 to
Fs/2)
Total harmonic distortion
Spurious-free dynamic range (0 to Fs/2)
Channel-to-channel isolation
FIN = 40.2 kHz, −0.02 dBFS
FIN = 40.2 kHz, −0.02 dBFS
FIN = 40.2 kHz, −0.02 dBFS
FIN = 40.2 kHz, −0.02 dBFS
FIN = 40.2 kHz, −0.02 dBFS
FIN = 20 kHz, −0.02 dBFS
IM2
IM3
2
3 nd rd
order intermodulation
order intermodulation fa = 19.5 kHz, fb = 20.5 kHz
VINA = VINB = -6.02 dBFS fa = 19.5 kHz, fb = 20.5 kHz
VINA = VINB = -6.02 dBFS
Analog input characteristics
IDCL
CINA Input capacitance
Track mode
Hold mode
Digital input characteristics
VIH
VIL
IIN
Input high voltage
Input low voltage
Digital input current
AVCC = DVCC = +2.7 V to +3.6 V
AVCC = DVCC = +2.7 V to +3.6 V
VIN = 0V or DVCC
CIND Digital input capacitance
Digital output characteristics (output coding: straight (natural) binary)
VOH Output high voltage
I source
= 200 µA
AVCC = DVCC = +2.7 V to +3.6 V
VOL Output low voltage Isink = 200 µA to 1.0 mA,
Min.
−1.1
-0.9
−2.3
−2.3
11.1
68.9
71
74
-1
2.1
-1
2.8
Typ.
11.7
72
73
−80
81
84
±0.4
±0.4
0.8
0.8
0.8
0.8
−90
−90
45
4.5
4.5
Max.
12
1.1
0.9
2.3
2.3
−73
+1
0.8
+1
0.4
Unit
Bits
LSB
LSB
LSB
LSB
LSB
LSB dB dB
V
V
µA pF
µA pF
V
V
Bits dB dB dB dB dB
DS13668 - Rev 2 page 5/20
Symbol Parameters Test conditions
AVCC = DVCC = +2.7 V to +3.6 V
IOZH, IOZL
COUT
High impedance output leakage current
High-impedance output capacitance
Power supply characteristics, CL=10 pF
AVCC = DVCC = +2.7 V to +3.6 V
Total supply current, normal mode (/CS low)
AVCC = DVCC = +2.7 V to +3.6 V, f
S
= 1 MSPS, FIN = 40 kHz
IAVCC + IDVCC
Total supply current,shutdown mode
(/CS high) f
AVCC = DVCC = +2.7 V to +3.6 V,
S
= 0
Clocking characteristics, AVCC = DVCC = +2.7 V to +3.6 V
Min.
-1
Typ.
4.5
0.9
0.11
t
CONVERT
Conversion (hold) time t
DC
ACQ
SCLK duty cycle
Acquisition (track) time cycles
See
40
Throughput time acquisition time + conversion time t
AD
Aperture delay
Timing specifications, AVCC = DVCC = +2.7 V to +3.6 V t t
CSH
CSS
/CS hold time after SCLK rising edge
/CS setup time prior SCLK rising edge t t t
EN
DACC
DHLD t t
DS
DH
/CSfalling edge to DOUT enabled
DOUT access time after
SCLK falling edge
DOUT hold time after SCLK falling edge
DIN set-up time prior to
SCLK rising edge
DIN hold time after SCLK rising edge t
CH t
CL
Min. SCLK high time
Min. SCLK low time t
DIS
/CS rising edge to DOUT high-impedance
DOUT falling
DOUT rising
10
10
7
10
10
0.4 x t
0.4 x t
SCLK
SCLK
1. Limits are guaranteed by functional test.
2. Clock may be in any state (high or low) when /CS goes high. Set-up and hold time restrictions apply only to /CS going low.
4
0
4.5
5
17
4
2.4
0.9
LEOAD128
Electrical characteristics
Max.
+1
Unit
µA pF
2
10
13
60
3
16
30
27
20
20 mA
µA ns ns ns ns ns ns ns ns ns
SCLK cycles
%
SCLK cycles
SCLK cycles ns ns
DS13668 - Rev 2 page 6/20
4
Timing diagrams
Figure 3. Operational timing diagram
LEOAD128
Timing diagrams
Figure 4. Serial timing diagram
Figure 5. SCLK and /CS timing parameters
DS13668 - Rev 2 page 7/20
5
LEOAD128
Radiations
Radiations
Total ionizing dose (TID):
For the qualification, the product is characterized in TID as per MIL-STD-883 TM 1019 up to 50 krad(Si) on 5 biased parts at high dose rate (between 50 and 300 rad(Si)/s), such a rate being the worst condition for a pure
CMOS technology.
All parameters provided in Table 6. Electrical characteristics
apply to both pre- and post-irradiation.
Each new production lot is tested at high dose rate as per MIL-STD-883 TM 1019 on 5 parts.
Heavy-ions:
Single event latchup (SEL) is characterized at 125 °C at a LET of 62.5 MeV.cm2/mg. The test shows the product is immune to heavy ions at this LET. Heavy-ion trials are performed on qualification lots only.
The results in radiation are summarized in
Table 7. Radiations as follows:
Table 7. Radiations
Symbol
•
•
•
•
•
•
•
Characteristics
High-dose rate (50-to-300 rad (Si)/s)
Temperature: 25 °C
Performed on 5 biased parts
LET: 62.5 MeV.cm2/mg (Xenon ions)
Temperature: 125 °C
Fluence: 1 x 10 7 ions/cm 2
Normal incidence
(10 million of particles per cm²)
Value
Table 6. Electrical characteristics
1. A total ionizing dose (TID) of 50 krad(Si) is equivalent to 500 Gy(Si), (1 gray = 100 rad).
2. SEL: single event latchup.
krad(Si)
Immune to SEL up to
62.5 MeV.cm
2 /mg
up to 50
DS13668 - Rev 2 page 8/20
6
Outgassing
1. RML < 1%.
2. CVCM < 0.1%.
Specification (tested per ASTM E 595)
Recovered mass loss (RML)
Collected volatile condensable material (CVCM) (2)
LEOAD128
Outgassing
Value
0.06
0.00
Unit
%
%
DS13668 - Rev 2 page 9/20
7
LEOAD128
PCB precautions
PCB precautions
•
•
•
•
•
•
A ground plane on each layer of the PCB with multiple vias dedicated for interconnexion is recommended for high-speed circuit applications to provide low parasitic inductance and resistance. The goal is to have a
“common ground plane” where AGND and DGND are connected with the lowest DC resistance and lowest
AC impedance.
The separation of the analog signal from the digital output is mandatory to prevent noise from coupling onto the input signal.
Power supply bypass capacitors must be placed as close as possible to the IC pins to improve highfrequency bypassing and reduce harmonic distortion.
All leads must be as short as possible, especially for the analog input, so to decrease parasitic capacitance and inductance.
To minimize the transition current when the output changes, the capacitive load at the digital outputs must be reduced as much as possible by using the shortest possible routing tracks. One way to reduce capacitive load is to remove the ground plane under the output digital pins and layers at high sampling frequencies.
Choose the smallest possible component sizes (SMD).
DS13668 - Rev 2 page 10/20
8
LEOAD128
Definitions
Definitions
The "acquisition time" is the time required to get the input voltage. During this time, the hold capacitor is charged by the input voltage.
The "aperture delay" is the time between the fourth falling edge of SCLK and the time when the input signal is internally acquired or held for conversion.
Channel-to-channel isolation is the residual noise injected on the selected channel by other unselected channels.
The "conversion time" is the time required, after the input voltage is acquired, to convert the input voltage to a digital word.
"Differential non-linearity" (DNL) is the maximum deviation from the ideal step size of 1 LSB.
Duty cycle is the ratio, for a periodic digital signal, of the high level duration divided by the total period.
Effective number of bits (ENOB) is a method of specifying signal-to-noise and distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits.
Full power bandwidth is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input.
Full scale error (single-ended input) is the deviation of the last code transition (111...110) to (111...111) from the ideal (AVCC -1LSB), after offset error is fixed.
Positive full scale error (differential input) is the deviation of the last code transition (111...110) to (111...111) from the ideal (AVCC -1LSB), after offset error is fixed.
Negative full scale error (differential input) is the deviation of the last code transition (111...110) to (111...111) from the ideal (-AVCC +1LSB), after offset error is fixed.
Integral non-linearity (INL) is the deviation of each individual code from a line drawn from negative full scale
(½ LSB below the first code transition) through positive full scale (½ LSB above the last code transition). The deviation of any given code from this straight line is measured from the center of that code value.
Intermodulation distortion (IMD) is the result of the product of two pure sinewaves at frequency fa and fb applied to the ADC input. To avoid clipping when the sinewave is in phase, the level must be just below -6 dBFS.
Assuming that the level of the two tones is equal, IMD2 is the difference in dBc between level(fa or fb) and level(fa
± fb). IMD3 is is the difference in dBc between level(fa or fb) and level(2fa ± fb) or level(fa ± 2fb).
Missing codes are those output codes that never appear at the ADC outputs. The RH-AD128 is guaranteed not to have any missing code.
Offset error (single-ended input) is the deviation of the first code transition (000...000) to (000...001) from the ideal
(i.e. GND +1 LSB).
Offset error (differential input) is the deviation of the mid-code transition (01…111) to (10…000) from the ideal (i.e.
AVCC/2 +1 LSB).
Signal-to-noise ratio (SNR) is the ratio, expressed in dB, of the rms value of the fundamental of input signal to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or DC-component.
Signal-to-noise plus distortion (S/N+D or SINAD) is the ratio of the rms value of the fundamental of input signal to the rms value of all of the other spectral components below half the sampling frequency, including harmonics but excluding DC-component.
Spurious free dynamic range (SFDR) is the difference, expressed in dB, between the desired signal amplitude of fundamental to the amplitude of the peak spurious spectral component, where a spurious spectral component is any signal present in the output spectrum that is not present at the input and may or may not be a harmonic.
Total harmonic distortion (THD) is the ratio, expressed in dBc, of the rms total of the first nine harmonic components at the output to the rms level of fundamental of the input signal frequency as seen at the output. THD is calculated as
THD=20log10[sqrt((Af2²+…+Af10²)/Af1²)] where Af1 is the RMS power of the fundamental at the output and Af2 to Af10 are the RMS power in the first nine harmonic frequencies.
Throughput time is the minimum time required between the start of two successive conversions. It is the acquisition time plus the conversion time.
DS13668 - Rev 2 page 11/20
9
9.1
LEOAD128
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
[Package name] package information
Figure 6. TSSOP-20 package outline
DS13668 - Rev 2
Table 8. TSSOP-20 package mechanical data
Symbol
Min.
Milimeters
Typ.
Max.
K
L
A
A1
A2 b c
D
E
E1 e
0.05
0.8
0.19
0.09
6.4
6.2
4.3
1
6.5
6.4
4.4
0.65 BSC
1.2
0.15
1.05
0.30
0.20
6.6
6.6
4.48
0°
0.45
0.60
8°
0.75
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Min
0.002
0.031
0.007
0.004
0.252
0.244
0.169
0°
0.018
Typ
0.004
0.039
0.256
0.252
0.173
0.0256 BSC
0.024
Max
0.047
0.006
0.041
0.260
0.260
0.176
8°
0.030
page 12/20
9.2
LEOAD128
TSSOP-20 packing information
TSSOP-20 packing information
Figure 7. TSSOP-20 Carrier tape (dimensions in mm) outline
DS13668 - Rev 2 page 13/20
LEOAD128
TSSOP-20 packing information
Figure 8. TSSOP-20 tape (dimensions in mm) outline
DS13668 - Rev 2 page 14/20
10
LEOAD128
Ordering information
Ordering information
Order code
LEOAD128PT-D
LEOAD128PT
Table 9. Ordering information
Quality Level
Development sample
Flight model
Package
TSSOP-20
TSSOP-20
Lead-finish
NiPdAu
NiPdAu
Marking
DLEOAD128
LEOAD128
Packing
Tape and reel
Tape and reel
LEO
LEO qualification
AD128
Name
Table 10. Order code
P
TSSOP-20 package
T
Tape and reel
Figure 9. TSSOP-20 marking
1 a
B
F
A C D
E
G H
a: pin-1 reference
A : Second Level of interconnexion (type of lead-finishing)
B: ST logo
C: Assy plant
D: Lot code
E: Marking area
F: Country of origin
G: Assy year
H: Assy week
DS13668 - Rev 2 page 15/20
Revision history
Date
01-Mar-2021
16-Sep-2021 2
Table 11. Document revision history
Version
1
Changes
Initial release.
Updated Section 5 Radiations .
Removed note and footnote in
Table 9. Ordering information .
LEOAD128
DS13668 - Rev 2 page 16/20
LEOAD128
Contents
Contents
DS13668 - Rev 2 page 17/20
LEOAD128
List of tables
List of tables
DS13668 - Rev 2 page 18/20
LEOAD128
List of figures
List of figures
DS13668 - Rev 2 page 19/20
LEOAD128
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STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2021 STMicroelectronics – All rights reserved
DS13668 - Rev 2 page 20/20
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