STMicroelectronics RHFAD128 Datasheet
STMicroelectronics RHFAD128, a rad-hard and reliable analog-to-digital converter, offers exceptional performance in harsh environments. With its 8-channel multiplexing capability, it can handle various analog input signals. The device's flexibility allows for both single-ended and differential input configurations, making it suitable for diverse applications. RHFAD128 operates at a conversion rate ranging from 50 ksps to 1 Msps, providing high-speed data acquisition. Its 12-bit resolution ensures accurate signal representation, while the low power consumption of 1.65 mA (typ.
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RHFAD128
RHFAD128
Datasheet
Rad-hard, 8-channel, 50 ksps to 1 Msps, 12-bit A/D converter
Features
• 50 ksps to 1 Msps conversion rate
• 8-to-1-channel single input MUX
• 4-to-1-channel differential input MUX
• 2.7 to 3.6 V operating supply
• Independent analog and digital supplies
• Pure CMOS
• Very low consumption: 1.65 mA typ.@ 3.6 V
• SPI, serial digital output
• Power-down function
• 300 krad TID
• 125 MeV.cm²/mg SEL free
Applications
• Analog multiplexing and conversion in space and harsh environments
• Telemetry
• Housekeeping
Description
The RHFAD128 is specifically designed to sustain ionizing dose and heavy-ions for space applications by using a high-end proven CMOS technology.
This device is a low-power, multiplexed eight-channel 12-bit analog-to-digital converter for conversion from 50 ksps to 1 Msps. The architecture is based on the successive-approximation register with internal track-and-hold. The RHFAD128 features 8 analog inputs which can be programmed to be either 8-single ended or
4 differential inputs using the control register bits. The output serial data are straight binary and are compatible with SPI™.
The analog and digital power supplies operate from 2.7 V to 3.6 V, drawing a current consumption of 1.65 mA typ. and 2 mA max. only.
The RHFAD128 is in hermetic ceramic Flat-16 leads, and works from
-55 °C to + 125 °C ambient temperature.
DS12480 - Rev 3 - December 2021
For further information contact your local STMicroelectronics sales office.
www.st.com
1
RHFAD128
Functional description
Functional description
Figure 1. Pin description
Top View
/C S
AVC C
AG ND
IN0
IN1
IN2
IN3
IN4
1
5
6
7
2
3
4
8
Note: the upper metallic lid is internally connected to ground.
16
15
14
13
12
11
10
9
Figure 2. Block diagram
S C LK
DOUT
DIN
DVC C
DG ND
IN7
IN6
IN5
IN0
Input
Mux.
IN7
8 s ingle -input or 4 differential-input that can be programmed by control register bits.
T /H
AG ND
12 bit
S AR
ADC
C ontrol
Logic
AVC C
AG ND
DVC C
/C S
S C LK
DIN
DOUT
DG ND
Bit#
Symbol for single input
Symbol for differential input
Table 1. Control register bits
7 (MSB) 6
Any code except 11
1 1
5
ADD2
0
4
ADD1
ADD1
3
ADD0
ADD0
2 1 0
Any code except 001
0 0 1
DS12480 - Rev 3 page 2/27
ADD2
1
1
1
1
0
0
0
0
ADD1
1
1
0
0
RHFAD128
Functional description
Table 2. Single input channel description
ADD1
0
0
1
1
1
1
0
0
ADD0
0
1
0
1
0
1
0
1
Table 3. Differential input channel description
ADD0
0
1
0
1
Differential channel
IN0-IN1
IN2-IN3
IN4-IN5
IN6-IN7
Input channel
IN4
IN5
IN6
IN7
IN0
IN1
IN2
IN3
DS12480 - Rev 3 page 3/27
1.1
RHFAD128
Maximum ratings and operating conditions
Maximum ratings and operating conditions
Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operations under these conditions is not implied.
Table 4. Absolute maximum ratings
Symbol
DVCC
T stg
T j
R thja
R thjc
V i
I i
ESD
Parameters
Maximum analog power supply between AVCC and AGND
Maximum digital power supply between DVCC and DGND
Maximum temperature storage
Maximum junction temperature
Junction-to-ambient thermal resistance (Flat-16 package)
Junction-to-case thermal resistance (Flat-16 package)
Max. voltage on any pin vs. GND
Max. input current at any pin
HBM on all pins (human body model)
Value
-0.3 V to 4.8 V
-0.3 V to AVCC+0.3 V (4.8 V max.)
-65 to +150
+150
120
22
-0.3 V to AVCC+0.3 V (4.8 V max.)
±10
4 k
1. All voltages, except differential I/O bus voltage, refer to the network ground level.
2. Short-circuits can cause excessive heating. Destructive dissipation can result from short-circuits on the amplifiers.
Unit
V
V
°C
°C
°C/W
°C/W
V mA
V
Symbol
AVCC
DVCC
VIN
VICM
VIND
SCLK
T a
Table 5. Operating conditions
Parameters
Analog supply voltage
Digital supply voltage
Analog input voltage in single-ended
Analog input voltage in differential configuration, and VICM=AVCC/2 (see
Figure 7. True-differential input range )
Common mode in differential configuration
Digital input voltage
Clock frequency
Ambient temperature range
Min.
2.7
Max.
3.6
Unit
V
AVCC - 0.15 AVCC + 0.15
V
0 AVCC V
-AVCC AVCC
0
0
0.1
-55
AVCC
AVCC
16
+125
V
V
MHz
°C
DS12480 - Rev 3 page 4/27
RHFAD128
Electrical characteristics
1.2
Electrical characteristics
AVCC = DVCC = +3.3 V, sngle-ended input, AGND = DGND = 0 V, f
SCLK
= 0.1 MHz to 16 MHz, f
SAMPLE
= 50 ksps to 1 Msps, CL = 50 pF, typ. values at +25 °C, min./max. values at -55 °C/125 °C, unless otherwise specified.
Table 6. Electrical characteristics in single-ended input
Symbol
Static characteristics
Parameters
INL
DNL
OE
OEM
FSE
Resolution without missing codes
Integral non-linearity (endpoint method)
Differential non-linearity
Offset error
Offset error match
Full scale error
FSEM Full scale error match
Dynamic characteristics
FPBW Full power bandwidth-3 dB
Test conditions
SINAD
SNR
THD
SFDR
ENOB
ISO
IM2
IM3
Signal-to-noise plus distortion ratio (0 to Fs/2)
Signal-to-noise ratio
(0 to Fs/2)
Total harmonic distortion
Spurious-free dynamic range (0 to Fs/2)
FIN = 40.2 kHz, −0.02 dBFS
Effective number of bits
Channel-to-channel isolation FIN = 20 kHz, −0.02 dBFS
2 nd order intermodulation
3 rd order intermodulation f a
= 19.5 kHz, f b
= 20.5 kHz
VINA=VINB=-6.02 dBFS
Analog input characteristics
IDCL
CINA
IOZH, IOZL
DC leakage current
Input capacitance
Digital input characteristics
VIH Input high voltage
VIL
IIN
Input low voltage
Digital input current VIN = 0 V or DVCC
CIND Digital input capacitance
Digital output characteristics, output coding: straight (natural) binary
VOH
VOL
Output high voltage
Output low voltage
I source
=1 mA
I sink
=1 mA
Hi-impedance output leakage current
Track mode
Hold mode
Min.
−1.1
-0.9
−2.3
−2
−2
−2
68
69
75
11.1
80
-1
2.1
-1
2.8
-1
Typ.
±0.6
±0.5
0.8
±0.1
0.8
6.8
72
71
−80
81
11.4
84
−90
−90
45
4.5
3.5
Max.
12
1.1
0.9
2.3
2
2
2
−74
−78
−72
0.4
1
0.8
1
1
Unit
MHz dB dB dB dB
Bits dB dB dB
V
V
µA
µA pF
V
V
µA pF pF
Bits
LSB
LSB
LSB
LSB
LSB
LSB
DS12480 - Rev 3 page 5/27
RHFAD128
Electrical characteristics
Symbol
COUT
Parameters
Hi impedance output capacitance
Power supply characteristics, CL=10 pF
Test conditions
Total supply current, normal mode (CS low)
AVCC = DVCC = +2.7 V to +3.6 V, f
S
=1 MSPS,
FIN=40 kHz
IAVCC +
IDVCC
Total supply current, shutdown mode (CS high)
AVCC = DVCC = +2.7 V to
+3.6 V, f
S
=0
AC characteristics (AVCC = DVCC = +2.7 V to +3.6 V)
Min.
Typ.
3.5
1.65
2 t
CONVERT
Conversion (hold) time 13 t
DC
ACQ
SCLK duty cycle
Acquisition (track) time cycles
See
Figure 5. Serial timing diagram
40
3 t t t t t t t t
Throughput time
Acquisition time +
Conversion time t
AD
Aperture delay
Timing specifications
(AVCC = DVCC = +2.7 V to +3.6 V) (1)
CSH
CSS
EN
CS/ hold time after SCLK rising edge
CS/ setup time prior SCLK rising edge
CS/ falling edge to DOUT enabled
DACC
DHLD
DS
DH
DOUT access time after
SCLK falling edge
DOUT hold time after SCLK falling edge
DIN setup time prior to
SCLK rising edge
DIN hold time after SCLK rising edge
DIS
CS/ rising edge to DOUT high-impedance
DOUT falling
DOUT rising t
CH t
CL
Min. SCLK high time
Min. SCLK low time
10
10
7
10
10
16
4
0
4.5
5
17
2.4
0.9
0.4 x t
SCLK
0.4 x t
SCLK
1. Limits are guaranteed by functional test.
2. Clock may be in any state (high or low) when CS/ goes high. Set-up and hold time restrictions apply to CS/ going low only.
Max.
2
10
60
30
27
20
20
Unit pF mA
µA
SCLK cycles
%
SCLK cycles
SCLK cycles ns ns ns ns ns ns ns ns ns ns ns ns
AVCC = DVCC = +3.3 V, differential input (see figure 4 for configuration), AGND = DGND = 0 V, f
SCLK
MHz, f
SAMPLE
= 16
= 1 Msps, CL = 50 pF, typ. values at +25 °C, min./max. values at -55 °C/125 °C, unless otherwise specified.
DS12480 - Rev 3 page 6/27
RHFAD128
Electrical characteristics
Table 7. Electrical characteristics in differential input
Symbol Parameters
Static characteristics
INL
Integral non-linearity
(end point method)
DNL
OE
Differential non-linearity
Offset error
OEM
FSE
Offset error match
Full scale error
FSEM Full scale error match
Dynamic characteristics
SINAD
SNR
THD
SFDR
ENOB
Signal-to-noise plus distortion ratio (0 to Fs/2)
Signal-to-noise ratio
(0 to Fs/2)
Total harmonic distortion
Spurious-free dynamic range
(0 to Fs/2)
Effective number of bits
Test conditions
VICM=AVCC/2
FIN=40.2 kHz, −0.02 dBFS
ISO
IM2
IM3
Channel-to-channel isolation
2
3 nd rd
order intermodulation
order intermodulation
FIN=20 kHz,
−0.02 dBFS f a
= 19.5 kHz, f b
=20.5 kHz
VINA=VINB=-6.02 dBFS f a
= 19.5 kHz, f b
=20.5 kHz
VINA=VINB=- 6.02 dBFS
Min.
-0.9
−0.8
−1.5
−1.5
−2
−2
69.3
71
75
11.2
85
Typ.
±0.3
72
73
−80
81
11.6
95
−90
−90
±0.3
0.2
±0.3
0.5
Max.
−74
0.9
0.8
1.5
1.5
2
2
−78
−72
Unit dB dB dB dB
Bits dB
LSB
LSB
LSB
LSB
LSB
LSB dB dB
DS12480 - Rev 3 page 7/27
1.3
Note:
RHFAD128
Radiations
Radiations
Total dose (MIL-STD-883 TM 1019):
•
•
The products guaranteed in radiation within the RHA QML-V system fully comply with the MIL-STD-883 TM 1019 specification.
The RHFAD128 is RHA QML-V, tested and characterized in full compliance with the MIL-STD-883 specification, between 50 and 300 rad/s only (full CMOS technology).
irradiation, as follows:
• All tests are performed in accordance with MIL-PRF-38535 and test method 1019 of MIL-STD-883 for total ionizing dose (TID)
The initial characterization is performed in qualification only on both biased and unbiased parts
Each wafer lot is tested at high dose rate only, in the worst bias case condition, based on the results obtained during the initial qualification
Heavy-ions:
The behavior of the product when submitted to heavy-ions is not tested in production. Heavy-ion trials are performed on qualification lots only.
•
•
•
Table 8. Radiations
Type
TID
Heavy-ions
Characteristics
High dose rate (50 - 300 rad/s) up to
SEL immune up to (with a particle angle of 60 ° at 125 °C, and a fluence of 1e7 cm-2)
SEL immune up to (with a particle angle of 0 ° at 125 °C, and a fluence of 1e7 cm-2)
SEU immune up to (at 25 °C, and a fluence of 1e6 cm-2)
SEFI immune up to (at 25 °C, and a fluence of 1e6 cm-2)
1. Total ionizing dose (TID) of 300 krad(Si) is equivalent to 3000 Gy(Si), (1 gray = 100 rad).
SEL: single event latch-up
SEU: single event upset
SEFI: single event functional interrupt
Value
300
125
62
32
62
Unit krad
MeV.cm²/mg
DS12480 - Rev 3 page 8/27
1.4
Timing diagrams
Figure 3. Operational timing diagram in single-ended input
RHFAD128
Timing diagrams
Figure 4. Operational timing diagram in differential input
Figure 5. Serial timing diagram
DS12480 - Rev 3 page 9/27
Figure 6. SCLK and CS/ timings
RHFAD128
Timing diagrams
DS12480 - Rev 3 page 10/27
1.5
Differential input
Figure 7. True-differential input range
RHFAD128
Differential input
The maximum differential input swing is limited by the input common mode value (VICM) and it is limited by
the grey area as shown in Figure 7. True-differential input range
. The maximum value equals to +/-AVCC for
VICM=AVCC/2.
DS12480 - Rev 3 page 11/27
1.6
RHFAD128
Definitions
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Definitions
Acquisition time is the time required to acquire the input voltage. During this time, the hold capacitor is charged by the input voltage
Aperture delay is the time between the fourth falling edge of SCLK and the time when the input signal is internally acquired or held for conversion
Channel-to-channel isolation is the residual noise injected on the selected channel by other unselected channels
Conversion time is the time required, after the input voltage is acquired, to convert the input voltage to a digital word
Differential non-linearity (DNL) is the maximum deviation from the ideal step size of 1 LSB
Duty cycle is the ratio, for a periodic digital signal, of the high level duration divided by the total period
Effective number of bits (ENOB) is a method to specify signal-to-noise and distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits
Full power bandwidth is a measure of the frequency at which the reconstructed output fundamental drops
3 dB below its low frequency value for a full scale input
Full scale error (single-ended input) is the deviation of the last code transition (111...110) to (111...111) from the ideal (AVCC -1LSB), after adjusting for offset error
Positive full scale error (differential input) is the deviation of the last code transition (111...110) to
(111...111) from the ideal (AVCC -1LSB), after adjusting for offset error
Negative full scale error (differential input) is the deviation of the last code transition (111...110) to
(111...111) from the ideal (-AVCC +1LSB), after adjusting for offset error
Integral non-linearity (INL) is the deviation of each individual code from a line drawn from negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code transition). The deviation of any given code from this straight line is measured from the center of that code value
Intermodulation distortion (IMD) is the result of the product of two pure sine waves at frequency f a
and f b applied to the ADC input. To avoid clipping when the sine waves are in phase, the level must be just below
-6 dBFS. Assuming that the level of the two tones is equal, IMD2 is the difference in dBc between level (f a
or f b
) and level(f a
± f b
). IMD3 is is the difference in dBc between level (f a
or f b
) and level (2f a
± f b
) or level (f a
±
2f b
)
Missing codes are those output codes that never appear on the ADC outputs. The RHFAD128 is guaranteed not to have any missing codes
Offset error (single-ended input) is the deviation of the first code transition (000...000) to (000...001) from the ideal (i.e. GND +1 LSB)
Signal-to-noise ratio (SNR) is the ratio, expressed in dB, of the RMS value of the fundamental of input signal to the RMS value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or DC-component
Signal-to-noise plus distortion (S/N+D or SINAD) is the ratio of the RMS value of the fundamental of input signal to the RMS value of all of the other spectral components below half the sampling frequency, including harmonics but excluding DC-component
Spurious free dynamic range (SFDR) is the difference, expressed in dB, between the desired signal amplitude of fundamental to the amplitude of the peak spurious spectral component, where a spurious spectral component is any signal present in the output spectrum that is not present on the input and may or may not be a harmonic
Total harmonic distortion (THD) is the ratio, expressed in dBc, of the RMS total of the first nine harmonic components on the output to the RMS level of fundamental of the input signal frequency as seen on the output. THD is calculated as THD=20log10[sqrt((Af2²+…+Af10²)/Af1²)] where Af1 is the RMS power of the fundamental on the output and Af2 to Af10 are the RMS power in the first nine harmonic frequencies
Throughput time is the minimum time required between the start of two successive conversions. It is the acquisition time plus the conversion time
DS12480 - Rev 3 page 12/27
1.7
RHFAD128
PCB layout precautions
•
•
•
•
•
•
PCB layout precautions
A ground plane on each layer of the PCB with multiple vias dedicated to interconnection is recommended for high speed circuit applications to provide low parasitic inductance and resistance. The goal is to have a
“common ground plane” where AGND and DGND are connected with the lowest DC resistance and lowest
AC impedance
The separation of the analog signal from the digital output is mandatory to prevent noise from coupling onto the input signal
Power supply bypass capacitors must be placed as close as possible to the IC pins to improve high frequency bypassing and reduce harmonic distortion
All leads must be as short as possible, especially for the analog input, so to decrease parasitic capacitance and inductance
To minimize the transition current when the output changes, the capacitive load at the digital outputs must be reduced as much as possible by using the shortest possible routing tracks
Choose the smallest possible component sizes (SMD)
DS12480 - Rev 3 page 13/27
2
RHFAD128
Typical performance characteristics
Typical performance characteristics
AVCC = DVCC = +3.3 V, single-ended input, AGND = DGND = 0 V, f
SCLK
= 16 MHz, f
SAMPLE
= 1 Msps,
C
L
= 25 pF, T a
= +25 °C, f in
= 40 KHz unless otherwise specified.
Figure 8. DNL vs. output code @ V
A
= V
D
= 3.3 V Figure 9. DNL vs. output code @ V
A
= V
D
= 3.3 V
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
0 512 1024 1536 2048 code
2560 3072 3584 4096
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
0 512 1024 1536 2048 code
2560 3072 3584 4096
DS12480 - Rev 3 page 14/27
2.1
RHFAD128
Input frequency
Input frequency
Figure 10. SNR vs. input frequency Figure 11. THD vs. input frequency
75
74.5
74
73.5
73
72.5
72
71.5
71
70.5
70
0 10 20 30 40 50 60
Fin (kHz) @ VA = VD = 3 V
70 80 90 100
-75
-80
-85
-90
-95
0 10 20 30 40 50 60 70
SCLK (MHz), VA = VD = 3.3 V
80 90 100
Figure 12. ENOB vs. input frequency
Figure 13. Power consumption vs. SCLK frequency
@ V
A
= V
D
= 3 V; C
L
= 50 pF
12
11.9
11.8
11.7
11.6
11.5
11.4
11.3
11.2
11.1
11
0 10 20 30 40 50 60 70
SCLK (MHz), VA = VD = 3.3 V
80 90 100
4.00
3.50
3.00
2.50
2.00
0 2 4 6 8
SCLK (MHz)
10 12 14 16
DS12480 - Rev 3 page 15/27
2.2
RHFAD128
Power supply
Power supply
Figure 14. DNL vs. power supply
DNL+ DNL-
0.5
0.3
0.1
-0.1
-0.3
-0.5
2.7
3
VA, VD (V)
3.3
3.6
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
2.7
Figure 15. INL vs. power supply
INL+ INL-
3
VA, VD (V)
3.3
3.6
72
71
74
73
70
2.7
Figure 16. SNR vs. power supply
3
VA, VD (V)
3.3
3.6
-75
-80
-85
-90
-95
2.7
Figure 17. THD vs. power supply
3
VA, VD (V)
3.3
3.6
12
11.8
11.6
11.4
11.2
11
2.7
Figure 18. ENOB vs. power supply
3
VA, VD (V)
3.3
3.6
DS12480 - Rev 3 page 16/27
2.3
RHFAD128
Temperature
Temperature
Figure 19. DNL vs. temperature
DNL+
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-60 -40 -20 0 20 40 60
Temperature, VA = VD = 3.3 V
DNL-
80 100 120
Figure 20. INL vs. temperature
INL+ INL-
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-60 -40 -20 0 20 40 60
Temperature, VA = VD = 3.3 V
80 100 120
Figure 21. SNR vs. temperature
75
74.5
74
73.5
73
72.5
72
71.5
71
70.5
70
-60 -40 -20 0 20 40 60
Temperature, VA = VD = 3.3 V
80 100 120
Figure 22. THD vs. temperature
-75
-80
-85
-90
-95
-60 -40 -20 0 20 40 60
Temperature, VA = VD = 3.3 V
80 100 120
Figure 23. ENOB vs. temperature
12
11.9
11.8
11.7
11.6
11.5
11.4
11.3
11.2
11.1
11
-40 -20 0 20 40 60
Temperature, VA = VD = 3.3 V
80 100 120
DS12480 - Rev 3 page 17/27
2.4
RHFAD128
SCLK frequency
SCLK frequency
Figure 24. DNL vs. SCLK frequency
DNL+ DNL-
0.2
0.1
0
-0.1
-0.2
0.5
0.4
0.3
-0.3
-0.4
-0.5
8 10 12
SCLK (MHz), VA = VD = 3.3 V
14 16
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
8
Figure 25. INL vs. SCLK frequency
INL+ INL-
10 12
SCLK (MHz), VA = VD = 3.3 V
14 16
75
74.5
74
73.5
73
72.5
72
71.5
71
70.5
70
8
Figure 26. SNR vs. SCLK frequency
10 12
SCLK (MHz), VA = VD = 3.3 V
14
-75
-80
-85
-90
16
-95
8
Figure 27. THD vs. SCLK frequency
10 12
SCLK (MHz), VA = VD = 3.3 V
14 16
12
11.8
11.6
11.4
11.2
11
8
Figure 28. ENOB vs. SCLK frequency
10 12
SCLK (MHz), VA = VD = 3.3 V
14 16
DS12480 - Rev 3 page 18/27
3
3.1
RHFAD128
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
Flat-16 package information
The upper metallic lid is electrically connected to AGND and DGND.
Figure 29. Flat-16 package information outline
DS12480 - Rev 3
Ref.
c
D
E
A b
E2
E3 e
L
Q
S1
0.76
6.35
0.66
0.13
Min.
2.31
0.38
0.10
9.75
6.75
Table 9. Flat-16 package mechanical data mm
Typ.
Max.
2.72
0.48
0.18
10.13
7.06
Min.
0.091
0.015
0.004
0.384
0.266
4.32
0.030
1.27
7.36
1.14
0.250
0.026
0.005
Inch
Typ.
0.170
0.050
Max.
0.107
0.019
0.007
0.399
0.278
0.290
0.045
page 19/27
RHFAD128
Ordering information
4 Ordering information
Table 10. Order code
Order code
RH-AD128KX
RH-AD128K1
RHFAD128K01V
SMD
-
-
5962F18204
Quality level
Prototype
Engineering model
QML-V
Flight
Temp.
range
-55 °C to
+125 °C
Mass
0.65 g
Package
Flat-16
1. Standard microcircuit drawing.
2. • Specific marking only. Complete marking includes the following:
•
•
•
ST logo
Date code (date the package was sealed) in YYWWA (year, week, and lot index of week)
Country of origin (FR = France).
RH-AD128KX
RH-AD128K1
5962F1820401VXC
Packing
Strip pack
DS12480 - Rev 3 page 20/27
5
Note:
RHFAD128
Other information
Other information
Date code:
The date code is structured as follows:
Engineering model: EM xyywwz where: x = 3 (EM only), assembly location Rennes (France) yy = last two digits of the year ww = week digits z = lot index of the week
Product documentation
Each product shipment includes a set of associated documentation within the shipment box. This documentation depends on the quality level of the products, as detailed in the table below.
The certificate of conformance is provided on paper whatever the quality level. For QML parts, complete documentation, including the certificate of conformance, is provided on a CDROM.
Please, contact ST for details on the documentation of other quality levels
Quality level
Engineering model
QML-V Flight
Table 11. Product documentation
Item
Certificate of conformance including :
Customer name
Customer purchase order number
ST sales order number and item
ST part number
Quantity delivered
Date code
Reference to ST datasheet
Reference to the TN1181 on engineering models
ST Rennes assembly lot ID
Certificate of conformance including
Customer name
Customer purchase order number
ST sales order number and item
ST part number
Quantity delivered
Date code
Serial numbers
Group C reference
Group D reference
Reference to the applicable SMD
ST Rennes assembly lot ID
Quality control inspection (groups A, B, C, D, E)
Screening electrical data in/out summary
Pre-cap report
PIND (particle impact noise detection) test
SEM (scanning electronic microscope) inspection report
DS12480 - Rev 3 page 21/27
Quality level
QML-V Flight X-ray plates
Item
RHFAD128
Other information
DS12480 - Rev 3 page 22/27
RHFAD128
Revision history
Date
12-Mar-2018
06-Sep-2018
10-Dec-2021
2
3
Table 12. Document revision history
Revision
1
Changes
Initial version.
Updated , Section Features and the Section Description in cover page.
Updated Section 1 Functional description, Table 4. Absolute maximum ratings, Table 6. Electrical characteristics in single-ended input and Table
7. Electrical characteristics in differential input, Table 8. Radiations and
Table 10. Order code.
Added new
Section 2 Typical performance characteristics
.
DS12480 - Rev 3 page 23/27
RHFAD128
Contents
Contents
DS12480 - Rev 3 page 24/27
RHFAD128
List of tables
List of tables
DS12480 - Rev 3 page 25/27
RHFAD128
List of figures
List of figures
Figure 8. DNL vs. output code @ V
Figure 9. DNL vs. output code @ V
Figure 13. Power consumption vs. SCLK frequency @ V
= 50 pF . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DS12480 - Rev 3 page 26/27
RHFAD128
IMPORTANT NOTICE – PLEASE READ CAREFULLY
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Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2021 STMicroelectronics – All rights reserved
DS12480 - Rev 3 page 27/27
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