ARM ® Cortex ® -M0 32-bit RISC core operating at up to 48 MHz frequency, high-speed embedded memories (up to 32 Kbytes of Flash memory and 6 Kbytes of SRAM), and an extensive range of enhanced peripherals and I/Os. All devices offer standard communication interfaces (one I 2 C, two SPIs/one I 2 S, one HDMI CEC and two USARTs), one USB Full-speed device (crystal-less), one CAN, one 12-bit ADC, four 16-bit timers, one

32-bit timer and an advanced-control PWM timer.

The STM32F042x4/x6 microcontrollers operate in the -40 to +85 °C and -40 to +105 °C temperature ranges, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving modes allows the design of low-power applications.

The STM32F042x4/x6 microcontrollers include devices in seven different packages ranging from 20 pins to 48 pins with a die form also available upon request. Depending on the device chosen, different sets of peripherals are included.

These features make the STM32F042x4/x6 microcontrollers suitable for a wide range of applications such as application control and user interfaces, hand-held equipment, A/V receivers and digital TV, PC peripherals, gaming and GPS platforms, industrial applications,

PLCs, inverters, printers, scanners, alarm systems, video intercoms and HVACs.

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DocID025832 Rev 5

STM32F042x4 STM32F042x6 Description

Peripheral

Table 2. STM32F042x4/x6 device features and peripheral counts

STM32F042Fx STM32F042G STM32F042K STM32F042T STM32F042C

Flash memory (Kbyte)

SRAM (Kbyte)

Advanced control

Timers

General purpose

SPI [I

(1)

16 32 16 32

1 [1]

1 (16-bit)

4 (16-bit)

1 (32-bit)

16 32 16

2 [1]

Comm. interfaces

USART

CAN

GPIOs channels

USB

CEC

12-bit ADC

(number of channels)

Capacitive sensing

(9 ext. + 3 int.)

(10 ext. + 3 int.)

48 MHz

2.0 to 3.6 V

Max. CPU frequency

Operating voltage

Operating temperature

Packages TSSOP20

Ambient operating temperature: -40°C to 85°C / -40°C to 105°C

Junction temperature: -40°C to 105°C / -40°C to 125°C

UQFPN28

LQFP32

UQFPN32

1. The SPI interfaces can be used either in SPI mode or in I 2 S audio mode.

WLCSP36

LQFP48

UFQFPN48

DocID025832 Rev 5

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Description STM32F042x4 STM32F042x6

Figure 1. Block diagram

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DocID025832 Rev 5

STM32F042x4 STM32F042x6 Functional overview

Figure 1 shows the general block diagram of the STM32F042x4/x6 devices.

3.1 ARM

®

-Cortex

®

-M0 core

The ARM

Cortex

-M0 is a generation of ARM 32-bit RISC processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.

The ARM

Cortex

-M0 processors feature exceptional code-efficiency, delivering the high performance expected from an ARM core, with memory sizes usually associated with 8- and

16-bit devices.

The STM32F042x4/x6 devices embed ARM core and are compatible with all ARM tools and software.

3.2 Memories

The device has the following features:

• 6 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states and featuring embedded parity checking with exception generation for fail-critical applications.

• The non-volatile memory is divided into two arrays:

– 16 to 32 Kbytes of embedded Flash memory for programs and data

– Option bytes

The option bytes are used to write-protect the memory (with 4 KB granularity) and/or readout-protect the whole memory with the following options:

– Level 0: no readout protection

– Level 1: memory readout protection, the Flash memory cannot be read from or written to if either debug features are connected or boot in RAM is selected

– Level 2: chip readout protection, debug features (Cortex

®

-M0 serial wire) and boot in RAM selection disabled

At startup, the boot pin and boot selector option bits are used to select one of the three boot options:

• boot from User Flash memory

• boot from System Memory

• boot from embedded SRAM

The boot pin is shared with the standard GPIO and can be disabled through the boot selector option bits. The boot loader is located in System Memory. It is used to reprogram the Flash memory by using USART on pins PA14/PA15, or PA9/PA10 or I 2 C on pins

PB6/PB7 or through the USB DFU interface.

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Functional overview STM32F042x4 STM32F042x6

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a CRC-32 (Ethernet) polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.

3.5.1

3.5.2

Power supply schemes

• V

= V

DDIO1

= 2.0 to 3.6 V: external power supply for I/Os (V

DDIO1

) and the internal regulator. It is provided externally through VDD pins.

• V

DDA

= from V

to 3.6 V: external analog power supply for ADC, Reset blocks, RCs and PLL (minimum voltage to be applied to V

DDA provided externally through VDDA pin. The V or equal to the V

DDA

is 2.4 V when the ADC is used). It is

voltage level must be always greater

voltage level and must be established first.

• V

DDIO2 from V

DDIO2

= 1.65 to 3.6 V: external power supply for marked I/Os. V

DDIO2 externally through the VDDIO2 pin. The V

DDIO2

is provided

voltage level is completely independent

supply is monitored and compared with the internal reference voltage

REFINT

or V

DDA

, but it must not be provided without a valid supply on V

. The

). When the V

DDIO2

is below this threshold, all the I/Os supplied from this rail are disabled by hardware. The output of this comparator is connected to EXTI line 31 and it can be used to generate an interrupt. Refer to the pinout diagrams or tables for concerned I/Os list.

• V

BAT

= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when V

is not present.

For more details on how to connect power pins, refer to

Figure 13: Power supply scheme .

Power supply supervisors

The device has integrated power-on reset (POR) and power-down reset (PDR) circuits.

They are always active, and ensure proper operation above a threshold of 2 V. The device remains in reset mode when the monitored supply voltage is below a specified threshold,

POR/PDR

, without the need for an external reset circuit.

• The POR monitors only the V

DD that V

DDA

supply voltage. During the startup phase it is required

should arrive first and be greater than or equal to V

• The PDR monitors both the V

and V

DDA

supply voltages, however the V

DDA

power supply supervisor can be disabled (by programming a dedicated Option bit) to reduce the power consumption if the application design ensures that V

DDA equal to V

is higher than or

The device features an embedded programmable voltage detector (PVD) that monitors the

power supply and compares it to the V

PVD

threshold. An interrupt can be generated when V

drops below the V

PVD

threshold and/or when V

is higher than the V

PVD

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STM32F042x4 STM32F042x6 Functional overview threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

The regulator has two operating modes and it is always enabled after reset.

• Main (MR) is used in normal operating mode (Run).

• Low power (LPR) can be used in Stop mode where the power demand is reduced.

In Standby mode, it is put in power down mode. In this mode, the regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost).

Note:

The STM32F042x4/x6 microcontrollers support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:

• Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

• Stop mode

Stop mode achieves very low power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the

HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low power mode.

The device can be woken up from Stop mode by any of the EXTI lines. The EXTI line source can be one of the 16 external lines, the PVD output, RTC, I2C1 USART1, USB or the CEC.

The CEC, USART1 and I2C1 peripherals can be configured to enable the HSI RC oscillator so as to get clock for processing incoming data. If this is used when the voltage regulator is put in low power mode, the regulator is first switched to normal mode before the clock is provided to the given peripheral.

• Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The

PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering

Standby mode, SRAM and register contents are lost except for registers in the RTC domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pins, or an RTC event occurs.

The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode.

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Functional overview

3.6

STM32F042x4 STM32F042x6

Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example on failure of an indirectly used external crystal, resonator or oscillator).

Several prescalers allow the application to configure the frequency of the AHB and the APB domains. The maximum frequency of the AHB and the APB domains is 48 MHz.

Additionally, also the internal RC 48 MHz oscillator can be selected for system clock or PLL input source. This oscillator can be automatically fine-trimmed by the means of the CRS peripheral using the external synchronization.

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STM32F042x4 STM32F042x6 Functional overview

Figure 2. Clock tree

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3.7 General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions.

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Functional overview STM32F042x4 STM32F042x6

The I/O configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers.

3.8 Direct memory access controller (DMA)

The 5-channel general-purpose DMAs manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers.

The DMA supports circular buffer management, removing the need for user code intervention when the controller reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent.

DMA can be used with the main peripherals: SPIx, I2Sx, I2Cx, USARTx, all TIMx timers

(except TIM14) and ADC.

3.9 Interrupts events

3.9.1

3.9.2

Nested vectored interrupt controller (NVIC)

32 maskable interrupt channels (not including the 16 interrupt lines of Cortex

®

-M0) and 4 priority levels.

• Closely coupled NVIC gives low latency interrupt processing

• Interrupt entry vector table address passed directly to the core

• Closely coupled NVIC core interface

• Allows early processing of interrupts

• Processing of late arriving higher priority interrupts

• Support for tail-chaining

• Processor state automatically saved

• Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt latency.

Extended interrupt/event controller (EXTI)

The extended interrupt/event controller consists of 24 edge detector lines used to generate interrupt/event requests and wake-up the system. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the internal clock period. Up to 38

GPIOs can be connected to the 16 external interrupt lines.

3.10 Analog-to-digital converter (ADC)

The 12-bit analog-to-digital converter has up to 10 external and 3 internal (temperature

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STM32F042x4 STM32F042x6 Functional overview sensor, voltage reference, VBAT voltage measurement) channels and performs conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs.

The ADC can be served by the DMA controller.

An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.

The temperature sensor (TS) generates a voltage V

SENSE temperature.

that varies linearly with

The temperature sensor is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value.

The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only.

To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode.

Table 3. Temperature sensor calibration values

Calibration value name Description Memory address

TS_CAL1

TS_CAL2

TS ADC raw data acquired at a temperature of 30 °C (± 5 °C),

DDA

= 3.3 V (± 10 mV)

TS ADC raw data acquired at a temperature of 110 °C (± 5 °C),

DDA

= 3.3 V (± 10 mV)

0x1FFF F7B8 - 0x1FFF F7B9

0x1FFF F7C2 - 0x1FFF F7C3

3.10.2 Internal voltage reference (V

REFINT

)

The internal voltage reference (V

REFINT

ADC. V

REFINT of V

REFINT

) provides a stable (bandgap) voltage output for the

is internally connected to the ADC_IN17 input channel. The precise voltage

is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode.

Table 4. Internal voltage reference calibration values

Calibration value name Description Memory address

VREFINT_CAL

Raw data acquired at a temperature of 30 °C (± 5 °C),

DDA

= 3.3 V (± 10 mV)

0x1FFF F7BA - 0x1FFF F7BB

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Functional overview STM32F042x4 STM32F042x6

3.10.3 V

BAT

battery voltage monitoring

This embedded hardware feature allows the application to measure the V

BAT

battery voltage using the internal ADC channel ADC_IN18. As the V and thus outside the ADC input range, the V

BAT

voltage may be higher than V

DDA

pin is internally connected to a bridge divider by 2. As a consequence, the converted digital value is half the V

BAT

voltage.

3.11 Touch sensing controller (TSC)

The STM32F042x4/x6 devices provide a simple solution for adding capacitive sensing functionality to any application. These devices offer up to 14 capacitive sensing channels distributed over 5 analog I/O groups.

Capacitive sensing technology is able to detect the presence of a finger near a sensor which is protected from direct touch by a dielectric (glass, plastic...). The capacitive variation introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. It consists in charging the sensor capacitance and then transferring a part of the accumulated charges into a sampling capacitor until the voltage across this capacitor has reached a specific threshold. To limit the CPU bandwidth usage, this acquisition is directly managed by the hardware touch sensing controller and only requires few external components to operate.

For operation, one capacitive sensing GPIO in each group is connected to an external capacitor and cannot be used as effective touch sensing channel.

The touch sensing controller is fully supported by the STMTouch touch sensing firmware library, which is free to use and allows touch sensing functionality to be implemented reliably in the end application.

Table 5. Capacitive sensing GPIOs available on STM32F042x4/x6 devices

Group

Capacitive sensing signal name

Pin name

Group

Capacitive sensing signal name

Pin name

TSC_G1_IO1

TSC_G1_IO2

TSC_G1_IO3

TSC_G1_IO4

TSC_G2_IO1

TSC_G2_IO2

TSC_G2_IO3

TSC_G2_IO4

TSC_G3_IO2

TSC_G3_IO3

TSC_G3_IO4

PA4

PA5

PA6

PA7

PA0

PA1

PA2

PA3

PB0

PB1

PB2

TSC_G4_IO1

TSC_G4_IO2

TSC_G4_IO3

TSC_G4_IO4

TSC_G5_IO1

TSC_G5_IO2

TSC_G5_IO3

TSC_G5_IO4

PA9

PA10

PA11

PA12

PB3

PB4

PB6

PB7

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STM32F042x4 STM32F042x6 Functional overview

Table 6. No. of capacitive sensing channels available on STM32F042x devices

Number of capacitive sensing channels

Analog I/O group

Number of capacitive sensing channels

STM32F042Cx

LQPF48

UQFPN48

STM32F042Tx

WLCSP36

STM32F042Kx

LQFP32

UQFPN32

STM32F042Gx

UQFPN28

STM32F042Fx

TSSOP20

3.12 Timers and watchdogs

The STM32F042x4/x6 devices include up to five general-purpose timers and an advanced control timer.

Table 7 compares the features of the different timers.

Timer type

General purpose

Timer

Advanced control

TIM1

TIM3

TIM14

TIM16

TIM17

Counter resolution

16-bit

TIM2 32-bit

16-bit

Table 7. Timer feature comparison

Counter type

Prescaler factor

DMA request generation

Capture/compare channels

Complementary outputs

Up, down, up/down

Up integer from

1 to 65536 integer from

1 to 65536

Yes

3.12.1 Advanced-control timer (TIM1)

The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on six channels. It has complementary PWM outputs with programmable inserted dead times. It

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Functional overview STM32F042x4 STM32F042x6 can also be seen as a complete general-purpose timer. The four independent channels can be used for:

• input capture

• output compare

• PWM generation (edge or center-aligned modes)

• one-pulse mode output

If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If configured as the 16-bit PWM generator, it has full modulation capability (0-100%).

The counter can be frozen in debug mode.

Many features are shared with those of the standard timers which have the same architecture. The advanced control timer can therefore work together with the other timers via the Timer Link feature for synchronization or event chaining.

There are five synchronizable general-purpose timers embedded in the STM32F042x4/x6

devices (see Table 7 for differences). Each general-purpose timer can be used to generate

PWM outputs, or as simple time base.

TIM2, TIM3

STM32F042x4/x6 devices feature two synchronizable 4-channel general-purpose timers.

TIM2 is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. TIM3 is based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. They feature 4 independent channels each for input capture/output compare, PWM or one-pulse mode output. This gives up to 12 input captures/output compares/PWMs on the largest packages.

The TIM2 and TIM3 general-purpose timers can work together or with the TIM1 advancedcontrol timer via the Timer Link feature for synchronization or event chaining.

TIM2 and TIM3 both have independent DMA request generation.

These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors.

Their counters can be frozen in debug mode.

TIM14

This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler.

TIM14 features one single channel for input capture/output compare, PWM or one-pulse mode output.

Its counter can be frozen in debug mode.

TIM16 and TIM17

Both timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.

They each have a single channel for input capture/output compare, PWM or one-pulse mode output.

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STM32F042x4 STM32F042x6 Functional overview

TIM16 and TIM17 have a complementary output with dead-time generation and independent DMA request generation.

Their counters can be frozen in debug mode.

The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with user-defined refresh window. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode.

3.12.4 System window watchdog (WWDG)

The system window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the APB clock (PCLK). It has an early warning interrupt capability and the counter can be frozen in debug mode.

This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features:

• a 24-bit down counter

• autoreload capability

• maskable system interrupt generation when the counter reaches 0

• programmable clock source (HCLK or HCLK/8)

The RTC and the five backup registers are supplied through a switch that takes power either on V

supply when present or through the V

BAT

pin. The backup registers are five 32-bit registers used to store 20 bytes of user application data when V

power is not present.

They are not reset by a system or power reset, or at wake up from Standby mode.

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Functional overview STM32F042x4 STM32F042x6

The RTC is an independent BCD timer/counter. Its main features are the following:

• calendar with subseconds, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format

• automatic correction for 28, 29 (leap year), 30, and 31 day of the month

• programmable alarm with wake up from Stop and Standby mode capability

• on-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize the RTC with a master clock

• digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal inaccuracy

• two anti-tamper detection pins with programmable filter. The MCU can be woken up from Stop and Standby modes on tamper event detection

• timestamp feature which can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be woken up from Stop and Standby modes on timestamp event detection

• reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision

The RTC clock sources can be:

• a 32.768 kHz external crystal

• a resonator or oscillator

• the internal low-power RC oscillator (typical frequency of 40 kHz)

• the high-speed external clock divided by 32

circuit interface (I

2

C)

The I

C interface (I2C1) can operate in multimaster or slave modes. It can support Standard mode (up to 100 kbit/s), Fast mode (up to 400 kbit/s) and Fast Mode Plus (up to 1 Mbit/s) with 20 mA output drive.

It supports 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (two addresses, one with configurable mask). It also includes programmable analog and digital noise filters.

Table 8. Comparison of I

C analog and digital filters

Analog filter Digital filter Aspect

Pulse width of suppressed spikes

Benefits

Drawbacks

≥ 50 ns

Available in Stop mode

Variations depending on temperature, voltage, process

Programmable length from 1 to 15

I2Cx peripheral clocks

–Extra filtering capability vs.

standard requirements

–Stable length

Wakeup from Stop on address match is not available when digital filter is enabled.

In addition, I2C1 provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts verifications and ALERT protocol management. I2C1 also has a clock domain independent

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DocID025832 Rev 5

STM32F042x4 STM32F042x6 Functional overview from the CPU clock, allowing the I2C1 to wake up the MCU from Stop mode on address match.

The I2C peripheral can be served by the DMA controller.

Table 9. STM32F042x4/x6 I

C implementation

C features

(1)

7-bit addressing mode

10-bit addressing mode

Standard mode (up to 100 kbit/s)

Fast mode (up to 400 kbit/s)

Fast Mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s)

Independent clock

SMBus

Wakeup from STOP

1. X = supported.

I2C1

(USART)

The device embeds two universal synchronous/asynchronous receivers/transmitters

(USART1, USART2) which communicate at speeds of up to 6 Mbit/s.

They provide hardware management of the CTS, RTS and RS485 DE signals, multiprocessor communication mode, master synchronous communication and single-wire half-duplex communication mode. USART1 supports also SmartCard communication (ISO

7816), IrDA SIR ENDEC, LIN Master/Slave capability and auto baud rate feature, and has a clock domain independent of the CPU clock, allowing to wake up the MCU from Stop mode.

The USART interfaces can be served by the DMA controller.

Table 10. STM32F042x4/x6 USART implementation

USART modes/features

(1)

USART1

Hardware flow control for modem

Continuous communication using DMA

Multiprocessor communication

Synchronous mode

Smartcard mode

Single-wire half-duplex communication

IrDA SIR ENDEC block

LIN mode

Dual clock domain and wakeup from Stop mode

Receiver timeout interrupt

USART2

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Functional overview STM32F042x4 STM32F042x6

Table 10. STM32F042x4/x6 USART implementation (continued)

USART modes/features

(1)

USART1 USART2

Modbus communication

Auto baud rate detection

Driver Enable

1. X = supported.

3.16 Serial peripheral interface (SPI) / Inter-integrated sound interface (I

2

S)

Up to two SPIs are able to communicate up to 18 Mbit/s in slave and master modes in fullduplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits.

One standard I

S interface (multiplexed with SPI1) supporting four different audio standards can operate as master or slave at half-duplex communication mode. It can be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data resolution and synchronized by a specific signal. Audio sampling frequency from 8 kHz up to 192 kHz can be set by an 8-bit programmable linear prescaler. When operating in master mode, it can output a clock for an external audio component at 256 times the sampling frequency.

Hardware CRC calculation

Rx/Tx FIFO

NSS pulse mode

S mode

TI mode

1. X = supported.

Table 11. STM32F042x4/x6 SPI/I

S implementation

SPI features

(1)

SPI1

SPI2

3.17 High-definition electronics control (CEC)

The device embeds a HDMI-CEC controller that provides hardware support for the

Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard).

This protocol provides high-level control functions between all audiovisual products in an environment. It is specified to operate at low speeds with minimum processing and memory overhead. It has a clock domain independent from the CPU clock, allowing the HDMI_CEC controller to wakeup the MCU from Stop mode on data reception.

3.18 Controller area network (CAN)

The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames

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DocID025832 Rev 5

STM32F042x4 STM32F042x6 Functional overview with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and

14 scalable filter banks.

3.19 Universal serial bus (USB)

The STM32F042x4/x6 embeds a full-speed USB device peripheral compliant with the USB specification version 2.0. The internal USB PHY supports USB FS signaling, embedded DP pull-up and also battery charging detection according to Battery Charging Specification

Revision 1.2. The USB interface implements a full-speed (12 Mbit/s) function interface with added support for USB 2.0 Link Power Management. It has software-configurable endpoint setting with packet memory up-to 1 KB (the last 256 byte are used for CAN peripheral if enabled) and suspend/resume support. It requires a precise 48 MHz clock which can be generated from the internal main PLL (the clock source must use an HSE crystal oscillator) or by the internal 48 MHz oscillator in automatic trimming mode. The synchronization for this oscillator can be taken from the USB data stream itself (SOF signalization) which allows crystal-less operation.

The STM32F042x4/x6 embeds a special block which allows automatic trimming of the internal 48 MHz oscillator to guarantee its optimal accuracy over the whole device operational range. This automatic trimming is based on the external synchronization signal, which could be either derived from USB SOF signalization, from LSE oscillator, from an external signal on CRS_SYNC pin or generated by user software. For faster lock-in during startup it is also possible to combine automatic trimming with manual trimming action.

3.21 Serial wire debug port (SW-DP)

An ARM SW-DP interface is provided to allow a serial wire debugging tool to be connected to the MCU.

DocID025832 Rev 5

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Pinouts and pin descriptions

4 Pinouts and pin descriptions

STM32F042x4 STM32F042x6

Figure 3. LQFP48 package pinout

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28/117

DocID025832 Rev 5

STM32F042x4 STM32F042x6 Pinouts and pin descriptions

7RSYLHZ

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Figure 6. LQFP32 package pinout

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DocID025832 Rev 5

29/117

Pinouts and pin descriptions STM32F042x4 STM32F042x6

Figure 7. UFQFPN32 package pinout

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1. Pin pair PA11/12 can be remapped in place of pin pair PA9/10 using the SYSCFG_CFGR1 register.

06Y9

30/117

DocID025832 Rev 5

STM32F042x4 STM32F042x6 Pinouts and pin descriptions

Figure 9. TSSOP20 package

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Name

Table 12. Legend/abbreviations used in the pinout table

Abbreviation Definition

I/O structure

Pin name

Pin type functions

Notes

Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name

I/O

Supply pin

Input / output pin

FTf

TTa

5 V-tolerant I/O

5 V-tolerant I/O, FM+ capable

3.3 V-tolerant I/O directly connected to ADC

Standard 3.3 V I/O

RST Bidirectional reset pin with embedded weak pull-up resistor

Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset.

Alternate functions

Additional functions

Functions selected through GPIOx_AFR registers

Functions directly selected/enabled through peripheral registers

DocID025832 Rev 5

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Pinouts and pin descriptions

Table 13. STM32F042x pin definitions

STM32F042x4 STM32F042x6

Pin numbers Pin functions

Pin name

(function upon reset)

Pin type

Alternate function

Additional functions

1 -

2 A6 -

VBAT

PC13

S -

I/O TC

(1)

(2)

Backup power supply

WKUP2,

RTC_TAMP1,

RTC_TS,

RTC_OUT

7 D5 4 4 4 4

8 D6 32 0 16 15

9 E5 5 5 5 5

10 F6 6

11 D4 7

12 E4 8

13 F5 9

PC14-

OSC32_IN

(PC14)

PC15-

OSC32_OUT

(PC15)

PF0-OSC_IN

(PF0)

PF1-OSC_OUT

(PF1)

NRST

VSSA

VDDA

PA0

PA1

PA2

PA3

I/O TC

(1)

(2)

I/O TC

(1)

(2)

I/O FTf -

CRS_ SYNC

I2C1_SDA

OSC32_IN

OSC32_OUT

OSC_IN

I/O FTf -

I/O RST -

(3)

I/O TTa -

I2C1_SCL OSC_OUT

Device reset input / internal reset output

(active low)

Analog ground

Analog power supply

USART2_CTS,

TIM2_CH1_ETR,

TSC_G1_IO1

RTC_

TAMP2,

WKUP1,

ADC_IN0,

USART2_RTS,

TIM2_CH2,

TSC_G1_IO2,

EVENTOUT

USART2_TX,

TIM2_CH3,

TSC_G1_IO3

ADC_IN1

ADC_IN2,

WKUP4

USART2_RX,

TIM2_CH4,

TSC_G1_IO4

ADC_IN3

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DocID025832 Rev 5

STM32F042x4 STM32F042x6 Pinouts and pin descriptions

Pin numbers

Table 13. STM32F042x pin definitions (continued)

Pin functions

Pin name

(function upon reset)

Pin type

Alternate function

Additional functions

14 C3 10 10 10 10

15 D3 11 11 11 11

16 E3 12 12 12 12

17 F4 13 13 13 13

18 F3

22 -

19 F2 15 15 15 14

20 D2 16 -

21 -

23 F1 16 0 16 15

24 17 16

25 -

PA4

PA5

PA6

PA7

PB0

PB1

PB2

PB10

PB11

VSS

VDD

PB12

I/O TTa -

I/O FT

I/O FTf -

I/O

SPI1_NSS, I2S1_WS,

TIM14_CH1,

TSC_G2_IO1,

USART2_CK

USB_NOE

SPI1_SCK, I2S1_CK,

CEC,

TIM2_CH1_ETR,

TSC_G2_IO2

SPI1_MISO, I2S1_MCK,

TIM3_CH1, TIM1_BKIN,

TIM16_CH1,

TSC_G2_IO3,

EVENTOUT

SPI1_MOSI, I2S1_SD,

TIM3_CH2, TIM14_CH1,

TIM1_CH1N,

TIM17_CH1,

TSC_G2_IO4,

EVENTOUT

TIM3_CH3,

TIM1_CH2N,

TSC_G3_IO2,

EVENTOUT

ADC_IN4

ADC_IN5

ADC_IN6

ADC_IN7

ADC_IN8

TIM3_CH4, TIM14_CH1,

TIM1_CH3N,

TSC_G3_IO3

TSC_G3_IO4

SPI2_SCK, CEC,

TSC_SYNC, TIM2_CH3,

I2C1_SCL

TIM2_CH4,

EVENTOUT,

I2C1_SDA

ADC_IN9

Ground

Digital power supply

TIM1_BKIN, SPI2_NSS,

EVENTOUT

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Pinouts and pin descriptions STM32F042x4 STM32F042x6

Pin numbers

Table 13. STM32F042x pin definitions (continued)

Pin functions

Pin name

(function upon reset)

Pin type

Alternate function

Additional functions

26 -

27 -

28 -

21 19

22 20

(5)

34 B1 23 23 21 19

35 -

36 E1 17 17 18 16

37 B2 24 24 22 20

PB13

PB14

PB15

PA8

PA9

PA10

PA11

PA12

PA13

VSS

VDDIO2

PA14

I/O

FTf

(4)

(6)

(4)

(6)

SPI2_SCK,

TIM1_CH1N,

I2C1_SCL

SPI2_MISO,

TIM1_CH2N,

I2C1_SDA

SPI2_MOSI,

TIM1_CH3N

USART1_CK,

TIM1_CH1,

EVENTOUT, MCO,

CRS_SYNC

WKUP7,

RTC_REFIN

USART1_TX,

TIM1_CH2,

TSC_G4_IO1,

I2C1_SCL

USART1_RX,

TIM1_CH3,

TIM17_BKIN,

TSC_G4_IO2,

I2C1_SDA

CAN_RX,

USART1_CTS,

TIM1_CH4,

TSC_G4_IO3,

EVENTOUT,

I2C1_SCL

CAN_TX,USART1_RTS,

TIM1_ETR,

TSC_G4_IO4,

EVENTOUT,

I2C1_SDA

USB_DM

USB_DP

IR_OUT, SWDIO

USB_NOE

Ground

Digital power supply

USART2_TX, SWCLK -

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STM32F042x4 STM32F042x6 Pinouts and pin descriptions

Pin numbers

Table 13. STM32F042x pin definitions (continued)

Pin functions

Pin name

(function upon reset)

Pin type

Alternate function

Additional functions

38 A2 25 25 23

PA15

PB3

PB4

PB5

PB6

PB7

PF11-BOOT0

PB8-BOOT0

PB8

I/O

FTf

(4)

SPI1_NSS, I2S1_WS,

USART2_RX,

TIM2_CH1_ETR,

EVENTOUT,

USB_NOE

SPI1_SCK, I2S1_CK,

TIM2_CH2,

TSC_G5_IO1,

EVENTOUT

SPI1_MISO, I2S1_MCK,

TIM17_BKIN,

TIM3_CH1,

TSC_G5_IO2,

EVENTOUT

SPI1_MOSI, I2S1_SD,

I2C1_SMBA,

TIM16_BKIN,

TIM3_CH2

I2C1_SCL,

USART1_TX,

TIM16_CH1N,

TSC_G5_I03

I2C1_SDA,

USART1_RX,

TIM17_CH1N,

TSC_G5_IO4

I/O FT -

I/O

FTf

FTf -

I2C1_SCL, CEC,

TIM16_CH1,

TSC_SYNC,

CAN_RX

I2C1_SCL, CEC,

TIM16_CH1,

TSC_SYNC,

CAN_RX

WKUP6

Boot memory selection

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Pinouts and pin descriptions STM32F042x4 STM32F042x6

Pin numbers

Table 13. STM32F042x pin definitions (continued)

Pin functions

Pin name

(function upon reset)

Pin type

Alternate function

Additional functions

46 -

47 32 0

48 A5 1 1

PB9

VSS

VDD

I/O

FTf

SPI2_NSS,

I2C1_SDA, IR_OUT,

TIM17_CH1,

EVENTOUT,

CAN_TX

Ground

Digital power supply

1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current

(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:

- The speed should not exceed 2 MHz with a maximum load of 30 pF.

- These GPIOs must not be used as current sources (e.g. to drive an LED).

2. After the first RTC domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers which are not reset by the system reset. For details on how to manage these GPIOs, refer to the RTC domain and RTC register descriptions in the reference manual.

3. Distinct VSSA pin is only available on 48-pin packages. On all other packages, the pin number corresponds to the VSS pin to which VSSA pad of the silicon die is connected.

4. PA8, PA9, PA10, PA11, PA12, PA13, PA14 and PA15 I/Os are supplied by VDDIO2.

5. Pin pair PA11/12 can be remapped in place of pin pair PA9/10 using SYSCFG_CFGR1 register.

6. After reset, these pins are configured as SWDIO and SWCLK alternate functions, and the internal pull-up on the SWDIO pin and the internal pull-down on the SWCLK pin are activated.

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DocID025832 Rev 5

Pin name

PA7

PA8

PA9

PA10

PA11

PA12

PA13

PA14

PA15

PA0

PA1

PA2

PA3

PA4

PA5

PA6

Table 14. Alternate functions selected through GPIOA_AFR registers for port A

AF0

EVENTOUT

SPI1_NSS, I2S1_WS

SPI1_SCK, I2S1_CK

SPI1_MISO, I2S1_MCK

SPI1_MOSI, I2S1_SD

MCO

TIM17_BKIN

EVENTOUT

SWDIO

SWCLK

SPI1_NSS, I2S1_WS

AF1 AF2 AF3 AF4

USART2_CTS TIM2_CH1_ETR TSC_G1_IO1

USART2_RTS

USART2_TX

TIM2_CH2

TIM2_CH3

TSC_G1_IO2

TSC_G1_IO3

USART2_RX

USART2_CK

CEC

TIM3_CH1

TIM2_CH4

USB_NOE

TSC_G1_IO4

TSC_G2_IO1 TIM14_CH1

TIM2_CH1_ETR TSC_G2_IO2

TIM1_BKIN TSC_G2_IO3

TIM3_CH2

USART1_CK

USART1_TX

USART1_RX

TIM1_CH1N

TIM1_CH1

TIM1_CH2

TIM1_CH3

TSC_G2_IO4 TIM14_CH1

EVENTOUT CRS_SYNC

TSC_G4_IO1

TSC_G4_IO2

I2C1_SCL

I2C1_SDA

USART1_CTS

USART1_RTS

IR_OUT

USART2_TX

TIM1_CH4

TIM1_ETR

USB_NOE

TSC_G4_IO3

TSC_G4_IO4

USART2_RX TIM2_CH1_ETR EVENTOUT

CAN_RX

CAN_TX

AF5 AF6

TIM16_CH1 EVENTOUT

TIM17_CH1 EVENTOUT

MCO

I2C1_SCL

I2C1_SDA

USB_NOE

AF7

Pin name

PB7

PB8

PB9

PB10

PB11

PB12

PB13

PB14

PB15

PB0

PB1

PB2

PB3

PB4

PB5

PB6

AF0

Table 15. Alternate functions selected through GPIOB_AFR registers for port B

AF1 AF2 AF3 AF4

EVENTOUT

TIM14_CH1

SPI1_SCK, I2S1_CK

SPI1_MISO, I2S1_MCK

SPI1_MOSI, I2S1_SD

USART1_TX

TIM3_CH3

TIM3_CH4

EVENTOUT

TIM3_CH1

TIM3_CH2

I2C1_SCL

USART1_RX

CEC

IR_OUT

CEC

I2C1_SDA

I2C1_SCL

I2C1_SDA

I2C1_SCL

EVENTOUT

SPI2_NSS

I2C1_SDA

EVENTOUT

SPI2_SCK -

SPI2_MISO -

SPI2_MOSI -

TIM1_CH2N

TIM1_CH3N

TIM2_CH2

EVENTOUT

TIM16_BKIN

TIM16_CH1N

TIM17_CH1N

TIM16_CH1

TIM17_CH1

TIM2_CH3

TIM2_CH4

TIM1_BKIN

TIM1_CH1N

TIM1_CH2N

TIM1_CH3N

TSC_G3_IO2

TSC_G3_IO3

TSC_G3_IO4

TSC_G5_IO1

TSC_G5_IO2

I2C1_SMBA

TSC_G5_IO3

TSC_G5_IO4

TSC_SYNC

EVENTOUT

TSC_SYNC

CAN_RX

CAN_TX

Pin name

PF0

PF1

Table 16. Alternate functions selected through GPIOF_AFR registers for port F

AF0

CRS_SYNC

AF1

I2C1_SDA

I2C1_SCL

AF5

TIM17_BKIN

SPI2_NSS

SPI2_SCK

I2C1_SCL

I2C1_SDA

STM32F042x4 STM32F042x6 Memory mapping

To the difference of STM32F042x6 memory map in

Figure 10

, the two bottom code memory spaces of STM32F042x4 end at 0x0000 3FFF and 0x0800 3FFF, respectively.

Figure 10. STM32F042x6 memory map

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DocID025832 Rev 5

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Memory mapping STM32F042x4 STM32F042x6

Bus

AHB2

AHB1

APB

Table 17. STM32F042x4/x6 peripheral register boundary addresses

Boundary address Size Peripheral

0x4800 1800 - 0x5FFF FFFF

0x4800 1400 - 0x4800 17FF

0x4800 0C00 - 0x4800 13FF

0x4800 0800 - 0x4800 0BFF

0x4800 0400 - 0x4800 07FF

0x4800 0000 - 0x4800 03FF

0x4002 4400 - 0x47FF FFFF

0x4002 4000 - 0x4002 43FF

0x4002 3400 - 0x4002 3FFF

0x4002 3000 - 0x4002 33FF

0x4002 2400 - 0x4002 2FFF

0x4002 2000 - 0x4002 23FF

0x4002 1400 - 0x4002 1FFF

0x4002 1000 - 0x4002 13FF

0x4002 0400 - 0x4002 0FFF

0x4002 0000 - 0x4002 03FF

0x4001 8000 - 0x4001 FFFF

0x4001 5C00 - 0x4001 7FFF

0x4001 5800 - 0x4001 5BFF

0x4001 4C00 - 0x4001 57FF

0x4001 4800 - 0x4001 4BFF

0x4001 4400 - 0x4001 47FF

0x4001 3C00 - 0x4001 43FF

0x4001 3800 - 0x4001 3BFF

0x4001 3400 - 0x4001 37FF

0x4001 3000 - 0x4001 33FF

0x4001 2C00 - 0x4001 2FFF

0x4001 2800 - 0x4001 2BFF

0x4001 2400 - 0x4001 27FF

0x4001 0800 - 0x4001 23FF

0x4001 0400 - 0x4001 07FF

0x4001 0000 - 0x4001 03FF

0x4000 8000 - 0x4000 FFFF

1 KB

2 KB

1 KB

3 KB

1 KB

32 KB

9 KB

1 KB

3 KB

1 KB

7 KB

1 KB

32 KB

3 KB

1 KB

3 KB

1 KB

3 KB

1 KB

~384 MB

1 KB

2 KB

1 KB

~128 MB

1 KB

Reserved

GPIOF

Reserved

GPIOC

GPIOB

GPIOA

Reserved

TSC

Reserved

CRC

Reserved

Flash memory interface

Reserved

RCC

Reserved

DMA

Reserved

DBGMCU

Reserved

TIM17

TIM16

Reserved

USART1

Reserved

SPI1/I2S1

TIM1

Reserved

ADC

Reserved

EXTI

SYSCFG

Reserved

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STM32F042x4 STM32F042x6 Memory mapping

Bus

Table 17. STM32F042x4/x6 peripheral register boundary addresses (continued)

Boundary address Size Peripheral

APB

0x4000 7C00 - 0x4000 7FFF

0x4000 7800 - 0x4000 7BFF

0x4000 7400 - 0x4000 77FF

0x4000 7000 - 0x4000 73FF

0x4000 6C00 - 0x4000 6FFF

0x4000 6800 - 0x4000 6BFF0

0x4000 6400 - 0x4000 67FF

0x4000 6000 - 0x4000 63FF

0x4000 5C00 - 0x4000 5FFF

0x4000 5800 - 0x4000 5BFF

0x4000 5400 - 0x4000 57FF

0x4000 4800 - 0x4000 53FF

0x4000 4400 - 0x4000 47FF

0x4000 3C00 - 0x4000 43FF

0x4000 3800 - 0x4000 3BFF

0x4000 3400 - 0x4000 37FF

0x4000 3000 - 0x4000 33FF

0x4000 2C00 - 0x4000 2FFF

0x4000 2800 - 0x4000 2BFF

0x4000 2400 - 0x4000 27FF

0x4000 2000 - 0x4000 23FF

0x4000 0800 - 0x4000 1FFF

0x4000 0400 - 0x4000 07FF

0x4000 0000 - 0x4000 03FF

1 KB

3 KB

1 KB

2 KB

1 KB

6 KB

1 KB

Reserved

CEC

Reserved

PWR

CRS

Reserved

BxCAN

USB/CAN RAM

USB

Reserved

I2C1

Reserved

USART2

Reserved

SPI2

Reserved

IWDG

WWDG

RTC

Reserved

TIM14

Reserved

TIM3

TIM2

DocID025832 Rev 5

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Electrical characteristics STM32F042x4 STM32F042x6

6.1.1

Unless otherwise specified, all voltages are referenced to V

Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T

A the selected temperature range).

= 25 °C and T

= T

A max (given by

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ±3 σ ).

Unless otherwise specified, typical data are based on T

A are given only as design guidelines and are not tested.

= 25 °C, V

= V

DDA

= 3.3 V. They

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ±2 σ ).

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

6.1.5

The loading conditions used for pin parameter measurement are shown in

Figure 11

Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 12 .

Figure 11. Pin loading conditions Figure 12. Pin input voltage

0&8SLQ 0&8SLQ

& S)

42/117

069

DocID025832 Rev 5

069

STM32F042x4 STM32F042x6

6.1.6 Power supply scheme

Figure 13. Power supply scheme

Electrical characteristics

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Caution: Each power supply pair (V

, V

DDA

SSA

etc.) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device.

DocID025832 Rev 5

43/117

Electrical characteristics STM32F042x4 STM32F042x6

Figure 14. Current consumption measurement scheme

''B9%$7

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9''

9'',2

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069

44/117

DocID025832 Rev 5

STM32F042x4 STM32F042x6

6.2

Electrical characteristics

Absolute maximum ratings

Stresses above the absolute maximum ratings listed in

Table 18: Voltage characteristics

Table 19: Current characteristics

and

Table 20: Thermal characteristics may cause

permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Table 18. Voltage characteristics

(1)

Ratings Min Symbol Max Unit

–V

DDIO2

–V

DDA

–V

DDA

BAT

–V

(2)

External main supply voltage

External I/O supply voltage

External analog supply voltage

Allowed voltage difference for V

> V

DDA

External backup supply voltage

Input voltage on FT and FTf pins

Input voltage on TTa pins

Input voltage on any other pin

- 0.3

4.0

0.4

4.0

DDIOx

+ 4.0

4.0

| ∆ V

DDx

| Variations between different V

DD power pins

SSx

- V

Variations between all the different ground pins

ESD(HBM)

Electrostatic discharge voltage

(human body model)

50 see

Section 6.3.12: Electrical sensitivity characteristics

(3) mV

1. All main power (V , V ) and ground (V supply, in the permitted range.

, V

SSA

) pins must always be connected to the external power

2. V

maximum must always be respected. Refer to

Table 19: Current characteristics for the maximum

allowed injected current values.

3. Valid only if the internal pull-up/pull-down resistors are disabled. If internal pull-up or pull-down resistor is enabled, the maximum limit is 4 V.

V mV

DocID025832 Rev 5

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Electrical characteristics STM32F042x4 STM32F042x6

Table 19. Current characteristics

Symbol Ratings Max.

Unit

Σ I

VDD

Σ I

VSS

VDD(PIN)

VSS(PIN)

Total current into sum of all VDD power lines (source)

Total current out of sum of all VSS ground lines (sink)

Maximum current into each VDD power pin (source)

Maximum current out of each VSS ground pin (sink)

(1)

120

-120

100

-100

Output current sunk by any I/O and control pin 25

IO(PIN)

Output current source by any I/O and control pin

Total output current sunk by sum of all I/Os and control pins

(2)

Total output current sourced by sum of all I/Os and control pins

(2)

-25

Σ I

IO(PIN)

-80 mA

Total output current sourced by sum of all I/Os supplied by VDDIO2

Injected current on FT and FTf pins

-40

-5/+0 (4)

INJ(PIN)

(3)

Injected current on TC and RST pin

Injected current on TTa pins

(5)

Total injected current (sum of all I/O and control pins)

(6)

± 5

Σ I

INJ(PIN)

± 25

1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range.

2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.

3. A positive injection is induced by V

exceeded. Refer to

> V

DDIOx

while a negative injection is induced by V

< V

. I

Table 18: Voltage characteristics for the maximum allowed input voltage values.

must never be

4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.

5. On these I/Os, a positive injection is induced by V

device. See note below

Table 56: ADC accuracy .

> V

DDA

. Negative injection disturbs the analog performance of the

6. When several inputs are submitted to a current injection, the maximum negative injected currents (instantaneous values).

Σ I

INJ(PIN)

is the absolute sum of the positive and

Symbol

STG

Table 20. Thermal characteristics

Ratings

Storage temperature range

Maximum junction temperature

Value

–65 to +150

150

Unit

°C

46/117

DocID025832 Rev 5

STM32F042x4 STM32F042x6 Electrical characteristics

6.3.1 General operating conditions

Symbol

Table 21. General operating conditions

Parameter Conditions Min Max Unit

V f f

HCLK

PCLK

DDIO2

DDA

BAT

Internal AHB clock frequency

Internal APB clock frequency

Standard operating voltage

I/O supply voltage

Must not be supplied if V

DD is not present

Analog operating voltage

(ADC not used)

Analog operating voltage

(ADC used)

Backup operating voltage

Must have a potential equal to or higher than V

I/O input voltage

TC and RST I/O

TTa I/O

FT and FTf I/O

LQFP48

UFQFPN48

WLCSP36

Power dissipation at T

A for suffix 6 or T

A suffix 7

(2)

= 85 °C

= 105 °C for LQFP32

UFQFPN32

UFQFPN28

TSSOP20

Ambient temperature for the suffix 6 version

Ambient temperature for the suffix 7 version

Junction temperature range

Maximum power dissipation

Low power dissipation (3)

Maximum power dissipation

Low power dissipation

(3)

Suffix 6 version

Suffix 7 version

2.0

1.65

2.4

1.65

-0.3

–40

3.6

DDIOx

+0.3

DDA

+0.3

(1)

5.5

(1)

364

606

313

351

526

170

263

–40 105

–40 125

–40 105

125

MHz

V mW

°C

1. For operation with a voltage higher than V

DDIOx

+ 0.3 V, the internal pull-up resistor must be disabled.

2. If T

is lower, higher P

values are allowed as long as T

does not exceed T

Jmax

. See

Section 7.8: Thermal characteristics

3. In low power dissipation state, T

can be extended to this range as long as T

does not exceed T

Jmax

(see

Section 7.8:

Thermal characteristicsSection 7.8: Thermal characteristics

The parameters given in

Table 22 are derived from tests performed under the ambient

temperature condition summarized in

Table 21 .

DocID025832 Rev 5

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Electrical characteristics STM32F042x4 STM32F042x6

Symbol t

VDD t

VDDA

Table 22. Operating conditions at power-up / power-down

Parameter Conditions Min Max

rise time rate

fall time rate

DDA

rise time rate

DDA

fall time rate

∞

Unit

µs/V

6.3.3 Embedded reset and power control block characteristics

The parameters given in

Table 23 are derived from tests performed under the ambient

temperature and supply voltage conditions summarized in Table 21: General operating conditions

Table 23. Embedded reset and power control block characteristics

Symbol Parameter Conditions Min Typ Max Unit

POR/PDR

(1)

Power on/power down reset threshold

Falling edge

Rising edge

(2) 1.80

1.84

(3)

1.88

1.92

1.96

(3)

2.00

PDRhyst t

RSTTEMPO

(4)

PDR hysteresis

Reset temporization -

1.50

2.50

4.50

1. The PDR detector monitors V monitors only V

and also V

DDA

(if kept enabled in the option bytes). The POR detector

2. The product behavior is guaranteed by design down to the minimum V

POR/PDR

value.

3. Data based on characterization results, not tested in production.

4. Guaranteed by design, not tested in production.

mV ms

Symbol

PVD0

PVD1

PVD2

PVD3

PVD4

PVD5

Table 24. Programmable voltage detector characteristics

Parameter Conditions Min Typ Max

PVD threshold 0

PVD threshold 1

PVD threshold 2

PVD threshold 3

PVD threshold 4

PVD threshold 5

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

2.1

2.19

2.09

2.28

2.18

2.38

2.28

2.47

2.37

2.57

2.47

2.18

2.26

2.08

2.16

2.28

2.37

2.18

2.27

2.38

2.48

2.28

2.38

2.48

2.58

2.38

2.48

2.58

2.69

2.48

2.59

2.68

2.79

2.58

2.69

Unit

48/117

DocID025832 Rev 5

STM32F042x4 STM32F042x6 Electrical characteristics

Table 24. Programmable voltage detector characteristics (continued)

Symbol Parameter Conditions Min Typ Max

PVD6

PVD7

PVD threshold 6

PVD threshold 7

PVDhyst

(1)

DD(PVD)

PVD hysteresis

PVD current consumption

1. Guaranteed by design, not tested in production.

Rising edge

Falling edge

Rising edge

Falling edge

2.66

2.56

2.76

2.66

2.78

2.68

2.88

2.78

2.9

2.8

2.9

100 -

0.15

0.26

(1)

Unit

V mV

µA

6.3.5

The parameters given in

Table 25 are derived from tests performed under the ambient

temperature and supply voltage conditions summarized in Table 21: General operating conditions

Symbol

Table 25. Embedded internal reference voltage

Parameter Conditions Min Typ Max Unit

∆ t t

REFINT

START

S_vrefint

REFINT

Internal reference voltage –40 °C < T

< +105 °C

ADC_IN17 buffer startup time

ADC sampling time when reading the internal reference voltage

Internal reference voltage spread over the temperature range

DDA

= 3 V

Coeff

Temperature coefficient

1. Guaranteed by design, not tested in production.

1.2

1.23

1.25

(1)

- 100

(1)

µs

µs mV

100

(1) ppm/°C

Supply current characteristics

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code.

The current consumption is measured as described in

Figure 14: Current consumption measurement scheme

All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to CoreMark code.

DocID025832 Rev 5

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Electrical characteristics STM32F042x4 STM32F042x6

Typical and maximum current consumption

The MCU is placed under the following conditions:

• All I/O pins are in analog input mode

• All peripherals are disabled except when explicitly mentioned

• The Flash memory access time is adjusted to the f

HCLK

frequency:

– 0 wait state and Prefetch OFF from 0 to 24 MHz

– 1 wait state and Prefetch ON above 24 MHz

• When the peripherals are enabled f

PCLK

= f

HCLK

The parameters given in

Table 26 to

Table 28

are derived from tests performed under ambient temperature and supply voltage conditions summarized in

Table 21: General operating conditions

Table 26. Typical and maximum current consumption from V

supply at V

= 3.6 V

All peripherals enabled

(1)

All peripherals disabled

Conditions f

HCLK

Max @ T

(2)

Max @ T

(2)

Typ Typ

25 °C 85 °C 105 °C 25 °C 85 °C 105 °C

Unit

HSI48

HSE bypass,

PLL on

48 MHz 20.3

48 MHz 20.2

32 MHz 14.0

24 MHz 11.0

HSE bypass,

PLL off

HSI clock,

PLL on

8 MHz

1 MHz

3.9

0.9

48 MHz 20.5

32 MHz 14.3

24 MHz 11.2

HSI clock,

PLL off

8 MHz 4.1

5.2

1.3

23.1

15.6

13.6

23.2

22.9

16.0

13.5

5.2

5.3

1.5

23.3

15.9

13.8

23.4

23.0

16.1

13.7

5.3

5.6

1.8

23.6

17.0

14.8

24.6

23.9

16.7

13.8

5.6

12.7

14.4

12.6

14.1

8.7

9.5

6.9

7.6

2.6

0.7

3.1

1.0

12.8

14.6

8.6

6.9

9.5

7.4

2.6

3.1

3.2

1.1

14.6

9.7

7.5

14.4

14.3

9.7

7.8

3.1

3.3

1.3

15.0

10.0

7.7

14.7

14.4

10.3

8.2

3.3

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STM32F042x4 STM32F042x6 Electrical characteristics

Table 26. Typical and maximum current consumption from V

supply at V

= 3.6 V (continued)

All peripherals enabled

(1)

All peripherals disabled

Conditions f

HCLK

Max @ T

(2)

Max @ T

(2)

Unit

Typ Typ

25 °C 85 °C 105 °C 25 °C 85 °C 105 °C

HSI48

HSE bypass,

PLL on

48 MHz 19.3

21.9

48 MHz 19.2

21.8

(3)

22.1

23.7

22.0

22.1

(3)

11.9

13.4

11.7 13.3

(3)

32 MHz 13.4

15.8

15.9

16.0

7.9

8.8

24 MHz 10.3

12.6

13.0

13.4

6.2

8.0

8 MHz 3.6

4.1

4.3

4.4

2.0

2.1

1.6

0.7

0.1

3.0

2.1

1.6

3.0

3.2

2.9

3.2

(3)

1.9

2.1

1.8

0.8

0.3

3.0

2.2

1.6

3.2

2.2

1.7

1.8

0.8

0.3

3.3

2.2

13.6

13.7

13.5

13.7

(3)

8.9

8.2

2.1

9.7

8.3

2.5

HSE bypass,

PLL off

HSI clock,

PLL on

1 MHz 0.8

0.9

1.1

0.4

0.5

0.6

0.8

48 MHz 19.5

22.0

22.1

22.5

11.8

13.6

13.8

13.9

32 MHz 13.5

16.3

16.4

16.6

24 MHz 10.5

12.8

13.0

13.8

HSI clock,

PLL off

HSI48

HSE bypass,

PLL on

8 MHz 3.7

HSE bypass,

PLL off

HSI clock,

PLL on

1 MHz 0.4

48 MHz 12.4

32 MHz 8.6

24 MHz 6.6

4.7

0.4

15.3

10.7

8.4

5.0

48 MHz 12.4

15.1

48 MHz 12.3

15.0

(3)

16.3

16.7

16.0

16.2

(3)

32 MHz 8.5

10.6

11.2

24 MHz 6.5

8.1

8.5

11.7

8.7

8 MHz 2.3

3.0

3.1

3.2

0.4

15.7

11.3

8.7

5.3

0.6

15.9

11.6

8.9

8.0

6.5

2.1

8.8

8.0

2.3

9.1

8.1

2.4

9.9

8.4

3.0

3.4

(3)

2.5

1.9

0.9

0.4

3.4

2.5

1.9

HSI clock,

PLL off

8 MHz 2.4

3.2

3.4

3.6

0.6

0.8

0.9

1.0

1. USB is kept disabled as this IP functions only with a 48 MHz clock.

2. Data based on characterization results, not tested in production unless otherwise specified.

3. Data based on characterization results and tested in production (using one common test limit for sum of I

and I

DDA

DocID025832 Rev 5

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Electrical characteristics STM32F042x4 STM32F042x6

Symbol

Table 27. Typical and maximum current consumption from the V

DDA

supply

DDA

= 2.4 V V

DDA

= 3.6 V

Parameter

Conditions

(1) f

HCLK

Typ

Max @ T

(2)

Typ

Max @ T

(2)

25 °C 85 °C 105 °C 25 °C 85 °C 105 °C

Unit

DDA

Supply current in

Run or

Sleep mode, code executing from

Flash memory or RAM

HSI48

HSE bypass,

PLL on

HSE bypass,

PLL off

HSI clock,

PLL on

48 MHz 309 325

48 MHz 148 167

32 MHz

24 MHz

8 MHz

1 MHz

102

2.7

(3)

119

3.7

48 MHz 220 242

32 MHz 173 193

24 MHz 151 169

332

176 179

124

4.2

251

200

175

342

(3)

126

100

4.5

4.2

254

202

177

317 334 338

161 181

(3)

193

344

197

(3)

111

3.5

3.6

128

102

4.7

135

106

5.2

242 264 275

191 211 219

167 184 191

137

108

5.5

279

221

193

µA

HSI clock,

PLL off

8 MHz 72 82 85 85 82 92 95 95

1. Current consumption from the V the frequency.

DDA

supply is independent of whether the digital peripherals are enabled or disabled, being in Run or Sleep mode or executing from Flash memory or RAM. Furthermore, when the PLL is off, I

DDA

is independent from

2. Data based on characterization results, not tested in production unless otherwise specified.

3. Data based on characterization results and tested in production (using one common test limit for sum of I

and I

DDA

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STM32F042x4 STM32F042x6 Electrical characteristics

Table 28. Typical and maximum consumption in Stop and Standby modes

Typ @V

= V

DDA

) Max

(1)

Conditions

2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V

25°C

85°C

105°C

DDA

Supply current in

Stop mode

Regulator in run mode, all oscillators OFF

Regulator in lowpower mode, all oscillators OFF

Supply current in

Standby mode

LSI ON and IWDG

LSI OFF and IWDG

OFF

Supply current in

Stop mode

Supply current in

Standby mode

Supply current in

Stop mode

Supply current in

Standby mode

Regulator in run mode, all oscillators

OFF

Regulator in low-power mode, all oscillators

OFF

LSI ON and

IWDG ON

LSI OFF and

IWDG OFF

Regulator in run mode, all oscillators

OFF

Regulator in low-power mode, all oscillators

OFF

LSI ON and

IWDG ON

LSI OFF and

IWDG OFF

14.3

2.9

0.8

0.6

2.0

2.4

1.9

1.3

1.7

1.1

14.5

3.1

0.9

0.7

2.1

2.6

2.0

1.3

1.8

1.2

14.6

3.2

1.1

0.8

2.2

2.8

2.1

1.3

1.8

1.2

14.7

3.3

1.2

0.9

2.4

3.0

2.3

1.4

2.0

1.3

14.8

3.4

1.3

1.0

2.5

3.1

2.4

1.4

2.1

1.3

14.9

3.5

1.5

1.1

2.7

3.4

2.5

1.5

2.2

1.4

1. Data based on characterization results, not tested in production unless otherwise specified.

21.0

6.5

2.0

3.5

3.4

47.0

32.0

2.5

3.5

64.0

44.0

3.0

4.5

µA

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Electrical characteristics STM32F042x4 STM32F042x6

Table 29. Typical and maximum current consumption from the V

BAT

supply

Typ @ V

BAT

Max

(1)

Symbol Parameter Conditions

25 °C

85 °C

105 °C

Unit

VBAT

RTC domain supply current

LSE & RTC ON; “Xtal mode”: lower driving capability;

LSEDRV[1:0] = '00'

LSE & RTC ON; “Xtal mode” higher driving capability;

LSEDRV[1:0] = '11'

0.5

0.8

0.5

0.9

1. Data based on characterization results, not tested in production.

0.6

1.1

0.7

1.2

0.9

1.4

1.1

1.5

1.2

1.6

1.5

2.0

2.6

µA

Typical current consumption

The MCU is placed under the following conditions:

• V

= V

DDA

= 3.3 V

• All I/O pins are in analog input configuration

• The Flash memory access time is adjusted to f

HCLK

frequency:

– 0 wait state and Prefetch OFF from 0 to 24 MHz

– 1 wait state and Prefetch ON above 24 MHz

• When the peripherals are enabled, f

PCLK

= f

HCLK

• PLL is used for frequencies greater than 8 MHz

• AHB prescaler of 2, 4, 8 and 16 is used for the frequencies 4 MHz, 2 MHz, 1 MHz and

500 kHz respectively

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STM32F042x4 STM32F042x6 Electrical characteristics

Table 30. Typical current consumption, code executing from Flash memory,

running from HSE 8 MHz crystal

Typical consumption in

Run mode

Typical consumption in

Sleep mode

Symbol Parameter f

HCLK

Unit

Peripherals enabled

Peripherals disabled

Peripherals enabled

Peripherals disabled

DDA

48 MHz

36 MHz

32 MHz

Current consumption from V

DD supply

24 MHz

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

48 MHz

36 MHz

32 MHz

Current consumption from V

DDA supply

24 MHz

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

20.7

15.9

14.3

11.0

7.7

4.3

2.6

1.8

1.4

1.2

163.3

124.3

111.9

87.1

62.5

2.5

12.8

9.9

9.0

7.1

5.0

3.0

2.0

1.5

1.2

1.1

12.3

9.5

8.5

6.6

4.7

2.7

1.7

1.2

1.0

0.8

2.1

1.6

1.2

0.9

0.8

3.4

2.7

2.5

0.8

0.7

μ A

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in

Table 50: I/O static characteristics .

For the output pins, any external pull-down or external load must also be considered to estimate the current consumption.

Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt

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Electrical characteristics STM32F042x4 STM32F042x6 trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs.

Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode.

I/O dynamic current consumption

In addition to the internal peripheral current consumption measured previously (see

Table 32: Peripheral current consumption ), the I/Os used by an application also contribute

to the current consumption. When an I/O pin switches, it uses the current from the I/O supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load

(internal or external) connected to the pin:

DDIOx

×

C where

is the current sunk by a switching I/O to charge/discharge the capacitive load

DDIOx

is the I/O supply voltage f

is the I/O switching frequency

C is the total capacitance seen by the I/O pin: C = C

INT

+ C

EXT

+ C

is the PCB board capacitance including the pad pin.

The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency.

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STM32F042x4 STM32F042x6 Electrical characteristics

Symbol

Table 31. Switching output I/O current consumption

Parameter Conditions

(1)

I/O toggling frequency (f

)

I/O current consumption

DDIOx

= 3.3 V

C =C

INT

DDIOx

= 3.3 V

EXT

= 0 pF

C = C

INT

+ C

EXT

+ C

DDIOx

= 3.3 V

EXT

= 10 pF

C = C

INT

+ C

EXT

+ C

DDIOx

= 3.3 V

EXT

= 22 pF

C = C

INT

+ C

EXT

+ C

DDIOx

= 3.3 V

EXT

= 33 pF

C = C

INT

+ C

EXT

+ C

DDIOx

= 3.3 V

EXT

= 47 pF

C = C

INT

+ C

EXT

+ C

C = C int

DDIOx

= 2.4 V

EXT

= 47 pF

C = C

INT

+ C

EXT

+ C

C = C int

4 MHz

48 MHz

4 MHz

8 MHz

16 MHz

24 MHz

48 MHz

4 MHz

8 MHz

16 MHz

24 MHz

48 MHz

4 MHz

8 MHz

16 MHz

24 MHz

16 MHz

24 MHz

4 MHz

8 MHz

16 MHz

24 MHz

4 MHz

8 MHz

16 MHz

4 MHz

8 MHz

16 MHz

24 MHz

1. C

= 7 pF (estimated value).

Typ

0.07

2.188

0.32

0.64

1.25

2.23

4.442

0.49

0.94

0.18

0.37

0.76

1.39

0.15

0.31

0.53

0.92

3.24

5.02

0.81

1.7

2.38

3.99

0.64

1.25

3.67

0.66

1.43

2.45

4.97

Unit mA

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Electrical characteristics STM32F042x4 STM32F042x6

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in

Table 32 . The MCU is placed

under the following conditions:

• All I/O pins are in analog mode

• All peripherals are disabled unless otherwise mentioned

• The given value is calculated by measuring the current consumption

– with all peripherals clocked off

– with only one peripheral clocked on

•

Ambient operating temperature and supply voltage conditions summarized in Table 18:

Voltage characteristics

AHB

Table 32. Peripheral current consumption

Peripheral

BusMatrix

(1)

CRC

DMA

Flash memory interface

GPIOA

GPIOB

GPIOC

GPIOF

SRAM

TSC

All AHB peripherals

Typical consumption at 25 °C

2.2

1.9

5.1

15.0

8.2

7.7

2.1

1.8

1.1

4.9

49.8

Unit

µA/MHz

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STM32F042x4 STM32F042x6 Electrical characteristics

Table 32. Peripheral current consumption (continued)

APB

Peripheral Typical consumption at 25 °C

APB-Bridge

(2)

2.9

ADC (3) 3.9

CAN

CEC

CRS

DBG (MCU Debug Support)

12.9

1.5

1.0

0.2

I2C1

PWR

SPI1

SPI2

SYSCFG

TIM1

TIM2

TIM3

TIM14

TIM16

TIM17

USART1

USART2

USB

WWDG

3.6

1.4

8.5

6.1

1.8

15.1

16.8

11.7

5.5

7.0

6.9

17.8

5.6

4.9

1.4

Unit

µA/MHz

All APB peripherals 136.7

1. The BusMatrix is automatically active when at least one master is ON (CPU, DMA).

2. The APB Bridge is automatically active when at least one peripheral is ON on the Bus.

3. The power consumption of the analog part (I

DDA

) of peripherals such as ADC is not included. Refer to the tables of characteristics in the subsequent sections.

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Electrical characteristics STM32F042x4 STM32F042x6

6.3.6 Wakeup time from low-power mode

The wakeup times given in

Table 33 are the latency between the event and the execution of

the first user instruction. The device goes in low-power mode after the WFE (Wait For

Event) instruction, in the case of a WFI (Wait For Interruption) instruction, 16 CPU cycles must be added to the following timings due to the interrupt latency in the Cortex M0 architecture.

The SYSCLK clock source setting is kept unchanged after wakeup from Sleep mode.

During wakeup from Stop or Standby mode, SYSCLK takes the default setting: HSI 8 MHz.

The wakeup source from Sleep and Stop mode is an EXTI line configured in event mode.

The wakeup source from Standby mode is the WKUP1 pin (PA0).

All timings are derived from tests performed under the ambient temperature and supply voltage conditions summarized in

Table 21: General operating conditions ..

Symbol Parameter

Table 33. Low-power mode wakeup timings

Typ @V

DD =

DDA

Conditions

= 2.0 V = 2.4 V = 2.7 V = 3 V = 3.3 V

Max Unit t

WUSTOP

Wakeup from Stop mode

Regulator in run mode

Regulator in low power mode t

WUSTANDBY t

WUSLEEP

Wakeup from

Standby mode

Wakeup from Sleep mode

3.2

7.0

60.4

3.1

5.8

55.6

2.9

5.2

53.5

2.9

4.9

4 SYSCLK cycles

2.8

4.6

µs

60/117

High-speed external user clock generated from an external source

In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in Section 6.3.14

. However,

Symbol f

HSE_ext

HSEH

HSEL t w(HSEH) t w(HSEL) t r(HSE) t f(HSE)

Table 34. High-speed external user clock characteristics

Parameter

(1)

User external clock source frequency

OSC_IN input pin high level voltage

OSC_IN input pin low level voltage

OSC_IN high or low time

OSC_IN rise or fall time

Min

0.7 V

DDIOx

Typ

Max

DDIOx

0.3 V

DDIOx

Unit

MHz

V ns

DocID025832 Rev 5

STM32F042x4 STM32F042x6 Electrical characteristics

1. Guaranteed by design, not tested in production.

Figure 15. High-speed external clock source AC timing diagram

WZ+6(+

9+6(+

9+6(/

WU+6(

7+6(

WI+6( WZ+6(/

069

Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in Section 6.3.14

. However,

Symbol

Table 35. Low-speed external user clock characteristics

Parameter

(1) f

LSE_ext

LSEH

LSEL t w(LSEH) t w(LSEL) t r(LSE) t f(LSE)

User external clock source frequency

OSC32_IN input pin high level voltage

OSC32_IN input pin low level voltage

OSC32_IN high or low time

OSC32_IN rise or fall time

1. Guaranteed by design, not tested in production.

Min

0.7 V

DDIOx

450

Typ

32.768

Max

1000

DDIOx

0.3 V

DDIOx

Unit kHz

V ns

Figure 16. Low-speed external clock source AC timing diagram

WZ/6(+

9/6(+

9/6(/

WU/6(

7/6(

WI/6(

WZ/6(/

069

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Electrical characteristics

Note:

STM32F042x4 STM32F042x6

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in

Table 36 . In the

application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics

(frequency, package, accuracy).

Symbol

Table 36. HSE oscillator characteristics

Parameter Conditions

(1)

Min

(2)

Typ Max

(2)

Unit f

OSC_IN

Oscillator frequency

Feedback resistor

HSE current consumption

During startup

(3)

= 3.3 V,

Rm = 30 Ω ,

CL = 10 pF@8 MHz

= 3.3 V,

Rm = 45 Ω ,

CL = 10 pF@8 MHz

= 3.3 V,

Rm = 30 Ω ,

CL = 5 pF@32 MHz

= 3.3 V,

Rm = 30 Ω ,

CL = 10 pF@32 MHz

200

0.4

0.5

0.8

8.5

MHz k Ω mA

= 3.3 V,

Rm = 30 Ω ,

CL = 20 pF@32 MHz

1.5

g m t

SU(HSE)

(4)

Oscillator transconductance

Startup time

Startup

is stabilized

2 -

mA/V ms

1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

2. Guaranteed by design, not tested in production.

3. This consumption level occurs during the first 2/3 of the t

SU(HSE) startup time

4. t

SU(HSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer

For C

and C

, it is recommended to use high-quality external ceramic capacitors in the

5 pF to 20 pF range (Typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see

Figure 17

). C

and C

L2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C

and C

. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing

and C

For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com

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STM32F042x4 STM32F042x6 Electrical characteristics

Figure 17. Typical application with an 8 MHz crystal

5HVRQDWRUZLWKLQWHJUDWHG

FDSDFLWRUV

26&B,1

0+]

UHVRQDWRU

(;7

26&B287

)

%LDV

FRQWUROOHG

JDLQ

+6(

069

1. R

EXT

value depends on the crystal characteristics.

Low-speed external clock generated from a crystal resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator oscillator. All the information given in this paragraph are based on design simulation results

obtained with typical external components specified in Table 37

. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Symbol

Table 37. LSE oscillator characteristics (f

LSE

= 32.768 kHz)

Parameter Conditions

(1)

Min

(2)

Typ Max

(2)

Unit

LSE current consumption low drive capability medium-low drive capability medium-high drive capability -

0.5

0.9

1.3

µA g m

Oscillator transconductance high drive capability low drive capability medium-low drive capability medium-high drive capability

1.6

µA/V high drive capability 25 t

SU(LSE)

(3)

Startup time V

DDIOx is stabilized 2 -

1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for

ST microcontrollers”.

2. Guaranteed by design, not tested in production.

3. t

SU(LSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer s

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Electrical characteristics

Note:

STM32F042x4 STM32F042x6

For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com

Figure 18. Typical application with a 32.768 kHz crystal

5HVRQDWRUZLWKLQWHJUDWHG

FDSDFLWRUV

26&B,1 I

/6(

N+]

UHVRQDWRU

'ULYH

SURJUDPPDEOH

DPSOLILHU

26&B287

Note:

6.3.8

069

An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one.

Internal clock source characteristics

The parameters given in

Table 38 are derived from tests performed under ambient

temperature and supply voltage conditions summarized in Table 21: General operating conditions

. The provided curves are characterization results, not tested in production.

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STM32F042x4 STM32F042x6 Electrical characteristics

High-speed internal (HSI) RC oscillator

Table 38. HSI oscillator characteristics

(1)

Parameter Conditions Min Symbol f

HSI

TRIM

DuCy

ACC

(HSI)

HSI

Frequency

HSI user trimming step

Duty cycle

Accuracy of the HSI oscillator

= -40 to 105°C

= -10 to 85°C

= 0 to 85°C

= 0 to 70°C

= 0 to 55°C

= 25°C (4)

I t su(HSI)

DDA(HSI)

HSI oscillator startup time

HSI oscillator power consumption

1. V

DDA

= 3.3 V, T

= -40 to 105°C unless otherwise specified.

2. Guaranteed by design, not tested in production.

3. Data based on characterization results, not tested in production.

4. Factory calibrated, parts not soldered.

45 (2)

-2.8

(3)

-1.9

(3)

-1.9

(3)

-1.3

(3)

-1

(3)

-1

(2)

Typ

Max

(2)

55 (2)

3.8

(3)

2.3

(3)

(2)

100

(2)

Unit

MHz

µs

µA

Figure 19. HSI oscillator accuracy characterization results for soldered parts

."9

.*/

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Electrical characteristics STM32F042x4 STM32F042x6

High-speed internal 14 MHz (HSI14) RC oscillator (dedicated to ADC)

Table 39. HSI14 oscillator characteristics

(1)

Parameter Conditions Min Typ Symbol f

HSI14

TRIM

DuCy

ACC

(HSI14)

HSI14

Frequency

HSI14 user-trimming step

Duty cycle

Accuracy of the HSI14 oscillator (factory calibrated)

(2)

= –40 to 105 °C –4.2

(3)

= –10 to 85 °C –3.2

(3)

= 0 to 70 °C –2.5

(3)

= 25 °C –1

(2)

I t su(HSI14)

DDA(HSI14)

HSI14 oscillator startup time

HSI14 oscillator power consumption

1. V

DDA

= 3.3 V, T

= –40 to 105 °C unless otherwise specified.

2. Guaranteed by design, not tested in production.

3. Data based on characterization results, not tested in production.

100 150

(2)

Max Unit

(2)

55 (2)

5.1

(3)

3.1

(3)

2.3

(3)

(2)

MHz

µs

µA

Figure 20. HSI14 oscillator accuracy characterization results

0$;

0,1

069

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STM32F042x4 STM32F042x6 Electrical characteristics

High-speed internal 48 MHz (HSI48) RC oscillator

Table 40. HSI48 oscillator characteristics

(1)

Parameter Conditions Min Typ Symbol f

HSI48

TRIM

Frequency

HSI48 user-trimming step

DuCy

(HSI48)

Duty cycle

ACC

HSI48

Accuracy of the HSI48 oscillator (factory calibrated)

0.09

(2)

45 (2)

= –40 to 105 °C -4.9

(3)

= –10 to 85 °C -4.1

(3)

= 0 to 70 °C -3.8

(3)

= 25 °C -2.8

I t su(HSI48)

DDA(HSI48)

HSI48 oscillator startup time

HSI48 oscillator power consumption

1. V

DDA

= 3.3 V, T

= –40 to 105 °C unless otherwise specified.

2. Guaranteed by design, not tested in production.

3. Data based on characterization results, not tested in production.

312

0.14

Max

0.2

(2)

55 (2)

4.7

(3)

3.7

(3)

3.4

(3)

2.9

(2)

350

(2)

Unit

MHz

µs

µA

Figure 21. HSI48 oscillator accuracy characterization results

0$;

0,1

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Electrical characteristics STM32F042x4 STM32F042x6

Low-speed internal (LSI) RC oscillator

Table 41. LSI oscillator characteristics

(1)

Parameter Min Typ Symbol f

LSI t su(LSI)

(2)

DDA(LSI)

(2)

Frequency 30

LSI oscillator startup time

LSI oscillator power consumption

1. V

DDA

= 3.3 V, T

= –40 to 105 °C unless otherwise specified.

2. Guaranteed by design, not tested in production.

0.75

Max

1.2

Unit kHz

µs

µA

The parameters given in

Table 42 are derived from tests performed under ambient

temperature and supply voltage conditions summarized in Table 21: General operating conditions

Table 42. PLL characteristics

Value

Symbol Parameter Unit

Min Typ Max f

PLL_IN

PLL input clock

(1)

PLL input clock duty cycle

(2)

40 (2)

(2)

8.0

(2)

MHz

% f

PLL_OUT t

LOCK

Jitter

PLL

PLL multiplier output clock

PLL lock time

Cycle-to-cycle jitter -

200

(2)

300

(2)

MHz

1. Take care to use the appropriate multiplier factors to obtain PLL input clock values compatible with the range defined by f

PLL_OUT

2. Guaranteed by design, not tested in production.

µs ps

68/117

Flash memory

The characteristics are given at T

= –40 to 105 °C unless otherwise specified.

Table 43. Flash memory characteristics

Symbol Parameter Conditions t

I prog t

ERASE t

16-bit programming time T

= - 40 to +105 °C

Page (1 KB) erase time T

= - 40 to +105 °C

Mass erase time T

= - 40 to +105 °C

Write mode

Supply current

Erase mode

1. Guaranteed by design, not tested in production.

Min

Typ Max

(1)

53.5

Unit

µs ms ms mA mA

DocID025832 Rev 5

STM32F042x4 STM32F042x6 Electrical characteristics

Symbol

Table 44. Flash memory endurance and data retention

Parameter Conditions

N t

END

RET

Endurance

Data retention

= –40 to +105 °C

1 kcycle

(2)

at T

= 85 °C

1 kcycle

(2)

at T

= 105 °C

10 kcycle (2) at T

= 55 °C

1. Data based on characterization results, not tested in production.

2. Cycling performed over the whole temperature range.

Min

(1)

Unit kcycle

Year

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

•

Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

• FTB : A Burst of Fast Transient voltage (positive and negative) is applied to V

SS compliant with the IEC 61000-4-4 standard.

and

through a 100 pF capacitor, until a functional disturbance occurs. This test is

A device reset allows normal operations to be resumed.

The test results are given in

Table 45

. They are based on the EMS levels and classes defined in application note AN1709.

Table 45. EMS characteristics

Symbol Parameter Conditions

Level/

Class

FESD

EFTB

Voltage limits to be applied on any I/O pin to induce a functional disturbance

= 3.3 V, LQFP48, T f

HCLK

= +25 °C,

= 48 MHz, conforming to IEC 61000-4-2

Fast transient voltage burst limits to be applied through 100 pF on V

and V pins to induce a functional disturbance

= 3.3 V, LQFP48, T

= +25°C, f

HCLK

= 48 MHz, conforming to IEC 61000-4-4

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

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Electrical characteristics STM32F042x4 STM32F042x6

Software recommendations

The software flowchart must include the management of runaway conditions such as:

• Corrupted program counter

• Unexpected reset

• Critical Data corruption (for example control registers)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with

IEC 61967-2 standard which specifies the test board and the pin loading.

Table 46. EMI characteristics

Symbol

EMI

Parameter

Peak level

Conditions

= 3.6 V, T

A compliant with

IEC 61967-2

= 25 °C,

LQFP48 package

Monitored frequency band

Max vs. [f

HSE

HCLK

]

0.1 to 30 MHz

30 to 130 MHz

130 MHz to 1 GHz

EMI Level

8/48 MHz

-9

Unit dBµV

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard.

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STM32F042x4 STM32F042x6 Electrical characteristics

Symbol Ratings

Table 47. ESD absolute maximum ratings

Conditions Packages Class

Maximum value

(1)

Unit

ESD(HBM)

ESD(CDM)

Electrostatic discharge voltage

(human body model)

= +25 °C, conforming to JESD22-A114

Electrostatic discharge voltage

(charge device model)

= +25 °C, conforming to ANSI/ESD STM5.3.1

1. Data based on characterization results, not tested in production.

All

2000

500

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up performance:

• A supply overvoltage is applied to each power supply pin.

• A current injection is applied to each input, output and configurable I/O pin.

These tests are compliant with EIA/JESD 78A IC latch-up standard.

Symbol

Parameter

Table 48. Electrical sensitivities

Conditions

Static latch-up class T

= +105 °C conforming to JESD78A

Class

II level A

As a general rule, current injection to the I/O pins, due to external voltage below V

SS above V

DDIOx product operation. However, in order to give an indication of the robustness of the

(for standard, 3.3 V-capable I/O pins) should be avoided during normal microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of the -5 µA/+0 µA range) or other functional failure (for example reset occurrence or oscillator frequency deviation).

The characterization results are given in

Table 49 .

Negative induced leakage current is caused by negative injection and positive induced leakage current is caused by positive injection.

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Electrical characteristics STM32F042x4 STM32F042x6

Symbol

INJ

Table 49. I/O current injection susceptibility

Description

Functional susceptibility

Negative injection

Positive injection

Unit

Injected current on PA12 pin

Injected current on PA9, PB3, PB13, PF11 pins with induced leakage current on adjacent pins less than 50 µA

Injected current on PB0, PB1 and all other FT and FTf pins

Injected current on all other TC, TTa and RST pins

-0

-5

+5 mA

General input/output characteristics

Unless otherwise specified, the parameters given in Table 50

are derived from tests

performed under the conditions summarized in Table 21: General operating conditions

. All

I/Os are designed as CMOS- and TTL-compliant.

Symbol

V hys

I lkg

Parameter

Low level input voltage

High level input voltage

Schmitt trigger hysteresis

Input leakage current

(2)

Table 50. I/O static characteristics

Conditions

TC and TTa I/O

FT and FTf I/O

All I/Os

TC and TTa I/O

FT and FTf I/O

All I/Os

TC and TTa I/O

FT and FTf I/O

TC, FT and FTf I/O

TTa in digital mode

≤ V

DDIOx

TTa in digital mode

DDIOx

≤ V

DDA

TTa in analog mode

≤ V

DDA

FT and FTf I/O

DDIOx

≤ V

≤ 5 V

Min Typ

0.445 V

DDIOx

+0.398

(1)

0.5 V

DDIOx

+0.2

(1)

0.7 V

DDIOx

200 (1)

100

(1)

Max

0.3 V

DDIOx

+0.07

(1)

0.475 V

DDIOx

–0.2

(1)

0.3 V

DDIOx

Unit

V mV

± 0.1

± 0.2

µA

Weak pull-up equivalent resistor

(3)

= V

25 40 55 k Ω

72/117

DocID025832 Rev 5

STM32F042x4 STM32F042x6 Electrical characteristics

Symbol Parameter

Table 50. I/O static characteristics (continued)

Conditions Min Typ Max Unit

Weak pull-down equivalent resistor

(3)

= - V

DDIOx

25 40 55 k Ω

I/O pin capacitance 5 -

1. Data based on design simulation only. Not tested in production.

2. The leakage could be higher than the maximum value, if negative current is injected on adjacent pins. Refer to Table 49:

I/O current injection susceptibility

3. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

PMOS/NMOS contribution to the series resistance is minimal (~10% order).

All I/Os are CMOS- and TTL-compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in

Figure 22

for standard I/Os, and in

Figure 23

for

5 V-tolerant I/Os. The following curves are design simulation results, not tested in production.

DocID025832 Rev 5

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Electrical characteristics STM32F042x4 STM32F042x6

Figure 22. TC and TTa I/O input characteristics

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74/117

DocID025832 Rev 5

STM32F042x4 STM32F042x6 Electrical characteristics

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or source up to +/- 20 mA (with a relaxed V

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in

Section 6.2

• The sum of the currents sourced by all the I/Os on V

DDIOx consumption of the MCU sourced on V

Σ I

VDD

, plus the maximum

, cannot exceed the absolute maximum rating

(see Table 18: Voltage characteristics ).

• The sum of the currents sunk by all the I/Os on V

, plus the maximum consumption of the MCU sunk on V

, cannot exceed the absolute maximum rating

Table 18: Voltage characteristics

Σ I

VSS

(see

Output voltage levels

Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in

Table 21: General operating conditions . All I/Os are CMOS- and TTL-compliant (FT, TTa or

TC unless otherwise specified).

Table 51. Output voltage characteristics

(1)

Symbol Parameter Conditions Min Max Unit

(3)

(4)

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

CMOS port

(2)

| = 8 mA

DDIOx

≥ 2.7 V

TTL port (2)

| = 8 mA

DDIOx

≥ 2.7 V

| = 20 mA

DDIOx

≥ 2.7 V

| = 6 mA

DDIOx

≥ 2 V

| = 4 mA

DDIOx

–0.4

2.4

DDIOx

–1.3

DDIOx

–0.4

DDIOx

–0.4

0.4

1.3

0.4

OLFm+

(3)

Output low level voltage for an FTf I/O pin in

Fm+ mode

| = 20 mA

DDIOx

≥ 2.7 V

| = 10 mA -

0.4

1. The I

current sourced or sunk by the device must always respect the absolute maximum rating specified in

Table 18:

Voltage characteristics , and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always

respect the absolute maximum ratings Σ I

IO.

2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

3. Data based on characterization results. Not tested in production.

4. Data based on characterization results. Not tested in production.

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Electrical characteristics STM32F042x4 STM32F042x6

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in

Figure 24 and

Table 52 , respectively. Unless otherwise specified, the parameters given are derived from

tests performed under the ambient temperature and supply voltage conditions summarized in

Table 21: General operating conditions .

Table 52. I/O AC characteristics

(1)(2)

OSPEEDRy

[1:0] value

(1)

Symbol x0

Parameter f max(IO)out t f(IO)out t r(IO)out f max(IO)out t f(IO)out t r(IO)out f max(IO)out t f(IO)out t r(IO)out f max(IO)out t f(IO)out t r(IO)out

Maximum frequency

(3)

Output fall time

Output rise time

Maximum frequency

(3)

Output fall time

Output rise time

Maximum frequency

(3)

Output fall time

Output rise time

Maximum frequency

(3)

Output fall time

Output rise time

Conditions

= 50 pF, V

DDIOx

≥ 2 V

DDIOx

< 2 V

DDIOx

≥ 2 V

DDIOx

< 2 V

11 f max(IO)out

Maximum frequency

(3) t f(IO)out

Output fall time t r(IO)out

Output rise time

= 30 pF, V

DDIOx

≥ 2.7 V

= 50 pF, V

DDIOx

≥ 2.7 V

= 50 pF, 2 V ≤ V

DDIOx

< 2.7 V

= 50 pF, V

DDIOx

< 2 V

= 30 pF, V

DDIOx

≥ 2.7 V

= 50 pF, V

DDIOx

≥ 2.7 V

= 50 pF, 2 V ≤ V

DDIOx

< 2.7 V

= 50 pF, V

DDIOx

< 2 V

= 30 pF, V

DDIOx

≥ 2.7 V

= 50 pF, V

DDIOx

≥ 2.7 V

= 50 pF, 2 V ≤ V

DDIOx

< 2.7 V

= 50 pF, V

DDIOx

< 2 V

Min Max Unit

MHz ns

62.5

125

76/117

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STM32F042x4 STM32F042x6 Electrical characteristics

Table 52. I/O AC characteristics

(1)(2)

(continued)

OSPEEDRy

[1:0] value

(1)

Symbol Parameter Conditions Min Max Unit

Fm+ configuration

(4)

f max(IO)out t f(IO)out t r(IO)out f max(IO)out t f(IO)out t r(IO)out t

EXTIpw

Maximum frequency (3)

Output fall time

Output rise time

Maximum frequency

(3)

Output fall time

Output rise time

Pulse width of external signals detected by the

EXTI controller

= 50 pF, V

DDIOx

≥ 2 V

DDIOx

< 2 V

0.5

MHz

1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the STM32F0xxxx RM0091 reference manual for a description of GPIO Port configuration register.

2. Guaranteed by design, not tested in production.

3. The maximum frequency is defined in

Figure 24

4. When Fm+ configuration is set, the I/O speed control is bypassed. Refer to the STM32F0xxxx reference manual RM0091 for a detailed description of Fm+ I/O configuration.

MHz ns ns

Figure 24. I/O AC characteristics definition

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The NRST pin input driver uses the CMOS technology. It is connected to a permanent pullup resistor, R

Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in

Table 21: General operating conditions .

Symbol

IL(NRST)

IH(NRST)

Table 53. NRST pin characteristics

Parameter

NRST input low level voltage

NRST input high level voltage

Conditions

Min

0.445 V

+0.398

(1)

Typ

Max

0.3 V

+0.07

(1)

Unit

DocID025832 Rev 5

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Electrical characteristics STM32F042x4 STM32F042x6

Symbol

Table 53. NRST pin characteristics (continued)

Parameter Conditions Min Typ Max Unit

V hys(NRST)

NRST Schmitt trigger voltage hysteresis

200 -

Weak pull-up equivalent resistor

(2)

= V

25 40 55

F(NRST)

NF(NRST)

NRST input filtered pulse

NRST input not filtered pulse

2.7 < V

< 3.6

2.0 < V

< 3.6

300

500

(3)

100

(1)

1. Data based on design simulation only. Not tested in production.

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimal (~10% order).

3. Data based on design simulation only. Not tested in production.

mV k Ω ns ns

Figure 25. Recommended NRST pin protection

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1. The external capacitor protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the V

IL(NRST)

max level specified in

Table 53: NRST pin characteristics

. Otherwise the reset will not be taken into account by the device.

Note:

Unless otherwise specified, the parameters given in Table 54

are derived from tests

performed under the conditions summarized in Table 21: General operating conditions

It is recommended to perform a calibration after each power-up.

Symbol

DDA

DDA (ADC) f

ADC f

(2)

Table 54. ADC characteristics

Parameter

Analog supply voltage for

ADC ON

Current consumption of the ADC (1)

ADC clock frequency

Sampling rate

Conditions

DDA

= 3.3 V

12-bit resolution

Min

2.4

0.6

0.043

Typ

0.9

Max

3.6

Unit

V mA

MHz

78/117

DocID025832 Rev 5

STM32F042x4 STM32F042x6 Electrical characteristics

Symbol

Table 54. ADC characteristics (continued)

Parameter Conditions Min Typ Max Unit f

TRIG

(2) External trigger frequency f

ADC

= 14 MHz,

12-bit resolution

823 kHz

AIN

(2)

Conversion voltage range

External input impedance

See

Equation 1

and

Table 55 for details

DDA

1/f

ADC k

Ω

ADC

(2)

ADC

(2)

Sampling switch resistance

Internal sample and hold capacitor

8 k Ω pF t

CAL

(2)(3) Calibration time f

ADC

= 14 MHz

5.9

µs

1/f

ADC

LATENCY

(2)(4)

Jitter t t t t latr

(2)

ADC

(2)

STAB

(2)

CONV

(2)

ADC_DR register ready latency

ADC clock = HSI14

ADC clock = PCLK/2

ADC clock = PCLK/4

1.5 ADC cycles + 2 f

PCLK

cycles

4.5

8.5

1.5 ADC cycles + 3 f

PCLK

cycles

Trigger conversion latency f

ADC

= f

PCLK

/2 = 14 MHz f

ADC

= f

PCLK f

ADC

= f

PCLK

/4 = 12 MHz f

ADC

= f

PCLK

/4 f

ADC

= f

HSI14

= 14 MHz

ADC jitter on trigger conversion f

ADC

= f

HSI14

Sampling time f

ADC

= 14 MHz

Stabilization time

Total conversion time

(including sampling time)

ADC

= 14 MHz,

12-bit resolution

0.179

0.107

1.5

0.196

0.219

10.5

0.250

17.1

239.5

14 to 252 (t

for sampling +12.5 for successive approximation)

PCLK cycle f

PCLK cycle

µs

1/f

PCLK

µs

1/f

HSI14

µs

1/f

ADC

1/f

ADC

1/f

µs

ADC

1. During conversion of the sampled value (12.5 x ADC clock period), an additional consumption of 100 µA on I on I

should be taken into account.

DDA

and 60 µA

2. Guaranteed by design, not tested in production.

3. Specified value includes only ADC timing. It does not include the latency of the register access.

4. This parameter specify latency for transfer of the conversion result to the ADC_DR register. EOC flag is set at this time.

DocID025832 Rev 5

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Electrical characteristics STM32F042x4 STM32F042x6

Equation 1: R

AIN

max formula

AIN

< f

----------------------------------------------------------------

ADC

× C

ADC

× ln ( 2 )

– R

ADC

The formula above ( Equation 1 ) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).

T s

(cycles)

1.5

7.5

13.5

28.5

41.5

55.5

71.5

239.5

1. Guaranteed by design, not tested in production.

Table 55. R

AIN

max for f

ADC

= 14 MHz t

(µs)

0.11

0.54

0.96

2.04

2.96

3.96

5.11

17.1

AIN

max (k Ω )

(1)

0.4

5.9

11.4

25.2

37.2

Table 56. ADC accuracy

(1)(2)(3)

Test conditions Symbol Parameter

Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error

Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error

Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error f f f f

T f

PCLK f

ADC

= 48 MHz,

= 14 MHz, R

AIN

< 10 k Ω

DDA

= 2.7 V to 3.6 V

= - 40 to 105 °C

PCLK

ADC

= 14 MHz, R

DDA

PCLK

ADC

DDA

= 48 MHz,

= 14 MHz, R

AIN

< 10 k Ω

= 2.4 V to 3.6 V

= 25 °C

AIN

< 10 k Ω

= 3 V to 3.6 V

= 25 °C

1. ADC DC accuracy values are measured after internal calibration.

80/117

DocID025832 Rev 5

Typ

±0.7

±1.2

±3.3

±1.9

±2.8

±0.7

±1.2

±0.8

±3.3

±1.9

±2.8

±1.3

±1

±0.5

±0.7

Max

(4)

±1.3

±1.7

±4

±2.8

±3

±1.3

±1.7

±1.5

±4

±2.8

±3

±2

±1.5

±1

Unit

LSB

STM32F042x4 STM32F042x6 Electrical characteristics

2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current.

Any positive injection current within the limits specified for I accuracy.

INJ(PIN)

and Σ I

INJ(PIN)

Section 6.3.14

does not affect the ADC

3. Better performance may be achieved in restricted V

DDA

, frequency and temperature ranges.

4. Data based on characterization results, not tested in production.

Figure 26. ADC accuracy characteristics

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Figure 27. Typical connection diagram using the ADC

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1. Refer to Table 54: ADC characteristics for the values of R

AIN

, R

ADC

and C

ADC

2. C parasitic

represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 this, f

ADC pF). A high C

should be reduced.

parasitic

value will downgrade conversion accuracy. To remedy

General PCB design guidelines

Power supply decoupling should be performed as shown in

Figure 13: Power supply scheme

. The 10 nF capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip.

DocID025832 Rev 5

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Electrical characteristics STM32F042x4 STM32F042x6

6.3.17 Temperature sensor characteristics

Table 57. TS characteristics t

Symbol

(1)

Avg_Slope

30 t

START

(1)

S_temp

(1)

Parameter

SENSE

linearity with temperature

Average slope

Voltage at 30 °C (± 5 °C)

(2)

ADC_IN16 buffer startup time

ADC sampling time when reading the temperature

Min

4.0

1.34

Typ

± 1

4.3

1.43

Max

± 2

4.6

1.52

1. Guaranteed by design, not tested in production.

2. Measured at V

DDA

= 3.3 V ± 10 mV. The V

Temperature sensor calibration values

ADC conversion result is stored in the TS_CAL1 byte. Refer to Table 3:

Unit

°C mV/°C

µs

6.3.18 V

BAT monitoring characteristics

Symbol

Table 58. V

BAT

monitoring characteristics

Parameter

R Resistor bridge for V

BAT

(1) t

S_vbat

(1)

Ratio on V

BAT

measurement

Error on Q

ADC sampling time when reading the V

BAT

1. Guaranteed by design, not tested in production.

Min

–1

Typ

2 x 50

Max

Unit k Ω

µs

82/117

The parameters given in the following tables are guaranteed by design.

Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate

function characteristics (output compare, input capture, external clock, PWM output).

Symbol t res(TIM) f

EXT

Parameter

Table 59. TIMx characteristics

Conditions Min

Timer resolution time

Timer external clock frequency on CH1 to

CH4 t

MAX_COUNT

16-bit timer maximum period

32-bit counter maximum period

TIMxCLK

= 48 MHz

TIMxCLK

= 48 MHz

TIMxCLK

= 48 MHz

TIMxCLK

= 48 MHz

Typ

20.8

TIMxCLK

1365

89.48

Max

Unit t

TIMxCLK ns

MHz

MHz t

TIMxCLK

µs t

TIMxCLK s

DocID025832 Rev 5

STM32F042x4 STM32F042x6 Electrical characteristics

Table 60. IWDG min/max timeout period at 40 kHz (LSI)

(1)

Prescaler divider PR[2:0] bits

Min timeout RL[11:0]=

0x000

Max timeout RL[11:0]=

0xFFF

Unit

/16

/32

/64

/128

/256

6 or 7

0.1

0.2

0.4

0.8

1.6

3.2

6.4

409.6

819.2

1638.4

3276.8

6553.6

13107.2

26214.4

1. These timings are given for a 40 kHz clock but the microcontroller internal RC frequency can vary from 30 to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.

Prescaler

Table 61. WWDG min/max timeout value at 48 MHz (PCLK)

WDGTB Min timeout value Max timeout value

0.0853

0.1706

0.3413

0.6826

5.4613

10.9226

21.8453

43.6906

Unit ms

I

C interface characteristics

The I

C interface meets the timings requirements of the I

C-bus specification and user manual rev. 03 for:

• Standard-mode (Sm): with a bit rate up to 100 kbit/s

• Fast-mode (Fm): with a bit rate up to 400 kbit/s

• Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.

The I 2 C timings requirements are guaranteed by design when the I2Cx peripheral is properly configured (refer to Reference manual).

The SDA and SCL I/O requirements are met with the following restrictions: the SDA and

SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and V

DDIOx

is disabled, but is still present. Only FTf I/O pins support Fm+ low level output current maximum requirement. Refer to

Section 6.3.14: I/O port characteristics for the I

2 C I/Os characteristics.

All I 2 C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog filter characteristics:

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Electrical characteristics STM32F042x4 STM32F042x6

Table 62. I

C analog filter characteristics

(1)

Parameter Min Max Symbol t

Maximum width of spikes that are suppressed by the analog filter

1. Guaranteed by design, not tested in production.

2. Spikes with widths below t

AF(min) are filtered.

3. Spikes with widths above t

AF(max)

are not filtered

(2)

260

(3)

Unit ns

SPI/I

S characteristics

Unless otherwise specified, the parameters given in Table 63

for SPI or in

Table 64 for I

S are derived from tests performed under the ambient temperature, f

PCLKx

frequency and

supply voltage conditions summarized in Table 21: General operating conditions

Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate

function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I

S).

Table 63. SPI characteristics

(1)

Conditions Symbol Parameter Min Max Unit

1/t t t f

SCK c(SCK) t r(SCK) t f(SCK) t su(NSS) t h(NSS) t w(SCKH) t w(SCKL) t su(MI) su(SI) h(MI) t h(SI) t a(SO)

(2) t dis(SO)

(3) t t v(SO) t v(MO) t h(SO) h(MO)

DuCy(SCK)

SPI clock frequency

Master mode

Slave mode

SPI clock rise and fall time

NSS setup time

NSS hold time

SCK high and low time

Capacitive load: C = 15 pF

Slave mode

Master mode, f

PCLK presc = 4

= 36 MHz,

Master mode

Data input setup time

Data input hold time

Slave mode

Master mode

Slave mode

Data output access time Slave mode, f

PCLK

= 20 MHz

Data output disable time Slave mode

Data output valid time Slave mode (after enable edge)

Data output valid time

Data output hold time

Master mode (after enable edge)

Slave mode (after enable edge)

Master mode (after enable edge)

SPI slave input clock duty cycle

Slave mode

4Tpclk

2Tpclk + 10

Tpclk/2 -2

11.5

3Tpclk

22.5

Tpclk/2 + 1

MHz ns ns

1. Data based on characterization results, not tested in production.

2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.

3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z

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STM32F042x4 STM32F042x6 Electrical characteristics

Figure 28. SPI timing diagram - slave mode and CPHA = 0

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&32/

D62

0,62RXWSXW

VX166

Z6&./

)LUVWELW287

K6,

Y62

VX6,

026,LQSXW )LUVWELW,1

K62

1H[WELWV287

1H[WELWV,1

U6&.

K166

I6&.

/DVWELW287

GLV62

/DVWELW,1

06Y9

Figure 29. SPI timing diagram - slave mode and CPHA = 1

166LQSXW

VX166

Z6&.+

F6&.

I6&.

K166

&3+$

&32/

&3+$

&32/

0,62RXWSXW

026,LQSXW

D62

Z6&./

Y62

)LUVWELW287

VX6,

K6,

)LUVWELW,1

K62

1H[WELWV287

1H[WELWV,1

U6&.

GLV62

/DVWELW287

/DVWELW,1

06Y9

1. Measurement points are done at CMOS levels: 0.3 V

and 0.7 V

DocID025832 Rev 5

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Electrical characteristics STM32F042x4 STM32F042x6

Figure 30. SPI timing diagram - master mode

166LQSXW

+LJK

WF6&.

&3+$

&32/

&3+$

&32/

&3+$

&32/

&3+$

&32/

0,62

,13 87

026,

287387

WVX0,

WZ6&.+

WZ6&./

06%,1

WK0,

06%287

WY02

%,7,1

% , 7287

WK02

1. Measurement points are done at CMOS levels: 0.3 V

and 0.7 V

Symbol f

1/t c(CK) t r(CK) t f(CK) t w(CKH) t w(CKL) t v(WS) t h(WS) t su(WS) t h(WS)

DuCy(SCK)

Table 64. I

S characteristics

(1)

Conditions Parameter

S clock frequency

Master mode (data: 16 bits, Audio frequency = 48 kHz)

Slave mode

S clock rise time

S clock fall time

S clock high time

I 2 S clock low time

WS valid time

WS hold time

WS setup time

WS hold time

S slave input clock duty cycle

Capacitive load C

= 15 pF

Master f

PCLK

= 16 MHz, audio frequency = 48 kHz

Master mode

Slave mode

WU6&.

WI6&.

/6%,1

/6%287

DLF

Min

1.597

306

312

Max

1.601

6.5

Unit

MHz ns

86/117

DocID025832 Rev 5

STM32F042x4 STM32F042x6 Electrical characteristics

Table 64. I

S characteristics

(1)

(continued)

Parameter Conditions Symbol t su(SD_MR) t su(SD_SR) t h(SD_MR)

(2) t h(SD_SR)

(2) t v(SD_MT)

(2) t v(SD_ST)

(2) t h(SD_MT) t h(SD_ST)

Data input setup time

Data input hold time

Data output valid time

Data output hold time

Master receiver

Slave receiver

Master receiver

Slave receiver

Master transmitter

Slave transmitter

Master transmitter

Slave transmitter

1. Data based on design simulation and/or characterization results, not tested in production.

2. Depends on f

PCLK

. For example, if f

PCLK

= 8 MHz, then T

PCLK

= 1/f

PLCLK

= 125 ns.

Figure 31. I

S slave timing diagram (Philips protocol)

WF&.

Min

0.5

Max

&32/

Unit ns

&32/

WZ&.+ WZ&./ WK:6

:6LQSXW

6'WUDQVPLW

WVX:6

/6%WUDQVPLW

WVX6'B65

/6%UHFHLYH

06%WUDQVPLW

06%UHFHLYH

WY6'B67

%LWQWUDQVPLW

WK6'B65

%LWQUHFHLYH

WK6'B67

/6%UHFHLYH 6'UHFHLYH

06Y9

1. Measurement points are done at CMOS levels: 0.3 × V

DDIOx and 0.7 × V

DDIOx

2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

DocID025832 Rev 5

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Electrical characteristics STM32F042x4 STM32F042x6

Figure 32. I

S master timing diagram (Philips protocol)

WI&.

WU&.

WF&.

&32/

WY:6

:6RXWSXW

6'WUDQVPLW

WZ&.+

6'UHFHLYH

WZ&./ WK:6

WY6'B07

/6%WUDQVPLW

WVX6'B05

/6%UHFHLYH

06%WUDQVPLW

06%UHFHLYH

%LWQWUDQVPLW

WK6'B05

%LWQUHFHLYH

WK6'B07

/6%WUDQVPLW

/6%UHFHLYH

06Y9

1. Data based on characterization results, not tested in production.

2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

88/117

DocID025832 Rev 5

STM32F042x4 STM32F042x6 Electrical characteristics

USB characteristics

The STM32F042x4/x6 USB interface is fully compliant with the USB specification version

2.0 and is USB-IF certified (for Full-speed device operation).

Symbol

Table 65. USB electrical characteristics

Parameter Conditions Min.

Typ Max.

Unit t

DDIO2

STARTUP

(2)

PUI

PUR

USB transceiver operating voltage

USB transceiver startup time

Embedded USB_DP pull-up value during idle

Embedded USB_DP pull-up value during reception

3.0

(1)

1.1

2.0

1.26

2.26

3.6

1.0

1.5

2.6

µs k

Ω

DRV

(2)

Output driver impedance

(3)

Driving high and low

28 40 44

1. The STM32F042x4/x6 USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics which are degraded in the 2.7-to-3.0 V voltage range.

2. Guaranteed by design, not tested in production.

3. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-); the matching impedance is already included in the embedded driver.

Ω

CAN (controller area network) interface

Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate

function characteristics (CAN_TX and CAN_RX).

DocID025832 Rev 5

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Package information STM32F042x4 STM32F042x6

7.1

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com

ECOPACK ® is an ST trademark.

LQFP48 package information

LQFP48 is a 48-pin, 7 x 7 mm low-profile quad flat package.

Figure 33. LQFP48 package outline

6($7,1*

3/$1(

FFF &

*$8*(3/$1(

3,1

,'(17,),&$7,21

1. Drawing is not to scale.

%B0(B9

90/117

DocID025832 Rev 5

STM32F042x4 STM32F042x6 Package information

Table 66. LQFP48 package mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min e

E3 k ccc b c

0.050

1.350

0.170

0.090

8.800

6.800

8.800

6.800

0.450

0°

1.400

0.220

9.000

7.000

5.500

9.000

7.000

5.500

0.500

0.600

1.000

3.5°

1.600

0.150

1.450

0.270

0.200

9.200

7.200

9.200

7.200

0.750

7°

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.3465

0.2677

0.0177

0°

0.0020

0.0531

0.0067

0.0035

0.3465

0.2677

Typ

0.2165

0.3543

0.2756

0.2165

0.0197

0.0236

0.0394

3.5°

0.0551

0.0087

0.3543

0.2756

Figure 34. Recommended footprint for LQFP48 package

Max

0.3622

0.2835

0.0295

7°

0.0031

0.0630

0.0059

0.0571

0.0106

0.0079

0.3622

0.2835

1. Dimensions are expressed in millimeters.

DocID025832 Rev 5

DLG

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113

Package information STM32F042x4 STM32F042x6

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 35. LQFP48 package marking example

3URGXFWLGHQWLILFDWLRQ

670)

< ::

'DWHFRGH

5HYLVLRQFRGH

06Y9

1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering

Samples to run qualification activity.

92/117

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STM32F042x4 STM32F042x6

7.2

Package information

UFQFPN48 package information

UFQFPN48 is a 48-lead, 7x7 mm, 0.5 mm pitch, ultra-thin fine-pitch quad flat package.

Figure 36. UFQFPN48 package outline

3LQLGHQWLILHU

ODVHUPDUNLQJDUHD

( (

H E

'HWDLO<

GGG

6HDWLQJ

SODQH

([SRVHGSDG

DUHD

SLQFRUQHU

'HWDLO=

5W\S

(

$%B0(B9

1. Drawing is not to scale.

2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.

3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this back-side pad to PCB ground.

DocID025832 Rev 5

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113

Package information STM32F042x4 STM32F042x6

Table 67. UFQFPN48 package mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min

T b e ddd

0.500

0.000

6.900

5.500

0.300

0.200

0.550

0.020

7.000

5.600

0.400

0.152

0.250

0.500

0.600

0.050

7.100

5.700

0.500

0.300

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.0197

0.0000

0.2717

0.2165

0.0118

0.0079

Typ

0.0217

0.0008

0.2756

0.2205

0.0157

0.0060

0.0098

0.0197

Figure 37. Recommended footprint for UFQFPN48 package

Max

0.0236

0.0020

0.2795

0.2244

0.0197

0.0118

0.0031

94/117

1. Dimensions are expressed in millimeters.

DocID025832 Rev 5

$%B)3B9

STM32F042x4 STM32F042x6 Package information

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 38. UFQFPN48 package marking example

3URGXFWLGHQWLILFDWLRQ

670)

< ::

'DWHFRGH

5HYLVLRQFRGH

06Y9

Samples to run qualification activity.

DocID025832 Rev 5

95/117

113

Package information STM32F042x4 STM32F042x6

96/117

WLCSP36 is a 36-ball, 2.605 x 2.703 mm, 0.4 mm pitch wafer-level chip-scale package.

Figure 39. WLCSP36 package outline

)

$EDOOORFDWLRQ

EEE =

'HWDLO$

)

%XPSVLGH

6LGHYLHZ

;

RULHQWDWLRQ

UHIHUHQFH

%XPS

HHH = $

:DIHUEDFNVLGH

DDD =

EEDOOV

FFF

GGG

= ; <

6HDWLQJSODQH

'HWDLO$

URWDWHG

(2) b

(3)

E e e1 e2

1. Drawing is not to scale.

Table 68. WLCSP36 package mechanical data millimeters inches

(1)

Symbol

Min

0.525

0.220

2.570

2.668

Typ

0.555

0.175

0.380

0.025

0.250

2.605

2.703

0.400

2.000

Max

0.585

0.280

2.640

2.738

Min

0.0207

0.0087

0.1012

0.1050

Typ

0.0219

0.0069

0.0150

0.0010

0.0098

0.1026

0.1064

0.0157

0.0787

Ϭ>ͺDͺsϮ

Max

0.0230

0.0110

0.1039

0.1078

DocID025832 Rev 5

STM32F042x4 STM32F042x6 Package information

Table 68. WLCSP36 package mechanical data (continued) millimeters inches

(1)

Symbol

Min Typ Max Min Typ

G aaa bbb ccc ddd eee -

0.3025

0.3515

0.100

0.050

1. Values in inches are converted from mm and rounded to 4 decimal digits.

2. Back side coating.

3. Dimension is measured at the maximum bump diameter parallel to primary datum Z.

0.0119

0.0138

Figure 40. Recommended pad footprint for WLCSP36 package

Max

0.0039

0.0020

'SDG

'VP

Pitch

Dpad

Table 69. WLCSP36 recommended PCB design rules

Dimension Recommended values

Dsm

PCB pad design

0.4 mm

260 µm max. (circular)

220 µm recommended

300 µm min. (for 260 µm diameter pad)

Non-solder mask defined via underbump allowed

069

DocID025832 Rev 5

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113

Package information STM32F042x4 STM32F042x6

Device marking

The following figure gives an example of topside marking orientation versus ball A1 identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 41. WLCSP36 package marking example

'RW

3URGXFWLGHQWLILFDWLRQ )7

< ::

5HYLVLRQFRGH

'DWHFRGH

06Y9

Samples to run qualification activity.

98/117

DocID025832 Rev 5

STM32F042x4 STM32F042x6

7.4 LQFP32 package information

LQFP32 is a 32-pin, 7 x 7 mm low-profile quad flat package.

Figure 42. LQFP32 package outline

6($7,1*

3/$1(

Package information

FFF &

*$8*(3/$1(

3,1

,'(17,),&$7,21

1. Drawing is not to scale.

7@.&@7

DocID025832 Rev 5

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113

Package information STM32F042x4 STM32F042x6

Table 70. LQFP32 package mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min e

E3 k ccc b c

0.050

1.350

0.300

0.090

8.800

6.800

8.800

6.800

0.450

0°

1.400

0.370

9.000

7.000

5.600

9.000

7.000

5.600

0.800

0.600

1.000

3.5°

1.600

0.150

1.450

0.450

0.200

9.200

7.200

9.200

7.200

0.750

7°

0.100

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.3465

0.2677

0.0177

0°

0.0020

0.0531

0.0118

0.0035

0.3465

0.2677

Typ

0.2205

0.3543

0.2756

0.2205

0.0315

0.0236

0.0394

3.5°

0.0551

0.0146

0.3543

0.2756

Figure 43. Recommended footprint for LQFP32 package

Max

0.3622

0.2835

0.0295

7°

0.0039

0.0630

0.0059

0.0571

0.0177

0.0079

0.3622

0.2835

100/117

1. Dimensions are expressed in millimeters.

DocID025832 Rev 5

9B)3B9

STM32F042x4 STM32F042x6 Package information

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 44. LQFP32 package marking example

3URGXFWLGHQWLILFDWLRQ

670)

3LQLGHQWLILFDWLRQ

< ::

'DWHFRGH

5HYLVLRQFRGH

7.5

06Y9

Samples to run qualification activity.

UFQFPN32 package information

UFQFPN32 is a 32-pin, 5x5 mm, 0.5 mm pitch ultra-thin fine-pitch quad flat package.

DocID025832 Rev 5

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113

Package information

(

STM32F042x4 STM32F042x6

Figure 45. UFQFPN32 package outline

GGG &

6($7,1*

3/$1(

( (

' /

3,1,GHQWLILHU

$%B0(B9

1. Drawing is not to scale.

2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.

3. There is an exposed die pad on the underside of the UFQFPN package. This pad is used for the device ground and must be connected. It is referred to as pin 0 in

Table: Pin definitions

102/117

DocID025832 Rev 5

STM32F042x4 STM32F042x6 Package information

Table 71. UFQFPN32 package mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min

E2 e

L ddd b

0.500

0.000

0.180

4.900

3.400

4.900

3.400

0.300

0.550

0.020

0.152

0.230

5.000

3.500

5.000

3.500

0.500

0.400

0.600

0.050

0.280

5.100

3.600

5.100

3.600

0.500

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.0197

0.0000

0.0071

0.1929

0.1339

0.1929

0.1339

0.0118

Typ

0.0217

0.0008

0.0060

0.0091

0.1969

0.1378

0.1969

0.1378

0.0197

0.0157

Figure 46. Recommended footprint for UFQFPN32 package

Max

0.2008

0.1417

0.0197

0.0031

0.0236

0.0020

0.0110

0.2008

0.1417

1. Dimensions are expressed in millimeters.

DocID025832 Rev 5

$%B)3B9

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113

Package information STM32F042x4 STM32F042x6

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 47. UFQFPN32 package marking example

3URGXFWLGHQWLILFDWLRQ

< ::

'DWHFRGH

5HYLVLRQFRGH

'RWSLQ

06Y9

Samples to run qualification activity.

104/117

DocID025832 Rev 5

STM32F042x4 STM32F042x6

7.6

Package information

UFQFPN28 package information

UFQFPN28 is a 28-lead, 4x4 mm, 0.5 mm pitch, ultra-thin fine-pitch quad flat package.

Figure 48. UFQFPN28 package outline

'HWDLO<

(

'HWDLO=

T b e

1. Drawing is not to scale.

Symbol

Table 72. UFQFPN28 package mechanical data

(1) millimeters inches

Min

0.500

3.900

2.900

3.900

2.900

0.300

0.250

0.200

Typ

0.550

0.000

4.000

3.000

4.000

3.000

0.400

0.350

0.152

0.250

0.500

Max

0.600

0.050

4.100

3.100

4.100

3.100

0.500

0.450

0.300

Min

0.0197

0.1535

0.1142

0.1535

0.1142

0.0118

0.0098

0.0079

Typ

0.0217

0.0000

0.1575

0.1181

0.1575

0.1181

0.0157

0.0138

0.0060

0.0098

0.0197

$%B0(B9

Max

0.0236

0.0020

0.1614

0.1220

0.1614

0.1220

0.0197

0.0177

0.0118

DocID025832 Rev 5

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113

Package information STM32F042x4 STM32F042x6

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 49. Recommended footprint for UFQFPN28 package

1. Dimensions are expressed in millimeters.

$%B)3B9

106/117

DocID025832 Rev 5

STM32F042x4 STM32F042x6 Package information

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 50. UFQFPN28 package marking example

3URGXFWLGHQWLILFDWLRQ )*

'DWHFRGH

< :: 5 5HYLVLRQFRGH

'RW

06Y9

Samples to run qualification activity.

DocID025832 Rev 5

107/117

113

Package information STM32F042x4 STM32F042x6

7.7 TSSOP20 package information

TSSOP20 is a 20-lead thin shrink small-outline, 6.5 x 4.4 mm, 0.65 mm pitch, package.

Figure 51.TSSOP20 package outline

ϮϬ ϭ ϭϭ ϭϬ ϭ

^d/E'

W>E

Ϭ͘Ϯϱŵŵ

'h'W>E

W/Eϭ

/Ed/&/d/KE

ĂĂĂ ď Ğ

Ϯ ϭ

>ϭ

108/117

zͺDͺsϯ c

(2)

(3) e

A2 b

1. Drawing is not to scale.

Table 73. TSSOP20 package mechanical data millimeters inches

(1)

Symbol

Min.

0.050

0.800

0.190

0.090

6.400

6.200

4.300

0.450

Typ.

1.000

6.500

6.400

4.400

0.650

0.600

Max.

1.200

0.150

1.050

0.300

0.200

6.600

4.500

0.750

Min.

0.0020

0.0315

0.0075

0.0035

0.2520

0.2441

0.1693

0.0177

Typ.

0.0394

0.2559

0.2520

0.1732

0.0256

0.0236

Max.

0.0472

0.0059

0.0413

0.0118

0.0079

0.2598

0.1772

0.0295

DocID025832 Rev 5

STM32F042x4 STM32F042x6 Package information

Table 73. TSSOP20 package mechanical data (continued) millimeters inches

(1)

Symbol

Min.

Typ.

Max.

Min.

Typ.

Max.

L1 k aaa

0°

1.000

8°

0.100

0°

0.0394

8°

0.0039

1. Values in inches are converted from mm and rounded to four decimal digits.

2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side.

3. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side.

Figure 52. Recommended footprint for TSSOP20 package

1. Dimensions are expressed in millimeters.

DocID025832 Rev 5

<$B)3B9

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113

Package information STM32F042x4 STM32F042x6

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 53. TSSOP20 package marking example

3URGXFWLGHQWLILFDWLRQ

3LQLGHQWLILHU

))3

'DWHFRGH

< :: 5 5HYLVLRQFRGH

06Y9

Samples to run qualification activity.

110/117

DocID025832 Rev 5

STM32F042x4 STM32F042x6 Package information

The maximum chip junction temperature (T

Table 21: General operating conditions .

max) must never exceed the values given in

The maximum chip-junction temperature, T

J using the following equation:

max, in degrees Celsius, may be calculated

max = T

max + (P

max x Θ

)

Where:

• T

max is the maximum ambient temperature in °C,

• Θ

is the package junction-to-ambient thermal resistance, in °C/W,

• P

max is the sum of P

INT

max and P

I/O max (P

max = P

INT

max + P

I/O max),

• P

INT

max is the product of I internal power.

DD and V

, expressed in Watts. This is the maximum chip

I/O

max represents the maximum power dissipation on output pins where:

I/O

max = Σ (V

× I

) + Σ ((V

DDIOx

– V

) × I

), taking into account the actual V

OL application.

/ I

and V

/ I

OH of the I/Os at low and high level in the

Table 74. Package thermal characteristics

Symbol

Parameter

Thermal resistance junction-ambient

LQFP48 - 7 mm x 7 mm

Thermal resistance junction-ambient

UFQFPN48 - 7 mm x 7 mm

Thermal resistance junction-ambient

WLCSP36 2.6 mm x 2.7 mm

Thermal resistance junction-ambient

LQFP32 - 7 mm x 7 mm

Thermal resistance junction-ambient

UFQFPN32 - 5 mm x 5 mm

Thermal resistance junction-ambient

UFQFPN28 - 4 mm x 4 mm

Thermal resistance junction-ambient

TSSOP20 - 6.5 mm x 6.4 mm

Value

118

Unit

°C/W

7.8.2

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural

Convection (Still Air). Available from www.jedec.org

Selecting the product temperature range

When ordering the microcontroller, the temperature range is specified in the ordering

information scheme shown in Section 8: Ordering information .

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Package information STM32F042x4 STM32F042x6

Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature.

As applications do not commonly use the STM32F042x4/x6 at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application.

The following examples show how to calculate the temperature range needed for a given application.

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8 Ordering information

Ordering information

For a list of available options (memory, package, and so on) or for further information on any aspect of this device, please contact your nearest ST sales office.

Example

Table 75. Ordering information scheme

STM32 F 042 C 6 T 6 xxx

Device family

STM32 = ARM-based 32-bit microcontroller

Product type

F = General-purpose

Sub-family

042 = STM32F042xx

Pin count

F = 20 pins

G = 28 pins

K = 32 pins

T = 36 pins

C = 48 pins

User code memory size

4 = 16 Kbyte

6 = 32 Kbyte

Package

P = TSSOP

T = LQFP

U = UFQFPN

Y = WLCSP

Temperature range

6 = –40 to 85 °C

7 = –40 to 105 °C

Options xxx = code ID of programmed parts (includes packing type)

TR = tape and reel packing blank = tray packing

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Revision history STM32F042x4 STM32F042x6

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Date

25-Feb-2014

03-Apr-2014

26-Oct-2015

Revision

Table 76. Document revision history

Changes

Initial release.

Added the sample engineering sections for all the packages in the chapter Package information:

Updated tables:

– STM32F042x4/x6 USART implementation: added one table footnote.

– STM32F042x pin definitions,

– Current characteristics,

– Typical and maximum current consumption from VDD supply at VDD

= 3.6 V,

– Typical and maximum current consumption from the VDDA supply,

– Typical and maximum consumption in Stop and Standby modes,

– Typical and maximum current consumption from the VBAT supply,

– Typical current consumption, code executing from Flash, running from HSE 8 MHz crystal,

– Flash memory characteristics,

– I/O static characteristics,

– I/O current injection susceptibility,

– EMS characteristics,

– EMI characteristics,

Updated figures:

– UFQFPN32 32-pin package pinout,

– UQFPN28 28-pin package,

– Power supply scheme,

– TC and TTa I/O input characteristics,

– Five volt tolerant (FT and FTf) I/O input characteristics.

– LQFP48 marking example (package top view),

– UFQFPN48 marking example (package top view),

– WLCSP36 marking example (package top view),

– LQFP32 marking example (package top view),

– UFQFPN28 marking example (package top view),

– UFQFPN32 marking example (package top view),

– TSSOP20 marking example (package top view)

Cover page: number of I/Os and timers updated.

Updates in Section 2: Description :

– updated

Figure 1: Block diagram

Updates in Section 3: Functional overview:

– updated

Figure 2: Clock tree

– addition of the number of complementary outputs for the advanced control timer and for TIM16, TIM17 general purpose timers in

Table 7: Timer feature comparison

– removal of USART2 from

Figure 3.5.4: Low-power modes

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Date

26-Oct-2015

Table 76. Document revision history (continued)

Revision

Changes

– Table 9: STM32F042x4/x6 I

C implementation - adding 20 mA

Updates in Section 4: Pinouts and pin descriptions

– Table 12: Legend/abbreviations used in the pinout table - removing

“I” pin type

Updates in Section 5: Memory mapping :

–

Figure 10: STM32F042x6 memory map

, x4 difference described in text

Updates in Section 6: Electrical characteristics :

– the condition “Regulator in run mode, all oscillators OFF” in Table 28:

Typical and maximum consumption in Stop and Standby modes

– footnote for V

IN max value in Table 18: Voltage characteristics,

– footnote for max V

Table 21: General operating conditions

– t

START

parameter definition in Table 25: Embedded internal reference voltage

– addition of t

START

parameter in

Table 25: Embedded internal reference voltage, removal of -40°C to 85°C condition and the associated footnote

–

Table 26: Typical and maximum current consumption from VDD supply at VDD = 3.6 V: removing “code executing from Flash or

RAM”

– removal of the min value for t

START

parameter in Table 57: TS characteristics

– the typical value for R parameter in Table 58: VBAT monitoring characteristics

– removal of Res

parameter line from Table 59: TIMx characteristics and putting all values in new Typ column, substitution of t

COUNTER with t

MAX_COUNT,

values defined as powers of two

– V

ESD(CDM)

class in Table 47: ESD absolute maximum ratings

– reorganization of Table 64: I

S characteristics a nd filling max value of t v(SD_ST)

– adding definition of levels in Figure 32: I

S master timing diagram

(Philips protocol)

Updates in Section 7: Package information :

– heading and display of columns in

Table 68: WLCSP36 package mechanical data .,

– Figure 38: UFQFPN48 package marking example

– Figure 41: WLCSP36 package marking example

– Figure 50: UFQFPN28 package marking example

– Figure 41: WLCSP36 package marking example

– Figure 51: TSSOP20 package outline - correcting GAGE to GAUGE

– removing “die 445” from Table 74: Package thermal characteristics

Updates in Section 8: Part numbering :

– adding tray packing to options

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Date

16-Dec-2015

10-Jan-2017

Table 76. Document revision history (continued)

Revision Changes

Section 3: Functional overview

–

Figure 2: Clock tree

modified

Section 4: Pinouts and pin descriptions

– Package pinout figures updated (look and feel)

–

Figure 5: WLCSP36 package pinout -

now presented in top view

–

Table 13: STM32F042x pin definitions

- note 3 added; CIMP1_OUT

and USART4_CTS removed

–

Table 15: Alternate functions selected through GPIOB_AFR registers for port B - change of I2C2_SDA and I2C2_SCL to

I2C1_SDA and I2C1_SCL

Section 5: Memory mapping

–

Table 17: STM32F042x4/x6 peripheral register boundary addresses

- change of “SYSCFG + COMP” to “SYSCFG”

Section 6: Electrical characteristics

–

Table 50: I/O static characteristics

- removed note

–

Section 6.3.16: 12-bit ADC characteristics

- changed introductory

sentence

Section 7: Package information

–

Figure 49: Recommended footprint for UFQFPN28 package

distance between corner pads added

Section 6: Electrical characteristics

–

Table 37: LSE oscillator characteristics (fLSE = 32.768 kHz)

information on configuring different drive capabilities removed. See the corresponding reference manual.

–

Table 25: Embedded internal reference voltage

- V

REFINT

values

–

Figure 28: SPI timing diagram - slave mode and CPHA = 0

and

Figure 29: SPI timing diagram - slave mode and CPHA = 1

enhanced and corrected

Section 8: Ordering information

– The name of the section changed from the previous “Part numbering”

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IMPORTANT NOTICE – PLEASE READ CAREFULLY

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ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

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