STMicroelectronics STM32C011F4 Datasheet

STM32C011x4/x6

Arm

®

Cortex

®

-M0+ 32-bit MCU, 32 KB Flash, 6 KB RAM,

2 x USART, timers, ADC, comm. I/Fs, 2-3.6 V

Datasheet

-

production data

Features

• Core: Arm ® 32-bit Cortex ® -M0+ CPU, frequency up to 48 MHz

• -40°C to 85°C/105°C/125°C operating temperature

• Memories

– Up to 32 Kbytes of flash memory with protection

– 6 Kbytes of SRAM with HW parity check

• CRC calculation unit

• Reset and power management

– Voltage range: 2.0 V to 3.6 V

– Power-on/Power-down reset (POR/PDR)

– Programmable Brownout reset (BOR)

– Low-power modes:

Sleep, Stop, Standby, Shutdown

• Clock management

– 4 to 48 MHz crystal oscillator

– 32 kHz crystal oscillator with calibration

– Internal 48 MHz RC oscillator (±1 %)

– Internal 32 kHz RC oscillator (±5 %)

• Up to 18 fast I/Os

– All mappable on external interrupt vectors

– Multiple 5 V-tolerant I/Os

• 3-channel DMA controller with flexible mapping

• 12-bit, 0.4 µs ADC (up to 13 ext. channels)

– Conversion range: 0 to 3.6 V

• 8 timers: 16-bit for advanced motor control, four 16-bit general-purpose, two watchdogs,

SysTick timer

• Calendar RTC with alarm

SO8N

4.9 × 6 mm

WLCSP12

1.70 × 1.42 mm

TSSOP20

6.4 × 4.4 mm

UFQFPN20

3 × 3 mm

• Communication interfaces

– One I

2

C-bus interface supporting Fastmode Plus (1 Mbit/s) with extra current sink, supporting SMBus/PMBus and wakeup from Stop mode

– Two USARTs with master/slave synchronous SPI; one supporting ISO7816 interface, LIN, IrDA capability, auto baud rate detection and wakeup feature

– One SPI (24 Mbit/s) with 4- to 16-bit

I programmable bitframe, multiplexed with

2

S interface

• Development support: serial wire debug (SWD)

• All packages ECOPACK 2 compliant

Table 1. Device summary

Reference Part number

STM32C011x4

STM32C011x6

STM32C011F4, STM32C011J4

STM32C011F6, STM32C011J6,

STM32C011D6

December 2022

This is information on a product in full production.

DS13866 Rev 3 1/94 www.st.com

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Contents

Contents

2/94

STM32C011x4/x6

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.1

Arm

® Cortex ® -M0+ core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.2

Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.3

Embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.4

Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.5

Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.6

Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 13

3.7

Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.7.1

3.7.2

3.7.3

3.7.4

3.7.5

Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.8

Interconnect of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.9

Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.10

General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.11

Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.12

DMA request multiplexer (DMAMUX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.13

Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.13.1

Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 18

3.13.2

Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 19

3.14

Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.14.1

Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.14.2

Internal voltage reference (V

REFINT

) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.15

Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.15.1

Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.15.2

General-purpose timers (TIM3, 14, 16, 17) . . . . . . . . . . . . . . . . . . . . . . 21

3.15.3

Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.15.4

System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

DS13866 Rev 3

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STM32C011x4/x6 Contents

3.15.5

SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.16

Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.17

Inter-integrated circuit interface (I 2

C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.18

Universal synchronous/asynchronous receiver transmitter (USART) . . . 24

3.19

Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.20

Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.20.1

Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Pinouts, pin description and alternate functions . . . . . . . . . . . . . . . . . 27

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.1

Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.1.1

5.1.2

5.1.3

5.1.4

5.1.5

5.1.6

5.1.7

Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5.2

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5.3

Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.3.1

5.3.2

5.3.3

5.3.4

5.3.5

5.3.6

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 39

Embedded reset and power control block characteristics . . . . . . . . . . . 39

Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Wakeup time from low-power modes and voltage scaling transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

5.3.7

5.3.8

External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

5.3.9

flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

5.3.10

EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

5.3.11

Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5.3.12

I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.3.13

I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5.3.14

NRST input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.3.15

Analog-to-digital converter characteristics . . . . . . . . . . . . . . . . . . . . . . . 67

DS13866 Rev 3 3/94

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STM32C011x4/x6

5.3.16

Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

5.3.17

Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

5.3.18

Characteristics of communication interfaces . . . . . . . . . . . . . . . . . . . . . 73

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

6.1

SO8N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

6.2

WLCSP12 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

6.3

TSSOP20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

6.4

UFQFPN20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

4/94 DS13866 Rev 3

STM32C011x4/x6

List of tables

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

STM32C011x4/x6 family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . 9

Access status versus readout protection level and execution modes. . . . . . . . . . . . . . . . . 12

Interconnect of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

I

Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2

C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 9.

USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 10.

SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 11.

Terms and symbols used in

Table 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 12.

Pin assignment and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 13.

Port A alternate function mapping (AF0 to AF7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 14.

Port A alternate function mapping (AF8 to AF15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 15.

Port B alternate function mapping (AF0 to AF7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 16.

Port B alternate function mapping (AF8 to AF15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 17.

Port C alternate function mapping (AF0 to AF7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 18.

Port C alternate function mapping (AF8 to AF15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 19.

Port F alternate function mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 20.

Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 21.

Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 22.

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 23.

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 24.

Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 25.

Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 26.

Embedded internal voltage reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 27.

Current consumption in Run mode from flash memory at different die temperatures . . . . 42

Table 28.

Current consumption in Run mode from SRAM at different die temperatures . . . . . . . . . . 43

Table 29.

Typical current consumption in Run depending on code executed . . . . . . . . . . . . . . . . . . 44

Table 30.

Current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 31.

Current consumption in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 32.

Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 33.

Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 34.

Current consumption of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 35.

Low-power mode wakeup times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 36.

High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 37.

Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 38.

HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 39.

LSE oscillator characteristics (f

LSE

= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 40.

HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 41.

LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 42.

Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 43.

Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 44.

EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 45.

EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 46.

ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 47.

Electrical sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 48.

I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

DS13866 Rev 3 5/94

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List of tables STM32C011x4/x6

Table 49.

I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 50.

Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 51.

I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 52.

NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 53.

ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 54.

Maximum ADC R

AIN

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 55.

ADC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 56.

TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 57.

TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 58.

IWDG min/max timeout period at 32 kHz LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 59.

Minimum I2CCLK frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 60.

I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 61.

SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 62.

I

2 S characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 63.

USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 64.

SO8N – Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 65.

WLCSP12 – Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 66.

WLCSP12 – Example of PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 67.

TSSOP20 – Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 68.

UFQFPN20 – Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 69.

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

6/94 DS13866 Rev 3

STM32C011x4/x6

List of figures

List of figures

Figure 1.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 2.

Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 3.

STM32C011JxM SO8N pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 4.

STM32C011DxY WLCSP12 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 5.

STM32C011FxP TSSOP20 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 6.

STM32C011FxU UFQFPN20 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 7.

Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 8.

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 9.

Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 10.

Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 11.

V

REFINT

vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 12.

High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 13.

Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 14.

Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 15.

Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 16.

HSI48 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 17.

I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 18.

I/O AC characteristics definition

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 19.

Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 20.

ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 21.

Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 22.

SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 23.

SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 24.

SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 25.

Figure 26.

I

I

2

2

S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

S master timing diagram (Philips protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 27.

SO8N – Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 28.

SO8N – Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 29.

SO8N package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 30.

WLCSP12 – Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 31.

WLCSP12 – Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 32.

WLCSP12 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 33.

TSSOP20 – Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 34.

TSSOP20 – Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 35.

TSSOP20 package marking example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Figure 36.

UFQFPN20 – Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Figure 37.

UFQFPN20 – Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 38.

UFQFPN20 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

DS13866 Rev 3 7/94

7

Introduction

1 Introduction

STM32C011x4/x6

This document provides information on STM32C011x4/x6 microcontrollers, such as description, functional overview, pin assignment and definition, electrical characteristics, packaging, and ordering codes.

Information on memory mapping and control registers is object of reference manual.

Information on Arm ®(a) Cortex ® -M0+ core is available from the www.arm.com website.

8/94 a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

DS13866 Rev 3

STM32C011x4/x6

2 Description

Description

The STM32C011x4/x6 mainstream microcontrollers are based on high-performance

Arm ® Cortex ® -M0+ 32-bit RISC core operating at up to 48 MHz frequency. Offering a high level of integration, they are suitable for a wide range of applications in consumer, industrial and appliance domains and ready for the Internet of Things (IoT) solutions.

The devices incorporate a memory protection unit (MPU), high-speed embedded memories

(6 Kbytes of SRAM and up to 32 Kbytes of flash program memory with read and write protection), DMA, an extensive range of system functions, enhanced I/Os, and peripherals.

The devices offer standard communication interfaces (one I 2 Cs, one SPI / one I 2 S, and two

USARTs), one 12-bit ADC (2.5 MSps) with up to 15 channels, a low-power RTC, an advanced control PWM timer, four general-purpose 16-bit timers, two watchdog timers, and a SysTick timer.

The devices operate within ambient temperatures from -40 to 125°C and with supply voltages from 2.0 V to 3.6 V. Optimized dynamic consumption combined with power-saving modes allows the design of low-power applications.

The devices are housed in packages with 8 to 20 pins.

Table 2. STM32C011x4/x6 family device features and peripheral counts

STM32C011_

Peripheral

_J4 _J6 _D6 _F4 _F6

Flash memory (Kbyte)

SRAM (Kbyte)

Advanced control

General-purpose

SysTick

Watchdog

SPI [I2S]

(1)

16 32 32

6 with parity

1 (16-bit)

4 (16-bit)

1

2

1 [1]

16 32

I2C

USART

RTC / RNG / AES / VREFBUF

1

2

GPIOs

Wakeup pins

12-bit ADC channels (external + internal)

6

2

5 + 2

Yes / No / No / No

10

4

18

Max. CPU frequency

Operating voltage

7 + 2

48 MHz

2.0 to 3.6 V

13 + 2

Operating temperature

(2)

Ambient: -40 to 85 °C / -40 to 105 °C / -40 to 125 °C

Junction: -40 to 105 °C / -40 to 125 °C / -40 to 130 °C

20 Number of pins 8 12

1. The number in brackets denotes the count of SPI interfaces configurable as I

2

S interface.

2. Depends on order code. Refer to Section 7: Ordering information

for details.

DS13866 Rev 3 9/94

26

Description

Figure 1. Block diagram

SWCLK

SWDIO as AF

PA[14:0]

PB[7,6]

PC[15,14]

PF[2]

SWD

CPU

CORTEX-M0+ f max

= 48 MHz

NVIC

GPIOs

Port A

Port B

Port C

Port F

EXTI from peripherals

IOPORT

CRC

DMAMUX

DMA

I/F

V

CORE

Flash memory up to 32 KB

V

DDIO1

V

DDA

V

DD

POWER

Voltage regulator

SRAM

6 KB Parity

POR

Reset

Int

SUPPLY

SUPERVISION

POR/BOR

T sensor

HSI48

LSI

HSE

RCC

Reset & clock control

RC 48 MHz

RC 32 kHz

LSE

XTAL OSC

4-48 MHz

IWDG

LSE

XTAL32 kHz

RTC

System and peripheral clocks

AHB-to-APB

I/F

13x IN

MOSI/SD

MISO/MCK

SCK/CK

NSS/WS as AF

ADC I/F

SPI1/I2S

SYSCFG

TIM1

TIM3

TIM14

PWRCTRL

WWDG

DBGMCU

IRTIM

USART1

USART2

I2C1

STM32C011x4/x6

VDD/VDDA

VSS/VSSA

NRST

OSCX_IN

OSCX_OUT

RTC_OUT

RTC_REFIN

RTC_TS

4 ext./2 int. channels

BKIN, ETR input as AF

4 ch., ETR as AF

1 channel as AF

1 channel as AF

IR_OUT

RX, TX,CTS, RTS as AF

RX, TX,CTS, RTS as AF

SCL, SDA, SMBA,

SMBUS as AF

Power domain of analog blocks : V

DD

V

DDA

V

DDIO1

MSv65922V2

10/94 DS13866 Rev 3

STM32C011x4/x6 Functional overview

3.1 Arm

®

Cortex

®

-M0+ core with MPU

The Cortex-M0+ is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:

• a simple architecture, easy to learn and program

• ultra-low power, energy-efficient operation

• excellent code density

• deterministic, high-performance interrupt handling

• upward compatibility with Cortex-M processor family

• platform security robustness, with integrated Memory Protection Unit (MPU).

The Cortex-M0+ processor is built on a highly area- and power-optimized 32-bit core, with a

2-stage pipeline Von Neumann architecture. The processor delivers exceptional energy efficiency through a small but powerful instruction set and extensively optimized design, providing high-end processing hardware including a single-cycle multiplier.

The Cortex-M0+ processor provides the exceptional performance expected of a modern

32-bit architecture, with a higher code density than other 8-bit and 16-bit microcontrollers.

Owing to embedded Arm core, the STM32C011x4/x6 devices are compatible with Arm tools and software.

The Cortex-M0+ is tightly coupled with a nested vectored interrupt controller (NVIC) described in

Section 3.13.1

.

3.2 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task.

The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the

MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

3.3 Embedded flash memory

STM32C011x4/x6 devices feature up to 32 Kbytes of embedded flash memory available for storing code and data.

DS13866 Rev 3 11/94

26

Functional overview STM32C011x4/x6

Flexible protections can be configured thanks to option bytes:

• Readout protection (RDP) to protect the whole memory. Three levels are available:

– Level 0: no readout protection

– Level 1: memory readout protection: the flash memory cannot be read from or written to if either debug features are connected, boot in RAM or bootloader is selected

– Level 2: chip readout protection: debug features (Cortex-M0+ serial wire), boot in

RAM and bootloader selection are disabled. This selection is irreversible.

Table 3. Access status versus readout protection level and execution modes

Area

Protection level

User execution

Debug, boot from RAM or boot from system memory (loader)

Read Write Erase Read Write Erase

User memory

System memory

Option bytes

1

2

1

2

1

2

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

No

No

Yes

No

Yes

Yes

No

No

Yes

No

No

N/A

Yes

N/A

Yes

N/A

No

N/A

No

N/A

Yes

N/A

No

N/A

No

N/A

Yes

N/A

• Write protection (WRP): the protected area is protected against erasing and programming. Two areas per bank can be selected, with 2-Kbyte granularity.

STM32C011x4/x6 devices have 6 Kbytes of embedded SRAM with parity. Hardware parity check allows memory data errors to be detected, which contributes to increasing functional safety of applications.

The memory can be read/write-accessed at CPU clock speed, with 0 wait states.

12/94

At startup, the boot pin and boot selector option bit are used to select one of the three boot options:

• boot from User flash memory

• boot from System memory

• boot from embedded SRAM

The boot pin is shared with a standard GPIO and can be enabled through the boot selector option bit. The boot loader is located in System memory. It manages the flash memory reprogramming through one of the following interfaces:

• USART on pins PA9/PA10

• I

2

C-bus on pins PB6/PB7

DS13866 Rev 3

STM32C011x4/x6 Functional overview

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at link time and stored at a given memory location.

3.7.1 Power supply schemes

The STM32C011x4/x6 devices require a 2.0 V to 3.6 V operating supply voltage (V

DD

Several different power supplies are provided to specific peripherals:

).

• V

DD

= 2.0 (1.96) to 3.6 V

V

DD is the external power supply for the internal regulator and the system analog such as reset, power management and internal clocks. It is provided externally through

VDD/VDDA pin.

The minimum voltage of 2.0 V corresponds to power-on reset release threshold

V

POR

(max). Once this threshold is crossed and power-on reset is released, the functionality is guaranteed down to power-down reset threshold V

PDR

(min) of 1.96 V.

• V

DDA

= 2.0 V (1.96) (ADC) to 3.6 V

V

DDA

V

DD is the analog power supply for the A/D converter. V

DDA voltage level is identical to

voltage as it is provided externally through VDD/VDDA pin.

• V

DDIO1

= V

DD

V

DDIO1

is the power supply for the I/Os. V

DDIO1

voltage level is identical to V

DD as it is provided externally through VDD/VDDA pin.

voltage

• V

REF+

is the analog peripheral input reference voltage.

V

REF+ is internally connected with V

DD

.

• V

CORE

An embedded linear voltage regulator is used to supply the V

CORE power. V

CORE flash memory is also supplied with V

DD

.

internal digital is the power supply for digital peripherals, SRAM and flash memory. The

DS13866 Rev 3 13/94

26

Functional overview

Figure 2. Power supply overview

VSS

VDD

V

REF+

V

DDA

V

SSA

V

DDA

domain

A/D converter

V

V

SS

DD

V

DD

domain

V

DDIO1

I/O ring

Reset block

Temp. sensor

HSI48

Standby circuitry

(Wakeup logic,

IWDG)

LSE 32KHz

Voltage regulator

V

CORE

V

CORE

domain

Core

SRAM

Digital peripherals

Flash memory

RTC domain

RCC BDCR register

RTC

STM32C011x4/x6

3.7.2 Power supply supervisor

The device has an integrated power-on/power-down (POR/PDR) reset active in all power modes except Shutdown and ensuring proper operation upon power-on and power-down. It maintains the device in reset when the supply voltage is below V

POR/PDR

threshold, without the need for an external reset circuit. Brownout reset (BOR) function allows extra flexibility. It can be enabled and configured through option bytes, by selecting one of four thresholds for rising V

DD

and other four for falling V

DD

.

An embedded linear voltage regulator supplies most of the digital circuitry in the device.

In Standby and Shutdown modes, the regulator is powered down and its output set in highimpedance state, such as to bring its current consumption close to zero.

14/94

By default, the device is in Run mode after system or power reset. It is up to the user to select one of the low-power modes described below:

• Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

• Stop mode

In Stop mode, the device achieves the lowest power consumption while retaining the

SRAM and register contents. All clocks in the V

CORE

are stopped. The HSE and HSI48

DS13866 Rev 3

STM32C011x4/x6 Functional overview stop. The HSI48 can be restarted by a peripheral with wake-up capability requiring

HSI48.

The LSE and LSI can be kept running. The RTC can remain active (Stop mode with

RTC, Stop mode without RTC).

The event of exiting Stop mode enables the HSI48 oscillator and select HSISYS as system clock.

• Standby mode

The Standby mode is used to achieve the lowest power consumption, with POR/PDR always active in this mode. The regulator is switched off to power down V

CORE

domain.

The HSI48 RC oscillator and the HSE crystal oscillator are also powered down. The

RTC is switched off.

For each I/O, the software can determine whether a pull-up, a pull-down or no resistor shall be applied to that I/O during Standby mode.

Upon entering Standby mode, register contents are lost, except for 16-bit backup registers whose contents are kept.

The device exits Standby mode upon external reset event (NRST pin), IWDG reset event, wakeup event (WKUP pin, configurable rising or falling edge), or when a failure is detected on LSE (CSS on LSE).

• Shutdown mode

The Shutdown mode allows to achieve the lowest power consumption. The internal regulator is switched off to power down the V

CORE

domain. The HSI48 and LSI RCoscillators and HSE crystal oscillator are also powered down. The RTC is off.

The BOR is not available in Shutdown mode. No power voltage monitoring is possible in this mode.

SRAM and register contents are lost.

The device exits Shutdown mode upon external reset event (NRST pin), or wakeup event (WKUP pin, configurable rising or falling edge).

3.8

During and upon exiting reset, the Schmitt triggers of I/Os are disabled so as to reduce power consumption. In addition, when the reset source is internal, the built-in pull-up resistor on NRST pin is deactivated.

Interconnect of peripherals

Several peripherals have direct connections between them. This allows autonomous communication between peripherals, saving CPU resources thus power supply consumption. In addition, these hardware connections allow fast and predictable latency.

Depending on peripherals, these interconnections can operate in Run, Sleep and Stop modes.

DS13866 Rev 3 15/94

26

Functional overview

Interconnect source

Table 4. Interconnect of peripherals

Interconnect destination

Interconnect action

STM32C011x4/x6

Run Sleep Stop

TIMx

ADCx

CPU (hard fault)

GPIO

TIMx

ADCx

DMA

TIM1

Timer synchronization or chaining

Conversion triggers

Memory-to-memory transfer trigger

Timer triggered by analog watchdog

RTC TIM16 Timer input channel from RTC events Y

All clock sources (internal and external)

CSS

RAM (parity error)

TIM14,16,17

TIM1,16,17

Clock source used as input channel for

RC measurement and trimming

Y

Timer break Y

TIM1,16,17

TIM1,3

ADC

Timer break

External trigger

Conversion external trigger

Y

Y

Y

Y

Y

Y

Y

Y

Y

-

Y

Y

Y

Y

Y

Y

Y

3.9 Clocks and startup

The clock controller distributes the clocks coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness. It features:

• Clock prescaler: to get the best trade-off between speed and current consumption, the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler

• Safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register.

• Clock management: to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory.

• System clock source: the clock following sources can deliver SYSCLK system clock:

– 4-48 MHz high-speed oscillator with external crystal or ceramic resonator (HSE).

The HSE can also be configured in bypass mode for an external clock.

– 48 MHz high-speed internal RC oscillator (HSI48), trimmable by software.

– LSE - a low-speed oscillator with external crystal (32768 Hz)

– LSI - an internal low-speed RC oscillator (32 kHz)

-

-

-

-

-

-

-

-

-

-

16/94 DS13866 Rev 3

STM32C011x4/x6 Functional overview

• Auxiliary clock source: two ultra-low-power clock sources for the real-time clock

(RTC):

– 32.768 kHz low-speed oscillator with external crystal (LSE), supporting four drive capability modes. The LSE can also be configured in bypass mode for using an external clock.

– 32 kHz low-speed internal RC oscillator (LSI) with ±5% accuracy, also used to clock an independent watchdog.

• Peripheral clock sources: several peripherals ( I2S, USARTs, I2C, ADC) have their own clock independent of the system clock.

• Clock security system (CSS): in the event of HSE or LSE clock failure, the system clock is automatically switched to HSI48 or LSI, respectively. If enabled, a software interrupt is generated. The CCS feature can be enabled by software.

• Clock output:

– MCO (microcontroller clock output) provides one of the internal clocks for external use by the application

– LSCO (low speed clock output) provides LSI or LSE in all low-power modes .

Several prescalers allow the application to configure AHB and APB domain clock frequencies, 48 MHz at maximum.

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function (AF). Most of the GPIO pins are shared with special digital or analog functions.

Through a specific sequence, this special function configuration of I/Os can be locked, such as to avoid spurious writing to I/O control registers.

3.11 Direct memory access controller (DMA)

The direct memory access (DMA) controller is a bus master and system peripheral with single-AHB architecture.

With 3 channels, it performs data transfers between memory-mapped peripherals and/or memories, to offload the CPU.

Each channel is dedicated to managing memory access requests from one or more peripherals. The unit includes an arbiter for handling the priority between DMA requests.

Main features of the DMA controller:

• Single-AHB master

• Peripheral-to-memory, memory-to-peripheral, memory-to-memory and peripheral-toperipheral data transfers

• Access, as source and destination, to on-chip memory-mapped devices such as flash memory, SRAM, and AHB and APB peripherals

• All DMA channels independently configurable:

– Each channel is associated either with a DMA request signal coming from a peripheral, or with a software trigger in memory-to-memory transfers. This configuration is done by software.

DS13866 Rev 3 17/94

26

Functional overview STM32C011x4/x6

– Priority between the requests is programmable by software (four levels per channel: very high, high, medium, low) and by hardware in case of equality (such as request to channel 1 has priority over request to channel 2).

– Transfer size of source and destination are independent (byte, half-word, word), emulating packing and unpacking. Source and destination addresses must be aligned on the data size.

– Support of transfers from/to peripherals to/from memory with circular buffer management

– Programmable number of data to be transferred: 0 to 2

16

- 1

• Generation of an interrupt request per channel. Each interrupt request originates from any of the three DMA events: transfer complete, half transfer, or transfer error.

3.12 DMA request multiplexer (DMAMUX)

The DMAMUX request multiplexer enables routing a DMA request line between the peripherals and the DMA controller. Each channel selects a unique DMA request line, unconditionally or synchronously with events from its DMAMUX synchronization inputs.

DMAMUX may also be used as a DMA request generator from programmable events on its input trigger signals.

The device flexibly manages events causing interrupts of linear program execution, called exceptions. The Cortex-M0+ processor core, a nested vectored interrupt controller (NVIC) and an extended interrupt/event controller (EXTI) are the assets contributing to handling the exceptions. Exceptions include core-internal events such as, for example, a division by zero and, core-external events such as logical level changes on physical lines. Exceptions result in interrupting the program flow, executing an interrupt service routine (ISR) then resuming the original program flow.

The processor context (contents of program pointer and status registers) is stacked upon program interrupt and unstacked upon program resume, by hardware. This avoids context stacking and unstacking in the interrupt service routines (ISRs) by software, thus saving time, code and power. The ability to abandon and restart load-multiple and store-multiple operations significantly increases the device’s responsiveness in processing exceptions.

3.13.1 Nested vectored interrupt controller (NVIC)

The configurable nested vectored interrupt controller is tightly coupled with the core. It handles physical line events associated with a non-maskable interrupt (NMI) and maskable interrupts, and Cortex-M0+ exceptions. It provides flexible priority management.

The tight coupling of the processor core with NVIC significantly reduces the latency between interrupt events and start of corresponding interrupt service routines (ISRs). The ISR vectors are listed in a vector table, stored in the NVIC at a base address. The vector address of an ISR to execute is hardware-built from the vector table base address and the

ISR order number used as offset.

If a higher-priority interrupt event happens while a lower-priority interrupt event occurring just before is waiting for being served, the later-arriving higher-priority interrupt event is served first. Another optimization is called tail-chaining. Upon a return from a higher-priority

18/94 DS13866 Rev 3

STM32C011x4/x6 Functional overview

ISR then start of a pending lower-priority ISR, the unnecessary processor context unstacking and stacking is skipped. This reduces latency and contributes to power efficiency.

Features of the NVIC:

• Low-latency interrupt processing

• 4 priority levels

• Handling of a non-maskable interrupt (NMI)

• Handling of 32 maskable interrupt lines

• Handling of 10 Cortex-M0+ exceptions

• Later-arriving higher-priority interrupt processed first

• Tail-chaining

• Interrupt vector retrieval by hardware

3.13.2 Extended interrupt/event controller (EXTI)

The extended interrupt/event controller adds flexibility in handling physical line events and allows identifying wake-up events at processor wakeup from Stop mode.

The EXTI controller has a number of channels, of which some with rising, falling or rising, and falling edge detector capability. Any GPIO and a few peripheral signals can be connected to these channels.

The channels can be independently masked.

The EXTI controller can capture pulses shorter than the internal clock period.

A register in the EXTI controller latches every event even in Stop mode, which allows the software to identify the origin of the processor's wake-up from Stop mode or, to identify the

GPIO and the edge event having caused an interrupt.

3.14 Analog-to-digital converter (ADC)

A native 12-bit analog-to-digital converter is embedded into STM32C011x4/x6 devices. The

ADC has up to 13 external channels and 2 internal channels (temperature sensor, voltage reference). It performs conversions in single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs.

The ADC frequency is independent from the CPU frequency, allowing maximum sampling rate of 2.5 MSps even with a low CPU speed. An auto-shutdown function guarantees that the ADC is powered off except during the active conversion phase.

The ADC can be served by the DMA controller. It can operate in the whole V

DD range.

supply

An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all scanned channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.

The events generated by the general-purpose timers (TIMx) can be internally connected to the ADC start triggers, to allow the application to synchronize A/D conversions with timers.

DS13866 Rev 3 19/94

26

Functional overview STM32C011x4/x6

The temperature sensor (TS) generates a voltage V

TS

that varies linearly with temperature.

The temperature sensor is internally connected to an ADC input to convert the sensor output voltage into a digital value.

The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor may vary from part to part due to process variation, the uncalibrated internal temperature sensor is suitable only for relative temperature measurements.

To improve the accuracy of the temperature sensor, each part is individually factorycalibrated by ST. The resulting calibration data are stored in the part’s engineering bytes, accessible in read-only mode.

Table 5. Temperature sensor calibration values

Calibration value name Description Memory address

TS_CAL1

TS ADC raw data acquired at a temperature of 30 °C (± 5 °C),

V

DDA

= V

REF+

= 3.0 V (± 10 mV)

0x1FFF7568-0x1FFF7569

3.14.2 Internal voltage reference (V

REFINT

)

The internal voltage reference (V

REFINT

ADC. V

REFINT

) provides a stable (bandgap) voltage output for the

is internally connected to an ADC input. The V

REFINT

voltage is individually precisely measured for each part by ST during production test and stored in the part’s engineering bytes. It is accessible in read-only mode.

Table 6. Internal voltage reference calibration values

Calibration value name Description Memory address

V

REFINT

Raw data acquired at a temperature of 30 °C (± 5 °C),

V

DDA

= V

REF+

= 3.0 V (± 10 mV)

0x1FFF756A-0x1FFF756B

3.15 Timers and watchdogs

The device includes an advanced-control timer, four general-purpose timers, two low-power timers, two watchdog timers and a SysTick timer.

Table 7

compares features of the advanced-control, general-purpose and basic timers.

Timer type

Advanced- control

Timer

TIM1

Counter resolution

Table 7. Timer feature comparison

Counter type

Maximum operating frequency

Prescaler factor

DMA request generation

16-bit

Up, down, up/down

48 MHz

Integer from

1 to 2

16

Yes

Capture/ compare channels

4

Complementary outputs

3

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STM32C011x4/x6 Functional overview

Timer type

Generalpurpose

Timer

TIM3

TIM14

TIM16

TIM17

Table 7. Timer feature comparison (continued)

Counter resolution

Counter type

Maximum operating frequency

Prescaler factor

DMA request generation

16-bit

Up, down, up/down

48 MHz Yes

Capture/ compare channels

4

16-bit

16-bit

Up

Up

48 MHz

48 MHz

Integer from

1 to 2

16

Integer from

1 to 2

16

Integer from

1 to 2 16

No

Yes

1

1

Complementary outputs

-

-

1

3.15.1 Advanced-control timer (TIM1)

The advanced-control timer can be seen as a three-phase PWM unit multiplexed on 6 channels. It has complementary PWM outputs with programmable inserted dead-times. It can also be seen as a complete general-purpose timer. The four independent channels can be used for:

• input capture

• output compare

• PWM output (edge or center-aligned modes) with full modulation capability (0-100%)

• one-pulse mode output

In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled, so as to turn off any power switches driven by these outputs.

Many features are shared with those of the general-purpose TIMx timers (described in

Section 3.15.2

) using the same architecture, so the advanced-control timers can work

together with the TIMx timers via the Timer Link feature for synchronization or event chaining.

There are four synchronizable general-purpose timers embedded in the device (refer to

Table 7 for comparison). Each general-purpose timer can be used to generate PWM outputs

or act as a simple timebase.

• TIM3

This is a full-featured general-purpose timer with 16-bit auto-reload up/downcounter and 16-bit prescaler.

It has four independent channels for input capture/output compare, PWM or one-pulse mode output. It can operate in combination with other general-purpose timers via the

Timer Link feature for synchronization or event chaining. It can generate independent

DS13866 Rev 3 21/94

26

Functional overview STM32C011x4/x6

DMA request and support quadrature encoders. Its counter can be frozen in debug mode.

• TIM14

This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. It has one channel for input capture/output compare, PWM output or one-pulse mode output. Its counter can be frozen in debug mode.

• TIM16, TIM17

These are general-purpose timers featuring:

– 16-bit auto-reload upcounter and 16-bit prescaler

– 1 channel and 1 complementary channel

All channels can be used for input capture/output compare, PWM or one-pulse mode output. The timers can operate together via the Timer Link feature for synchronization or event chaining. They can generate independent DMA request. Their counters can be frozen in debug mode.

The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with user-defined refresh window. It is clocked from an independent 32 kHz internal RC (LSI).

Independent of the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. Its counter can be frozen in debug mode.

3.15.4 System window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked by the system clock. It has an early-warning interrupt capability. Its counter can be frozen in debug mode.

This timer is dedicated to real-time operating systems, but it can also be used as a standard down counter.

Features of SysTick timer:

• 24-bit down counter

• Autoreload capability

• Maskable system interrupt generation when the counter reaches 0

• Programmable clock source

The device embeds an RTC located in the RTC domain and supplied from V

CORE

.

The RTC is an independent BCD timer/counter.

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STM32C011x4/x6 Functional overview

Features of the RTC:

• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format

• Automatic correction for 28, 29 (leap year), 30, and 31 days of the month

• Programmable alarm

• On-the-fly correction from 1 to 32767 RTC clock pulses, usable for synchronization with a master clock

• Reference clock detection - a more precise second-source clock (50 or 60 Hz) can be used to improve the calendar precision

• Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal inaccuracy

• Timestamp feature to save a calendar snapshot, triggered by an event on the timestamp pin

• Multiple clock sources and references:

– a 32.768 kHz external crystal (LSE)

– an external resonator or oscillator (LSE)

– the internal low-power RC oscillator (LSI, with typical frequency of 32 kHz)

– the high-speed external clock (HSE) divided by 32

The RTC operates in Run, Sleep, and Stop mode.

RTC events (Alarm, Timestamp) can generate an interrupt and wake the device up from the low-power modes.

The device embeds one I2C peripheral. Refer to Table 8 for the features.

The I

I

2

2

C-bus interface handles communication between the microcontroller and the serial

C-bus. It controls all I

2

C-bus-specific sequencing, protocol, arbitration and timing.

DS13866 Rev 3 23/94

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Functional overview STM32C011x4/x6

Features of the I 2 C peripheral:

• I 2 C-bus specification and user manual rev. 5 compatibility:

– Slave and master modes, multimaster capability

– Standard-mode (Sm), with a bitrate up to 100 kbit/s

– Fast-mode (Fm), with a bitrate up to 400 kbit/s

– Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and extra output drive I/Os

– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses

– Programmable setup and hold times

– Clock stretching

• SMBus specification rev 3.0 compatibility:

– Hardware PEC (packet error checking) generation and verification with ACK control

– Command and data acknowledge control

– Address resolution protocol (ARP) support

– Host and Device support

– SMBus alert

– Timeouts and idle condition detection

• PMBus rev 1.3 standard compatibility

• Independent clock: a choice of independent clock sources allowing the I

2 communication speed to be independent of the PCLK reprogramming

C

• Wakeup from Stop mode on address match

• Programmable analog and digital noise filters

• 1-byte buffer with DMA capability

Table 8. I 2 C implementation

I 2 C features (1)

Standard mode (up to 100 kbit/s)

Fast mode (up to 400 kbit/s)

Fast Mode Plus (up to 1 Mbit/s) with extra output drive I/Os

Programmable analog and digital noise filters

SMBus/PMBus hardware support

Independent clock

Wakeup from Stop mode on address match

1. X: supported

I2C1

X

X

X

X

X

X

X

24/94

(USART)

The device embeds universal synchronous/asynchronous receivers/transmitters that communicate at speeds of up to 6 Mbit/s.

They provide hardware management of the CTS, RTS and RS485 DE signals, multiprocessor communication mode, master synchronous communication and single-wire

DS13866 Rev 3

STM32C011x4/x6 Functional overview half-duplex communication mode. Some can also support SmartCard communication (ISO

7816), IrDA SIR ENDEC, LIN Master/Slave capability and auto baud rate feature, and have a clock domain independent of the CPU clock, which allows them to wake up the MCU from

Stop mode. The wakeup events from Stop mode are programmable and can be:

• start bit detection

• any received data frame

• a specific programmed data frame

All USART interfaces can be served by the DMA controller.

Table 9. USART implementation

USART modes/features

(1)

USART1

Hardware flow control for modem

Continuous communication using DMA

Multiprocessor communication

Synchronous mode

Smartcard mode

Single-wire half-duplex communication

IrDA SIR ENDEC block

LIN mode

Dual clock domain and wakeup from Stop mode

Receiver timeout interrupt

Modbus communication

Auto baud rate detection

Driver Enable

1. X: supported

X

X

X

X

X

X

X

X

X

X

X

X

X

USART2

-

-

-

-

-

-

X

X

-

X

X

X

X

3.19 Serial peripheral interface (SPI)

The device contains one SPI running at up to 24 Mbits/s in master and slave modes. It supports half-duplex, full-duplex and simplex communications. A 3-bit prescaler gives eight master mode frequencies. The frame size is configurable from 4 bits to 16 bits. The SPI peripherals support NSS pulse mode, TI mode and hardware CRC calculation.

The SPI peripherals can be served by the DMA controller.

The I 2 S interface mode of the SPI peripheral (if supported, see the following table) supports four different audio standards can operate as master or slave, in half-duplex communication mode. It can be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data resolution and synchronized by a specific signal. Audio sampling frequency from 8 kHz up to

192 kHz can be set by an 8-bit programmable linear prescaler. When operating in master mode, it can output a clock for an external audio component at 256 times the sampling frequency.

DS13866 Rev 3 25/94

26

Functional overview

Hardware CRC calculation

Rx/Tx FIFO

NSS pulse mode

I 2 S mode

TI mode

1. X = supported.

Table 10. SPI/I2S implementation

SPI features

(1)

STM32C011x4/x6

SPI1

X

X

X

X

X

3.20.1 Serial wire debug port (SW-DP)

An Arm SW-DP interface is provided to allow a serial wire debugging tool to be connected to the MCU.

26/94 DS13866 Rev 3

STM32C011x4/x6

4

Pinouts, pin description and alternate functions

Pinouts, pin description and alternate functions

Figure 3. STM32C011JxM SO8N pinout

Top view

PB7/PC14-OSCX_IN

VDD/VDDA

VSS/VSSA

PA0/PA1/PA2/PF2-NRST

1

2

3

4

8

7

6

5

PB6/PA14-BOOT0/PC15-OSCX_OUT

PA13

PA12[PA10]

PA11[PA9]/PA8

MSv65924V2

Top view

A

B

C

D

E

Figure 4. STM32C011DxY WLCSP12 ballout

1 2 3 4

PB6

PC15-

OSCX

_OUT

PA13

PC14-

OSCX_IN

PA14-

BOOT0

VDD/

VDDA

PA11

[PA9]/

PA8

PB7

PA12

[PA10]/

PA7

VSS/

VSSA

F

PA3/PA4/

PA5/PA6

PF2-

NRST/

PA0/PA1/

PA2

MSv65925V1

DS13866 Rev 3 27/94

31

Pinouts, pin description and alternate functions

Figure 5. STM32C011FxP TSSOP20 pinout

Top view

PB7

PC14-OSCX_IN

PC15-OSCX_OUT

VDD/VDDA

VSS/VSSA

PF2-NRST

PA0

PA1

PA2

PA3

5

6

7

8

9

10

3

4

1

2

20

19

18

17

16

15

14

13

12

11

PB6

PA14-BOOT0

PA13

PA12[PA10]

PA11[PA9]

PA8

PA7

PA6

PA5

PA4

STM32C011x4/x6

Figure 6. STM32C011FxU UFQFPN20 pinout

Top view

PC15-OSCX_OUT

VDD/VDDA

VSS/VSSA

PF2-NRST

PA0

3

4

1

2

5

15

14

UFQFPN20

13

12

11

PA12 [PA10]

PA11 [PA9]

PA8

PA7

PA6

28/94

Column

Pin name

Pin type

I/O structure

Table 11. Terms and symbols used in Table 12

Symbol Definition

Terminal name corresponds to its by-default function at reset, unless otherwise specified in parenthesis under the pin name.

S

I

Supply pin

Input only pin

I/O

FT

RST

_f

Input / output pin

5 V tolerant I/O

Bidirectional reset pin with embedded weak pull-up resistor

Options for FT I/Os

I/O, Fm+ capable

_a I/O, with analog switch function

DS13866 Rev 3

STM32C011x4/x6 Pinouts, pin description and alternate functions

Column

Table 11. Terms and symbols used in Table 12 (continued)

Symbol Definition

Note Upon reset, all I/Os are set as analog inputs, unless otherwise specified.

Pin functions

Alternate functions

Functions selected through GPIOx_AFR registers

Additional functions

Functions directly selected/enabled through peripheral registers

Pin

Table 12. Pin assignment and description

Pin name

(function upon reset)

Alternate functions

Additional functions

1 B3 2 20

8 A4 3 1

2 C4 4 2

3 E4 5 3

4

4

F3

F3

6

7

4

5

PC14-

OSCX_IN

(PC14)

PC15-

OSCX_OUT

(PC15)

VDD/VDDA

VSS/VSSA

PF2-NRST

PA0

I/O

I/O

S

S

I/O

I/O

FT

FT

-

-

-

FT

4 F3 8 6

4 F3 9 7

F1 10 8

F1 11 9

PA1

PA2

PA3

PA4

I/O FT

I/O FT

I/O FT

I/O FT

-

-

-

-

-

-

-

-

-

-

USART1_TX, TIM1_ETR,

TIM1_BKIN2, IR_OUT,

USART2_RTS_DE_CK, TIM17_CH1,

TIM3_CH2, I2C1_SDA, EVENTOUT

OSCX_IN

OSC32_EN, OSC_EN, TIM1_ETR,

TIM3_CH3

OSCX_OUT

-

-

MCO, TIM1_CH4

USART2_CTS, TIM16_CH1,

USART1_TX, TIM1_CH1

SPI1_SCK/I2S1_CK,

USART2_RTS_DE_CK, TIM17_CH1,

USART1_RX, TIM1_CH2,

I2C1_SMBA, EVENTOUT

SPI1_MOSI/I2S1_SD, USART2_TX,

TIM16_CH1N, TIM3_ETR,

TIM1_CH3

USART2_RX, TIM1_CH1N,

TIM1_CH4, EVENTOUT

SPI1_NSS/I2S1_WS, USART2_TX,

TIM1_CH2N, TIM14_CH1,

TIM17_CH1N, EVENTOUT

-

-

NRST

ADC_IN0, WKUP1

ADC_IN1

ADC_IN2,

WKUP4,LSCO

ADC_IN3

ADC_IN4, RTC_TS,

RTC_OUT1, WKUP2

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31

Pinouts, pin description and alternate functions

Table 12. Pin assignment and description (continued)

Pin

STM32C011x4/x6

Pin name

(function upon reset)

Alternate functions

Additional functions

-

-

-

5

-

-

F1 12 10

F1 13 11

E2 14 12

D1 15 13

-

-

-

-

-

-

5 D1 16 14

6

7

E2 17 15

B1 18 16

PA5

PA6

PA7

PA8

PA9

PA10

PA11 [PA9]

PA12 [PA10]

PA13

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

FT

FT

FT

FT

FT

FT

FT

FT

FT

8 C2 19 17 PA14-BOOT0 I/O FT

-

-

-

-

(1)

(1)

(1)

(1)

(2)

(2)

SPI1_SCK/I2S1_CK, USART2_RX,

TIM1_CH3N, TIM1_CH1,

EVENTOUT

SPI1_MISO/I2S1_MCK, TIM3_CH1,

TIM1_BKIN, TIM16_CH1

SPI1_MOSI/I2S1_SD, TIM3_CH2,

TIM1_CH1N, TIM14_CH1,

TIM17_CH1

MCO, USART2_TX, TIM1_CH1,

EVENTOUT, SPI1_NSS/I2S1_WS,

TIM1_CH2N, TIM1_CH3N,

TIM3_CH3, TIM3_CH4, TIM14_CH1,

USART1_RX, MCO2

MCO, USART1_TX, TIM1_CH2,

TIM3_ETR, I2C1_SCL, EVENTOUT

USART1_RX, TIM1_CH3, MCO2,

TIM17_BKIN, I2C1_SDA,

EVENTOUT

SPI1_MISO/I2S1_MCK,

USART1_CTS, TIM1_CH4,

TIM1_BKIN2

SPI1_MOSI/I2S1_SD,

USART1_RTS_DE_CK, TIM1_ETR,

I2S_CKIN

SWDIO, IR_OUT, TIM3_ETR,

USART2_RX, EVENTOUT

SWCLK, USART2_TX, EVENTOUT,

SPI1_NSS/I2S1_WS, USART2_RX,

TIM1_CH1, MCO2,

USART1_RTS_DE_CK

ADC_IN5

ADC_IN6

ADC_IN7

ADC_IN8

-

-

ADC_IN11

ADC_IN12

ADC_IN13

ADC_IN14, BOOT0

30/94 DS13866 Rev 3

STM32C011x4/x6 Pinouts, pin description and alternate functions

Table 12. Pin assignment and description (continued)

Pin

Pin name

(function upon reset)

Alternate functions

Additional functions

8

1

A2 20 18

D3 1 19

PB6

PB7

I/O

I/O

FT

FT -

-

USART1_TX, TIM1_CH3,

TIM16_CH1N, TIM3_CH3,

USART1_RTS_DE_CK,

USART1_CTS, I2C1_SCL,

I2C1_SMBA, SPI1_MOSI/I2S1_SD,

SPI1_MISO/I2S1_MCK,

SPI1_SCK/I2S1_CK, TIM1_CH2,

TIM3_CH1, TIM3_CH2,

TIM16_BKIN, TIM17_BKIN

USART1_RX, TIM1_CH4,

TIM17_CH1N, TIM3_CH4,

I2C1_SDA, EVENTOUT,

USART2_CTS, TIM16_CH1,

TIM3_CH1, I2C1_SCL

WKUP3

RTC_REFIN

1. Pins PA9 and PA10 can be remapped in place of pins PA11 and PA12 (default mapping), using SYSCFG_CFGR1 register.

2. Upon reset, these pins are configured as SWD alternate functions, and the internal pull-up on PA13 pin and the internal pull-down on PA14 pin are activated.

DS13866 Rev 3 31/94

31

Port AF0

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

PA8

PA9

PA10

-

SPI1_SCK/I2S1_

CK

SPI1_MOSI/I2S1

_SD

-

SPI1_NSS/I2S1_

WS

SPI1_SCK/I2S1_

CK

SPI1_MISO/I2S1

_MCK

SPI1_MOSI/I2S1

_SD

MCO

MCO

-

PA11

PA12

PA13

PA14

SPI1_MISO/I2S1

_MCK

SPI1_MOSI/I2S1

_SD

SWDIO

SWCLK

AF1

USART2_CTS

USART2_RTS_

DE_CK

USART2_TX

USART2_RX

USART2_TX

USART2_RX

TIM3_CH1

TIM3_CH2

USART2_TX

USART1_TX

USART1_RX

USART1_CTS

USART1_RTS_

DE_CK

IR_OUT

USART2_TX

Table 13. Port A alternate function mapping (AF0 to AF7)

AF2 AF3 AF4 AF5

TIM16_CH1

TIM17_CH1

TIM16_CH1N

TIM1_CH1N

TIM1_CH2N

TIM1_CH3N

TIM1_BKIN

TIM1_CH1N

TIM1_CH1

TIM1_CH2

TIM1_CH3

TIM1_CH4

TIM1_ETR

-

-

-

-

TIM3_ETR

-

-

-

-

-

-

TIM3_ETR

MCO2

-

-

TIM3_ETR

-

USART1_TX

USART1_RX

-

TIM14_CH1

-

-

-

-

-

-

TIM14_CH1

-

-

USART2_RX

-

TIM1_CH1

TIM1_CH2

TIM1_CH3

TIM1_CH4

TIM17_CH1N

TIM1_CH1

TIM16_CH1

TIM17_CH1

-

-

-

TIM17_BKIN

TIM1_BKIN2

I2S_CKIN

AF6

-

I2C1_SMBA

-

-

-

-

-

-

-

I2C1_SCL

I2C1_SDA

-

-

-

-

AF7

-

EVENTOUT

-

EVENTOUT

EVENTOUT

EVENTOUT

-

-

EVENTOUT

EVENTOUT

EVENTOUT

-

-

EVENTOUT

EVENTOUT

Port AF8

PA8

PA14

SPI1_NSS/I2S1_

WS

SPI1_NSS/I2S1_

WS

AF9

TIM1_CH2N

Table 14. Port A alternate function mapping (AF8 to AF15)

AF10 AF11 AF12 AF13

TIM1_CH3N TIM3_CH3 TIM14_CH1

USART2_RX TIM1_CH1 MCO2

TIM3_CH4

USART1_RTS_

DE_CK

-

Port

PB6

PB7

AF0

USART1_TX

USART1_RX

AF1

TIM1_CH3

TIM1_CH4

Table 15. Port B alternate function mapping (AF0 to AF7)

AF2 AF3 AF4 AF5

TIM16_CH1N

TIM17_CH1N

TIM3_CH3

TIM3_CH4

USART1_RTS_

DE_CK

-

USART1_CTS

-

AF14

USART1_RX

-

AF6

I2C1_SCL

I2C1_SDA

Port

PB6

PB7

AF8 AF9

Table 16. Port B alternate function mapping (AF8 to AF15)

AF10

SPI1_MOSI/I2S1

_SD

SPI1_MISO/I2S1

_MCK

SPI1_SCK/I2S1_

CK

USART2_CTS TIM16_CH1

AF11

TIM1_CH2

TIM3_CH1

AF12

TIM3_CH1

-

AF13

TIM3_CH2

-

Port AF0

PC14 USART1_TX

PC15 OSC32_EN

Port

PC14

AF8

IR_OUT

AF1

TIM1_ETR

OSC_EN

Table 17. Port C alternate function mapping (AF0 to AF7)

AF2 AF3 AF4 AF5

TIM1_BKIN2

TIM1_ETR

-

TIM3_CH3 -

-

-

-

AF9

USART2_RTS_

DE_CK

Table 18. Port C alternate function mapping (AF8 to AF15)

AF10 AF11 AF12 AF13

TIM17_CH1 TIM3_CH2 -

AF15

MCO2

-

AF7

I2C1_SMBA

EVENTOUT

AF14

TIM16_BKIN

I2C1_SCL

AF15

TIM17_BKIN

-

AF6

-

-

AF14

I2C1_SDA

AF7

-

-

AF15

EVENTOUT

Port

PF2

*

AF0

MCO

AF1

TIM1_CH4

Table 19. Port F alternate function mapping

AF2 AF3 AF4

-

AF5

-

AF6

-

AF7

-

STM32C011x4/x6 Electrical characteristics

5.1.1

Unless otherwise specified, all voltages are referenced to V

SS

.

Parameter values defined at temperatures or in temperature ranges out of the ordering information scope are to be ignored.

Packages used for characterizing certain electrical parameters may differ from the commercial packages as per the ordering information.

Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T

A the selected temperature range).

= 25 °C and T

A

= T

A

(max) (given by

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ±3 σ ).

Unless otherwise specified, typical data are based on T

A are given only as design guidelines and are not tested.

= 25 °C, V

DD

= V

DDA

= 3 V. They

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ±2 σ )

.

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

5.1.5

The loading conditions used for pin parameter measurement are shown in

Figure 7

.

Pin input voltage

The input voltage measurement on a pin of the device is described in

Figure 8 .

Figure 7. Pin loading conditions Figure 8. Pin input voltage

MCU pin MCU pin

C = 50 pF

V

IN

DS13866 Rev 3 35/94

79

Electrical characteristics

5.1.6 Power supply scheme

1 x 100 nF

+ 1 x 4.7 μF

V

DD

Figure 9. Power supply scheme

VDD/VDDA

GPIOs

RTC

STM32C011x4/x6

V

CORE

V

DD

Regulator

V

DDIO

OUT

IN

IO logic

Kernel logic

(CPU, digital and memories)

V

SS

V

DDA

V

REF+

V

REF-

V

SSA

ADC

VSS/VSSA

MSv57328V1

Caution: Power supply pin pair (VDD/VDDA and VSS/VSSA) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device.

36/94 DS13866 Rev 3

STM32C011x4/x6 Electrical characteristics

Figure 10. Current consumption measurement scheme

I

DD

VDD/VDDA

V

DD

(V

DDA

)

MS55840V1

5.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in

Table 20 , Table 21

and Table 22

may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

All voltages are defined with respect to V

SS

.

Symbol

Table 20. Voltage characteristics

Ratings Min Max

V

DD

- V

SS

V

IN

(1)

External supply voltage

Input voltage on pin

-0.3

-0.3

V

DD

4.0

+ 4.0

(2)

1. V

IN

maximum must always be respected. Refer to

Table 21

for the maximum allowed injected current values.

2. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.

Unit

V

Symbol

Table 21. Current characteristics

Ratings Max Unit

I

VDD/VDDA

I

VSS/VSSA

Current into VDD/VDDA power pin (source)

Current out of VSS/VSSA ground pin (sink)

100

100

Output current sunk by any I/O and control pin 20

I

IO(PIN)

∑ I

(PIN)

Output current sourced by any I/O and control pin

Total output current sunk by sum of all I/Os and control pins

(1)

Total output current sourced by sum of all I/Os and control pins

(1)

20

80

80

I

INJ(PIN)

(1)(2)

∑ I

INJ(PIN)

Injected current on a FT_xx pin

Total injected current (sum of all I/Os and control pins)

(3)

-5 / 0

-25

1. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.

mA

DS13866 Rev 3 37/94

79

Electrical characteristics STM32C011x4/x6

2. A positive injection is induced by V

exceeded. Refer also to

> V

DDIOx

while a negative injection is induced by V < V

SS

. I

INJ(PIN)

must never be

3. When several inputs are submitted to a current injection, the maximum ∑ |I injected currents (instantaneous values).

INJ(PIN)

| is the absolute sum of the negative

Symbol

T

STG

T

J

Table 22. Thermal characteristics

Ratings

Storage temperature range

Maximum junction temperature

Value

–65 to +150

130

Unit

°C

°C

38/94 DS13866 Rev 3

STM32C011x4/x6 Electrical characteristics

5.3.1 General operating conditions

Symbol

V

DD

V

IN f

PCLK

T

A

T

J

Parameter

Standard operating voltage

I/O input voltage

APB clock frequency

Ambient temperature

(3)

Junction temperature

Table 23. General operating conditions

Conditions Min

-

-

-

Suffix 6 (4)

Suffix 7

(4)

Suffix 3

(4)

Suffix 6

(4)

Suffix 7

(4)

Suffix 3

(4)

2.0

(1)

-0.3

-

-40

-40

-40

-40

-40

-40

Max

3.6

Min (VDD + 3.6, 5.5)

(2)

48

85

105

125

105

125

130

Unit

V

V

MHz

°C

°C

1. When RESET is released functionality is guaranteed down to V

PDR

min.

2. For operation with voltage higher than VDD +0.3 V, the internal pull-up and pull-down resistors must be disabled.

3. The T

A

(max) applies to P

D

(max). At P

J

D

< P

D

(max) the ambient temperature is allowed to go higher than T

does not exceed T

J

(max). Refer to Section 6.5: Thermal characteristics .

A

(max) provided

4. Temperature range digit in the order code. See

Section 7: Ordering information

.

The parameters given in

Table 24 are derived from tests performed under the ambient

temperature condition summarized in

Table 23 .

Symbol t

VDD

Table 24. Operating conditions at power-up / power-down

Parameter Min Max

V

DD

rise time rate

V

DD

fall time rate

0

10

∞

∞

Unit

µs/V

5.3.3 Embedded reset and power control block characteristics

The parameters given in

Table 25 are derived from tests performed under the ambient temperature conditions summarized in Table 23

.

Symbol t

RSTTEMPO

(1)

V

POR

(1)

V

PDR

(1)

Table 25. Embedded reset and power control block characteristics

Parameter Conditions Min Typ Max Unit

POR temporization when V

DD

crosses V

POR

Power-on reset threshold

Power-down reset threshold

V

DD rising

-

-

270 500

1.9

1.94

1.98

1.88

1.92

1.96

µs

V

V

DS13866 Rev 3 39/94

79

Electrical characteristics STM32C011x4/x6

Table 25. Embedded reset and power control block characteristics (continued)

Symbol Parameter Conditions Min Typ Max Unit

V

BOR1

V

BOR2

V

BOR3

V

BOR4

Brownout reset threshold 1

Brownout reset threshold 2

Brownout reset threshold 3

Brownout reset threshold 4

V hyst_POR_PDR

V hyst_BOR

I

DD(BOR)

(1)

Hysteresis of V

POR

Hysteresis of V

and V

PDR

BORx

BOR consumption

1. Specified by design – Not tested in production.

V

DD rising

V

DD falling

V

DD rising

V

DD falling

V

DD rising

V

DD falling

V

DD rising

V

DD falling

-

-

-

-

-

-

2.05

2.10

2.18

1.95

2.00

2.08

2.20

2.31

2.38

2.10

2.21

2.28

2.50

2.62

2.68

2.40

2.52

2.58

2.80

2.91

3.00

2.70

2.81

2.90

20

100

2.2

-

-

2.5

V

V

V

V mV mV

µA

The parameters given in

Table 26 are derived from tests performed under the ambient

temperature and supply voltage conditions summarized in Table 23: General operating conditions

.

Symbol

Table 26. Embedded internal voltage reference

Parameter Conditions Min Typ Max

1.182 1.212

1.232

t

V

REFINT

S_vrefint

(1)(2)

Internal reference voltage

ADC sampling time when reading the internal reference voltage

-

t

start_vrefint

(2)

Start time of reference voltage buffer when ADC is enable

I

DD(VREFINTBUF)

(2)

∆ V

REFINT

(2)

V

REFINT

V

DD

buffer consumption from

when converted by ADC

Internal reference voltage spread over the temperature range

V

DD

-

-

= 3 V

T

Coeff

A

Coeff

V

DDCoeff

Averange temperature coefficient

Long term stability

-

1000 hours, T = 25 °C

Voltage coefficient 3.0 V < V

DD

< 3.6 V

1. The shortest sampling time can be determined in the application by multiple iterations.

2. Specified by design – Not tested in production.

4

-

9

-

-

-

-

-

8

13.5

30

20

300

250

-

12

23

50

Unit

V

µs

µs

µA mV

70

1000 ppm/°C ppm

1200 ppm/V

40/94 DS13866 Rev 3

STM32C011x4/x6

5.3.5

Electrical characteristics

Figure 11. V

REFINT

vs. temperature

V

1.235

1.23

1.225

1.22

1.215

1.21

1.205

1.2

1.195

1.19

1.185

-40 -20 0 20

Mean

40

Min

60

Max

80 100 120 °C

MSv40169V1

Supply current characteristics

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code.

The current consumption is measured as described in

Figure 10: Current consumption measurement scheme

.

Typical and maximum current consumption

The MCU is placed under the following conditions:

• All I/O pins are in analog input mode

• All peripherals are disabled except when explicitly mentioned

• The flash memory access time is adjusted with the minimum wait states number, depending on the f

HCLK

frequency (refer to the table “Number of wait states according to CPU clock (HCLK) frequency” available in the RM0490 reference manual).

• When the peripherals are enabled f

PCLK

= f

HCLK

• For flash memory and shared peripherals f

PCLK

= f

HCLK

= f

HCLKS

Unless otherwise stated, values given in

Table 27 through

Table 34 are derived from tests

performed under ambient temperature and supply voltage conditions summarized in

Table 23: General operating conditions .

DS13866 Rev 3 41/94

79

Table 27. Current consumption in Run mode from flash memory at different die temperatures

Conditions Typ Max

(1)

Symbol Parameter

General

(2) f

HCLK

48 MHz

32 MHz

24 MHz

Fetch from

(3)

25

°C

85

°C

105

°C

125

°C

25

°C

85

°C

105

°C

125

°C

3.05

3.15

3.25

3.35

3.60

3.80

4.10

4.60

2.10

2.15

2.25

2.35

2.50

2.70

3.00

3.50

1.80

1.85

1.90

2.05

2.10

2.40

2.70

3.20

I

DD(Run)

Supply current in

Run mode f f

HCLK

( > 32.768 kHz),

HCLK

= f

= f

HSE_bypass

LSE_bypass

( = 32.768 kHz) f f

HCLK

( > 32 kHz),

HCLK

= f

= f

HSI48/HSIDIV

LSI

( = 32 kHz)

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

125 kHz

32.768 kHz

48 MHz

24 MHz

12 MHz

6 MHz

3 MHz

1.5 MHz

750 kHz

375 kHz

32 kHz

Flash memory

1.25

1.30

1.35

1.45

1.50

1.70

2.00

2.50

0.655 0.710 0.765 0.865 0.790 1.10

1.40

1.90

0.3654 0.420 0.470 0.570 0.460 0.700 0.980

1.50

0.225 0.270 0.325 0.425 0.290 0.540 0.820

1.40

0.150 0.200 0.250 0.350 0.200 0.450 0.730

1.30

0.115

0.160 0.215 0.315 0.160 0.410 0.690

1.20

0.0875 0.135 0.185 0.285 0.130 0.380 0.650

1.20

0.082 0.130 0.180 0.280 0.120 0.370 0.650

1.20

3.40

3.50

3.55

3.60

3.90

4.10

4.40

4.90

2.25

2.30

2.35

2.45

2.60

2.80

3.10

3.60

1.45

1.50

1.55

1.65

1.70

1.90

2.20

2.70

1.05

1.10

1.15

1.20

1.20

1.40

1.70

2.20

0.855 0.880 0.925

1.00

0.960 1.20

1.50

2.00

0.750 0.780 0.825 0.915 0.840 1.10

1.40

1.90

0.700 0.730 0.775 0.865 0.780 1.00

1.30

1.80

0.675 0.705 0.750 0.840 0.760 0.970

1.30

1.80

0.082 0.130 0.180 0.280 0.120 0.370 0.650

1.20

1. Evaluated by characterization – Not tested in production.

2. V

DD

= 3.0 V for values in Typ columns and 3.6 V for values in Max columns, all peripherals disabled.

3. Prefetch and cache enabled when fetching from flash memory.

Unit mA

Table 28. Current consumption in Run mode from SRAM at different die temperatures

Conditions Typ Max

(1)

Symbol Parameter

General

(2) f

HCLK

48 MHz

32 MHz

24 MHz

Fetch from

(3)

25

°C

85

°C

105

°C

125

°C

25

°C

85

°C

105

°C

125

°C

2.80

2.90

2.95

3.05

3.20

3.40

3.70

4.20

1.90

1.95

2.00

2.10

2.20

2.40

2.70

3.20

1.45

1.50

1.55

1.65

1.70

1.90

2.20

2.70

I

DD(Run)

Supply current in

Run mode f

HCLK

= f

HSE_bypass f

(>32.768 kHz),

HCLK

= f

LSE_bypass

(=32.768 kHz) f

HCLK

= f

HSI48/HSIDIV f

( > 32 kHz),

HCLK

= f

LSI

( = 32 kHz)

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

125 kHz

32.768 kHz

48 MHz

24 MHz

12 MHz

6 MHz

3 MHz

1.5 MHz

750 kHz

375 kHz

32 kHz

SRAM

0.990

1.05

1.10

1.20

1.20

1.40

1.70

2.20

0.535 0.585 0.635 0.735 0.630 0.860

1.20

1.70

0.305 0.355 0.405 0.505 0.380 0.630 0.900

1.40

0.195 0.240 0.295 0.390 0.250 0.500 0.770

1.30

0.135 0.185 0.235 0.335 0.180 0.430 0.710

1.30

0.110

0.155 0.205 0.305 0.150 0.400 0.670

1.20

0.0865 0.135 0.185 0.285 0.130 0.370 0.650

1.20

0.082 0.130 0.180 0.280 0.120 0.370 0.640

1.20

3.15

3.20

3.25

3.30

3.50

3.70

3.90

4.40

1.90

1.95

2.00

2.05

2.10

2.30

2.60

3.10

1.30

1.30

1.35

1.45

1.50

1.70

1.90

2.40

0.965 0.995

1.05

1.15

1.15

1.30

1.60

2.10

0.810 0.835 0.880 0.970 0.900 1.20

1.40

1.90

0.730 0.760 0.800 0.890 0.810 1.10

1.30

1.80

0.690 0.720 0.765 0.855 0.770 0.990

1.30

1.80

0.670 0.700 0.745 0.835 0.750 0.970

1.30

1.80

0.082 0.130 0.180 0.280 0.120 0.370 0.640

1.20

1. Evaluated by characterization – Not tested in production.

2. V

DD

= 3.0 V for values in Typ columns and 3.6 V for values in Max columns, all peripherals disabled.

3. Code compiled with high optimization for space in SRAM.

Unit mA

Electrical characteristics STM32C011x4/x6

Table 29. Typical current consumption in Run depending on code executed

Conditions Typ Typ

Symbol Parameter Unit

General

(1)

Code

Fetch from (2)

25 °C 25 °C

I

DD(Run)

Supply current in

Run mode f

HCLK

= f

48 MHz

HSE_bypass

= f

HCLK

= f

16 MHz

HSE_bypass

= f

HCLK

= f

2 MHz

HSE_bypass

=

Reduced code

(3)

Coremark

Dhrystone

Fibonacci

WhileLoop

Reduced code

(3)

Coremark

Dhrystone

Fibonacci

WhileLoop

Reduced code

(3)

Coremark

Dhrystone

Fibonacci

WhileLoop

Reduced code

(3)

Coremark

Dhrystone

Fibonacci

WhileLoop

Reduced code

(3)

Coremark

Dhrystone

Fibonacci

WhileLoop

Reduced code

(3)

Coremark

Dhrystone

Fibonacci

WhileLoop

Flash memory

SRAM

Flash memory

SRAM

Flash memory

SRAM mA

μ A

1.15

0.835

0.645

0.990

0.950

0.945

1.00

0.775

0.225

0.210

0.210

0.175

0.150

0.195

0.190

0.190

0.195

0.165

3.40

3.15

3.20

2.40

1.80

2.80

2.70

2.70

2.85

2.15

1.25

1.15

59.1

62.5

48.4

112.5

105.0

105.0

87.5

75.0

71.9

52.2

40.3

61.9

59.4

97.5

95.0

95.0

97.5

82.5

70.8

65.6

66.7

50.0

37.5

58.3

56.3

56.3

59.4

44.8

78.1

71.9

Unit

μ A/MHz

μ A/MHz

44/94 DS13866 Rev 3

STM32C011x4/x6 Electrical characteristics

Table 29. Typical current consumption in Run depending on code executed (continued)

Conditions Typ Typ

Symbol Parameter Unit Unit

General

(1)

Code

Fetch from

(2)

25 °C 25 °C

I

DD(Run)

Supply current in

Run mode f

HCLK

= f

HSI48/HSIDIV

= 48 MHz

(HSIDIV = 1) f

HCLK

= f

HSI48/HSIDIV

= 12 MHz

(HSIDIV = 4) f

HCLK

= f

HSI48/HSIDIV

= 3 MHz

(HSIDIV = 16)

Reduced code

(3)

Coremark

Dhrystone

Fibonacci

WhileLoop

Reduced code

(3)

Coremark

Dhrystone

Fibonacci

WhileLoop

Reduced code

(3)

Coremark

Dhrystone

Fibonacci

WhileLoop

Reduced code

(3)

Coremark

Dhrystone

Fibonacci

WhileLoop

Reduced code

(3)

Coremark

Dhrystone

Fibonacci

WhileLoop

Reduced code

(3)

Coremark

Dhrystone

Fibonacci

WhileLoop

Flash memory

SRAM

Flash memory

SRAM

Flash memory

SRAM mA

μ A

μ A/MHz

μ A/MHz

1.25

1.30

1.10

0.855

0.835

1.40

1.15

1.00

1.30

1.25

3.05

3.20

2.50

1.45

1.40

3.75

3.50

3.55

2.75

2.15

3.15

3.05

0.835

0.780

0.745

0.810

0.800

0.800

0.810

0.770

116.7

95.8

83.3

108.3

104.2

104.2

108.3

91.7

285.0

278.3

63.5

66.7

52.1

120.8

116.7

78.1

72.9

74.0

57.3

44.8

65.6

63.5

278.3

260.0

248.3

270.0

266.7

266.7

270.0

256.7

1. V

DD

= 3.0 V , all peripherals disabled

2. Prefetch and cache enabled when fetching from flash

3. Reduced code used for characterization results provided in Table 27 .

DS13866 Rev 3 45/94

79

Table 30. Current consumption in Sleep mode

Conditions Typ Max

(1)

Symbol Parameter

General f

HCLK

25

°C

85

°C

105

°C

125

°C

25

°C

85

°C

105

°C

125

°C

I

DD(Sleep)

Supply current in

Sleep mode f

HCLK f

All peripherals

( > 32 kHz), f disabled,

= f

HSI48/HSIDIV

HCLK

= f

LSI

( = 32 kHz)

All peripherals f

HCLK disabled,

= f

HSE_bypass

( > 32.768 kHz),

HCLK

= f

LSE_bypass

( = 32.768 kHz)

Flash memory enabled

Flash memory disabled

(flash memory powerdown sleep mode)

48 MHz

24 MHz

12 MHz

6 MHz

1.5 MHz

375 kHz

32 kHz

48 MHz

32 MHz

24 MHz

16 MHz

1.20

1.20

1.25

1.35

1.50

1.70

2.00

2.50

0.92

0.95

0.99

1.10

1.10

1.30

1.60

2.10

0.79

0.81

0.86

0.95

0.91

1.20

1.40

1.90

0.72

0.75

0.79

0.88

0.82

1.10

1.30

1.80

0.67

0.70

0.74

0.83

0.75

0.97

1.30

1.80

0.66

0.69

0.73

0.82

0.73

0.95

1.30

1.80

0.08

0.13

0.18

0.28

0.12

0.37

0.64

1.20

0.820 0.875 0.930

1.05

1.20

1.40

1.70

2.20

0.575 0.630 0.680 0.785 0.800 1.10

1.40

1.90

0.450 0.500 0.555 0.655 0.630 0.880

1.20

1.70

0.325 0.380 0.430 0.535 0.460 0.710 0.980

1.50

8 MHz

2 MHz

0.205 0.250 0.305 0.405 0.300 0.540 0.820

1.40

0.110 0.160 0.210 0.310 0.170 0.420 0.690

1.20

500 kHz 0.0875 0.135 0.185 0.285 0.130 0.380 0.650

1.20

32.768 kHz 0.0805 0.125 0.180 0.280 0.120 0.370 0.640

1.20

48 MHz

32 MHz

24 MHz

16 MHz

0.815 0.870 0.925

1.05

1.20

1.40

0.570 0.620 0.675 0.775 0.790 1.10

0.445 0.495 0.545 0.650 0.630 0.870

1.70

1.40

1.20

0.320 0.375 0.425 0.525 0.460 0.700 0.980

2.20

1.90

1.70

1.50

8 MHz

2 MHz

0.200 0.245 0.295 0.395 0.290 0.530 0.810

1.40

0.105 0.150 0.205 0.300 0.160 0.410 0.680

1.20

500 kHz 0.0815 0.130 0.180 0.280 0.120 0.370 0.650

1.20

32.768 kHz 0.0745 0.120 0.170 0.270 0.110 0.360 0.630

1.20

1. Evaluated by characterization – Not tested in production.

Unit mA

Symbol

I

DD(Stop)

Parameter

Supply current in Stop mode

Table 31. Current consumption in Stop mode

Typ

Conditions V

DD 25

°C

85

°C

105

°C

All clocks off

All clocks off

Flash memory in power-down stop mode

RTC enabled and supplied with

LSE bypass (32.768 kHz)

RTC enabled and supplied with

LSE bypass (32.768 kHz)

Flash memory in power-down stop mode

HSI Kernel on

2 V 79.0

2.4 V 79.0

3 V 80.0

3.6 V 81.5

2 V 70.5

2.4 V 72.0

3 V 73.5

3.6 V 75.0

2 V 78.0

2.4 V 78.5

3 V 80.0

3.6 V 82.0

2 V 71.0

2.4 V 72.5

3 V 74.0

3.6 V 75.5

2 V 605

2.4 V 605

3 V 605

3.6 V 605

120

120

125

125

125

130

125

125

125

130

120

120

120

120

120

120

630

630

630

635

170

175

175

175

180

180

175

175

180

180

170

170

170

170

170

175

675

675

675

680

1. Evaluated by characterization – Not tested in production.

125

°C

270

270

275

275

275

280

275

275

275

280

270

270

270

270

270

270

765

765

765

770

25

°C

100

110

110

110

110

110

110

110

110

110

97.0

98.0

97.0

98.0

100

110

640

640

640

640

85

°C

340

340

350

350

350

350

350

350

350

350

340

340

340

340

340

340

850

850

850

850

Max

(1)

105

°C

125

°C

600

600

610

610

610

610

610

610

610

610

600

600

600

600

600

1100

1100

1100

600 1100

1100 1600

1100 1600

1200 1600

1200 1600

1100

1100

1100

1100

1100

1100

1100

1100

1100

1100

1100

1100

Unit

µA

Table 32. Current consumption in Standby mode

Typ

Symbol Parameter Conditions V

DD

I

DD(Standby)

Supply current in

Standby mode

All clocks off

IWDG enabled and clocked by

LSI

2 V

2.4 V

3 V

3.6 V

2 V

2.4 V

3 V

3.6 V

1. Evaluated by characterization – Not tested in production.

25

°C

6.75

7.05

7.45

7.90

7.30

7.65

8.10

8.60

85

°C

7.70

8.00

8.45

8.95

8.35

8.65

9.20

9.75

105

°C

8.55

8.85

9.45

10.0

9.20

9.60

10.0

11.0

125

°C

10.5

11.0

12.0

12.5

11.5

11.5

12.5

13.5

25

°C

7.50

7.70

8.20

8.70

8.10

8.30

8.90

9.50

Symbol

I

DD(Shutdown)

Parameter Conditions

Supply current in

Shutdown mode

All clocks off

V

DD

Table 33. Current consumption in Shutdown mode

Typ

25 °C 85 °C 105 °C 125 °C 25 °C

2 V

2.4 V

3.0 V

3.6 V

9.00

13.0

19.0

31.0

290

320

375

460

835

915

1050

1250

2350

2550

2900

3350

55

62

72

95

1. Evaluated by characterization – Not tested in production.

85

°C

8.90

9.10

9.70

11.0

9.50

9.80

11.0

12.0

Max

(1)

105

°C

11.0

11.0

12.0

13.0

12.0

12.0

13.0

14.0

85 °C

920

970

1200

1400

Max

(1)

105 °C

2700

2900

3300

3800

125 °C

7600

7900

8900

11000

125

°C

16.0

17.0

18.0

20.0

17.0

17.0

19.0

21.0

Unit

µA

Unit nA

STM32C011x4/x6 Electrical characteristics

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in

Table 49: I/O static characteristics

.

For the output pins, any external pull-down or external load must also be considered to estimate the current consumption.

Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs.

Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode.

I/O dynamic current consumption

In addition to the internal peripheral current consumption measured previously (see

Table 34: Current consumption of peripherals

), the I/Os used by an application also contribute to the current consumption. When an I/O pin switches, it uses the current from the I/O supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin:

I

SW

= V

DDIO1

×

f

SW

×

C where

I

SW

is the current sunk by a switching I/O to charge/discharge the capacitive load

V

DDIO1

is the I/O supply voltage f

SW

is the I/O switching frequency

C is the total capacitance seen by the I/O pin: C = C

INT

+ C

EXT

+ C

S

C

S

is the PCB board capacitance including the pad pin.

The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency.

DS13866 Rev 3 49/94

79

Electrical characteristics STM32C011x4/x6

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in the following table. The MCU is placed under the following conditions:

• All I/O pins are in Analog mode

• The given value is calculated by measuring the difference of the current consumptions:

– when the peripheral is clocked on

– when the peripheral is clocked off

•

Ambient operating temperature and supply voltage conditions summarized in Table 20:

Voltage characteristics

• The power consumption of the digital part of the on-chip peripherals is given in the following table. The power consumption of the analog part of the peripherals (where applicable) is indicated in each related section of the datasheet.

IOPORT bus

GPIOA

GPIOB

GPIOC

GPIOF

Bus matrix

All AHB peripherals

DMA1

FLASH

SRAM1

CRC1

All APB peripherals

AHB to APB bridge (2)

TIM3

RTCAPB

WWDG1

USART2

I2C1

I2C1 independent clock domain

DBGMCU1

PWR

SYSCFG

TIM1

Table 34. Current consumption of peripherals

Peripheral Bus

IOPORT

AHB

APB

Consumption in

µA/MHz

0.01

0.48

30.76

0.32

3.66

1.13

0.72

1.64

1.64

0.82

0.74

0.31

8

2.64

4.56

0.48

2.01

3.44

2.59

0.09

0.3

0.4

5.84

50/94 DS13866 Rev 3

STM32C011x4/x6 Electrical characteristics

Table 34. Current consumption of peripherals (continued)

Peripheral Bus

Consumption in

µA/MHz

SPI1

SPI1 independent clock domain

USART1

USART1 independent clock domain

TIM14

TIM16

TIM17

ADC1

ADC1 independent clock domain

All peripherals

APB

3.18

1.44

2.22

5.77

1.42

2.54

2.45

1.92

0.12

43.56

5.3.6 Wakeup time from low-power modes and voltage scaling transition times

The wakeup times given in

Table 35 are the latency between the event and the execution of

the first user instruction.

Symbol t

WUSLEEP

Parameter

Table 35. Low-power mode wakeup times (1)

Conditions

Wakeup time from

Sleep to Run mode

HCLK = HSI48/4 =

12 MHz

Transiting to Run-mode execution in flash memory powered during Sleep mode

Transiting to Run-mode execution in flash memory not powered during

Sleep mode t

WULPSTOP t t

WUSTBY

WUSHDN

Wakeup time from

Stop mode

Wakeup time from

Standby mode

Wakeup time from

Shutdown mode

Clock after wakeup is HCLK =

HSI48/4 = 12 MHz

Transiting to Run-mode execution in flash memory powered during Stop mode

Transiting to Run-mode execution in flash memory not powered during

Stop mode

Transiting to Run-mode execution in

SRAM

Clock after wakeup is HCLK =

HSI48/4 = 12 MHz

Clock after wakeup is HCLK =

HSI48/4 = 12 MHz

Transiting to Run mode

Transiting to Run mode

1. Evaluated by characterization – Not tested in production.

Typ Max Unit

10 12

CPU clock cycles

4.75

5.02

2.7

5.9

2.5

23

3.1

6.4

2.9

35

385 466

µs

µs

DS13866 Rev 3 51/94

79

Electrical characteristics STM32C011x4/x6

High-speed external user clock generated from an external source

In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in Section 5.3.13

. See

Figure 12

for recommended clock input waveform.

Symbol

Table 36. High-speed external user clock characteristics (1)

Parameter f

HSE_ext

V

HSEH

User external clock source frequency

Digital OSC_IN input pin high level voltage

V

HSEL

Digital OSC_IN input pin low level voltage t w(HSEH)/ t w(HSEL)

Digital OSC_IN high or low time

1. Specified by design – Not tested in production.

Conditions

-

-

-

-

Min

-

0.7 V

DD

V

SS

7

Typ

8

-

-

-

Max

48

V

DD

0.3 V

DD

-

Unit

MHz

V ns

Figure 12. High-speed external clock source AC timing diagram tw(HSEH)

VHSEH

VHSEL

90%

10% tr(HSE)

THSE tf(HSE) tw(HSEL) t

MS19214V2

Symbol f

LSE_ext

Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in Section 5.3.13

. See

Figure 13

for recommended clock input waveform.

Table 37. Low-speed external user clock characteristics

(1)

Parameter Conditions Min Typ

User external clock source frequency 32.768

Max

1000

Unit kHz

52/94 DS13866 Rev 3

STM32C011x4/x6 Electrical characteristics

Symbol

Table 37. Low-speed external user clock characteristics (1) (continued)

Parameter

V

LSEH

OSC32_IN input pin high level voltage

V

LSEL t w(LSEH)/ t w(LSEL)

OSC32_IN input pin low level voltage

OSC32_IN high or low time

1. Specified by design – Not tested in production.

Conditions

-

-

-

Min

0.7 V

DDIO1

V

SS

250

Typ

-

-

-

Max

V

DDIO1

0.3 V

DDIO1

-

Unit

V ns

Figure 13. Low-speed external clock source AC timing diagram tw(LSEH)

VLSEH

VLSEL

90%

10% tr(LSE) tw(LSEL) t

TLSE tf(LSE)

Symbol f

OSC_IN

R

F

MS19215V2

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in

Table 38 . In the

application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics

(frequency, package, accuracy).

Table 38. HSE oscillator characteristics

(1)

Parameter Conditions

(2)

Min

Oscillator frequency

Feedback resistor -

4

-

Typ

-

200

Max

48

-

Unit

MHz k Ω

DS13866 Rev 3 53/94

79

Electrical characteristics STM32C011x4/x6

Symbol

Table 38. HSE oscillator characteristics (1) (continued)

Parameter Conditions (2) Min Typ Max Unit

I

DD(HSE)

HSE current consumption

During startup

(3)

V

DD

= 3 V,

Rm = 30 Ω ,

CL = 10 pF@8 MHz

V

DD

= 3 V,

Rm = 45 Ω ,

CL = 10 pF@8 MHz

V

DD

= 3 V,

Rm = 30 Ω ,

CL = 5 pF@48 MHz

-

-

-

-

0.58

0.59

0.89

5.5

-

-

mA

V

DD

= 3 V,

Rm = 30 Ω ,

CL = 10 pF@48 MHz

V

DD

= 3 V,

Rm = 30 Ω ,

CL = 20 pF@48 MHz

-

1.14

1.94

-

-

G m

Maximum critical crystal transconductance

Startup 1.5

mA/V t

SU(HSE)

(4)

Startup time V

DD

is stabilized 2 ms

1. Specified by design – Not tested in production.

2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

3. This consumption level occurs during the first 2/3 of the t

SU(HSE) startup time

4. t

SU(HSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer

Note:

For C

L1

and C

L2

, it is recommended to use high-quality external ceramic capacitors in the

5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match

the requirements of the crystal or resonator (see Figure 14

). C

L1

and C

L2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C

L1

and C

L2

. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing

C

L1

and C

L2

.

For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com

.

54/94 DS13866 Rev 3

STM32C011x4/x6 Electrical characteristics

Figure 14. Typical application with an 8 MHz crystal

Resonator with integrated capacitors

C

L1

OSC_IN

8 MHz resonator

R

EXT

(1) OSC_OUT

C

L2

R

F

Bias controlled gain f

HSE

MS19876V1

1. R

EXT

value depends on the crystal characteristics.

Low-speed external clock generated from a crystal resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in

Table 39 . In the application, the

resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Symbol

Table 39. LSE oscillator characteristics (f

LSE

= 32.768 kHz)

(1)

Parameter Conditions

(2)

Min Typ Max Unit

I

DD(LSE)

LSE current consumption

LSEDRV = 0

Medium high drive capability

LSEDRV = 1

High drive capability

-

500

630 -

nA

LSEDRV = 0

Medium high drive capability

1.7

Gm critmax

Maximum critical crystal gm

2.7

µA/V

LSEDRV = 1

High drive capability t

SU(LSE)

(3)

Startup time V

DD

is stabilized 2 -

1. Specified by design – Not tested in production.

2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for

ST microcontrollers”.

3. t

SU(LSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer s

Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com

.

DS13866 Rev 3 55/94

79

Electrical characteristics STM32C011x4/x6

Figure 15. Typical application with a 32.768 kHz crystal

Resonator with integrated capacitors

C

L1

OSC32_IN f

LSE

32.768 kHz resonator

Drive programmable amplifier

OSC32_OUT

C

L2

Note:

MS30253V2

An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one.

5.3.8 Internal clock source characteristics

The parameters given in

Table 40 are derived from tests performed under ambient

temperature and supply voltage conditions summarized in Table 23: General operating conditions

. The provided curves are characterization results, not tested in production.

High-speed internal (HSI48) RC oscillator

Symbol

Table 40. HSI48 oscillator characteristics

Parameter Conditions Min

∆ f

HSI48

Temp(HSI)

TRIM

(1)

(1)

HSI48 Frequency

HSI48 oscillator frequency drift over temperature and

V

DD

full voltage range

HSI48 oscillator frequency user trimming step t

I t

D

HSI48

(2) su(HSI48)

(2) stab(HSI48)

(2)

DD(HSI48)

(1)

Duty cycle

HSI48 oscillator start-up time

HSI48 oscillator stabilization time

HSI48 oscillator power consumption

1. Based on characterization results, not tested in production

2. Specified by design – Not tested in production.

V

DD

=3.0 V, T

A

=30 °C 47.92

T

A

= 0 to 85 °C -1

-2.5

T

A

= -40 to 125 °C

From code 127 to

128

From code 63 to 64

From code 191 to

192

-

For all other code increments

at 1% of target frequency

-8

-5.8

0.2

45

-

-

-

Typ

-

-

-

-6

-3.8

0.3

-

1.4

1.5

525

0.4

55

1.8

3.6

Max

48.40

1

2

-4

-1.8

570

Unit

MHz

%

%

%

μ A

%

μ s

μ s

56/94 DS13866 Rev 3

STM32C011x4/x6

Figure 16. HSI48 frequency versus temperature

Electrical characteristics

Temperature

MS55839V1

Low-speed internal (LSI) RC oscillator

Symbol

Table 41. LSI oscillator characteristics

Parameter Conditions

V

DD

= 3.3 V, T

A

= 25 °C f

LSI

LSI frequency

V

DD

= 2 V to 3.6 V, T

A

= -40 to 125 °C t t

SU(LSI)

(2)

STAB(LSI)

(2)

I

DD(LSI)

(2)

LSI oscillator start-up time -

LSI oscillator stabilization time 5% of final frequency

LSI oscillator power consumption

-

1. Evaluated by characterization – Not tested in production.

2. Specified by design – Not tested in production.

Min Typ Max Unit

31.04

32 32.96

29.5

(1)

-

34 (1)

kHz

-

80 130 μ s

125 180 μ s

110 180 nA

Symbol t prog t prog_row t prog_page t

ERASE

Table 42. Flash memory characteristics (1)

Parameter Conditions Min

Word programming time

Row (32 double word) programming time

Page (2 Kbyte) programming time

Page (2 Kbyte) erase time

64 bits

Normal programming

Fast programming

Normal programming

Fast programming

-

-

-

-

-

-

-

Typ

85.0

2.7

1.7

21.8

13.7

22.0

Max

125.0

4.6

2.8

36.6

22.4

40.0

Unit

µs ms

DS13866 Rev 3 57/94

79

Electrical characteristics

Symbol

Table 42. Flash memory characteristics (1) (continued)

Parameter Conditions Min

I

I t prog_bank t

ME

DD(FlashA)

DD(FlashP)

Bank (32 Kbyte

(2) programming time

Mass erase time

)

Average consumption from

V

DD

Maximum current (peak)

Normal programming

Fast programming

Programming

-

Page erase

Mass erase

Programming, 2 µs peak duration

Erase, 41 µs peak duration

1. Specified by design – Not tested in production.

2. Values provided also apply to devices with less flash memory than one 32 Kbyte bank

-

-

-

-

-

-

-

-

Typ

7.0

7.0

0.4

0.2

22.1

3.0

3.0

5.0

STM32C011x4/x6

Max

0.6

0.4

40.1

-

-

-

-

-

Unit s ms mA mA

Symbol

Table 43. Flash memory endurance and data retention

Parameter Conditions

N t

END

RET

Endurance

Data retention

T

J

= -40 to +130 °C

1 kcycle

(2)

at T

A

= 85 °C

1 kcycle

(2) at T

A

= 105 °C

1 kcycle

(2)

at T

A

= 125 °C

10 kcycles

(2)

at T

A

= 55 °C

10 kcycles

(2)

at T

A

= 85 °C

10 kcycles

(2)

at T

A

= 105 °C

1. Evaluated by characterization – Not tested in production..

2. Cycling performed over the whole temperature range.

Min

(1)

10

30

15

7

30

15

10

Unit kcycles

Years

58/94 DS13866 Rev 3

STM32C011x4/x6 Electrical characteristics

Symbol

V

FESD

V

EFTB

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

• FTB : A Burst of Fast Transient voltage (positive and negative) is applied to V

V

SS

through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard.

DD

and

A device reset allows normal operations to be resumed.

The test results are given in Table 44

. They are based on the EMS levels and classes defined in application note AN1709.

Table 44. EMS characteristics

Parameter Conditions

Level/

Class

Voltage limits to be applied on any I/O pin to induce a functional disturbance f

V

DD

= 3.3 V, T

A

HCLK

= +25 °C,

= 48 MHz, LQFP48, conforming to IEC 61000-4-2

Fast transient voltage burst limits to be applied through 100 pF on V

DD functional disturbance

and V

SS pins to induce a f

V

DD

= 3.3 V, T

A

HCLK

= +25 °C,

= 48 MHz, LQFP48, conforming to IEC 61000-4-2

2B

4B

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

• corrupted program counter

• unexpected reset

• critical data corruption (for example control registers)

DS13866 Rev 3 59/94

79

Electrical characteristics STM32C011x4/x6

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with

IEC 61967-2 standard which specifies the test board and the pin loading.

S

EMI

Symbol Parameter

Table 45. EMI characteristics

Max vs.

[f

HSE

/f

CPU

]

Conditions

Monitored frequency band

Peak level

V

DD

= 3.6 V, T

A

= 25 °C,

LQFP48 package compliant with IEC

61967-2

0.1 MHz to 30 MHz

30 MHz to 130 MHz

130 MHz to 1 GHz

1 GHz to 2 GHz

EMI level

48 MHz /

48 MHz

1

7

3

5

2

Max vs.

[f

HSI

/f

CPU

]

48 MHz /

48 MHz

-1

8

3

-2

2

Unit dBµV

-

Symbol

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the ANSI/JEDEC standard.

Ratings

Table 46. ESD absolute maximum ratings

Conditions Package Class

Maximum value

(1)

Unit

V

V

ESD(HBM)

ESD(CDM)

Electrostatic discharge voltage

(human body model)

Electrostatic discharge voltage

(charge device model)

T

A

= +25 °C, conforming to

ANSI/ESDA/JEDEC JS-001

T

A

= +25 °C, conforming to

ANSI/ESDA/JEDEC JS-002

1. Evaluated by characterization – Not tested in production.

All 1C

All C2a

-2000/+1500

500

V

60/94 DS13866 Rev 3

STM32C011x4/x6 Electrical characteristics

Symbol

LU

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up performance:

• A supply overvoltage is applied to each power supply pin.

• A current is injected to each input, output and configurable I/O pin.

These tests are compliant with EIA/JESD 78A IC latch-up standard.

Parameter

Static latch-up class

Table 47. Electrical sensitivity

Conditions

T

A

= +125 °C conforming to JESD78

Class

II Level A

As a general rule, current injection to the I/O pins, due to external voltage below V

SS above V

DDIO1 product operation. However, in order to give an indication of the robustness of the

or

(for standard, 3.3 V-capable I/O pins) should be avoided during normal microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out-of-range parameter: ADC error above a certain limit

(higher than 5 LSB TUE), induced leakage current on adjacent pins out of conventional limits (-5 µA/+0 µA range) or other functional failure (for example reset occurrence or oscillator frequency deviation).

Negative induced leakage current is caused by negative injection and positive induced leakage current is caused by positive injection.

Symbol

Table 48. I/O current injection susceptibility (1)

Functional susceptibility

Description

Negative injection

Positive injection

I

INJ

(2)

Injected current on pin

Any IO 5

1. Evaluated by characterization – Not tested in production.

2. The injection current value is applicable when the switchable diode is activated, NA when not activated.

NA

Unit mA

DS13866 Rev 3 61/94

79

Electrical characteristics STM32C011x4/x6

General input/output characteristics

Unless otherwise specified, the parameters given in

Table 49 are derived from tests

performed under the conditions summarized in Table 23: General operating conditions

. All

I/Os are designed as CMOS- and TTL-compliant.

Symbol

V

IL

(1)

V

IH

(1)

V hys

(2)

I lkg

(3)

R

PU

Parameter

Table 49. I/O static characteristics

Conditions Min

I/O input low level voltage

I/O input high level voltage

All

All

2 V < V

2 V < V

DDIO1

DDIO1

< 3.6 V

< 3.6 V

-

0.7 x V

I/O input hysteresis -

Input leakage

current

(3)

-

0 < V

IN

≤ V

DDIO1

V

DDIO1

≤ V

IN

≤ V

DDIO1

+1 V

V

DDIO1

+1 V ≤ V

IN

-

-

-

Weak pull-up equivalent resistor

(4)

V

IN

= V

SS

25

DDIO1

Typ

-

-

200

-70

600

150

40

Max

0.3 x V

DDIO1

-

-

-

-

-

55

Unit

V

V mV nA k Ω

R

PD

Weak pull-down equivalent resistor

(4)

V

IN

= V DDIO1 25 40 55

C

IO

I/O pin capacitance 5 -

1. Refer to Figure 17: I/O input characteristics .

2. Specified by design – Not tested in production.

3. This parameter represents the pad leakage of the I/O itself. The total product pad leakage is provided by the following formula: ITotal_Ileak_max = 10 μ A + [number of I/Os where VIN is applied on the pad] ₓ Ilkg(Max).

4. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

PMOS/NMOS contribution to the series resistance is minimal (~10% order).

k Ω pF

62/94 DS13866 Rev 3

STM32C011x4/x6 Electrical characteristics

All I/Os are CMOS- and TTL-compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters, as shown in

Figure 17

.

Figure 17. I/O input characteristics

TTL requirement Vih min = 2V

DDIOx

DDIO x

>1.62

.49xV

DDIO x

+0.26 for V

DDIOx

<1.62 or 0

DDIOx

+0.05 for 1.08<V

DDIOx

<1.62 or 0.39xV

Tested in production CMOS requirement Vih min = 0.7xV

DDIOx

-0.1 for 1.08<V

DDIOx

-0.06 for V

DDIOx

>1.62

TTL requirement Vil max = 0.8V

Based on simulation Vih min = 0.61xV

Based on simulation Vil max =0.43xV

Tested in production CMOS requirement Vil max = 0.3xVdd

MSv37613V1

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±6 mA, and up to

±15 mA with relaxed V

OL

/V

OH

.

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in

Section 5.2

:

• The sum of the currents sourced by all the I/Os on V

DDIO1,

I consumption of the MCU sourced on V

DD,

VDD

(see

Table 20: Voltage characteristics

).

plus the maximum cannot exceed the absolute maximum rating

• The sum of the currents sunk by all the I/Os on V

SS

, plus the maximum consumption of the MCU sunk on V

SS

, cannot exceed the absolute maximum rating I

Voltage characteristics

).

VSS

(see Table 20:

Output voltage levels

Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in

Table 23: General operating conditions . All I/Os are CMOS- and TTL-compliant (FT OR TT

unless otherwise specified).

DS13866 Rev 3 63/94

79

Electrical characteristics STM32C011x4/x6

Symbol

Table 50. Output voltage characteristics (1)

Parameter Conditions Min Max Unit

V

V

V

V

V

V

OL

OH

OL

(3)

OH

(3)

OL

(3)

OH

(3)

Output low level voltage

Output high level voltage

Output low level voltage

Output high level voltage

Output low level voltage

Output high level voltage

CMOS port

|I

IO

| = 8 mA

2.7 V ≤ V

(2)

DD

≤ 3.6 V

TTL port

|I

IO

|

(2)

= 8 mA

2.7 V ≤ V

DD

≤ 3.6 V

All I/Os

|I

IO

| = 20 mA

2.7 V ≤ V

DD

≤ 3.6 V

V

V

DD

2.4

DD

-

- 0.4

-

-

- 1.3

0.4

0.4

-

-

-

1.3

V

OL

(3)

V

OH

(3)

Output low level voltage

Output high level voltage

|I

IO

| = 4 mA

2.7 V ≤ V

DD

≤ 3.6 V

-

V

DD

- 0.45

0.45

-

V Output low level voltage for an FT I/O pin in FM+ mode

|I

IO

| = 20 mA

2.7 V ≤ V

DD

≤ 3.6 V

|I

IO

| = 10 mA

2.7 V ≤ V

DD

≤ 3.6 V

-

0.4

0.4

1. The I

IO

current sourced or sunk by the device must always respect the absolute maximum rating specified in

Table 20:

Voltage characteristics

, and the sum of respect the absolute maximum ratings the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always

∑ I

IO

.

2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

3. Specified by design – Not tested in production.

V

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in

Figure 18

and

Table 51 , respectively.

Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in

Table 23: General operating conditions

.

Speed Symbol

00

Table 51. I/O AC characteristics (1)(2)

Parameter

Fmax Maximum frequency

Tr/Tf Output rise and fall time

(3)

Conditions

C=50 pF, 2.7 V ≤ V

DD

≤ 3.6 V

C=50 pF, 2 V ≤ V

DD

≤ 2.7 V

C=10 pF, 2.7 V ≤ V

DD

≤ 3.6 V

C=10 pF, 2 V ≤ V

DD

≤ 2.7 V

C=50 pF,2.7 V ≤ V

DD

≤ 3.6 V

C=50 pF, 2 V ≤ V

DD

≤ 2.7 V

C=10 pF, 2.7 V ≤ V

DD

≤ 3.6 V

C=10 pF, 2 V ≤ V

DD

≤ 2.7 V

-

-

-

Min

-

-

-

-

-

Max

2

0.35

3.00

0.45

100.00

225.00

75.00

150.00

Unit

MHz ns

64/94 DS13866 Rev 3

STM32C011x4/x6 Electrical characteristics

Table 51. I/O AC characteristics (1)(2) (continued)

Speed Symbol

01

10

11

Fmax

Tr/Tf

Fmax

Tr/Tf

Fmax

Tr/Tf

Parameter

Maximum frequency

Output rise and fall time

Maximum frequency

Output rise and fall time

Maximum frequency

Output rise and fall time

(3)

(3)

(3)

Conditions

C=50 pF, 2.7 V ≤ V

DD

≤ 3.6 V

C=50 pF, 2 V ≤ V

DD

≤ 2.7 V

C=10 pF, 2.7 V ≤ V

DD

≤ 3.6 V

C=10 pF, 2 V ≤ V

DD

≤ 2.7 V

C=50 pF, 2.7 V ≤ V

DD

≤ 3.6 V

C=50 pF, 2 V ≤ V

DD

≤ 2.7 V

C=10 pF, 2.7 V ≤ V

DD

≤ 3.6 V

C=10 pF, 2 V ≤ V

DD

≤ 2.7 V

C=50 pF, 2.7 V ≤ V

DD

≤ 3.6 V

C=50 pF, 2 V ≤ V

DD

≤ 2.7 V

C=10 pF, 2.7 V ≤ V

DD

≤ 3.6 V

C=10 pF, 2 V ≤ V

DD

≤ 2.7 V

C=50 pF, 2.7 V ≤ V

DD

≤ 3.6 V

C=50 pF, 2 V ≤ V

DD

≤ 2.7 V

C=10 pF, 2.7 V ≤ V

DD

≤ 3.6 V

C=10 pF, 2 V ≤ V

DD

≤ 2.7 V

C=30 pF, 2.7 V ≤ V

DD

≤ 3.6 V

C=30 pF, 2 V ≤ V

DD

≤ 2.7 V

C=10 pF, 2.7 V ≤ V

DD

≤ 3.6 V

C=10 pF, 2 V ≤ V

DD

≤ 2.7 V

C=30 pF, 2.7 V ≤ V

DD

≤ 3.6 V

C=30 pF, 2 V ≤ V

DD

≤ 2.7 V

C=10 pF, 2.7 V ≤ V

DD

≤ 3.6 V

C=10 pF, 2 V ≤ V

DD

≤ 2.7 V

Min

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Max

10.00

2.00

15.00

2.50

30.00

60.00

15.00

30.00

30.00

15.00

60.00

4.00

8.00

60.00

(4)

30.00

11.00

22.00

(4)

30.00

80.00

(4)

40.00

5.50

11.00

2.50

5.00

Unit

MHz ns

MHz ns

MHz ns

1. The I/O speed is configured using the OSPEEDRy[1:0] bits. The Fm+ mode is configured in the SYSCFG_CFGR1 register.

Refer to the RM0490 reference manual for a description of GPIO Port configuration register.

2. Specified by design – Not tested in production.

3. The fall time is defined between 70% and 30% of the output waveform, according to I

2

C specification.

4. This value represents the I/O capability but the maximum system frequency is limited to 48 MHz.

DS13866 Rev 3 65/94

79

Electrical characteristics

Figure 18. I/O AC characteristics definition

(1)

90% 10%

50% 50%

10% 90% t

U,2RXW t

I,2RXW

T

STM32C011x4/x6

ZKHQORDGHGE\WKHVSHFLILHGFDSDFLWDQFH

1. Refer to Table 51: I/O AC characteristics .

MS32132V2

The NRST input driver uses CMOS technology. It is connected to a permanent pull-up resistor, R

PU

.

Unless otherwise specified, the parameters given in the following table are derived from tests performed under the ambient temperature and supply voltage conditions summarized in

Table 23: General operating conditions .

Symbol Parameter

Table 52. NRST pin characteristics

Conditions Min Typ Max Unit

V

V

V

IL(NRST)

IH(NRST) hys(NRST)

R

PU

(1)

NRST input low level voltage

NRST input high level voltage

NRST Schmitt trigger voltage hysteresis

Weak pull-up equivalent resistor

(2)

V

F(NRST)

(1)

NRST input filtered pulse

V

NF(NRST)

(1)

NRST input not filtered pulse

-

-

-

V

IN

= V

SS

2.0 V < V

DD

< 3.6 V

2.0 V < V

DD

< 3.6 V

0.7 x V

DD

-

-

25

-

350

-

-

200

40

-

-

0.3 x V

DD

-

-

-

55

70

1. Specified by design – Not tested in production..

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimal (~10% order)

.

V mV k Ω ns ns

66/94 DS13866 Rev 3

STM32C011x4/x6 Electrical characteristics

Figure 19. Recommended NRST pin protection

External reset circuit

(1)

0.1 μF

NRST

(2)

V

DD

R

PU

Filter

Internal reset

MS19878V3

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the V

IL(NRST)

max level specified in

Table 52: NRST pin characteristics

. Otherwise the reset will not be taken into account by the device.

3. The external capacitor on NRST must be placed as close as possible to the device.

Note:

Symbol

V

DDA

V

REF+ f

ADC f s f

TRIG

V

AIN

R

AIN

C

ADC

Unless otherwise specified, the parameters given in Table 53

are preliminary values derived from tests performed under ambient temperature, f

PCLK frequency and V

conditions summarized in Table 23: General operating conditions

.

DDA

supply voltage

It is recommended to perform a calibration after each power-up.

Table 53. ADC characteristics (1)

Conditions Min Typ Max Unit Parameter

Analog supply voltage

Positive reference voltage

ADC clock frequency

-

-

2.0

2

0.14

-

-

3.6

V

DD

35

V

V

MHz

Sampling rate

External trigger frequency

Conversion voltage range

External input impedance

Internal sample and hold capacitor

12 bits

10 bits

8 bits

6 bits f

ADC

= 35 MHz; 12 bits

12 bits

-

-

-

-

-

-

-

-

-

0

-

-

-

-

-

-

-

-

-

5

2.50

2.92

3.50

4.38

2.33

f

ADC

/15

V

REF+

(2)

50

-

MSps

MHz

V k Ω pF

DS13866 Rev 3 67/94

79

Electrical characteristics STM32C011x4/x6

Symbol Parameter

Table 53. ADC characteristics (1) (continued)

Conditions Min Typ Max Unit t

STAB t

CAL t

LATR

ADC power-up time

Calibration time

Trigger conversion latency for regular and injected channels without aborting the conversion

LDO already started f

ADC

= 35 MHz

-

CKMODE = 00

CKMODE = 01

CKMODE = 10

CKMODE = 11

2

2

2.35

82

-

6.5

12.5

3.5

3

Conversion cycle

µs

1/f

ADC

1/f

ADC

1/f

PCLK t s

Sampling time f

ADC

= 35 MHz

0.043

1.5

-

4.59

160.5

µs

1/f

ADC

t

ADCVREG_S

TUP

ADC voltage regulator start-up time

20

µs

t

CONV

Total conversion time

(including sampling time) f

ADC

= 35 MHz

Resolution = 12 bits

Resolution = 12 bits

0.40

4.95

t s

+ 12.5 cycles for successive approximation

= 14 to 173

µs

1/f

ADC t

IDLE

Laps of time allowed between two conversions without rearm

100 µs

I

I

DDA(ADC)

DDV(ADC)

ADC consumption from V

DDA

ADC consumption from V

REF+ f s

= 2.5 MSps f s

= 1 MSps f s

= 10 kSps f s

= 2.5 MSps f s

= 1 MSps f s

= 10 kSps -

-

-

-

-

410

164

17

65

26

0.26

-

-

-

-

-

-

1. Specified by design – Not tested in production.

2.

V

REF+

is internally connected to V

for further details.

DDA

on some packages.Refer to

Section 4: Pinouts, pin description and alternate

µA

µA

68/94 DS13866 Rev 3

STM32C011x4/x6

Resolution

12 bits

10 bits

8 bits

6 bits

12.5

19.5

39.5

79.5

160.5

1.5

39.5

79.5

160.5

1.5

3.5

7.5

3.5

7.5

12.5

19.5

39.5

79.5

160.5

160.5

1.5

3.5

7.5

12.5

19.5

1.5

3.5

7.5

12.5

19.5

39.5

79.5

1. Specified by design – Not tested in production.

Table 54. Maximum ADC R

AIN

.

Sampling cycle at 35 MHz

Sampling time at 35 MHz

[ns]

357

557

1129

2271

4586

43

1129

2271

4586

43

100

214

100

214

357

557

1129

2271

4586

4586

43

100

214

357

557

43

100

214

357

557

1129

2271

Electrical characteristics

Max. R

( Ω )

AIN

(1)

6800

12000

27000

50000

50000

390

22000

39000

50000

82

1500

3900

2200

5600

10000

15000

33000

50000

50000

50000

68

820

3300

5600

10000

50

680

2200

4700

8200

15000

33000

DS13866 Rev 3 69/94

79

Electrical characteristics

Symbol Parameter

Table 55. ADC accuracy (1)(2)

Conditions

ET

EO

EG

ED

EL

ENOB

SINAD

SNR

THD

Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error

Effective number of bits

Signal-to-noise and distortion ratio

Signal-to-noise ratio

Total harmonic distortion

V

DDA f

ADC

= V

REF+

= 3 V

= 35 MHz, f s

≤ 2.5 Msps, T

A

= 25°C

2 V < V f

ADC

DDA

= V

REF+

= 35 MHz, f s

≤

< 3.6 V

2.5 Msps, T

A

= entire range

V

DDA f

ADC

= V

REF+

= 3 V

= 35 MHz, f s

≤ 2.5 Msps, T

A

= 25°C

2 V < V f

ADC

DDA

= V

REF+

= 35 MHz, f s

≤

< 3.6 V

2.5 Msps, T

A

= entire range

V

DDA f

ADC

= V

REF+

= 3 V

= 35 MHz, f s

≤ 2.5 Msps, T

A

= 25 °C

2 V < V f

ADC

DDA

= V

REF+

= 35 MHz, f s

≤

< 3.6 V

2.5 Msps, T

A

= entire range

V

DDA f

ADC

= V

REF+

= 3 V

= 35 MHz, f s

≤ 2.5 Msps, T

A

= 25 °C

2 V < V f

ADC

DDA

= V

REF+

= 35 MHz, f s

≤

< 3.6 V

2.5 Msps, T

A

= entire range

V

DDA f

ADC

= V

REF+

= 3 V

= 35 MHz, f s

≤ 2.5 Msps, T

A

= 25 °C

2 V < V f

ADC

DDA

= V

REF+

= 35 MHz, f s

≤

< 3.6 V

2.5 Msps, T

A

= entire range

V

DDA f

ADC

= V

REF+

= 3 V

= 35 MHz, f s

≤ 2.5 Msps, T

A

= 25 °C

2 V < V f

ADC

DDA

= V

REF+

= 35 MHz, f s

≤

< 3.6 V

2.5 Msps, T

A

= entire range

V

DDA f

ADC

= V

REF+

= 3 V

= 35 MHz, f s

≤ 2.5 Msps, T

A

= 25 °C

2 V < V f

ADC

DDA

= V

REF+

= 35 MHz, f s

≤

< 3.6 V

2.5 Msps, T

A

= entire range

V

DDA f

ADC

= V

REF+

= 3 V

= 35 MHz, f s

≤ 2.5 Msps, T

A

= 25 °C

2 V < V f

ADC

DDA

= V

REF+

= 35 MHz, f s

≤

< 3.6 V

2.5 Msps, T

A

= entire range

V

DDA f

ADC

= V

REF+

= 3 V

= 35 MHz, f s

≤ 2.5 Msps, T

A

= 25 °C

2 V < V f

ADC

DDA

= V

REF+

= 35 MHz, f s

≤

< 3.6 V

2.5 Msps, T

A

= entire range

1. Evaluated by characterization – Not tested in production.

2. ADC DC accuracy values are measured after internal calibration.

STM32C011x4/x6

Min Typ Max Unit

±3 ±4

±3 ±6.5

-

-

±1.5

±2

±1.5

±4.5

±3 ±3.5

LSB

±3 ±5

±1.2

±1.5

±1.2

±1.5

±2.5

±3

±2.5

±3

-

-

10.1 10.2

-

9.6

10.2

-

62.5

63

59.5

63

63

60

64

64 -

-

-

bit dB dB

-74 -73

-74 -70 dB

70/94 DS13866 Rev 3

STM32C011x4/x6

Output code

2 n

-1

2 n

-2

2 n

-3

5

4

7

6

3

2

1

0

V

SSA

E

O

Electrical characteristics

Figure 20. ADC accuracy characteristics

[1LSB =

V

REF+

2 n

V

DDA

(or )]

2 n

E

G

E

T

E

L

E

D

1 LSB ideal

(2)

(3)

(1)

(1) Example of an actual transfer curve

(2) Ideal transfer curve

(3) End-point correlation line n = ADC resolution

E

T

= total unadjusted error: maximum deviation between the actual and ideal transfer curves

E

O

= offset error: maximum deviation between the first actual transition and the first ideal one

E

G

= gain error: deviation between the last ideal transition and the last actual one

E

D

= differential linearity error: maximum deviation between actual steps and the ideal one

E

L

= integral linearity error: maximum deviation between any actual transition and the end point correlation line

V

REF+

(V

DDA

)

MSv19880V6

Figure 21. Typical connection diagram using the ADC

V

DDA

(4)

V

REF+

(4)

Sample-and-hold ADC converter

R

AIN

(1)

I/O analog switch R

ADC

Converter

V

AIN

C parasitic

(2)

I lkg

(3) C

ADC

Sampling switch with multiplexing

V

SS

V

SS

V

SSA

MSv67871V3

1. Refer to Table 53: ADC characteristics

for the values of R

AIN

and C

ADC

.

2. C parasitic

represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

Table 49: I/O static characteristics for the value of the pad capacitance). A high

C parasitic

value will downgrade conversion accuracy. To remedy this, f

ADC

should be reduced.

3. Refer to Table 49: I/O static characteristics for the values of I

lkg

.

4. Refer to Figure 2: Power supply overview .

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 9: Power supply scheme

.

The 100 nF capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip.

DS13866 Rev 3 71/94

79

Electrical characteristics

5.3.16 Temperature sensor characteristics

Symbol

T

L

(1)

Avg_Slope

(2)

V

30

(3)

V

SENSE

Table 56. TS characteristics

Parameter linearity with temperature

Average slope from V

SENSE

Voltage at 30°C (±5 °C)

voltage t

START(TS_BUF)

(1)

Sensor Buffer Start-up time in continuous mode

Min

-

2.4

0.742

t

START

(1)

Start-up time when entering in continuous mode 8 t

S_temp

(1)

ADC sampling time when reading the temperature 5 i sens

(1)

Temperature sensor consumption from VDD, when selected by ADC

4.7

1. Specified by design – Not tested in production.

2. Evaluated by characterization – Not tested in production.

3. Measured at V

DDA

= 3.3 V ±10 mV. The V

30

ADC conversion result is stored in the TS_CAL1 byte.

Typ

±1

2.53

0.76

8

STM32C011x4/x6

Max

±5

2.65

0.786

15

120

-

7.0

Unit

°C mV/°C

V

µs

µA

The parameters given in the following tables are guaranteed by design. Refer to

Section 5.3.13: I/O port characteristics

for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output).

Symbol Parameter

Table 57. TIMx (1) (2) characteristics

Conditions t t t res(TIM) f

EXT

Res

TIM

COUNTER

MAX_COUNT

-

Timer resolution time f

TIMxCLK

= 48 MHz

Timer external clock frequency on CH1 to CH4

Timer resolution TIMx

-

16-bit counter clock period

Maximum possible count with

16-bit counter

-

1. TIMx

, is used as a general term to refer to the TIM1 and TIM17 timers.

2. Specified by design – Not tested in production.

Min

1

20.833

0

-

1

-

Max

-

f

TIMxCLK

/4

16

65536

65536

Unit t

TIMxCLK ns

MHz bit t

TIMxCLK t

TIMxCLK

72/94 DS13866 Rev 3

STM32C011x4/x6 Electrical characteristics

Table 58. IWDG min/max timeout period at 32 kHz LSI clock (1)

Prescaler divider PR[2:0] bits Min timeout RL[11:0]= 0x000 Max timeout RL[11:0]= 0xFFF

/4

/8

/16

/32

/64

/128

/256

0

1

2

3

4

5

6 or 7

0.125

0.250

0.500

1.0

2.0

4.0

8.0

512

1024

2048

4096

8192

16384

32768

1. The exact timings further depend on the phase of the APB interface clock versus the LSI clock, which causes an uncertainty of one RC period.

Unit ms

Symbol f

I2CCLK(min)

I

2

C-bus interface characteristics

The I 2 C-bus interface meets timing requirements of the I 2 C-bus specification and user manual rev. 03 for:

• Standard-mode (Sm): with a bit rate up to 100 kbit/s

• Fast-mode (Fm): with a bit rate up to 400 kbit/s

• Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.

The timings are guaranteed by design as long as the I2C peripheral is properly configured

(refer to the reference manual RM0490) and when the I2CCLK frequency is greater than the minimum shown in the following table.

Table 59. Minimum I2CCLK frequency

Parameter Condition

Minimum I2CCLK frequency for correct operation of I2C peripheral

Fast-mode

Fast-mode Plus

Standard-mode

Analog filter enabled

DNF = 0

Analog filter disabled

DNF = 1

Analog filter enabled

DNF = 0

Analog filter disabled

DNF = 1

Typ

2

9

9

19

16

Unit

MHz

The SDA and SCL I/O requirements are met with the following restrictions: the SDA and

SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and V

DDIO1

is disabled, but is still present. Only FT_f I/O pins

DS13866 Rev 3 73/94

79

Electrical characteristics STM32C011x4/x6 support Fm+ low-level output current maximum requirement. Refer to

Section 5.3.13: I/O port characteristics for the I2C I/Os characteristics.

All I2C SDA and SCL I/Os embed an analog filter. Refer to the following table for its characteristics:

Symbol

Table 60. I2C analog filter characteristics (1)

Parameter t

AF

Limiting duration of spikes suppressed by the filter (2)

1. Specified by design – Not tested in production.

2. Spikes shorter than the limiting duration are suppressed.

Min

50

Max

260

Unit ns

SPI/I

2

S characteristics

Unless otherwise specified, the parameters given in

Table 61

for SPI are derived from tests performed under the ambient temperature, f

PCLKx frequency and supply voltage conditions summarized in

Table 23: General operating conditions . The additional general conditions

are:

• OSPEEDRy[1:0] set to 11 (output speed)

• capacitive load C = 30 pF

• measurement points at CMOS levels: 0.5 x V

DD

Refer to Section 5.3.13: I/O port characteristics

for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI).

Symbol Parameter

Table 61. SPI characteristics

(1)

Conditions

f

1/t

SCK c(SCK)

SPI clock frequency

Master mode

2. V < V

DD

< 3.6 V

Master transmitter mode

2. V < V

DD

< 3.6 V

Slave receiver mode

Slave transmitter mode/full duplex

(2)

2.7 V < V

DD

< 3.6 V

Slave transmitter mode/full duplex

(2)

2 V < V

DD

< 3.6 V t su(NSS) t h(NSS) t w(SCKH) t w(SCKL)

NSS setup time

NSS hold time

Slave mode

SCK high and low time Master mode

Min

-

t su(MI) t su(SI)

SCK low time

Data input setup time

Master mode

Master mode

Slave mode

4 * T

PCLK

2 * T

PCLK

T

PCLK

- 1

T

PCLK

- 2

4.5

2

Typ

-

-

-

T

PCLK

T

PCLK

-

-

Max

24

24

24

24

22

-

-

T

PCLK

+ 1

T

PCLK

+ 2

-

-

Unit

MHz ns ns ns ns ns ns

74/94 DS13866 Rev 3

STM32C011x4/x6

First bit OUT t h(SI)

Next bits OUT

Electrical characteristics

Symbol Parameter

Table 61. SPI characteristics (1) (continued)

Conditions Min Typ Max Unit t h(MI) t h(SI)

Data input hold time

Master mode

Slave mode

2

3

-

-

-

ns ns t a(SO)

Data output access time

Slave mode 9 34 ns t dis(SO)

Data output disable time

Slave mode 9 16 ns t v(SO)

Data output valid time

Slave mode

2.7 V < V

DD

< 3.6 V

Slave mode

2 V < V

DD

< 3.6 V

Master mode

-

10

10

16

22 ns t v(MO)

3 5.5

ns t h(SO)

Data output hold time

Slave mode

2 V < V

DD

< 3.6 V

Master mode

8 t h(MO)

1.5

-

1. Evaluated by characterization – Not tested in production.

2. Maximum frequency in Slave transmitter mode is determined by the sum of t having t su(MI)

= 0 while Duty(SCK) = 50% v(SO)

and t su(MI

) which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master ns ns

Figure 22. SPI timing diagram - slave mode and CPHA = 0

NSS input t su(NSS) t w(SCKH) t c(SCK) t r(SCK) t h(NSS)

CPHA=0

CPOL=0

CPHA=0

CPOL=1 t a(SO) t w(SCKL) t v(SO) t h(SO) t f(SCK) t dis(SO)

MISO output Last bit OUT t su(SI)

MOSI input First bit IN Next bits IN Last bit IN

MSv41658V1

DS13866 Rev 3 75/94

79

Electrical characteristics

Figure 23. SPI timing diagram - slave mode and CPHA = 1

STM32C011x4/x6

NSS input t su(NSS) t w(SCKH) t c(SCK) t f(SCK) t h(NSS)

CPHA=1

CPOL=0

CPHA=1

CPOL=1

MISO output

MOSI input t a(SO) t w(SCKL) t v(SO)

First bit OUT t su(SI) t h(SI)

First bit IN t h(SO)

Next bits OUT

Next bits IN t r(SCK) t dis(SO)

Last bit OUT

Last bit IN

MSv41659V1

1. Measurement points are done at CMOS levels: 0.3 V

DD

and 0.7 V

DD

.

Figure 24. SPI timing diagram - master mode

NSS input

High

CPHA=0

CPOL=0

CPHA=0

CPOL=1 tc(SCK)

CPHA=1

CPOL=0

CPHA=1

CPOL=1

MISO

INPUT

MOSI

OUTPUT tsu(MI) tw(SCKH) tw(SCKL)

MSB IN th(MI)

MSB OUT tv(MO)

1. Measurement points are set at CMOS levels: 0.3 V

DD

and 0.7 V

DD

.

BIT6 IN

BIT1 OUT th(MO) tr(SCK) tf(SCK)

LSB IN

LSB OUT ai14136c

76/94 DS13866 Rev 3

STM32C011x4/x6 Electrical characteristics

Symbol Parameter

Table 62. I 2 S characteristics (1)

Conditions f

MCK f

CK t v(WS) t h(WS) t su(WS) t h(WS) t su(SD_MR) t su(SD_SR) t h(SD_MR) t h(SD_SR) t v(SD_ST) t v(SD_MT)

I2S main clock output

I2S clock frequency

WS valid time

WS hold time

WS setup time

WS hold time

Data input setup time

Data input hold time

Data output valid time

-

Master TX

Master RX

Slave TX

Slave RX

Master mode

Master mode

Slave mode

Slave mode

Master receiver

Slave receiver

Master receiver

Slave receiver

Slave transmitter (after enable edge)

Master transmitter (after enable edge) t h(SD_ST)

Slave transmitter (after enable edge)

Data output hold time t h(SD_MT)

Master transmitter (after enable edge)

1. Evaluated by characterization – Not tested in production.

Figure 25. I 2 S slave timing diagram (Philips protocol) tc(CK)

Min

-

-

-

-

-

-

2

3.5

1

5

2.5

1.5

1

-

-

8

2.5

Max

48

12

12

15

48

5

-

-

-

-

-

-

-

19,5

5

-

-

CPOL = 0

Unit

MHz

MHz ns

ns

CPOL = 1

WS input tw(CKH) tw(CKL) th(WS)

SDtransmit

SDreceive tsu(WS)

LSB transmit(2) tsu(SD_SR)

LSB receive(2)

MSB transmit

MSB receive tv(SD_ST)

Bitn transmit th(SD_SR)

Bitn receive th(SD_ST)

LSB receive

MSv39721V1

DS13866 Rev 3 77/94

79

Electrical characteristics STM32C011x4/x6

1. Measurement points are done at CMOS levels: 0.3 V

DDIO1

and 0.7 V

DDIO1

.

2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

Figure 26. I

2

S master timing diagram (Philips protocol)

90%

10% tf(CK) tr(CK) tc(CK)

CPOL = 0

CPOL = 1 tv(WS)

WS output

SDtransmit tw(CKH)

SDreceive tw(CKL) th(WS) tv(SD_MT)

LSB transmit(2) tsu(SD_MR)

LSB receive(2)

MSB transmit

MSB receive

Bitn transmit th(SD_MR)

Bitn receive th(SD_MT)

LSB transmit

LSB receive

MSv39720V1

1. Evaluated by characterization – Not tested in production.

2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

USART characteristics

Unless otherwise specified, the parameters given in

Table 63 for USART are derived from

tests performed under the ambient temperature, f

PCLKx frequency and supply voltage

conditions summarized in Table 23: General operating conditions

. The additional general conditions are:

• OSPEEDRy[1:0] set to 10 (output speed)

• capacitive load C = 30 pF

• measurement points at CMOS levels: 0.5 x V

DD

Refer to Section 5.3.13: I/O port characteristics

for more details on the input/output alternate function characteristics (NSS, CK, TX, and RX for USART).

78/94 DS13866 Rev 3

STM32C011x4/x6 Electrical characteristics t su(NSS) t h(NSS) t w(CKH) t w(CKL) t su(MI) t su(SI) t h(MI) t h(SI)

Symbol f

CK t v(SO) t v(MO) t h(SO) t h(SO)

Parameter

USART clock frequency

NSS setup time

NSS hold time

CK high time

CK low time

Table 63. USART characteristics

Conditions Min

Master mode

Slave receiver mode

Slave transmitter

Slave mode

Slave mode

Master mode

-

-

t ker

+ 1

2

1 / f

CK

- 1

/ 2

Data input setup time

Data input hold time

Data output valid time

Data output hold time

Master mode

Slave mode

Master mode

Slave mode

Slave mode

2.7 V < VDD < 3.6 V

Slave mode

1.6 V < VDD < 3.6 V

Master mode

Slave mode

Master mode

-

9.5

0.5

16

1.5

0

0

-

-

Typ

-

-

-

-

-

1 / f

CK

/ 2

-

-

-

-

1 / f

CK

+ 1

/ 2

-

-

-

-

Max

6.0

16.0

16.0

-

-

12.0

12.0

2.0

-

-

19

13

4

-

-

Unit

MHz ns

DS13866 Rev 3 79/94

79

Package information STM32C011x4/x6

6.1

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com

.

ECOPACK is an ST trademark.

Symbol

A

A1

A2 b c

D

(2)

E

E1

(3) k

L e h

SO8N package information

SO8N is an 8-lead 4.9 x 6 mm plastic small-outline package with 150 mils body width.

Figure 27. SO8N – Outline

K[Û

A2 A c ccc b e

D

0.25 mm

GAUGE PLANE k

8

1

E1 E

A1

L1

L

SO-A_V2

1. Drawing is not to scale.

Min.

-

0.100

1.250

0.280

0.170

4.800

5.800

3.800

-

0.250

0°

0.400

Table 64. SO8N – Mechanical data millimeters

Typ.

-

4.900

6.000

3.900

-

-

-

-

1.270

-

-

-

Max.

1.750

0.250

-

0.480

0.230

5.000

6.200

4.000

-

0.500

8°

1.270

Min.

-

0.0039

0.0492

0.0110

0.0067

0.1890

0.2283

0.1496

-

0.0098

0°

0.0157

inches

(1)

Typ.

-

0.1929

0.2362

0.1535

-

-

-

-

0.0500

-

-

-

Max.

0.0689

0.0098

-

0.0189

0.0091

0.1969

0.2441

0.1575

-

0.0197

8°

0.0500

80/94 DS13866 Rev 3

STM32C011x4/x6 Package information

Table 64. SO8N – Mechanical data (continued) millimeters inches (1)

Symbol

Min.

Typ.

Max.

Min.

L1 ccc

-

-

1.040

-

-

0.100

-

-

1. Values in inches are converted from mm and rounded to four decimal digits.

2. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side

3. Dimension “E1” does not include interlead flash or protrusions.

Interlead flash or protrusions shall not exceed 0.25 mm per side.

Typ.

0.0409

-

Figure 28. SO8N – Footprint example

0.6 (x8)

Max.

-

0.0039

1.27

O7_FP_V1

1. Dimensions are expressed in millimeters.

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks that identify the parts throughout supply chain operations, are not indicated below.

DS13866 Rev 3 81/94

90

Package information

Figure 29. SO8N package marking example

STM32C011x4/x6

32C01146

A Y WW

Date code Product identification(1)

Pin 1 identifier

MS55864V1

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.

82/94 DS13866 Rev 3

STM32C011x4/x6

6.2 WLCSP12 package information

Package information

This WLCSP is a 12-ball, 1.70 x 1.42 mm, 0.35 mm pitch, wafer level chip scale package e2

G F e1

A4

C4

E4

A2

B3

D3

C2

E2

F3

B1

D1

F1

Figure 30. WLCSP12 – Outline

(DETAIL B) e

DETAIL B e

(DETAIL A)

A3

BOTTOM VIEW

A2

A

SIDE VIEW

SIDE VIEW

D

BUMP

4x aaa

E

B1 Orientation ref eee Z

A1

TOP VIEW

Z b (Nx) ccc ddd

Z X Y

Z

SEATING

PLANE

DETAIL A

ROATATED 90

B0EK_WLCSP12_ME_V1

1. Drawing is not to scale.

2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.

3. Primary datum Z and seating plane are defined by the spherical crowns of the bump.

4. Bump position designation per JESD 95-1, SPP-010. The tolerance of position that controls the location of the pattern of balls with respect to datums X and Y. For each ball there is a cylindrical tolerance zone ccc perpendicular to datum Z and located on true position with respect to datums X and Y as defined by e. The axis perpendicular to datum Z of each ball must lie within this tolerance zone.

DS13866 Rev 3 83/94

90

Package information STM32C011x4/x6

Table 65. WLCSP12 – Mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max

A

(2)

A1

A2

A3

(3)

Ø b

(4)

D

E e e1 e2

F

(5)

G

(5)

N aaa bbb ccc

(6) ddd

(7) eee

-

-

-

-

0.21

1.68

1.41

-

-

-

-

-

-

0.17

0.29

0.025

0.24

1.70

1.42

0.35

0.909

0.875

0.409

0.282

0.49

-

-

-

0.27

1.72

1.43

-

-

-

-

-

12

-

-

-

-

0.0083

0.0661

0.0555

-

-

-

-

-

-

0.0067

0.0114

0.0098

0.0094

0.0669

0.0559

0.0138

0.0358

0.0344

0.0161

0.0111

-

-

-

-

-

-

-

-

-

-

0.10

0.10

0.10

0.05

0.05

-

-

-

-

-

-

-

-

-

-

0.0039

0.0039

0.0039

0.0020

0.0020

1. Values in inches are converted from mm and rounded to 4 decimal digits.

2. The maximum total package height is calculated by the RSS method (Root Sum Square) using nominal and tolerances values of A1 and A2.

3. Back side coating. Nominal dimension is rounded to the 3rd decimal place resulting from process capability.

4. Dimension is measured at the maximum bump diameter parallel to primary datum Z.

5. Calculated dimensions are rounded to the 3rd decimal place

6. Bump position designation per JESD 95-1, SPP-010. The tolerance of position that controls the location of the pattern of balls with respect to datums X and Y. For each ball there is a cylindrical tolerance zone ccc perpendicular to datum Z and located on true position with respect to datums X and Y as defined by e. The axis perpendicular to datum Z of each ball must lie within this tolerance zone.

7. The tolerance of position that controls the location of the balls within the matrix with respect to each other.

For each ball there is a cylindrical tolerance zone ddd perpendicular to datum Z and located on true position as defined by e. The axis perpendicular to datum Z of each ball must lie within this tolerance zone.

Each tolerance zone ddd in the array is contained entirely in the respective zone ccc above. The axis of each ball must lie simultaneously in both tolerance zones

0.0193

-

-

-

0.0106

0.0677

0.0563

-

-

-

-

-

84/94 DS13866 Rev 3

STM32C011x4/x6

Figure 31. WLCSP12 – Footprint example

Package information

Dpad

Dsm

BGA_WLCSP_FT_V1

Pitch

Dpad

Dsm

Stencil thickness

Table 66. WLCSP12 – Example of PCB design rules

Dimension Recommended values

0.35 mm

0.200 mm

0.275 mm

0.08 mm

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks that identify the parts throughout supply chain operations, are not indicated below.

Figure 32. WLCSP12 package marking example

Product identification(1)

Pin 1 identifier

3C0

Y WW

Date code

DS13866 Rev 3

MS55865V1

85/94

90

Package information STM32C011x4/x6

Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use.

In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.

TSSOP20 is a 20-lead, 6.5 x 4.4 mm thin small-outline package with 0.65 mm pitch.

Figure 33. TSSOP20 – Outline

D

20

PIN 1

IDENTIFICATION aaa C

A

1

11

10

E1 E

SEATING

PLANE

C e

A2

0.25 mm

GAUGE PLANE

A1 L

L1 k c b

YA_ME_V3

A

A1

A2 b c

D

(2)

E

E1 (3) e

L

L1

1. Drawing is not to scale.

Symbol

Min.

-

0.050

0.800

0.190

0.090

6.400

6.200

4.300

-

0.450

-

Table 67. TSSOP20 – Mechanical data millimeters inches

(1)

Typ.

-

-

1.000

-

-

6.500

6.400

4.400

0.650

0.600

1.000

Max.

1.200

0.150

1.050

0.300

0.200

6.600

6.600

4.500

-

0.750

-

Min.

-

0.0020

0.0315

0.0075

0.0035

0.2520

0.2441

0.1693

-

0.0177

-

Typ.

-

-

0.0394

-

-

0.2559

0.2520

0.1732

0.0256

0.0236

0.0394

Max.

0.0472

0.0059

0.0413

0.0118

0.0079

0.2598

0.2598

0.1772

-

0.0295

-

86/94 DS13866 Rev 3

STM32C011x4/x6 Package information

Table 67. TSSOP20 – Mechanical data (continued) millimeters inches (1)

Symbol

Min.

Typ.

Max.

Min.

Typ.

Max.

k aaa

0°

-

-

-

8°

0.100

0°

-

-

-

8°

0.0039

1. Values in inches are converted from mm and rounded to four decimal digits.

2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm per side.

3. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25 mm per side.

Figure 34. TSSOP20 – Footprint example

0.25

6.25

20 11

1.35

0.25

7.10 4.40

1.35

1 10

0.40

0.65

YA_FP_V1

1. Dimensions are expressed in millimeters.

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks that identify the parts throughout supply chain operations, are not indicated below.

DS13866 Rev 3 87/94

90

Package information

Figure 35. TSSOP20 package marking example

STM32C011x4/x6

Product identification(1)

Pin 1 identifier e3

32C011F4P6

Y WW A

Revision code

6.4

Date code

MS55848V1

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.

UFQFPN20 package information

UFQFPN20 is a 20-lead, 3 x 3 mm, 0.5 mm pitch, ultra-thin fine-pitch quad flat package.

Figure 36. UFQFPN20 – Outline

D

Pin 1 E

L3 b

5

TOP VIEW

D

D1 e

10

L1

L2 e

E1

E

1

L5

20

16

BOTTOM VIEW

15

1. Drawing is not to scale.

A3 ddd

A1

A

SIDE VIEW

A0A5_ME_V4

88/94 DS13866 Rev 3

STM32C011x4/x6 Package information

Table 68. UFQFPN20 – Mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min b e ddd

L1

L2

L3

L5

D

D1

E

E1

A

A1

A3

0.500

0.000

-

2.900

-

2.900

-

0.500

0.300

-

-

0.180

-

-

0.550

0.020

0.152

3.000

2.000

3.000

2.000

0.550

0.350

0.200

0.150

0.250

0.500

-

0.600

0.050

-

3.100

-

3.100

-

0.600

0.400

-

-

0.300

-

0.050

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.0197

0.0118

-

-

0.0071

-

-

0.0197

0.0000

-

0.1142

-

0.1142

-

Typ

0.0217

0.0138

0.0079

0.0059

0.0098

0.0197

-

0.0217

0.0008

0.060

0.1181

0.0790

0.1181

0.0790

Figure 37. UFQFPN20 – Footprint example

Max

0.0236

0.0157

-

-

0.0118

-

0.0020

0.0236

0.0020

-

0.1220

-

0.1220

-

1. Dimensions are expressed in millimeters.

DS13866 Rev 3

A0A5_FP_V2

89/94

90

Package information STM32C011x4/x6

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks that identify the parts throughout supply chain operations, are not indicated below.

Figure 38. UFQFPN20 package marking example

Product identification(1)

C166

Y WW A

Pin 1 identifier

Date code

MS55849V1

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.

90/94 DS13866 Rev 3

STM32C011x4/x6 Ordering information

Example

Device family

STM32 = Arm

®

based 32-bit microcontroller

Product type

C = general-purpose

Device subfamily

011 = STM32C011

Pin count

J = 8

D = 12

F = 20

Flash memory size

4 = 16 Kbytes

6 = 32 Kbytes

STM32 C 011

Package type

U = UFQFPN

Y = WLCSP

P = TSSOP

M = SO ˽ N

Temperature range

6 = -40 to 85°C (105°C junction)

7 = -40 to 105°C (125°C junction)

3 = -40 to 125°C (130°C junction)

Options

TR = tape and reel packing

= tray packing other = 3-character ID incl. custom Flash code and packing information

F 6 P 6 xyy

For a list of available options (memory, package, and so on) or for further information on any aspect of this device, contact your nearest ST sales office.

DS13866 Rev 3 91/94

91

Important security notice

8 Important security notice

92/94

STM32C011x4/x6

The STMicroelectronics group of companies (ST) places a high value on product security, which is why the ST product(s) identified in this documentation may be certified by various security certification bodies and/or may implement our own security measures as set forth herein. However, no level of security certification and/or built-in security measures can guarantee that ST products are resistant to all forms of attacks. As such, it is the responsibility of each of ST's customers to determine if the level of security provided in an

ST product meets the customer needs both in relation to the ST product alone, as well as when combined with other components and/or software for the customer end product or application. In particular, take note that:

• ST products may have been certified by one or more security certification bodies, such as Platform Security Architecture (www.psacertified.org) and/or Security Evaluation standard for IoT Platforms (www.trustcb.com). For details concerning whether the ST product(s) referenced herein have received security certification along with the level and current status of such certification, either visit the relevant certification standards website or go to the relevant product page on www.st.com for the most up to date information. As the status and/or level of security certification for an ST product can change from time to time, customers should re-check security certification status/level as needed. If an ST product is not shown to be certified under a particular security standard, customers should not assume it is certified.

• Certification bodies have the right to evaluate, grant and revoke security certification in relation to ST products. These certification bodies are therefore independently responsible for granting or revoking security certification for an ST product, and ST does not take any responsibility for mistakes, evaluations, assessments, testing, or other activity carried out by the certification body with respect to any ST product.

• Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open standard technologies which may be used in conjunction with an ST product are based on standards which were not developed by ST. ST does not take responsibility for any flaws in such cryptographic algorithms or open technologies or for any methods which have been or may be developed to bypass, decrypt or crack such algorithms or technologies.

• While robust security testing may be done, no level of certification can absolutely guarantee protections against all attacks, including, for example, against advanced attacks which have not been tested for, against new or unidentified forms of attack, or against any form of attack when using an ST product outside of its specification or intended use, or in conjunction with other components or software which are used by customer to create their end product or application. ST is not responsible for resistance against such attacks. As such, regardless of the incorporated security features and/or any information or support that may be provided by ST, each customer is solely responsible for determining if the level of attacks tested for meets their needs, both in relation to the ST product alone and when incorporated into a customer end product or application.

• All security features of ST products (inclusive of any hardware, software, documentation, and the like), including but not limited to any enhanced security features added by ST, are provided on an "AS IS" BASIS. AS SUCH, TO THE EXTENT

PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS

OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF

MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the applicable written and signed contract terms specifically provide otherwise.

DS13866 Rev 3

STM32C011x4/x6 Revision history

Date

30-Mar-2022

14-Sep-2022

9-Dec-2022

Table 69. Document revision history

Revision Changes

1

2

3

Initial release

Fixed typo errors.

Updated:

–

Table 2

,

Table 20 ,

Table 27 ,

Table 28

,

Table 29 ,

Table 30 ,

Table 36

,

Table 40 ,

Table 55

–

Figure 4 ,

Figure 9 ,

Figure 20

,

Figure 21

– title of Figure 3 and Figure 4

DS13866 Rev 3 93/94

93

STM32C011x4/x6

IMPORTANT NOTICE – READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on

ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks . All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2022 STMicroelectronics – All rights reserved

94/94 DS13866 Rev 3