STMicroelectronics STM32F105RB Datasheet

1. Refer to Table 5: Pin definitions

for peripheral availability when the I/O pins are shared by the peripherals required by the application.

2. The SPI2 and SPI3 interfaces give the flexibility to work in either the SPI mode or the I

S audio mode.

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107

Description STM32F105xx, STM32F107xx

The STM32F105xx and STM32F107xx constitute the connectivity line family whose members are fully pin-to-pin, software and feature compatible.

The STM32F105xx and STM32F107xx are a drop-in replacement for the low-density

(STM32F103x4/6), medium-density (STM32F103x8/B) and high-density

(STM32F103xC/D/E) performance line devices, allowing the user to try different memory densities and peripherals providing a greater degree of freedom during the development cycle.

Table 3. STM32F105xx and STM32F107xx family versus STM32F103xx family

(1)

STM32 device

Low-density

STM32F103xx devices

Medium-density

STM32F103xx devices

High-density

STM32F103xx devices

STM32F105xx STM32F107xx

Flash size (KB)

16 32 32 64 128 256 384 512 64 128 256 128 256

RAM size (KB)

6 10 10 20 20 48 64 64 64 64 64 64 64

144 pins

100 pins

64 pins

2 × USARTs

2 × 16-bit timers

1 × SPI, 1 × I 2 C, USB,

CAN,

1 × PWM timer

2 × ADCs

2 × USARTs

2 × 16-bit timers

1 × SPI,

1 × I

USB, CAN,

1 × PWM timer

2 × ADCs

3 × USARTs

3 × 16-bit timers

2 × SPIs,

2 × I 2 Cs, USB,

CAN,

1 × PWM timer

2 × ADCs

5 × USARTs

4 × 16-bit timers,

2 × basic timers, 3 × SPIs,

2 × I 2 Ss, 2 × I2Cs, USB,

CAN, 2 × PWM timers

3 × ADCs, 2 × DACs,

1 × SDIO, FSMC (100- and 144-pin packages (2) )

5 × USARTs,

4 × 16-bit timers,

2 × basic timers,

3 × SPIs,

2 × I

Ss,

2 × I2Cs,

USB OTG FS,

2 × CANs,

1 × PWM timer,

2 × ADCs,

2 × DACs

48 pins

36 pins

5 × USARTs,

4 × 16-bit timers,

2 × basic timers,

3 × SPIs,

2 × I 2 S,

1 × I2C,

USB OTG FS,

2 × CANs,

1 × PWM timer,

2 × ADCs,

2 × DACs,

Ethernet

for peripheral availability when the I/O pins are shared by the peripherals required by the application.

2. Ports F and G are not available in devices delivered in 100-pin packages.

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STM32F105xx, STM32F107xx Description

2.3 Overview

Figure 1. STM32F105xx and STM32F107xx connectivity line block diagram

TRACECLK

TRACED[0: 3 ] as AF

NJTR S T

JTDI

JTCK/ S WCLK

JTM S / S WDIO

JTDO as A F

MII_TXD[ 3 :0]/RMII_TXD[1:0]

MII_TX_CLK/RMII_TX_CLK

MII_TX_EN/RMII_TX_EN

MII_RXD[ 3 :0]/RMII_RXD[1:0]

MII_RX_ER/RMII_RX_ER

MII_RX_CLK/RMII_REF_CLK

MII_RX_DV/RMII_CR S _DV

MII_CR S

MII_COL/RMII_COL

MDC

MDIO

PP S _OUT

S OF

VBU S

8 0 AF

PA[ 15:0]

PB[ 15:0]

PC[15:0]

PD[15:0]

PE[15:0]

4 Channels

4 compl. Channels

BKIN, ETR input as AF

MO S I,MI S O,

S CK,N SS as AF

RX,TX, CT S , RT S ,

CK as AF

16 ADC12_INs common to

ADC1 & ADC2

REF–

REF+

TPIU

S W/JTAG

ETM

Trace/Trig

Cortex-M 3 CPU

F max

: 72 MHz Dbus

S ystem

Ibus

NVIC

GP DMA1

7 channels

GP DMA2

5 channels

Ethernet MAC

10/100

DMA Ethernet

DPRAM 2 KB DPRAM 2 KB

U S B OTG F S

S RAM 1.25 KB

EXT.IT

WKUP

GPIO port C

GPIO port D

GPIO port E

TIM1

S PI1

U S ART1

Temp sensor

12bi t ADC1 IF

12bit ADC2 IF

@VDDA

Flash 256 KB

64 bit

S RAM

64 KB

Reset & clock control

PCLK1

PCLK2

HCLK

FCLK

PLL 3

DDA

RC H S

RC L S

PLL 3

PLL

PLL2

AHB to

APB2

AHB to

APB1

WWDG

TIM6

TIM7

DD1 8

Power

Voltage reg.

3 .

3 V to 1.

8 V

POR

Reset

Int

S upply supervision

POR / PDR

PVD

DDA

XTAL osc

3 -25 MHz

IWDG

S tandby

interface

BAT

XTAL 3 2kHz

RTC

AWU

Bac kup register

Backup interface

TIM2

TIM 3

TIM4

TIM5

U S ART2

U S ART 3

UART4

UART5

2x( 8

S PI2 / I2 S 2

(1)

2x( 8

S PI 3 / I2 S3

I2C1

I2C2 bx CAN1

S RAM 512B bx CAN2

12bit DAC1

12bit DAC 2

@VDDA

= 2 to 3 .6 V

NR S T

DDA

SS A

O S C_IN

O S C_OUT

BAT

=1.

8 V to 3 .6 V

O S C 3 2_IN

O S C 3 2_OUT

TAMPER-RTC/

ALARM/ S ECOND OUT

4 Channels , ETR as AF

4 Channel s, ETR as A F

RX,TX, CT S , RT S ,

CK as AF

RX,TX, CT S , RT S ,

CK as AF

RX,TX as AF

MO S I/ S D, MI S O, MCK,

S CK/CK, N SS /W S as AF

MO S I/ S D, MI S O, MCK,

S CK/CK, N SS /W S as AF

S CL, S DA, S MBA as AF

CAN1_TX as AF

CAN1_RX as AF

CAN2_RX as AF

DAC_OUT1 as AF

DAC_OUT2 as AF ai15411

1. T

= –40 °C to +85 °C (suffix 6, see

Table 62 ) or –40 °C to +105 °C (suffix 7, see Table 62

), junction temperature up to

105 °C or 125 °C, respectively.

2. AF = alternate function on I/O port pin.

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Description

2.3.1

STM32F105xx, STM32F107xx

ARM Cortex-M3 core with embedded Flash and SRAM

The ARM Cortex-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.

The ARM Cortex-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices.

With its embedded ARM core, STM32F105xx and STM32F107xx connectivity line family is compatible with all ARM tools and software.

Figure 1 shows the general block diagram of the device family.

2.3.3

64 to 256 Kbytes of embedded Flash is available for storing programs and data.

CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.

2.3.5

64 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states.

Nested vectored interrupt controller (NVIC)

The STM32F105xx and STM32F107xx connectivity line embeds a nested vectored interrupt controller able to handle up to 67 maskable interrupt channels (not including the 16 interrupt lines of Cortex-M3) and 16 priority levels.

• Closely coupled NVIC gives low latency interrupt processing

• Interrupt entry vector table address passed directly to the core

• Closely coupled NVIC core interface

• Allows early processing of interrupts

• Processing of late arriving higher priority interrupts

• Support for tail-chaining

• Processor state automatically saved

• Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt latency.

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2.3.7

The external interrupt/event controller consists of 20 edge detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 80 GPIOs can be connected to the 16 external interrupt lines.

Clocks and startup

System clock selection is performed on startup, however, the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 3-25 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example with failure of an indirectly used external oscillator).

A single 25 MHz crystal can clock the entire system including the ethernet and USB OTG

FS peripherals. Several prescalers and PLLs allow the configuration of the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the high speed APB domains is 72 MHz. The maximum allowed

frequency of the low speed APB domain is 36 MHz. Refer to Figure 59: USB O44TG FS +

Ethernet solution on page 100 .

The advanced clock controller clocks the core and all peripherals using a single crystal or oscillator. In order to achieve audio class performance, an audio crystal can be used. In this case, the I 2 S master clock can generate all standard sampling frequencies from 8 kHz to

96 kHz with less than 0.5% accuracy error. Refer to

Figure 60: USB OTG FS + I2S (Audio) solution on page 100 .

To configure the PLLs, refer to

Table 63 on page 101

, which provides PLL configurations according to the application type.

At startup, boot pins are used to select one of three boot options:

• Boot from User Flash

• Boot from System Memory

• Boot from embedded SRAM

The boot loader is located in System Memory. It is used to reprogram the Flash memory by using USART1, USART2 (remapped), CAN2 (remapped) or USB OTG FS in device mode

(DFU: device firmware upgrade). For remapped signals refer to Table 5: Pin definitions .

The USART peripheral operates with the internal 8 MHz oscillator (HSI), however the CAN and USB OTG FS can only function if an external 8 MHz, 14.7456 MHz or 25 MHz clock

(HSE) is present.

For full details about the boot loader, refer to AN2606.

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Description STM32F105xx, STM32F107xx

2.3.9 Power supply schemes

• V

= 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.

Provided externally through V

pins.

• V

SSA

, V

DDA

= 2.0 to 3.6 V: external analog power supplies for ADC, Reset blocks, RCs and PLL (minimum voltage to be applied to V

DDA and V

SSA

must be connected to V

and V

SS is 2.4 V when the ADC is used). V

, respectively.

DDA

• V

BAT

= 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when V

is not present.

2.3.10 Power supply supervisor

The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains in reset mode when V

DD external reset circuit.

is below a specified threshold, V

POR/PDR

, without the need for an

The device features an embedded programmable voltage detector (PVD) that monitors the

DDA

power supply and compares it to the V

PVD

threshold. An interrupt can be generated when V higher than the V

PVD

DDA

drops below the V

PVD

threshold and/or when V

DDA

threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

The regulator has three operation modes: main (MR), low power (LPR) and power down.

• MR is used in the nominal regulation mode (Run)

• LPR is used in the Stop modes.

• Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost)

This regulator is always enabled after reset. It is disabled in Standby mode.

The STM32F105xx and STM32F107xx connectivity line supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:

• Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

• Stop mode

Stop mode achieves the lowest power consumption while retaining the content of

SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode.

The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB

OTG FS wakeup.

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STM32F105xx, STM32F107xx Description

Note:

• Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The

PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering

Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs.

The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode.

2.3.13 DMA

The flexible 12-channel general-purpose DMAs (7 channels for DMA1 and 5 channels for

DMA2) are able to manage memory-to-memory, peripheral-to-memory and memory-toperipheral transfers. The two DMA controllers support circular buffer management, removing the need for user code intervention when the controller reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent.

The DMA can be used with the main peripherals: SPI, I

C, USART, general-purpose, basic and advanced control timers TIMx, DAC, I

S and ADC.

In the STM32F107xx, there is a DMA controller dedicated for use with the Ethernet (see

Section 2.3.20: Ethernet MAC interface with dedicated DMA and IEEE 1588 support for

more information).

2.3.14 RTC (real-time clock) and backup registers

The RTC and the backup registers are supplied through a switch that takes power either on

supply when present or through the V

BAT

pin. The backup registers are forty-two 16-bit registers used to store 84 bytes of user application data when V

power is not present.

They are not reset by a system or power reset, and they are not reset when the device wakes up from the Standby mode.

The real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low power RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC has a typical frequency of 40 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation. The RTC features a 32-bit programmable counter for long term measurement using the Compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz.

For more information, refer to AN2604: “ STM32F101xx and STM32F103xx RTC calibration ”, available from www.st.com

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Description STM32F105xx, STM32F107xx

2.3.15 Timers and watchdogs

The STM32F105xx and STM32F107xx devices include an advanced-control timer, four general-purpose timers, two basic timers, two watchdog timers and a SysTick timer.

Table 4 compares the features of the general-purpose and basic timers.

Timer

Counter resolution

TIM1 16-bit

Counter type

Table 4. Timer feature comparison

Prescaler factor

DMA request generation

Capture/compare channels

Complementary outputs

Up, down, up/down

Any integer between 1 and 65536

Yes 4 Yes

TIMx

(TIM2,

TIM3,

TIM4,

TIM5)

16-bit

Up, down, up/down

Any integer between 1 and 65536

Yes 4 No

TIM6,

TIM7

16-bit Up

Any integer between 1 and 65536

Yes 0 No

Advanced-control timer (TIM1)

The advanced control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable inserted dead-times. It can also be seen as a complete general-purpose timer. The 4 independent channels can be used for:

• Input capture

• Output compare

• PWM generation (edge or center-aligned modes)

• One-pulse mode output

If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If configured as the 16-bit PWM generator, it has full modulation capability (0-100%).

The counter can be frozen in debug mode.

Many features are shared with those of the standard TIM timers which have the same architecture. The advanced control timer can therefore work together with the TIM timers via the Timer Link feature for synchronization or event chaining.

General-purpose timers (TIMx)

There are up to 4 synchronizable standard timers (TIM2, TIM3, TIM4 and TIM5) embedded in the STM32F105xx and STM32F107xx connectivity line devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input capture/output compare, PWM or one pulse mode output. This gives up to 16 input captures / output compares / PWMs on the largest packages. They can work together with the Advanced Control timer via the Timer Link feature for synchronization or event chaining.

The counter can be frozen in debug mode.

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STM32F105xx, STM32F107xx Description

Any of the standard timers can be used to generate PWM outputs. Each of the timers has independent DMA request generations.

Basic timers TIM6 and TIM7

These timers are mainly used for DAC trigger generation. They can also be used as a generic 16-bit time base.

Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode.

Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features:

• A 24-bit down counter

• Autoreload capability

• Maskable system interrupt generation when the counter reaches 0.

• Programmable clock source

Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support standard and fast modes.

They support 7/10-bit addressing mode and 7-bit dual addressing mode (as slave). A hardware CRC generation/verification is embedded.

They can be served by DMA and they support SMBus 2.0/PMBus.

The STM32F105xx and STM32F107xx connectivity line embeds three universal synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3) and two universal asynchronous receiver transmitters (UART4 and UART5).

These five interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability.

The USART1 interface is able to communicate at speeds of up to 4.5 Mbit/s. The other available interfaces communicate at up to 2.25 Mbit/s.

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Description STM32F105xx, STM32F107xx

USART1, USART2 and USART3 also provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller except for UART5.

2.3.18 Serial peripheral interface (SPI)

Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC/SDHC

(a)

modes.

All SPIs can be served by the DMA controller.

Two standard I 2 S interfaces (multiplexed with SPI2 and SPI3) are available, that can be operated in master or slave mode. These interfaces can be configured to operate with 16/32 bit resolution, as input or output channels. Audio sampling frequencies from 8 kHz up to

96 kHz are supported. When either or both of the I 2 S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency with less than 0.5% accuracy error owing to the advanced clock controller (see

Section 2.3.7: Clocks and startup ).

Refer to the “Audio frequency precision” tables provided in the “Serial peripheral interface

(SPI)” section of the STM32F10xxx reference manual.

Peripheral not available on STM32F105xx devices.

The STM32F107xx devices provide an IEEE-802.3-2002-compliant media access controller

(MAC) for ethernet LAN communications through an industry-standard media-independent interface (MII) or a reduced media-independent interface (RMII). The STM32F107xx requires an external physical interface device (PHY) to connect to the physical LAN bus

(twisted-pair, fiber, etc.). the PHY is connected to the STM32F107xx MII port using as many as 17 signals (MII) or 9 signals (RMII) and can be clocked using the 25 MHz (MII) or 50 MHz

(RMII) output from the STM32F107xx.

The STM32F107xx includes the following features:

• Supports 10 and 100 Mbit/s rates

• Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM and the descriptors (see the STM32F105xx/STM32F107xx reference manual for details)

• Tagged MAC frame support (VLAN support)

• Half-duplex (CSMA/CD) and full-duplex operation

• MAC control sublayer (control frames) support

20/108 a. SDHC = Secure digital high capacity.

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STM32F105xx, STM32F107xx Description

• 32-bit CRC generation and removal

• Several address filtering modes for physical and multicast address (multicast and group addresses)

• 32-bit status code for each transmitted or received frame

• Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the receive FIFO are both 2 Kbytes, that is 4 Kbytes in total

• Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 with the timestamp comparator connected to the TIM2 trigger input

• Triggers interrupt when system time becomes greater than target time

The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to

1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive

FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one

CAN is used). The 256 bytes of SRAM which are allocated for each CAN (512 bytes in total) are not shared with any other peripheral.

The STM32F105xx and STM32F107xx connectivity line devices embed a USB OTG fullspeed (12 Mb/s) device/host/OTG peripheral with integrated transceivers. The USB OTG

FS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume.

The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are:

• 1.25 KB of SRAM used exclusively by the endpoints (not shared with any other peripheral)

• 4 bidirectional endpoints

• HNP/SNP/IP inside (no need for any external resistor)

• for OTG/Host modes, a power switch is needed in case bus-powered devices are connected

• the SOF output can be used to synchronize the external audio DAC clock in isochronous mode

• in accordance with the USB 2.0 Specification, the supported transfer speeds are:

– in Host mode: full speed and low speed

– in Device mode: full speed

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions. All GPIOs are high currentcapable.

The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers.

I/Os on APB2 with up to 18 MHz toggling speed

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Description STM32F105xx, STM32F107xx

This feature allows the use of a maximum number of peripherals in a given application.

Indeed, alternate functions are available not only on the default pins but also on other specific pins onto which they are remappable. This has the advantage of making board design and port usage much more flexible.

For details refer to

Table 5: Pin definitions ; it shows the list of remappable alternate

functions and the pins onto which they can be remapped. See the STM32F10xxx reference manual for software considerations.

Two 12-bit analog-to-digital converters are embedded into STM32F105xx and

STM32F107xx connectivity line devices and each ADC shares up to 16 external channels, performing conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs.

Additional logic functions embedded in the ADC interface allow:

• Simultaneous sample and hold

• Interleaved sample and hold

• Single shunt

The ADC can be served by the DMA controller.

An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.

The events generated by the standard timers (TIMx) and the advanced-control timer (TIM1) can be internally connected to the ADC start trigger and injection trigger, respectively, to allow the application to synchronize A/D conversion and timers.

The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration.

This dual digital Interface supports the following features:

• two DAC converters: one for each output channel

• 8-bit or 12-bit monotonic output

• left or right data alignment in 12-bit mode

• synchronized update capability

• noise-wave generation

• triangular-wave generation

• dual DAC channel independent or simultaneous conversions

• DMA capability for each channel

• external triggers for conversion

• input voltage reference V

REF+

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Eight DAC trigger inputs are used in the STM32F105xx and STM32F107xx connectivity line family. The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels.

The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 2 V < V

DDA

< 3.6 V. The temperature sensor is internally connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value.

The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.

The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

The ARM

Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the

STM32F10xxx through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. TPA hardware is commercially available from common development tool vendors. It operates with third party debugger software tools.

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Pinouts and pin description

3 Pinouts and pin description

STM32F105xx, STM32F107xx

Figure 2. STM32F105xx and STM32F107xx connectivity line BGA100 ballout top view

1 2 3 4 5 6 7 8 9 10

PC14-

OSC32_IN

PC13-

TAMPER-

RTC

PC15-

OSC32_OUT

VBAT

PE2

PE3

PB9

PB8

PB7

PB6

PB4

PD5

PB3

PD2

PA15 PA14 PA13

PC11 PC10 PA12

C OSC_IN

VSS_5

PE4 PE1 PB5 PD6 PD3 PC12 PA9 PA11

D OSC_OUT VDD_5 PE5 PE0 BOOT0 PD7 PD4 PD0 PA8 PA10

E NRST PC2 PE6 VSS_4 VSS_3 VSS_2 VSS_1 PD1 PC9 PC7

F PC0 PC1 PC3 VDD_4 VDD_3 VDD_2 VDD_1 NC PC8 PC6

G VSSA PA0-WKUP PA4 PC4 PB2 PE10 PE14 PB15 PD11 PD15

H VREF– PA1 PA5 PC5 PE7 PE11 PE15 PB14 PD10 PD14

J VREF+ PA2

K VDDA PA3

PA6 PB0 PE8 PE12 PB10 PB13 PD9 PD13

PA7 PB1 PE9 PE13 PB11 PB12 PD8 PD12

AI14601c

24/108 DocID15274 Rev 10

STM32F105xx, STM32F107xx Pinouts and pin description

Figure 3. STM32F105xx and STM32F107xx connectivity line LQFP100 pinout

6"!4

0#4!-0%224#

0#/3#?).

0#/3#?/54

633?

6$$?

/3#?).

/3#?/54

.234

633!

62%&

6$$!

0!7+50

,1&0

6$$?

633?

DocID15274 Rev 10 25/108

107

Pinouts and pin description STM32F105xx, STM32F107xx

Figure 4. STM32F105xx and STM32F107xx connectivity line LQFP64 pinout s d

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W ϭϰͲK ^ ϯϮͺ/E

W ϭϱͲK ^ ϯϮͺKh d

W ϬͲK^ ͺ/E

W ϭͲK^ ͺKhd

EZ^d

WϬ

Wϭ

WϮ

Wϯ s ^^ s

W ϬͲt< hW

W ϭ

W Ϯ ϵ ϭϬ ϭϭ ϰ ϱ ϭ ϲϰ ϲϯ ϲϮ ϲϭ ϲϬ ϱϵ ϱϴ ϱϳ ϱϲ ϱϱ ϱϰ ϱϯ ϱϮ ϱϭ ϱϬ ϰϵ ϰϴ

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Ϯϵ ϯϬ ϯϭ ϯϮ ϯϳ ϯϲ ϯϱ s ͺϮ s

^^ͺϮ

W ϭϯ

W ϭϮ

W ϭϭ

W ϭϬ

W ϵ

W ϴ

Wϵ

Wϴ

Wϳ

Wϲ

W ϭϱ

W ϭϰ

W ϭϯ

W ϭϮ

26/108 DocID15274 Rev 10

STM32F105xx, STM32F107xx

Pins

Pin name

Pinouts and pin description

Table 5. Pin definitions

Alternate functions

(4)

Main function

(3)

(after reset) Default Remap

C2 10

D2 11

C1 5 12

D1 6 13

E1 7 14

F1 8 15

PE2

PE3

PE4

PE5

I/O

PE6 I/O

BAT

PC13-TAMPER-

RTC

(5)

S -

I/O -

PC14-

OSC32_IN

(5)

PC15-

OSC32_OUT (5)

I/O -

SS_5

DD_5

OSC_IN

OSC_OUT

NRST

PC0

PE2

PE3

PE4

PE5

PE6

BAT

PC13

PC14

PC15

(6)

I -

SS_5

DD_5

OSC_IN

O - OSC_OUT

I/O - NRST

I/O - PC0

F2 9 16 PC1 I/O - PC1

E2 10 17

F3 11 18

G1 12 19

H1 20

J1 21

K1 13 22

PC2

PC3

SSA

REF-

REF+

DDA

I/O -

S -

PC2

PC3

SSA

REF-

REF+

DDA

G2 14 23 PA0-WKUP I/O - PA0

TRACECK

TRACED0

TRACED1

TRACED2

TRACED3

TAMPER-RTC

OSC32_IN

OSC32_OUT

ADC12_IN10

ADC12_IN11/ ETH_MII_MDC/

ETH_RMII_MDC

ADC12_IN12/ ETH_MII_TXD2

ADC12_IN13/

ETH_MII_TX_CLK

WKUP/USART2_CTS

(7)

ADC12_IN0/TIM2_CH1_ETR

TIM5_CH1/

ETH_MII_CRS_WKUP

DocID15274 Rev 10

27/108

107

Pinouts and pin description

Pins

STM32F105xx, STM32F107xx

Table 5. Pin definitions (continued)

Alternate functions

(4)

Pin name

Main function

(3)

(after reset) Default Remap

H2 15 24

J2 16 25

K2 17 26

E4 18 27

F4 19 28

G3 20 29

H3 21 30

J3 22 31

K3 23 32

G4 24 33

H4 25 34

J4 26 35

K4 27 36

G5 28 37

H5 38

J5 39

PC5

PB0

PB1

PB2

PE7

PE8

PA1

PA2

PA3

SS_4

DD_4

PA4

PA5

PA6

PA7

PC4

I/O -

PA1

PA2

PA3

SS_4

DD_4

PA4

PA5

PA6

PA7

PC4

PC5

PB0

PB1

I/O FT PB2/BOOT1

I/O FT PE7

I/O FT PE8

/ ADC12_IN1/

ETH_MII_RX_CLK/

ETH_RMII_REF_CLK

USART2_TX

TIM5_CH3/ADC12_IN2/

TIM2_CH3

/ ETH_MII_MDIO/

ETH_RMII_MDIO

USART2_RX

TIM5_CH4/ADC12_IN3 /

TIM2_CH4

SPI1_NSS

USART2_CK

/ ADC12_IN4

DAC_OUT2 / ADC12_IN5

/ADC12_IN6 /

TIM3_CH1

SPI1_MOSI

/ADC12_IN7 /

TIM3_CH2

ETH_MII_RX_DV (8) /

ETH_RMII_CRS_DV

ADC12_IN14/

ETH_MII_RXD0

(8)

ETH_RMII_RXD0

ADC12_IN15/

ETH_MII_RXD1

(8)

ETH_RMII_RXD1

ADC12_IN8/TIM3_CH3/

ETH_MII_RXD2

(8)

ADC12_IN9/TIM3_CH4

ETH_MII_RXD3

(8)

SPI3_NSS/I2S3_WS

TIM1_BKIN

TIM1_CH1N

TIM1_CH2N

TIM1_CH3N

TIM1_ETR

TIM1_CH1N

28/108 DocID15274 Rev 10

STM32F105xx, STM32F107xx

Pins

Pinouts and pin description

Table 5. Pin definitions (continued)

Alternate functions

(4)

Pin name

Main function

(3)

(after reset) Default Remap

K5 40

G6 41

H6 42

J6 43

K6 44

G7 45

H7 46

J7 29 47

K7 30 48

E7 31 49

F7 32 50

K8 33 51

J8 34 52

H8 35 53

G8 36 54

K9 55

PE9

SS_7

DD_7

PE10

PE11

PE12

PE13

PE14

PE15

PB10

PB11

SS_1

DD_1

PB12

PB13

PB14

PB15

PD8

I/O FT

S -

I/O FT

S -

I/O FT

PE9

PE10

PE11

PE12

PE13

PE14

PE15

PB10

PB11

SS_1

DD_1

PB12

PB13

PB14

PB15

PD8

I2C2_SCL

(8)

/USART3_TX

ETH_MII_RX_ER

I2C2_SDA

(8)

/USART3_RX

ETH_MII_TX_EN/

ETH_RMII_TX_EN

SPI2_NSS

(8)

/I2S2_WS

I2C2_SMBA

(8)

USART3_CK

/ TIM1_BKIN

CAN2_RX/ ETH_MII_TXD0/

ETH_RMII_TXD0

SPI2_SCK

(8)

/ I2S2_CK

USART3_CTS

(8)

TIM1_CH1N/CAN2_TX/

ETH_MII_TXD1/

ETH_RMII_TXD1

SPI2_MISO

(8)

/ TIM1_CH2N /

USART3_RTS

SPI2_MOSI

(8)

/ I2S2_SD

(8)

TIM1_CH3N

TIM1_CH1

TIM1_CH2N

TIM1_CH2

TIM1_CH3N

TIM1_CH3

TIM1_CH4

TIM1_BKIN

TIM2_CH3

TIM2_CH4

USART3_TX/

ETH_MII_RX_DV/

ETH_RMII_CRS_DV

DocID15274 Rev 10 29/108

107

Pinouts and pin description

Pins

STM32F105xx, STM32F107xx

Table 5. Pin definitions (continued)

Alternate functions

(4)

Pin name

Main function

(3)

(after reset) Default Remap

J9 56

H9 57

G9 58

K10 59

J10 60

H10 61

G10 62

F10 37 63

E10 38 64

F9 39 65

E9 40 66

D9 41 67

C9 42 68

D10 43 69

C10 44 70

B10 45 71

A10 46 72

F8 73

E6 47 74

F6 48 75

A9 49 76

PD9

PD10

PD11

PA10

PA11

PA12

PA13

PD12

PD13

PD14

PD15

PC6

PC7

PC8

PC9

PA8

PA9

SS_2

DD_2

PA14

I/O FT

PD9

PD10

PD11

I/O FT PD12 -

I/O FT

PD13

PD14

PD15

PC6

PC7

PC8

PC9

I2S2_MCK/

I2S3_MCK

I/O FT

PA8

PA9

PA10

PA11

PA12

I/O FT JTMS-SWDIO

Not connected

S - V

SS_2

S - V

DD_2

I/O FT JTCK-SWCLK

USART1_CK/OTG_FS_SOF /

TIM1_CH1

(8)

/MCO

USART1_TX

/ TIM1_CH2

OTG_FS_VBUS

USART1_RX

TIM1_CH3

/OTG_FS_ID

USART1_CTS / CAN1_RX /

TIM1_CH4

/OTG_FS_DM

USART1_RTS / OTG_FS_DP /

CAN1_TX

/ TIM1_ETR

PA13

PA14

USART3_RX/

ETH_MII_RXD0/

ETH_RMII_RXD0

USART3_CK/

ETH_MII_RXD1/

ETH_RMII_RXD1

USART3_CTS/

ETH_MII_RXD2

TIM4_CH1 /

USART3_RTS/

ETH_MII_RXD3

TIM4_CH2

TIM4_CH3

TIM4_CH4

TIM3_CH1

TIM3_CH2

TIM3_CH3

TIM3_CH4

30/108 DocID15274 Rev 10

STM32F105xx, STM32F107xx

Pins

Pinouts and pin description

Table 5. Pin definitions (continued)

Alternate functions

(4)

Pin name

Main function

(3)

(after reset) Default Remap

A8 50 77

B9 51 78

B8 52 79

C8 53 80

D8 81

E8 82

B7 54 83

C7 84

D7 85

B6 86

C6 87

D6 88

A7 55 89

A6 56 90

C5 57 91

B5 58 92

A5 59 93

D5 60 94

B4 61 95

A4 62 96

D4 97

C4 98

E5 63 99

F5 64 100

PA15

PC10

PC11

PC12

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PD7

PB3

PB4

PB5

PB6

PB7

BOOT0

PB8

PB9

PE0

PE1

SS_3

DD_3

I/O FT

I/O -

I/O FT

I -

I/O FT

S -

PB6

PB7

BOOT0

PB8

PB9

PE0

PE1

SS_3

DD_3

PC12

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PD7

JTDO

JTDI

PC10

PC11

NJTRST

PB5

SPI3_NSS / I2S3_WS

UART4_TX

TIM2_CH1_ETR / PA15

SPI1_NSS

USART3_TX/

SPI3_SCK/I2S3_CK

UART4_RX

UART5_TX

TIM3_ETR / UART5_RX

USART3_RX/

SPI3_MISO

USART3_CK/

SPI3_MOSI/I2S3_SD

OSC_IN

(9)

OSC_OUT

/CAN1_RX

(9)

/CAN1_TX

USART2_CTS

USART2_RTS

USART2_TX

SPI3_SCK / I2S3_CK

SPI3_MISO

USART2_RX

USART2_CK

PB3 / TRACESWO/

TIM2_CH2 / SPI1_SCK

PB4 / TIM3_CH1/

SPI1_MISO

I2C1_SMBA / SPI3_MOSI /

ETH_MII_PPS_OUT / I2S3_SD

ETH_RMII_PPS_OUT

I2C1_SDA

TIM3_CH2/SPI1_MOSI/

CAN2_RX

USART1_TX/CAN2_TX

USART1_RX

- -

TIM4_CH3 (7)

/ ETH_MII_TXD3 I2C1_SCL/CAN1_RX

TIM4_CH4

The input voltage measurement on a pin of the device is described in Figure 7

I2C1_SDA / CAN1_TX

TIM4_ETR -

DocID15274 Rev 10 31/108

107

Pinouts and pin description STM32F105xx, STM32F107xx

1. I = input, O = output, S = supply, HiZ = high impedance.

2. FT = 5 V tolerant. All I/Os are V

capable.

3. Function availability depends on the chosen device.

4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).

5. PC13, PC14 and PC15 are supplied through the power switch, and so their use in output mode is limited: they can be used only in output 2 MHz mode with a maximum load of 30 pF and only one pin can be put in output mode at a time.

6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the

Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the

STMicroelectronics website: www.st.com

7. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com

8. SPI2/I2S2 and I2C2 are not available when the Ethernet is being used.

9. For the LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100 and BGA100 packages, PD0 and PD1 are available by default, so there is no need for remapping. For more details, refer to Alternate function I/O and debug configuration section in the STM32F10xxx reference manual.

32/108 DocID15274 Rev 10

STM32F105xx, STM32F107xx Memory mapping

The memory map is shown in

Figure 5 .

0xFFFF FFFF

0xE000 0000

0xDFFF FFFF

512-Mbyte

block 7

Cortex-M 3 's internal peripherals

512-Mbyte

block 6

Not used

0xC000 0000

0xBFFF FFFF

512-Mbyte

block 5

Not used

0xB000 0000

0xAFFF FFFF

512-Mbyte

block 4

Not used

0x 8 000 0000

0x7FFF FFFF

512-Mbyte

block 3

Not used

0x6000 0000

0x5FFF FFFF

512-Mbyte

block 2

Peripherals

0x4000 0000

0x 3 FFF FFFF

512-Mbyte

block 1

S RAM

0x2000 0000

0x1FFF FFFF

512-Mbyte

block 0

Code

0x0000 0000

Figure 5. Memory map

AHB

APB2

APB1

S PI 3 /I2 S3

S PI2/I2 S 2

Reserved

IWDG

WWDG

RTC

Reserved

TIM7

TIM6

TIM5

TIM4

TIM 3

TIM2 bxCAN2 bxCAN1

Reserved

I2C2

I2C1

UART5

UART4

U S ART 3

U S ART2

Reserved

U S B OTG F S

Reserved

Ethernet

Reserved

CRC

Reserved

Flash interface

Reserved

RCC

Reserved

DMA2

DMA1

Reserved

U S ART1

Reserved

S PI1

TIM1

ADC2

ADC1

Reserved

Port E

Port D

Port C

Port B

Port A

EXTI

AFIO

Reserved

DAC

PWR

BKP

Reserved

S RAM (aliased by bit-banding)

Option bytes

S ystem memory

Reserved

Flash

Reserved

Aliased to Flash or system memory depending on

BOOT pins

0x 3 FFF FFFF

0x2001 0000

0x2000 FFFF

0x2000 0000

0x1FFF F 8 00 - 0x1FFF FFFF

0x1FFF B000 - 0x1FFF F7FF

0x1FFF AFFF

0x0 8 04 0000

0x0 8 0 3 FFFF

0x0 8 00 0000

0x07FF FFFF

0x0004 0000

0x000 3 FFFF

0x0000 0000

0x5000 0400 - 0x5FFF FFFF

0x5000 0000 - 0x500 3 FFFF

0x400 3 0000 - 0x4FFF FFFF

0x4002 8 000 - 0x4002 9FFF

0x4002 3 400 - 0x4002 7FFF

0x4002 3 000 - 0x4002 33 FF

0x4002 2400 - 0x4002 2FFF

0x4002 2000 - 0x4002 2 3 FF

0x4002 1400 - 0x4002 1FFF

0x4002 1000 - 0x4002 1 3 FF

0x4002 0 8 00 - 0x4002 0FFF

0x4002 0400 - 0x4002 07FF

0x4002 0000 - 0x4002 0 3 FF

0x4001 3 C00 - 0x4001 FFFF

0x4001 38 00 - 0x4001 3 BFF

0x4001 3 400 - 0x4001 3 7FF

0x4001 3 000 - 0x4001 33 FF

0x4001 2C00 - 0x4001 2FFF

0x4001 2 8 00 - 0x4001 2BFF

0x4001 2400 - 0x4001 27FF

0x4001 1C00 - 0x4001 2 3 FF

0x4001 1 8 00 - 0x4001 1BFF

0x4001 1400 - 0x4001 17FF

0x4001 1000 - 0x4001 1 3 FF

0x4001 0C00 - 0x4001 0FFF

0x4001 0 8 00 - 0x4001 0BFF

0x4001 0400 - 0x4001 07FF

0x4001 0000 - 0x4001 3 FFF

0x4000 7 8 00 - 0x4000 FFFF

0x4000 7400 - 0x4000 77FF

0x4000 7000 - 0x4000 7 3 FF

0x4000 6C00 - 0x4000 6FFF

0x4000 6 8 00 - 0x4000 6BFF

0x4000 6400 - 0x4000 67FF

0x4000 5C00 - 0x4000 6 3 FF

0x4000 5 8 00 - 0x4000 5BFF

0x4000 5400 - 0x4000 57FF

0x4000 5000 - 0x4000 5 3 FF

0x4000 4C00 - 0x4000 4FFF

0x4000 4 8 00 - 0x4000 4BFF

0x4000 4400 - 0x4000 47FF

0x4000 4000 - 0x4000 4 3 FF

0x4000 3 C00 - 0x4000 3 FFF

0x4000 38 00 - 0x4000 3 BFF

0x4000 3 400 - 0x4000 3 7FF

0x4000 3 000 - 0x4000 33 FF

0x4000 2C00 - 0x4000 2FFF

0x4000 2 8 00 - 0x4000 2BFF

0x4000 1 8 00 - 0x4000 27FF

0x4000 1400 - 0x4000 17FF

0x4000 1000 - 0x4000 1 3 FF

0x4000 0C00 - 0x4000 0FFF

0x4000 0 8 00 - 0x4000 0BFF

0x4000 0400 - 0x4000 07FF

0x4000 0000 - 0x4000 0 3 FF ai15412b

DocID15274 Rev 10 33/108

107

Electrical characteristics STM32F105xx, STM32F107xx

5.1.1

Unless otherwise specified, all voltages are referenced to V

Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T

A the selected temperature range).

= 25 °C and T

= T

A max (given by

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3 Σ ).

Unless otherwise specified, typical data are based on T

= 25 °C, V

2 V ≤ V tested.

= 3.3 V (for the

≤ 3.6 V voltage range). They are given only as design guidelines and are not

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2 Σ )

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

5.1.5

The loading conditions used for pin parameter measurement are shown in

Figure 6 .

Pin input voltage

Figure 6. Pin loading conditions Figure 7. Pin input voltage

670)[[[SLQ

& S)

06Y9 06Y9

34/108 DocID15274 Rev 10

STM32F105xx, STM32F107xx

5.1.6 Power supply scheme

Figure 8. Power supply scheme

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Electrical characteristics

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Caution: In

Figure 8 , the 4.7 µF capacitor must be connected to V

DD3

Figure 9. Current consumption measurement scheme

,''B9%$7

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9''

9''$

DocID15274 Rev 10 35/108

107

Electrical characteristics

5.2 Absolute maximum ratings

STM32F105xx, STM32F107xx

Stresses above the absolute maximum ratings listed in

Table 6: Voltage characteristics ,

Table 7: Current characteristics , and

Table 8: Thermal characteristics

may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Symbol

Table 6. Voltage characteristics

Ratings Min Max Unit

–V

(2)

External main supply voltage (including V

DDA and V

)

(1)

Input voltage on five volt tolerant pin

Input voltage on any other pin

| Δ V

DDx

| Variations between different V

power pins

SSX

− V

| Variations between all the different ground pins

ESD(HBM)

Electrostatic discharge voltage (human body model)

–0.3

− 0.3

4.0

+ 4.0

4.0

- 50 see

Section 5.3.11:

Absolute maximum ratings

(electrical sensitivity)

1. All main power (V , V

DDA

) and ground (V supply, in the permitted range.

, V

SSA

) pins must always be connected to the external power

2. V

maximum must always be respected. Refer to Table 7: Current characteristics for the maximum

allowed injected current values.

V mV

Symbol

Table 7. Current characteristics

Ratings Max.

Unit

VDD

VSS

Total current into V

DDA power lines (source)

(1)

Total current out of V

SS ground lines (sink)

(1)

Output current sunk by any I/O and control pin

150

INJ(PIN)

(2)

Output current source by any I/Os and control pin

Injected current on five volt tolerant pins

(3)

Injected current on any other pin

(4)

Total injected current (sum of all I/O and control pins)

(5)

−

-5/+0

± 5 mA

Σ I

INJ(PIN)

± 25

1. All main power (V , V

DDA

) and ground (V supply, in the permitted range.

, V

SSA

) pins must always be connected to the external power

2. Negative injection disturbs the analog performance of the device. See Note: on page 76 .

3. Positive injection is not possible on these I/Os. A negative injection is induced by V values.

. I

INJ(PIN)

must

never be exceeded. Refer to Table 6: Voltage characteristics

for the maximum allowed input voltage

4. A positive injection is induced by V

never be exceeded. Refer to

values.

while a negative injection is induced by V

Table 6: Voltage characteristics

. I

for the maximum allowed input voltage

must

5. When several inputs are submitted to a current injection, the maximum Σ I positive and negative injected currents (instantaneous values).

INJ(PIN)

is the absolute sum of the

36/108 DocID15274 Rev 10

STM32F105xx, STM32F107xx

Symbol

STG

Electrical characteristics

Table 8. Thermal characteristics

Ratings

Storage temperature range

Maximum junction temperature

Value

–65 to +150

150

Unit

°C

5.3.1 General operating conditions

Symbol

Table 9. General operating conditions

Parameter Conditions Min Max Unit f f

V f

HCLK

PCLK1

PCLK2

DDA

(1)

Internal AHB clock frequency

Internal APB1 clock frequency

Internal APB2 clock frequency

Standard operating voltage

Analog operating voltage

(ADC not used)

Analog operating voltage

(ADC used)

Backup operating voltage

Must be the same potential as V

(2)

2.4

3.6

MHz

BAT

Power dissipation at T

85 °C for suffix 6 or T

105 °C for suffix 7

(3)

LFBGA100

LQFP100

LQFP64

LQFP100

- 1.8

3.6

500

434

444

434

V mW

Power dissipation at T

85 °C for suffix 6 or T

105 °C for suffix 7

(4)

LQFP64 - 444 mW

Ambient temperature for 6 suffix version

Ambient temperature for 7 suffix version

Junction temperature range

Maximum power dissipation –40

Low power dissipation

(5)

–40 105

Maximum power dissipation –40

Low power dissipation

(5)

105

–40 125

6 suffix version –40 105

7 suffix version –40 125

1. When the ADC is used, refer to Table 52: ADC characteristics .

2. It is recommended to power V between V

and V

DDA

and V

DDA

from the same source. A maximum difference of 300 mV

can be tolerated during power-up and operation.

3. If T

is lower, higher P

values are allowed as long as T

does not exceed T

J max.

4. If T

is lower, higher P

values are allowed as long as T

does not exceed T

J max.

5. In low power dissipation state, T

can be extended to this range as long as T

does not exceed T

J max.

°C

DocID15274 Rev 10 37/108

107

Electrical characteristics STM32F105xx, STM32F107xx

5.3.3

Subject to general operating conditions for T

Symbol t

VDD

Table 10. Operating condition at power-up / power down

Parameter Condition Min Max

rise time rate

fall time rate

20 -

Unit

µs/V

Embedded reset and power control block characteristics

The parameters given in

Table 11

are derived from tests performed under ambient temperature and V

supply voltage conditions summarized in

Table 12 are derived from tests performed under ambient

Table 11. Embedded reset and power control block characteristics

Symbol Parameter Conditions Min Typ Max Unit

PVD

PLS[2:0]=000 (rising edge)

PLS[2:0]=000 (falling edge)

PLS[2:0]=001 (rising edge)

PLS[2:0]=001 (falling edge)

PLS[2:0]=010 (rising edge)

PLS[2:0]=010 (falling edge)

PLS[2:0]=011 (rising edge)

PLS[2:0]=011 (falling edge)

Programmable voltage detector level selection

PLS[2:0]=100 (rising edge)

PLS[2:0]=100 (falling edge)

PLS[2:0]=101 (rising edge)

2.1

2.18

2.08

2.26

2.16

2.19

2.28

2.37

2.09

2.18

2.27

2.28

2.38

2.48

2.18

2.28

2.38

2.48

2.58

2.28

2.38

2.48

2.47

2.58

2.69

2.37

2.48

2.59

2.57

2.68

2.79

PLS[2:0]=101 (falling edge)

PLS[2:0]=110 (rising edge)

PLS[2:0]=110 (falling edge)

2.47

2.66

2.56

2.58

2.78

2.68

2.69

2.9

2.8

PLS[2:0]=111 (rising edge) 2.76

2.88

PLS[2:0]=111 (falling edge) 2.66

2.78

2.9

PVDhyst

(2)

PVD hysteresis - - 100 -

POR/PDR

Power on/power down reset threshold

Falling edge 1.8

(1) 1.88

1.96

Rising edge 1.84

1.92

2.0

PDRhyst

(2)

RSTTEMPO

(2)

PDR hysteresis

Reset temporization

1. The product behavior is guaranteed by design down to the minimum V

POR/PDR

value.

2. Guaranteed by design, not tested in production.

2.5

4.5

V mV

V mV ms

38/108 DocID15274 Rev 10

STM32F105xx, STM32F107xx Electrical characteristics

5.3.5

The parameters given in

temperature and V

supply voltage conditions summarized in

Figure 9: Current consumption measurement scheme

Symbol

Table 12. Embedded internal reference voltage

Parameter Conditions Min Typ Max Unit

REFINT

Internal reference voltage

–40 °C < T

< +105 °C 1.16

1.20

1.26

–40 °C < T

< +85 °C 1.16

1.20

1.24

S_vrefint

(1)

ADC sampling time when reading the internal reference voltage

- -

RERINT

(2)

Internal reference voltage spread over the temperature range

= 3 V ±10 mV -

Coeff

(2)

Temperature coefficient - -

1. Shortest sampling time can be determined in the application by multiple iterations.

2. Guaranteed by design, not tested in production.

5.1

17.1

(2)

100

µs mV ppm/°C

Supply current characteristics

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code.

The current consumption is measured as described in

All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to Dhrystone 2.1 code.

Maximum current consumption

The MCU is placed under the following conditions:

• All I/O pins are in input mode with a static value at V

or V

(no load)

• All peripherals are disabled except when explicitly mentioned

• The Flash memory access time is adjusted to the f

HCLK

frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above)

• Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling)

• When the peripherals are enabled f

PCLK1

= f

HCLK

/2, f

PCLK2

= f

HCLK

The parameters given in

Table 13 , Table 14

and Table 15

are derived from tests performed under ambient temperature and V

supply voltage conditions summarized in

DocID15274 Rev 10 39/108

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Electrical characteristics STM32F105xx, STM32F107xx

Table 13. Maximum current consumption in Run mode, code with data processing running from Flash

Max

(1)

Symbol Parameter Conditions f

HCLK

Unit

= 85 °C T

= 105 °C

72 MHz 68 68.4

External clock

(2)

, all peripherals enabled

48 MHz

36 MHz

24 MHz

16 MHz

Supply current in

Run mode

External clock

, all peripherals disabled

8 MHz

72 MHz

48 MHz

36 MHz

24 MHz

16 MHz

8 MHz

10.2

32.7

20.3

38.7

27.3

20.2

14.8

11.2

6.6

10.8

32.9

25.2

20.6

49.2

38.9

27.9

20.5

15.1

11.7

7.2

1. Based on characterization, not tested in production.

2. External clock is 8 MHz and PLL is on when f

HCLK

> 8 MHz.

Table 14. Maximum current consumption in Run mode, code with data processing running from RAM

Max

(1)

Symbol Parameter Conditions f

HCLK

Unit

= 85 °C T

= 105 °C

Supply current in

Run mode

External clock

(2)

, all peripherals enabled

External clock

, all

peripherals disabled

72 MHz

48 MHz

36 MHz

24 MHz

16 MHz

8 MHz

72 MHz

48 MHz

36 MHz

24 MHz

16 MHz

8 MHz

10.5

31.4

27.8

17.6

65.5

45.4

35.5

25.2

13.1

10.2

6.1

18.5

31.9

28.2

18.3

36.1

25.6

13.8

10.9

7.8

1. Based on characterization, tested in production at V

max, f

HCLK

max..

2. External clock is 8 MHz and PLL is on when f

HCLK

> 8 MHz.

40/108 DocID15274 Rev 10

STM32F105xx, STM32F107xx Electrical characteristics

Table 15. Maximum current consumption in Sleep mode, code running from Flash or RAM

Max

(1)

Symbol Parameter Conditions f

HCLK

Unit

= 85 °C T

= 105 °C

Supply current in

Sleep mode

External clock

(2)

, all peripherals enabled

External clock

, all peripherals disabled

72 MHz

48 MHz

36 MHz

24 MHz

16 MHz

8 MHz

72 MHz

48 MHz

36 MHz

24 MHz

16 MHz

8 MHz

14.2

8.7

10.1

8.3

48.4

33.9

26.7

19.3

7.5

6.6

2.5

14.8

9.1

10.6

8.75

34.4

27.2

19.8

7.1

6.5

3 mA

1. Based on characterization, tested in production at V

DD max and f

HCLK

max with peripherals enabled.

2. External clock is 8 MHz and PLL is on when f

HCLK

> 8 MHz.

Table 16. Typical and maximum current consumptions in Stop and Standby modes

Typ (1) Max

Symbol Parameter Conditions

BAT

= 2.0 V

BAT

= 2.4 V

BAT

= 3.3 V

85 °C

105 °C

Unit

Regulator in Run mode, low-speed and high-speed internal RC oscillators and high-speed oscillator

OFF (no independent watchdog) Supply current in Stop mode Regulator in Low Power mode, lowspeed and high-speed internal RC oscillators and high-speed oscillator

OFF (no independent watchdog)

Low-speed internal RC oscillator and independent watchdog ON

Supply current in Standby mode

Low-speed internal RC oscillator

ON, independent watchdog OFF

Low-speed internal RC oscillator and independent watchdog OFF, lowspeed oscillator and RTC OFF

DD_VBAT

Backup domain supply current

Low-speed oscillator and RTC ON

1. Typical values are measured at T

= 25 °C.

2. Based on characterization, not tested in production.

1.1

2.8

1.9

1.2

3.8

3.6

2.1

1.4

600 1300

590 1280

(2)

2.1

(2)

6.5

(2)

2.3

(2)

µA

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Electrical characteristics STM32F105xx, STM32F107xx

Figure 10. Typical current consumption on V different V

BAT

with RTC on vs. temperature at

values

2.5

1.5

8 V

2 V

2.4 V

3 .

3 V

3 .6 V

0.5

–40 °C 25 °C 70 °C 8 5 °C 105 °C

Temperature (°C) ai17 3 29

Figure 11. Typical current consumption in Stop mode with regulator in Run mode versus temperature at different V

values

900.00

8 00.00

700.00

600.00

500.00

400.00

3 00.00

200.00

100.00

0.00

3 .6 V

3 .

3 V

2.7 V

2.4 V

–40 °C 25 °C 8 5 °C

Temperature (°C)

105 °C ai17122

42/108 DocID15274 Rev 10

STM32F105xx, STM32F107xx Electrical characteristics

Figure 12. Typical current consumption in Stop mode with regulator in Low-power mode versus temperature at different V

values

900.00

8 00.00

700.00

600.00

500.00

400.00

3 00.00

200.00

100.00

0.00

3 .6 V

3 .

3 V

2.7 V

2.4 V

–40 °C 25 °C 8 5 °C

Temperature (°C)

105 °C ai1712 3

Figure 13. Typical current consumption in Standby mode versus temperature at different V

values

4.50

4.00

3 .50

3 .00

2.50

2.00

1.50

1.00

0.50

0.00

3 .6 V

3 .

3 V

2.7 V

2.4 V

–40 °C 25 °C 8 5 °C

Temperature (°C)

105 °C ai17124

Typical current consumption

The MCU is placed under the following conditions:

• All I/O pins are in input mode with a static value at V

or V

(no load).

• All peripherals are disabled except if it is explicitly mentioned.

• The Flash access time is adjusted to f

HCLK

frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above).

• Ambient temperature and V

supply voltage conditions summarized in

Table 19 . The MCU is placed

• Prefetch is ON (Reminder: this bit must be set before clock setting and bus prescaling)

When the peripherals are enabled f

PCLK1

= f

HCLK

/4, f

PCLK

2 = f

HCLK

/2, f

ADCCLK

= f

PCLK2

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Electrical characteristics STM32F105xx, STM32F107xx

Table 17. Typical current consumption in Run mode, code with data processing running from Flash

Typ

(1)

Symbol Parameter Conditions f

HCLK All peripherals enabled

(2)

All peripherals disabled

Unit

Supply current in

Run mode

External clock

(3)

Running on high speed internal RC

(HSI), AHB prescaler used to reduce the frequency

36 MHz

24 MHz

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

125 kHz

72 MHz

48 MHz

36 MHz

24 MHz

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

125 kHz

47.3

24.6

16.8

11.8

5.9

3.7

2.5

1.8

1.5

1.3

23.9

16.1

11.1

5.6

3.1

1.8

1.16

0.8

0.6

1. Typical values are measures at T

= 25 °C, V

= 3.3 V.

2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).

3. External clock is 8 MHz and PLL is on when f

HCLK

> 8 MHz.

14.8

9.7

6.7

3.8

2.1

1.3

0.9

0.67

0.5

28.3

19.6

15.4

10.6

7.4

3.7

2.9

1.53

1.3

1.2

mA mA

44/108 DocID15274 Rev 10

STM32F105xx, STM32F107xx Electrical characteristics

Table 18. Typical current consumption in Sleep mode, code running from Flash or

RAM

Typ

(1)

Symbol Parameter Conditions f

HCLK All peripherals enabled

(2)

All peripherals disabled

Unit

External clock (3)

Supply current in

Sleep mode

1 MHz

500 kHz

125 kHz

36 MHz

24 MHz

16 MHz

Running on high speed internal RC

(HSI), AHB prescaler used to reduce the frequency

8 MHz

4 MHz

2 MHz

1 MHz

72 MHz

48 MHz

36 MHz

24 MHz

16 MHz

8 MHz

4 MHz

2 MHz

28.2

14.7

10.1

6.7

3.2

2.3

1.7

1.5

1.3

1.2

13.7

9.3

6.3

2.7

1.6

0.8

1.3

1.2

1.16

4.2

3.4

2.5

500 kHz

125 kHz

0.6

0.5

0.43

0.42

1. Typical values are measures at T

= 25 °C, V

= 3.3 V.

2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).

3. External clock is 8 MHz and PLL is on when f

HCLK

> 8 MHz.

1.3

0.6

0.5

0.46

0.44

1.1

1.05

2.6

1.8

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in

under the following conditions:

• all I/O pins are in input mode with a static value at V

or V

(no load)

• all peripherals are disabled unless otherwise mentioned

• the given value is calculated by measuring the current consumption

– with all peripherals clocked off

– with one peripheral clocked on (with only the clock applied)

• ambient operating temperature and V

Table 6

supply voltage conditions summarized in

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107

Electrical characteristics STM32F105xx, STM32F107xx

AHB (up to 72 MHz)

APB1(up to 36MHz)

USART2

USART3

UART4

UART5

I2C1

I2C2

CAN1

CAN2

DAC

(3)

WWDG

PWR

BKP

IWDG

DMA1

DMA2

OTG_fs

ETH-MAC

CRC

BusMatrix

(1)

APB1-Bridge

TIM2

TIM3

TIM4

TIM5

TIM6

TIM7

SPI2/I2S2

(2)

SPI3/I2S3

Table 20 result from tests performed using an high-speed

Table 19. Peripheral current consumption

Peripheral Typical consumption at 25 °C

19.44

18.33

8.61

3.33

2.22

0.83

3.89

10.83

11.11

10.83

10.56

11.39

11.11

33.61

33.06

32.50

31.94

6.11

7.50

14.03

9.31

111.11

56.25

1.11

15.97

9.72

Unit

µA/MHz

46/108 DocID15274 Rev 10

STM32F105xx, STM32F107xx Electrical characteristics

Table 19. Peripheral current consumption (continued)

Peripheral Typical consumption at 25 °C Unit

APB2-Bridge

GPIOA

GPIOB

APB2 (up to 72 MHz)

GPIOC

GPIOD

GPIOE

SPI1

USART1

TIM1

ADC1

(4)

3.47

6.39

6.11

6.39

6.11

3.61

12.08

23.47

18.21

µA/MHz

1. The BusMatrix is automatically active when at least one master is ON.(CPU, ETH-MAC, DMA1 or DMA2).

2. When I2S is enabled we have a consumption add equal to 0, 02 mA.

3. When DAC_OUT1 or DAC_OUT2 is enabled we have a consumption add equal to 0, 3 mA.

4. Specific conditions for measuring ADC current consumption: f

HCLK f

HCLK

, f

ADCCLK

= f

APB2

= 56 MHz, f

APB1

= f

HCLK

/2, f

APB2

/4. When ADON bit in the ADC_CR2 register is set to 1, a current consumption of analog part equal to 0.6 mA must be added.

High-speed external user clock generated from an external source

The characteristics given in

external clock source, and under ambient temperature and supply voltage conditions summarized in

Table 21 result from tests performed using an low-speed

Symbol

Table 20. High-speed external user clock characteristics

Parameter f

HSE_ext

External user clock source frequency

(1)

HSEH

HSEL t w(HSE) t w(HSE) t r(HSE) t f(HSE)

C in(HSE)

DuCy

(HSE)

OSC_IN input pin high level voltage

OSC_IN input pin low level voltage

OSC_IN high or low time

OSC_IN rise or fall time

(1)

OSC_IN input capacitance

Duty cycle

(1)

OSC_IN Input leakage current

1. Guaranteed by design, not tested in production.

Conditions

≤ V

Min

0.7V

Typ

- V

- 0.3V

Max Unit

±1

MHz

V ns pF

µA

DocID15274 Rev 10 47/108

107

Electrical characteristics STM32F105xx, STM32F107xx

Low-speed external user clock generated from an external source

The characteristics given in

external clock source, and under ambient temperature and supply voltage conditions summarized in

characterization results obtained with typical external components specified in Table 22

Symbol

Table 21. Low-speed external user clock characteristics

Parameter Conditions f

LSE_ext

LSEH

User External clock source frequency

(1)

OSC32_IN input pin high level voltage

LSEL

OSC32_IN input pin low level voltage

t w(LSE) t w(LSE) t r(LSE) t f(LSE)

C in(LSE)

DuCy

(LSE)

OSC32_IN high or low time

OSC32_IN rise or fall time

(1)

OSC32_IN input capacitance

Duty cycle

(1)

OSC32_IN Input leakage current V

≤ V

1. Guaranteed by design, not tested in production.

Min

0.7V

450

Typ Max Unit

32.768

1000 kHz

0.3V

±1

V ns pF

µA

Figure 14. High-speed external clock source AC timing diagram

+6(+

+6(/

U+6(

+6(

([WHUQDOFORFNVRXUFH

+6(BH[W

26&B,1

:+6(

670)[[[

:+6(

DLF

48/108 DocID15274 Rev 10

STM32F105xx, STM32F107xx Electrical characteristics

Figure 15. Low-speed external clock source AC timing diagram

VLSEH

VLSEL

90%

10% tr(LSE)

TLSE tf(LSE) tW(LSE) tW(LSE) t

Extern a l clock s o u rce fLSE_ext

OSC32_IN

STM32F10xxx a i14140c

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 3 to 25 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on

. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Symbol

Table 22. HSE 3-25 MHz oscillator characteristics (1) (2)

Parameter Conditions Min Typ Max Unit f

OSC_IN

Oscillator frequency

Feedback resistor

- 200

25 MHz

- k Ω

Recommended load capacitance versus equivalent serial resistance of the crystal (R

)

(3)

= 30 Ω - 30 - pF i

HSE driving current

= 3.3 V, V

= V with 30 pF load

- - 1 mA g m t

SU(HSE

(4)

Oscillator transconductance

Startup time

Startup

is stabilized

- mA/V ms

1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

2. Based on characterization, not tested in production.

3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions.

4. t

SU(HSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer

DocID15274 Rev 10 49/108

107

Electrical characteristics STM32F105xx, STM32F107xx

For C

and C

, it is recommended to use high-quality external ceramic capacitors in the

5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see

Figure 16

). C

and C

L2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C

and C

. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing

and C

. Refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com

Figure 16. Typical application with an 8 MHz crystal

5HVRQDWRUZLWK

LQWHJUDWHGFDSDFLWRUV

26&B,1 I+6(

0+ ]

UHVRQDWRU

%LDV

FRQWUROOHG

JDLQ

5(;7

26&B28 7 670)[[[

DLE

1. R

EXT

value depends on the crystal characteristics.

Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on

characterization results obtained with typical external components specified in Table 23

Symbol

(2)

2 g m

Table 23. LSE oscillator characteristics (f

LSE

= 32.768 kHz) (1)

Parameter Conditions Min Typ Max Unit

- 5 - M Ω Feedback resistor

Recommended load capacitance versus equivalent serial resistance of the crystal (R

)

(3)

LSE driving current

Oscillator Transconductance

= 30 k Ω

= 3.3 V, V

= V

15 pF

1.4

µA

- µA/V

50/108 DocID15274 Rev 10

STM32F105xx, STM32F107xx Electrical characteristics

Symbol

Table 23. LSE oscillator characteristics (f

LSE

= 32.768 kHz) (1) (continued)

Parameter Conditions Min Typ Max Unit t

Startup time V

is stabilized

= 50 °C

= 25 °C

= 10 °C

= 0 °C

= -10 °C

= -20 °C

= -30 °C

= -40 °C

1.5

2.5

1. Based on characterization, not tested in production.

2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for

ST microcontrollers”.

3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small R example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details

value for

4. t

SU(LSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer s

Note: For C

and C

L2 it is recommended to use high-quality external ceramic capacitors in the

5 pF to 15 pF range selected to match the requirements of the crystal or resonator (see

Figure 17

). C

and C

L2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C

has the following formula: C

= C

x C

/ ( C

+ C

) + C stray

where

C stray between 2 pF and 7 pF.

and C

Load capacitance C

is the pin capacitance and board or trace PCB-related capacitance. Typically, it is

Caution: To avoid exceeding the maximum value of C

and C to use a resonator with a load capacitance C

L capacitance of 12.5 pF.

(15 pF) it is strongly recommended

≤ 7 pF. Never use a resonator with a load

Example: if you choose a resonator with a load capacitance of C

L then C

= C

= 8 pF.

= 6 pF, and C stray

= 2 pF,

Figure 17. Typical application with a 32.768 kHz crystal

5HVRQDWRUZLWK

LQWHJUDWHGFDSDFLWRUV

.+ ]

UHVRQDWRU

26&B,1

%LDV

FRQWUROOHG

JDLQ

26&B28 7

I/6(

670)[[[

DLE

DocID15274 Rev 10 51/108

107

Electrical characteristics

5.3.7 Internal clock source characteristics

STM32F105xx, STM32F107xx

The parameters given in

Table 24 are derived from tests performed under ambient

temperature and V

supply voltage conditions summarized in

Table 26 is measured on a wakeup phase with a 8-MHz HSI RC

High-speed internal (HSI) RC oscillator

Symbol

Table 24. HSI oscillator characteristics (1)

Parameter Conditions Min Typ Max Unit

I t f

HSI

DuCy

ACC

(HSI)

HSI su(HSI)

(4)

DD(HSI)

(4)

Frequency -

Duty cycle -

Accuracy of the HSI oscillator

User-trimmed with the RCC_CR register (2)

Factorycalibrated (4)

= –40 to 105 °C

= –10 to 85 °C

= 0 to 70 °C

= 25 °C

HSI oscillator startup time

HSI oscillator power consumption

–2

–1.5

–1.3

–1.1

(3)

2.5

2.2

1.8

100

µs

µA

1. V

= 3.3 V, T

= –40 to 105 °C unless otherwise specified.

2. Refer to application note AN2868 “STM32F10xxx internal RC oscillator (HSI) calibration” available from the

ST website www.st.com

3. Guaranteed by design, not tested in production.

4. Based on characterization, not tested in production.

Low-speed internal (LSI) RC oscillator

Symbol

Table 25. LSI oscillator characteristics

(1)

Parameter f

LSI

(2) t su(LSI)

(3)

DD(LSI)

(3)

Frequency

LSI oscillator startup time

LSI oscillator power consumption

1. V

= 3 V, T

= –40 to 105 °C unless otherwise specified.

2. Based on characterization, not tested in production.

3. Guaranteed by design, not tested in production.

Min

Typ

0.65

Max

1.2

Unit kHz

µs

µA

Wakeup time from low-power mode

The wakeup times given in

oscillator. The clock source used to wake up the device depends from the current operating mode:

• Stop or Standby mode: the clock source is the RC oscillator

• Sleep mode: the clock source is the clock that was set before entering Sleep mode.

52/108 DocID15274 Rev 10

STM32F105xx, STM32F107xx

5.3.8

Electrical characteristics

All timings are derived from tests performed under ambient temperature and V

DD voltage conditions summarized in

Table 27 and Table 28 are derived from tests performed under

supply

Symbol

Table 26. Low-power mode wakeup timings

Parameter Typ Unit t

WUSLEEP

(1) Wakeup from Sleep mode 1.8

µs t

WUSTOP

(1)

Wakeup from Stop mode (regulator in run mode)

Wakeup from Stop mode (regulator in low power mode)

3.6

5.4

µs t

WUSTDBY

(1)

Wakeup from Standby mode 50

1. The wakeup times are measured from the wakeup event to the point in which the user application code reads the first instruction.

µs

PLL, PLL2 and PLL3 characteristics

The parameters given in

temperature and V

supply voltage conditions summarized in

Symbol f

PLL_IN f

PLL_OUT f

VCO_OUT t

LOCK

Jitter

Table 27. PLL characteristics

Parameter Min

(1)

PLL input clock

(2)

Pulse width at high level

PLL multiplier output clock

PLL VCO output

PLL lock time

Cycle-to-cycle jitter

Max

(1)

144

350

300

Unit

MHz ns

MHz

µs ps

1. Based on characterization, not tested in production.

2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by f

PLL_OUT

Symbol f

PLL_IN f

PLL_OUT f

VCO_OUT t

LOCK

Jitter

Table 28. PLL2 and PLL3 characteristics

Parameter Min

(1)

PLL input clock

(2)

Pulse width at high level

PLL multiplier output clock

PLL VCO output

PLL lock time

Cycle-to-cycle jitter

Max

(1)

148

350

400

Unit

MHz ns

MHz

µs ps

1. Based on characterization, not tested in production.

2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by f

PLL_OUT

DocID15274 Rev 10 53/108

107

Electrical characteristics STM32F105xx, STM32F107xx

Flash memory

The characteristics are given at T

= – 40 to 105 °C unless otherwise specified.

Symbol

Table 29. Flash memory characteristics

Parameter Conditions t t

I prog

ERASE t

V prog

16-bit programming time T

= –40 to +105 °C

Page (1 KB) erase time T

= –40 to +105 °C

Mass erase time T

= –40 to +105 °C

Read mode f

HCLK

= 72 MHz with 2 wait states, V

= 3.3 V

Supply current

Programming voltage

Write / Erase modes f

HCLK

= 72 MHz, V

= 3.3 V

Power-down mode / Halt,

= 3.0 to 3.6 V

1. Guaranteed by design, not tested in production.

Min

(1)

Typ Max

(1)

52.5

3.6

Unit

µs ms ms mA mA

µA

Symbol

Table 30. Flash memory endurance and data retention

Parameter Conditions

N t

END

RET

Endurance

Data retention

= –40 to +85 °C (6 suffix versions)

= –40 to +105 °C (7 suffix versions)

1 kcycle

(2)

at T

= 85 °C

1 kcycle

at T

= 105 °C

10 kcycles

Unless otherwise specified, the parameters given in Table 36

at T

= 55 °C

1. Based on characterization, not tested in production.

2. Cycling performed over the whole temperature range.

Min

(1)

Typ Max

(1)

Unit

Kcycles

Years

54/108

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

• FTB : A burst of fast transient voltage (positive and negative) is applied to V

and V

SS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard.

DocID15274 Rev 10

STM32F105xx, STM32F107xx Electrical characteristics

A device reset allows normal operations to be resumed.

The test results are given in

Table 31

. They are based on the EMS levels and classes defined in application note AN1709.

Symbol

Table 31. EMS characteristics

Parameter Conditions

Level/

Class

FESD

EFTB

Voltage limits to be applied on any I/O pin to induce a functional disturbance

Fast transient voltage burst limits to be applied through 100 pF on V

and V pins to induce a functional disturbance

= 3.3 V, LQFP100, T

+25 °C, f

HCLK to IEC 61000-4-2

= 72 MHz, conforms

= 3.3 V, LQFP100, T

+25 °C, f

HCLK to IEC 61000-4-4

= 72 MHz, conforms

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

• Corrupted program counter

• Unexpected reset

• Critical Data corruption (control registers...)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with

IEC61967-2 standard which specifies the test board and the pin loading.

DocID15274 Rev 10 55/108

107

Electrical characteristics STM32F105xx, STM32F107xx

EMI

Symbol Parameter

Table 32. EMI characteristics

Conditions

Monitored frequency band

Peak level

= 3.3 V, T

= 25 °C,

LQFP100 package compliant with IEC61967-2

0.1 to 30 MHz

30 to 130 MHz

130 MHz to 1GHz

EMI Level

Max vs. [f

HSE

HCLK

]

8/48 MHz 8/72 MHz

Unit dBµV

5.3.11 Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard.

Symbol

Table 33. ESD absolute maximum ratings

Ratings Conditions Class

Maximum value

(1)

Unit

ESD(HBM)

ESD(CDM)

Electrostatic discharge voltage

(human body model)

Electrostatic discharge voltage

(charge device model)

= +25 °C conforming to

JESD22-A114

= +25 °C conforming to

JESD22-C101

1. Based on characterization results, not tested in production.

2000

500

Symbol

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up performance:

• A supply overvoltage is applied to each power supply pin

• A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD 78A IC latch-up standard.

Parameter

Static latch-up class

Table 34. Electrical sensitivities

Conditions

= +105 °C conforming to JESD78A

Class

II level A

56/108

As a general rule, current injection to the I/O pins, due to external voltage below V

SS above V

(for standard, 3 V-capable I/O pins) should be avoided during normal product

DocID15274 Rev 10

STM32F105xx, STM32F107xx Electrical characteristics operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (>5

LSB TUE), out of spec current injection on adjacent pins or other functional failure (for example reset, oscillator frequency deviation).

The test results are given in

Table 35

Symbol

INJ

Table 35. I/O current injection susceptibility

Functional susceptibility

Description

Negative injection

Positive injection

Injected current on OSC_IN32,

OSC_OUT32, PA4, PA5, PC13

Injected current on all FT pins

Injected current on any other pin

-0

-5

Unit mA

General input/output characteristics

are derived from tests

performed under the conditions summarized in Table 9 . All I/Os are CMOS and TTL

compliant.

Symbol

Parameter

Standard IO input low level voltage

IO FT

(1) voltage

input low level

Standard IO input high level voltage

IO FT

(1) voltage

input high level

Table 36. I/O static characteristics

Conditions Min

> 2 V

2 V

–0.3

0.41*(V

-2 V)+1.3 V -

0.42*(V

-2 V)+1 V

Typ

Max

- 0.28*(V

-2 V)+0.8 V V

- 0.32*(V

-2V)+0.75 V V

+0.3

5.5

5.2

Unit

V hys

Standard IO Schmitt trigger voltage hysteresis

(2)

IO FT Schmitt trigger voltage hysteresis (2)

200

5% V

(3)

- mV mV

DocID15274 Rev 10 57/108

107

Electrical characteristics STM32F105xx, STM32F107xx

Symbol Parameter

Table 36. I/O static characteristics (continued)

Conditions Min Typ Max Unit

I lkg

Input leakage current

(4)

≤ V

Standard I/Os

- - ± 1

µA

= 5 V, I/O FT - - 3

Weak pullup equivalent resistor

(5)

All pins except for

PA10 V

= V

30 40 50 k Ω

Weak pulldown equivalent resistor (5)

PA10

All pins except for

PA10 V

= V

50 k Ω

PA10 8 11 15

I/O pin capacitance - - 5 -

1. FT = Five-volt tolerant. In order to sustain a voltage higher than V disabled.

+0.3 the internal pull-up/pull-down resistors must be

2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.

3. With a minimum of 100 mV.

4. Leakage could be higher than max. if negative current is injected on adjacent pins.

5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

MOS/NMOS contribution to the series resistance is minimum (~10% order)

All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in

Figure 18

and

Figure 19 for standard I/Os, and

Figure 20 and Figure 21 for 5 V tolerant I/Os.

Figure 18. Standard I/O input characteristics - CMOS port

6)(6),6

6)(6$$

)(MIN

),MAX

#-/3STANDARDREQUIREMENT

6 )(6

#-/3STANDARDREQUIREMENT

6),6$$

6 $$

)NPUTRANGE

NOTGUARANTEED

6$$6

AIB

58/108 DocID15274 Rev 10

STM32F105xx, STM32F107xx Electrical characteristics

Figure 19. Standard I/O input characteristics - TTL port

6)(6),6

)(MIN

),MAX

44,REQUIREMENTS 6)(6

6)(6$$

6),6$$

44,REQUIREMENTS 6),6

)NPUTRANGE

NOTGUARANTEED

6$$6

Figure 20. 5 V tolerant I/O input characteristics - CMOS port

6)(6),6

#-/3STANDARDREQUIREMENTS

6)(6

6)(6$$

6),6$$

#-/3STANDARDREQUIR

MENT6),6$$

)NPUTRANGE

NOTGUARANTEED

Figure 21. 5 V tolerant I/O input characteristics - TTL port

6$$

6$$6

AIB

6)(6),6

44,REQUIREMENT6)(6

)(MIN

),MAX

6)(6$$

6),6$$

)NPUTRANGE

NOTGUARANTEED

44,REQUIREMENTS6),6

6$$6

DocID15274 Rev 10 59/108

107

Electrical characteristics STM32F105xx, STM32F107xx

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or source up to +/-20 mA (with a relaxed V

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in

Section 5.2

• The sum of the currents sourced by all the I/Os on V

DD,

I consumption of the MCU sourced on V

DD,

VDD

(see

). plus the maximum Run cannot exceed the absolute maximum rating

• The sum of the currents sunk by all the I/Os on V

I consumption of the MCU sunk on V

VSS

(see

Unless otherwise specified, the parameters given in Table 37

plus the maximum Run

cannot exceed the absolute maximum rating

Output voltage levels

are derived from tests performed under ambient temperature and V

Table 9 . All I/Os are CMOS and TTL compliant.

supply voltage conditions summarized in

Symbol

Table 37. Output voltage characteristics

Parameter Conditions Min Max Unit

(1)

(2)

(1)

(2)

Output low level voltage for an I/O pin when 8 pins are sunk at same time

Output high level voltage for an I/O pin when 8 pins are sourced at same time

Output low level voltage for an I/O pin when 8 pins are sunk at same time

Output high level voltage for an I/O pin when 8 pins are sourced at same time

(1)(3)

Output low level voltage for an I/O pin when 8 pins are sunk at same time

(2)(3)

(1)(3)

Output high level voltage for an I/O pin when 8 pins are sourced at same time

Output low level voltage for an I/O pin when 8 pins are sunk at same time

(2)(3)

Output high level voltage for an I/O pin when 8 pins are sourced at same time

TTL port

= +8 mA

2.7 V < V

< 3.6 V

CMOS port

=+ 8mA

2.7 V < V

< 3.6 V

2.7 V < V

= +20 mA

< 3.6 V

= +6 mA

2 V < V

< 2.7 V

–0.4

2.4

–1.3

–0.4

0.4

1.3

0.4

1. The I

current sunk by the device must always respect the absolute maximum rating specified in

and the sum of I

(I/O ports and control pins) must not exceed I

VSS

2. The I

Unless otherwise specified, the parameters given in Table 38

current sourced by the device must always respect the absolute maximum rating specified in

and the sum of I

(I/O ports and control pins) must not exceed I

VDD

3. Based on characterization data, not tested in production.

60/108 DocID15274 Rev 10

STM32F105xx, STM32F107xx Electrical characteristics

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in

Figure 22 and

Table 38 , respectively.

are derived from tests performed under the ambient temperature and V

DD in

Unless otherwise specified, the parameters given in Table 39

supply voltage conditions summarized

Table 38. I/O AC characteristics (1)

MODEx[1:0] bit value

(1)

Symbol

Parameter Conditions f max(IO)out t f(IO)out

Maximum frequency

(2)

= 50 pF, V

= 2 V to 3.6 V

Output high to low level fall time

= 50 pF, V

= 2 V to 3.6 V t r(IO)out

Output low to high level rise time f max(IO)out t t f(IO)out r(IO)out

Maximum frequency

(2)

= 50 pF, V

= 2 V to 3.6 V

Output high to low level fall time

= 50 pF, V

= 2 V to 3.6 V

Output low to high level rise time

Min Max Unit

- 2 MHz

- 125

(3)

- 125

(3)

- 25

(3)

- 25

(3) ns

- 10 MHz ns

= 30 pF, V

= 2.7 V to 3.6 V - 50 MHz

F max(IO)out

Maximum frequency

(2)

= 50 pF, V

= 2.7 V to 3.6 V - 30 MHz t t f(IO)out r(IO)out

Output high to low level fall time

Output low to high level rise time

= 50 pF, V

= 2 V to 2.7 V - 20

= 30 pF, V

= 2.7 V to 3.6 V - 5

(3)

MHz

= 50 pF, V

= 2.7 V to 3.6 V - 8 (3)

= 50 pF, V

= 2 V to 2.7 V - 12

(3) ns

= 30 pF, V

= 2.7 V to 3.6 V - 5

(3)

= 50 pF, V

= 2.7 V to 3.6 V - 8

(3)

= 50 pF, V

= 2 V to 2.7 V - 12

(3) t

EXTIpw

Pulse width of external signals detected by the EXTI controller

10 - ns

1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a description of GPIO Port configuration register.

2. The maximum frequency is defined in

Figure 22 .

3. Guaranteed by design, not tested in production.

DocID15274 Rev 10 61/108

107

Electrical characteristics STM32F105xx, STM32F107xx

Figure 22. I/O AC characteristics definition

10%

50%

90% 10%

50%

90%

EXTERNAL

OUTPUT

ON 50 pF tr(IO)out

T tf(IO)o u t when loaded by 50 pF ai14131

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, R

(see

Table 36 ).

are derived from tests performed under the ambient temperature and V

DD in

Table 39 . Otherwise the reset will not be taken into account by the device.

supply voltage conditions summarized

Table 39. NRST pin characteristics

Symbol Parameter Conditions Min Typ Max Unit

IL(NRST)

(1)

IH(NRST)

(1)

NRST Input low level voltage

NRST Input high level voltage -

–0.5

- 0.8

- V

+0.5

V hys(NRST)

F(NRST)

(1)

NF(NRST)

(1)

NRST Schmitt trigger voltage hysteresis

Weak pull-up equivalent resistor

(2)

NRST Input filtered pulse

NRST Input not filtered pulse

= V

> 2.7 V

300

200

100

- mV

1. Guaranteed by design, not tested in production.

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order)

k Ω ns ns

62/108 DocID15274 Rev 10

STM32F105xx, STM32F107xx Electrical characteristics

Figure 23. Recommended NRST pin protection

External reset circuit (1)

NR S T (2)

VDD

RPU

0.1 µF

Filter

Internal Reset

STM32F10xxx ai141 3 2d

2. The reset network protects the device against parasitic resets.

3. The user must ensure that the level on the NRST pin can go below the V

max level specified in

The parameters given in

Table 40 are guaranteed by design.

Refer to Section 5.3.12: I/O current injection characteristics for details on the input/output

alternate function characteristics (output compare, input capture, external clock, PWM output).

Symbol Parameter

Table 40. TIMx

(1)

characteristics

Conditions Min Max Unit t res(TIM)

- 1

TIMxCLK

= 72 MHz 13.9

- t

TIMxCLK f

EXT

Timer resolution time

Timer external clock frequency on CH1 to CH4

- f

TIMxCLK

= 72 MHz

0 f

TIMxCLK

/2 ns

MHz

MHz t

Res

TIM

COUNTER

Timer resolution - -

16-bit counter clock period when internal clock is selected

- 1

TIMxCLK

= 72 MHz 0.0139

65536

910 t bit

TIMxCLK

µs t

MAX_COUNT

Maximum possible count

TIMxCLK

= 72 MHz

65536 × 65536 t

TIMxCLK

59.6

1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3, TIM4 and TIM5 timers.

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107

Electrical characteristics STM32F105xx, STM32F107xx

I

C interface characteristics

Unless otherwise specified, the parameters given in Table 41

are derived from tests performed under the ambient temperature, f

conditions summarized in Table 9 .

PCLK1 frequency and V

supply voltage

The STM32F105xx and STM32F107xx I

C interface meets the requirements of the standard I

C communication protocol with the following restrictions: the I/O pins SDA and

SCL are mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and V

DD is disabled, but is still present.

The I

C characteristics are described in

Table 41

. Refer also to

Section 5.3.12: I/O current injection characteristics

for more details on the input/output alternate function characteristics

(SDA and SCL).

Symbol Parameter

Table 41. I 2 C characteristics

Standard mode I

(1)

Min Max

Fast mode I

(1)(2)

Unit

Min Max t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t r(SDA) t r(SCL) t f(SDA) t f(SCL) t h(STA)

SCL clock low time

SCL clock high time

SDA setup time

SDA data hold time

SDA and SCL rise time

SDA and SCL fall time

4.7

4.0

250

(3)

1000

300

1.3

0.6

100

(4)

20 + 0.1C

900

(3)

300

µs ns t t su(STA) su(STO) t w(STO:STA)

C b

Start condition hold time

Repeated Start condition setup time

Stop condition setup time

Stop to Start condition time

(bus free)

Capacitive load for each bus line

4.0

4.7

4.0

4.7

400

0.6

0.6 -

0.6

1.3

400

µs

μ s s pF

1. Guaranteed by design, not tested in production.

2. f

PCLK1

must be at least 2 MHz to achieve standard mode I achieve the fast mode I 2 maximum clock 400 kHz.

2 C frequencies. It must be at least 4 MHz to

C frequencies and it must be a mulitple of 10 MHz in order to reach I 2 C fast mode

3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of SCL signal.

4. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL.

64/108 DocID15274 Rev 10

STM32F105xx, STM32F107xx Electrical characteristics

Figure 24. I 2 C bus AC waveforms and measurement circuit

VDD VDD

I²C bus

4 .7 k Ω 4 .7 k Ω

100 Ω

100

STM32F10x

S DA

S CL

S tart repeated

S tart

S tart tsu(

S TA)

S DA tf(

S DA) th(

S TA) tr(

S DA) tw(

S CLL) tsu(

S DA) th(

S DA)

S top tsu(

S TO: S TA)

S CL tw(

S CLH) tr(

S CL) tf(

S CL) tsu(

S TO) ai141 33 d

1. Measurement points are done at CMOS levels: 0.3V

and 0.7V

Table 42. SCL frequency (f

PCLK1

= 36 MHz.,V

= 3.3 V)

(1)(2)

I2C_CCR value f

SCL

(kHz)

= 4.7 k Ω

400 0x801E

300

200

100

0x8028

0x803C

0x00B4

0x0168

20 0x0384

1. R

= External pull-up resistance, f

SCL

= I

C speed,

2. For speeds around 200 kHz, the tolerance on the achieved speed is of tolerance on the achieved speed 2%. These variations depend on the accuracy of the external components used to design the application.

± 5%. For other speed ranges, the

DocID15274 Rev 10 65/108

107

Electrical characteristics STM32F105xx, STM32F107xx

I

S - SPI interface characteristics

Unless otherwise specified, the parameters given in Table 43

for SPI or in

Table 44 for I

2 S are derived from tests performed under the ambient temperature, f

supply voltage conditions summarized in Table 9 .

PCLKx frequency and V

Refer to Section 5.3.12: I/O current injection characteristics for more details on the

input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK,

SD for I 2 S).

Symbol Parameter

Table 43. SPI characteristics

Conditions

1/t f

SCK c(SCK)

SPI clock frequency

Master mode

Slave mode t r(SCK) t f(SCK)

DuCy(SCK) t t su(NSS) h(NSS) t w(SCKH) t w(SCKL) t su(MI) t su(SI) t h(MI) t h(SI)

SPI slave input clock duty cycle

NSS setup time

NSS hold time

Slave mode

SCK high and low time

Master mode, f

PCLK presc = 4

= 36 MHz,

Master mode

Data input setup time

Data input hold time

Slave mode

Master mode

Slave mode t a(SO) t v(SO) t v(MO) t h(SO) t h(MO)

SPI clock rise and fall time

Capacitive load: C = 30 pF

Data output access time

Slave mode, f

PCLK

= 20 MHz

Data output valid time Slave mode (after enable edge)

Data output valid time Master mode (after enable edge)

Data output hold time

Slave mode (after enable edge)

Master mode (after enable edge)

Min

Max

4 t

PCLK

2 t

PCLK

3*t

PCLK

Unit

MHz ns

% ns

66/108 DocID15274 Rev 10

STM32F105xx, STM32F107xx Electrical characteristics

Figure 25. SPI timing diagram - slave mode and CPHA = 0

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Figure 26. SPI timing diagram - slave mode and CPHA = 1

(1)

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1. Measurement points are done at CMOS levels: 0.3V

and 0.7V

DocID15274 Rev 10 67/108

107

Electrical characteristics STM32F105xx, STM32F107xx

Figure 27. SPI timing diagram - master mode (1)

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and 0.7V

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68/108 DocID15274 Rev 10

STM32F105xx, STM32F107xx

Symbol Parameter

Table 44. I 2 S characteristics

Conditions

1/t f

CK c(CK)

S clock frequency

Master data: 16 bits, audio freq = 48 K

Slave t r(CK) t f(CK) t w(CKH)

(1) t w(CKL)

(1) t v(WS)

(1)

S clock rise and fall time

S clock high time

S clock low time

WS valid time capacitive load C

Master f

PCLK

= 50 pF

= 16 MHz, audio freq = 48 K

Master mode t t h(WS)

(1) su(WS)

(1)

WS hold time

WS setup time

Master mode

Slave mode

I2S2

I2S3

I2S2

I2S3 t h(WS)

(1)

DuCy(SCK)

WS hold time

I2S slave input clock duty cycle

Slave mode

Slave mode t t t t t su(SD_MR)

(1) su(SD_SR)

(1) h(SD_MR)

(1) h(SD_SR)

(1) v(SD_ST)

(1)(3) t t h(SD_ST)

(1) v(SD_MT)

(1)

Data input setup time

Data input hold time

Data output valid time

Data output hold time

Data output valid time

Master receiver

Slave receiver

Master receiver

Slave receiver

Slave transmitter

(after enable edge)

Slave transmitter

(after enable edge)

Master transmitter

(after enable edge)

I2S3

I2S2

I2S3

I2S2

I2S3

I2S2

I2S3

I2S2

I2S3

I2S2

I2S3

I2S2

I2S3 t h(SD_MT)

(1)

Data output hold time

Master transmitter

(after enable edge)

I2S2

I2S3

1. Based on design simulation and/or characterization results, not tested in production.

Electrical characteristics

Min

1.52

317

333

Unit

MHz ns

% ns

Max

1.54

6.5

320

336

DocID15274 Rev 10 69/108

107

Electrical characteristics STM32F105xx, STM32F107xx

Figure 28. I 2 S slave timing diagram (Philips protocol) (1)

1. Measurement points are done at CMOS levels: 0.3 × V

and 0.7 × V

2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

Figure 29. I 2 S master timing diagram (Philips protocol) (1)

70/108

1. Based on characterization, not tested in production.

2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

DocID15274 Rev 10

STM32F105xx, STM32F107xx Electrical characteristics

USB OTG FS characteristics

The USB OTG interface is USB-IF certified (Full-Speed).

Symbol

Table 45. USB OTG FS startup time

Parameter t

STARTUP

(1)

USB OTG FS transceiver startup time

1. Guaranteed by design, not tested in production.

Max

Unit

µs

Symbol

Table 46. USB OTG FS DC electrical characteristics

Parameter Conditions Min.

(1) Typ. Max.

(1) Unit

Input levels

USB OTG FS operating voltage

(3)

Differential input sensitivity

Differential common mode range

I(USBDP, USBDM)

Includes V

DI range

3.0

(2)

0.2

0.8

3.6

2.5

(3)

Single ended receiver threshold

Static output level low R

of 1.5 k

Ω to 3.6 V (4)

of 15 k Ω to V

(4)

1.3

- 2.0

Output levels

2.8

0.3

3.6

Static output level high

Pull-down resistance on

PA11, PA12

Pull-down resistance on

PA9

= V

0.65

1.1

2.0

Pull-up resistance on PA12

Pull-up resistance on PA9

= V

1.5

0.25

1.8

0.37

2.1

0.55

1. All the voltages are measured from the local ground potential.

2. The STM32F105xx and STM32F107xx USB OTG FS functionality is ensured down to 2.7 V but not the full

USB OTG FS electrical characteristics which are degraded in the 2.7-to-3.0 V V

voltage range.

3. Guaranteed by design, not tested in production.

4. R

is the load connected on the USB OTG FS drivers

Figure 30. USB OTG FS timings: definition of data signal rise and fall time

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DocID15274 Rev 10 71/108

107

Electrical characteristics STM32F105xx, STM32F107xx

Table 47. USB OTG FS electrical characteristics

(1)

Driver characteristics

Symbol Parameter Conditions Min Max Unit t r t f t rfm

CRS

Rise time

Fall time

(2)

Rise/ fall time matching

Output signal crossover voltage

= 50 pF

= 50 pF t r

- f

1.3

110

2.0

ns ns

1. Guaranteed by design, not tested in production.

2. Measured from 10% to 90% of the data signal. For more detailed informations, refer to USB Specification -

Chapter 7 (version 2.0).

Ethernet characteristics

Table 48 showns the Ethernet operating voltage.

Symbol

Table 48. Ethernet DC electrical characteristics

Parameter

Input level V

Ethernet operating voltage

1. All the voltages are measured from the local ground potential.

Min.

(1)

3.0

Max.

(1)

3.6

Unit

Table 49 gives the list of Ethernet MAC signals for the SMI (station management interface) and Figure 31

shows the corresponding timing diagram.

Figure 31. Ethernet SMI timing diagram

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Symbol

Table 49. Dynamic characteristics: Ethernet MAC signals for SMI

Rating t

MDC t d(MDIO) t su(MDIO) t h(MDIO)

MDC cycle time (1.71 MHz, AHB = 72 MHz)

MDIO write data valid time

Read data setup time

Read data hold time

Min

583

13.5

Typ

583.5

14.5

Max

584

15.5

Unit ns ns ns ns

72/108 DocID15274 Rev 10

STM32F105xx, STM32F107xx Electrical characteristics

Table 50 gives the list of Ethernet MAC signals for the RMII and Figure 32 shows the

corresponding timing diagram.

Figure 32. Ethernet RMII timing diagram

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Table 50. Dynamic characteristics: Ethernet MAC signals for RMII

Rating Min Typ Max t su(RXD) t ih(RXD) t su(DV) t ih(DV) t d(TXEN) t d(TXD)

Receive data setup time

Receive data hold time

Carrier sense set-up time

Carrier sense hold time

Transmit enable valid delay time

Transmit data valid delay time

Unit ns ns ns ns ns ns

Table 51

gives the list of Ethernet MAC signals for MII and Figure 32 shows the

corresponding timing diagram.

Figure 33. Ethernet MII timing diagram

MII_RX_CLK

MII_RXD[3:0]

MII_RX_DV

MII_RX_ER t su (RXD) t su (ER) t su (DV)

MII_TX_CLK t ih(RXD) t ih(ER) t ih(DV) t d(TXEN) t d(TXD)

MII_TX_EN

MII_TXD[3:0] a i15668

DocID15274 Rev 10 73/108

107

Electrical characteristics STM32F105xx, STM32F107xx

Symbol

Table 51. Dynamic characteristics: Ethernet MAC signals for MII

Rating Min Typ Max t su(RXD) t ih(RXD) t su(DV) t ih(DV) t su(ER) t ih(ER) t d(TXEN) t d(TXD)

Receive data setup time

Receive data hold time

Data valid setup time

Data valid hold time

Error setup time

Error hold time

Transmit enable valid delay time

Transmit data valid delay time

CAN (controller area network) interface

Refer to Section 5.3.12: I/O current injection characteristics for more details on the

input/output alternate function characteristics (CANTX and CANRX).

Unit ns ns ns ns ns ns ns ns

Note:

Unless otherwise specified, the parameters given in Table 52

are derived from tests performed under the ambient temperature, f

conditions summarized in Table 9 .

PCLK2 frequency and V

DDA

supply voltage

It is recommended to perform a calibration after each power-up.

Symbol

DDA

REF+

VREF f

ADC f

(2)

Parameter

Power supply

Positive reference voltage

Current on the V

REF

input pin

ADC clock frequency

Sampling rate f

TRIG

(2)

External trigger frequency

AIN

Conversion voltage range

(3)

Table 52. ADC characteristics

Conditions Min

- f

ADC

= 14 MHz

2.4

0.6

0.05

0 (V

SSA or V

REFtied to ground)

R t

AIN

(2)

CAL

(2)

External input impedance

ADC

(2)

ADC

(2)

Sampling switch resistance

Internal sample and hold capacitor

Calibration time

See Equation 1 and

Table 53 for details

- f

ADC

= 14 MHz

5.9

Typ

160 (1)

Max

3.6

DDA

220 (1)

823

REF+

Unit

µA

MHz

MHz kHz

1/f

ADC

V k Ω k Ω pF

µs

1/f

ADC

74/108 DocID15274 Rev 10

STM32F105xx, STM32F107xx Electrical characteristics t

Symbol t t t t lat

(2) latr

(2)

STAB

(2)

CONV

(2)

Parameter

Sampling time

Power-up time sampling time)

Table 52. ADC characteristics (continued)

Injection trigger conversion latency

Regular trigger conversion latency

Total conversion time (including

Conditions f

ADC

= 14 MHz

ADC

= 14 MHz

ADC

= 14 MHz f

ADC

= 14 MHz

Min Typ Max Unit

0.214

(4)

µs

1/f

ADC

µs

0.107

1.5

0.143

(4)

17.1

239.5

1/f

ADC

1 µs

1 18

14 to 252 (t

for sampling +12.5 for successive approximation)

1/f

ADC

µs

1/f

µs

ADC

1. Based on characterization, not tested in production.

2. Guaranteed by design, not tested in production.

3. V

REF+

is internally connected to V

DDA

and V

REF-

is internally connected to V

SSA

4. For external triggers, a delay of 1/f

PCLK2

must be added to the latency specified in

Table 52

Equation 1: R

AIN

AIN

< f

max formula

----------------------------------------------------------------

ADC

× C

ADC

× ln ( 2 N + 2 )

– R

ADC

The form u l a ab ove ( Equation 1 ) i s us ed to determine the m a xim u m extern a l imped a nce a llowed for a n error b elow 1/4 of LSB. Here N = 12 (from 12b it re s ol u tion).

T s

(cycles)

1.5

7.5

13.5

28.5

41.5

55.5

71.5

239.5

Table 53. R

AIN

max for f

ADC

= 14 MHz (1) t

(µs)

0.11

0.54

0.96

2.04

2.96

3.96

5.11

17.1

1. Based on characterization, not tested in production.

AIN

max (k Ω )

0.4

5.9

11.4

25.2

37.2

DocID15274 Rev 10 75/108

107

Electrical characteristics

Note:

STM32F105xx, STM32F107xx

Symbol

Table 54. ADC accuracy - limited test conditions (1)

Parameter Test conditions

Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error f

PCLK2

= 56 MHz, f

ADC

= 14 MHz, R

AIN

< 10 k Ω ,

DDA

= 3 V to 3.6 V

= 25 °C

Measurements made after

ADC calibration

1. ADC DC accuracy values are measured after internal calibration.

2. Based on characterization, not tested in production.

Typ

±1.3

±1

±0.5

±0.7

±0.8

Max

(2)

±2

±1.5

±1

±1.5

Symbol Parameter

Table 55. ADC accuracy

(1) (2)

Test conditions Typ Max

(3)

Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error f

PCLK2 f

ADC

= 14 MHz, R

AIN

DDA

= 56 MHz,

= 2.4 V to 3.6 V

Measurements made after

ADC calibration

< 10 k Ω ,

±2

±1.5

±1

±1.5

1. ADC DC accuracy values are measured after internal calibration.

2. Better performance could be achieved in restricted V

, frequency and temperature ranges.

3. Based on characterization, not tested in production.

±5

±2.5

±3

±2

±3

Unit

LSB

Unit

LSB

ADC accuracy vs. negative injection current: Injecting a negative current on any of the standard (non-robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative currents.

Any positive injection current within the limits specified for I

INJ(PIN)

Section 5.3.12

does not affect the ADC accuracy.

and Σ I

INJ(PIN)

76/108 DocID15274 Rev 10

STM32F105xx, STM32F107xx Electrical characteristics

Figure 34. ADC accuracy characteristics

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Figure 35. Typical connection diagram using the ADC

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1. Refer to Table 52 for the values of R

AIN

, R

ADC

and C

ADC

2. C parasitic this, f

represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

ADC

should be reduced.

parasitic

value will downgrade conversion accuracy. To remedy

DocID15274 Rev 10 77/108

107

Electrical characteristics STM32F105xx, STM32F107xx

General PCB design guidelines

Power supply decoupling should be performed as shown in

Figure 36

Figure 37

, depending on whether V

REF+

is connected to V

DDA

or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip.

Figure 36. Power supply and reference decoupling (V

REF+ not connected to V

DDA

)

STM32F10xxx

V REF+

(See note 1)

1 µ F // 10 nF V DDA

1 µ F // 10 nF

V SSA/V REF-

(See note 1) a i14380c

1. V

REF+

and V

REF–

inputs are available only on 100-pin packages.

Figure 37. Power supply and reference decoupling (V

REF+ connected to V

DDA

)

STM32F10xxx

REF+

DDA

(See note 1)

1 µ F // 10 nF

REF–

SSA

(See note 1) a i14381c

1. V

REF+

and V

REF–

inputs are available only on 100-pin packages.

78/108 DocID15274 Rev 10

STM32F105xx, STM32F107xx Electrical characteristics

Symbol

LOAD

(1)

Capacitive load

DAC_OUT max

(1)

Higher DAC_OUT voltage with buffer ON

DAC_OUT min

(1)

Lower DAC_OUT voltage with buffer OFF

DAC_OUT max

(1)

Higher DAC_OUT voltage with buffer OFF

DDVREF+

DAC DC current consumption in quiescent mode (Standby mode)

Table 56. DAC characteristics

Min

DDA

REF+

SSA

LOAD

(1)

Analog supply voltage 2.4

Reference supply voltage 2.4

Ground 0

Resistive load with buffer ON 5

(1)

Parameter

Impedance output with buffer

OFF

DAC_OUT min

(1)

Lower DAC_OUT voltage with buffer ON

DDA

DNL

(2)

INL (2)

DAC DC current consumption in quiescent mode (Standby mode)

Differential non linearity

Difference between two consecutive code-1LSB)

Integral non linearity

(difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023)

0.2

Typ

3.6

DDA

– 0.2

±0.5

±2

±1

V -

V V

REF+

must always be below V

DDA

V k Ω k Ω pF

When the buffer is OFF, the

Minimum resistive load between

DAC_OUT and V

SS accuracy is 1.5 M Ω

to have a 1%

Maximum capacitive load at

DAC_OUT pin (when the buffer is

ON).

It gives the maximum output excursion of the DAC.

It corresponds to 12-bit input code

(0x0E0) to (0xF1C) at V

REF+

3.6 V and (0x155) to (0xEAB) at

REF+

= 2.4 V

0.5

- mV

It gives the maximum output excursion of the DAC.

- V

REF+

– 1LSB V

220

380

480

µA

With no load, worst code (0xF1C) at V

REF+

= 3.6 V in terms of DC consumption on the inputs

With no load, middle code (0x800) on the inputs

With no load, worst code (0xF1C) at V

REF+

= 3.6 V in terms of DC consumption on the inputs

LSB

Given for the DAC in 10-bit configuration.

LSB

Given for the DAC in 12-bit configuration.

LSB

Given for the DAC in 10-bit configuration.

Max

±4

Unit Comments

LSB

Given for the DAC in 12-bit configuration.

DocID15274 Rev 10 79/108

107

Electrical characteristics STM32F105xx, STM32F107xx

Symbol

Offset

(2)

Parameter

Table 56. DAC characteristics (continued)

Offset error

(difference between measured value at Code

(0x800) and the ideal value =

REF+

/2)

Min Typ

Max

±10

±3

±12

±0.5

Unit Comments mV

Given for the DAC in 12-bit configuration

LSB

Given for the DAC in 10-bit at

REF+

= 3.6 V

Given for the DAC in 12-bit at

REF+

= 3.6 V

Given for the DAC in 12bit configuration

Gain error (2)

Update rate

(2)

Gain error t

SETTLING

(2)

Settling time (full scale: for a

10-bit input code transition between the lowest and the highest input codes when

DAC_OUT reaches final value ±1LSB

Max frequency for a correct

DAC_OUT change when small variation in the input code (from code i to i+1LSB) t

WAKEUP

(2)

Wakeup time from off state

(Setting the ENx bit in the

DAC Control register)

6.5

PSRR+

(1)

Power supply rejection ratio

(to V

DDA

) (static DC measurement

- –67

1. Guaranteed by design, not tested in production.

2. Guaranteed by characterization, not tested in production.

–40

µs

MS/s

LOAD

≤

≥ 5 k Ω

µs

LOAD

≤

≥ 5 k Ω

LOAD

≤

LOAD

≥ 5 k Ω input code between lowest and highest possible ones.

dB No R

LOAD

, C

LOAD

= 50 pF

Figure 38. 12-bit buffered /non-buffered DAC

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1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the

DAC_CR register.

80/108 DocID15274 Rev 10

STM32F105xx, STM32F107xx Electrical characteristics

5.3.19 Temperature sensor characteristics

Symbol

Table 57. TS characteristics

Parameter Min Typ

(1)

Avg_Slope

(1)

(1) t

START

(2)

SENSE

linearity with temperature

Average slope

Voltage at 25 °C

Startup time

4.0

1.34

± 1

4.3

1.43

S_temp

(3)(2)

ADC sampling time when reading the temperature

1. Based on characterization, not tested in production.

2. Guaranteed by design, not tested in production.

3. Shortest sampling time can be determined in the application by multiple iterations.

Max

± 2

4.6

1.52

17.1

Unit

°C mV/°C

µs

DocID15274 Rev 10 81/108

107

Package information STM32F105xx, STM32F107xx

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com

ECOPACK ® is an ST trademark.

Figure 39. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package outline

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$ $

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$ $

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82/108 DocID15274 Rev 10

STM32F105xx, STM32F107xx Package information

Figure 40. LFBGA100 – 100-ball low profile fine pitch ball grid array, 10 x 10 mm,

0.8 mm pitch, package mechanical data inches

(1)

Symbol millimeters

Min Typ Max Typ Min Max

E1 e

F ddd eee fff

A4 b

0.270

0.450

9.850

0.300

0.500

10.000

7.200

10.000

7.200

0.800

1.400

1.700

0.800

0.550

10.150

0.120

0.150

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.0106

0.0177

0.3878

0.0118

0.0197

0.3937

0.2835

0.3937

0.2835

0.0315

0.0551

0.0669

0.0315

0.0217

0.3996

0.0047

0.0059

0.0031

Figure 41. LFBGA100 – 100-ball low profile fine pitch ball grid array, 10 x 10 mm,

0.8 mm pitch, package recommended footprint

'SDG

'VP

+B)3B9

Pitch

Dpad

Dsm

Table 58. LFBGA100 recommended PCB design rules (0.8 mm pitch BGA)

Dimension Recommended values

Stencil opening

Stencil thickness

Pad trace width

0.8

0.500 mm

0.570 mm typ. (depends on the soldermask registration tolerance)

0.500 mm

Between 0.100 mm and 0.125 mm

0.120 mm

DocID15274 Rev 10 83/108

107

Package information STM32F105xx, STM32F107xx

Device marking for LFBGA100

The following figure shows the device marking for the LQFP100 package.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 42. LFBGA100 marking example (package top view)

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069

Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST

Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity.

84/108 DocID15274 Rev 10

STM32F105xx, STM32F107xx

6.2 LQFP100 package information

Package information

Figure 43. LQFP100 – 14 x 14 mm 100 pin low-profile quad flat package outline

3%!4).'0,!.%

'!5'%0,!.%

CCC #

, +

0).

)$%.4)&)#!4)/.

,?-%?6

1. Drawing is not to scale. Dimension are in millimeter.

Table 59. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max b c

0.050

1.350

0.170

0.090

15.800

13.800

15.800

13.800

1.400

0.220

16.000

14.000

12.000

16.000

14.000

1.600

0.150

1.450

0.270

0.200

16.200

14.200

16.200

14.200

0.0020

0.0531

0.0067

0.0035

0.6220

0.5433

0.6220

0.5433

0.0551

0.0087

0.6299

0.5512

0.4724

0.6299

0.5512

0.0630

0.0059

0.0571

0.0106

0.0079

0.6378

0.5591

0.6378

0.5591

DocID15274 Rev 10 85/108

107

Package information STM32F105xx, STM32F107xx

Table 59. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data (continued) millimeters inches (1)

Symbol

Min Typ Max Min Typ Max

E3 e

0.450

12.000

0.500

0.600

0.750

0.0177

0.4724

0.0197

0.0236

L1 k

0.0°

1.000

3.5°

7.0°

0.0° ccc 0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.0394

3.5°

0.0295

7.0°

0.0031

Figure 44. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint

AIC

86/108 DocID15274 Rev 10

STM32F105xx, STM32F107xx Package information

Device marking for LQFP100

The following figure shows the device marking for the LQFP100 package.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 45.LQFP100 marking example (package top view)

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PDUN

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06Y9

1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity.

DocID15274 Rev 10 87/108

107

Package information

6.3 LQFP64 package information

STM32F105xx, STM32F107xx

Figure 46.LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline

6($7,1*3/$1(

*$8*(3/$1(

FFF &

' /

88/108

3,1

,'(17,),&$7,21

:B0(B9

Dr a wing i s not in s c a le.

Table 60.LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data millimeter s inche s

(1)

S ymbol

Min Typ Max Min Typ Max b c

0.050

1.350

0.170

0.090

1.400

0.220

12.000

10.000

7.500

12.000

10.000

7.500

1.600

0.150

1.450

0.270

0.200

0.0020

0.0531

0.0067

0.0035

0.0551

0.0087

0.4724

0.3937

0.2953

0.4724

0.3937

0.2953

0.0630

0.0059

0.0571

0.0106

0.0079

DocID15274 Rev 10

STM32F105xx, STM32F107xx Package information

Table 60.LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data millimeter s inche s

(1)

S ymbol

Min Typ Max Min Typ Max e

L1 ccc

0°

0.450

0.500

3.5°

0.600

1.000

7°

0.750

0.080

0°

0.0177

V a l u e s in inche s a re converted from mm a nd ro u nded to 4 decim a l digit s .

0.0197

3.5°

0.0236

0.0394

7°

0.0295

0.0031

Figure 47.LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat recommended footprint

AIC

1. Dimensions are in millimeters.

DocID15274 Rev 10 89/108

107

Package information STM32F105xx, STM32F107xx

Device marking for LQFP64

The following figure shows the device marking for the LQFP64 package.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 48.LQFP64 marking example (package top view)

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3URGXFWLGHQWLILFDWLRQ

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90/108 DocID15274 Rev 10

STM32F105xx, STM32F107xx Package information

The maximum chip junction temperature (T

J max) must never exceed the values given in

Table 9: General operating conditions on page 37 .

The maximum chip-junction temperature, T

J using the following equation:

max, in degrees Celsius, may be calculated

max = T

max + (P

max × Θ

)

Where:

• T

max is the maximum ambient temperature in ° C,

• Θ

is the package junction-to-ambient thermal resistance, in ° C/W,

• P

max is the sum of P

INT

max and P

I/O max (P

max = P

INT

max + P

I/O max),

• P

INT

max is the product of I

DD and internal power.

, expressed in Watts. This is the maximum chip

I/O

max represents the maximum power dissipation on output pins where:

I/O

max = Σ (V

× I

) + Σ ((V

– V

) × I

), taking into account the actual V

OL application.

/ I

and V

/ I

OH of the I/Os at low and high level in the

S ymbol

Table 61. Package thermal characteristics

Parameter

Thermal resistance junction-ambient

LQFP100 - 14 × 14 mm / 0.5 mm pitch

Thermal resistance junction-ambient

LQFP64 - 10 × 10 mm / 0.5 mm pitch

Thermal resistance junction-ambient

LFBGA100 - 10 × 10 mm / 0.8 mm pitch

Thermal resistance junction-ambient

LQFP100 - 14 × 14 mm / 0.5 mm pitch

Thermal resistance junction-ambient

LQFP64 - 10 × 10 mm / 0.5 mm pitch

Value

Unit

°C/W

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural

Convection (Still Air). Available from www.jedec.org.

DocID15274 Rev 10 91/108

107

Package information

6.4.2 Selecting the product temperature range

STM32F105xx, STM32F107xx

When ordering the microcontroller, the temperature range is specified in the ordering

information scheme shown in Table 62: Ordering information scheme .

Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature.

As applications do not commonly use the STM32F103xx at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application.

The following examples show how to calculate the temperature range needed for a given application.

Example 1: High-performance application

Assuming the following application conditions:

Maximum ambient temperature T

Amax

DDmax

= 50 mA, V

= 82 °C (measured according to JESD51-2),

= 3.5 V, maximum 20 I/Os used at the same time in output at low level with I

= 8 mA, V

= 0.4 V and maximum 8 I/Os used at the same time in output at low level with I

= 20 mA, V

= 1.3 V

INTmax

= 50 mA × 3.5 V= 175 mW

IOmax

= 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW

This gives: P

INTmax

= 175 mW and P

IOmax

= 272 mW:

Dmax

= 175 + 272 = 447 mW

Thus: P

Dmax

= 447 mW

Using the values obtained in Table 61

Jmax

is calculated as follows:

– For LQFP100, 46 °C/W

Jmax

= 82 °C + (46 °C/W × 447 mW) = 82 °C + 20.6 °C = 102.6 °C

This is within the range of the suffix 6 version parts (–40 < T

< 105 °C).

In this case, parts must be ordered at least with the temperature range suffix 6 (see

Table 62: Ordering information scheme ).

Example 2: High-temperature application

Using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature T

J specified range.

remains within the

Assuming the following application conditions:

Maximum ambient temperature T

Amax

DDmax

= 20 mA, V

= 115 °C (measured according to JESD51-2),

= 3.5 V, maximum 20 I/Os used at the same time in output at low level with I

= 8 mA, V

= 0.4 V

INTmax

= 20 mA × 3.5 V= 70 mW

IOmax

= 20 × 8 mA × 0.4 V = 64 mW

This gives: P

INTmax

= 70 mW and P

IOmax

= 64 mW:

Dmax

= 70 + 64 = 134 mW

Thus: P

Dmax

= 134 mW

92/108 DocID15274 Rev 10

STM32F105xx, STM32F107xx Package information

Using the values obtained in Table 61

Jmax

is calculated as follows:

– For LQFP100, 46 °C/W

Jmax

= 115 °C + (46 °C/W × 134 mW) = 115 °C + 6.2 °C = 121.2 °C

This is within the range of the suffix 7 version parts (–40 < T

< 125 °C).

In this case, parts must be ordered at least with the temperature range suffix 7 (see

Table 62: Ordering information scheme ).

Figure 49. LQFP100 P

max vs. T

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DocID15274 Rev 10 93/108

107

Part numbering STM32F105xx, STM32F107xx

Table 62. Ordering information scheme

STM32 F 105 R C Example:

Device family

STM32 = ARM-based 32-bit microcontroller

Product type

F = general-purpose

Device subfamily

105 = connectivity, USB OTG FS

107 = connectivity, USB OTG FS & Ethernet

Pin count

R = 64 pins

V = 100 pins

Flash memory size

8 = 64 Kbytes of Flash memory

B = 128 Kbytes of Flash memory

C = 256 Kbytes of Flash memory

Package

H = BGA

T = LQFP

Temperature range

6 = Industrial temperature range, –40 to 85 °C.

7 = Industrial temperature range, –40 to 105 °C.

Software option

Internal code or Blank

Options xxx = programmed parts

Packing

Blank = tray

TR = tape and reel

T 6 V xxx TR

For a list of available options (speed, package, etc.) or for further information on any aspect of this device, contact your nearest ST sales office.

94/108 DocID15274 Rev 10

STM32F105xx, STM32F107xx

Appendix A Application block diagrams

Application block diagrams

A.1 USB OTG FS interface solutions

Figure 50. USB OTG FS device mode

34-&XX34-&XX

/4'0(9

53"

&ULLSPEED

TRANSCEIVER

53"

/4'

&ULLSPEED

CORE

"53

4OHOST

"53

$$ 6TO6$$

2EGULATOR

AIB

1. Use a regulator if you want to build a bus-powered device.

34-&XX34-&XX

Figure 51. Host connection

/4'0(9

53"

FULLSPEED

LOWSPEED

TRANSCEIVER

53"

/4'

&ULLSPEED

CORE

"53

'0)/

'0)/)21

/62#2

FLAG

#URRENTLIMITED

POWERDISTRIBUTION

SWITCH

34-03342

1. STMPS2141STR needed only if the application has to support bus-powered devices.

DocID15274 Rev 10

AIB

95/108

107

Application block diagrams STM32F105xx, STM32F107xx

Figure 52. OTG connection (any protocol)

S TM 3 2F105xx/ S TM 3 2F107xx

OTG PHY

U S B full-speed/ low-speed transceiver

U S B

OTG

Full-speed core

BU S

S RP

GPIO

GPIO + IRQ

OVRCR flag

Current-limited power distribution switch

S TMP S 2141 S TR

(1)

5 V

1. STMPS2141STR needed only if the application has to support bus-powered devices.

ai15655b

96/108 DocID15274 Rev 10

STM32F105xx, STM32F107xx Application block diagrams

MCU

HCLK (1)

Figure 53. MII mode using a 25 MHz crystal

STM32F107xx

Ethernet

MAC 10/100

TIM2

IEEE1588 PTP

Timer inp u t trigger Time s t a mp comp a r a tor

MII_TX_CLK

MII_TX_EN

MII_TXD[3:0]

MII_CRS

MII_COL

MII_RX_CLK

MII_RXD[3:0]

MII_RX_DV

MII_RX_ER

MDIO

MDC

PPS_OUT

(2)

MII

= 15 pin s

Ethernet

PHY 10/100

MII + MDC

= 17 pin s

XTAL

25 MHz

OSC

PLL HCLK

PHY_CLK 25 MHz

XT1 a i15656

1. HCLK must be greater than 25 MHz.

2. Pulse per second when using IEEE1588 PTP, optional signal.

Figure 54. RMII with a 50 MHz oscillator

STM32F107xx

MCU

HCLK

(1)

Ethernet

MAC 10/100

TIM2

IEEE1588 PTP

Timer inp u t trigger Time s t a mp comp a r a tor

RMII_TX_EN

RMII_TXD[1:0]

RMII_RXD[1:0]

RMII_CRX_DV

RMII_REF_CLK

MDIO

MDC

Ethernet

PHY 10/100

RMII

= 7 pin s

RMII + MDC

= 9 pin s

OSC

50 MHz

2.5 or 25 MHz

/2 or /20 s ynchrono us 50 MHz

PLL HCLK

PHY_CLK 50 MHz XT1 50 MHz a i15657

1. HCLK must be greater than 25 MHz.

DocID15274 Rev 10 97/108

107

Application block diagrams STM32F105xx, STM32F107xx

Figure 55. RMII with a 25 MHz crystal and PHY with PLL

MCU

STM32F107xx

Ethernet

MAC 10/100

HCLK

(1)

IEEE1588 PTP

TIM2

Timer inp u t trigger Time s t a mp comp a r a tor

RMII_TX_EN

RMII_TXD[1:0]

RMII_RXD[1:0]

RMII_CRX_DV

RMII_REF_CLK

MDIO

MDC

Ethernet

PHY 10/100

RMII

= 7 pin s

REF_CLK RMII + MDC

= 9 pin s

XTAL

25 MHz

2.5 or 25 MHz

/2 or /20 s ynchrono us 50 MHz

OSC

PLL

HCLK

PHY_CLK 25 MHz XT1

PLL a i15658

1. HCLK must be greater than 25 MHz.

Figure 56. RMII with a 25 MHz crystal

S TM 3 2F107xx

MCU

HCLK

Ethernet

MAC 10/100

TIM2

Timer input trigger

IEEE15 88 PTP

Time stamp comparator

50 MHz

RMII_TX_EN

RMII_TXD[1:0]

RMII_RXD[1:0]

RMII_CRX_DV

RMII_REF_CLK

MDIO

MDC

Ethernet

PHY 10/100

RMII

= 7 pins

50 MHz

RMII + MDC

= 9 pins

XTAL

25 MHz

O S C PLL S

50 MHz

XT1/XT2

N S DP 838 4 8 (1) ai15659b

1. The NS DP83848 is recommended as the input jitter requirement of this PHY. It is compliant with the output jitter specification of the MCU.

98/108 DocID15274 Rev 10

STM32F105xx, STM32F107xx

A.3 Complete audio player solutions

Application block diagrams

Two solutions are offered, illustrated in

Figure 57 and Figure 58 .

Figure 57

shows storage media to audio DAC/amplifier streaming using a software Codec.

This solution implements an audio crystal to provide audio class I

S accuracy on the master clock (0.5% error maximum, see the Serial peripheral interface section in the reference manual for details).

XTAL

14.7456 MHz

USB

M ass s tor a ge device

MMC/

SDC a rd

Figure 57. Complete audio player solution 1

STM32F105/STM32F107

OTG

(ho s t mode) +

PHY

SPI

Cortex-M3 core

72 MHz

Progr a m memory

File

Sy s tem

A u dio

CODEC

U s er a pplic a tion

SPI

GPIO

I2S

LCD to u ch s creen

Control bu tton s

DAC +

A u dio a mpli

Figure 58

shows storage media to audio Codec/amplifier streaming with SOF synchronization of input/output audio streaming using a hardware Codec.

Figure 58. Complete audio player solution 2

STM32F105/STM32F107

XTAL

14.7456 MHz

Cortex-M3 core

72 MHz

Progr a m memory

SPI

GPIO

LCD to u ch s creen

Control bu tton s

USB

M ass s tor a ge device

OTG

PHY

File

Sy s tem

I2S

SOF

U s er a pplic a tion

MMC/

SDC a rd

SPI

A u dio

CODEC

A u dio a mpli

SOF s ynchroniz a tion of inp u t/o u tp u t au dio s tre a ming a i15660 a i15661

DocID15274 Rev 10 99/108

107

Application block diagrams

A.4

STM32F105xx, STM32F107xx

USB OTG FS interface + Ethernet/I

2

S interface solutions

With the clock tree implemented on the STM32F107xx, only one crystal is required to work with both the USB (host/device/OTG) and the Ethernet (MII/RMII) interfaces.

Figure 59

illustrate the solution.

Figure 59. USB O44TG FS + Ethernet solution

34-&-#5

-(Z

84!,

$IV

0,,-5,

5PTO-(Z 393#,+

%THERNET

0(9

-#/

$IV

3EL

0,,-5,

5PTO-(Z

0,,-5,

0,,6#/

X0,,#,+

$IV

/4'

-(Z

53"

0(9

ACCURACY

3EL

-36

With the clock tree implem1ented on the STM32F107xx, only one crystal is required to work with both the USB (host/device/OTG) and the I 2 S (Audio) interfaces.

Figure 60

illustrate the solution.

Figure 60. USB OTG FS + I 2 S (Audio) solution

-(Z

84!,

%THERNET

0(9

-#/

$IV

0,,-5,

34-&34-&-#5

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0,,6#/

X0,,#,+

5PTO-(Z

,ESSTHANACCURACY

ON-#,+AND3#,+

-#,+

3#,+

-36

100/108 DocID15274 Rev 10

STM32F105xx, STM32F107xx Application block diagrams

Application

Table 63. PLL configurations

Crystal value in

MHz

(XT1)

PREDIV2 PLL2MUL PLLSRC PREDIV1 PLLMUL

USB prescaler

(PLLVCO output)

PLL3MUL

I2Sn clock input

MCO (main clock output)

Ethernet only

Ethernet + OTG

+ basic audio

Ethernet + OTG 25

Ethernet + OTG

+ Audio class

2 S (1)

14.7456

PLL2ON x8

PLL2ON x12

PLL2OFF

PLL2

XT1

PLLON x9

PLLON x6.5

PLLON x9

PLL3ON x10

XT1 (MII)

PLL3 (RMII)

XT1 (MII)

PLL3 (RMII)

PLL3ON x10

PLL3ON x20

PLL

XT1 (MII)

PLL3 (RMII)

PLL3

VCO

Out

ETH PHY must use its own crystal

PLL3OFF NA NA OTG only

OTG + basic audio

8 NA PLL2OFF XT1 /1 PLLON x9 /3 PLL3OFF PLL NA

OTG + Audio class I 2 S (1)

14.7456

Audio class I 2 S only (1)

14.7456

PLL2ON x12

PLL2

PLLON x6.5

PLL3ON x20

PLL3

VCO

Out

PLL3

VCO out

1. SYSCLK is set to be at 72 MHz except in this case where SYSCLK is at 71.88 MHz.

Table 64 give the I

Table 63 .

run mode values that correspond to the conditions specified in

DocID15274 Rev 10 101/108

107

Application block diagrams STM32F105xx, STM32F107xx

Table 64. Applicative current consumption in Run mode, code with data processing running from Flash

Symbol parameter Conditions

(1)

Typ

(2)

Max

(2)

Unit

85 °C 105 °C

External clock, all peripherals enabled except ethernet,

HSE = 8 MHz, f

HCLK

MCO

= 72 MHz, no

External clock, all peripherals enabled except ethernet,

HSE = 14.74 MHz, f

HCLK

MCO

= 72 MHz, no

External clock, all peripherals enabled except OTG,

HSE = 25 MHz, f

HCLK

= 25 MHz

= 72 MHz, MCO

Supply current in run mode

External clock, all peripherals enabled,

HSE = 25 MHz, f

HCLK

= 25 MHz

= 72 MHz, MCO

External clock, all peripherals enabled,

HSE = 25 MHz, f

HCLK

= 50 MHz

= 72 MHz, MCO

External clock, all peripherals enabled,

HSE = 50 MHz

(3)

, f

HCLK

= 72 MHz, no

MCO

External clock, only OTG enabled,

HSE = 8 MHz, f

HCLK

MCO

= 48 MHz, no

External clock, only ethernet enabled,

HSE = 25 MHz, f

HCLK

= 25 MHz

= 25 MHz, MCO

1. V

= 3.3 V.

2. Based on characterization, not tested in production.

3. External oscillator.

60.5

62.5

60.7

65.5

69.7

67.5

26.7

None None

14.3

None None mA

102/108 DocID15274 Rev 10

STM32F105xx, STM32F107xx Revision history

Date

18-Dec-2008

20-Feb-2009

Revision

Table 65. Document revision history

Changes

Initial release.

I/O information clarified on page 1 . Figure 4: STM32F105xxx and

STM32F107xxx connectivity line BGA100 ballout top view corrected.

Section 2.3.8: Boot modes

updated.

PB4, PB13, PB14, PB15, PB3/TRACESWO moved from Default

column to Remap column, plus small additional changes in Table 5:

Pin definitions .

Consumption values modified in

Section 5.3.5: Supply current characteristics

Note modified in Table 13: Maximum current consumption in Run mode, code with data processing running from Flash and

Table 15:

Maximum current consumption in Sleep mode, code running from

Flash or RAM

Table 20: High-speed external user clock characteristics and

Table 21: Low-speed external user clock characteristics modified.

Table 27: PLL characteristics modified and Table 28: PLL2 and PLL3 characteristics

added.

DocID15274 Rev 10 103/108

107

Revision history STM32F105xx, STM32F107xx

Date

19-Jun-2009

Table 65. Document revision history (continued)

Revision Changes

Section 2.3.8: Boot modes

and Section 2.3.20: Ethernet MAC interface with dedicated DMA and IEEE 1588 support

updated.

Section 2.3.24: Remap capability added.

Figure 1: STM32F105xx and STM32F107xx connectivity line block diagram and

Figure 5: Memory map

updated.

Table 13: Maximum current consumption in Run mode, code with data processing running from Flash , Table 14: Maximum current consumption in Run mode, code with data processing running from

– I2S3_WS, I2S3_CK and I2S3_SD default alternate functions added

– small changes in signal names

–

Note 6

modified

– ETH_MII_PPS_OUT and ETH_RMII_PPS_OUT replaced by

ETH_PPS_OUT

– ETH_MII_MDIO and ETH_RMII_MDIO replaced by ETH_MDIO

– ETH_MII_MDC and ETH_RMII_MDC replaced by ETH_MDC

Figures: Typical current consumption in Run mode versus frequency

(at 3.6 V) - code with data processing running from RAM, peripherals enabled and Typical current consumption in Run mode versus frequency (at 3.6 V) - code with data processing running from RAM, peripherals disabled removed.

RAM and

Table 15: Maximum current consumption in Sleep mode, code running from Flash or RAM are to be determined.

Figure 12 and Figure 13 show typical curves. PLL1 renamed to PLL.

supply current in Stop mode modified in

Table 16: Typical and maximum current consumptions in Stop and Standby modes

Figure 11: Typical current consumption in Stop mode with regulator in Run mode versus temperature at different VDD values ,

Figure 13:

Typical current consumption in Standby mode versus temperature at different VDD values and Figure 13: Typical current consumption in

Standby mode versus temperature at different VDD values

updated.

Table 17: Typical current consumption in Run mode, code with data processing running from Flash

Table 18: Typical current consumption in Sleep mode, code running from Flash or RAM

and

Table 19: Peripheral current consumption updated.

HSE_ext

modified in Table 20: High-speed external user clock characteristics

Min PLL input clock (f

PLL_IN

), f

PLL_OUT

min and f modified in

Table 27: PLL characteristics

PLL_VCO min

ACC

HSI

max values modified in Table 24: HSI oscillator characteristics

Table 31: EMS characteristics

and Table 32: EMI characteristics

updated. Table 43: SPI characteristics

updated.

Modified: Figure 28: I2S slave timing diagram (Philips protocol)(1) ,

Figure 29: I2S master timing diagram (Philips protocol)(1)

and

Figure 31: Ethernet SMI timing diagram

BGA100 package removed.

Section 6.4: Thermal characteristics

added. Small text changes.

104/108 DocID15274 Rev 10

STM32F105xx, STM32F107xx Revision history

Date

14-Sep-2009

Table 65. Document revision history (continued)

Revision Changes

Document status promoted from Preliminary data to full datasheet.

Number of DACs corrected in

Table 3: STM32F105xx and

STM32F107xx family versus STM32F103xx family

Note 5

added in Table 5: Pin definitions .

RERINT

voltage

and T

Coeff

added to Table 12: Embedded internal reference

Values added to Table 13: Maximum current consumption in Run mode, code with data processing running from Flash , Table 14:

Maximum current consumption in Run mode, code with data processing running from RAM and

Table 15: Maximum current consumption in Sleep mode, code running from Flash or RAM .

Typical I

DD_VBAT

value added in Table 16: Typical and maximum current consumptions in Stop and Standby modes

Figure 10: Typical current consumption on VBAT with RTC on vs. temperature at different VBAT values added.

Values modified in

Table 17: Typical current consumption in Run mode, code with data processing running from Flash and

Table 18:

Typical current consumption in Sleep mode, code running from Flash or RAM

HSE_ext

min modified in Table 20: High-speed external user clock characteristics

and C

replaced by C in Table 22: HSE 3-25 MHz oscillator characteristics

and Table 23: LSE oscillator characteristics (fLSE =

32.768 kHz) , notes modified and moved below the tables.

Note 1 modified below

Figure 16: Typical application with an 8 MHz crystal .

Conditions removed from Table 26: Low-power mode wakeup timings .

Standards modified in Section 5.3.10: EMC characteristics on page 54

, conditions modified in Table 31: EMS characteristics

Jitter maximum values added to Table 27: PLL characteristics and

Table 28: PLL2 and PLL3 characteristics

and R

modified in Table 36: I/O static characteristics .

Condition added for V

NF(NRST) parameter in

Table 39: NRST pin characteristics

. Note removed and R

, R

values added in

Table 46: USB OTG FS DC electrical characteristics

Table 48: Ethernet DC electrical characteristics added.

Parameter values added to

Table 49: Dynamic characteristics:

Ethernet MAC signals for SMI

, Table 50: Dynamic characteristics:

Ethernet MAC signals for RMII and

Table 51: Dynamic characteristics: Ethernet MAC signals for MII .

ADC

and R

AIN

parameters modified in

Table 52: ADC characteristics

. R

AIN

fADC = 14 MHz .

max values modified in Table 53: RAIN max for

Table 56: DAC characteristics

modified. Figure 38: 12-bit buffered

/non-buffered DAC

added.

Table 64: Applicative current consumption in Run mode, code with data processing running from Flash

added.

Small text changes.

DocID15274 Rev 10 105/108

107

Revision history STM32F105xx, STM32F107xx

Date

11-May-2010

01-Aug-2011

06-Mar-2014

Table 65. Document revision history (continued)

Revision Changes

Added BGA package.

Table 36: I/O static characteristics on page 57

ETH_RMII_RXD0 and ETH_RMII_RXD1 added in remap column for

PD9 and PD10, respectively.

Note added to ETH_MII_RX_DV, ETH_MII_RXD0, ETH_MII_RXD1,

ETH_MII_RXD2 and ETH_MII_RXD3

Updated

Added

Figure 18: Standard I/O input characteristics - CMOS port

Figure 21: 5 V tolerant I/O input characteristics - TTL port

Updated

Table 43: SPI characteristics on page 66

Updated

Table 44: I2S characteristics on page 69 .

Updated

Table 48: Ethernet DC electrical characteristics on page 72 .

Updated

Table 49: Dynamic characteristics: Ethernet MAC signals for SMI on page 72

Updated

Table 50: Dynamic characteristics: Ethernet MAC signals for RMII on page 73

Updated

Figure 59: USB O44TG FS + Ethernet solution on page 100 .

Updated

Figure 60: USB OTG FS + I2S (Audio) solution on page 100

Changed SRAM size to 64 KB on all parts.

Updated PD0 and PD1 description in

Table 5: Pin definitions on page 27

Updated footnotes below

Table 6: Voltage characteristics on page 36 and Table 7: Current characteristics on page 36

Updated tw min in

Table 20: High-speed external user clock characteristics on page 47

Updated startup time in

Table 23: LSE oscillator characteristics (fLSE

= 32.768 kHz) on page 50

Added

Section 5.3.12: I/O current injection characteristics on page 56

Updated

Table 36: I/O static characteristics on page 57

Add Interna code V to Table 62: Ordering information scheme on page 94

Added a “Packing” entry to Table 62: Ordering information scheme

including “Blank = tray” and “TR = Tape and reel”.

Referenced 4 Figures: Figure 41

Figure 49

, Figure 59 and

Figure 60 .

Updated the “Package” line with “BGA100” in

Table 2:

STM32F105xx and STM32F107xx features and peripheral counts .

106/108 DocID15274 Rev 10

STM32F105xx, STM32F107xx Revision history

Date

06-Mar-2015

3-Sept-2015

22-Mar-2017

Table 65. Document revision history (continued)

Revision Changes

Updated

Table 40: LFBGA100 – 100-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package mechanical data

Table 59: LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data

and Table 60: LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data

Updated

Figure 14: High-speed external clock source AC timing diagram ;

Figure 39: LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package outline ,

Figure 43: LQFP100 – 14 x 14 mm

100 pin low-profile quad flat package outline ,

Figure 44: LQFP100 -

100-pin, 14 x 14 mm low-profile quad flat recommended footprint ,

Figure 46: LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline

and Figure 47: LQFP64 - 64-pin, 10 x 10 mm lowprofile quad flat recommended footprint

Added

Figure 45: LQFP100 marking example (package top view) ,

Figure 48: LQFP64 marking example (package top view)

Updated:

–

Table 19: Peripheral current consumption

–

Figure 44: LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint

–

Table 58: LFBGA100 recommended PCB design rules (0.8 mm pitch BGA)

Updated:

–