STMicroelectronics STM32F100RE Datasheet

STM32F100xC STM32F100xD

STM32F100xE

High-density value line, advanced Arm

®

-based 32-bit MCU with

256 to 512 KB Flash, 16 timers, ADC, DAC & 11 comm interfaces

Datasheet

−

production data

Features

• Core: Arm ® 32-bit Cortex ® -M3 CPU

– 24 MHz maximum frequency, 1.25 DMIPS

/MHz (Dhrystone 2.1) performance

– Single-cycle multiplication and hardware division

• Memories

– 256 to 512 Kbytes of Flash memory

– 24 to 32 Kbytes of SRAM

– Flexible static memory controller with 4

Chip Selects. Supports SRAM, PSRAM and NOR memories

– LCD parallel interface, 8080/6800 modes

• Clock, reset and supply management

– 2.0 to 3.6 V application supply and I/Os

– POR, PDR and programmable voltage detector (PVD)

– 4-to-24 MHz crystal oscillator

– Internal 8 MHz factory-trimmed RC

– Internal 40 kHz RC

– PLL for CPU clock

– 32 kHz oscillator for RTC with calibration

• Low power

– Sleep, Stop and Standby modes

– V

BAT

supply for RTC and backup registers

• Serial wire debug (SWD) and JTAG I/F

• DMA

– 12-channel DMA controller

– Peripherals supported: timers, ADC, SPIs,

I 2 Cs, USARTs and DACs

• 1 × 12-bit, 1.2 µs A/D converter (up to 16 ch.)

– Conversion range: 0 to 3.6 V

– Temperature sensor

• 2 × 12-bit D/A converters

• Up to 112 fast I/O ports

– 51/80/112 I/Os, all mappable on 16 external interrupt vectors and almost all

5 V-tolerant

LQFP144

20 × 20 mm

LQFP100

14 × 14 mm

LQFP64

10 × 10 mm

• Up to 16 timers

– Up to seven 16-bit timers, each with up to 4

IC/OC/PWM or pulse counter

– One 16-bit, 6-channel advanced-control timer: up to 6 channels for PWM output, dead time generation and emergency stop

– One 16-bit timer, with 2 IC/OC, 1

OCN/PWM, dead-time generation and emergency stop

– Two 16-bit timers, each with

IC/OC/OCN/PWM, dead-time generation and emergency stop

– Two watchdog timers

– SysTick timer: 24-bit downcounter

– Two 16-bit basic timers to drive the DAC

• Up to 11 communications interfaces

– Up to two I 2 C interfaces (SMBus/PMBus)

– Up to 3 USARTs (ISO 7816 interface, LIN,

IrDA capability, modem control)

– Up to 2 UARTs

– Up to 3 SPIs (12 Mbit/s)

– Consumer electronics control (CEC) I/F

• CRC calculation unit, 96-bit unique ID

Table 1. Device summary

Reference Part number

STM32F100xC

STM32F100xD

STM32F100xE

STM32F100RC, STM32F100VC,

STM32F100ZC

STM32F100RD, STM32F100VD,

STM32F100ZD

STM32F100RE, STM32F100VE,

STM32F100ZE

October 2018

This is information on a product in full production.

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Contents

Contents

STM32F100xC, STM32F100xD, STM32F100xE

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1

Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

2.2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2.1

2.2.2

2.2.3

2.2.4

2.2.5

2.2.6

2.2.7

Arm® Cortex®-M3 core with embedded Flash and SRAM . . . . . . . . . . 14

Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 14

Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

FSMC (flexible static memory controller) . . . . . . . . . . . . . . . . . . . . . . . . 14

LCD parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 15

2.2.8

2.2.9

External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 15

Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.2.10

Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.2.11

Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.2.12

Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.2.13

Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.2.14

Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.2.15

DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.2.16

RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 17

2.2.17

Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.2.18

I

²

C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.2.19

Universal synchronous/asynchronous receiver transmitter (USART) . . 20

2.2.20

Universal asynchronous receiver transmitter (UART) . . . . . . . . . . . . . . 20

2.2.21

Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.2.22

HDMI (high-definition multimedia interface) consumer electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.2.23

GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 21

2.2.24

Remap capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.2.25

ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.2.26

DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.2.27

Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.2.28

Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 22

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Contents

Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.1

Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.1.1

5.1.2

5.1.3

5.1.4

5.1.5

5.1.6

5.1.7

Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5.2

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5.3

Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5.3.1

5.3.2

5.3.3

5.3.4

5.3.5

5.3.6

5.3.7

5.3.8

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 39

Embedded reset and power control block characteristics . . . . . . . . . . . 40

Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

5.3.9

Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

5.3.10

FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

5.3.11

EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

5.3.12

Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 69

5.3.13

I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

5.3.14

I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

5.3.15

NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

5.3.16

TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

5.3.17

Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

5.3.18

12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

5.3.19

DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

5.3.20

Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

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6.1

LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

6.2

LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

6.3

LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

6.4

Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

6.4.1

6.4.2

Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 102

Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

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List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

STM32F100xx features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

High-density STM32F100xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 9.

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 10.

Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 11.

Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 12.

Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 13.

Maximum current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 14.

Maximum current consumption in Run mode, code with data processing running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 15.

STM32F100xxB maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 16.

Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 44

Table 17.

Typical current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 18.

Typical current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . 46

Table 19.

Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 20.

High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 21.

Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 22.

HSE 4-24 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 23.

LSE oscillator characteristics (f

LSE

= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 24.

HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 25.

LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 26.

Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 27.

PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 28.

Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 29.

Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 30.

Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . 58

Table 31.

Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . 59

Table 32.

Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 33.

Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 34.

Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 35.

Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 36.

Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 37.

Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 38.

EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 39.

EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 40.

ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 41.

Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 42.

I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 43.

I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 44.

Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

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Table 45.

I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 46.

NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 47.

TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 48.

I

2 C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 49.

SCL frequency (f

PCLK1

= 24 MHz, V

DD

= 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 50.

SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 51.

ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 52.

R

AIN

max for f

ADC

= 12 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 53.

ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 54.

ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 55.

DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 56.

TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 57.

LQFP - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 58.

LQPF - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 59.

LQFP - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 60.

Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Table 61.

Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 62.

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

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STM32F100xC, STM32F100xD, STM32F100xE

List of figures

List of figures

Figure 1.

STM32F100 Value Line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 2.

Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 3.

STM32F100 Value Line LQFP144 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 4.

STM32F100 Value Line LQFP100 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 5.

STM32F100 Value Line in LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 6.

Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 7.

Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 8.

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 9.

Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 10.

Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 11.

High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 12.

Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 13.

Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 14.

Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 15.

Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . . 57

Figure 16.

Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . . 59

Figure 17.

Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 18.

Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 19.

Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 20.

Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 21.

Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 22.

Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 23.

Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 24.

Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 25.

5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 26.

5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 27.

I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 28.

Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 29.

I

2

C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 30.

SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 31.

SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 32.

SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 33.

ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 34.

Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 35.

Power supply and reference decoupling (V

Figure 36.

Power supply and reference decoupling (V

REF+

REF+ not connected to V

DDA connected to V

DDA

). . . . . . . . . . . . . . 87

). . . . . . . . . . . . . . . . . 87

Figure 37.

12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 38.

LQFP - 144-pin, 20 x 20 mm low-profile quad flat package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 39.

LQFP - 144-pin, 20 x 20 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 40.

LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 41.

LQFP – 14 x 14 mm 100 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 95

Figure 42.

LQFP - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 43.

LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Figure 44.

LQFP - 64 pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 98

Figure 45.

LQFP - 64-pin, 10 x 10 mm low-profile quad flat recommended footprint . . . . . . . . . . . . . 99

DS5944 Rev 11

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8

List of figures STM32F100xC, STM32F100xD, STM32F100xE

Figure 46.

LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Figure 47.

LQFP100 P

D

max vs. T

A

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

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DS5944 Rev 11

STM32F100xC, STM32F100xD, STM32F100xE

1 Introduction

Introduction

This datasheet provides the ordering information and mechanical device characteristics of the STM32F100xC, STM32F100xD and STM32F100xE value line microcontrollers. In the rest of the document, the STM32F100xC, STM32F100xD and STM32F100xE are referred to as high-density value line devices.

This STM32F100xC, STM32F100xD and STM32F100xE datasheet should be read in conjunction with the STM32F100xx high-density Arm ® -based 32-bit MCUs reference manual (RM0059) . For information on programming, erasing and protection of the internal

Flash memory please refer to the STM32F100xx high-density value line Flash programming manual (PM0072). The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com

.

For information on the Arm ®(a) Cortex ® -M3 core, please refer to the Cortex ® -M3 Technical

Reference Manual, available from the www.arm.com website.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

DS5944 Rev 11

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34

Description

2 Description

STM32F100xC, STM32F100xD, STM32F100xE

The STM32F100 Value Line family incorporates the high-performance Arm ® Cortex ® -M3

32-bit RISC core operating at a 24 MHz frequency, high-speed embedded memories (Flash memory up to 512 Kbytes and SRAM up to 32 Kbytes), a flexible static memory control

(FSMC) interface (for devices offered in packages of 100 pins and more) and an extensive range of enhanced peripherals and I/Os connected to two APB buses. All devices offer standard communication interfaces (up to two I 2 Cs, three SPIs, one HDMI CEC, up to three

USARTs and 2 UARTS), one 12-bit ADC, two 12-bit DACs, up to 9 general-purpose 16-bit timers and an advanced-control PWM timer.

The STM32F100xx high-density value line family operates in the –40 to +85 °C and –40 to

+105 °C temperature ranges, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving mode allows the design of low-power applications.

The STM32F100 Value Line family includes devices in three different packages ranging from 64 pins to 144 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family.

These features make the STM32F100xx value line microcontroller family suitable for a wide range of applications such as motor drives, application control, medical and handheld equipment, PC and gaming peripherals, GPS platforms, industrial applications, PLCs, inverters, printers, scanners, alarm systems, video intercoms, and HVACs.

10/107

DS5944 Rev 11

STM32F100xC, STM32F100xD, STM32F100xE Description

Flash - Kbytes

SRAM - Kbytes

FSMC

Advanced-control

Timers

General-purpose

SPI

I

2

C

Communication interfaces

USART

UART

CEC

12-bit synchronized ADC number of channels

GPIOs

12-bit DAC

Number of channels

CPU frequency

Operating voltage

Packages

Peripheral

Operating temperatures

Table 2. STM32F100xx features and peripheral counts

STM32F100Rx

256

24

2

3

10

3

384

32

No

1

2

1

1

16 channels

51

2

2

512

32

STM32F100Vx

256

24

2

3

10

3

384

32

Yes

(1)

1

2

1

1

16 channels

80

2

2

24 MHz

512

32

2.0 to 3.6 V

Ambient operating temperature: –40 to +85 °C /–40 to +105 °C

Junction temperature: –40 to +125 °C

LQFP64 LQFP100 LQFP144

STM32F100Zx

256

24

2

3

10

3

384

32

Yes

1

2

1

1

16 channels

112

2

2

512

32

1. For the LQFP100 package, only FSMC Bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory.

DS5944 Rev 11

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34

Description STM32F100xC, STM32F100xD, STM32F100xE

Figure 1. STM32F100 Value Line block diagram

TRACECLK

TRACED[0:3] as AF

NJTRST

JTDI

JTCK/SWCLK

JTMS/SWDIO

JTDO as AF

A[25:0]

D[15:0]

CLK

NOE

NWE

NE[3:0]

NBL[1:0]

NWAIT

NADV as AF

80 AF

PA[15:0]

PB[15:0]

PC[15:0]

PD[15:0]

PE[15:0]

PF[15:0]

PG[15:0]

2 channels, 1 compl. channel and BKIN as AF

1 channel, 1 compl. channel and BKIN as AF

1 channel, 1 compl. channel and BKIN as AF

4 channels, 3 compl. channels,

ETR and BKIN as AF

MOSI, MISO, SCK, NSS as AF

RX, TX, CTS, RTS, CK as AF

16 ADC channels

(ADC_INx)

V

REF+

V

REF–

F

JTAG & SW

Cortex-M3 CPU max

: 24 MHz

NVIC

GP DMA

12 channels

FSMC

EXT.I T

WKUP

GPIO port A

GPIO port B

GPIO port C

GPIO port D pbus

Dbus

Ibus

System

Trace controller

Flash 512 KB

32 bit

SRAM

32 KB

Reset & clock control

PCLK1

PCLK2

HCLK

FCLK

@VDDA

RC HS

RC LS

POR

Reset

Int

PLL

V

DD18

Power

Voltage reg.

3.3 V to 1.8 V

@VDD33

Supply supervision

POR / PDR

PVD

@VDDA

@VDD

XTAL OSC

4-24 MHz

IWDG

Standby

interface

@V

BAT

XTAL 32 kHz

RTC

AWU

Backup register

Backup interface

AHB2

APB 2

AHB2

APB1

TIM2

TIM3

GPIO port E

GPIO port F

GPIO port G

TIM15

TIM4

TIM5

TIM12

TIM16

TIM17

TIM13

TIM14

TIM1

USART2

USART3

SPI1

UART4

USART1

Temp sensor

UART5

SPI2

WWDG

12-bit ADC1 IF SPI3

@VDDA

TIM6

TIM7

HDMI CEC

I2C1

I2C2

V

DD

V

SS

= 2.0 V to 3.6 V

NRST

VDDA

VSSA

OSC_IN

OSC_OUT

V

BA T

= 1.8 V to 3.6 V

OSC32_IN

OSC32_OUT

TAM PER-RTC

(ALARM OUT)

4 channels as AF

4 channels as AF

4 channels as AF

4 channels

2 channels as AF

1 channel as AF

1 channel as AF

RX,TX, CTS, RTS,

CK as AF

RX,TX, CTS, RTS,

CK as AF

RX,TX, CTS, RTS,

CK as AF

RX,TX, CTS, R

CK as AF

MOSI, MISO,

SCK, NSS as AF

MOSI, MISO,

SCK, NSS as AF

HDMI CEC as AF

SCL, SDA, SMBA as AF

SCL, SDA, SMBA as AF

12-bit DAC1

IF

12-bit DAC2

@VDDA

DAC1_OUT as AF

DAC2 _OUT as AF ai17515b

1. AF = alternate function on I/O port pin.

2. T = –40 °C to +85 °C (junction temperature up to 105 °C) or T up to 125 °C).

A

= –40 °C to +105 °C (junction temperature

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DS5944 Rev 11

STM32F100xC, STM32F100xD, STM32F100xE Description

/3#?/54

/3#?).

/3#?).

/3#?/54

Figure 2. Clock tree

-(Z

(3%/3#

&,)4&#,+

TO&LASHPROGRAMMINGINTERFACE

-(Z

(3)2#

0,,32#

,3%/3#

K(Z

(3)

0,,-5,

X

XXX

0,,

02%$)6

,3%

(3)

0,,#,+

(3%

37

#33

393#,+ !("

0RESCALER

-(Z

MAX

TO24#

0ERIPHERALCLOCK

%NABLE

&3-#,+

TO&3-#

-(ZMAX

(#,+

TO!("BUSCORE

MEMORYAND$-!

#LOCK

%NABLE

!0"

0RESCALER

TO#ORTEX3YSTEMTIMER

&#,+#ORTEX

FREERUNNINGCLOCK

-(ZMAX

0ERIPHERAL#LOCK

%NABLE

0#,+

TO!0"

PERIPHERALS

4)-

)F!0"PRESCALER X

ELSEX

TO4)-

4)-X#,+

0ERIPHERAL#LOCK

%NABLE

!0"

0RESCALER

-(ZMAX 0#,+

0ERIPHERAL#LOCK

PERIPHERALSTO!0"

%NABLE

4)-TIMERS

)F!0"PRESCALER X

ELSEX

!$#

0RESCALER

TO4)-4)-

4)-AND4)-

4)-X#,+

0ERIPHERAL#LOCK

%NABLE

TO!$#

!$##,+-(ZMAX

24##,+

,3)2#

K(Z

24#3%,;=

,3)

TOINDEPENDENTWATCHDOG)7$'

)7$'#,+

-#/

-AIN

CLOC KOUT PUT

0,,#,+

(3)

(3%

393#,+

-#/

1. To obtain an ADC conversion time of 1.2 µs, APB2 must be at 24 MHz.

,EGEND

(3%(IGHSPEEDEXTERNALCLOCKSIGNAL

(3) (IGHSPEEDINTERNALCLOCKSIGNAL

,3),OWSPEEDINTERNALCLOCKSIGNAL

,3%,OWSPEEDEXTERNALCLOCKSIGNAL

AI

DS5944 Rev 11

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34

Description STM32F100xC, STM32F100xD, STM32F100xE

2.2 Overview

2.2.1 Arm

®

Cortex

®

-M3 core with embedded Flash and SRAM

The Arm Cortex ® -M3 processor is the latest generation of Arm processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.

The Arm Cortex ® -M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an Arm core in the memory size usually associated with 8- and 16-bit devices.

The STM32F100 Value Line family having an embedded Arm core, is therefore compatible with all Arm tools and software.

2.2.3

Up to 512 Kbytes of embedded Flash memory is available for storing programs and data.

CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.

2.2.5

2.2.6

14/107

Up to 32 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states.

FSMC (flexible static memory controller)

The FSMC is embedded in the high-density value line family. It has four Chip Select outputs supporting the following modes: SRAM, PSRAM, and NOR.

Functionality overview:

• The three FSMC interrupt lines are ORed in order to be connected to the NVIC

• No read FIFO

• Code execution from external memory

• No boot capability

• The targeted frequency is HCLK/2, so external access is at 12 MHz when HCLK is at

24 MHz

LCD parallel interface

The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to

DS5944 Rev 11

STM32F100xC, STM32F100xD, STM32F100xE Description specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or highperformance solutions using external controllers with dedicated acceleration.

2.2.7 Nested vectored interrupt controller (NVIC)

The STM32F100 Value Line embeds a nested vectored interrupt controller able to handle up to 60 maskable interrupt channels (not including the 16 interrupt lines of Cortex

®

-M3) and 16 priority levels.

• Closely coupled NVIC gives low latency interrupt processing

• Interrupt entry vector table address passed directly to the core

• Closely coupled NVIC core interface

• Allows early processing of interrupts

• Processing of late arriving higher priority interrupts

• Support for tail-chaining

• Processor state automatically saved

• Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt latency.

2.2.9

The external interrupt/event controller consists of 18 edge detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 112 GPIOs can be connected to the 16 external interrupt lines.

Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-24 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example on failure of an indirectly used external crystal, resonator or oscillator).

Several prescalers allow the configuration of the AHB frequency, the high-speed APB

(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and the APB domains is 24 MHz.

At startup, boot pins are used to select one of three boot options:

• Boot from user Flash

• Boot from system memory

• Boot from embedded SRAM

DS5944 Rev 11

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34

Description STM32F100xC, STM32F100xD, STM32F100xE

The boot loader is located in System Memory. It is used to reprogram the Flash memory by using USART1. For further details please refer to AN2606.

2.2.11 Power supply schemes

• V

DD

= 2.0 to 3.6 V: External power supply for I/Os and the internal regulator.

Provided externally through V

DD

pins.

• V

SSA

, V

DDA

= 2.0 to 3.6 V: External analog power supplies for ADC, DAC, Reset blocks, RCs and PLL (minimum voltage to be applied to V

DDA is 2.4 V when the ADC or

DAC is used).

V

DDA

and V

SSA must be connected to V

DD and V

SS

, respectively.

• V

BAT

= 1.8 to 3.6 V: Power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when V

DD

is not present.

2.2.12 Power supply supervisor

The device has an integrated power on reset (POR)/power down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains in reset mode when V

DD external reset circuit.

is below a specified threshold, V

POR/PDR

, without the need for an

The device features an embedded programmable voltage detector (PVD) that monitors the

V

DD

/V

DDA

power supply and compares it to the V

PVD

threshold. An interrupt can be generated when V higher than the V

DD

PVD

/V

DDA

drops below the V

PVD

threshold and/or when V

DD

/V

DDA

threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

is

The regulator has three operation modes: main (MR), low power (LPR) and power down.

• MR is used in the nominal regulation mode (Run)

• LPR is used in the Stop mode

• Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost)

This regulator is always enabled after reset. It is disabled in Standby mode, providing high impedance output.

16/107

The STM32F100 Value Line supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:

• Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

• Stop mode

Stop mode achieves the lowest power consumption while retaining the content of

SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put

DS5944 Rev 11

STM32F100xC, STM32F100xD, STM32F100xE Description

Note: either in normal or in low power mode.

The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output or the RTC alarm.

• Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The

PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering

Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs.

The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode.

2.2.15 DMA

The flexible 12-channel general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The two DMA controllers support circular buffer management avoiding the generation of interrupts when the controller reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent.

The DMA can be used with the main peripherals: SPI, DAC, I 2 C, USART, all timers and

ADC.

2.2.16 RTC (real-time clock) and backup registers

The RTC and the backup registers are supplied through a switch that takes power either on

V

DD

supply when present or through the V

BAT

pin. The backup registers are ten 16-bit registers used to store 20 bytes of user application data when V

DD

power is not present.

The real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low power RC oscillator or the high-speed external clock divided by 128. The internal low power RC has a typical frequency of 40 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural crystal deviation. The RTC features a 32-bit programmable counter for long term measurement using the Compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz.

2.2.17 Timers and watchdogs

The STM32F100xx devices include an advanced-control timer, nine general-purpose timers, two basic timers and two watchdog timers.

Table 3 compares the features of the advanced-control, general-purpose and basic timers.

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34

Description STM32F100xC, STM32F100xD, STM32F100xE

Timer

TIM1

Counter resolution

16-bit

Table 3. Timer feature comparison

Counter type

Prescaler factor

DMA request generation

Capture/compare channels

Complementary outputs

Up, down, up/down

16 bits Yes 4 Yes

TIM2,

TIM3,

TIM4,

TIM5

16-bit

Up, down, up/down

Any integer between 1 and 65536

Yes 4 No

TIM12

TIM13,

TIM14

TIM15

TIM16,

TIM17

TIM6,

TIM7

16-bit

16-bit

16-bit

16-bit

16-bit

Up

Up

Up

Up

Up

Any integer between 1 and 65536

Any integer between 1 and 65536

Any integer between 1 and 65536

Any integer between 1 and 65536

Any integer between 1 and 65536

No

No

Yes

Yes

Yes

2

1

2

1

0

No

No

Yes

Yes

No

Advanced-control timer (TIM1)

The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable inserted dead times. It can also be seen as a complete general-purpose timer. The 4 independent channels can be used for:

• Input capture

• Output compare

• PWM generation (edge or center-aligned modes)

• One-pulse mode output

If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If configured as the 16-bit PWM generator, it has full modulation capability (0-100%).

The counter can be frozen in debug mode.

Many features are shared with those of the standard TIM timers which have the same architecture. The advanced control timer can therefore work together with the TIM timers via the Timer Link feature for synchronization or event chaining.

General-purpose timers (TIM2..5, TIM12..17)

There are ten synchronizable general-purpose timers embedded in the STM32F100xx

devices (see Table 3 for differences). Each general-purpose timer can be used to generate

PWM outputs, or as simple time base.

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DS5944 Rev 11

STM32F100xC, STM32F100xD, STM32F100xE Description

TIM2, TIM3, TIM4, TIM5

STM32F100xx devices feature four synchronizable 4-channel general-purpose timers.

These timers are based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler.

They feature 4 independent channels each for input capture/output compare, PWM or onepulse mode output. This gives up to 12 input captures/output compares/PWMs on the largest packages.

The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together or with the TIM1 advanced-control timer via the Timer Link feature for synchronization or event chaining.

TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation.

These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors.

Their counters can be frozen in debug mode.

TIM12, TIM13 and TIM14

These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.

TIM12 has two independent channels, whereas TIM13 and TIM14 feature one single channel for input capture/output compare, PWM or one-pulse mode output.

Their counters can be frozen in debug mode.

TIM15, TIM16 and TIM17

These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.

TIM15 has two independent channels, whereas TIM16 and TIM17 feature one single channel for input capture/output compare, PWM or one-pulse mode output.

The TIM15, TIM16 and TIM17 timers can work together, and TIM15 can also operate with

TIM1 via the Timer Link feature for synchronization or event chaining.

TIM15 can be synchronized with TIM16 and TIM17.

TIM15, TIM16, and TIM17 have a complementary output with dead-time generation and independent DMA request generation

Their counters can be frozen in debug mode.

Basic timers TIM6 and TIM7

These timers are mainly used for DAC trigger generation. They can also be used as a generic 16-bit time base.

Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode.

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34

Description STM32F100xC, STM32F100xD, STM32F100xE

Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

SysTick timer

This timer is dedicated for OS, but could also be used as a standard down counter. It features:

• A 24-bit down counter

• Autoreload capability

• Maskable system interrupt generation when the counter reaches 0.

• Programmable clock source

2.2.18 I

²

C bus

The I²C bus interface can operate in multimaster and slave modes. It can support standard and fast modes.

It supports dual slave addressing (7-bit only) and both 7/10-bit addressing in master mode.

A hardware CRC generation/verification is embedded.

The interface can be served by DMA and it supports SM Bus 2.0/PM Bus.

The STM32F100 Value Line embeds three universal synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3).

The available USART interfaces communicate at up to 3 Mbit/s. They provide hardware management of the CTS and RTS signals, they support IrDA SIR ENDEC, the multiprocessor communication mode, the single-wire half-duplex communication mode and have LIN Master/Slave capability.

The USART interfaces can be served by the DMA controller.

The STM32F100 Value Line embeds 2 universal asynchronous receiver transmitters

(UART4, and UART5).

The available UART interfaces support IrDA SIR ENDEC, the multiprocessor communication mode, the single-wire half-duplex communication mode and have LIN

Master/Slave capability.

The UART interfaces can be served by the DMA controller.

2.2.21 Serial peripheral interface (SPI)

Up to three SPIs are able to communicate up to 12 Mbit/s in slave and master modes in fullduplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits.

The SPIs can be served by the DMA controller.

20/107

DS5944 Rev 11

STM32F100xC, STM32F100xD, STM32F100xE Description

(high-definition electronics control (CEC)

The STM32F100xx value line embeds a HDMI-CEC controller that provides hardware support of consumer electronics control (CEC) (Appendix supplement 1 to the HDMI standard).

This protocol provides high-level control functions between all audiovisual products in an environment. It is specified to operate at low speeds with minimum processing and memory overhead.

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current capable.

The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers.

This feature allows the use of a maximum number of peripherals in a given application.

Indeed, alternate functions are available not only on the default pins but also on other specific pins onto which they are remappable. This has the advantage of making board design and port usage much more flexible.

For details refer to

Table 4: High-density STM32F100xx pin definitions

; it shows the list of remappable alternate functions and the pins onto which they can be remapped. See the

STM32F100xx reference manual for software considerations.

The 12-bit analog to digital converter has up to 16 external channels and performs conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs.

The ADC can be served by the DMA controller.

An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.

The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in noninverting configuration.

DS5944 Rev 11

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34

Description STM32F100xC, STM32F100xD, STM32F100xE

This dual digital Interface supports the following features:

• two DAC converters: one for each output channel

• up to 10-bit output

• left or right data alignment in 12-bit mode

• synchronized update capability

• noise-wave generation

• triangular-wave generation

• dual DAC channels’ independent or simultaneous conversions

• DMA capability for each channel

• external triggers for conversion

• input voltage reference V

REF+

Eight DAC trigger inputs are used in the STM32F100xx. The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels.

The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 2 V < V

DDA

< 3.6 V. The temperature sensor is internally connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value.

The Arm SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.

The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

22/107

DS5944 Rev 11

STM32F100xC, STM32F100xD, STM32F100xE

3 Pinouts and pin descriptions

Pinouts and pin descriptions

Figure 3. STM32F100 Value Line LQFP144 pinout

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DS5944 Rev 11

23/107

34

Pinouts and pin descriptions STM32F100xC, STM32F100xD, STM32F100xE

Figure 4. STM32F100 Value Line LQFP100 pinout

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24/107

DS5944 Rev 11

STM32F100xC, STM32F100xD, STM32F100xE Pinouts and pin descriptions

Figure 5. STM32F100 Value Line in LQFP64 pinout s d

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Pins

DL

Table 4. High-density STM32F100xx pin definitions

Alternate functions

(4)

Pin name

Main function

(3)

(after reset) Default Remap

4

5

6

1

2

3

7

8

9

10

11

12

13

8 3

9

-

-

-

-

1

2

3

4

5

6 1

-

-

-

-

-

7 2

4

-

-

-

-

PE2

PE3

PE4

PE5

PE6

V

BAT

PC13-TAMPER-

RTC

(5)

PC14-

OSC32_IN

(5)

PC15-

OSC32_OUT

(5)

PF0

PF1

PF2

PF3

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

S -

I/O -

I/O -

I/O -

I/O FT

I/O FT

I/O FT

I/O FT

PE2

PE3

PE4

PE5

PE6

V

BAT

PC13

(6)

PC14

(6)

PC15

(6)

PF0

PF1

PF2

PF3

TRACECK/ FSMC_A23

TRACED0/FSMC_A19

TRACED1/FSMC_A20

TRACED2/FSMC_A21

TRACED3/FSMC_A22

-

TAMPER-RTC

OSC32_IN

OSC32_OUT

FSMC_A0

FSMC_A1

FSMC_A2

FSMC_A3

-

-

-

-

-

-

-

-

-

-

-

-

-

DS5944 Rev 11

25/107

34

Pinouts and pin descriptions

Pins

STM32F100xC, STM32F100xD, STM32F100xE

Table 4. High-density STM32F100xx pin definitions (continued)

Alternate functions (4)

Pin name

Main function

(3)

(after reset) Default Remap

14 -

15 -

16 10 -

-

17 11 -

-

18

19

20

-

-

-

21

22

-

-

23 12 5

-

-

-

-

-

24 13 6

25 14 7

26 15 8

27 16 9

28 17 10

29 18 11

30 19 12

31 20 -

32 21 -

33 22 13

34 23 14

35 24 15

36 25 16

37 26 17

38 27 18

39 28 19

PF4

PF5

V

SS_5

V

DD_5

PF6

PF7

PF8

PF9

PF10

OSC_IN

OSC_OUT

NRST

PC0

PC1

PC2

PC3

V

SSA

V

REF-

V

REF+

V

DDA

PA0-WKUP

PA1

PA2

PA3

V

SS_4

V

DD_4

I/O FT

I/O FT

S -

S -

I/O -

I/O -

I/O -

I/O -

I/O -

I -

O -

I/O -

I/O -

I/O -

I/O -

I/O -

S -

S -

S -

S -

PF4

PF5

V

SS_5

V

DD_5

PF6

PF7

PF8

PF9

PF10

OSC_IN

OSC_OUT

NRST

PC0

PC1

PC2

PC3

V

SSA

V

REF-

V

REF+

V

DDA

I/O

I/O

I/O

I/O

S -

S -

-

-

-

-

PA0

PA1

PA2

PA3

V

SS_4

V

DD_4

FSMC_A4

FSMC_A5

-

-

-

-

-

-

-

-

-

-

ADC_IN10

ADC_IN11

ADC_IN12

ADC_IN13

-

-

-

-

WKUP/USART2_CTS

(8)

ADC_IN0

TIM2_CH1_ETR

TIM5_CH1

USART2_RTS

(8)

ADC_IN1/

TIM5_CH2/TIM2_CH2

(8)

USART2_TX

(8)

/TIM5_CH3

ADC_IN2/ TIM15_CH1

TIM2_CH3

(8)

USART2_RX

(8)

/TIM5_CH4

ADC_IN3/TIM2_CH4

(8)

/

TIM15_CH2

-

-

26/107

DS5944 Rev 11

-

-

-

-

-

-

-

-

PD0 (7)

PD1

(7)

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

STM32F100xC, STM32F100xD, STM32F100xE

Pins

Pinouts and pin descriptions

Table 4. High-density STM32F100xx pin definitions (continued)

Alternate functions (4)

Pin name

Main function

(3)

(after reset) Default Remap

40 29 20

41 30 21

42 31 22

43 32 23

44 33 24

45 34 25

46 35 26

47 36 27

48 37 28

49 -

50

51

52

53

54

-

-

-

-

-

-

-

-

-

-

55

56

57 -

-

-

58 38 -

59 39 -

60 40 -

-

-

-

61 -

62 -

63 41 -

64 42 -

65 43 -

PA7

PC4

PC5

PB0

PB1

PF15

PG0

PG1

PE7

PE8

PE9

PB2

PF11

PF12

V

SS_6

V

DD_6

PF13

PF14

V

SS_7

V

DD_7

PE10

PE11

PE12

PA4

PA5

PA6

I/O

I/O

I/O

-

-

-

PA4

PA5

PA6

I/O -

I/O -

I/O -

I/O -

PA7

PC4

PC5

PB0

I/O PB1

I/O FT PB2/BOOT1

I/O FT PF11

I/O FT

S

S -

-

I/O FT

I/O FT

PF12

V

SS_6

V

DD_6

PF13

PF14

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

PF15

PG0

PG1

PE7

PE8

PE9

S -

S -

I/O FT

I/O FT

I/O FT

V

SS_7

V

DD_7

PE10

PE11

PE12

SPI1_NSS

(8)

/

USART2_CK

(8)

DAC_OUT1/ADC_IN4

SPI1_SCK (8)

DAC_OUT2/ADC_IN5

SPI1_MISO

(8)

/

ADC_IN6 /

TIM3_CH1

(8)

SPI1_MOSI

(8)

/

ADC_IN7 /

TIM3_CH2

(8)

ADC_IN14 / TIM12_CH1

ADC_IN15 / TIM12_CH2

ADC_IN8/TIM3_CH3

ADC_IN9/TIM3_CH4

(8)

-

-

FSMC_A6

-

-

FSMC_A7

FSMC_A8

FSMC_A9

FSMC_A10

FSMC_A11

FSMC_D4

FSMC_D5

FSMC_D6

-

-

FSMC_D7

FSMC_D8

FSMC_D9

-

-

TIM1_BKIN /

TIM16_CH1

TIM1_CH1N/

TIM17_CH1

-

-

-

TIM1_ETR

TIM1_CH1N

TIM1_CH1

-

-

TIM1_CH2N

TIM1_CH2

TIM1_CH3N

-

-

TIM1_CH2N /

TIM13_CH1

TIM1_CH3N /

TIM14_CH1

-

-

-

-

-

-

-

DS5944 Rev 11

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34

Pinouts and pin descriptions

Pins

STM32F100xC, STM32F100xD, STM32F100xE

Table 4. High-density STM32F100xx pin definitions (continued)

Alternate functions (4)

Pin name

Main function

(3)

(after reset) Default Remap

66 44 -

67 45 -

68 46 -

69 47 29

70 48 30

71 49 31

72 50 32

73 51 33

74 52 34

75 53 35

76 54 36

77 55 -

78 56 -

79 57 -

80 58 -

81 59 -

82 60 -

83

84

-

-

85 61 -

-

-

86 62 -

87

88

-

-

-

89

90 -

-

-

-

PB13

PB14

PB15

PD8

PD9

PD10

PD11

PD12

PD13

V

SS_8

V

DD_8

PD14

PD15

PG2

PG3

PG4

PG5

PE13

PE14

PE15

PB10

PB11

V

SS_1

V

DD_1

PB12

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

S -

S -

I/O FT

PE13

PE14

PE15

PB10

PB11

V

SS_1

V

DD_1

PB12

PB13

PB14

PB15

PD8

PD9

PD10

PD11

PD12

PD13

V

SS_8

V

DD_8

PD14

PD15

PG2

PG3

PG4

PG5

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

S -

S -

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

FSMC_D10

FSMC_D11

FSMC_D12

I2C2_SCL/USART3_TX

(8)

I2C2_SDA/USART3_RX

(8)

-

-

SPI2_NSS/

I2C2_SMBA/

USART3_CK

(8)

/

TIM1_BKIN (8)

SPI2_SCK/

USART3_CTS

(8)

/

TIM1_CH1N

SPI2_MISO/TIM1_CH2N

USART3_RTS

(8)

/

SPI2_MOSI/

TIM1_CH3N

(8)

/

TIM15_CH1N

FSMC_D13

FSMC_D14

FSMC_D15

FSMC_A16

FSMC_A17

FSMC_A18

-

-

FSMC_D0

FSMC_D1

FSMC_A12

FSMC_A13

FSMC_A14

FSMC_A15

TIM1_CH3

TIM1_CH4

TIM1_BKIN

TIM2_CH3 /

HDMI_CEC

TIM2_CH4

-

-

TIM12_CH1

TIM12_CH2

TIM15_CH1

TIM15_CH2

USART3_TX

USART3_RX

USART3_CK

USART3_CTS

TIM4_CH1 /

USART3_RTS

TIM4_CH2

-

-

TIM4_CH3

TIM4_CH4

-

-

-

-

28/107

DS5944 Rev 11

PA9

PA10

PA11

PA12

PA13

PG6

PG7

PG8

V

SS_9

V

DD_9

PC6

PC7

PC8

PC9

PA8

V

SS_2

V

DD_2

PA14

PA15

PC10

PC11

PC12

PD0

PD1

PD2

PD3

PD4

PD5

STM32F100xC, STM32F100xD, STM32F100xE

Pins

Pinouts and pin descriptions

Table 4. High-density STM32F100xx pin definitions (continued)

Alternate functions (4)

Pin name

Main function

(3)

(after reset) Default Remap

91

92

93

94

-

-

-

-

95 -

96 63 37

97 64 38

98 65 39

99 66 40

-

-

-

-

100 67 41

101 68 42

102 69 43

103 70 44

104 71 45

105 72 46

106 73 -

107 74 47

108 75 48

109 76 49

110 77 50

111 78 51

112 79 52

113 80 53

114 81 -

115 82 -

116 83 54

117 84 -

118 85 -

119 86 -

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

S -

S -

I/O FT

I/O FT

I/O FT

I/O FT

PG6

PG7

PG8

V

SS_9

V

DD_9

PC6

-

-

-

-

I/O FT

I/O FT

I/O FT

PC7

PC8

PC9

PA8

PA9

PA10

I/O FT PA11

I/O FT PA12

I/O FT JTMS-SWDIO

Not connected

S

S -

V

SS_2

V

DD_2

I/O FT JTCK-SWCLK

-

-

-

TIM13_CH1

TIM14_CH1

USART1_CK/

TIM1_CH1

(8)

/MCO

USART1_TX (8)

/

TIM1_CH2

(8)

/ TIM15_BKIN

USART1_RX

(8)

/

TIM1_CH3

(8)

/ TIM17_BKIN

USART1_CTS / TIM1_CH4 (8)

USART1_RTS / TIM1_ETR

(8)

-

-

-

-

I/O FT JTDI SPI3_NSS

-

-

-

-

-

TIM3_CH1

TIM3_CH2

TIM3_CH3

TIM3_CH4

-

-

-

-

-

-

-

-

-

-

TIM2_CH1_ETR /

SPI1_NSS

PC10

PC11

PC12

PD0

PD1

PD2

PD3

PD4

PD5

UART4_TX

UART4_RX

UART5_TX

FSMC_D2

(9)

FSMC_D3

(9)

TIM3_ETR/UART5_RX

FSMC_CLK

FSMC_NOE

FSMC_NWE

USART3_TX

USART3_RX

USART3_CK

-

-

-

USART2_CTS

USART2_RTS

USART2_TX

DS5944 Rev 11

29/107

34

Pinouts and pin descriptions

Pins

STM32F100xC, STM32F100xD, STM32F100xE

Table 4. High-density STM32F100xx pin definitions (continued)

Alternate functions (4)

Pin name

Main function

(3)

(after reset) Default Remap

120 -

121 -

122 87 -

-

123 88 -

-

124 -

125 -

126 -

127 -

128 -

129 -

130 -

131 -

132 -

-

-

-

-

-

-

-

-

-

133 89 55

V

SS_10

V

DD_10

PD6

PD7

PG9

PG10

PG11

PG12

PG13

PG14

V

SS_11

V

DD_11

PG15

PB3/

134 90 56

135 91 57

PB4

PB5

136 92 58 PB6

137 93 59

138 94 60

PB7

BOOT0

139 95 61 PB8

140 96 62

141 97 -

142 98 -

PB9

PE0

PE1

143 99 63

144 100 64

V

SS_3

V

DD_3

1. I = input, O = output, S = supply.

2. FT = 5 V tolerant.

S -

S -

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

S -

S -

I/O FT

I/O FT

I/O FT

I/O -

I/O FT

I/O FT

I -

I/O FT

I/O FT

I/O FT

I/O FT

S -

S -

PG12

PG13

PG14

V

SS_11

V

DD_11

PG15

V

SS_10

V

DD_10

PD6

PD7

PG9

PG10

PG11

JTDO

NJTRST

PB5

PB6

PB7

BOOT0

PB8

PB9

PE0

PE1

V

SS_3

V

DD_3

-

FSMC_NWAIT

FSMC_NE1

FSMC_NE2

FSMC_NE3

-

FSMC_NE4

FSMC_A24

FSMC_A25

-

-

-

-

SPI3_SCK

SPI3_MISO

I2C1_SMBA/ SPI3_MOSI

TIM16_BKIN

I2C1_SCL

(8)

/ TIM4_CH1

(8)

/

TIM16_CH1N

I2C1_SDA

(8)

TIM4_CH2

/ FSMC_NADV /

(8)

/ TIM17_CH1N

-

TIM4_CH3

(8)

/TIM16_CH1 /

HDMI_CEC

TIM4_CH4

(8)

/ TIM17_CH1

TIM4_ETR / FSMC_NBL0

FSMC_NBL1

-

-

-

-

USART2_RX

USART2_CK

-

-

-

-

-

-

-

-

-

PB3/TRACESWO

TIM2_CH2 /

SPI1_SCK

TIM3_CH1

SPI1_MISO

TIM3_CH2 /

SPI1_MOSI

USART1_TX

USART1_RX

I2C1_SDA

-

-

-

-

-

I2C1_SCL

30/107

DS5944 Rev 11

Pins

PF3

PF4

PF5

PF6

PF7

PF8

PE2

PE3

PE4

PE5

PE6

PF0

PF1

PF2

PF9

PF10

PF11

PF12

PF13

PF14

PF15

STM32F100xC, STM32F100xD, STM32F100xE Pinouts and pin descriptions

3. Function availability depends on the chosen device.

4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).

5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).

6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the

Battery backup domain and BKP register description sections in the STM32F100xx reference manual, available from the

STMicroelectronics website: www.st.com

.

7. For the LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100 and LQFP144 packages, PD0 and PD1 are available by default, so there is no need for remapping. For more details, refer to Alternate function I/O and debug configuration section in the STM32F100xx reference manual.

8. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F100xx reference manual, available from the STMicroelectronics website: www.st.com

.

9. For devices delivered in LQFP64 packages, the FSMC function is not available.

Table 5. FSMC pin definition

FSMC

NOR/PSRAM/SRAM

A3

A4

A5

-

-

-

A23

A19

A20

A21

A22

A0

A1

A2

A6

A7

A8

A9

-

-

-

NOR/PSRAM Mux

-

-

-

-

-

-

A23

A19

A20

A21

A22

-

-

-

-

-

-

-

-

-

-

LQFP100

(1)

-

-

-

-

-

-

Yes

Yes

Yes

Yes

Yes

-

-

-

-

-

-

-

-

-

-

DS5944 Rev 11

31/107

34

Pins

PG4

PG5

PG6

PG7

PD0

PD1

PD12

PD13

PD14

PD15

PG2

PG3

PD3

PD4

PD5

PD6

PD7

PG9

PE12

PE13

PE14

PE15

PD8

PD9

PD10

PD11

PG0

PG1

PE7

PE8

PE9

PE10

PE11

Pinouts and pin descriptions STM32F100xC, STM32F100xD, STM32F100xE

Table 5. FSMC pin definition (continued)

FSMC

NOR/PSRAM/SRAM

A14

A15

-

-

D2

D3

A17

A18

D0

D1

A12

A13

CLK

NOE

NWE

NWAIT

NE1

NE2

D9

D10

D11

D12

D13

D14

D15

A16

A10

A11

D4

D5

D6

D7

D8

NOR/PSRAM Mux

-

-

-

-

DA2

DA3

A17

A18

DA0

DA1

-

-

CLK

NOE

NWE

NWAIT

NE1

NE2

DA9

DA10

DA11

DA12

DA13

DA14

DA15

A16

-

-

DA4

DA5

DA6

DA7

DA8

LQFP100

(1)

-

-

-

-

Yes

Yes

Yes

Yes

Yes

Yes

-

-

Yes

Yes

Yes

Yes

Yes

-

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

-

-

Yes

Yes

Yes

Yes

Yes

32/107

DS5944 Rev 11

STM32F100xC, STM32F100xD, STM32F100xE Pinouts and pin descriptions

Table 5. FSMC pin definition (continued)

FSMC

Pins

NOR/PSRAM/SRAM NOR/PSRAM Mux

PG10

PG11

PG12

PG13

PG14

PB7

PE0

PE1

NE3

-

NE4

A24

A25

NADV

NBL0

NBL1

1. Ports F and G are not available in devices delivered in 100-pin packages.

NE3

-

NE4

A24

A25

NADV

NBL0

NBL1

LQFP100

(1)

-

-

Yes

Yes

Yes

-

-

-

DS5944 Rev 11

33/107

34

Memory mapping STM32F100xC, STM32F100xD, STM32F100xE

34/107

The memory map is shown in

Figure 6 .

0xFFFF FFFF

7

0xE010 0000

0xE000 0000

Cortex-M3 internal peripherals

6

0xC000 0000

5

0xA000 0000

FSMC regs

4

0x8000 0000

3

0x7000 0000

0x6000 0000

FSMC external memory

2

0x4000 0000

Peripherals

1

0x2000 0000

0

0x0000 0000

SRAM

Reserved

Figure 6. Memory map

0x1FFF FFFF

0x1FFF F80F

0x1FFF F800

0x1FFF F000

0x0801 FFFF reserved

Option Bytes

System memory reserved

Flash memory

0x0800 0000

0x0000 0000

Aliased to Flash or system memory depending on

BOOT pins

0xFFFF FFFF

0x4002 3400

APB memory space reserved

CRC

0x4002 3000 reserved

0x4002 2400

0x4002 2000

Flash interface

0x4002 1400 reserved

0x4002 1000

RCC

0x4002 0400

DMA2

0x4002 0000

DMA1 reserved

0x4001 4C00

TIM17

0x4001 4800

TIM16

0x4001 4400

TIM15

0x4001 4000 reserved

0x4001 3C00

USART1

0x4001 3800 reserved

0x4001 3400

SPI1

0x4001 3000

TIM1

0x4001 2C00 reserved

0x4001 2800

ADC1

0x4001 2400

0x4001 2000

Port G

Port F

0x4001 1C00

0x4001 1800

Port E

0x4001 1400

Port D

0x4001 1000

Port C

0x4001 0C00

Port B

0x4001 0800

Port A

0x4001 0400

EXTI

0x4001 0000

AFIO

0x4000 7C00 reserved

0x4000 7800

CEC

DAC

0x4000 7400

PWR

0x4000 7000

BKP

0x4000 6C00

I2C2

0x4000 5C00 reserved

0x4000 5800

0x4000 5400

I2C1

0x4000 5000

0x4000 4C00

UART5

UART4

USART3

0x4000 4800

USART2

0x4000 4400

SPI3

0x4000 3C00

SPI2

0x4000 3800

0x4000 3400 reserved

0x4000 3000

IWDG

0x4000 2C00

WWDG

0x4000 2800

RTC

0x4000 2000

0x4000 1C00

TIM14

TIM13

TIM12

0x4000 1800

0x4000 1400

TIM7

TIM6

0x4000 1000

0x4000 0C00

TIM5

0x4000 0800

TIM4

0x4000 0400

TIM3

0x4000 0000

TIM2 ai18400

DS5944 Rev 11

STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics

5.1.1

Unless otherwise specified, all voltages are referenced to V

SS

.

Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T

A the selected temperature range).

= 25 °C and T

A

= T

A max (given by

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3 Σ ).

Unless otherwise specified, typical data are based on T

A

= 25 °C, V

DD

2 V ≤ V tested.

DD

= 3.3 V (for the

≤ 3.6 V voltage range). They are given only as design guidelines and are not

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2 Σ )

.

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

5.1.5

The loading conditions used for pin parameter measurement are shown in

Figure 7 .

Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 8

.

DS5944 Rev 11

35/107

106

Electrical characteristics

Figure 7. Pin loading conditions

STM32F100xC, STM32F100xD, STM32F100xE

Figure 8. Pin input voltage

S TM 3 2F10xxx pin

S TM 3 2F10xxx pin

C = 50 pF

VIN a i1412 3b a i14124 b

5.1.6 Power supply scheme

9

Figure 9. Power supply scheme

9%$7

3R ZHU VZL WFK

%DFNXSFLUFXLWU\

26&.57&

:DNHXSORJLF

%DFNXSUHJLVWHUV

*3 ,2V

287

,1

,2

/RJLF

îQ)

î—)

9''

9''

966

9''

Q)

—)

Q)

—)

95()

9''$

95()

95()

966$

5HJXODWRU

!$#$!#

$QDORJ

5&V3//

Caution: In

Figure 9 , the 4.7 µF capacitor must be connected to V

DD3

.

.HUQHOORJLF

&38

'LJLWDO

0HPRULHV

AIE

36/107

DS5944 Rev 11

STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics

Figure 10. Current consumption measurement scheme

IDD_VBAT

VBAT

IDD

VDD

VDDA a i14126

5.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in

Table 6: Voltage characteristics ,

Table 7: Current characteristics , and Table 8: Thermal characteristics

may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Symbol

Table 6. Voltage characteristics

Ratings Min Max Unit

V

DD

V

SS

External main supply voltage (including

V

DDA and V

DD

)

(1)

Input voltage on five volt tolerant pin

V

IN

(2)

Input voltage on any other pin

|V

| Δ V

DDx

| Variations between different V

DD power pins

SSX

− V

SS

|

Variations between all the different ground pins

V

ESD(HBM)

V

–0.3

SS

V

SS

-

-

− 0.3

− 0.3

4.0

V

DD

+ 4.0

4.0

50

50

Electrostatic discharge voltage (human body model)

see Section 5.3.12: Absolute maximum ratings (electrical sensitivity)

V mV

-

1. All main power (V

DD

, V

DDA

) and ground (V supply, in the permitted range.

SS

, V

SSA

) pins must always be connected to the external power

2. V

IN

maximum must always be respected. Refer to

Table 7: Current characteristics

for the maximum allowed injected current values.

DS5944 Rev 11

37/107

106

Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE

Symbol

Table 7. Current characteristics

Ratings Max.

Unit

I

I

VDD

VSS

Total current into V

DD

/V

DDA power lines (source)

(1)

Total current out of V

SS ground lines (sink)

(1)

Output current sunk by any I/O and control pin

150

150

I

IO

I

INJ(PIN)

(2)

Output current source by any I/Os and control pin

Injected current on five volt tolerant pins

(3)

Injected current on any other pin

(4)

Total injected current (sum of all I/O and control pins)

(5)

25

− 25

-5 / +0

± 5 mA

Σ I

INJ(PIN)

± 25

1. All main power (V , V

DDA

) and ground (V supply, in the permitted range.

SS

, V

SSA

) pins must always be connected to the external power

2. Negative injection disturbs the analog performance of the device. See Note: on page 85 .

3. Positive injection is not possible on these I/Os. A negative injection is induced by V values.

IN

<V

SS

. I

INJ(PIN)

must

never be exceeded. Refer to Table 6: Voltage characteristics

for the maximum allowed input voltage

4. A positive injection is induced by V

never be exceeded. Refer to

values.

>V

DD

while a negative injection is induced by V

Table 6: Voltage characteristics

IN

<V

SS

. I

for the maximum allowed input voltage

must

5. When several inputs are submitted to a current injection, the maximum Σ I positive and negative injected currents (instantaneous values).

INJ(PIN)

is the absolute sum of the

Symbol

T

STG

T

J

Table 8. Thermal characteristics

Ratings

Storage temperature range

Maximum junction temperature

Value

–65 to +150

150

Unit

°C

°C

5.3.1 General operating conditions

Symbol f

HCLK f

PCLK1 f

PCLK2

V

DD

V

DDA

(1)

V

BAT

Table 9. General operating conditions

Parameter Conditions

Internal AHB clock frequency

Internal APB1 clock frequency

Internal APB2 clock frequency

Standard operating voltage

Analog operating voltage

(ADC not used)

Analog operating voltage

(ADC used)

Backup operating voltage

-

-

-

-

Must be the same potential as V

DD

-

Min

0

2

0

0

2

2.4

1.8

Max

24

24

24

3.6

3.6

3.6

3.6

Unit

MHz

V

V

V

38/107

DS5944 Rev 11

STM32F100xC, STM32F100xD, STM32F100xE

Note:

Electrical characteristics

Symbol

Table 9. General operating conditions (continued)

Parameter Conditions Min Max Unit

P

T

T

D

A

J

Power dissipation at T

85 °C for suffix 6 or T

A

105 °C for suffix 7

(2)

Ambient temperature for 6 suffix version

Ambient temperature for 7 suffix version

A

=

=

Junction temperature range

LQFP144

LQFP100 -

666

434

LQFP64 444

Maximum power dissipation –40

Low power dissipation

(3)

85

–40 105

Maximum power dissipation –40

Low power dissipation

(3)

105

–40 125

6 suffix version –40 105

7 suffix version –40 125 mW

°C

°C

°C

1. When the ADC is used, refer to Table 51: ADC characteristics .

2. If T is lower, higher P

D

values are allowed as long as T

Thermal characteristics on page 101 ).

J

does not exceed T

J

max (see Section 6.4:

3. In low power dissipation state, T can be extended to this range as long as T

Section 6.4: Thermal characteristics on page 101

).

J

does not exceed T

J max (see

It is recommended to power V

DD

300 mV between V

DD

and V

DDA

and V

DDA

from the same source. A maximum difference of

can be tolerated during power-up and operation

Subject to general operating conditions for T

A

.

Symbol t

VDD

Table 10. Operating conditions at power-up / power-down

Parameter Min Max

V

DD

rise time rate

V

DD

fall time rate

0

20

∞

∞

Unit

µs/V

DS5944 Rev 11

39/107

106

Electrical characteristics

5.3.3

STM32F100xC, STM32F100xD, STM32F100xE

Embedded reset and power control block characteristics

The parameters given in

Table 11

are derived from tests performed under the ambient temperature and V

DD

supply voltage conditions summarized in

Table 9

.

.

Table 11. Embedded reset and power control block characteristics

Symbol Parameter Conditions Min Typ Max Unit

PLS[2:0]=000 (rising edge)

PLS[2:0]=000 (falling edge)

PLS[2:0]=001 (rising edge)

PLS[2:0]=001 (falling edge)

PLS[2:0]=010 (rising edge)

PLS[2:0]=010 (falling edge)

PLS[2:0]=011 (rising edge)

2.1

2.18

2.26

2 2.08

2.16

2.19

2.28

2.37

2.09

2.18

2.27

2.28

2.38

2.48

2.18

2.28

2.38

2.38

2.48

2.58

V

PVD

Programmable voltage detector level selection

PLS[2:0]=011 (falling edge)

PLS[2:0]=100 (rising edge)

PLS[2:0]=100 (falling edge)

PLS[2:0]=101 (rising edge)

PLS[2:0]=101 (falling edge)

2.28

2.38

2.48

2.47

2.58

2.69

2.37

2.48

2.59

2.57

2.68

2.79

2.47

2.58

2.69

PLS[2:0]=110 (rising edge)

PLS[2:0]=110 (falling edge)

PLS[2:0]=111 (rising edge)

2.66

2.56

2.76

2.78

2.68

2.88

2.9

2.8

3

PLS[2:0]=111 (falling edge) 2.66

2.78

2.9

V

PVDhyst

(2)

V

POR/PDR

PVD hysteresis

Power on/power down reset threshold

Falling edge

Rising edge

-

1.8

(1)

100

1.88

-

1.96

1.84

1.92

2.0

V

PDRhyst

(2) t

RSTTEMPO

(2)

PDR hysteresis

Reset temporization -

-

1.5

1. The product behavior is guaranteed by design down to the minimum V

POR/PDR

value.

2. Guaranteed by design, not tested in production.

40

2.5

-

4.5

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V mV

V

V mV ms

40/107

DS5944 Rev 11

STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics

5.3.5

The parameters given in

Table 12 are derived from tests performed under the ambient

temperature and V

DD

supply voltage conditions summarized in

Table 9

.

Symbol

Table 12. Embedded internal reference voltage

Parameter Conditions Min Typ Max

V

REFINT

Internal reference voltage

–40 °C < T

A

< +105 °C 1.16 1.20

1.26

–40 °C < T

A

< +85 °C 1.16 1.20

1.24

T

S_vrefint

(1)

ADC sampling time when reading the internal reference voltage

-

V

RERINT

(2)

Internal reference voltage spread over the temperature range

V

DD

= 3 V ±10 mV -

T

Coeff

(2)

Temperature coefficient -

1. Shortest sampling time can be determined in the application by multiple iterations.

2. Guaranteed by design, not tested in production.

5.1

-

-

17.1

10

100

(2)

Unit

V

V

µs mV ppm/°C

Supply current characteristics

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code.

The current consumption is measured as described in

Figure 10: Current consumption measurement scheme

.

All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to Dhrystone 2.1 code.

Maximum current consumption

The MCU is placed under the following conditions:

• All I/O pins are in input mode with a static value at V

DD

or V

SS

(no load)

• All peripherals are disabled except if it is explicitly mentioned

• Prefetch in on (reminder: this bit must be set before clock setting and bus prescaling)

• When the peripherals are enabled f

PCLK1

= f

HCLK

/2, f

PCLK2

= f

HCLK

The parameters given in

Table 13 are derived from tests performed under the ambient

temperature and V

DD

supply voltage conditions summarized in

Table 9

.

DS5944 Rev 11

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106

Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE

Table 13. Maximum current consumption in Run mode, code with data processing running from Flash

Max

(1)

Symbol Parameter Conditions f

HCLK

Unit

T

A

= 85 °C T

A

= 105 °C

24 MHz 19.7

20

External clock

(2)

, all peripherals enabled

16 MHz

8 MHz

14.6

8.2

14.7

8.6

I

DD

Supply current in

Run mode

External clock

(2)

, all peripherals disabled

HSI clock

(2)

, all peripherals enabled

HSI clock

(2)

, all peripherals disabled

24 MHz

16 MHz

8 MHz

24 MHz

16 MHz

8 MHz

24 MHz

16 MHz

8 MHz

13.1

10.1

9.4

6.7

5.4

11.3

8.7

5.6

19

13.2

10.1

9.6

7

5.6

11.6

8.9

6

19 mA

1. Based on characterization, not tested in production.

2. External clock or HSI frequency is 8 MHz and PLL is on when f

HCLK

> 8 MHz.

Table 14. Maximum current consumption in Run mode, code with data processing running from RAM

Max

(1)

Symbol Parameter Conditions f

HCLK

Unit

T

A

= 85 °C T

A

= 105 °C

I

DD

Supply current in Run mode

External clock

(2)

, all peripherals enabled

External clock

(2)

all peripherals disabled

HSI clock

(2)

, all peripherals enabled

HSI clock

(2)

, all peripherals disabled

24 MHz

16 MHz

8 MHz

24 MHz

16 MHz

8 MHz

24 MHz

16 MHz

8 MHz

24 MHz

16 MHz

8 MHz

18.5

13.1

7.3

10.9

7.3

4.8

17.2

11.7

8.9

8.1

5.6

4.3

19

13.5

7.6

11.5

7.7

5.2

17.2

11.8

9

8.3

5.8

4.5

mA

1. Based on characterization, tested in production at V

DD max, f

HCLK

max.

2. External clock or HSI frequency is 8 MHz and PLL is on when f

HCLK

> 8 MHz.

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DS5944 Rev 11

STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics

Table 15. STM32F100xxB maximum current consumption in Sleep mode, code running from Flash or RAM

Max

(1)

Symbol Parameter Conditions f

HCLK

Unit

T

A

= 85 °C T

A

= 105 °C

24 MHz 14.1

14.3

External clock

(2)

all peripherals enabled

16 MHz

8 MHz

9.7

5.9

10.3

6.2

I

DD

Supply current in Sleep mode

External clock

(2)

, all peripherals disabled

HSI clock

(2)

, all peripherals enabled

HSI clock

(2)

, all peripherals disabled

24 MHz

16 MHz

8 MHz

24 MHz

16 MHz

8 MHz

24 MHz

16 MHz

8 MHz

8.2

6.4

2.3

1.7

1.4

4.2

3.7

2.9

12.5

8.5

6.6

2.5

2

1.7

4.6

4.1

3.4

12.7

mA

1. Based on characterization, tested in production at V

DD max and f

HCLK

max with peripherals enabled.

2. External clock or HSI frequency is 8 MHz and PLL is on when f

HCLK

> 8 MHz.

DS5944 Rev 11

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Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE

Table 16. Typical and maximum current consumptions in Stop and Standby modes

Typ

(1)

Max

Symbol Parameter Conditions

V

DD

/V

BAT

= 2.0 V

V

DD

/ V

BAT

= 2.4 V

V

DD

/V

BAT

= 3.3 V

T

A

=

85 °C

T

A

=

105 °C

Unit

I

DD

Supply current in Stop mode

Regulator in Run mode,

Low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog)

Regulator in Low-Power mode,

Low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog)

Low-speed internal RC oscillator and independent watchdog ON

I

DD_VBAT

Supply current in Standby mode

Low-speed internal RC oscillator ON, independent watchdog OFF

Low-speed internal RC oscillator and independent watchdog OFF, low-speed oscillator and RTC OFF

Backup domain supply current

Low-speed oscillator and RTC

ON

1. Typical values are measured at T

A

= 25 °C.

-

-

-

-

-

1.0

-

-

-

-

-

1.2

31

24

3.2

3.1

2.2

1.4

320

305

-

-

3.9

2

670

650

-

-

5.7

2.3

µA

Typical current consumption

The MCU is placed under the following conditions:

• All I/O pins are in input mode with a static value at V

DD

or V

SS

(no load)

• All peripherals are disabled except if it is explicitly mentioned

• When the peripherals are enabled f

PCLK1 f

PCLK2

/4

= f

HCLK

/4, f

PCLK2

= f

HCLK

/2, f

ADCCLK

=

The parameters given in

Table 17 are derived from tests performed under the ambient

temperature and V

DD

supply voltage conditions summarized in

Table 9

.

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DS5944 Rev 11

STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics

Table 17. Typical current consumption in Run mode, code with data processing running from Flash

Typical values

(1)

Symbol Parameter Conditions f

HCLK All peripherals enabled

(2)

All peripherals disabled

Unit

I

DD

Supply current in

Run mode

Running on high-speed external clock with an

8 MHz crystal

(3)

Running on high-speed internal RC (HSI)

24 MHz

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

125 kHz

24 MHz

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

125 kHz

14.1

10

5.8

3.6

2.3

1.7

1.4

1.15

13.4

9.3

5.2

2.95

1.7

1.1

0.8

0.6

mA

1. Typical values are measures at T

A

= 25 °C, V

DD

= 3.3 V.

2. Add an additional power consumption of 0.8 mA for the ADC and of 0.5 mA for the DAC analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).

3. An 8 MHz crystal is used as the external clock source. The AHB prescaler is used to reduce the frequency when f

HCLK

< 8 MHz, the PLL is used when f

HCLK

> 8 MHz.

8.7

6.2

3.45

2.1

1.3

0.9

0.7

0.55

1.85

1.46

1.3

1.1

9.5

6.85

4.05

2.65

DS5944 Rev 11

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Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE

Table 18. Typical current consumption in Sleep mode, code running from Flash or

RAM

Typical values

(1)

Symbol Parameter Conditions f

HCLK All peripherals enabled

(2)

All peripherals disabled

Unit

I

DD

Supply current in

Sleep mode

Running on high-speed external clock with an

8 MHz crystal

(3)

Running on high-speed internal RC (HSI)

24 MHz

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

125 kHz

24 MHz

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

125 kHz

8

5.5

2.7

1.65

1.1

0.8

0.65

0.53

1.65

1.35

1.2

1.1

8.7

6.1

3.3

2.25

2.15

1.5

0.75

0.6

0.55

0.5

0.49

0.47

1.15

1.1

1.07

1.05

2.75

2.1

1.3

1.2

mA

1. Typical values are measures at T

A

= 25 °C, V

DD

= 3.3 V.

2. Add an additional power consumption of 0.8 mA for the ADC and of 0.5 mA for the DAC analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).

3. An 8 MHz crystal is used as the external clock source. The AHB prescaler is used to reduce the frequency when f

HCLK

> 8 MHz, the PLL is used when f

HCLK

> 8 MHz.

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DS5944 Rev 11

STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in

Table 19 . The MCU is placed

under the following conditions:

• all I/O pins are in input mode with a static value at V

DD

or V

SS

(no load)

• all peripherals are disabled unless otherwise mentioned

• the given value is calculated by measuring the current consumption

– with all peripherals clocked off

– with only one peripheral clocked on

• ambient operating temperature and V

DD

Table 6

.

supply voltage conditions summarized in

AHB (up to 24MHz)

Table 19. Peripheral current consumption

Peripheral Typical consumption at 25 °C

DMA1

DMA2

FSMC

CRC

BusMatrix

(1)

12.50

8.33

28.33

1.25

16.67

Unit

µA/MHz

DS5944 Rev 11

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106

Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE

Table 19. Peripheral current consumption (continued)

Peripheral Typical consumption at 25 °C

APB1 (up to 24 MHz)

UART5

I2C1

I2C2

CEC

DAC (2)

WWDG

PWR

BKP

IWDG

APB1-Bridge

TIM2

TIM3

TIM4

TIM5

TIM6

TIM7

TIM12

TIM13

TIM14

SPI2/I2S2

SPI3/I2S3

USART2

USART3

UART4

7.08

7.08

4.58

4.58

12.08

12.08

11.25

10.83

10.42

10.42

3.75

17.08

17.50

17.08

17.08

4.58

4.17

10.42

5.42

7.92

2.92

1.25

2.08

3.33

Unit

µA/MHz

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DS5944 Rev 11

STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics

Table 19. Peripheral current consumption (continued)

Peripheral Typical consumption at 25 °C Unit

APB2 (up to 24 MHz)

APB2-Bridge

GPIOA

GPIOB

GPIOC

GPIOD

GPIOE

GPIOF

GPIOG

SPI1

USART1

TIM1

TIM15

TIM16

TIM17

ADC1

(3)

4.17

6.67

6.25

6.67

6.67

6.67

5.42

6.67

4.17

12.08

22.08

14.17

10.00

10.00

15.83

µA/MHz

1. The BusMatrix is automatically active when at least one master is ON.(CPU, DMA1 or DMA2).

2. When DAC_OUT1 or DAC_OUT2 is enabled, there is an additional current consumption equal to 0,42 mA

3. Specific conditions for measuring ADC current consumption: f

HCLK f

ADCCLK

= f

APB2 part equal to 0.82 mA must be added.

= 24 MHz, f

APB1

= f

HCLK

, f

APB2

= f

HCLK

/2. When ADON bit in the ADC_CR2 register is set to 1, a current consumption of analog

,

High-speed external user clock generated from an external source

The characteristics given in

Table 20 result from tests performed using an high-speed

external clock source, and under the ambient temperature and supply voltage conditions summarized in

Table 9

.

DS5944 Rev 11

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106

Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE

Symbol

Table 20. High-speed external user clock characteristics

Parameter f

HSE_ext

V

HSEH

User external clock source frequency

(1)

OSC_IN input pin high level voltage (1)

V

HSEL

OSC_IN input pin low level voltage

(1) t w(HSE) t w(HSE) t r(HSE) t f(HSE)

C in(HSE)

DuCy

(HSE)

I

L

OSC_IN high or low time

OSC_IN rise or fall time

(1)

(1)

OSC_IN input capacitance

Duty cycle

(1)

(1)

OSC_IN Input leakage current

1. Guaranteed by design, not tested in production.

Conditions

-

-

-

V

SS

≤ V

IN

≤ V

DD

Min

1

0.7V

DD

V

SS

5

-

-

45

-

Typ

8

-

-

-

-

5

-

-

Max Unit

24

V

DD

0.3V

DD

-

20

-

55

±1

MHz

V ns pF

%

µA

Low-speed external user clock generated from an external source

The characteristics given in

Table 21 result from tests performed using an low-speed

external clock source, and under the ambient temperature and supply voltage conditions summarized in

Table 9

.

Symbol

Table 21. Low-speed external user clock characteristics

Parameter Conditions f

LSE_ext

V

LSEH

User external clock source frequency (1)

OSC32_IN input pin high level voltage (1)

V

LSEL

OSC32_IN input pin low level voltage

(1) t w(LSE) t w(LSE) t r(LSE) t f(LSE)

C in(LSE)

DuCy

(LSE)

I

L

OSC32_IN high or low time

OSC32_IN rise or fall time

(1)

(1)

OSC32_IN input capacitance

Duty cycle

(1)

(1)

-

OSC32_IN Input leakage current V

SS

≤ V

IN

≤ V

DD

1. Guaranteed by design, not tested in production.

Min

-

0.7V

DD

V

SS

450

-

-

30

-

Typ Max

32.768

1000

-

-

-

-

5

-

-

V

DD

0.3V

DD

-

50

-

70

±1

Unit kHz

V ns pF

%

µA

50/107

DS5944 Rev 11

STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics

Figure 11. High-speed external clock source AC timing diagram

9+6(+

9+6(/

W

U+6(

7

+6(

([WHUQDOFORFNVRXUFH

I

+6(BH[W

26&B,1

W

:+6(

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:+6(

W

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670)[[[

Figure 12. Low-speed external clock source AC timing diagram

DLE

VL

S EH

VL

S EL

90%

10% tr(L

S E)

TL

S E tf(L

S E) tW(L

S E) tW(L

S E) t

Extern a l clock s o u rce fL

S E_ext

O S C 3 2_IN

IL

S TM 3 2F10xxx a i14140c

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 24 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on

characterization results obtained with typical external components specified in Table 22

. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Symbol f

OSC_IN

R

F

Table 22. HSE 4-24 MHz oscillator characteristics (1)(2)

Parameter

Oscillator frequency

Feedback resistor

Conditions

-

-

Min Typ Max Unit

4

-

8

200

24

-

MHz k Ω

DS5944 Rev 11

51/107

106

Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE t

Symbol

C

C

L1

L2

(3) i

2 g m

Table 22. HSE 4-24 MHz oscillator characteristics (1)(2)

Parameter Conditions Min Typ Max Unit

Recommended load capacitance versus equivalent serial resistance of the crystal (R

S

)

(4)

R

S

= 30 Ω

HSE driving current

Oscillator transconductance

V

DD

V

IN load

= 3.3 V

= V

SS with 30 pF

Startup

-

-

25

30

-

1

-

pF mA mA/V

Startup time V

DD

is stabilized 2 ms

1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

2. Based on characterization, not tested in production.

3. It is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator. C

L1

and C

L2, are usually the same size. The crystal manufacturer typically specifies a load

L1

and C

L2

. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing

C

L1

and C

L2

.

4. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions.

5. t

SU(HSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer

Figure 13. Typical application with an 8 MHz crystal

Note:

52/107

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5)

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DLE

1. R

EXT

value depends on the crystal characteristics.

Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on

characterization results obtained with typical external components specified in Table 23

. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

For C

L1

and C

L2 it is recommended to use high-quality ceramic capacitors in the 5 pF to

15 pF range selected to match the requirements of the crystal or resonator. C

L1

and C

L2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which

DS5944 Rev 11

STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics is the series combination of C

L1

and C

L2

Load capacitance C

L

C stray

.

has the following formula: C

L

= C

L1

x C

L2

/ ( C

L1

+ C

L2

) + C stray

where

is the pin capacitance and board or trace PCB-related capacitance. Typically, it is between 2 pF and 7 pF.

For further details, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com

.

Caution: To avoid exceeding the maximum value of C

L1

and C to use a resonator with a load capacitance C

L capacitance of 12.5 pF.

Example: if you choose a resonator with a load capacitance of C then C

L1

= C

L2

= 8 pF.

≤

L2

(15 pF) it is strongly recommended

7 pF. Never use a resonator with a load

L

= 6 pF, and C stray

= 2 pF,

Symbol

Table 23. LSE oscillator characteristics (f

LSE

= 32.768 kHz) (1)

Parameter Conditions Min Typ Max Unit

R

F

Feedback resistor 5 M Ω

C

C

L1

L2

(2)

Recommended load capacitance versus equivalent serial resistance of the crystal (R

S

)

(3)

R

S

= 30 K Ω 15 pF

I

2

LSE driving current

V

DD

= 3.3 V

V

IN

= V

SS

-

1.4

µA g m

Oscillator transconductance 5 µA/V t

SU(LSE)

(4)

Startup time

V

DD

is stabilized

T

A

= 50 °C

T

A

= 25 °C

T

A

= 10 °C

T

A

= 0 °C

T

A

= -10 °C

T

A

= -20 °C

T

A

= -30 °C

T

A

= -40 °C -

-

-

-

-

-

-

1.5

2.5

4

6

10

17

32

60 -

-

-

-

-

-

-

s

1. Based on characterization, not tested in production.

2. Refer to the note and caution paragraphs above the table.

3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small R example MSIV-TIN32.768 kHz. Refer to crystal manufacturer for more details

S

value for

4. t

SU(LSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer

DS5944 Rev 11

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106

Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE

Figure 14. Typical application with a 32.768 kHz crystal

5.3.7

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DLE

Internal clock source characteristics

The parameters given in

Table 24 are derived from tests performed under the ambient

temperature and V

DD

supply voltage conditions summarized in

Table 9

.

High-speed internal (HSI) RC oscillator

Symbol

Table 24. HSI oscillator characteristics (1)

Parameter Conditions f

HSI

ACC

HSI t su(HSI)

(3)

I

DD(HSI)

(3)

Frequency -

Accuracy of HSI oscillator

HSI oscillator startup time

HSI oscillator power consumption

T

A

= –40 to 105 °C

(2)

T

A

= –10 to 85 °C

(2)

T

A

= 0 to 70 °C

(2)

T

A

= 25 °C

-

-

1. V

DD

= 3.3 V, T

A

= –40 to 105 °C °C unless otherwise specified.

2. Based on characterization, not tested in production.

3. Guaranteed by design. Not tested in production

Min Typ Max Unit

-

-2.4

-2.2

-1.9

-1

1

-

-

80

-

-

8

-

-

-

2.5

1.3

1.3

1

2

100

MHz

%

%

%

%

µs

µA

Low-speed internal (LSI) RC oscillator

Symbol

Table 25. LSI oscillator characteristics (1)

Parameter Min f

LSI t su(LSI)

(2)

I

DD(LSI)

(2)

Frequency

LSI oscillator startup time

LSI oscillator power consumption

1. V

DD

= 3 V, T

A

= –40 to 105 °C °C unless otherwise specified.

2. Guaranteed by design, not tested in production.

30

-

-

Typ

40

-

0.65

Max

60

85

1.2

Unit kHz

µs

µA

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DS5944 Rev 11

STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics

Wakeup time from low-power mode

The wakeup times given in

Table 26 are measured on a wakeup phase with an 8-MHz HSI

RC oscillator. The clock source used to wake up the device depends from the current operating mode:

• Stop or Standby mode: the clock source is the RC oscillator

• Sleep mode: the clock source is the clock that was set before entering Sleep mode.

All timings are derived from tests performed under the ambient temperature and V

DD voltage conditions summarized in

Table 9

.

supply

Symbol

Table 26. Low-power mode wakeup timings

Parameter Typ Unit t

WUSLEEP

(1)

Wakeup from Sleep mode 1.8

µs t

WUSTOP

(1)

Wakeup from Stop mode (regulator in run mode) 3.6

µs

Wakeup from Stop mode (regulator in low-power mode) 5.4

t

WUSTDBY

(1) Wakeup from Standby mode 50

1. The wakeup times are measured from the wakeup event to the point at which the user application code reads the first instruction.

µs

The parameters given in

Table 27 are derived from tests performed under the ambient

temperature and V

DD

supply voltage conditions summarized in

Table 9

.

Table 27. PLL characteristics

Value

Symbol Parameter Unit

Min

(1)

Typ Max

(1) f

PLL_IN f

PLL_OUT t

LOCK

Jitter

PLL input clock (2)

PLL input clock duty cycle

PLL multiplier output clock

PLL lock time

Cycle-to-cycle jitter

1

40

16

-

-

8.0

-

-

-

-

24

60

24

200

300

1. Based on device characterization, not tested in production.

2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by f

PLL_OUT

.

MHz

%

MHz

µs ps

Flash memory

The characteristics are given at T

A

= –40 to 105 °C unless otherwise specified.

DS5944 Rev 11

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106

Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE

Symbol

Table 28. Flash memory characteristics

Parameter Conditions t t

I prog

ERASE t

ME

DD

16-bit programming time

Page (2 KB) erase time

Mass erase time

Supply current

T

A

= –40 to +105 °C

T

A

= –40 to +105 °C

T

A

= –40 to +105 °C f

Read mode

HCLK

= 24 MHz, V

DD

= 3.3 V f

Write / Erase modes

HCLK

= 24 MHz, V

DD

= 3.3 V

Power-down mode / Halt,

V

DD

= 3.0 to 3.6 V

V prog

Programming voltage

1. Guaranteed by design, not tested in production.

-

Min

(1)

40

20

20

-

-

-

2

Typ Max

(1)

52.5

-

-

70

40

40

Unit

µs ms ms

-

-

-

20

5

50

3.6

mA mA

µA

V

Table 29. Flash memory endurance and data retention

Value

Symbol Parameter Conditions

Min (1) Typ Max

N t

END

RET

Endurance

Data retention

T

A

T

A

= –40 to +85 °C (6 suffix versions)

= –40 to +105 °C (7 suffix versions)

1 kcycle

(2)

at T

A

= 85 °C

1 kcycle (2) at T

A

= 105 °C

10 kcycles

(2)

at T

A

= 55 °C

1. Based on characterization not tested in production.

2. Cycling performed over the whole temperature range.

10

30

10

20

-

-

-

-

-

-

-

Unit kcycles

Years

Asynchronous waveforms and timings

Figure 15

through Figure 18 represent asynchronous waveforms and

Table 30 through

Table 33 provide the corresponding timings. The results shown in these tables are obtained

with the following FSMC configuration:

• AddressSetupTime = 0

• AddressHoldTime = 1

• DataSetupTime = 1

56/107

DS5944 Rev 11

STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics

Figure 15. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms

)60&B1(

W

Y12(B1(

W

Z12(

W

K1(B12(

)60&B12(

)60&B1:(

)60&B$>@

W

Y$B1(

W

Y%/B1(

$GGUHVV

W

K$B12(

W

K%/B12(

)60&B1%/>@

)60&B'>@

W

Y1$'9B1(

W

Z1$'9

)60&B1$'9

1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.

W

VX'DWDB12(

W

VX'DWDB1(

'DWD

W

K'DWDB1(

W

K'DWDB12(

069

DS5944 Rev 11

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106

Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE

Table 30. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings (1) (2)

Symbol Parameter Min Max Unit t w(NE) t v(NOE_NE) t w(NOE) t h(NE_NOE) t v(A_NE) t h(A_NOE) t v(BL_NE) t h(BL_NOE) t su(Data_NE) t su(Data_NOE) t h(Data_NOE) t h(Data_NE) t v(NADV_NE) t w(NADV)

FSMC_NE low time

FSMC_NEx low to FSMC_NOE low

5T

0.5

HCLK

2T

HCLK

2T

HCLK

0

– 1.5

5T

+ 25

+ 25

1.5

HCLK

+ 2 ns ns

FSMC_NOE low time 5T

HCLK

– 1.5

5T

HCLK

+ 1.5

ns

FSMC_NOE high to FSMC_NE high hold time –1.5

ns

FSMC_NEx low to FSMC_A valid

Address hold time after FSMC_NOE high

FSMC_NEx low to FSMC_BL valid

FSMC_BL hold time after FSMC_NOE high

Data to FSMC_NEx high setup time

Data to FSMC_NOEx high setup time

Data hold time after FSMC_NOE high

Data hold time after FSMC_NEx high

FSMC_NEx low to FSMC_NADV low

FSMC_NADV low time

1. C

L

= 15 pF.

2. Preliminary values.

0.1

0

0

-

-

-

0

0

5

T

HCLK

-

-

-

-

-

-

+ 1.5

ns ns ns ns ns ns ns ns ns ns

58/107

DS5944 Rev 11

STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics

Figure 16. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms t w(NE)

F S MC_NEx

F S MC_NOE t v(NWE_NE) t w(NWE) t h(NE_NWE)

F S MC_NWE

F S MC_A[25:0]

F S MC_NBL[ 3 :0] t v(A_NE) t v(BL_NE) t v(D a t a _NE) t h(A_NWE)

Addre ss t h(BL_NWE)

NBL t h(D a t a _NWE)

D a t a

F S MC_D[15:0] t v(NADV_NE) t w(NADV)

F S MC_NADV (1) a i14990

1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.

Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings (1)(2)

Symbol Parameter Min Max Unit t w(NE) t v(NWE_NE) t w(NWE) t h(NE_NWE) t v(A_NE) t h(A_NWE) t v(BL_NE) t h(BL_NWE) t v(Data_NE) t h(Data_NWE) t v(NADV_NE) t w(NADV)

FSMC_NE low time

FSMC_NEx low to FSMC_NWE low

3T

HCLK

– 1 3T

HCLK

+ 2 ns

T

HCLK

– 0.5

T

HCLK

+ 1.5

ns

FSMC_NWE low time

FSMC_NWE high to FSMC_NE high hold time T

FSMC_NEx low to FSMC_A valid

T

HCLK

– 0.5

T

HCLK

+ 1.5

ns

HCLK

7.5

ns ns

Address hold time after FSMC_NWE high

FSMC_NEx low to FSMC_BL valid

FSMC_BL hold time after FSMC_NWE high

FSMC_NEx low to Data valid

Data hold time after FSMC_NWE high

FSMC_NEx low to FSMC_NADV low

FSMC_NADV low time

1. C

L

= 15 pF.

2. Preliminary values.

T

T

T

HCLK

HCLK

HCLK

-

– 0.5

-

-

-

1.5

T

T

HCLK

5.5

HCLK

+ 7

-

-

ns ns ns ns ns ns

+ 1.5

ns

DS5944 Rev 11

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106

Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE

Figure 17. Asynchronous multiplexed PSRAM/NOR read waveforms

T

W.%

&3-#?.%

T

V./%?.%

T

H.%?./%

&3-#?./%

T

W./%

&3-#?.7%

T

V!?.%

T

H!?./%

&3-#?!;=

!DDRESS

T

V",?.%

T

H",?./%

&3-#?.",;= .",

T

H$ATA?.%

&3-#?

!$;=

T

V!?.%

!DDRESS

T

V.!$6?.%

T

W.!$6

T

H!$?.!$6

T

SU$ATA?.%

T

SU$ATA?./%

$ATA

T

H$ATA?./%

&3-#?.!$6

AIB

Table 32. Asynchronous multiplexed PSRAM/NOR read timings (1)(2)

Symbol Parameter Min Max Unit t w(NE) t v(NOE_NE) t w(NOE) t h(NE_NOE) t v(A_NE) t v(NADV_NE) t w(NADV)

FSMC_NE low time

FSMC_NEx low to FSMC_NOE low

FSMC_NOE low time 4T

HCLK

– 1 4T

HCLK

+ 2 ns

FSMC_NOE high to FSMC_NE high hold time –1 ns

FSMC_NEx low to FSMC_A valid

FSMC_NEx low to FSMC_NADV low

FSMC_NADV low time t h(AD_NADV)

FSMC_AD (address) valid hold time after

FSMC_NADV high t h(A_NOE) t h(BL_NOE) t v(BL_NE) t su(Data_NE) t su(Data_NOE) t h(Data_NE) t h(Data_NOE)

Address hold time after FSMC_NOE high

FSMC_BL hold time after FSMC_NOE high

FSMC_NEx low to FSMC_BL valid

Data to FSMC_NEx high setup time

Data to FSMC_NOE high setup time

Data hold time after FSMC_NEx high

Data hold time after FSMC_NOE high

1. C

L

= 15 pF.

2. Preliminary values.

7T

HCLK

– 2 7T

HCLK

+ 2 ns

3T

HCLK

– 0.5 3T

HCLK

+ 1.5 ns

3

T

T

T

0

2T

HCLK

+ 24

2T

HCLK

+ 25

0

0

-

5 ns

HCLK

–1.5

T

HCLK

+ 1.5

ns

HCLK

HCLK

0

0

-

-

-

-

-

-

-

ns ns ns

ns

ns

ns

ns

ns

ns

60/107

DS5944 Rev 11

STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics

Figure 18. Asynchronous multiplexed PSRAM/NOR write waveforms

WZ1(

)60&B1([

)60&B12(

WY1:(B1( WZ1:( W K1(B1:(

)60&B1:(

)60&B$>@

)60&B1%/>@

)60&B$'>@

WY$B1(

WY%/B1(

W Y$B1(

$GGUHVV

W Y1$'9B1(

WZ1$'9

WK$B1:(

$GGUHVV

WK%/B1:(

1%/

W Y'DWDB1$'9

'DWD

WK$'B1$'9

WK'DWDB1:(

)60&B1$'9

DL%

Table 33. Asynchronous multiplexed PSRAM/NOR write timings (1)(2)

Symbol Parameter t w(NE) t v(NWE_NE) t w(NWE) t h(NE_NWE) t v(A_NE) t v(NADV_NE) t w(NADV)

FSMC_NE low time

FSMC_NEx low to FSMC_NWE low

FSMC_NWE low time

FSMC_NWE high to FSMC_NE high hold time

FSMC_NEx low to FSMC_A valid

FSMC_NEx low to FSMC_NADV low

FSMC_NADV low time t h(AD_NADV)

FSMC_AD (address) valid hold time after

FSMC_NADV high t h(A_NWE) t v(BL_NE) t h(BL_NWE) t v(Data_NADV) t h(Data_NWE)

Address hold time after FSMC_NWE high

FSMC_NEx low to FSMC_BL valid

FSMC_BL hold time after FSMC_NWE high

FSMC_NADV high to Data valid

Data hold time after FSMC_NWE high

1. C

L

= 15 pF.

2. Preliminary values.

Min Unit

5T

HCLK

– 1 5T

HCLK

+ 2 ns

2T

HCLK

2T

HCLK

+ 1 ns

2T

HCLK

– 1 2T

HCLK

+ 2 ns

T

HCLK

– 1 ns

7 ns

3

T

HCLK

– 1

5

T

HCLK

+ 1 ns ns

T

HCLK

– 3

4T

HCLK

-

T

HCLK

– 1.5

-

T

HCLK

– 5

Max

ns

1.6

ns ns

ns

T

HCLK

+ 1.5

ns

ns

DS5944 Rev 11

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106

Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE

Synchronous waveforms and timings

Figure 19

through Figure 22

represent synchronous waveforms and Table 35

through

Table 37 provide the corresponding timings. The results shown in these tables are obtained

with the following FSMC configuration:

• BurstAccessMode = FSMC_BurstAccessMode_Enable;

• MemoryType = FSMC_MemoryType_CRAM;

• WriteBurst = FSMC_WriteBurst_Enable;

• CLKDivision = 1; (0 is not supported, see the STM32F10xxx reference manual)

• DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM

Figure 19. Synchronous multiplexed NOR/PSRAM read timings

TW#,+ TW#,+ "53452.

&3-#?#,+

$ATALATENCY

TD#,+,.%X, TD#,+,.%X(

&3-#?.%X

TD#,+,.!$6,

&3-#?.!$6

TD#,+,.!$6(

TD#,+,!6 TD#,+,!)6

&3-#?!;=

TD#,+(./%, TD#,+,./%(

&3-#?./%

TD#,+,!$6

&3-#?!$;=

TD#,+,!$)6

TSU!$6#,+(

!$;=

TSU.7!)46#,+(

&3-#?.7!)4

7!)4#&'B7!)40/,B

$

TH#,+(!$6

TSU!$6#,+(

$

TH#,+(.7!)46

TH#,+(!$6

$

TSU.7!)46#,+( TH#,+(.7!)46

&3-#?.7!)4

7!)4#&'B7!)40/,B

TSU.7!)46#,+( TH#,+(.7!)46

AII

62/107

DS5944 Rev 11

STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics

Table 34. Synchronous multiplexed NOR/PSRAM read timings (1)(2)

Symbol Parameter Min Max t w(CLK) t d(CLKL-NExL) t d(CLKL-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKL-AIV) t d(CLKH-NOEL) t d(CLKL-NOEH) t d(CLKL-ADV) t d(CLKL-ADIV)

FSMC_CLK period

FSMC_CLK low to FSMC_NEx low (x = 0...2)

FSMC_CLK low to FSMC_NEx high (x = 0...2)

FSMC_CLK low to FSMC_NADV low

FSMC_CLK low to FSMC_NADV high

FSMC_CLK low to FSMC_Ax valid (x = 16...25)

FSMC_CLK low to FSMC_Ax invalid (x = 16...25)

FSMC_CLK high to FSMC_NOE low

FSMC_CLK low to FSMC_NOE high

FSMC_CLK low to FSMC_AD[15:0] valid

FSMC_CLK low to FSMC_AD[15:0] invalid

27.7

2

5

2

0.5

0 t su(ADV-CLKH)

FSMC_A/D[15:0] valid data before FSMC_CLK high

6 t h(CLKH-ADV) t su(NWAITV-CLKH) t h(CLKH-NWAITV)

FSMC_A/D[15:0] valid data after FSMC_CLK high 0

FSMC_NWAIT valid before FSMC_CLK high

FSMC_NWAIT valid after FSMC_CLK high

1. C

L

= 15 pF.

2. Preliminary values.

8

2

-

-

-

-

-

1.5

4

0

1

12

-

-

-

-

-

-

-

-

-

ns

ns

ns

ns

Unit

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

DS5944 Rev 11

63/107

106

Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE

&3-#?#,+

Figure 20. Synchronous multiplexed PSRAM write timings

TW#,+ TW#,+ "53452.

$ATALATENCY

TD#,+,.%X, TD#,+,.%X(

&3-#?.%X

TD#,+,.!$6,

&3-#?.!$6

TD#,+,.!$6(

TD#,+,!6 TD#,+,!)6

&3-#?!;=

TD#,+,.7%, TD#,+,.7%(

&3-#?.7%

TD#,+,!$6

&3-#?!$;=

TD#,+,!$)6

TD#,+,$ATA

!$;=

TD#,+,$ATA

$ $

&3-#?.7!)4

7!)4#&'B7!)40/,B

TSU.7!)46#,+(

&3-#?.",

TH#,+(.7!)46

TD#,+,.",(

AIH

64/107

DS5944 Rev 11

STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics

Symbol

Table 35. Synchronous multiplexed PSRAM write timings (1)(2)

Parameter Min Max Unit t w(CLK) t d(CLKL-NExL) t d(CLKL-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKL-AIV) t d(CLKL-NWEL) t d(CLKL-NWEH) t d(CLKL-ADV) t d(CLKL-ADIV) t d(CLKL-Data) t su(NWAITV-CLKH) t h(CLKH-NWAITV) t d(CLKL-NBLH)

1. C

L

= 15 pF.

2. Preliminary values

FSMC_CLK period

FSMC_CLK low to FSMC_Nex low (x = 0...2)

FSMC_CLK low to FSMC_NEx high (x = 0...2)

FSMC_CLK low to FSMC_NADV low

FSMC_CLK low to FSMC_NADV high

FSMC_CLK low to FSMC_Ax valid (x = 16...25)

FSMC_CLK low to FSMC_Ax invalid (x = 16...25)

FSMC_CLK low to FSMC_NWE low

FSMC_CLK low to FSMC_NWE high

FSMC_CLK low to FSMC_AD[15:0] valid

FSMC_CLK low to FSMC_AD[15:0] invalid

FSMC_A/D[15:0] valid after FSMC_CLK low

FSMC_NWAIT valid before FSMC_CLK high

FSMC_NWAIT valid after FSMC_CLK high

FSMC_CLK low to FSMC_NBL high

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

2

4

0

1

12

-

-

-

6

-

-

-

-

-

-

7

2

1

27.7

-

2

-

5

-

2

-

1

-

3

-

DS5944 Rev 11

65/107

106

Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE

Figure 21. Synchronous non-multiplexed NOR/PSRAM read timings

&3-#?#,+

TW#,+ TW#,+

"53452.

TD#,+,.%X,

&3-#?.%X

$ATALATENCY

TD#,+,.%X(

TD#,+,.!$6,

&3-#?.!$6

TD#,+,.!$6(

TD#,+,!6 TD#,+,!)6

&3-#?!;=

TD#,+(./%, TD#,+,./%(

&3-#?./%

TSU$6#,+(

&3-#?$;=

TSU.7!)46#,+(

$

TH#,+($6

TSU$6#,+(

$

TH#,+(.7!)46

TH#,+($6

$

&3-#?.7!)4

7!)4#&'B7!)40/,B

TSU.7!)46#,+( T H#,+(.7!)46

&3-#?.7!)4

7!)4#&'B7!)40/,B

TSU.7!)46#,+( TH#,+(.7!)46

AIH

Table 36. Synchronous non-multiplexed NOR/PSRAM read timings

(1)(2)

Symbol Parameter Min Max

t w(CLK) t d(CLKL-NExL) t d(CLKL-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKL-AIV) t d(CLKH-NOEL) t d(CLKL-NOEH)

FSMC_CLK period

FSMC_CLK low to FSMC_NEx low (x = 0...2)

FSMC_CLK low to FSMC_NEx high (x = 0...2)

FSMC_CLK low to FSMC_NADV low

FSMC_CLK low to FSMC_NADV high

FSMC_CLK low to FSMC_Ax valid (x = 0...25)

FSMC_CLK low to FSMC_Ax invalid (x = 0...25)

FSMC_CLK high to FSMC_NOE low

FSMC_CLK low to FSMC_NOE high

27.7

2

5

4

1.5

t su(DV-CLKH)

FSMC_D[15:0] valid data before FSMC_CLK high

6.5

t h(CLKH-DV) t su(NWAITV-CLKH) t h(CLKH-NWAITV)

FSMC_D[15:0] valid data after FSMC_CLK high 7

FSMC_NWAIT valid before FSMC_SMCLK high 7

FSMC_NWAIT valid after FSMC_CLK high

1. C

L

= 15 pF.

2. Preliminary values.

2

-

-

-

-

1.5

4

0

1.5

-

-

-

-

-

-

-

-

ns

ns

ns

ns

Unit

ns

ns

ns

ns

ns

ns

ns

ns

ns

66/107

DS5944 Rev 11

STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics

Figure 22. Synchronous non-multiplexed PSRAM write timings

&3-#?#,+

TW#,+ TW#,+

"53452.

TD#,+,.%X,

&3-#?.%X

$ATALATENCY

TD#,+,.%X(

TD#,+,.!$6,

&3-#?.!$6

TD#,+,.!$6(

TD#,+,!6 TD#,+,!)6

&3-#?!;=

TD#,+,.7%, TD#,+,.7%(

&3-#?.7%

&3-#?$;=

TD#,+,$ATA

$

TD#,+,$ATA

$

&3-#?.7!)4

7!)4#&'B7!)40/,B

TSU.7!)46#,+( TD#,+,.",(

TH#,+(.7!)46

&3-#?.",

AII

Table 37. Synchronous non-multiplexed PSRAM write timings (1)(2)

Symbol Parameter Min Max Unit t w(CLK) t d(CLKL-NExL) t d(CLKL-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKL-AIV) t d(CLKL-NWEL) t d(CLKL-NWEH) t d(CLKL-Data) t su(NWAITV-CLKH) t h(CLKH-NWAITV) t d(CLKL-NBLH)

FSMC_CLK period

FSMC_CLK low to FSMC_NEx low (x = 0...2)

FSMC_CLK low to FSMC_NEx high (x = 0...2)

FSMC_CLK low to FSMC_NADV low

FSMC_CLK low to FSMC_NADV high

FSMC_CLK low to FSMC_Ax valid (x = 16...25)

FSMC_CLK low to FSMC_Ax invalid (x = 16...25)

FSMC_CLK low to FSMC_NWE low

FSMC_CLK low to FSMC_NWE high

FSMC_D[15:0] valid data after FSMC_CLK low

FSMC_NWAIT valid before FSMC_CLK high

FSMC_NWAIT valid after FSMC_CLK high

FSMC_CLK low to FSMC_NBL high

1. C

L

= 15 pF.

2. Preliminary values.

27.7

2

5

2

1

7

2

1

-

-

-

-

2

4

0

1

6

-

-

-

-

-

-

-

-

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

DS5944 Rev 11

67/107

106

Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE

68/107

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (Electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

• FTB : A Burst of Fast Transient voltage (positive and negative) is applied to V

DD

V

SS compliant with the IEC 61000-4-4 standard.

and

through a 100 pF capacitor, until a functional disturbance occurs. This test is

A device reset allows normal operations to be resumed.

The test results are given in

Table 38

. They are based on the EMS levels and classes defined in application note AN1709.

Symbol

V

FESD

V

EFTB

Table 38. EMS characteristics

Parameter Conditions

Voltage limits to be applied on any I/O pin to induce a functional disturbance f

V

DD

= 3.3 V, T

A

HCLK

= +25 °C,

= 24 MHz, LQFP144 package, conforms to

IEC 61000-4-2

Fast transient voltage burst limits to be applied through 100 pF on V

DD

and V to induce a functional disturbance

SS pins f

V

DD

= 3.3 V, T

A

HCLK

= +25 °C,

= 24 MHz, LQFP144 package, conforms to

IEC 61000-4-4

Level/Class

2B

4A

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and pre qualification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

• Corrupted program counter

• Unexpected reset

• Critical Data corruption (control registers...)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

DS5944 Rev 11

STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device is monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with

IEC 61967-2 standard which specifies the test board and the pin loading.

Table 39. EMI characteristics

Symbol Parameter

S

EMI

Conditions

Monitored frequency band

Peak level

V

DD

= 3.6 V, T

A

= 25°C,

LQFP144 package compliant with SAE

J1752/3

0.1 MHz to 30 MHz

30 MHz to 130 MHz

130 MHz to 1GHz

SAE EMI Level

Max vs. [f

HSE

/f

HCLK

]

8/24 MHz

16

25

25

4

Unit dBµV

-

5.3.12 Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard.

Symbol

Table 40. ESD absolute maximum ratings

Ratings Conditions Class

Maximum value

(1)

Unit

V

ESD(HBM)

V

ESD(CDM)

Electrostatic discharge voltage (human body model)

Electrostatic discharge voltage (charge device model)

T

A

= +25 °C conforming to JESD22-A114

T

A

= +25 °C conforming to JESD22-C101

1. Based on characterization results, not tested in production.

2

II

2000

500

V

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up performance:

• A supply overvoltage is applied to each power supply pin

• A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD78 IC latch-up standard.

Symbol

LU

Parameter

Table 41. Electrical sensitivities

Conditions

Static latch-up class T

A

= +105 °C conforming to JESD78

Class

II level A

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106

Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE

As a general rule, current injection to the I/O pins, due to external voltage below V

SS above V

DD

or

(for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.

Functional susceptibilty to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (>5

LSB TUE), out of spec current injection on adjacent pins or other functional failure (for example reset, oscillator frequency deviation).

The test results are given in

Table 42

Symbol

I

INJ

Table 42. I/O current injection susceptibility

Functional susceptibility

Description

Negative injection

Positive injection

Injected current on OSC_IN32,

OSC_OUT32, PA4, PA5, PC13

Injected current on all FT pins

Injected current on any other pin

-0

-5

-5

+0

+0

+5

Unit mA

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DS5944 Rev 11

STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Table 43

are derived from tests

performed under the conditions summarized in Table 9 . All I/Os are CMOS and TTL

compliant.

Symbol Parameter

Table 43. I/O static characteristics

Conditions Min Typ Max

V

IL

Standard I/O input low level voltage

I/O FT

(1)

input low level voltage

Standard I/O input high level voltage

-

–0.3

–0.3

0.41*(V

DD

–2 V) +1.3 V -

-

0.28*(V

DD

–2 V)+0.8 V

0.32*(V

DD

–2 V)+0.75 V

V

DD

+0.3

V

IH

I/O FT (1) input high level voltage

V

DD

> 2 V

V

DD

≤ 2 V

0.42*(V

DD

–2)+1 V -

5.5

5.2

V hys

Standard I/O Schmitt trigger voltage hysteresis

(2)

I/O FT Schmitt trigger voltage hysteresis

(2)

-

200

5% V

DD

(3)

-

-

-

-

I lkg

Input leakage current

(4)

V

SS

≤ V

IN

≤ V

DD

Standard I/Os

V

IN

= 5 V

I/O FT

-

-

-

± 1

3

R

PU

R

PD

Weak pull-up equivalent resistor

(5)

Weak pull-down equivalent resistor

(5)

V

IN

= V

SS

V

IN

= V

DD

30

30

40

40

50

50

C

IO

I/O pin capacitance 5 -

1. FT = 5V tolerant. To sustain a voltage higher than V

DD

+0.3 the internal pull-up/pull-down resistors must be disabled.

2. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by design, not tested in production.

3. With a minimum of 100 mV.

4. Leakage could be higher than max. if negative current is injected on adjacent pins.

5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

PMOS/NMOS contribution to the series resistance is minimum (~10% order)

.

Unit

V mV mV

µA k Ω k Ω pF

All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in

Figure 23

and

Figure 24 for standard I/Os, and

in

Figure 25 and Figure 26 for 5 V tolerant I/Os.

DS5944 Rev 11

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106

Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE

Figure 23. Standard I/O input characteristics - CMOS port

6)(6),6

6)(6$$

7

)(MIN

7

),MAX

#-/3STANDARDREQUIREMENT

6 )(6

$$

#-/3STANDARDREQUIREMENT

6),6$$

6

),

6 $$

)NPUTRANGE

NOTGUARANTEED

6$$6

AIB

Figure 24. Standard I/O input characteristics - TTL port

7

)(MIN

6)(6),6

7

),MAX

44,REQUIREMENTS 6)(6

6)(6$$

6),6$$

44,REQUIREMENTS 6),6

)NPUTRANGE

NOTGUARANTEED

6$$6

AI

72/107

DS5944 Rev 11

STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics

Figure 25. 5 V tolerant I/O input characteristics - CMOS port

6)(6),6

#-/3STANDARDREQUIREMENTS

6)(6

$$

6)(6$$

)NPUTRANGE

NOTGUARANTEED

#-/3STANDARDREQUIR

MENT6),6$$

6),6$$

6$$

6$$6

AIB

Figure 26. 5 V tolerant I/O input characteristics - TTL port

6)(6),6

7

)(MIN

7

),MAX

44,REQUIREMENT6)(6

6)(6$$

6),6$$

)NPUTRANGE

NOTGUARANTEED

44,REQUIREMENTS6),6

6$$6

AI

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or source up to +/- 20 mA (with a relaxed VOL/VOH) except PC13, PC14 and PC15 it can sink or source up to +/-3mA. When using the GPIOs PC13 to PC15 in output mode, the speed should not exceed 2 MHz with a maximum load of 30 pF.

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in

Section 5.2

:

• The sum of the currents sourced by all the I/Os on V

DD,

I consumption of the MCU sourced on V

DD,

VDD

(see

Table 7

). plus the maximum Run cannot exceed the absolute maximum rating

• The sum of the currents sunk by all the I/Os on V

SS

I consumption of the MCU sunk on V

SS

VSS

(see

Table 7

).

plus the maximum Run

cannot exceed the absolute maximum rating

DS5944 Rev 11

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106

Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE

Output voltage levels

Unless otherwise specified, the parameters given in Table 44

are derived from tests performed under the ambient temperature and V

DD in

Table 9

. All I/Os are CMOS and TTL compliant.

supply voltage conditions summarized

Symbol

Table 44. Output voltage characteristics

Parameter Conditions Min Max Unit

V

V

V

V

V

V

V

V

OL

(1)

OH

(3)

OL

(1)

OH

(3)

OL

(1)

OH

(3)

OL

(1)

OH

(3)

Output Low level voltage for an I/O pin when 8 pins are sunk at the same time

Output High level voltage for an I/O pin when 8 pins are sourced at the same time

Output low level voltage for an I/O pin when 8 pins are sunk at the same time

Output high level voltage for an I/O pin when 8 pins are sourced at the same time

Output low level voltage for an I/O pin when 8 pins are sunk at the same time

Output high level voltage for an I/O pin when 8 pins are sourced at the same time

Output low level voltage for an I/O pin when 8 pins are sunk at the same time

Output high level voltage for an I/O pin when 8 pins are sourced at the same time

CMOS port

(2)

,

I

IO

= +8 mA,

2.7 V < V

DD

< 3.6 V

TTL port

(2)

I

IO

= +8 mA

2.7 V < V

DD

< 3.6 V

I

IO

= +20 mA

(4)

2.7 V < V

DD

< 3.6 V

I

IO

= +6 mA

2 V < V

DD

(4)

< 2.7 V

V

V

V

DD

-

-

–0.4

2.4

DD

DD

-

-

–1.3

–0.4

0.4

-

-

0.4

-

1.3

-

0.4

1. The I

IO

current sunk by the device must always respect the absolute maximum rating specified in

Table 7

and the sum of I

IO

(I/O ports and control pins) must not exceed I

VSS

.

2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

3. The I

Table 7

current sourced by the device must always respect the absolute maximum rating specified in

and the sum of I

IO

(I/O ports and control pins) must not exceed I

VDD

.

4. Based on characterization data, not tested in production.

V

V

V

V

74/107

DS5944 Rev 11

STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in

Figure 27 and

Table 45 , respectively.

Unless otherwise specified, the parameters given in Table 45

are derived from tests performed under the ambient temperature and V

DD in

Table 9

.

supply voltage conditions summarized

Table 45. I/O AC characteristics (1)

MODEx

[1:0] bit value (1)

Symbol Parameter Conditions Max Unit

10

01

11

f max(IO)out t f(IO)out t r(IO)out f max(IO)out t f(IO)out t r(IO)out f max(IO)out t f(IO)out t r(IO)out t

EXTIpw

Maximum frequency

(2)

Output high to low level fall time

Output low to high level rise time

Maximum frequency

(2)

C

L

C

L

= 50 pF, V

= 50 pF, V

DD

= 2 V to 3.6 V

DD

= 2 V to 3.6 V

2

(3)

125

(3)

125

(3)

Output high to low level fall time

Output low to high level rise time

Maximum frequency

(2)

C

L

= 50 pF, V

DD

= 2 V to 3.6 V

Output high to low level fall time

Output low to high level rise time

25

(3)

25

(3)

C

L

= 50 pF, V

DD

= 2 V to 3.6 V 24

C

L

= 30 pF, V

DD

= 2.7 V to 3.6 V 5

(3)

C

L

= 50 pF, V

DD

= 2.7 V to 3.6 V 8

(3)

C

L

= 50 pF, V

DD

= 2 V to 2.7 V 12 (3)

C

L

V

= 30 pF, V

DD

= 2.7 V to 3.6

5

(3)

C

L

= 50 pF, V

DD

= 2.7 V to 3.6 V 8

(3)

C

L

= 50 pF, V

DD

= 2 V to 2.7 V 12

(3)

Pulse width of external signals detected by the

EXTI controller

C

L

= 50 pF, V

DD

= 2 V to 3.6 V

-

10

(3)

10 (3)

MHz ns

MHz ns

MHz ns ns

1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F100xx reference manual for a description of GPIO Port configuration register.

2. The maximum frequency is defined in

Figure 27

.

3. Guaranteed by design, not tested in production.

DS5944 Rev 11

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106

Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE

Figure 27. I/O AC characteristics definition

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The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, R

PU

(see

Table 43 ).

Unless otherwise specified, the parameters given in Table 46

are derived from tests performed under the ambient temperature and V

DD in

Table 9

.

supply voltage conditions summarized

Table 46. NRST pin characteristics

Symbol Parameter Conditions Min Typ Max Unit

V

IL(NRST)

(1)

V

IH(NRST)

(1)

NRST Input low level voltage

NRST Input high level voltage -

–0.5

2 -

0.8

V

DD

+0.5

V

V hys(NRST)

R

PU

V

F(NRST)

(1)

V

NF(NRST)

(1)

NRST Schmitt trigger voltage hysteresis

Weak pull-up equivalent resistor

(2)

NRST Input filtered pulse

NRST Input not filtered pulse

-

V

IN

= V

SS

-

-

-

30

-

300

200

40

-

-

-

50

100

mV k Ω ns ns

1. Guaranteed by design, not tested in production.

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution the series resistance must be minimum (~10% order)

.

to

76/107

DS5944 Rev 11

STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics

Figure 28. Recommended NRST pin protection

External reset circuit

(1)

NRST (2)

VDD

RPU

0.1 µF

Filter

Internal Reset

STM32F10xxx ai14132d

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the V

Table 46 . Otherwise the reset will not be taken into account by the device.

max level specified in

DS5944 Rev 11

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106

Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE

The parameters given in

Table 47 are guaranteed by design.

Refer to Section 5.3.13: I/O current injection characteristics for details on the input/output

alternate function characteristics (output compare, input capture, external clock, PWM output).

Symbol Parameter

Table 47. TIMx characteristics

Conditions

(1)

Min Max Unit t res(TIM) f

EXT

Res

TIM

Timer resolution time

Timer external clock frequency on CHx

Timer resolution

(2)

-

f

TIMxCLK

= 24 MHz 41.7

0 f

TIMxCLK

= 24 MHz

-

1

0

-

-

f

TIMxCLK

/2

12

16 t

TIMxCLK ns

MHz

MHz bit t

COUNTER

16-bit counter clock period when the internal clock is selected

f

TIMxCLK

-

= 24 MHz

1

-

65536

2730 t

TIMxCLK

µs t

MAX_COUNT

Maximum possible count

-

f

TIMxCLK

= 24 MHz

-

-

65536 × 65536 t

TIMxCLK

178 s

1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3, TIM4, TIM5, TIM15, TIM16 and TIM17 timers.

2. CHx is used as a general term to refer to CH1 to CH4 for TIM1, TIM2, TIM3, TIM4 and TIM5, to the CH1 to

CH2 for TIM15, and to CH1 for TIM16 and TIM17.

I

2

C interface characteristics

Unless otherwise specified, the parameters given in Table 48 are preliminary values derived

from tests performed under the ambient temperature, f

PCLK1 voltage conditions summarized in

Table 9

.

frequency and V

DD

supply

The STM32F100xx value line I 2 C interface meets the requirements of the standard I 2 C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and V

DD is disabled, but is still present.

The I 2 C characteristics are described in

Table 48

. Refer also to

Section 5.3.13: I/O current injection characteristics

for more details on the input/output alternate function characteristics

(SDA and SCL).

78/107

DS5944 Rev 11

STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics

Symbol

Table 48. I 2 C characteristics

Standard mode I

2

C

(1)

Parameter

Min Max

Fast mode I

2

C

(1) (2)

Min Max

Unit t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t r(SDA) t r(SCL) t f(SDA) t f(SCL) t h(STA)

SCL clock low time

SCL clock high time

SDA setup time

SDA data hold time

SDA and SCL rise time

SDA and SCL fall time

4.7

4.0

250

0

-

-

-

-

-

-

1000

300

1.3

0.6

100

0

-

-

-

-

-

900

(3)

300

300

µs ns t su(STA)

Start condition hold time

Repeated Start condition setup time

4.0

4.7

-

0.6

0.6 -

-

µs t su(STO)

Stop condition setup time t w(STO:STA)

Stop to Start condition time (bus free)

4.0

4.7

-

0.6

1.3

-

µs

µs

C b

Capacitive load for each bus line 400 400

1. Guaranteed by design, not tested in production.

2. f

PCLK1

must be at least 2 MHz to achieve standard mode I

2 achieve fast mode I fast mode clock.

2

C frequencies. It must be at least 4 MHz to

C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum I2C

3. The maximum Data hold time has only to be met if the interface does not stretch the low period of SCL signal.

pF

DS5944 Rev 11

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106

Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE

Figure 29. I 2 C bus AC waveforms and measurement circuit

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5V

5V

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1. Measurement points are done at CMOS levels: 0.3V

DD

and 0.7V

DD.

Table 49. SCL frequency (f

PCLK1

= 24 MHz, V

DD

= 3.3 V)

(1)(2)

I2C_CCR value f

SCL

(kHz)

(3)

R

P

= 4.7 k Ω

400

300

200

0x8011

0x8016

0x8021

100

50

0x0064

0x00C8

20 0x01F4

1. R

P

= External pull-up resistance, f

SCL

= I 2 C speed,

2. For speeds around 400 kHz, the tolerance on the achieved speed is of ± 2%. For other speed ranges, the tolerance on the achieved speed 1%. These variations depend on the accuracy of the external components used to design the application.

3. Guaranteed by design, not tested in production.

80/107

DS5944 Rev 11

STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics

SPI interface characteristics

Unless otherwise specified, the parameters given in Table 50 are preliminary values derived

from tests performed under the ambient temperature, f voltage conditions summarized in

Table 9

.

PCLKx frequency and V

DD

supply

Refer to Section 5.3.13: I/O current injection characteristics for more details on the

input/output alternate function characteristics (NSS, SCK, MOSI, MISO).

Symbol Parameter

Table 50. SPI characteristics

Conditions Min Max Unit

1/t f

SCK c(SCK)

SPI clock frequency

Master mode

Slave mode t r(SCK) t f(SCK) t su(NSS)

(1) t h(NSS)

(1) t t w(SCKH)

(1) w(SCKL)

(1) t t su(MI)

(1) su(SI)

(1) t h(MI)

(1) t h(SI)

(1) t a(SO)

(1)(2) t dis(SO)

(1)(3) t v(SO)

(1)

SPI clock rise and fall time

DuCy(SCK)

SPI slave input clock duty cycle

NSS setup time

NSS hold time

SCK high and low time

Data input setup time

Data input hold time

Slave mode

Slave mode

Slave mode

Master mode

Data output access time Slave mode, f

Data output disable time Slave mode

Data output valid time

Capacitive load: C = 30 pF

Slave mode

Master mode, f presc = 4

Master mode

Slave mode

PCLK

= 24 MHz,

PCLK

= 24 MHz

Slave mode (after enable edge) t v(MO)

(1)

Data output valid time

Master mode (after enable edge) t h(SO)

(1)

Slave mode (after enable edge)

Data output hold time t h(MO)

(1)

Master mode (after enable edge)

4t

2t

-

-

30

PCLK

PCLK

50

5

5

5

4

0

2

-

-

15

2

12

12

8

70

60

-

-

-

-

-

-

3t

PCLK

10

25

5

-

-

MHz ns

% ns

1. Preliminary values.

2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.

3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z

DS5944 Rev 11

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106

Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE

Figure 30. SPI timing diagram - slave mode and CPHA = 0

82/107

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Figure 31. SPI timing diagram - slave mode and CPHA = 1

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Y62

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1. Measurement points are done at CMOS levels: 0.3V

DD

and 0.7V

DD.

DLE

DS5944 Rev 11

STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics

Figure 32. SPI timing diagram - master mode

166LQSXW

+LJK

WF6&.

&3+$

&32/

&3+$

&32/

&3+$

&32/

&3+$

&32/

0,62

,13 87

WVX0,

WZ6&.+

WZ6&./

06%,1 %,7,1

WU6&.

WI6&.

/6%,1

WK0,

026,

287387

06%287

WY02

% , 7287

WK02

/6%287

1. Measurement points are done at CMOS levels: 0.3V

DD

and 0.7V

DD.

HDMI consumer electronics control (CEC)

Refer to Section 5.3.13: I/O current injection characteristics for more details on the

input/output alternate function characteristics.

DLF

Note:

Unless otherwise specified, the parameters given in Table 51 are preliminary values derived

from tests performed under the ambient temperature, f

PCLK2 voltage conditions summarized in

Table 9

.

frequency and V

DDA

supply

It is recommended to perform a calibration after each power-up.

DS5944 Rev 11

83/107

106

Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE

Symbol Parameter

Table 51. ADC characteristics

Conditions Min Typ Max f

V

I

V

V f f

DDA

REF+

VREF

ADC

S

(2)

TRIG

(2)

AIN

(3)

Power supply

Positive reference voltage

Current on the V

REF pin

input

ADC clock frequency

Sampling rate

External trigger frequency

Conversion voltage range f

ADC

-

-

-

-

-

= 12 MHz

-

-

2.4

2.4

-

0.6

0.05

-

-

0 (V

SSA tied to ground)

-

-

160

-

-

-

-

-

(1)

V

3.6

DDA

220

V

12

1

(1)

823

17

REF+

R

R

C

AIN

(2)

ADC

(2)

ADC

(2)

External input impedance

Sampling switch resistance

Internal sample and hold capacitor

See Equation 1 and

Table 52 for details

-

-

-

-

-

-

-

-

50

1

8 t t t t

CAL

(2) t t lat

(2) latr

(2)

S

(2)

STAB

(2)

CONV

(2)

Calibration time

Injection trigger conversion latency

Regular trigger conversion latency

Sampling time

Power-up time

Total conversion time

(including sampling time) f f

ADC

ADC f

ADC

= 12 MHz f

ADC

= 12 MHz

f

ADC

= 12 MHz

-

-

= 12 MHz

-

= 12 MHz

-

5.9

83

-

0.125

1.5

-

-

-

-

-

-

-

-

-

0.214

3

(4)

0.143

2

(4)

17.1

239.5

0

1.17

0

-

1

21

14 to 252 (t

S

for sampling +12.5 for successive approximation)

1. Preliminary values.

2. Guaranteed by design, not tested in production.

3. V

REF+

is internally connected to V

DDA

4. For external triggers, a delay of 1/f

PCLK2

must be added to the latency specified in

Table 51 .

Unit

V

V

µA

MHz

MHz kHz

1/f

ADC k k

V

Ω

Ω pF

µs

1/f

ADC

µs

1/f

ADC

µs

1/f

ADC

µs

1/f

ADC

µs

µs

1/f

ADC

Equation 1: R

AIN

R

AIN

< f

max formula:

T

----------------------------------------------------------------

ADC

× C

ADC

× ln ( 2 )

– R

ADC

The ab ove form u l a ( Equation 1 ) i s us ed to determine the m a xim u m extern a l imped a nce a llowed for a n error b elow 1/4 of L S B. Here N = 12 (from 12b it re s ol u tion).

84/107

DS5944 Rev 11

STM32F100xC, STM32F100xD, STM32F100xE

Note:

Electrical characteristics

1.5

7.5

13.5

28.5

41.5

55.5

71.5

239.5

T s

(cycles)

Table 52. R

AIN

max for f

ADC

= 12 MHz (1) t

S

(µs)

0.125

0.625

1.125

2.375

3.45

4.625

5.96

20

1. Guaranteed by design, not tested in production.

37.2

50

NA

NA

0.4

5.9

11.4

25.2

R

AIN

max (k Ω )

Symbol

Table 53. ADC accuracy - limited test conditions

(1)(2)

Parameter Test conditions

ET

EO

EG

ED

EL

Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error f

PCLK2 f

ADC

= 24 MHz,

= 12 MHz, R

AIN

< 10 k Ω ,

V

DDA

= 3 V to 3.6 V

V

REF+

= V

DDA

T

A

= 25 °C

Measurements made after

ADC calibration

1. ADC DC accuracy values are measured after internal calibration.

2. Preliminary values.

Typ

±1.5

±1

±0.5

±1.5

±1.5

Max

±2.5

±2

±1.5

±2

±2

Symbol Parameter

Table 54. ADC accuracy (1) (2) (3)

Test conditions Typ Max

ET

EO

EG

ED

EL

Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error f

PCLK2 f

ADC

= 12 MHz, R

V

DDA

= 24 MHz,

AIN

< 10 k Ω ,

= 2.4 V to 3.6 V

T

A =

Full operating range

Measurements made after

ADC calibration

±2

±1.5

±1.5

±1.5

±1.5

1. ADC DC accuracy values are measured after internal calibration.

2. Better performance could be achieved in restricted V

DD

, frequency, V

REF

and temperature ranges.

3. Preliminary values.

±5

±2.5

±3

±2.5

±4.5

Unit

LSB

Unit

LSB

ADC accuracy vs. negative injection current: Injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.

DS5944 Rev 11

85/107

106

Electrical characteristics

Note:

9$,1

5$,1

$,1[

&SDUDVLWLF

9''

97

9

STM32F100xC, STM32F100xD, STM32F100xE

Any positive injection current within the limits specified for I

INJ(PIN)

Section 5.3.13

does not affect the ADC accuracy.

and

Σ

I

INJ(PIN)

in

>/6%

,'($/

9

5()

Figure 33. ADC accuracy characteristics

9

''$

(

*

([DPSOHRIDQDFWX DOWUDQVIHUFXUYH

7KHLGHDOWUDQVIHUFX UYH

(QGSRLQWFRUUHODWLRQOLQH

(

2

(

7

(

/

/6%

,'($/

(

'

(

7

7RWDOXQDGMXVWHG(UURUPD[LPXPGHYLDWLRQ

EHWZHHQWKHDFWXDODQGWKHLGHDOWUDQVIHUFXUYHV

(

2

2IIVHW(UURUGHYLDWLRQEHWZHHQWKHILUVWDFWXDO

WUDQVLWLRQDQGWKHODVWDFWXDORQH

(

*

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WUDQVLWLRQDQGWKHODVWDFWXDORQH

(

'

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EHWZHHQDFWXDOVWHSVDQGWKHLGHDORQH

(

/

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EHWZHHQDQ\DFWXDOWUDQVLWLRQDQGWKHHQGSRLQW

FRUUHODWLRQOLQH

9

66$ 9

''$

DLH

Figure 34. Typical connection diagram using the ADC

,/“—$

670)[[[

6DPSOHDQGKROG$'&

FRQYHUWHU

5$'&

ELW

FRQYHUWHU

&$'&

DLG

1. Refer to Table 51 for the values of R

AIN

, R

ADC

and C

ADC

.

2. C parasitic

represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 this, f

ADC pF). A high C

should be reduced.

parasitic

value will downgrade conversion accuracy. To remedy

General PCB design guidelines

Power supply decoupling should be performed as shown in

Figure 35

or

Figure 36

, depending on whether V

REF+

is connected to V

DDA

or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip.

86/107

DS5944 Rev 11

STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics

Figure 35. Power supply and reference decoupling (V

REF+ not connected to V

DDA

)

S TM 3 2F10xxx

V REF+

1 µ F // 10 nF

1 µ F // 10 nF

V DDA

V

SS A/V REFa i14 38 0 b

1. V is available on 100-pin packages and on TFBGA64 packages. V packages only.

REF-

is available on 100-pin

Figure 36. Power supply and reference decoupling (V

REF+ connected to V

DDA

)

S TM 3 2F10xxx

V

REF+

/V

DDA

1 µ F // 10 nF

V

REF–

/V

SS A a i14 38 1 b

1. V

REF+

and V

REF-

inputs are available only on 100-pin packages.

DS5944 Rev 11

87/107

106

Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE

Symbol

V

DDA

V

REF+

V

SSA

R

LOAD

(1)

R

O

(1)

C

LOAD

(1)

DAC_OUT min

(1)

Lower DAC_OUT voltage with buffer

ON

0.2 -

I

DDVREF+

I

DDA

DNL

(1)

INL

(1)

Parameter

Analog supply voltage

Reference supply voltage

Ground

Resistive load with buffer ON

Impedance output with buffer OFF

Capacitive load

Table 55. DAC characteristics

DAC_OUT max

(1)

DAC_OUT min

(1)

DAC_OUT max

(1)

Higher DAC_OUT voltage with buffer

ON

Lower DAC_OUT voltage with buffer

OFF

Higher DAC_OUT voltage with buffer

OFF

DAC DC current consumption in quiescent mode (Standby mode)

DAC DC current consumption in quiescent mode

(2)

Differential non linearity Difference between two consecutive code-1LSB)

Integral non linearity (difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code

1023)

Min Typ Max

(1)

2.4

2.4

0

5

-

-

-

-

-

-

-

-

-

-

-

0.5

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Unit Comments

3.6

3.6

0

15

50

V

0.2

±2

±1

±4

-

-

DDA

–

V

V

V k k

V

V

Ω

Ω pF

-

V

REF+

must always be below

V

DDA

-

-

When the buffer is OFF, the

Minimum resistive load between DAC_OUT and V

SS

to have a 1% accuracy is 1.5 M Ω

Maximum capacitive load at

DAC_OUT pin (when the buffer is ON).

It gives the maximum output excursion of the DAC.

It corresponds to 12-bit input code (0x0E0) to (0xF1C) at

V

REF+

= 3.6 V and (0x155) and

(0xEAB) at V

REF+

= 2.4 V

mV

V

REF+

– 1LSB

V

220

380

480

±0.5

It gives the maximum output excursion of the DAC.

µA

µA

µA

With no load, worst code

(0xF1C) at V

REF+

= 3.6 V in terms of DC consumption on the inputs

With no load, middle code

(0x800) on the inputs

With no load, worst code

(0xF1C) at V

REF+

= 3.6 V in terms of DC consumption on the inputs

LSB

Given for the DAC in 10-bit configuration

LSB

LSB

LSB

Given for the DAC in 12-bit configuration

Given for the DAC in 10-bit configuration

Given for the DAC in 12-bit configuration

88/107

DS5944 Rev 11

STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics

Symbol

Table 55. DAC characteristics (continued)

Parameter Min Typ Max (1) Unit Comments

Offset

(1)

Offset error

(difference between measured value at Code (0x800) and the ideal value =

V

REF+

/2)

-

-

-

-

-

±10

±3

±12 mV

LSB

LSB

Given for the DAC in 12-bit configuration

Given for the DAC in 10-bit at

V

REF+

= 3.6 V

Given for the DAC in 12-bit at

V

REF+

= 3.6 V

Given for the DAC in 12-bit configuration t

Gain error (1)

Gain error t

SETTLING

(1)

Update rate

(1)

Settling time (full scale: for a 10-bit input code transition between the lowest and the highest input codes when DAC_OUT reaches final value

±1LSB

Max frequency for a correct

DAC_OUT change when small variation in the input code (from code i to i+1LSB)

WAKEUP

(1)

PSRR+

(1)

Wakeup time from off state (Setting the ENx bit in the DAC Control register)

Power supply rejection ratio (to V

DDA

(static DC measurement

)

-

-

-

-

-

3

6.5

-

±0.5

4

1

10

–67 –40

%

µs

MS/s C

µs dB

C

C

LOAD

LOAD

≤

LOAD

≤

≤

50 pF, R

LOAD

LOAD

≥ 5 k Ω input code between lowest and highest possible ones.

LOAD

, C

LOAD

LOAD

≥ 5 k Ω

≥ 5 k Ω

= 50 pF

1. Preliminary values.

2. Quiescent mode refer to the state of the DAC keeping steady value on the output, so no dynamic consumption is involved.

Figure 37. 12-bit buffered /non-buffered DAC

%XIIHUHGQRQEXIIHUHG'$&

%XIIHU

5 /2$'

ELW

GLJLWDOWR

DQDORJ

FRQYHUWHU

'$&[B287

& /2$'

DLG

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register.

DS5944 Rev 11

89/107

106

Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE

5.3.20 Temperature sensor characteristics

Symbol

Table 56. TS characteristics

Parameter Min

T

L

(1)

Avg_Slope

(1)

V

25

(1) t

START

(2)

T

S_temp

(3)(2)

V

SENSE

linearity with temperature

Average slope

Voltage at 25°C

Startup time

ADC sampling time when reading the temperature

1. Guaranteed by characterization, not tested in production.

2. Guaranteed by design, not tested in production.

3. Shortest sampling time can be determined in the application by multiple iterations.

-

-

4.0

1.32

4

Typ

± 1

4.3

1.41

-

-

Max

± 2

4.6

1.50

10

17.1

Unit

°C mV/°C

V

µs

µs

90/107

DS5944 Rev 11

STM32F100xC, STM32F100xD, STM32F100xE Package information

6.1

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com

.

ECOPACK ® is an ST trademark.

LQFP144 package information

6($7,1*

3/$1(

&

Figure 38. LQFP - 144-pin, 20 x 20 mm low-profile quad flat package outline

F

FFF &

'

'

'

PP

*$8*(3/$1(

/

/ .

3,1

,'(17,),&$7,21

1. Drawing is not to scale.

DS5944 Rev 11

H

$B0(B9

91/107

106

Package information STM32F100xC, STM32F100xD, STM32F100xE

Symbol

Table 57. LQFP - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data millimeters inches

(1)

Min Typ Max Min Typ Max e

L

L1

D3

E

E1

E3 k ccc

D

D1 b c

A

A1

A2

-

0.050

1.350

0.170

0.090

21.800

19.800

-

21.800

19.800

-

-

0.450

-

0°

-

-

-

1.400

0.220

-

22.000

20.000

17.500

22.000

20.000

17.500

0.500

0.600

1.000

3.5°

-

1.600

0.150

1.450

0.270

0.200

22.200

20.200

-

22.200

20.200

-

-

0.750

-

7°

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

-

0.8583

0.7795

-

-

0.0177

-

0°

-

-

0.0020

0.0531

0.0067

0.0035

0.8583

0.7795

0.6890

0.8661

0.7874

0.6890

0.0197

0.0236

0.0394

3.5°

-

-

-

0.0551

0.0087

-

0.8661

0.7874

-

0.8740

0.7953

-

-

0.0295

-

7°

0.0031

0.0630

0.0059

0.0571

0.0106

0.0079

0.8740

0.7953

92/107

DS5944 Rev 11

STM32F100xC, STM32F100xD, STM32F100xE Package information

Figure 39. LQFP - 144-pin, 20 x 20 mm low-profile quad flat package recommended footprint

1. Dimensions are expressed in millimeters.

DLH

DS5944 Rev 11

93/107

106

Package information STM32F100xC, STM32F100xD, STM32F100xE

Device marking for LQFP144

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which also depend on supply chain operations, are not indicated below.

Figure 40.LQFP144 marking example (package top view)

2SWLRQDOJDWHPDUN

3URGXFWLGHQWLILFDWLRQ

5HYLVLRQFRGH

$

)

=&7%

'DWHFRGH

< ::

3LQLGHQWLILHU

06Y9

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.

94/107

DS5944 Rev 11

STM32F100xC, STM32F100xD, STM32F100xE

6.2 LQFP100 package information

Package information

Figure 41. LQFP – 14 x 14 mm 100 pin low-profile quad flat package outline

3%!4).'0,!.%

#

C

MM

'!5'%0,!.%

CCC #

$

$

$

,

, +

0).

)$%.4)&)#!4)/.

E

,?-%?6

1. Drawing is not to scale.

Symbol

Table 58. LQPF - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data millimeters inches

(1)

Min Typ Max Min Typ Max b c

D

D1

A

A1

A2

D3

E

E1

-

0.050

1.350

0.170

0.090

15.800

13.800

-

15.800

13.800

-

-

1.400

0.220

-

16.000

14.000

12.000

16.000

14.000

1.600

0.150

1.450

0.270

0.200

16.200

14.200

-

16.200

14.200

-

0.0020

0.0531

0.0067

0.0035

0.6220

0.5433

-

0.6220

0.5433

-

-

0.0551

0.0087

-

0.6299

0.5512

0.4724

0.6299

0.5512

0.0630

0.0059

0.0571

0.0106

0.0079

0.6378

0.5591

-

0.6378

0.5591

DS5944 Rev 11

95/107

106

Package information STM32F100xC, STM32F100xD, STM32F100xE

Symbol

Table 58. LQPF - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data (continued) millimeters inches (1)

Min Typ Max Min Typ Max

E3 e

L

-

-

0.450

12.000

0.500

0.600

-

-

0.750

-

-

0.0177

0.4724

0.0197

0.0236

L1 k

-

0.0°

1.000

3.5°

-

7.0°

-

0.0° ccc 0.080

-

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.0394

3.5°

-

-

-

0.0295

-

7.0°

0.0031

Figure 42. LQFP - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint

96/107

1. Dimensions are expressed in millimeters.

DS5944 Rev 11

AIC

STM32F100xC, STM32F100xD, STM32F100xE Package information

Device marking for LQFP100

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which also depend on supply chain operations, are not indicated below.

Figure 43.LQFP100 marking example (package top view)

3URGXFWLGHQWLILFDWLRQ

^dDϯϮ&ϭϬϬ sdϲ y z tt

2SWLRQDOJDWH

PDUN

5HYLVLRQFRGH

'DWHFRGH

3LQLGHQWLILHU

06Y9

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.

DS5944 Rev 11

97/107

106

Package information

6.3 LQFP64 package information

STM32F100xC, STM32F100xD, STM32F100xE

Figure 44.LQFP - 64 pin, 10 x 10 mm low-profile quad flat package outline

6($7,1*3/$1(

&

PP

*$8*(3/$1(

FFF &

.

'

'

' /

/

E

98/107

3,1

,'(17,),&$7,21

H

:B0(B9

1.

Dr a wing i s not in s c a le.

Symbol

Table 59. LQFP - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data millimeters inches

(1)

Min Typ Max Min Typ Max c

D

D1

D3

A

A1

A2 b

E

E1

E3

-

-

-

-

0.050

1.350

0.170

0.090

-

-

-

-

-

1.400

0.220

-

12.000

10.000

7.500

12.000

10.000

7.500

1.600

0.150

1.450

0.270

0.200

-

-

-

-

-

-

-

0.0020

0.0531

0.0067

0.0035

-

-

-

-

-

-

-

-

0.0551

0.0087

-

0.4724

0.3937

0.2953

0.4724

0.3937

0.2953

0.0630

0.0059

0.0571

0.0106

0.0079

-

-

-

-

-

-

DS5944 Rev 11

STM32F100xC, STM32F100xD, STM32F100xE Package information

Symbol

Table 59. LQFP - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data (continued) millimeters inches (1)

Min Typ Max Min Typ Max e

K

L

L1 ccc

-

0°

0.450

-

-

0.500

3.5°

0.600

1.000

-

-

7°

0.750

-

0.080

0°

0.0177

-

-

-

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.0197

3.5°

0.0236

0.0394

-

-

7°

0.0295

-

0.0031

Figure 45.LQFP - 64-pin, 10 x 10 mm low-profile quad flat recommended footprint

1. Dimensions are in millimeters.

AIC

DS5944 Rev 11

99/107

106

Package information STM32F100xC, STM32F100xD, STM32F100xE

Device marking for LQFP64

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which also depend on supply chain operations, are not indicated below.

Figure 46.LQFP64 marking example (package top view)

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1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.

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DS5944 Rev 11

STM32F100xC, STM32F100xD, STM32F100xE Package information

The maximum chip junction temperature (T

J max) must never exceed the values given in

Table 9: General operating conditions on page 38 .

The maximum chip-junction temperature, T

J using the following equation:

max, in degrees Celsius, may be calculated

T

J

max = T

A

max + (P

D

max x Θ

JA

)

Where:

• T

A

max is the maximum ambient temperature in ° C,

• Θ

JA

is the package junction-to-ambient thermal resistance, in ° C/W,

• P

D

max is the sum of P

INT

max and P

I/O max (P

D

max = P

INT

max + P

I/O max),

• P

INT

max is the product of I

DD and internal power.

V

DD

, expressed in Watts. This is the maximum chip

P

I/O

max represents the maximum power dissipation on output pins where:

P

I/O

max = Σ (V

OL

× I

OL

) + Σ ((V

DD

– V

OH

) × I

OH

), taking into account the actual V

OL application.

/ I

OL

and V

OH

/ I

OH of the I/Os at low and high level in the

Symbol

Θ

JA

Table 60. Package thermal characteristics

Parameter Value

Thermal resistance junction-ambient

LQFP 144 - 20 × 20 mm / 0.5 mm pitch

Thermal resistance junction-ambient

LQFP 100 - 14 × 14 mm / 0.5 mm pitch

Thermal resistance junction-ambient

LQFP 64 - 10 × 10 mm / 0.5 mm pitch

35

40

49

Unit

°C/W

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural

Convection (Still Air). Available from www.jedec.org.

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106

Package information

6.4.2

STM32F100xC, STM32F100xD, STM32F100xE

Selecting the product temperature range

When ordering the microcontroller, the temperature range is specified in the ordering

information scheme shown in Table 61: Ordering information

.

Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature.

As applications do not commonly use the STM32F100xx at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application.

The following examples show how to calculate the temperature range needed for a given application.

Example: high-performance application

Assuming the following application conditions:

Maximum ambient temperature T

Amax

I

DDmax

= 50 mA, V

DD

= 82 °C (measured according to JESD51-2),

= 3.5 V, maximum 20 I/Os used at the same time in output at low level with I

OL

= 8 mA, V

OL

= 0.4 V and maximum 8 I/Os used at the same time in output mode at low level with I

OL

= 20 mA, V

OL

= 1.3 V

P

INTmax =

50 mA × 3.5 V= 175 mW

P

IOmax = 20

× 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW

This gives: P

INTmax

= 175 mW and P

IOmax

= 272 mW

P

Dmax =

175

+

272 = 447 mW

Thus: P

Dmax

= 447 mW

Using the values obtained in Table 60

T

Jmax

is calculated as follows:

– For LQFP64, 49 °C/W

T

Jmax

= 82 °C + (49 °C/W × 447 mW) = 82 °C + 20.1 °C = 102.1 °C

This is within the range of the suffix 6 version parts (–40 < T

J

< 105 °C).

In this case, parts must be ordered at least with the temperature range suffix 6 (see

Table 61: Ordering information ).

Example 2: High-temperature application

Using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature T

J specified range.

remains within the

Assuming the following application conditions:

Maximum ambient temperature T

Amax

I

DDmax

= 20 mA, V

DD

= 115 °C (measured according to JESD51-2),

= 3.5 V, maximum 20 I/Os used at the same time in output at low level with I

OL

= 8 mA, V

OL

= 0.4 V

P

INTmax =

20 mA × 3.5 V= 70 mW

P

IOmax = 20

× 8 mA × 0.4 V = 64 mW

This gives: P

INTmax

= 70 mW and P

IOmax

= 64 mW:

P

Dmax =

70

+

64 = 134 mW

Thus: P

Dmax

= 134 mW

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DS5944 Rev 11

STM32F100xC, STM32F100xD, STM32F100xE Package information

Using the values obtained in Table 60

T

Jmax

is calculated as follows:

– For LQFP100, 40 °C/W

T

Jmax

= 115 °C + (40 °C/W × 134 mW) = 115 °C + 5.4 °C = 120.4 °C

This is within the range of the suffix 7 version parts (–40 < T

J

< 125 °C).

In this case, parts must be ordered at least with the temperature range suffix 7 (see

Table 61: Ordering information ).

Figure 47. LQFP100 P

D

max vs. T

A

700

600

500

400

3 00

200

100

0

65 75 8 5 95 105 115 125 1 3 5

T

A

(°C)

Su ffix 6

Su ffix 7

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Ordering information STM32F100xC, STM32F100xD, STM32F100xE

Table 61. Ordering information

Example: STM32 F 100 V C T 6 B xxx

Device family

STM32 = Arm-based 32-bit microcontroller

Product type

F = General-purpose

Device subfamily

100 = value line

Pin count

R = 64 pins

V = 100 pins

Z = 144 pins

Flash memory size

C = 256 Kbytes of Flash memory

D = 384 Kbytes of Flash memory

E = 512 Kbytes of Flash memory

Package

T = LQFP

Temperature range

6 = Industrial temperature range, –40 to 85 °C

7 = Industrial temperature range, –40 to 105 °C

Internal code

B

Options xxx = programmed parts

TR = tape and real

For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office.

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DS5944 Rev 11

STM32F100xC, STM32F100xD, STM32F100xE Revision history

Date

09-Oct-2008

31-Mar-2009

01-Sep-2010

18-Oct-2010

11-Apr-2011

Revision

Table 62. Document revision history

Changes

1

2

3

4

5

Initial release.

I/O information clarified on page 1.

Table 5: High-density STM32F100xx pin definitions modified.

Figure 5: Memory map on page 26 modified.

Note modified in Table 13: Maximum current consumption in Run mode, code with data processing running from Flash and Table 15:

Maximum current consumption in Sleep mode, code running from

Flash or RAM.

Table 20: High-speed external user clock characteristics and Table

21: Low-speed user external clock characteristics modified. ACCHSI max values modified in Table 24: HSI oscillator characteristics.

Note modified in Table 13: Maximum current consumption in Run mode, code with data processing running from Flash and Table 15:

Maximum current consumption in Sleep mode, code running from

Flash or RAM.

Figure 10, Figure 11 and Figure 12 show typical curves (titles changed).

Small text changes.

Major revision of whole document.

Added LQFP144 package and additional peripherals (SPI3, UART4,

UART, TIM5, 12, 14, 13, FSMC).

Updated Power consumption data in

Table 13

to

Table 16

Updated

Section 5.3.11: EMC characteristics on page 68

Added Section 2.2.6: LCD parallel interface on page 13

In Table 4 on page 24 moved TIM15_BKIN and TIM17_BKIN from remap to default column. Updated description of PA3, PA5 and PF6 to PF10.

Updated footnotes below

Table 6: Voltage characteristics on page 37

and Table 7: Current characteristics on page 38

Added VBAT values in

Table 16: Typical and maximum current consumptions in Stop and Standby modes on page 44

Updated tw min in

Table 20: High-speed external user clock characteristics on page 50

Updated startup time in Table 23: LSE oscillator characteristics (f

LSE

= 32.768 kHz) on page 53

Added HSI clock accuracy values in Table 24: HSI oscillator characteristics on page 54

Updated FSMC Synchronous waveforms and timings on page 62

Updated

Table 43: I/O static characteristics on page 71

Added

Section 5.3.13: I/O current injection characteristics on page 70

Corrected TTL and CMOS designations in

Table 44: Output voltage characteristics on page 74

DS5944 Rev 11

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Revision history STM32F100xC, STM32F100xD, STM32F100xE

Date

08-Jun-2012

17-Sep-2012

10-Mar-2015

23-Sep-2015

29-Mar-2016

15-Oct-2018

Table 62. Document revision history (continued)

Revision Changes

6

7

8

9

10

11

Updated

Table 7: Current characteristics on page 38

Corrected “CLKL-NOEL” in

Section 5.3.10: FSMC characteristics on page 56

Updated

Table 48: I

2

C characteristics on page 79

Corrected note “non-robust “ in

Section 5.3.18: 12-bit ADC characteristics on page 83

Updated Figure 1: STM32F100xx value line block diagram on page 11

Updated

Section 5.3.14: I/O port characteristics on page 71

Updated Section 2.2.22: GPIOs (general-purpose inputs/outputs) on page 20

Updated Table 4: High-density STM32F100xx pin definitions on page 24

Updated

Section 5.3.1: General operating conditions on page 38

Updated PD0 and PD1 in Table 4: High-density STM32F100xx pin definitions on page 24

Updated P

D

conditions

max specifications in

Table 9: General operating

Added footnote to IDDA parameter description in Table 55: DAC characteristics

Updated

Table 57: LQFP - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data

,

Table 58: LQPF - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data

,

Table 59: LQFP - 64pin, 10 x 10 mm low-profile quad flat package mechanical data

Updated Figure 38: LQFP - 144-pin, 20 x 20 mm low-profile quad flat package outline on page 91 ,

Figure 39: LQFP - 144-pin, 20 x 20 mm low-profile quad flat package recommended footprint on page 93 ,

Figure 41: LQFP – 14 x 14 mm 100 pin low-profile quad flat package outline on page 95 ,

Figure 42: LQFP - 100-pin, 14 x 14 mm lowprofile quad flat recommended footprint on page 96 ,

Figure 44:

LQFP - 64 pin, 10 x 10 mm low-profile quad flat package outline on page 98 ,

Figure 45: LQFP - 64-pin, 10 x 10 mm low-profile quad flat recommended footprint on page 99

Added Figure 40: LQFP144 marking example (package top view) on page 94 ,

Figure 43: LQFP100 marking example (package top view) on page 97

,

Figure 46: LQFP64 marking example (package top view) on page 100

Updated

Table 19: Peripheral current consumption

Updated

Section 6: Package information

Updated

Table 14: Maximum current consumption in Run mode, code with data processing running from RAM

Updated:

–

Section 1: Introduction

–

Section 2.2.23: GPIOs (general-purpose inputs/outputs)

–

Section 6: Package information

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