This datasheet provides the ordering information and mechanical device characteristics of the STM32F101xF and STM32F101xG XL-density access line microcontrollers. For more details on the whole STMicroelectronics STM32F101xx family, please refer to

Section 2.2:

Full compatibility throughout the family .

The XL-density STM32F101xx datasheet should be read in conjunction with the

STM32F10xxx reference manual.

For information on programming, erasing and protection of the internal Flash memory please refer to the STM32F10xxx Flash programming manual.

The reference and Flash programming manuals are both available from the

STMicroelectronics website www.st.com

For information on the Cortex ® -M3 core please refer to the Cortex ® -M3 Technical Reference

Manual, available from the www.arm.com website.

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Description

2 Description

STM32F101xF, STM32F101xG

The STM32F101xF and STM32F101xG access line family incorporates the highperformance ARM ® Cortex ® -M3 32-bit RISC core operating at a 36 MHz frequency, highspeed embedded memories (Flash memory up to 1 Mbyte and SRAM of 80 Kbytes), and an extensive range of enhanced I/Os and peripherals connected to two APB buses. All devices offer one 12-bit ADC, ten general-purpose 16-bit timers, as well as standard and advanced communication interfaces: up to two I 2 Cs, three SPIs and five USARTs.

The STM32F101xx XL-density access line family operates in the –40 to +85 °C temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving mode allows the design of low-power applications.

These features make the STM32F101xx XL-density access line microcontroller family suitable for a wide range of applications such as medical and handheld equipment, PC peripherals and gaming, GPS platforms, industrial applications, PLC, printers, scanners alarm systems , power meters, and video intercom.

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DocID16553 Rev 5

STM32F101xF, STM32F101xG Description

The STM32F101xx XL-density access line family offers devices in 3 different package types: from 64 pins to 144 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family.

Figure 1 shows the general block diagram of the device family.

Table 2. STM32F101xF and STM32F101xG features and peripheral counts

Peripherals STM32F101Rx STM32F101Vx STM32F101Zx

Flash memory

SRAM in Kbytes

FSMC

Timers

General-purpose

Basic

Communication interfaces

SPI

USART

GPIOs

12-bit ADC

Number of channels

12-bit DAC

Number of channels

CPU frequency

Operating voltage

Operating temperatures

768 KB

1 MB 768 KB

Yes

1 MB

768 KB

Yes

1 MB

YES

112

36 MHz

2.0 to 3.6 V

Ambient temperature: –40 to +85 °C (see

Table 10

)

Junction temperature: –40 to +105 °C (see Table 10

)

LQFP64 LQFP100

(1)

LQFP144 Package

1. For the LQFP100 package, only FSMC Bank1 and Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16- or 8-bit NAND

Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available in this package.

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Description STM32F101xF, STM32F101xG

Figure 1. STM32F101xF and STM32F101xG access line block diagram

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1. T

= –40 °C to +85 °C (junction temperature up to 105 °C).

2. AF = alternate function on I/O port pin.

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DocID16553 Rev 5

STM32F101xF, STM32F101xG Description

Figure 2. Clock tree

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1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is

36 MHz.

2. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz or 28 MHz.

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Description STM32F101xF, STM32F101xG

The STM32F101xx is a complete family whose members are fully pin-to-pin, software and feature compatible.In the reference manual, the STM32F101x4 and STM32F101x6 are identified as low-density devices, the STM32F101x8 and STM32F101xB are referred to as medium-density devices, the STM32F101xC, STM32F101xD and STM32F101xE are referred to as high-density devices, and the STM32F101xF and STM32F101xG are referred to as XL-density devices.

Low-, high-density and XL-density devices are an extension of the STM32F101x8/B medium-density devices, they are specified in the STM32F101x4/6, STM32F101xC/D/E and STM32F101xF/G datasheets, respectively.

Low-density devices feature lower Flash memory and RAM capacities, less timers and peripherals. High-density devices have higher Flash memory and RAM densities, and additional peripherals like FSMC and DAC. XL-density devices bring greater Flash and

RAM capacities, and more features, namely an MPU, a higher number of timers and a dual bank Flash memory, while remaining fully compatible with the other members of the family.

The STM32F101x4, STM32F101x6, STM32F101xC, STM32F101xD, STM32F101xE,

STM32F101xF and STM32F101xG are a drop-in replacement for the STM32F101x8/B devices, allowing the user to try different memory densities and providing a greater degree of freedom during the development cycle.

Moreover, the STM32F101xx access line family is fully compatible with all existing

STM32F103xx performance line and STM32F102xx USB access line devices.

Table 3. STM32F101xx family

Memory size

Low-density devices Medium-density devices High-density devices XL-density devices

Pinout 16 KB

Flash

32 KB

Flash

(1)

64 KB

Flash

128 KB

Flash

256 KB

Flash

384 KB

Flash

512 KB

Flash

768 KB

Flash

1 MB

Flash

4 KB RAM 6 KB RAM 10 KB RAM 16 KB RAM

32 KB

RAM

48 KB

RAM

48 KB

RAM

80 KB

RAM

80 KB

RAM

144

100

64 2 × USARTs

2 × 16-bit timers

1 × SPI, 1 × I

1 × ADC

3 × USARTs

3 × 16-bit timers

2 × SPIs, 2 × I2Cs,

1 × ADC

5 × USARTs

4 × 16-bit timers,

2 × basic timers

3 × SPIs, 2 × I

Cs,

1 × ADC, 1 × DAC

FSMC (100 and 144 pins)

5 × USARTs

10 × 16-bit timers,

2 × basic timers

3 × SPIs, 2 × I

Cs,

1 × ADC, 1 × DAC

FSMC (100 and 144 pins), Cortex-M3 with

MPU, Dual bank Flash memory

1. For orderable part numbers that do not show the A internal code after the temperature range code (6), the reference datasheet for electrical characteristics is that of the STM32F101x8/B medium-density devices.

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STM32F101xF, STM32F101xG Description

2.3 Overview

2.3.1 ARM

Cortex

-M3 core with embedded Flash and SRAM

The ARM ® Cortex ® -M3 processor is the latest generation of ARM ® processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.

The ARM ® Cortex ® -M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM ® core in the memory size usually associated with 8- and 16-bit devices.

The STM32F101xF and STM32F101xG access line family having an embedded ARM ® core, is therefore compatible with all ARM ® tools and software.

Figure 1 shows the general block diagram of the device family.

2.3.2 Memory protection unit

The memory protection unit (MPU) is used to separate the processing of tasks from the data protection. The MPU can manage up to 8 protection areas that can all be further divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory.

The memory protection unit is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-time operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

2.3.4

768 Kbytes to 1 Mbyte of embedded Flash are available for storing programs and data. The

Flash memory is organized as two banks. The first bank has a size of 512 Kbytes. The second bank is either 256 or 512 Kbytes depending on the device. This gives the device the capability of writing to one bank while executing code from the other bank (read-while-write capability).

CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.

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Description STM32F101xF, STM32F101xG

2.3.6

2.3.7

2.3.8

80 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states.

FSMC (flexible static memory controller)

The FSMC is embedded in the STM32F101xF and STM32F101xG access line family. It has four Chip Select outputs supporting the following modes: PC Card/Compact Flash, SRAM,

PSRAM, NOR and NAND.

Functionality overview:

• The three FSMC interrupt lines are ORed in order to be connected to the NVIC

• Write FIFO

• Code execution from external memory except for NAND Flash and PC Card

• The targeted frequency is HCLK/2, so external access is at 18 MHz when HCLK is at

36 MHz

LCD parallel interface

The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or highperformance solutions using external controllers with dedicated acceleration.

Nested vectored interrupt controller (NVIC)

The STM32F101xF and STM32F101xG access line embeds a nested vectored interrupt controller able to handle up to 60 maskable interrupt channels (not including the 16 interrupt lines of Cortex ® -M3) and 16 priority levels.

• Closely coupled NVIC gives low-latency interrupt processing

• Interrupt entry vector table address passed directly to the core

• Closely coupled NVIC core interface

• Allows early processing of interrupts

• Processing of late arriving higher priority interrupts

• Support for tail-chaining

• Processor state automatically saved

• Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt latency.

The external interrupt/event controller consists of 19 edge detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 112 GPIOs can be connected to the 16 external interrupt lines.

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STM32F101xF, STM32F101xG Description

2.3.10 Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock is available when necessary (for example with failure of an indirectly used external oscillator).

Several prescalers are used to configure the AHB frequency, the high-speed APB (APB2) domain and the low-speed APB (APB1) domain. The maximum frequency of the AHB and

APB domains is 36 MHz. See

Figure 2 for details on the clock tree.

At startup, boot pins are used to select one of three boot options:

• Boot from user Flash: you have an option to boot from any of two memory banks. By default, boot from Flash memory bank 1 is selected. You can choose to boot from Flash memory bank 2 by setting a bit in the option bytes.

• Boot from system memory

• Boot from embedded SRAM

The bootloader is located in system memory. It is used to reprogram the Flash memory by using USART1.

2.3.12 Power supply schemes

• V

= 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.

Provided externally through V

pins.

• V

SSA

, V

DDA

= 2.0 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL (minimum voltage to be applied to V

DDA

DAC is used). V

DDA

and V

SSA

must be connected to V

DD is 2.4 V when the ADC or

and V

, respectively.

• V

BAT

= 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when V

is not present.

For more details on how to connect power pins, refer to

Figure 9: Power supply scheme .

2.3.13 Power supply supervisor

The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains in reset mode when V

DD external reset circuit.

is below a specified threshold, V

POR/PDR

, without the need for an

The device features an embedded programmable voltage detector (PVD) that monitors the

DDA

power supply and compares it to the V

PVD

threshold. An interrupt can be generated when V higher than the V

PVD

DDA

drops below the V

PVD

threshold and/or when V

DDA

threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to

Table 12: Embedded reset and power control block characteristics for the values of

POR/PDR

and V

PVD

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Description STM32F101xF, STM32F101xG

The regulator has three operation modes: main (MR), low power (LPR) and power down.

• MR is used in the nominal regulation mode (Run)

• LPR is used in the Stop modes.

• Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost)

This regulator is always enabled after reset. It is disabled in Standby mode.

Note:

The STM32F101xF and STM32F101xG access line supports three low-power modes to achieve the best compromise between low-power consumption, short startup time and available wakeup sources:

• Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

• Stop mode

Stop mode achieves the lowest power consumption while retaining the content of

SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode.

The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output or the RTC alarm.

• Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The

PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering

Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs.

The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode.

2.3.16 DMA

The flexible 12-channel general-purpose DMAs (7 channels for DMA1 and 5 channels for

DMA2) are able to manage memory-to-memory, peripheral-to-memory and memory-toperipheral transfers.

The two DMA controllers support circular buffer management, removing the need for user code intervention when the controller reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent.

DMA can be used with the main peripherals: SPI, I

C, USART, general-purpose and basic timers TIMx, DAC and ADC.

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STM32F101xF, STM32F101xG Description

2.3.17 RTC (real-time clock) and backup registers

The RTC and the backup registers are supplied through a switch that takes power either on

supply when present or through the V

BAT

pin. The backup registers are forty-two 16-bit registers used to store 84 bytes of user application data when V

power is not present.

They are not reset by a system or power reset, and they are not reset when the device wakes up from the Standby mode.

The real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power RC oscillator or the high speed external clock divided by 128. The internal low-speed RC has a typical frequency of 40 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation. The RTC features a 32-bit programmable counter for long term measurement using the Compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz.

2.3.18 Timers and watchdogs

The XL-density STM32F101xx access line devices include up to ten general-purpose timers, two basic timers, two watchdog timers and a SysTick timer.

Table 4: STM32F101xF and STM32F101xG timer feature comparison compares the

features of the general-purpose and basic timers.

Timer

TIM2, TIM3,

TIM4, TIM5

TIM9, TIM12

TIM10, TIM11,

TIM13, TIM14

TIM6, TIM7

Table 4. STM32F101xF and STM32F101xG timer feature comparison

Counter resolution

Counter type

Prescaler factor

DMA request generation

Capture/compare channels

Complementary outputs

16-bit

Up, down, up/down

Any integer between

1 and 65536

Any integer between

1 and 65536

Any integer between

1 and 65536

Any integer between

1 and 65536

Yes

General-purpose timers (TIMx)

There are 10 synchronizable general-purpose timers embedded in the STM32F101xF and

STM32F101xG XL-density access line devices (see Table 4

for differences).

• TIM2, TIM3, TIM4, TIM5

There are up to 4 synchronizable general-purpose timers (TIM2, TIM3, TIM4 and TIM5) embedded in the STM32F101xF and STM32F101xG access line devices.

These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input capture/output compare, PWM or

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Description STM32F101xF, STM32F101xG one-pulse mode output. This gives up to 16 input captures / output compares / PWMs on the largest packages.

Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs. They all have independent DMA request generation.

These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors.

• TIM10, TIM11 and TIM9

These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.

TIM10 and TIM11 feature one independent channel, whereas TIM9 has two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be used as simple time bases.

• TIM13, TIM14 and TIM12

These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.

TIM13 and TIM14 feature one independent channel, whereas TIM12 has two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be used as simple time bases.

Basic timers TIM6 and TIM7

These timers are mainly used for DAC trigger generation. They can also be used as a generic 16-bit time base.

Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode.

Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features:

• A 24-bit down counter

• Autoreload capability

• Maskable system interrupt generation when the counter reaches 0.

• Programmable clock source

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STM32F101xF, STM32F101xG Description

Up to two I²C bus interfaces can operate in multi-master and slave modes. They support standard and fast modes.

They support 7/10-bit addressing mode and 7-bit dual addressing mode (as slave). A hardware CRC generation/verification is embedded.

They can be served by DMA and they support SMBus 2.0/PMBus.

The STM32F101xF and STM32F101xG access line embeds three universal synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3) and two universal asynchronous receiver transmitters (UART4 and UART5).

These five interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. The five interfaces are able to communicate at speeds of up to 2.25 Mbit/s.

USART1, USART2 and USART3 also provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller except for UART5.

2.3.21 Serial peripheral interface (SPI)

Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes.

All SPIs can be served by the DMA controller.

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions. All GPIOs are high currentcapable.

The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers.

A 12-bit analog-to-digital converter is embedded into STM32F101xF and STM32F101xG access line devices. It has up to 16 external channels, performing conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs.

The ADC can be served by the DMA controller.

An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.

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Description STM32F101xF, STM32F101xG

The events generated by the general-purpose timers (TIMx) can be internally connected to the ADC start trigger and injection trigger, respectively, to allow the application to synchronize A/D conversion and timers.

The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration.

This dual digital Interface supports the following features:

• two DAC converters: one for each output channel

• 8-bit or 12-bit monotonic output

• left or right data alignment in 12-bit mode

• synchronized update capability

• noise-wave generation

• triangular-wave generation

• dual DAC channel independent or simultaneous conversions

• DMA capability for each channel

• external triggers for conversion

• input voltage reference V

REF+

Seven DAC trigger inputs are used in the STM32F101xF and STM32F101xG access line family. The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels.

The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 2 V < V

DDA

< 3.6 V. The temperature sensor is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value.

The ARM

SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.

The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

The ARM ® Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the

STM32F10xxx through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. TPA hardware is commercially available from common development tool vendors. It operates with third party debugger software tools.

22/117

DocID16553 Rev 5

STM32F101xF, STM32F101xG

3 Pinouts and pin descriptions

Figure 3. LQFP144 pinout

Pinouts and pin descriptions

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1. The above figure shows the package top view.

DocID16553 Rev 5

23/117

Pinouts and pin descriptions

Figure 4. LQFP100 pinout

STM32F101xF, STM32F101xG

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1. The above figure shows the package top view.

24/117

DocID16553 Rev 5

STM32F101xF, STM32F101xG

Figure 5. LQFP64 pinout

Pinouts and pin descriptions s d

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Pins

1. The above figure shows the package top view.

Table 5. STM32F101xF/STM32F101xG pin definitions

Alternate functions

(4)

Pin name

Main function

(3)

(after reset) Default Remap

1 1

2 2

3 3

4 4

5 5

PE2

PE3

PE4

PE5

PE6

6 1 6 V

BAT

7 2 7 PC13-TAMPER-RTC

(5)

8 3 8 PC14-OSC32_IN

(5)

9 4 9 PC15-OSC32_OUT

(5)

10 -

11 -

PF0

PF1

I/O FT

S -

I/O -

I/O FT

PE2

PE3

PE4

PE5

PE6

BAT

PC13

(6)

PC14

(6)

PC15

(6)

PF0

PF1

TRACECLK / FSMC_A23

TRACED0 / FSMC_A19

TRACED1 / FSMC_A20

TRACED2 / FSMC_A21

TRACED3 / FSMC_A22

TAMPER-RTC

OSC32_IN

OSC32_OUT

FSMC_A0

FSMC_A1

TIM9_CH1

TIM9_CH2

DocID16553 Rev 5

25/117

Pinouts and pin descriptions

Pins

STM32F101xF, STM32F101xG

Table 5. STM32F101xF/STM32F101xG pin definitions (continued)

Alternate functions

(4)

Pin name

Main function

(3)

(after reset) Default Remap

22 -

23 5 12

24 6 13

25 7 14

26 8 15

27 9 16

28 10 17

29 11 18

30 12 19

31 20

32 21

33 13 22

12 -

13 -

14 -

15 -

16 10

17 11

18 -

19 -

20 -

21 -

34 14 23

35 15 24

36 16 25

PF2

PF3

PF4

PF5

SS_5

DD_5

PF6

PF7

PF8

PF9

PF10

OSC_IN

OSC_OUT

NRST

PC0

PC1

PC2

PC3

SSA

REF-

REF+

DDA

PA0-WKUP

PA1

PA2

I/O -

S -

I/O -

I -

O -

I/O -

I/O FT

S -

I/O -

PF2

PF3

PF4

PF5

SS_5

DD_5

PF6

PF7

PF8

PF9

PF10

OSC_IN

OSC_OUT

NRST

PC0

PC1

PC2

PC3

SSA

REF-

REF+

DDA

I/O -

I/O

I/O -

PA0

PA1

PA2

FSMC_A2

FSMC_A3

FSMC_A4

FSMC_A5

FSMC_NIORD

FSMC_NREG

FSMC_NIOWR

FSMC_CD

FSMC_INTR

ADC_IN10

ADC_IN11

ADC_IN12

ADC_IN13

WKUP/ USART2_CTS

(8)

ADC_IN0 / TIM5_CH1/

TIM2_CH1_ETR

(8)

USART2_RTS

(8)

ADC_IN1 / TIM5_CH2

TIM2_CH2

(8)

USART2_TX

(8)

TIM5_CH3 / ADC_IN2/

TIM2_CH3

(8)

/ TIM9_CH1

TIM10_CH1

TIM11_CH1

TIM13_CH1

TIM14_CH1

PD0

(7)

PD1

(7)

26/117

DocID16553 Rev 5

STM32F101xF, STM32F101xG

Pins

Pinouts and pin descriptions

Table 5. STM32F101xF/STM32F101xG pin definitions (continued)

Alternate functions

(4)

Pin name

Main function

(3)

(after reset) Default Remap

37 17 26

38 18 27

39 19 28

40 20 29

41 21 30

42 22 31

43 23 32

44 24 33

45 25 34

46 26 35

47 27 36

48 28 37

49 -

50 -

51 -

52 -

53 -

54 -

55 -

56 -

57 -

58 38

59 39

60 40

61 -

PA6

PA7

PF12

SS_6

DD_6

PF13

PF14

PF15

PG0

PG1

PE7

PC4

PC5

PB0

PB1

PB2

PF11

PE8

PE9

SS_7

PA3

SS_4

DD_4

PA4

PA5

I/O

PA3

SS_4

DD_4

PA4

PA5

PA6

PA7

I/O -

PC4

PC5

PB0

I/O PB1

I/O FT PB2/BOOT1

I/O FT PF11

I/O FT

S -

I/O FT

S -

PF12

SS_6

DD_6

PF13

PF14

PF15

PG0

PG1

PE7

PE8

PE9

SS_7

USART2_RX

(8)

/ TIM5_CH4/

ADC_IN3 / TIM2_CH4

(8)

TIM9_CH2

SPI1_NSS/ DAC_OUT1 /

ADC_IN4 / USART2_CK

(8)

SPI1_SCK / DAC_OUT2 /

ADC_IN5

SPI1_MISO / ADC_IN6 /

TIM3_CH1

(8)

/ TIM13_CH1

SPI1_MOSI / ADC_IN7 /

TIM3_CH2

(8)

/ TIM14_CH1

ADC_IN14 -

ADC_IN15 -

ADC_IN8 / TIM3_CH3

(8)

ADC_IN9 / TIM3_CH4

(8)

FSMC_NIOS16 -

FSMC_A6

FSMC_A7

FSMC_A8

FSMC_A9

FSMC_A10

FSMC_A11

FSMC_D4

FSMC_D5

FSMC_D6

DocID16553 Rev 5

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Pinouts and pin descriptions

Pins

STM32F101xF, STM32F101xG

Table 5. STM32F101xF/STM32F101xG pin definitions (continued)

Alternate functions

(4)

Pin name

Main function

(3)

(after reset) Default Remap

75 35 53

76 36 54

77 55

78 56

79 57

80 58

81 59

82 60

83 -

84 -

85 61

86 62

87 -

62 -

63 41

64 42

65 43

66 44

67 45

68 46

69 29 47

70 30 48

71 31 49

72 32 50

73 33 51

74 34 52

28/117

PB14

PB15

PD8

PD9

PD10

PD11

PD12

PD13

SS_8

DD_8

PD14

PD15

PG2

DD_7

PE10

PE11

PE12

PE13

PE14

PE15

PB10

PB11

SS_1

DD_1

PB12

PB13

S -

I/O FT

S -

I/O FT

S -

I/O FT

PB14

PB15

PD8

PD9

PD10

PD11

PD12

PD13

SS_8

DD_8

PD14

PD15

PG2

DD_7

PE10

PE11

PE12

PE13

PE14

PE15

PB10

PB11

SS_1

DD_1

PB12

PB13

FSMC_D7

FSMC_D8

FSMC_D9

FSMC_D10

FSMC_D11

FSMC_D12

I2C2_SCL / USART3_TX

(8)

I2C2_SDA / USART3_RX

(8)

SPI2_NSS

(8)

/ I2C2_SMBA /

USART3_CK

(8)

SPI2_SCK

(8)

USART3_CTS

(8)

SPI2_MISO

(8)

USART3_RTS

(8)

TIM12_CH1

SPI2_MOSI

(8)

/ TIM12_CH2

FSMC_D13

FSMC_D14

FSMC_D15

FSMC_A16

FSMC_A17

FSMC_A18

FSMC_D0

FSMC_D1

FSMC_A12

USART3_TX

USART3_RX

USART3_CK

USART3_CTS

TIM4_CH1 /

USART3_RTS

TIM4_CH2

TIM4_CH3

TIM4_CH4

TIM2_CH3

TIM2_CH4

DocID16553 Rev 5

STM32F101xF, STM32F101xG

Pins

Pinouts and pin descriptions

Table 5. STM32F101xF/STM32F101xG pin definitions (continued)

Alternate functions

(4)

Pin name

Main function

(3)

(after reset) Default Remap

98 39 65

99 40 66

100 41 67

101 42 68

102 43 69

103 44 70

104 45 71

105 46 72

106 73

107 47 74

108 48 75

88 -

89 -

90 -

91 -

92 -

93 -

94 -

95 -

96 37 63

97 38 64

109 49 76

110 50 77

111 51 78

112 52 79

113 53 80

114 81

115 82

SS_2

DD_2

PA14

PA15

PC10

PC11

PC12

PD0

PD1

PG3

PG4

PG5

PG6

PG7

PG8

SS_9

DD_9

PC6

PC7

PC8

PC9

PA8

PA9

PA10

PA11

PA12

PA13

I/O FT

S -

I/O FT

PG3

PG4

PG5

PG6

PG7

PG8

SS_9

DD_9

PC6

PC7

PC8

PC9

PA8

PA9

PA10

PA11

FSMC_A13

FSMC_A14

FSMC_A15

FSMC_INT2

FSMC_INT3

USART1_CK / MCO

USART1_TX

(8)

USART1_RX

(8)

USART1_CTS

I/O FT PA12

I/O FT JTMS-SWDIO

Not connected

USART1_RTS

S -

I/O FT

SS_2

DD_2

JTCK-

SWCLK

JTDI

PC10

PC11

PC12

SPI3_NSS

UART4_TX

UART4_RX

UART5_TX

FSMC_D2

(9)

FSMC_D3

(9)

TIM3_CH1

TIM3_CH2

TIM3_CH3

TIM3_CH4

PA13

PA14

TIM2_CH1_ETR/

PA15 /SPI1_NSS

USART3_TX

USART3_RX

USART3_CK

DocID16553 Rev 5

29/117

Pinouts and pin descriptions

Pins

STM32F101xF, STM32F101xG

Table 5. STM32F101xF/STM32F101xG pin definitions (continued)

Alternate functions

(4)

Pin name

Main function

(3)

(after reset) Default Remap

116 54 83

117 84

118 85

119 86

120 -

121 -

122 87

123 88

124 -

125 -

126 -

127 -

128 -

129 -

130 -

131 -

132 -

133 55 89

134 56 90

135 57 91

136 58 92

137 59 93

138 60 94

139 61 95

140 62 96

30/117

PG10

PG11

PG12

PG13

PG14

SS_11

DD_11

PG15

PD2

PD3

PD4

PD5

SS_10

DD_10

PD6

PD7

PG9

PB3

PB4

PB5

PB6

PB7

BOOT0

PB8

PB9

I/O FT

S -

I/O FT

S -

I/O FT

I/O -

I/O FT

I -

I/O FT

PB5

PB6

PB7

BOOT0

PB8

PB9

PG10

PG11

PG12

PG13

PG14

SS_11

DD_11

PG15

PD2

PD3

PD4

PD5

SS_10

DD_10

PD6

PD7

PG9

JTDO

NJTRST

TIM3_ETR / UART5_RX

FSMC_CLK

FSMC_NOE

FSMC_NWE

FSMC_NWAIT

FSMC_NE1 / FSMC_NCE2

FSMC_NE2 / FSMC_NCE3

FSMC_NE3 /

FSMC_NCE4_1

FSMC_NCE4_2

FSMC_NE4

FSMC_A24

FSMC_A25

SPI3_SCK

SPI3_MISO

I2C1_SMBA/ SPI3_MOSI

I2C1_SCL / TIM4_CH1

(8)

I2C1_SDA / FSMC_NADV /

TIM4_CH2 (8)

TIM4_CH3

(8)

/ TIM10_CH1

TIM4_CH4

(8)

/ TIM11_CH1

USART2_CTS

USART2_RTS

USART2_TX

USART2_RX

USART2_CK

TIM2_CH2 /PB3

TRACESWO

SPI1_SCK

PB4 / TIM3_CH1

SPI1_MISO

TIM3_CH2 /

SPI1_MOSI

USART1_TX

USART1_RX

I2C1_SCL

I2C1_SDA

DocID16553 Rev 5

STM32F101xF, STM32F101xG

Pins

Pinouts and pin descriptions

Table 5. STM32F101xF/STM32F101xG pin definitions (continued)

Alternate functions

(4)

Pin name

Main function

(3)

(after reset) Default Remap

141 97 PE0 I/O FT PE0 TIM4_ETR

(8)

/ FSMC_NBL0 -

142 98 PE1 I/O FT PE1 FSMC_NBL1 -

143 63 99

144 64 100

SS_3

DD_3

S -

SS_3

DD_3

1. I = input, O = output, S = supply.

2. FT = 5 V tolerant.

3. Function availability depends on the chosen device.

4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).

5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current

(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).

6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the

Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the

STMicroelectronics website: www.st.com

7. For the LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100 and LQFP144 packages, PD0 and PD1 are available by default, so there is no need for remapping. For more details, refer to Alternate function I/O and debug configuration section in the STM32F10xxx reference manual

8. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com

9. For devices delivered in LQFP64 packages, the FSMC function is not available.

DocID16553 Rev 5

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PG1

PE7

PE8

PE9

PE10

PE11

PF11

PF12

PF13

PF14

PF15

PG0

PE12

PE13

PE14

PE15

PD8

PF3

PF4

PF5

PF6

PF7

PF8

PF9

PF10

PE6

PF0

PF1

PF2

PE2

PE3

PE4

PE5

Pinouts and pin descriptions

Pins

STM32F101xF, STM32F101xG

NIOS16

A10

NIORD

NREG

NIOWR

INTR

D10

D11

D12

D13

NIOS16

NIORD

NREG

NIOWR

INTR

D10

D11

D12

D13

NOR/PSRAM/

SRAM

A11

A10

D10

D11

D12

D13

A22

A23

A19

A20

A21

Table 6. FSMC pin definition

FSMC

CF/IDE

NOR/PSRAM

Mux

DA4

DA5

DA6

DA7

DA8

DA9

DA10

DA11

DA12

DA13

A22

A23

A19

A20

A21

NAND 16 bit

LQFP100 (1)

D10

D11

D12

D13

Yes

32/117

DocID16553 Rev 5

STM32F101xF, STM32F101xG Pinouts and pin descriptions

Pins

Table 6. FSMC pin definition (continued)

FSMC

CF/IDE

NOR/PSRAM/

SRAM

NOR/PSRAM

Mux

NAND 16 bit

LQFP100

(1)

NOE

NWE

NWAIT

NCE4_1

NCE4_2

D14

D15

NOE

NWE

NWAIT

NCE4_1

NCE4_2

D14

D15

PG9

PG10

PG11

PG12

PG13

PG14

PD1

PD3

PD4

PD5

PD6

PD7

PB7

PE0

PE1

PG3

PG4

PG5

PG6

PG7

PD0

PD9

PD10

PD11

PD12

PD13

PD14

PD15

PG2

1. Ports F and G are not available in devices delivered in 100-pin packages.

NE2

NE3

NE4

A24

A25

CLK

NOE

NWE

NWAIT

NE1

NADV

NBL0

NBL1

A13

A14

A15

A18

A12

D14

D15

A16

A17

NE2

NE3

NE4

A24

A25

DA3

CLK

NOE

NWE

NWAIT

NE1

NADV

NBL0

NBL1

DA2

DA14

DA15

A16

A17

A18

DA0

DA1

D14

D15

CLE

ALE

NCE3

NOE

NWE

NWAIT

NCE2

INT2

INT3

Yes

DocID16553 Rev 5

33/117

Memory mapping STM32F101xF, STM32F101xG

34/117

The memory map is shown in

Figure 6 .

Figure 6. Memory map

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DocID16553 Rev 5

STM32F101xF, STM32F101xG Electrical characteristics

5.1.1

Unless otherwise specified, all voltages are referenced to V

Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T

A the selected temperature range).

= 25 °C and T

= T

A max (given by

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3 Σ ).

Unless otherwise specified, typical data are based on T

2 V ≤ V tested.

= 25 °C, V

= 3.3 V (for the

≤ 3.6 V voltage range). They are given only as design guidelines and are not

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2 Σ ).

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

The loading conditions used for pin parameter measurement are shown in

Figure 7 .

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Electrical characteristics

5.1.5 Pin input voltage

STM32F101xF, STM32F101xG

The input voltage measurement on a pin of the device is described in Figure 8

Figure 7. Pin loading conditions Figure 8. Pin input voltage

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& S) 9,1

5.1.6 Power supply scheme

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Figure 9 , the 4.7 µF capacitor must be connected to V

DD3

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36/117

DocID16553 Rev 5

STM32F101xF, STM32F101xG Electrical characteristics

Figure 10. Current consumption measurement scheme

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Absolute maximum ratings

Stresses above the absolute maximum ratings listed in

Table 7: Voltage characteristics ,

Table 8: Current characteristics , and Table 9: Thermal characteristics

may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Symbol

Table 7. Voltage characteristics

Ratings Min Max Unit

(2)

− V

DDx

SSX

− V

ESD(HBM)

External main supply voltage (including

DDA and V

)

(1)

Input voltage on five volt tolerant pin

–0.3

4.0

Input voltage on any other pin

− 0.3

+ 4.0

4.0

Variations between different V

DD power pins

Variations between all the different ground pins including V

REF-

Electrostatic discharge voltage (human body model)

see Section 5.3.12: Absolute maximum ratings (electrical sensitivity)

V mV

1. All main power (V , V

DDA

) and ground (V supply, in the permitted range.

, V

SSA

) pins must always be connected to the external power

2. V

maximum must always be respected. Refer to Table 8: Current characteristics for the maximum

allowed injected current values.

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Electrical characteristics STM32F101xF, STM32F101xG

Symbol

Table 8. Current characteristics

Ratings Max.

Unit

Σ I

VDD

VSS

Total current into V

DDA power lines (source)

(1)

Total current out of V

SS ground lines (sink)

(1)

Output current sunk by any I/O and control pin

150

INJ(PIN)

(2)

Output current source by any I/Os and control pin

Injected current on five volt tolerant pins

(3)

Injected current on any other pin

(4)

Total injected current (sum of all I/O and control pins)

(5)

−

-5/+0

± 5 mA

Σ I

INJ(PIN)

± 25

1. All main power (V , V

DDA

) and ground (V supply, in the permitted range.

, V

SSA

) pins must always be connected to the external power

2. Negative injection disturbs the analog performance of the device. See note 3 below

Table 59 on page 95 .

3. Positive injection is not possible on these I/Os. A negative injection is induced by V values.

. I

INJ(PIN)

must

never be exceeded. Refer to Table 7: Voltage characteristics

for the maximum allowed input voltage

4. A positive injection is induced by V

never be exceeded. Refer to

values.

while a negative injection is induced by V

Table 7: Voltage characteristics

. I

for the maximum allowed input voltage

must

5. When several inputs are submitted to a current injection, the maximum Σ I positive and negative injected currents (instantaneous values).

INJ(PIN)

is the absolute sum of the

Symbol

STG

Table 9. Thermal characteristics

Ratings

Storage temperature range

Maximum junction temperature

Value

–65 to +150

150

Unit

°C

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DocID16553 Rev 5

STM32F101xF, STM32F101xG Electrical characteristics

5.3.1 General operating conditions

Symbol

Table 10. General operating conditions

Parameter Conditions Min Max Unit f f

V f

HCLK

PCLK1

PCLK2

DDA

(1)

Internal AHB clock frequency

Internal APB1 clock frequency

Internal APB2 clock frequency

Standard operating voltage

Analog operating voltage

(ADC not used)

Analog operating voltage

(ADC used)

Backup operating voltage

Must be the same potential as V

(2)

2.4

3.6

MHz

BAT

Power dissipation at T

85 °C

(3)

Ambient temperature

LQFP144

LQFP100

1.8

3.6

666

434

LQFP64 444

Maximum power dissipation –40 low-power dissipation

(4)

–40 105

V mW

Junction temperature range

1. When the ADC is used, refer to Table 56: ADC characteristics .

2. It is recommended to power V between V

and V

DDA

and V

DDA

from the same source. A maximum difference of 300 mV

can be tolerated during power-up and operation.

3. If T is lower, higher P

Thermal characteristics

values are allowed as long as T

does not exceed T

max (see Section 6.4:

4. In low-power dissipation state, T can be extended to this range as long as T

Section 6.4: Thermal characteristics ).

does not exceed T

J max (see

°C

The parameters given in

Table 11

are derived from tests performed under the ambient temperature condition summarized in

Table 10 .

Symbol t

VDD

Table 11. Operating conditions at power-up / power-down

Parameter Conditions Min Max

rise time rate

fall time rate

∞

Unit

µs/V

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Electrical characteristics

5.3.3

STM32F101xF, STM32F101xG

Embedded reset and power control block characteristics

The parameters given in

Table 12 are derived from tests performed under ambient

temperature and V

supply voltage conditions summarized in

Table 10 .

Symbol

Table 12. Embedded reset and power control block characteristics

Parameter Conditions Min Typ Max Unit

PLS[2:0]=000 (rising edge)

PLS[2:0]=000 (falling edge)

PLS[2:0]=001 (rising edge)

PLS[2:0]=001 (falling edge)

PLS[2:0]=010 (rising edge)

PLS[2:0]=010 (falling edge)

PLS[2:0]=011 (rising edge)

2.1

2.18

2.26

2 2.08

2.16

2.19

2.28

2.37

2.09

2.18

2.27

2.28

2.38

2.48

2.18

2.28

2.38

2.48

2.58

PVD

Programmable voltage detector level selection

PLS[2:0]=011 (falling edge)

PLS[2:0]=100 (rising edge)

PLS[2:0]=100 (falling edge)

PLS[2:0]=101 (rising edge)

PLS[2:0]=101 (falling edge)

2.28

2.38

2.48

2.47

2.58

2.69

2.37

2.48

2.59

2.57

2.68

2.79

2.47

2.58

2.69

PLS[2:0]=110 (rising edge)

PLS[2:0]=110 (falling edge)

PLS[2:0]=111 (rising edge)

2.66

2.56

2.76

2.78

2.68

2.88

2.9

2.8

PLS[2:0]=111 (falling edge) 2.66

2.78

2.9

PVDhyst

(2) PVD hysteresis 100 mV

POR/PDR

Power on/power down reset threshold

Falling edge 1.8

(1) 1.88

1.96

Rising edge 1.84

1.92

2.0

PDRhyst

(2) t

RSTTEMPO

(2)

PDR hysteresis

Reset temporization -

1.5

1. The product behavior is guaranteed by design down to the minimum V

POR/PDR

value.

2. Guaranteed by design.

2.5

3.5

V mV ms

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DocID16553 Rev 5

STM32F101xF, STM32F101xG Electrical characteristics

5.3.5

The parameters given in

Table 13 are derived from tests performed under ambient

temperature and V

supply voltage conditions summarized in

Table 10 .

Symbol

Table 13. Embedded internal reference voltage

Parameter Conditions Min Typ Max Unit

REFINT

Internal reference voltage

S_vrefint

(1)

ADC sampling time when reading the internal reference voltage

–40 °C < T

< +85 °C 1.16

1.20

1.24

5.1

17.1

(2)

RERINT

(2)

Internal reference voltage spread over the temperature range

= 3 V ±10 mV 10

µs mV

Coeff

(2)

Temperature coefficient 100 ppm/

°C

1. Shortest sampling time can be determined in the application by multiple iterations.

2. Guaranteed by design.

Supply current characteristics

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code.

The current consumption is measured as described in

Figure 10: Current consumption measurement scheme

All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to Dhrystone 2.1 code.

Maximum current consumption

The MCU is placed under the following conditions:

• All I/O pins are in input mode with a static value at V

or V

(no load)

• All peripherals are disabled except if it is explicitly mentioned

• The Flash access time is adjusted to f

HCLK wait state from 24 to 36 MHz)

frequency (0 wait state from 0 to 24 MHz, 1

• Prefetch in on (reminder: this bit must be set before clock setting and bus prescaling)

• When the peripherals are enabled f

PCLK1

= f

HCLK/2

, f

PCLK2

= f

HCLK

The parameters given in

Table 14 are derived from tests performed under ambient

temperature and V

supply voltage conditions summarized in

Table 10 .

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Electrical characteristics STM32F101xF, STM32F101xG

Table 14. Maximum current consumption in Run mode, code with data processing running from Flash

Max

(1)

Symbol Parameter Conditions f

HCLK

Unit

= 85 °C

36 MHz 41

Supply current in Run mode

External clock

(2)

, all peripherals enabled

External clock

(2)

, all peripherals disabled

24 MHz

16 MHz

8 MHz

36 MHz

24 MHz

16 MHz

8 MHz

12.5

17.5

8.5

1. Guaranteed by characterization results.

2. External clock is 8 MHz and PLL is on when f

HCLK

> 8 MHz.

Table 15. Maximum current consumption in Run mode, code with data processing running from RAM

Max

(1)

Symbol Parameter Conditions f

HCLK

Unit

= 85 °C

Supply current in

Run mode

External clock

(2)

, all peripherals enabled

External clock

(2)

all peripherals disabled

36 MHz

24 MHz

16 MHz

8 MHz

36 MHz

24 MHz

16 MHz

8 MHz

26.5

11.5

20.5

7.5

1. Guaranteed by characterization results, tested in production at V

DD max, f

HCLK

max.

2. External clock is 8 MHz and PLL is on when f

HCLK

> 8 MHz.

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STM32F101xF, STM32F101xG Electrical characteristics

Figure 11. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled

8 MHz

16 MHz

24 MHz

36 MHz

-45 25

Temperature (°C)

70 85

Figure 12. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals disabled

8 MHz

16 MHz

24 MHz

36 MHz

-45 25

Temperature (°C)

70 85

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Electrical characteristics STM32F101xF, STM32F101xG

Table 16. Maximum current consumption in Sleep mode, code running from Flash or

RAM

Max

(1)

Symbol Parameter Conditions f

HCLK

Unit

= 85 °C

36 MHz 27.5

Supply current in

Sleep mode

External clock

(2)

all peripherals enabled

External clock

(2)

, all peripherals disabled

24 MHz

16 MHz

8 MHz

36 MHz

24 MHz

16 MHz

8 MHz

5.9

5.4

4.7

6.9

1. Guaranteed by characterization results, tested in production at V enabled.

DD max, f

HCLK

max with peripherals

2. External clock is 8 MHz and PLL is on when f

HCLK

> 8 MHz.

Table 17. Typical and maximum current consumptions in Stop and Standby modes

Typ

(1)

Max

Symbol Parameter Conditions V

BAT

2.0 V

BAT

2.4 V

= 3.3 V

85 °C

Unit

Supply current in Stop mode

Regulator in Run mode,

Low-speed and high-speed internal RC oscillators and high-speed oscillator

OFF (no independent watchdog)

Regulator in Low-power mode,

Low-speed and high-speed internal RC oscillators and high-speed oscillator

OFF (no independent watchdog)

Low-speed internal RC oscillator and independent watchdog ON

Supply current in Standby mode

Low-speed internal RC oscillator ON, independent watchdog OFF

Low-speed internal RC oscillator and independent watchdog OFF, low-speed oscillator and RTC OFF

DD_VBAT

Backup domain supply current

Low-speed oscillator and RTC ON

1. Typical values are measured at T

= 25 °C.

2. Guaranteed by characterization results.

1.05

34.5

24.5

2.8

1.9

1.1

3.8

3.6

2.1

1.4

379

365

(2)

µA

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STM32F101xF, STM32F101xG Electrical characteristics

Figure 13. Typical current consumption on V different V

BAT

with RTC on vs. temperature at

values

7HPSHUDWXUH&

Figure 14. Typical current consumption in Standby mode versus temperature at different V

values

1.5

0.5

3.5

2.5

2.4V

2.7V

3.0V

3.3V

3.6V

-45 25

Temperature (°C)

70 85

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Electrical characteristics STM32F101xF, STM32F101xG

Typical current consumption

The MCU is placed under the following conditions:

• All I/O pins are in input mode with a static value at V

or V

(no load)

• All peripherals are disabled except if it is explicitly mentioned

• The Flash access time is adjusted to f

HCLK wait state from 24 to 36 MHz)

frequency (0 wait state from 0 to 24 MHz, 1

• Prefetch is on (reminder: this bit must be set before clock setting and bus prescaling)

• When the peripherals are enabled f

PCLK1 f

PCLK2

= f

HCLK/4

, f

PCLK2

= f

HCLK/2

, f

ADCCLK

• When the peripherals are enabled f

PCLK1

= f

HCLK

, f

PCLK2

= f

HCLK

, f

ADCCLK

= f

PCLK2

The parameters given in

Table 18 are derived from tests performed under ambient

temperature and V

supply voltage conditions summarized in

Table 10 .

Table 18. Typical current consumption in Run mode, code with data processing running from Flash

Typ

(1)

Typ

(1)

Symbol Parameter Conditions f

HCLK All peripherals enabled

(2)

All peripherals disabled

Unit

Supply current in

Run mode

External clock

(3)

Running on high speed internal RC

(HSI), AHB prescaler used to reduce the frequency

36 MHz

24 MHz

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

125 kHz

36 MHz

24 MHz

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

125 kHz

28.5

24.1

7.7

4.6

2.2

1.7

1.4

27.5

18.9

12.2

7.2

2.3

1.5

1.1

0.75

1. Typical values are measures at T

= 25 °C, V

= 3.3 V.

2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).

3. External clock is 8 MHz and PLL is on when f

HCLK

> 8 MHz.

3.4

2.3

1.8

1.5

1.3

17.5

18.7

12.8

9.2

5.4

11.6

8.2

4.8

2.7

1.7

1.2

0.9

0.7

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STM32F101xF, STM32F101xG Electrical characteristics

Table 19. Typical current consumption in Sleep mode, code running from Flash or

RAM

Typ

(1)

Typ

(1)

Symbol Parameter Conditions f

HCLK All peripherals enabled

(2)

All peripherals disabled

Unit

Supply current in

Sleep mode

External clock

(3)

Running on High

Speed Internal

RC (HSI), AHB prescaler used to reduce the frequency

125 kHz

36 MHz

24 MHz

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

125 kHz

36 MHz

24 MHz

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

17.7

12.2

8.4

4.6

2.15

1.7

1.5

1.35

11.6

7.7

3.9

2.3

1.5

1.1

0.9

0.7

1. Typical values are measures at T

= 25 °C, V

= 3.3 V.

2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).

3. External clock is 8 MHz and PLL is on when f

HCLK

> 8 MHz.

0.7

0.6

0.5

1.15

3.35

2.3

1.6

0.8

1.3

1.25

1.2

1.15

3.1

2.3

1.5

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in

Table 20 . The MCU is placed

under the following conditions:

• all I/O pins are in input mode with a static value at V

or V

(no load)

• all peripherals are disabled unless otherwise mentioned

• the given value is calculated by measuring the current consumption

– with all peripherals clocked off

– with only one peripheral clocked on

• ambient operating temperature and V

Table 7

supply voltage conditions summarized in

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Electrical characteristics STM32F101xF, STM32F101xG

Table 20. Peripheral current consumption (1)

Peripherals

AHB (up to 36MHz)

APB1 (up to 18 MHz)

DMA1

DMA2

FSMC

CRC

BusMatrix

(2)

APB1-Bridge

TIM2

TIM3

TIM4

TIM5

TIM6

TIM7

TIM12

TIM13

TIM14

SPI2/I2S2

(3)

SPI3/I2S3

(3)

USART2

USART3

UART4

UART5

I2C1

I2C2

DAC

(4)

WWDG

PWR

BKP

IWDG

µA/MHz

35.56

33.61

7.78

19.17

12.22

13.33

8.33

12.22

23.06

18.47

55.14

2.08

11.67

8.61

37.22

36.39

12.22

10.28

9.17

3.06

2.50

2.78

4.44

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STM32F101xF, STM32F101xG Electrical characteristics

Table 20. Peripheral current consumption (1)

(continued)

Peripherals µA/MHz

APB2 (up to 36MHz)

APB2-Bridge 2.78

GPIOA 7.64

GPIOB

GPIOC

7.64

GPIOD

GPIOE

GPIOF

GPIOG

8.47

8.19

SPI1

USART1

TIM9

TIM10

TIM11

ADC1 (5)(6)

5.14

16.67

11.81

8.47

17.68

1. f

HCLK

= 36 MHz, f

APB1

= f

HCLK/2

, f

APB2

= f

HCLK

, default prescaler value for each peripheral.

2. The BusMatrix is automatically active when at least one master peripheral is ON.

When the I2S is enabled. a current consumption of 0.02 mA must be added.

4. When DAC_OUT1 or DAC_OUT2 is enabled, a current consumption of 0.36 mA must be added.

5. Specific conditions for ADC: f = 28 MHz, f = f

HCLK/2

, f = f

HCLK

, f

ADCCLK

= f

APB2

/2. When

6. When the ADC is enabled, a current consumption of 0,1 mA must be added.

High-speed external user clock generated from an external source

The characteristics given in

Table 21 result from tests performed using an high-speed

external clock source, and under ambient temperature and supply voltage conditions summarized in

Table 10 .

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Electrical characteristics STM32F101xF, STM32F101xG

Symbol

Table 21. High-speed external user clock characteristics

Parameter Conditions f

HSE_ext

HSEH

User external clock source frequency

(1)

OSC_IN input pin high level voltage

HSEL

OSC_IN input pin low level voltage

t w(HSE) t w(HSE) t r(HSE) t f(HSE)

C in(HSE)

DuCy

(HSE)

OSC_IN high or low time

OSC_IN rise or fall time

(1)

OSC_IN input capacitance

Duty cycle

(1)

OSC_IN Input leakage current V

≤ V

1. Guaranteed by design.

Min

0.7V

Typ

Max

0.3V

±1

Unit

MHz

V ns pF

µA

Low-speed external user clock generated from an external source

The characteristics given in

Table 22 result from tests performed using an low-speed

external clock source, and under ambient temperature and supply voltage conditions summarized in

Table 10 .

Symbol

Table 22. Low-speed user external clock characteristics

Parameter f

LSE_ext

LSEH

User external clock source frequency (1)

OSC32_IN input pin high level voltage

LSEL

OSC32_IN input pin low level voltage t w(LSE) t w(LSE) t r(LSE) t f(LSE)

OSC32_IN high or low time

OSC32_IN rise or fall time

C in(LSE)

OSC32_IN input capacitance

(1)

DuCy

(LSE)

Duty cycle

OSC32_IN Input leakage current

(1)

1. Guaranteed by design.

Conditions

≤ V

Min

0.7V

450

Typ

32.768

Max

1000

0.3V

±1

Unit kHz

V ns pF

µA

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STM32F101xF, STM32F101xG Electrical characteristics

Figure 15. High-speed external clock source AC timing diagram

9+6(+

9+6(/

U+6(

+6(

([WHUQDOFORFNVRXUFH

+6(BH[W

26&B,1

:+6(

670)[[[

DLE

Figure 16. Low-speed external clock source AC timing diagram

9/6(+

9/6(/

WU/6(

7/6(

WI/6(

([WHUQDO

FORFNVRXUFH

I/6(BH[W 26&B,1

W:/6(

670)[[[

W:/6( W

DLG

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Electrical characteristics STM32F101xF, STM32F101xG

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on

characterization results obtained with typical external components specified in Table 23

. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Symbol

Table 23. HSE 4-16 MHz oscillator characteristics (1)(2)

Parameter Conditions Min Typ Max Unit f

OSC_IN

Oscillator frequency

Feedback resistor

200

MHz k Ω i

Recommended load capacitance versus equivalent serial resistance of the crystal (R

)

(3)

= 30 Ω

HSE driving current

= 3.3 V

= V load

SS with 30 pF -

1 pF mA g m t

SU(HSE)

(4)

Oscillator transconductance

Startup time

Startup

is stabilized

2 -

mA/V ms

1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

2. Guaranteed by characterization results.

3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions.

4. t

SU(HSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer

For C

and C

, it is recommended to use high-quality external ceramic capacitors in the

5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see

Figure 17

). C

and C

L2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C

and C

. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing

and C

. Refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com

52/117

DocID16553 Rev 5

STM32F101xF, STM32F101xG Electrical characteristics

Figure 17. Typical application with an 8 MHz crystal

5HVRQDWRUZLWK

LQWHJUDWHGFDSDFLWRUV

0+ ]

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5(;7

26&B,1

26&B28 7

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JDLQ

I+6(

670)[[[

DLE

1. R

EXT

value depends on the crystal characteristics.

Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on

characterization results obtained with typical external components specified in Table 24

Symbol

Table 24. LSE oscillator characteristics (f

LSE

= 32.768 kHz) (1) (2)

Parameter Conditions Min Typ Max Unit

Feedback resistor 5 M Ω

Recommended load capacitance versus equivalent serial resistance of the crystal (R

)

= 30 K Ω 15 pF

LSE driving current

= 3.3 V

= V

1.4

µA g m

Oscillator transconductance 5 µA/V t

SU(LSE)

(3)

Startup time

is stabilized

= 50 °C

= 25 °C

= 10 °C

= 0 °C

= -10 °C

= -20 °C

= -30 °C

= -40 °C -

1.5

2.5

60 -

1. Guaranteed by characterization results.

2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for

ST microcontrollers”.

3. t

SU(LSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer s

DocID16553 Rev 5

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Electrical characteristics STM32F101xF, STM32F101xG

Note: For C

and C

, it is recommended to use high-quality ceramic capacitors in the 5 pF to

15 pF range selected to match the requirements of the crystal or resonator. C

and C

L2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C

and C

Load capacitance C

has the following formula: C

= C

x C

/ ( C

C stray between 2 pF and 7 pF.

+ C

) + C stray

where

is the pin capacitance and board or trace PCB-related capacitance. Typically, it is

Caution: To avoid exceeding the maximum value of C

and C to use a resonator with a load capacitance C

L capacitance of 12.5 pF.

(15 pF) it is strongly recommended

≤ 7 pF. Never use a resonator with a load

Example: if you choose a resonator with a load capacitance of C

L then C

= C

= 8 pF.

= 6 pF, and C stray

= 2 pF,

Figure 18. Typical application with a 32.768 kHz crystal

5.3.7

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.+ ]

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Internal clock source characteristics

The parameters given in

Table 25 are derived from tests performed under ambient

temperature and V

supply voltage conditions summarized in

Table 10 .

High-speed internal (HSI) RC oscillator

Symbol

Table 25. HSI oscillator characteristics (1)

Parameter Conditions Min Typ Max Unit f

HSI

DuCy

ACC

(HSI)

HSI

Frequency

Duty cycle

Accuracy of the HSI oscillator

User-trimmed with the RCC_CR register

(2)

Factorycalibrated

(4)

= –40 to 105 °C –2

= –10 to 85 °C –1.5

= 0 to 70 °C

= 25 °C

–1.3

–1.1

HSI oscillator startup time

HSI oscillator power consumption

1. V

= 3.3 V, T

= –40 to 85 °C unless otherwise specified.

(3)

2.5

2.2

1.8

100

MHz

µs

µA

54/117

DocID16553 Rev 5

STM32F101xF, STM32F101xG Electrical characteristics

2. Refer to application note AN2868 “STM32F10xxx internal RC oscillator (HSI) calibration” available from the ST website www.st.com

3. Guaranteed by design.

4. Guaranteed by characterization results.

Low-speed internal (LSI) RC oscillator

Table 26. LSI oscillator characteristics (1)

Symbol Parameter Min f

LSI

(2) t su(LSI)

(3)

DD(LSI)

(3)

Frequency 30

LSI oscillator startup time

LSI oscillator power consumption

1. V

= 3 V, T

= –40 to 85 °C unless otherwise specified.

2. Guaranteed by characterization results.

3. Guaranteed by design.

Typ

0.65

Max

1.2

Unit kHz

µs

µA

Wakeup time from low-power mode

The wakeup times given in

Table 27 are measured on a wakeup phase with an 8-MHz HSI

RC oscillator. The clock source used to wake up the device depends from the current operating mode:

• Stop or Standby mode: the clock source is the RC oscillator

• Sleep mode: the clock source is the clock that was set before entering Sleep mode.

All timings are derived from tests performed under ambient temperature and V

DD voltage conditions summarized in

Table 10 .

supply

Symbol

Table 27. Low-power mode wakeup timings

Parameter Typ Unit t

WUSLEEP

(1) Wakeup from Sleep mode 1.8

µs t

WUSTOP

(1)

Wakeup from Stop mode (regulator in run mode) 3.6

µs

Wakeup from Stop mode (regulator in low-power mode) 5.4

WUSTDBY

(1)

Wakeup from Standby mode 50

1. The wakeup times are measured from the wakeup event to the point at which the user application code reads the first instruction.

µs

DocID16553 Rev 5

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Electrical characteristics STM32F101xF, STM32F101xG

The parameters given in

Table 28 are derived from tests performed under ambient

temperature and V

supply voltage conditions summarized in

Table 10 .

Table 28. PLL characteristics

Value

Symbol Parameter Unit

Min (1)

Typ Max (1) f

PLL_IN f

PLL_OUT t

LOCK

Jitter

PLL input clock

(2)

PLL input clock duty cycle

PLL multiplier output clock

PLL lock time

Cycle-to-cycle jitter

8.0

200

300

MHz

µs ps

1. Guaranteed by characterization results.

2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by f

PLL_OUT

Flash memory

The characteristics are given at T

= –40 to 85 °C unless otherwise specified.

Symbol t prog t

ERASE t

Table 29. Flash memory characteristics

Parameter Conditions Min

16-bit programming time

Page (2 KB) erase time

Mass erase time

Supply current

V prog

Programming voltage

1. Guaranteed by design.

= –40 to +85 °C

Read mode f

HCLK

= 36 MHz with 1 wait state, V

= 3.3 V

Write mode f

HCLK

3.3 V

= 36 MHz, V

Erase mode f

HCLK

3.3 V

= 36 MHz, V

Power-down mode / Halt,

= 3.0 to 3.6 V

Typ Max

(1)

52.5

3.6

Unit

µs ms ms mA mA mA

µA

56/117

DocID16553 Rev 5

STM32F101xF, STM32F101xG Electrical characteristics

Symbol

Table 30. Flash memory endurance and data retention

Value

Parameter Conditions

Min

(1)

N t

END

RET

Endurance

Data retention

= –40 °C to 85 °C

= 85 °C, 1 kcycle

(2)

= 55 °C, 10 kcycle

(2)

1. Guaranteed by characterization results.

2. Cycling performed over the whole temperature range.

Unit kcycles

Years

Asynchronous waveforms and timings

Figure 19

through Figure 22 represent asynchronous waveforms and

Table 31 through

Table 34 provide the corresponding timings. The results shown in these tables are obtained

with the following FSMC configuration:

• AddressSetupTime = 0

• AddressHoldTime = 1

• DataSetupTime = 1

DocID16553 Rev 5

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Electrical characteristics STM32F101xF, STM32F101xG

Figure 19. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms

Z1(

)60&B1(

Y12(B1(

Z12(

K1(B12(

)60&B12(

Note:

)60&B1:(

Y$B1( W

K$B12(

)60&B$>@

$GGUHVV

Y%/B1( W

K%/B12(

)60&B1%/>@

VX'DWDB12(

VX'DWDB1(

'DWD

K'DWDB1(

K'DWDB12(

)60&B'>@

Y1$'9B1(

Z1$'9

)60&B1$'9

069

1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.

FSMC_BusTurnAroundDuration = 0.

Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings

(1) (2)

Symbol Parameter Min Max Unit t w(NE) t v(NOE_NE) t w(NOE) t h(NE_NOE) t v(A_NE) t h(A_NOE) t v(BL_NE) t h(BL_NOE) t su(Data_NE) t su(Data_NOE) t h(Data_NOE)

FSMC_NE low time

FSMC_NEx low to FSMC_NOE low

FSMC_NOE low time

FSMC_NOE high to FSMC_NE high hold time

FSMC_NEx low to FSMC_A valid

Address hold time after FSMC_NOE high

FSMC_NEx low to FSMC_BL valid

FSMC_BL hold time after FSMC_NOE high

Data to FSMC_NEx high setup time

Data to FSMC_NOEx high setup time

Data hold time after FSMC_NOE high

HCLK

+ 0.5

0.5

HCLK

– 1

0.5

HCLK

- 1

HCLK

- 1

HCLK

+ 2

1.5

HCLK

+ 1

ns ns ns ns ns ns ns ns ns ns ns

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DocID16553 Rev 5

STM32F101xF, STM32F101xG Electrical characteristics

Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings (1) (2)

Symbol Parameter Min Max Unit t h(Data_NE) t v(NADV_NE) t w(NADV)

Data hold time after FSMC_NEx high

FSMC_NEx low to FSMC_NADV low

FSMC_NADV low time

1. C

= 15 pF.

2. Guaranteed by characterization results.

0 t

HCLK

+ 2 ns ns ns

Figure 20. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms

WZ1(

)60&B1([

)60&B12(

WY1:(B1( WZ1:( W K1(B1:(

)60&B1:(

)60&B$>@

)60&B1%/>@

)60&B'>@

WY$B1(

WY%/B1(

WY'DWDB1(

WK$B1:(

$GGUHVV

WK%/B1:(

1%/

WK'DWDB1:(

'DWD

W Y1$'9B1(

WZ1$'9

)60&B1$'9

1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.

Table 32. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings (1)(2)

Symbol Parameter Min Max Unit t w(NE) t v(NWE_NE) t w(NWE) t h(NE_NWE) t v(A_NE) t h(A_NWE) t v(BL_NE) t h(BL_NWE) t v(Data_NE)

FSMC_NE low time

FSMC_NEx low to FSMC_NWE low

FSMC_NWE low time

HCLK

+ 0.5

HCLK

+ 1.5

ns t

HCLK

+ 0.5

HCLK

– 0.5

HCLK t

+ 1.5

HCLK

+ 1 ns ns

FSMC_NWE high to FSMC_NE high hold time t

HCLK

– 0.5

FSMC_NEx low to FSMC_A valid -

0 ns ns

Address hold time after FSMC_NWE high

FSMC_NEx low to FSMC_BL valid

FSMC_BL hold time after FSMC_NWE high

FSMC_NEx low to Data valid t

HCLK

– 1.5

1.5

HCLK ns ns ns

DocID16553 Rev 5

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Electrical characteristics STM32F101xF, STM32F101xG

Table 32. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings (1)(2)

Symbol Parameter Min Max Unit t h(Data_NWE) t v(NADV_NE) t w(NADV)

Data hold time after FSMC_NWE high

FSMC_NEx low to FSMC_NADV low

FSMC_NADV low time

1. C

= 15 pF.

2. Guaranteed by characterization results.

HCLK

0 t

HCLK

+ 1.5

ns ns ns

Figure 21. Asynchronous multiplexed NOR/PSRAM read waveforms

W.%

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V./%?.%

H.%?./%

&3-#?./%

W./%

&3-#?.7%

V!?.%

H!?./%

&3-#?!;=

!DDRESS

V",?.% T

H",?./%

&3-#?.",;= .",

H$ATA?.%

&3-#?!$;=

V!?.%

!DDRESS

V.!$6?.%

W.!$6

H!$?.!$6

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SU$ATA?./%

$ATA

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&3-#?.!$6

AIB

Table 33. Asynchronous multiplexed NOR/PSRAM read timings (1)(2)

Symbol t w(NE) t v(NOE_NE) t w(NOE) t h(NE_NOE) t v(A_NE) t v(NADV_NE) t w(NADV) t h(AD_NADV)

Parameter

FSMC_NE low time

FSMC_NEx low to FSMC_NOE low

FSMC_NOE low time

FSMC_NOE high to FSMC_NE high hold time

FSMC_NEx low to FSMC_A valid

FSMC_NEx low to FSMC_NADV low

FSMC_NADV low time

FSMC_AD (address) valid hold time after

FSMC_NADV high

Min t

HCLK

Max

HCLK

+ 0.5

HCLK

+ 2

HCLK

+ 0.5

HCLK

+ 1.5

HCLK

0.5

– 1 4t

HCLK

+ 1

0 t

HCLK

+ 0.5

ns t

HCLK

+ 2 ns

Unit ns

60/117

DocID16553 Rev 5

STM32F101xF, STM32F101xG Electrical characteristics

Table 33. Asynchronous multiplexed NOR/PSRAM read timings (1)(2) (continued)

Symbol Parameter Min Max Unit t h(A_NOE) t h(BL_NOE) t v(BL_NE) t su(Data_NE) t su(Data_NOE) t h(Data_NE) t h(Data_NOE)

Address hold time after FSMC_NOE high

FSMC_BL hold time after FSMC_NOE high

FSMC_NEx low to FSMC_BL valid

Data to FSMC_NEx high setup time

Data to FSMC_NOE high setup time

Data hold time after FSMC_NEx high

Data hold time after FSMC_NOE high

1. C

= 15 pF.

2. Guaranteed by characterization results.

HCLK

-2

0.5

HCLK

- 0.5

HCLK

- 1

DocID16553 Rev 5

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Electrical characteristics STM32F101xF, STM32F101xG

Figure 22. Asynchronous multiplexed NOR/PSRAM write waveforms

WZ1(

)60&B1([

)60&B12(

WY1:(B1( WZ1:( W K1(B1:(

)60&B1:(

)60&B$>@

)60&B1%/>@

)60&B$'>@

WY$B1(

WY%/B1(

W Y$B1(

$GGUHVV

W Y1$'9B1(

WZ1$'9

WK$B1:(

$GGUHVV

WK%/B1:(

1%/

WY'DWDB1$'9

'DWD

WK$'B1$'9

WK'DWDB1:(

)60&B1$'9

DL%

Table 34. Asynchronous multiplexed NOR/PSRAM write timings (1)(2)

Symbol Parameter t w(NE) t v(NWE_NE) t w(NWE) t h(NE_NWE) t v(A_NE) t v(NADV_NE) t w(NADV)

FSMC_NE low time

FSMC_NEx low to FSMC_NWE low

FSMC_NWE low time

FSMC_NWE high to FSMC_NE high hold time

FSMC_NEx low to FSMC_A valid

FSMC_NEx low to FSMC_NADV low t h(AD_NADV)

FSMC_NADV low time

FSMC_AD (address) valid hold time after

FSMC_NADV high t h(A_NWE) t v(BL_NE) t h(BL_NWE) t v(Data_NADV) t h(Data_NWE)

Address hold time after FSMC_NWE high

FSMC_NEx low to FSMC_BL valid

FSMC_BL hold time after FSMC_NWE high

FSMC_NADV high to Data valid

Data hold time after FSMC_NWE high

1. C

= 15 pF.

2. Guaranteed by characterization results.

Min

HCLK

+ 0.5

HCLK

+ 2 ns t

HCLK

+ 1 t

HCLK

+ 1.5

3t t

HCLK

– 1

- 0.5

HCLK

+ 2 ns

3.5

0 1 ns t

HCLK

+ 0.5

HCLK

+ 1.5

ns t

HCLK

– 0.5

HCLK

– 2

HCLK

– 1.5

HCLK

– 0.5

Max

0.5

HCLK

+ 6

Unit ns ns ns ns ns ns

62/117

DocID16553 Rev 5

STM32F101xF, STM32F101xG Electrical characteristics

Synchronous waveforms and timings

Figure 23

through Figure 26

represent synchronous waveforms and Table 36

through

Table 38 provide the corresponding timings. The results shown in these tables are obtained

with the following FSMC configuration:

• BurstAccessMode = FSMC_BurstAccessMode_Enable;

• MemoryType = FSMC_MemoryType_CRAM;

• WriteBurst = FSMC_WriteBurst_Enable;

• CLKDivision = 1; (0 is not supported, see the STM32F10xxx reference manual)

• DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM

Figure 23. Synchronous multiplexed NOR/PSRAM read timings

)60&B&/.

WZ&/.

%867851

WG&/./1([/

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WG&/./1([+

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WG&/./1$'9/

)60&B1$'9

WG&/./1$'9+

WG&/./$9 WG&/./$,9

)60&B$>@

WG&/.+12(/ WG&/./12(+

)60&B12(

WG&/./$'9

)60&B$'>@

WG&/./$',9

WVX$'9&/.+

$'>@

WVX1:$,79&/.+

)60&B1:$,7

:$,7&)* E:$,732/E

WVX1:$,79&/.+

WK&/.+$'9

WVX$'9&/.+

WK&/.+1:$,79

WK&/.+$'9

WK&/.+1:$,79

)60&B1:$,7

:$,7&)* E:$,732/E

WVX1:$,79&/.+ WK&/.+1:$,79

DLK

DocID16553 Rev 5

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Electrical characteristics STM32F101xF, STM32F101xG

Table 35. Synchronous multiplexed NOR/PSRAM read timings (1)(2)

Symbol Parameter Min Max t w(CLK) t d(CLKL-NExL) t d(CLKL-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKL-AIV) t d(CLKL-NOEL) t d(CLKL-NOEH) t d(CLKL-ADV) t d(CLKL-ADIV)

FSMC_CLK period

FSMC_CLK low to FSMC_NEx low (x = 0...2)

FSMC_CLK low to FSMC_NEx high (x = 0...2)

FSMC_CLK low to FSMC_NADV low

FSMC_CLK low to FSMC_NADV high

FSMC_CLK low to FSMC_Ax valid (x = 16...25)

FSMC_CLK low to FSMC_Ax invalid (x = 16...25)

FSMC_CLK low to FSMC_NOE low

FSMC_CLK low to FSMC_NOE high

FSMC_CLK low to FSMC_AD[15:0] valid

FSMC_CLK low to FSMC_AD[15:0] invalid t su(ADV-CLKH)

FSMC_A/D[15:0] valid data before FSMC_CLK high t h(CLKH-ADV) t su(NWAITV-CLKH) t h(CLKH-NWAITV)

FSMC_A/D[15:0] valid data after FSMC_CLK high

FSMC_NWAIT valid before FSMC_CLK high

FSMC_NWAIT valid after FSMC_CLK high

1. C

= 15 pF.

2. Guaranteed by characterization results.

0.5

1.5

55.5

0.5

2 -

0.5

Unit

64/117

DocID16553 Rev 5

STM32F101xF, STM32F101xG Electrical characteristics

Figure 24. Synchronous multiplexed PSRAM write timings

&3-#?#,+

TW#,+ TW#,+

"53452.

$ATALATENCY

TD#,+,.%X, TD#,+,.%X(

&3-#?.%X

TD#,+,.!$6,

&3-#?.!$6

TD#,+,.!$6(

TD#,+,!6 TD#,+,!)6

&3-#?!;=

TD#,+,.7%, TD#,+,.7%(

&3-#?.7%

TD#,+,!$6

&3-#?!$;=

TD#,+,!$)6

TD#,+,$ATA

!$;=

TD#,+,$ATA

$ $

&3-#?.7!)4

7!)4#&'B7!)40/,B

TSU.7!)46#,+(

&3-#?.",

TH#,+(.7!)46

TD#,+,.",(

AIG

DocID16553 Rev 5

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Electrical characteristics STM32F101xF, STM32F101xG

Symbol

Table 36. Synchronous multiplexed PSRAM write timings (1)(2)

Parameter Min Max Unit t w(CLK) t d(CLKL-NExL) t d(CLKL-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKL-AIV) t d(CLKL-NWEL) t d(CLKL-NWEH) t d(CLKL-ADV) t d(CLKL-ADIV) t d(CLKL-Data) t d(CLKL-NBLH) t su(NWAITV-CLKH) t h(CLKH-NWAITV)

FSMC_CLK period

FSMC_CLK low to FSMC_Nex low (x = 0...2)

FSMC_CLK low to FSMC_NEx high (x = 0...2)

FSMC_CLK low to FSMC_NADV low

FSMC_CLK low to FSMC_NADV high

FSMC_CLK low to FSMC_Ax valid (x = 16...25)

FSMC_CLK low to FSMC_Ax invalid (x = 16...25)

FSMC_CLK low to FSMC_NWE low

FSMC_CLK low to FSMC_NWE high

FSMC_CLK low to FSMC_AD[15:0] valid

FSMC_CLK low to FSMC_AD[15:0] invalid

FSMC_A/D[15:0] valid after FSMC_CLK low

FSMC_CLK low to FSMC_NBL high

FSMC_NWAIT valid before FSMC_CLK high

FSMC_NWAIT valid after FSMC_CLK high

1. C

= 15 pF.

2. Guaranteed by characterization results.

1.5

27.5

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DocID16553 Rev 5

STM32F101xF, STM32F101xG Electrical characteristics

Figure 25. Synchronous non-multiplexed NOR/PSRAM read timings

&3-#?#,+

TW#,+ TW#,+

"53452.

TD#,+,.%X( TD#,+,.%X,

&3-#?.%X

TD#,+,.!$6,

&3-#?.!$6

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TD#,+,.!$6(

TD#,+,!6 TD#,+,!)6

&3-#?!;=

TD#,+(./%, TD#,+,./%(

&3-#?./%

&3-#?$;=

TSU$6#,+(

TSU.7!)46#,+(

TH#,+($6

TSU$6#,+(

TH#,+(.7!)46

TH#,+($6

&3-#?.7!)4

7!)4#&'B7!)40/,B

TSU.7!)46#,+( T H#,+(.7!)46

&3-#?.7!)4

7!)4#&'B7!)40/,B

TSU.7!)46#,+( TH#,+(.7!)46

AIG

Table 37. Synchronous non-multiplexed NOR/PSRAM read timings (1)(2)

Symbol Parameter t w(CLK) t d(CLKL-NExL) t d(CLKL-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKL-AIV) t d(CLKL-NOEL) t d(CLKL-NOEH) t su(DV-CLKH) t h(CLKH-DV) t su(NWAITV-CLKH) t h(CLKH-NWAITV)

1. C

= 15 pF.

FSMC_CLK period

FSMC_CLK low to FSMC_NEx low (x = 0...2)

FSMC_CLK low to FSMC_NEx high (x = 0...2)

FSMC_CLK low to FSMC_NADV low

FSMC_CLK low to FSMC_NADV high

FSMC_CLK low to FSMC_Ax valid (x = 0...25)

FSMC_CLK low to FSMC_Ax invalid (x = 0...25)

FSMC_CLK low to FSMC_NOE low

FSMC_CLK low to FSMC_NOE high

FSMC_D[15:0] valid data before FSMC_CLK high

FSMC_D[15:0] valid data after FSMC_CLK high

FSMC_NWAIT valid before FSMC_SMCLK high

FSMC_NWAIT valid after FSMC_CLK high

Min

27.6

1.5

3.5

Max Unit

0.5

1.5

HCLK

+ 1 ns

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Electrical characteristics STM32F101xF, STM32F101xG

2. Guaranteed by characterization results.

Figure 26. Synchronous non-multiplexed PSRAM write timings

)60&B&/.

WZ&/.

%867851

WG&/./1([/

'DWDODWHQF\

WG&/./1([+

)60&B1([

WG&/./1$'9/

)60&B1$'9

WG&/./1$'9+

WG&/./$9 WG&/./$,9

)60&B$>@

WG&/.+12(/ WG&/./12(+

)60&B12(

WG&/./$'9

)60&B$'>@

WG&/./$',9

WVX$'9&/.+

$'>@

WVX1:$,79&/.+

)60&B1:$,7

:$,7&)* E:$,732/E

WVX1:$,79&/.+

WK&/.+$'9

WVX$'9&/.+

WK&/.+1:$,79

WK&/.+$'9

WK&/.+1:$,79

)60&B1:$,7

:$,7&)* E:$,732/E

WVX1:$,79&/.+ WK&/.+1:$,79

DLK

Table 38. Synchronous non-multiplexed PSRAM write timings (1)(2)

Symbol Parameter Min Max Unit t w(CLK) t d(CLKL-NExL) t d(CLKL-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKL-AIV) t d(CLKL-NWEL) t d(CLKL-NWEH) t d(CLKL-Data) t d(CLKL-NBLH)

FSMC_CLK period

FSMC_CLK low to FSMC_NEx low (x = 0...2)

FSMC_CLK low to FSMC_NEx high (x = 0...2)

FSMC_CLK low to FSMC_NADV low

FSMC_CLK low to FSMC_NADV high

FSMC_CLK low to FSMC_Ax valid (x = 16...25)

FSMC_CLK low to FSMC_Ax invalid (x = 16...25)

FSMC_CLK low to FSMC_NWE low

FSMC_CLK low to FSMC_NWE high

FSMC_D[15:0] valid data after FSMC_CLK low

FSMC_CLK low to FSMC_NBL high

27.6

1.5

0.5

1.5

0.5

2.5

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STM32F101xF, STM32F101xG Electrical characteristics

Table 38. Synchronous non-multiplexed PSRAM write timings (1)(2) (continued)

Symbol Parameter Min Max Unit t su(NWAITV-CLKH) t h(CLKH-NWAITV)

FSMC_NWAIT valid before FSMC_CLK high

FSMC_NWAIT valid after FSMC_CLK high

1. C

= 15 pF.

2. Guaranteed by characterization results.

2 -

PC Card/CompactFlash controller waveforms and timings

Figure 27

through Figure 32

represent synchronous waveforms and Table 40

and

Table 41

provide the corresponding timings. The results shown in this table are obtained with the following FSMC configuration:

• COM.FSMC_SetupTime = 0x04;

• COM.FSMC_WaitSetupTime = 0x07;

• COM.FSMC_HoldSetupTime = 0x04;

• COM.FSMC_HiZSetupTime = 0x00;

• ATT.FSMC_SetupTime = 0x04;

• ATT.FSMC_WaitSetupTime = 0x07;

• ATT.FSMC_HoldSetupTime = 0x04;

• ATT.FSMC_HiZSetupTime = 0x00;

• IO.FSMC_SetupTime = 0x04;

• IO.FSMC_WaitSetupTime = 0x07;

• IO.FSMC_HoldSetupTime = 0x04;

• IO.FSMC_HiZSetupTime = 0x00;

• TCLRSetupTime = 0;

• TARSetupTime = 0;

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Electrical characteristics STM32F101xF, STM32F101xG

Figure 27. PC Card/CompactFlash controller waveforms for common memory read access

)60&B1&(B

WY1&([$ WK1&([$,

)60&B$>@

WG15(*1&([

WG1,25'1&([

WK1&([15(*

WK1&([1,25'

WK1&([1,2:5

)60&B15(*

)60&B1,2:5

)60&B1,25'

)60&B1:(

WG1&(B12(

)60&B12(

WZ12(

WVX'12( WK12('

)60&B'>@

DLE

1. FSMC_NCE4_2 remains high (inactive during 8-bit access.

Figure 28. PC Card/CompactFlash controller waveforms for common memory write access

)60&B1&(B

)60&B1&(B +LJK

WY1&(B$

)60&B$>@

)60&B15(*

)60&B1,2:5

)60&B1,25'

WG1&(B1:(

)60&B1:(

WG15(*1&(B

WG1,25'1&(B

WZ1:(

WK1&(B$,

WK1&(B15(*

WK1&(B1,25'

WK1&(B1,2:5

WG1:(1&(B

)60&B12(

0(0[+,=

WG'1:(

WY1:(' WK1:('

)60&B'>@

DLE

70/117

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STM32F101xF, STM32F101xG Electrical characteristics

Figure 29. PC Card/CompactFlash controller waveforms for attribute memory read access

)60&B1&(B

WY1&(B$ WK1&(B$,

)60&B1&(B

+LJK

)60&B$>@

)60&B1,2:5

)60&B1,25'

)60&B15(*

)60&B1:(

WG1&(B12(

)60&B12(

WG15(*1&(B

WZ12(

WVX'12(

)60&B'>@

WK1&(B15(*

WK12('

WG12(1&(B

DLE

1. Only data bits 0...7 are read (bits 8...15 are disregarded).

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Electrical characteristics STM32F101xF, STM32F101xG

Figure 30. PC Card/CompactFlash controller waveforms for attribute memory write access

)60&B1&(B

)60&B1&(B +LJK

WY1&(B$ WK1&(B$,

)60&B$>@

)60&B1,2:5

)60&B1,25'

WG15(*1&(B WK1&(B15(*

)60&B15(*

WG1&(B1:(

)60&B1:(

WZ1:(

WG1:(1&(B

)60&B12(

WY1:('

)60&B'>@

DLE

1. Only data bits 0...7 are driven (bits 8...15 remains HiZ).

Figure 31. PC Card/CompactFlash controller waveforms for I/O space read access

)60&B1&(B

WY1&([$ WK1&(B$,

)60&B$>@

)60&B15(*

)60&B1:(

)60&B12(

)60&B1,2:5

WG1,25'1&(B

)60&B1,25'

WZ1,25'

WVX'1,25' WG1,25''

)60&B'>@

DL%

72/117

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STM32F101xF, STM32F101xG Electrical characteristics

Figure 32. PC Card/CompactFlash controller waveforms for I/O space write access

)60&B1,2:5

WY1&([$ WK1&(B$,

)60&B$>@

)60&B15(*

)60&B1:(

)60&B12(

)60&B1,25'

WG1&(B1,2:5

)60&B1,2:5

WZ1,2:5

$77[+,=

WY1,2:5' WK1,2:5'

)60&B'>@

DLE

Symbol

Table 39. Switching characteristics for PC Card/CF read and write cycles in attribute/common space

Parameter Min Max t v(NCEx-A) t h(NCEx-AI) t d(NREG-NCEx) t h(NCEx-NREG) t d(NCEx_NWE) t d(NCEx_NOE) t w(NOE) t d(NOE-NCEx t su(D-NOE) t h(NOE-D) t w(NWE) t d(NWE_NCEx) t d(NCEx-NWE) t v(NWE-D) t h(NWE-D) t d(D-NWE)

FSMC_NCEx low to FSMC_Ay valid

FSMC_NCEx high to FSMC_Ax invalid

FSMC_NCEx low to FSMC_NREG valid

FSMC_NCEx high to FSMC_NREG invalid

FSMC_NCEx low to FSMC_NWE low

FSMC_NCEx low to FSMC_NOE low

FSMC_NOE low width

FSMC_NOE high to FSMC_NCEx high

FSMC_D[15:0] valid data before FSMC_NOE high

FSMC_NOE high to FSMC_D[15:0] invalid

FSMC_NWE low width

FSMC_NWE high to FSMC_NCEx high

FSMC_NCEx low to FSMC_NWE low

FSMC_NWE low to FSMC_D[15:0] valid

FSMC_NWE high to FSMC_D[15:0] invalid

FSMC_D[15:0] valid before FSMC_NWE high

HCLK

+ 4

HCLK

- 0.5

HCLK

- 0.5

32 t

HCLK

– 1

HCLK

+ 1.5

11t

HCLK

13t

HCLK

+ 2.5

HCLK

+ 1

HCLK

+ 1

HCLK

+ 1

HCLK

+ 4

HCLK

+ 1

Unit

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Electrical characteristics STM32F101xF, STM32F101xG

Table 40. Switching characteristics for PC Card/CF read and write cycles in I/O space

Symbol Parameter Min Max Unit tw

(NIOWR) tv

(NIOWR-D)

FSMC_NIOWR low width

FSMC_NIOWR low to FSMC_D[15:0] valid

8 THCLK

5 THCLK -

4 ns ns th

(NIOWR-D)

FSMC_NIOWR high to FSMC_D[15:0] invalid

11THCLK -

ns td

(NCE4_1-NIOWR)

FSMC_NCE4_1 low to FSMC_NIOWR valid -

5THCLK +

1 ns th

(NCEx-NIOWR)

FSMC_NCEx high to FSMC_NIOWR invalid

5THCLK -

2.5

ns td

(NIORD-NCEx)

FSMC_NCEx low to FSMC_NIORD valid -

5THCLK -

0.5 ns th

(NCEx-NIORD) tw

(NIORD) tsu

(D-NIORD) td

(NIORD-D)

FSMC_NCEx high to FSMC_NIORD) valid

FSMC_NIORD low width

FSMC_D[15:0] valid before FSMC_NIORD high

FSMC_D[15:0] valid after FSMC_NIORD high

5 THCLK -

0.5

8THCLK

ns ns ns ns

NAND controller waveforms and timings

Figure 33

through Figure 36

represent synchronous waveforms and Table 40

and

Table 41

provide the corresponding timings. The results shown in this table are obtained with the following FSMC configuration:

• COM.FSMC_SetupTime = 0x00;

• COM.FSMC_WaitSetupTime = 0x02;

• COM.FSMC_HoldSetupTime = 0x02;

• COM.FSMC_HiZSetupTime = 0x00;

• ATT.FSMC_SetupTime = 0x01;

• ATT.FSMC_WaitSetupTime = 0x02;

• ATT.FSMC_HoldSetupTime = 0x01;

• ATT.FSMC_HiZSetupTime = 0x00;

• Bank = FSMC_Bank_NAND;

• MemoryDataWidth = FSMC_MemoryDataWidth_16b;

• ECC = FSMC_ECC_Enable;

• ECCPageSize = FSMC_ECCPageSize_512Bytes;

• TCLRSetupTime = 0;

• TARSetupTime = 0;

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STM32F101xF, STM32F101xG Electrical characteristics

Figure 33. NAND controller waveforms for read access

)60&B1&([ /RZ

$/()60&B$

&/()60&B$

)60&B1:(

WG$/(12( WK12($/(

)60&B12(15(

WVX'12( WK12('

)60&B'>@

DLE

Figure 34. NAND controller waveforms for write access

)60&B1&([ /RZ

$/()60&B$

&/()60&B$

WG$/(1:(

)60&B1:(

WK1:($/(

)60&B12(15(

WY1:(' WK1:('

)60&B'>@

Figure 35. NAND controller waveforms for common memory read access

DLE

)60&B1&([ /RZ

$/()60&B$

&/()60&B$

)60&B1:(

WG$/(12( WK12($/(

WZ12(

)60&B12(

WVX'12( WK12('

)60&B'>@

DLE

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Electrical characteristics STM32F101xF, STM32F101xG

Figure 36. NAND controller waveforms for common memory write access

)60&B1&([ /RZ

$/()60&B$

&/()60&B$

WG$/(1:(

)60&B1:(

WZ1:( WK1:($/(

)60&B12(

WG'1:(

WY1:(' WK1:('

)60&B'>@

DLE

Symbol

Table 41. Switching characteristics for NAND Flash write cycles (1)

Parameter t w(NWE) t v(NWE-D) t h(NWE-D) t d(ALE-NWE) t h(NWE-ALE) t d(ALE-NOE) t h(NOE-ALE)

1. C

= 15 pF.

FSMC_NWE low width

FSMC_NWE low to FSMC_D[15:0] valid

FSMC_NWE high to FSMC_D[15:0] invalid

FSMC_ALE valid before FSMC_NWE low

FSMC_NWE high to FSMC_ALE invalid

FSMC_ALE valid before FSMC_NOE low

FSMC_NWE high to FSMC_ALE invalid

Min

HCLK

+ 2

HCLK

+ 8

HCLK

Max Unit

HCLK

+ 1.5

HCLK

ns ns

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (Electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports), the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

• FTB : A Burst of Fast Transient voltage (positive and negative) is applied to V

SS compliant with the IEC 61000-4-4 standard.

and

through a 100 pF capacitor, until a functional disturbance occurs. This test is

A device reset allows normal operations to be resumed.

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STM32F101xF, STM32F101xG Electrical characteristics

The test results are given in

Table 42

. They are based on the EMS levels and classes defined in application note AN1709.

Symbol

FESD

EFTB

Table 42. EMS characteristics

Parameter Conditions

Voltage limits to be applied on any I/O pin to induce a functional disturbance

= 3.3 V, LQFP144,

= +25 °C, f

HCLK

= 36 MHz conforms to IEC 61000-4-2

Fast transient voltage burst limits to be applied through 100 pF on V

and V

SS pins to induce a functional disturbance

= 3.3 V, LQFP144,

+25 °C, f

HCLK

= 36 MHz conforms to IEC 61000-4-4

Level/Class

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and pre qualification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

• Corrupted program counter

• Unexpected reset

• Critical Data corruption (control registers...)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device is monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with

IEC 61967-2 standard which specifies the test board and the pin loading.

Table 43. EMI characteristics

Symbol Parameter

EMI

Conditions

Monitored frequency band

Peak level

= 3.3 V, T

= 25 °C,

LQFP144 package compliant with

IEC 61967-2

0.1 MHz to 30 MHz

30 MHz to 130 MHz

130 MHz to 1 GHz

SAE EMI Level

Max vs. [f

HSE

HCLK

]

Unit

8/36 MHz

4 dBµV

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Electrical characteristics STM32F101xF, STM32F101xG

5.3.12 Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/JESD22-C101 standard.

Symbol

Table 44. ESD absolute maximum ratings

Ratings Conditions Class

Maximum value

(1)

Unit

ESD(HBM)

Electrostatic discharge voltage (human body model)

= +25 °C, conforming to

JESD22-A114

ESD(CDM)

Electrostatic discharge voltage (charge device model)

= +25 °C, conforming to

JESD22-C101

1. Guaranteed by characterization results.

III

2000

500

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up performance:

• A supply overvoltage is applied to each power supply pin

• A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD 78 IC latch-up standard.

Symbol

Parameter

Table 45. Electrical sensitivities

Conditions

Static latch-up class T

= +85 °C conforming to JESD78A

Class

II level A

78/117

As a general rule, current injection to the I/O pins, due to external voltage below V

SS above V

(for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.

Functional susceptibilty to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (>5

LSB TUE), out of spec current injection on adjacent pins or other functional failure (for example reset, oscillator frequency deviation).

DocID16553 Rev 5

STM32F101xF, STM32F101xG Electrical characteristics

The test results are given in

Table 46

Symbol

INJ

Table 46. I/O current injection susceptibility

Functional susceptibility

Description

Negative injection

Positive injection

Injected current on OSC_IN32,

OSC_OUT32, PA4, PA5, PC13

Injected current on all FT pins

Injected current on any other pin

-0

-5

Unit mA

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Electrical characteristics STM32F101xF, STM32F101xG

General input/output characteristics

Unless otherwise specified, the parameters given in Table 47

are derived from tests

performed under the conditions summarized in Table 10

All I/Os are CMOS and TTL compliant.

Symbol Parameter

Table 47. I/O static characteristics

Conditions Min Typ Max Unit

V hys

I lkg

Standard IO input low level voltage

IO FT

(1) voltage

input low level

Standard IO input high level voltage

IO FT (1) input high level voltage

> 2 V

2 V

Standard IO Schmitt trigger voltage hysteresis

(2)

IO FT Schmitt trigger voltage hysteresis

(2)

Input leakage current

(4)

≤ V

Standard I/Os

= 5 V

I/O FT

–0.3

0.41*(V

-2 V)+1.3 V -

0.42*(V

-2 V)+1 V

200

5% V

(3)

0.28*(V

-2 V)+0.8 V

0.32*(V

-2V)+0.75 V V

+0.3

5.5

5.2

± 1

V mV mV

µA

Weak pull-up equivalent resistor

(5)

Weak pull-down equivalent resistor

(5)

= V

50 k Ω k Ω

I/O pin capacitance 5 -

1. FT = Five-volt tolerant. In order to sustain a voltage higher than V disabled.

+0.3 the internal pull-up/pull-down resistors must be

2. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization results.

3. With a minimum of 100 mV.

4. Leakage could be higher than maximum value if negative current is injected on adjacent pins.

5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

PMOS/NMOS contribution to the series resistance is minimum (~10% order)

All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in

Figure 37

and

Figure 38 for standard I/Os, and

Figure 39 and Figure 40 for 5 V tolerant I/Os.

80/117

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STM32F101xF, STM32F101xG Electrical characteristics

Figure 37. Standard I/O input characteristics - CMOS port

6)(6),6

6)(6$$

)(MIN

),MAX

#-/3STANDARDREQUIREMENT

6 )(6

#-/3STANDARDREQUIREMENT

6),6$$

6 $$

)NPUTRANGE

NOTGUARANTEED

6$$6

AIB

Figure 38. Standard I/O input characteristics - TTL port

6)(6),6

)(MIN

),MAX

44,REQUIREMENTS 6)(6

6)(6$$

6),6$$

44,REQUIREMENTS 6),6

)NPUTRANGE

NOTGUARANTEED

6$$6

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Electrical characteristics STM32F101xF, STM32F101xG

Figure 39. 5 V tolerant I/O input characteristics - CMOS port

6)(6),6

#-/3STANDARDREQUIREMENTS

6)(6

6)(6$$

6),6$$

#-/3STANDARDREQUIR

MENT6),6$$

)NPUTRANGE

NOTGUARANTEED

Figure 40. 5 V tolerant I/O input characteristics - TTL port

6$$

6$$6

AIB

6)(6),6

)(MIN

),MAX

44,REQUIREMENT6)(6

6)(6$$

6),6$$

)NPUTRANGE

NOTGUARANTEED

44,REQUIREMENTS6),6

6$$6

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source up to ± 20 mA (with a relaxedV

) except PC13, PC14 and PC15 which can sink or source up to ±3 mA. When using the GPIOs PC13 to PC15 in output mode, the speed should not exceed 2 MHz with a maximum load of 30 pF.

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in

Section 5.2

• The sum of the currents sourced by all the I/Os on V

DD,

I consumption of the MCU sourced on V

DD,

VDD

(see

Table 8

). plus the maximum Run cannot exceed the absolute maximum rating

• The sum of the currents sunk by all the I/Os on V

I consumption of the MCU sunk on V

VSS

(see

Table 8

plus the maximum Run

cannot exceed the absolute maximum rating

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STM32F101xF, STM32F101xG Electrical characteristics

Output voltage levels

Unless otherwise specified, the parameters given in Table 48

are derived from tests performed under ambient temperature and V

supply voltage conditions summarized in

Table 10 .

All I/Os are CMOS and TTL compliant.

Symbol

Table 48. Output voltage characteristics

Parameter Conditions Min Max Unit

(1)

(3)

(1)

(3)

(1)

(3)

(1)

(3)

Output Low level voltage for an I/O pin when 8 pins are sunk at the same time

Output High level voltage for an I/O pin when 8 pins are sourced at the same time

Output low level voltage for an I/O pin when 8 pins are sunk at the same time

Output high level voltage for an I/O pin when 8 pins are sourced at the same time

Output low level voltage for an I/O pin when 8 pins are sunk at the same time

Output high level voltage for an I/O pin when 8 pins are sourced at the same time

Output low level voltage for an I/O pin when 8 pins are sunk at the same time

Output high level voltage for an I/O pin when 8 pins are sourced at the same time

CMOS port

(2)

= +8 mA,

2.7 V < V

< 3.6 V

TTL port

(2)

= +8 mA

2.7 V < V

< 3.6 V

= +20 mA

(4)

2.7 V < V

< 3.6 V

= +6 mA

2 V < V

(4)

< 2.7 V

–0.4

2.4

–1.3

–0.4

0.4

1.3

0.4

1. The I

current sunk by the device must always respect the absolute maximum rating specified in

Table 8

and the sum of I

(I/O ports and control pins) must not exceed I

VSS

2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

3. The I

Table 8

current sourced by the device must always respect the absolute maximum rating specified in

and the sum of I

(I/O ports and control pins) must not exceed I

VDD

4. Guaranteed by characterization results.

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Electrical characteristics STM32F101xF, STM32F101xG

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in

Figure 41 and

Table 49 , respectively.

Unless otherwise specified, the parameters given in Table 49

are derived from tests performed under ambient temperature and V

Table 10 .

supply voltage conditions summarized in

Table 49. I/O AC characteristics (1)

MODEx

[1:0] bit value (1)

Symbol Parameter Conditions Max Unit

f f max(IO)out t t f(IO)out r(IO)out max(IO)out t t f(IO)out r(IO)out

Maximum frequency

(2)

Output high to low level fall time

= 50 pF, V

= 2 V to 3.6 V

= 50 pF, V

= 2 V to 3.6 V

Output low to high level rise time

Maximum frequency

(2)

= 50 pF, V

= 2 V to 3.6 V

Output high to low level fall time

Output low to high level rise time

= 50 pF, V

= 2 V to 3.6 V

125

(3)

F max(IO)out t t f(IO)out r(IO)out

Maximum Frequency

(2)

Output high to low level fall time

Output low to high level rise time

= 30 pF, V

= 2.7 V to 3.6 V 50

= 50 pF, V

= 2.7 V to 3.6 V 30

= 50 pF, V

= 2 V to 2.7 V 20

= 30 pF, V

= 2.7 V to 3.6 V 5 (3)

= 50 pF, V

= 2.7 V to 3.6 V 8

(3)

= 50 pF, V

= 2 V to 2.7 V 12

(3)

= 30 pF, V

= 2.7 V to 3.6

(3)

= 50 pF, V

= 2.7 V to 3.6 V 8

(3)

= 50 pF, V

= 2 V to 2.7 V 12 (3) t

EXTIpw

Pulse width of external signals detected by the

EXTI controller

MHz ns

MHz

MHz ns ns

1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a description of GPIO Port configuration register.

2. The maximum frequency is defined in

Figure 41

3. Guaranteed by design.

84/117

DocID16553 Rev 5

STM32F101xF, STM32F101xG Electrical characteristics

Figure 41. I/O AC characteristics definition

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DLG

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, R

(see

Table 47 ).

Unless otherwise specified, the parameters given in Table 50

are derived from tests performed under ambient temperature and V

Table 10 .

supply voltage conditions summarized in

Table 50. NRST pin characteristics

Symbol Parameter Conditions Min Typ Max Unit

IL(NRST)

(1)

IH(NRST)

(1)

NRST Input low level voltage

NRST Input high level voltage -

–0.5

2 -

0.8

+0.5

V hys(NRST)

F(NRST)

(1)

NF(NRST)

(1)

NRST Schmitt trigger voltage hysteresis

Weak pull-up equivalent resistor

(2)

NRST Input filtered pulse

NRST Input not filtered pulse

= V

300

200

100

mV k Ω ns ns

1. Guaranteed by design.

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution the series resistance must be minimum (~10% order)

DocID16553 Rev 5

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Electrical characteristics STM32F101xF, STM32F101xG

Figure 42. Recommended NRST pin protection

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1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the V

Table 50 . Otherwise the reset will not be taken into account by the device.

max level specified in

3. The external capacitor on NRST must be placed as close as possible to the device.

The parameters given in

Table 51 are guaranteed by design.

Refer to Section 5.3.13: I/O current injection characteristics for details on the input/output

alternate function characteristics (output compare, input capture, external clock, PWM output).

Symbol Parameter

Table 51. TIMx (1) characteristics

Conditions Min Max Unit t res(TIM)

Timer resolution time

TIMxCLK

= 36 MHz 27.8

TIMxCLK ns f

EXT

Timer external clock frequency on CH1 to CH4

TIMxCLK

= 36 MHz

0 f

TIMxCLK

/2 MHz

MHz t

Res

TIM

COUNTER

Timer resolution -

16-bit counter clock period when internal clock is selected

TIMxCLK

= 36 MHz 0.0278

65536

1820 t bit

TIMxCLK

µs t

MAX_COUNT

Maximum possible count

65536 × 65536 t

TIMxCLK

= 36 MHz -

1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3 and TIM4 timers.

119.2

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STM32F101xF, STM32F101xG Electrical characteristics

I

C interface characteristics

The STM32F101xF and STM32F101xG access line I 2 the standard I 2

C interface meets the requirements of

C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-drain. When configured as open-drain, the

PMOS connected between the I/O pin and V

DD is disabled, but is still present.

The I 2 C characteristics are described in

Table 52

. Refer also to

Section 5.3.13: I/O current injection characteristics

for more details on the input/output alternate function characteristics

(SDA and SCL).

Symbol

Table 52. I 2 C characteristics

Parameter

Standard mode

(1)(2)

Min Max

Fast mode I

(1)(2)

Unit

Min Max t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t r(SDA) t r(SCL) t f(SDA) t f(SCL) t h(STA)

SCL clock low time

SCL clock high time

SDA setup time

SDA data hold time

SDA and SCL rise time

SDA and SCL fall time t su(STA)

Start condition hold time

Repeated Start condition setup time t su(STO)

Stop condition setup time t w(STO:STA)

Stop to Start condition time (bus free)

C b t

Capacitive load for each bus line

Pulse width of the spikes that are suppressed by the analog filter for standard and fast mode

4.7

4.0

250

4.0

4.7

4.0

4.7

3450

(3)

1000

300

400

(4)

1.3

0.6

100

0.6

900

(3)

300

0.6 -

0.6

1.3

400

(4)

1. Guaranteed by design.

2. f

PCLK1

must be at least 2 MHz to achieve standard mode I

2 achieve the fast mode I

2 mode maximum clock speed of 400 kHz.

C frequencies. It must be at least 4 MHz to

C frequencies and it must be a multiple of 10 MHz in order to reach the I2C fast

3. The maximum data hold time has only to be met if the interface does not stretch the low period of SCL signal.

4. The minimum width of the spikes filtered by the analog filter is above t

(max).

µs ns

µs

µs pF

μ s

DocID16553 Rev 5

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Electrical characteristics STM32F101xF, STM32F101xG

Figure 43. I 2 C bus AC waveforms and measurement circuit (1)

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1. Measurement points are done at CMOS levels: 0.3V

and 0.7V

1. R

= series protection resistor.

2. R

= external pull-up resistor.

3. V

DD_I2C

is the I2C bus power supply.

Table 53. SCL frequency (f

PCLK1

= 36 MHz, V

= V

DD_I2C

= 3.3 V)

(1)(2)

I2C_CCR value f

SCL

(kHz)

= 4.7 k Ω

400

300

200

100

0x801E

0x8028

0x803C

0x00B4

50 0x0168

20 0x0384

1. R

= External pull-up resistance, f

SCL

= I

C speed.

2. For speeds around 200 kHz, the tolerance on the achieved speed is of ± 5%. For other speed ranges, the tolerance on the achieved speed ± 2%. These variations depend on the accuracy of the external components used to design the application.

88/117

DocID16553 Rev 5

STM32F101xF, STM32F101xG Electrical characteristics

SPI interface characteristics

Unless otherwise specified, the parameters given in

Table 54Table 55 are derived from tests

performed under ambient temperature, f

PCLKx summarized in

Table 10 .

frequency and V

supply voltage conditions

Refer to Section 5.3.13: I/O current injection characteristics for more details on the

input/output alternate function characteristics (NSS, SCK, MOSI, MISO).

Symbol

Table 54. STM32F10xxx SPI characteristics

Parameter Conditions Min Max Unit f

SCK

1/t c(SCK)

SPI clock frequency

Master mode 10

MHz

Slave mode 10 t r(SCK) t f(SCK) t su(NSS)

(1) t

t t

SPI clock rise and fall time

NSS setup time

NSS hold time

SCK high and low time

Capacitive load: C = 30 pF

Slave mode

Master mode, f

PCLK presc = 4

= 36 MHz,

PCLK

60 t t t su(MI)

(1) su(SI)

(1)

h(MI)

(1)

Data input setup time

Data input hold time

Master mode - SPI1

Master mode - SPI2

Slave mode

Master mode - SPI1

Master mode - SPI2

t t

h(SI)

(1)

a(SO)

(1)(2)

Data output access time

Slave mode

Slave mode, f presc = 4

PCLK

= 36 MHz,

Slave mode, f

PCLK

= 20 MHz

PCLK t

dis(SO)

(1)(3)

Data output disable time

Slave mode 10 t

v(SO)

(1)

Data output valid time

Slave mode (after enable edge) 25 t v(MO)

(1)

Data output valid time

Master mode (after enable edge) 6 t

Data output hold time

Slave mode (after enable edge)

Master mode (after enable edge)

6 -

1. Guaranteed by characterization results.

2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.

3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z ns

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Electrical characteristics STM32F101xF, STM32F101xG

Symbol Parameter

Table 55. SPI characteristics

Conditions Min Max Unit

1/t f

SCK c(SCK)

SPI clock frequency

Master mode

Slave mode

MHz t r(SCK) t f(SCK)

SPI clock rise and fall time

Capacitive load: C = 30 pF

8 ns

DuCy(SCK)

SPI slave input clock duty cycle

Slave mode 30 70 % t su(NSS)

(1) t

t t

NSS setup time

NSS hold time

SCK high and low time

Slave mode

Master mode, f presc = 4

PCLK

= 36 MHz,

PCLK

60 t t

su(SI)

t h(MI)

t v(SO)

Data input setup time

Data input hold time

Master mode

Slave mode

Master mode

Slave mode

Data output access time Slave mode, f

Data output disable time

Data output valid time

Data output hold time

Slave mode

PCLK

= 20 MHz

Slave mode (after enable edge)

Master mode (after enable edge)

Slave mode (after enable edge)

Master mode (after enable edge)

PCLK

1. Guaranteed by characterization results.

2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.

3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z ns

90/117

DocID16553 Rev 5

STM32F101xF, STM32F101xG Electrical characteristics

Figure 44. SPI timing diagram - slave mode and CPHA=0

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1. Measurement points are done at CMOS levels: 0.3V

and 0.7V

DLE

DocID16553 Rev 5

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Electrical characteristics STM32F101xF, STM32F101xG

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Figure 46. SPI timing diagram - master mode (1)

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Note:

Unless otherwise specified, the parameters given in Table 56 are preliminary values derived

from tests performed under ambient temperature, f

PCLK2 frequency and V

DDA supply voltage conditions summarized in

Table 10 .

It is recommended to perform a calibration after each power-up.

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STM32F101xF, STM32F101xG Electrical characteristics

Symbol Parameter

Table 56. ADC characteristics

Conditions Min Typ Max Unit

DDA

REF+

REF-

VREF

Power supply

Positive reference voltage

Negative reference voltage

Current on the V

REF pin

input

ADC clock frequency

2.4

160

3.6

DDA

220

(1)

µA f

ADC f

(2) Sampling rate -

0.6

0.05

MHz

MHz f

TRIG

(2)

AIN

External trigger frequency

Conversion voltage range

(3) f

ADC

= 14 MHz

0 (V

SSA or V

REFtied to ground)

823

REF+ kHz

1/f

ADC

AIN

(2)

External input impedance

See Equation 1 and

Table 57

for details

50 k Ω

ADC

(2) Sampling switch resistance

ADC

(2)

Internal sample and hold capacitor

8 k Ω pF t t t t

CAL

(2) t t lat

(2) latr

(2)

STAB

(2)

CONV

(2)

Calibration time

Injection trigger conversion latency

Regular trigger conversion latency

Sampling time

Power-up time

Total conversion time

(including sampling time) f

ADC

= 14 MHz

ADC

= 14 MHz

ADC

= 14 MHz

ADC

= 14 MHz

ADC

= 14 MHz

0.107

1.5

5.9

µs

1/f

ADC

µs 0.214

(4)

0.143

(4)

1/f

ADC

µs

1/f

ADC

µs 17.1

239.5

1/f

ADC

1 µs

18 µs

14 to 252 (t

for sampling +12.5 for successive approximation)

1/f

ADC

1. Guaranteed by characterization results.

2. Guaranteed by design.

3. V can be internally connected to V the package. Refer to

DDA

and V

REF-

can be internally connected to V

Section 3: Pinouts and pin descriptions for further details.

SSA

, depending on

4. For external triggers, a delay of 1/f

PCLK2

must be added to the latency specified in Table 56 .

Equation 1: R

AIN

max formula:

AIN

< f

----------------------------------------------------------------

ADC

× C

ADC

× ln ( 2 )

– R

ADC

DocID16553 Rev 5

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Electrical characteristics STM32F101xF, STM32F101xG

The formula above ( Equation 1 ) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).

T s

(cycles)

1.5

7.5

13.5

28.5

41.5

55.5

71.5

239.5

1. Guaranteed by design.

Table 57. R

AIN

max for f

ADC

= 14 MHz (1) t

(µs)

2.96

3.96

5.11

17.1

0.11

0.54

0.96

2.04

37.2

0.4

5.9

11.4

25.2

AIN

max (k Ω )

Symbol

Table 58. ADC accuracy - limited test conditions

(1)(2)

Parameter Test conditions Typ Max

(3)

Unit

Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error f

PCLK2

= 28 MHz, f

ADC

= 14 MHz, R

AIN

< 10 k Ω ,

DDA

°C

= 3 V to 3.6 V, T

= 25

Measurements made after

ADC calibration

REF+

= V

DDA

±1.3

±1

±0.5

±0.7

±0.8

±2

±1.5

±1

±1.5

LSB

1. ADC DC accuracy values are measured after internal calibration.

2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current.

Any positive injection current within the limits specified for I affect the ADC accuracy.

INJ(PIN)

and Σ I

INJ(PIN)

in Section 5.3.13

does not

3. Guaranteed by characterization results.

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DocID16553 Rev 5

STM32F101xF, STM32F101xG Electrical characteristics

Symbol Parameter

Table 59. ADC accuracy (1) (2)(3)

Test conditions Typ Max

(4)

Unit

Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error f

PCLK2 f

ADC

= 28 MHz,

= 14 MHz, R

AIN

DDA

= 2.4 V to 3.6 V

Measurements made after

ADC calibration

< 10 k Ω ,

±2

±1.5

±1

±1.5

±5

±2.5

±3

±2

±3

LSB

1. ADC DC accuracy values are measured after internal calibration.

2. Better performance could be achieved in restricted V

, frequency, V

REF

and temperature ranges.

3. ADC accuracy vs. negative injection current: Injecting negative current on any of the standard (non-robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current.

Any positive injection current within the limits specified for I affect the ADC accuracy.

INJ(PIN)

and Σ I

INJ(PIN)

in Section 5.3.13

does not

4. Preliminary values.

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DocID16553 Rev 5

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Electrical characteristics STM32F101xF, STM32F101xG

Figure 48. Typical connection diagram using the ADC

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1. Refer to Table 56 for the values of R

AIN

, R

ADC

and C

ADC

2. C parasitic this, f

represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

ADC

should be reduced.

parasitic

value will downgrade conversion accuracy. To remedy

General PCB design guidelines

Power supply decoupling should be performed as shown in

Figure 49

Figure 50

, depending on whether V

REF+

is connected to V

DDA

or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip.

Figure 49. Power supply and reference decoupling (V

REF+ not connected to V

DDA

)

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1. V

REF+

and V

REF-

inputs are available only on 100-pin packages.

DLF

96/117

DocID16553 Rev 5

STM32F101xF, STM32F101xG Electrical characteristics

Figure 50. Power supply and reference decoupling (V

REF+ connected to V

DDA

)

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1. V

REF+

and V

REF-

inputs are available only on 100-pin packages.

Symbol

DDA

REF+

SSA

Parameter

Analog supply voltage

Reference supply voltage

Ground

Table 60. DAC characteristics

Conditions Min Typ Max

2.4

LOAD

(2)

Resistive load with buffer ON

DAC output buffer ON

LOAD connected to V

SSA

LOAD connected to V

DDA

25 -

(1) Unit

3.6 V -

3.6

Comments

V -

REF+

must always be below

DDA k Ω

(2)

Impedance output with buffer OFF

LOAD

(2)

Capacitive load -

50 k Ω pF

When the buffer is OFF, the minimum resistive load between DAC_OUT and V

SS to have a 1% accuracy is

1.5 M Ω

Maximum capacitive load at

DAC_OUT pin (when the buffer is ON).

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Electrical characteristics STM32F101xF, STM32F101xG

Symbol Parameter

DAC_OUT min

(2)

Lower DAC_OUT voltage with buffer

DAC_OUT max

(2)

Higher DAC_OUT voltage with buffer

DAC_OUT min

(2)

Lower DAC_OUT voltage with buffer

OFF

DAC_OUT max

(2)

Higher DAC_OUT voltage with buffer

OFF

DDVREF+

DAC DC current consumption in quiescent mode

(Standby mode)

Table 60. DAC characteristics (continued)

Conditions Min Typ Max (1) Unit

0.2 -

Comments

DDA

0.2

–

It gives the maximum output excursion of the DAC.

It corresponds to 12-bit input code (0x0E0) to (0xF1C) at

REF+

= 3.6 V and (0x155) and (0xEAB) at V

REF+

= 2.4 V.

0.5

REF+

1LSB

–

It gives the maximum output excursion of the DAC.

DDA

Gain error

DAC DC current consumption in quiescent mode

(3)

Differential non linearity Difference between two consecutive code-

1LSB)

Integral non linearity

(difference between measured value at

Code i and the value at Code i on a line drawn between Code

0 and last Code

1023)

Offset error

(difference between measured value at

Code (0x800) and the ideal value =

REF+

/2)

Gain error

220

380

480

µA

With no load, worst code

(0xF1C) at V

REF+

= 3.6 V in terms of DC consumption on the inputs.

With no load, middle code

(0x800) on the inputs.

With no load, worst code

(0xF1C) at V

REF+

= 3.6 V in terms of DC consumption on the inputs.

±0.5 LSB

Given for the DAC in 10-bit configuration.

±2

±1

LSB

Given for the DAC in 12-bit configuration.

LSB

Given for the DAC in 10-bit configuration.

±4 LSB

Given for the DAC in 12-bit configuration.

±10 mV -

±3 LSB

Given for the DAC in 10-bit at

REF+

= 3.6 V.

±12 LSB

Given for the DAC in 12-bit at

REF+

= 3.6 V.

±0.5

Given for the DAC in 12bit configuration.

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DocID16553 Rev 5

STM32F101xF, STM32F101xG Electrical characteristics

Symbol Parameter

Table 60. DAC characteristics (continued)

Conditions Min Typ Max (1) Unit Comments t

SETTLING

Update rate

(1)

Settling time (full scale: for a 10-bit input code transition between the lowest and the highest input codes when

DAC_OUT reaches final value ±1LSB

Max frequency for a correct DAC_OUT change when small variation in the input code (from code i to i+1LSB)

µs C

MS/s C

LOAD

≤

LOAD

≤

50 pF, R

LOAD

50 pF, R

LOAD

≥ 5 k Ω

≥ 5 k Ω t

WAKEUP

(1)

Wakeup time from off state (Setting the

ENx bit in the DAC

Control register)

PSRR+

(2)

Power supply rejection ratio (to

DDA

) (static DC measurement

6.5

–67 –40

µs

LOAD

≤

LOAD

≥ 5 k Ω input code between lowest and highest possible ones.

LOAD

, C

LOAD

= 50 pF

1. Preliminary values.

2. Guaranteed by design.

3. Quiescent mode refers to the state of the DAC when a steady value is kept on the output so that no dynamic consumption is involved.

Figure 51. 12-bit buffered /non-buffered DAC

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1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register.

DocID16553 Rev 5

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Electrical characteristics STM32F101xF, STM32F101xG

5.3.20 Temperature sensor characteristics

Symbol

(1)

Avg_Slope

(1)

START

(2)

(1)

S_temp

(3)(2)

Table 61. TS characteristics

Parameter

SENSE

linearity with temperature

Average slope

Voltage at 25°C

Startup time

ADC sampling time when reading the temperature

Min

4.0

1.34

Typ

4.3

1.43

1. Preliminary values.

2. Guaranteed by design.

3. Shortest sampling time can be determined in the application by multiple iterations.

Max

4.6

1.52

17.1

Unit

°C mV/°C

µs

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STM32F101xF, STM32F101xG Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com

ECOPACK ® is an ST trademark.

Figure 52. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline

3%!4).'

0,!.%

CCC #

'!5'%0,!.%

, +

0).

)$%.4)&)#!4)/.

1. Drawing is not to scale.

DocID16553 Rev 5

!?-%?6

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Package information STM32F101xF, STM32F101xG

Table 62. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data millimeters inches

(1)

Symbol

Min Typ Max c

A2 b

L1 k ccc

E3 e

0.050

1.350

0.170

0.090

21.800

19.800

21.800

19.800

0.450

0°

0.600

1.000

3.5°

1.400

0.220

22.000

20.000

17.500

22.000

20.000

17.500

0.500

1. Values in inches are converted from mm and rounded to 4 decimal digits.

1.600

0.150

1.450

0.270

0.200

22.200

20.200

22.200

20.200

0.750

7°

0.080

Min

0.0020

0.0531

0.0067

0.0035

0.8583

0.7795

0.8583

0.7795

0.0177

0°

Typ

0.0551

0.0087

0.8661

0.7874

0.689

0.8661

0.7874

0.689

0.0197

0.0236

0.0394

3.5°

Max

0.0630

0.0059

0.0571

0.0106

0.0079

0.874

0.7953

0.874

0.7953

0.0295

7°

0.0031

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STM32F101xF, STM32F101xG Package information

Figure 53. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package footprint

1. Dimensions are expressed in millimeters.

DLH

DocID16553 Rev 5

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Package information STM32F101xF, STM32F101xG

Device marking for LQFP144

The following figure gives an example of topside marking versus pin 1 position identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 54. LQFP144 marking (package top view)

3URGXFWLGHQWLILFDWLRQ

5HYLVLRQFRGH

670)=)7

3LQ

LGHQWLILHU

'DWHFRGH

< ::

06Y9

1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity.

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STM32F101xF, STM32F101xG

6.2 LQFP100 package information

Package information

Figure 55. LQFP100 – 14 x 14 mm, 100-pin low-profile quad flat package outline

3%!4).'0,!.%

'!5'%0,!.%

CCC #

, +

0).

)$%.4)&)#!4)/.

A2 b c

Symbol

1. Drawing is not to scale.

Table 63. LQPF100 – 14 x 14 mm, 100-pin low-profile quad flat package mechanical data millimeters inches

(1)

Min

0.050

1.350

0.170

0.090

15.800

13.800

15.800

13.800

Typ

1.400

0.220

16.000

14.000

12.000

16.000

14.000

Max

1.600

0.150

1.450

0.270

0.200

16.200

14.200

16.200

14.200

Min

0.0020

0.0531

0.0067

0.0035

0.622

0.5433

0.622

0.5433

Typ

0.0551

0.0087

0.6299

0.5512

0.4724

0.6299

0.5512

,?-%?6

Max

0.0630

0.0059

0.0571

0.0106

0.0079

0.6378

0.5591

0.6378

0.5591

DocID16553 Rev 5

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Package information STM32F101xF, STM32F101xG

Table 63. LQPF100 – 14 x 14 mm, 100-pin low-profile quad flat package mechanical data (continued) millimeters inches

(1)

Symbol

Min Typ Max

E3 e

L1 k ccc

0.450

0°

12.000

0.500

0.600

1.000

3.5°

0.750

7°

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Min

0.0177

0°

Typ

0.4724

0.0197

0.0236

0.0394

3.5°

Figure 56. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint

Max

0.0295

7°

0.0031

1. Dimensions are in millimeters.

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DocID16553 Rev 5

AIC

STM32F101xF, STM32F101xG Package information

Device marking for LQFP100

The following figure gives an example of topside marking versus pin 1 position identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 57. LQFP100 marking (package top view)

3URGXFWLGHQWLILFDWLRQ

670)

9*75

'DWHFRGH

< ::

5HYLVLRQFRGH

3LQ

LQGHQWLILHU

06Y9

DocID16553 Rev 5

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Package information STM32F101xF, STM32F101xG

Figure 58. LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package outline

6($7,1*3/$1(

*$8*(3/$1(

FFF &

' /

3,1

,'(17,),&$7,21

:B0(B9

1. Drawing is not to scale.

Table 64. LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package mechanical data inches

(1)

Symbol millimeters

Min Typ Max Min Typ Max c

A2 b

0.050

1.350

0.170

1.400

0.220

0.090

- 12.000

10.000

7.500

12.000

10.000

7.500

1.600

0.150

1.450

0.270

0.200

0.0020

0.0531

0.0067

0.0035

0.0551

0.0087

0.4724

0.3937

0.2953

0.4724

0.3937

0.2953

0.0630

0.0059

0.0571

0.0106

0.0079

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STM32F101xF, STM32F101xG Package information

Table 64. LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package mechanical data (continued) millimeters inches (1)

Symbol

Min Typ Max Min Typ Max e

L1 ccc

0°

0.450

0.500

3.5°

0.600

1.000

7°

0.750

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0°

0.0177

0.0197

3.5°

0.0236

0.0394

7°

0.0295

0.0031

Figure 59. LQFP64 - 10 x 10 mm low-profile quad flat recommended footprint

1. Dimensions are in millimeters.

AIC

DocID16553 Rev 5

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Package information STM32F101xF, STM32F101xG

Device marking for LQFP64

The following figure gives an example of topside marking versus pin 1 position identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 60. LQFP64 marking (package top view)

3URGXFWLGHQWLILFDWLRQ

5HYLVLRQFRGH

670)

5)7

'DWHFRGH

< ::

3LQ

LQGHQWLILHU

06Y9

110/117

DocID16553 Rev 5

STM32F101xF, STM32F101xG Package information

The maximum chip junction temperature (T

J max) must never exceed the values given in

Table 10: General operating conditions on page 39 .

The maximum chip-junction temperature, T

J using the following equation:

max, in degrees Celsius, may be calculated

max = T

max + (P

max × Θ

)

Where:

• T

max is the maximum ambient temperature in °C,

• Θ

is the package junction-to-ambient thermal resistance, in °C/W,

• P

max is the sum of P

INT

max and P

I/O max (P

max = P

INT

max + P

I/O max),

• P

INT

max is the product of I

DD and internal power.

, expressed in Watts. This is the maximum chip

I/O

max represents the maximum power dissipation on output pins where:

I/O

max = Σ (V

× I

) + Σ ((V

– V

) × I

), taking into account the actual V

OL application.

/ I

and V

/ I

OH of the I/Os at low and high level in the

Symbol

Table 65. Package thermal characteristics

Parameter

Thermal resistance junction-ambient

LQFP144 - 20 x 20 mm / 0.5 mm pitch

Thermal resistance junction-ambient

LQFP100 - 14 x 14 mm / 0.5 mm pitch

Thermal resistance junction-ambient

LQFP64 - 10 x 10 mm / 0.5 mm pitch

Value

Unit

°C/W

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural

Convection (Still Air), available from www.jedec.org.

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Package information

6.4.2

STM32F101xF, STM32F101xG

Evaluating the maximum junction temperature for an application

When ordering the microcontroller, the temperature range is specified in the ordering

information scheme shown in Table 66: STM32F101xF and STM32F101xG ordering information scheme .

Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. Here, only temperature range 6 is available (–40 to 85 °C).

The following example shows how to calculate the temperature range needed for a given application, making it possible to check whether the required temperature range is compatible with the STM32F10xxx junction temperature range.

Example: High-performance application

Assuming the following application conditions:

Maximum ambient temperature T

Amax

DDmax

= 50 mA, V

= 82 °C (measured according to JESD51-2),

= 3.5 V, maximum 20 I/Os used at the same time in output at low level with I

= 8 mA, V

= 0.4 V and maximum 8 I/Os used at the same time in output mode at low level with I

= 20 mA, V

= 1.3 V

INTmax

= 50 mA × 3.5 V= 175 mW

IOmax

= 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW

This gives: P

INTmax

= 175 mW and P

IOmax

= 272 mW

Dmax

= 175 + 272 = 447 mW

Thus: P

Dmax

= 447 mW

Using the values obtained in Table 66

Jmax

is calculated as follows:

– For LQFP64, 45 °C/W

Jmax

= 82 °C + (45 °C/W × 447 mW) = 82 °C + 20.1 °C = 102.1 °C

This is within the junction temperature range of the STM32F10xxx (–40 < T

< 105 °C).

Figure 61. LQFP64 P

max vs. T

700

600

500

400

300

200

100

65 75 85 95

(°C)

105 115

Suffix 6

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DocID16553 Rev 5

STM32F101xF, STM32F101xG Part numbering

Example:

Table 66. STM32F101xF and STM32F101xG ordering information scheme

STM32F 101 R F T 6 xxx

Device family

STM32 = ARM

-based 32-bit microcontroller

Product type

F = general-purpose

Device subfamily

101 = access line

Pin count

R = 64 pins

V = 100 pins

Z = 144 pins

Flash memory size

F = 768 Kbytes of Flash memory

G = 1 Mbyte of Flash memory

Package

T = LQFP

Temperature range

6 = Industrial temperature range, –40 to 85 °C.

Options xxx = programmed parts

TR = tape and real

For a list of available options (speed, package, etc..) or for further information on any aspect of this device, please contact your nearest ST sales office.

DocID16553 Rev 5

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Revision history STM32F101xF, STM32F101xG

Date

27-Oct-2009

15-Nov-2010

Revision

Table 67. Document revision history

Changes

Initial release.

LQFP64 package mechanical data updated: see

Figure 58: LQFP64 –

10 x 10 mm, 64 pin low-profile quad flat package outline and Table 64:

LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package mechanical data .

Internal code removed from Table 66: STM32F101xF and

STM32F101xG ordering information scheme .

Updated note 2 below

Table 52: I

C characteristics

Updated

Figure 43: I

C bus AC waveforms and measurement circuit

(1)

Updated

Figure 42: Recommended NRST pin protection

Updated note 1 below

Table 47: I/O static characteristics

Updated

Table 20: Peripheral current consumption

Updated

Table 14: Maximum current consumption in Run mode, code with data processing running from Flash

Updated

Table 15: Maximum current consumption in Run mode, code with data processing running from RAM

Updated Table 16: Maximum current consumption in Sleep mode, code running from Flash or RAM

Updated Table 17: Typical and maximum current consumptions in Stop and Standby modes

Updated Table 18: Typical current consumption in Run mode, code with data processing running from Flash

Updated

Table 19: Typical current consumption in Sleep mode, code running from Flash or RAM

Updated

Table 24: LSE oscillator characteristics (f

LSE

= 32.768 kHz)

Updated

Figure 19: Asynchronous non-multiplexed

SRAM/PSRAM/NOR read waveforms on page 58

Added Section 5.3.13: I/O current injection characteristics on page 99.

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STM32F101xF, STM32F101xG Revision history

Date

25-Nov-2014

Table 67. Document revision history (continued)

Revision Changes

Updated number of ADCs in Table 2: STM32F101xF and

STM32F101xG features and peripheral counts .

Modified Section 2.3.22: GPIOs (general-purpose inputs/outputs) on page 21

Added note below Figure 3: LQFP144 pinout ,

Figure 4: LQFP100 pinout

, and Figure 5: LQFP64 pinout .

Modified OSC_IN, OSC_OUT, PD0, PD1, PB8, PB9 and PF8 in

Table 5: STM32F101xF/STM32F101xG pin definitions on page 25

Updated notes related to parameters not tested in production in the whole document.

Modified notes in Table 7: Voltage characteristics on page 37 and

Table 8: Current characteristics on page 38 .

Removed ADC2/3 and CAN from Table 20: Peripheral current consumption on page 48

Modified t w(HSE)

value in Table 21: High-speed external user clock characteristics on page 50 .

Updated Table 24: LSE oscillator characteristics (f

LSE page 53

= 32.768 kHz) on

Changed JESD22-C101 to ANSI/ESD STM5.3.1 in Section :

Electrostatic discharge (ESD) .

Updated

Section 5.3.10: FSMC characteristics on page 57

Updated

Figure 41: I/O AC characteristics definition . Updated

conditions related to Section : I

C interface characteristics on page 87

Modified Table 52: I

C bus AC waveforms and measurement circuit conditions in

2 C characteristics on page 87

, updated Figure 43:

Table 53: SCL frequency (f

= 3.3 V) on page 88

PCLK1

(1)

and V

= 36 MHz, V

DD_I2C

= V

DD_I2C

Modified Section : Output driving current on page 82

Modified Table 52: I

Figure 43: I

C characteristics on page 87 and updated

C bus AC waveforms and measurement circuit

(1)

Modified Figure 46: SPI timing diagram - master mode

(1)

on page 92 .

Modified notes in Table 56: ADC characteristics on page 93

and

Table 59: ADC accuracy on page 95 .

Updated I

DDA

definition in

Table 60: DAC characteristics on page 97

and removed comment related to the offset parameter for ±10 mV.

Added Device marking information for all packages.

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Revision history STM32F101xF, STM32F101xG

Date

18-May-2015

13-Dec-2016

Table 67. Document revision history (continued)

Revision Changes

Modified Cortex-M3 technical reference manual url in

Section 1:

Introduction

Updated

Table 20: Peripheral current consumption

Restored CDM standard and class in Table 44: ESD absolute maximum ratings

Updated ccc dimension in

Table 62: LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data and

Section : Device marking for LQFP144 .

Updated Section : Device marking for LQFP100 .

Updated

Table 64: LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package mechanical data

and Section : Device marking for LQFP64 .

Updated:

–

Table 5: STM32F101xF/STM32F101xG pin definitions

– |V

SSX

- V

| in Table 7: Voltage characteristics to add V

– R

LOAD

Table 60: DAC characteristics

–

Figure 42: Recommended NRST pin protection

REF-

–

Section 6: Package information

Added:

– V

REF- in

Table 56: ADC characteristics

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STM32F101xF, STM32F101xG

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on

ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

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