The ST2149B is a 4-bit dual supply level translator which provides the level shifting capability to allow data transfer in a multi-voltage system. Externally applied voltages, V

CC and V

, set the logic levels on either side of the device. Its architecture allows bi-directional level translation without a control pin.

The ST2149B accepts V

from 1.65 to 3.6 V and V

from V

to 5.5 V, making it ideal for data transfer between low-voltage ASICs/PLD and higher voltage systems. This device has a tri-state output mode which can be used to disable all I/Os.

Doc ID 023310 Rev 1 5/23

Pin settings ST2149B

Figure 1.

Pin connection (top through view)

)/6,

'.$

6##

) /6##

)/6##

) /

6##

Table 2.

Pin description

Pin number

Symbol

I/O

VCC4

I/O

VCC3

I/O

VCC2

I/O

VCC1

I/O

VL1

I/O

VL2

I/O

VL3

I/O

VL4

GND

!-6

Name and function

Supply voltage

Data input/output

Ground

Data input/output

Supply voltage

Output enable

6/23 Doc ID 023310 Rev 1

ST2149B

Figure 2.

Logic block diagram

Logic diagram

Device block diagrams

Figure 3.

ST2149BQTR block diagram

6##

)/6,

)/6##

ONESHOTCIRCUITBLOCK

ST2149

When OE is LOW, all I/Os are in high-impedance mode.

ST2149BQTR has 4 channels. For simplicity, the above diagram shows only 1 channel.

!-6

Doc ID 023310 Rev 1 7/23

Logic diagram

Figure 4.

Application block diagram

SYSTEM

CONTROLLER

)/6,

6##

)/6##

6##

SYSTEM

CONTROLLER

ST2149B

6##

!-6

8/23 Doc ID 023310 Rev 1

ST2149B Supplementary notes

For proper operation, the driver from each side of the device must be able to source and sink a minimum of 1 mA current. The device architecture requires the driver to source/sink maximum current of (V

/4) mA to/from the weak 4 k Ω output buffer.

To support the architecture that allows level translation without the direction pin, the one-shot transistor is turned ON only during state transition at the output side. After the one-shot transistor is turned OFF, only the 4 k Ω resistor maintains the output logic state.

So, a resistive load or pull-up resistor less than 50 k Ω is not recommended for proper operation.

Table 3.

Truth table

Enable

(1)

High level V

power supply referred.

High level V

power supply referred.

Z = high impedance.

I/O

VCC

(2)

(3)

Bi-directional input/output

I/O

(1)

(3)

Doc ID 023310 Rev 1 9/23

Maximum ratings ST2149B

Stressing the device above the ratings listed in

Table 4 may cause permanent damage to the

device. These are stress ratings only and operation of the device at these or any other

conditions above those indicated in Recommended operating conditions

of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Table 4.

Symbol

I/OVL

I/OVCC

I/OVL

I/OVCC

SCTOUT

STG

ESD

Absolute maximum ratings

Parameter

Supply voltage

DC control input voltage

DC I/O

input voltage (OE = GND or V

)

DC I/O

VCC

input voltage (OE = GND or V

)

DC input diode current

DC output current

Short-circuit duration, continuous

Power dissipation

Storage temperature

Lead temperature (10 seconds)

Electrostatic discharge protection (HBM)

Value

-0.3 to 4.6

-0.3 to 6.5

-0.3 to V

+ 0.3

-0.3 to V

+ 0.3

-20

±25

500

-65 to 150

300

±2

Unit

V mA mA mA mA mW

° C

° C kV

Recommended operating conditions

Table 5.

Symbol

Recommended operating conditions

Parameter

Supply voltage

Input voltage (OE output enable pin, V

power supply referred)

I/OVL

I/OVCC

I/O

voltage

VCC

voltage

Operating temperature dt/dV Input rise and fall time

Min.

1.65

-40

Typ.

–

Max.

3.6

5.5

3.6

Unit

° C ns/V

10/23 Doc ID 023310 Rev 1

ST2149B Electrical characteristics

Over recommended operating conditions unless otherwise noted. All typical values are at

= 25 °C.

Table 6.

DC characteristics

Value

Symbol Parameter V

Test conditions

= 25 ° C

Min.

Typ.

Max.

-40 to 85 ° C Unit

Min.

Max.

IHL

ILL

IHC

ILC

IH-OE

IL-OE

OHL

OLL

OHC

OLC

High-level input voltage

(I/O

)

Low-level input voltage

(I/O

)

1.65 to 3.6 V

L to 5.5

1.65 to 3.6 V

L to 5.5

High-level input voltage

(I/O

VCC

)

Low-level input voltage

(I/O

VCC

)

1.65 to 3.6 V

to 5.5

1.65 to 3.6 V

to 5.5

High-level input voltage

(OE)

1.65 to 3.6 V

L to 5.5

Low-level input voltage

(OE)

1.65 to 3.6 V

to 5.5

0.8 V

–

0.8 V

–

0.8 V

–

High-level output voltage

(I/O

)

Low-level output voltage

(I/O

)

High-level output voltage

(I/O

VCC

)

1.65 to 3.6 V

to 5.5

IO = -60 µA V

to 5.5

IO = +60 µA

to 5.5

IO = -60 µA V

Low-level output voltage

(I/O

VCC

)

Control input leakage current (OE)

1.65 to 3.6 V

to 5.5

1.65 to 3.6 V

to 5.5

IO = +60 µA

= GND or

- 0.4

–

- 0.4

–

0.2 V

–

0.2 V

–

0.2 V

–

0.4

–

0.4

0.1

0.8 V

–

0.8 V

–

- 0.4

0.4

–

0.2 V

–

0.2 V

–

0.2 V

–

0.4

–

0.4

µA

Doc ID 023310 Rev 1 11/23

Electrical characteristics ST2149B

Table 6.

DC characteristics (continued)

Symbol Parameter V

Test conditions

Value

= 25 ° C

Min.

Typ.

Max.

-40 to 85 ° C

Min.

Max.

Unit

IO_LKG

High impedance leakage current

(I/O

I/O

VCC

)

QVCC

Quiescent supply current V

1.65 to 3.6 V

to 5.5

OE = GND

I/O

= high

I/O

VCC

= low

OE = GND

I/O

= low

I/O

VCC

= high

1.65 to 3.6 V

to 5.5

OE = V

QVL

Quiescent supply current V

1.65 to 3.6 V

to 5.5

OE = V

Z-VCC

Z-VL

High impedance quiescent supply current V

1.65 to 3.6 V

to 5.5

OE = GND

I/O = Hi-Z

1.65 to 3.6 V

to 5.5

OE = GND

I/O = Hi-Z

–

–-

–

0.1

–

µA

12/23 Doc ID 023310 Rev 1

ST2149B Electrical characteristics

AC characteristics

Load C

= 15 pF; driver t r

= t f

≤ 6 ns over temperature range -40 °C to 85 °C.

Table 7.

Symbol

AC characteristics - test conditions: V

= 1.65 - 1.95 V

= V

-1.95 V V

= 2.3-2.7 V V

= 3.0-3.6 V V

= 4.5-5.5 V

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit t t t t

RVcc

FVcc

RVL

FVL

Rise time I/O

Vcc

Fall time I/O

Vcc

Rise time I/O

Fall time I/O

Propagation delay time t

I/OVL-Vcc

I/O

VL-LH

to I/O

Vcc-LH t

PLH

I/O

VL-HL

to I/O

Vcc-HL t

PHL

Propagation delay time

5.2

3.2

3.3

1.5

7.6

4.6

3.2

1.5

3.3

1.4

5.8

3.9

2.4

1.3

3.3

1.4

5.0

3.9

1.8

1.2

3.3

1.3

4.4

3.5

ns ns ns ns ns ns t

I/OVcc-VL

I/O

Vcc-LH

to I/O

VL-LH t

PLH

I/O

Vcc-HL

to I/O

VL-HL t

PHL

7.1

5.3

6.6

5.1

4.8

4.3

4.6

4.1

ns ns t

PZL t

PZH t

PLZ t

PHZ

Output enable time t

Output disable time t

PZH

PLZ

Output disable time t

PHZ

Data rate

(1)

PZL

120

ns ns ns ns

Mbps

Data rate is guaranteed based on the condition that output I/O signal rise/fall time is less than 15% of period of input I/O signal; input I/O signal is at 50% duty cycle and output I/O signal duty cycle deviation is less than 50% ± 10%.

Doc ID 023310 Rev 1 13/23

Electrical characteristics ST2149B

Table 8.

Symbol

AC characteristics - test conditions: V

= 2.3 - 2.7 V

Parameter

= V

-2.7 V

Min.

Max.

= 3.0-3.6 V

Min.

Max.

= 4.5-5.5 V

Unit

Min.

Max.

RVcc t

FVcc t t

RVL

FVL

Rise time I/O

Vcc

Fall time I/O

Vcc

Rise time I/O

Fall time I/O

Propagation delay time t

I/OVL-Vcc

I/O

VL-LH

to I/O

Vcc-LH

I/O

VL-HL

to I/O

Vcc-HL

Propagation delay time t t

PLH

PHL

3.3

1.7

2.2

1.3

4.8

3.7

2.2

1.6

2.2

1.2

4.3

3.3

1.7

1.4

1.9

1.2

3.9

2.9

ns ns ns ns ns ns t

I/OVcc-VL

I/O

Vcc-LH

to I/O

VL-LH t t t t

PZL

PZH

PLZ

PHZ

I/O

Vcc-HL

to I/O

VL-HL

Output enable time t

PZL

Output enable time t

PZH

Output disable time t

PLZ

Output disable time t

PHZ

Data rate

(1) t t

PLH

PHL

3.9

3.6

100

136

3.5

100

158

3.5

3.4

ns ns ns ns ns ns

Mbps

14/23 Doc ID 023310 Rev 1

ST2149B Electrical characteristics

Table 9.

Symbol

AC characteristics - test conditions: V

= 3.0 - 3.6 V

= V

-3.6 V

Parameter

Min.

Max.

= 4.5-5.5 V

Unit

Min.

Max.

t t t

FVcc t

RVcc t

RVL

FVL

I/OVL-Vcc

Rise time I/O

Vcc

Fall time I/O

Vcc

Rise time I/O

Fall time I/O

Propagation delay time

I/O

VL-LH

to I/O

Vcc-LH

I/O

VL-HL

to I/O

Vcc-HL

Propagation delay time t t

PLH

PHL

2.1

1.3

1.6

1.1

4.1

2.9

1.7

1.3

1.5

1.1

4.1

2.6

ns ns ns ns ns ns t

I/OVcc-VL t

PZL t

PZH t

PLZ t

PHZ

I/O

Vcc-LH

to I/O

VL-LH

I/O

Vcc-HL

to I/O

VL-HL

Output enable time t

Output disable time t

Data rate

(1)

PZL

PZH

PLZ

PHZ t t

PLH

PHL

144

4.0

2.6

186

4.0

2.5

ns ns ns ns ns ns

Mbps

Doc ID 023310 Rev 1 15/23

Test circuit

Figure 5.

Test circuit

P u l s e gener a tor

ST2149B

VL VCC

D.U.T

C L

V L

VCC

OPEN

GND

AM040 8 0V1

Table 10.

Test circuit switches

Test C

15 pF t

PLH, t

PHL t r

, t f t

PZL, t

PLZ t

PZH, t

PHZ

15 pF

20 k

Switch

Open

L or V

GND

Table 11.

Waveform symbol value

Symbol

Driving I/O

1.65 V

≤

2.5 V

3.3 V

≤

5.5 V

≤

50% V

Driving I/O

VCC

1.65 V

≤

2.5 V

3.3 V

≤

5.5 V

≤

50% V

16/23 Doc ID 023310 Rev 1

ST2149B

Figure 6.

Waveform - propagation delay (f = 1 MHz, 50% duty cycle)

Test circuit

Figure 7.

Waveform - output enable and disable time (f = 1 MHz, 50% duty cycle)

Doc ID 023310 Rev 1 17/23

Package mechanical data ST2149B

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK

packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com

. ECOPACK is an ST trademark.

Figure 8.

Package outline for QFN12 (1.7 x 2.0 mm) - 0.40 mm pitch

).$%8!2%!

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CCC #

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AAA # X

4/06)%7

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$ X%

3%!4 ).'

0,!.%

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Doc ID 023310 Rev 1

ST2149B Package mechanical data

Table 12.

Mechanical data for QFN12 (1.7 x 2.0 mm) - 0.40 mm pitch

Dimensions

Symbol mm.

Min.

Nom.

Max.

ccc ddd eee

E e

A1 b

L aaa bbb

Notes

LF part No.

LF DWG. No.

0.45

0.00

0.15

0.50

0.02

0.20

1.70 BSC

2.00 BSC

0.40 BSC

0.35 0.45

0.05

0.07

0.10

0.05

0.08

(1)

(2)

B-2888

0.55

0.05

0.25

0.55

Dimensioning and tolerance conform to ASME Y14.5M-1994.

All dimensions are in millimeters.

N is the total number of terminals.

4. The location of the terminal #1 identifier and terminal numbering convention conforms to JEDEC publication 95 SPP-002.

5. ND and NE refer to the number of terminals on the D and E side respectively.

Dimension b applies to the metallized terminal. If the terminal has the optional radius on the other end of the terminal, dimension b should not be measured in that radius area.

7. Coplanarity applies to the terminals and all other bottom surface metallization.

8. NJ in the variation code refers to a package which is not currently JEDEC registered.

Doc ID 023310 Rev 1 19/23

Package mechanical data

Figure 9.

Carrier tape for QFN12 (1.7 x 2.0 mm) - 0.40 mm pitch

MAX

MIN

TYP

0 !

3ECTION99

Measured from centerline of sprocket hole to centerline of pocket.

Cumulative tolerance of sprocket holes is ± 0.20.

Measured from centerline of sprocket hole to centerline of pocket.

Other material available.

All dimensions are in millimeters unless otherwise stated.

Table 13.

Carrier tape dimensions

Symbol Dimensions

1.80 ± 0.05

2.25 ± 0.05

0.60 ± 0.05

3.50 ± 0.05

4.00 ± 0.1

1.00 min.

0.25 ± 0.03

0.75 min.

6.25 min.

8.00 + 0.3 / -0.1

ST2149B

20/23 Doc ID 023310 Rev 1

ST2149B Package mechanical data

Figure 10.

Reel information for QFN12 (1.7 x 2.0 mm) - 0.40 mm pitch

EINT

E 2 2

Table 14.

Reel dimensions mm

Reel 7

″

180

Doc ID 023310 Rev 1 21/23

Revision history

Table 15.

Document revision history

Date Revision

19-Jun-2012 1 Initial release.

Changes

ST2149B

22/23 Doc ID 023310 Rev 1

ST2149B

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Doc ID 023310 Rev 1 23/23

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