STMicroelectronics STM32L083CB Datasheet
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STM32L083x8 STM32L083xB
STM32L083xZ
Ultra-low-power 32-bit MCU Arm
®
-based Cortex
®
-M0+, up to 192KB
Flash, 20KB SRAM, 6KB EEPROM, LCD, USB, ADC, DACs, AES
Datasheet
-
production data
Features
• Ultra-low-power platform
– 1.65 V to 3.6 V power supply
– 40 to 125 °C temperature range
– 0.29 µA Standby mode (3 wakeup pins)
– 0.43 µA Stop mode (16 wakeup lines)
– 0.86 µA Stop mode + RTC + 20-Kbyte RAM retention
– Down to 93 µA/MHz in Run mode
– 5 µs wakeup time (from Flash memory)
– 41 µA 12-bit ADC conversion at 10 ksps
• Core: Arm ® 32-bit Cortex ® -M0+ with MPU
– From 32 kHz up to 32 MHz max.
– 0.95 DMIPS/MHz
• Memories
– Up to 192-Kbyte Flash memory with ECC (2 banks with read-while-write capability)
– 20-Kbyte RAM
– 6 Kbytes of data EEPROM with ECC
– 20-byte backup register
– Sector protection against R/W operation
• Up to 84 fast I/Os (78 I/Os 5V tolerant)
• Reset and supply management
– Ultra-safe, low-power BOR (brownout reset) with 5 selectable thresholds
– Ultra-low-power POR/PDR
– Programmable voltage detector (PVD)
• Clock sources
– 1 to 25 MHz crystal oscillator
– 32 kHz oscillator for RTC with calibration
– High speed internal 16 MHz factory-trimmed RC
(+/- 1%)
– Internal low-power 37 kHz RC
– Internal multispeed low-power 65 kHz to
4.2 MHz RC
– Internal self calibration of 48 MHz RC for USB
– PLL for CPU clock
• Pre-programmed bootloader
– USB, USART supported
• Development support
– Serial wire debug supported
• LCD driver for up to 4x52 or 8x48 segments
FBGA
FBGA
LQFP48 (7 x 7 mm)
LQFP64 (10x10 mm)
LQFP100 (14x14 mm)
UFQFPN48
(7x7 mm)
UFBGA100
7x7 mm
TFBGA64
5x5 mm
– Support contrast adjustment
– Support blinking mode
– Step-up converted on board
• Rich Analog peripherals
– 12-bit ADC 1.14 Msps up to 16 channels (down to 1.65 V)
– 2 x 12-bit channel DACs with output buffers
(down to 1.8 V)
– 2x ultra-low-power comparators (window mode and wake up capability, down to 1.65 V)
• Up to 24 capacitive sensing channels supporting touchkey, linear and rotary touch sensors
• 7-channel DMA controller, supporting ADC, SPI,
I2C, USART, DAC, Timers, AES
• 11x peripheral communication interfaces
– 1x USB 2.0 crystal-less, battery charging detection and LPM
– 4x USART (2 with ISO 7816, IrDA), 1x UART
(low power)
– Up to 6x SPI 16 Mbits/s
– 3x I2C (2 with SMBus/PMBus)
• 11x timers: 2x 16-bit with up to 4 channels, 2x 16-bit with up to 2 channels, 1x 16-bit ultra-low-power timer, 1x SysTick, 1x RTC, 2x 16-bit basic for DAC, and 2x watchdogs (independent/window)
• CRC calculation unit, 96-bit unique ID
• True RNG and firewall protection
• Hardware Encryption Engine AES 128-bit
• All packages are ECOPACK2
Table 1. Device summary
Reference Part number
STM32L083x8
STM32L083xB
STM32L083xZ
STM32L083V8
STM32L083CB, STM32L083VB, STM32L083RB
STM32L083CZ, STM32L083VZ, STM32L083RZ
November 2019
This is information on a product in full production.
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Contents
Contents
STM32L083xx
Ultra-low-power device continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Arm® Cortex®-M0+ core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Low-power real-time clock and backup registers . . . . . . . . . . . . . . . . . . . 25
General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 25
Direct memory access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
REFINT
) . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Ultra-low-power comparators and reference voltage . . . . . . . . . . . . . . . . 29
Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
General-purpose timers (TIM2, TIM3, TIM21 and TIM22) . . . . . . . . . . . 31
Low-power Timer (LPTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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Basic timer (TIM6, TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Universal synchronous/asynchronous receiver transmitter (USART) . . 34
Low-power universal asynchronous receiver transmitter (LPUART) . . . 35
Serial peripheral interface (SPI)/Inter-integrated sound (I2S) . . . . . . . . 35
Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Cyclic redundancy check (CRC) calculation unit . . . . . . . . . . . . . . . . . . . 36
Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Optional LCD power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Embedded reset and power control block characteristics . . . . . . . . . . . 66
Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
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STM32L083xx
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
UFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
TFBGA64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
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List of tables
List of tables
Ultra-low-power STM32L083xxx device features and peripheral counts . . . . . . . . . . . . . . 11
Functionalities depending on the working mode
Capacitive sensing GPIOs available on STM32L083xx devices . . . . . . . . . . . . . . . . . . . . 30
C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Current consumption in Run mode, code with data processing running from
Current consumption in Run mode, code with data processing running from RAM . . . . . . 71
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List of tables STM32L083xx
max for f
ADC
= 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
UFBGA100 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 128
TFBGA64 recommended PCB design rules (0.5 mm pitch BGA). . . . . . . . . . . . . . . . . . . 134
LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data. . . . . . . . . . . 137
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List of figures
List of figures
IDD vs VDD, at TA= 25/55/85/105 °C, Run mode, code running from
IDD vs VDD, at TA= 25/55/85/105 °C, Run mode, code running from
Power supply and reference decoupling (V
REF+
Power supply and reference decoupling (V
REF+ not connected to V
DDA connected to V
DDA
) . . . . . . . . . . . . 105
). . . . . . . . . . . . . . . . 106
SPI timing diagram - slave mode and CPHA = 1
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
SPI timing diagram - master mode
2
2
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
S slave timing diagram (Philips protocol)
(1)
S master timing diagram (Philips protocol)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . 124
UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
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List of figures STM32L083xx
LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat recommended footprint . . . . . . . . . . 131
TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch, thin profile fine pitch ball
LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat recommended footprint . . . . . . . . . . . . 137
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1 Introduction
Introduction
The ultra-low-power STM32L083xx are offered in 6 different package types from 48 to 100 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family.
These features make the ultra-low-power STM32L083xx microcontrollers suitable for a wide range of applications:
• Gas/water meters and industrial sensors
• Healthcare and fitness equipment
• Remote control and user interface
• PC peripherals, gaming, GPS equipment
• Alarm system, wired and wireless sensors, video intercom
This STM32L083xx datasheet should be read in conjunction with the STM32L0x3xx reference manual (RM0367) .
For information on the Arm
®(a)
Cortex
®
-M0+ core please refer to the Cortex
®
-M0+ Technical
Reference Manual, available from the www.arm.com website.
Figure 1 shows the general block diagram of the device family.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
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Description
2 Description
STM32L083xx
The ultra-low-power STM32L083xx microcontrollers incorporate the connectivity power of the universal serial bus (USB 2.0 crystal-less) with the high-performance Arm Cortex-M0+
32-bit RISC core operating at a 32 MHz frequency, a memory protection unit (MPU), highspeed embedded memories (up to 192 Kbytes of Flash program memory, 6 Kbytes of data
EEPROM and 20 Kbytes of RAM) plus an extensive range of enhanced I/Os and peripherals.
The STM32L083xx devices provide high power efficiency for a wide range of performance.
It is achieved with a large choice of internal and external clock sources, an internal voltage adaptation and several low-power modes.
The STM32L083xx devices offer several analog features, one 12-bit ADC with hardware oversampling, two DACs, two ultra-low-power comparators, AES, several timers, one lowpower timer (LPTIM), four general-purpose 16-bit timers and two basic timer, one RTC and one SysTick which can be used as timebases. They also feature two watchdogs, one watchdog with independent clock and window capability and one window watchdog based on bus clock.
Moreover, the STM32L083xx devices embed standard and advanced communication interfaces: up to three I2Cs, two SPIs, one I2S, four USARTs, a low-power UART
(LPUART), and a crystal-less USB. The devices offer up to 24 capacitive sensing channels to simply add touch sensing functionality to any application.
The STM32L083xx also include a real-time clock and a set of backup registers that remain powered in Standby mode.
Finally, their integrated LCD controller has a built-in LCD voltage generator that allows to drive up to 8 multiplexed LCDs with contrast independent of the supply voltage.
The ultra-low-power STM32L083xx devices operate from a 1.8 to 3.6 V power supply (down to 1.65 V at power down) with BOR and from a 1.65 to 3.6 V power supply without BOR option. They are available in the -40 to +125 °C temperature range. A comprehensive set of power-saving modes allows the design of low-power applications.
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Table 2. Ultra-low-power STM32L083xxx device features and peripheral counts
Peripheral
STM32L083
V8
STM32L083
CB
STM32L083
VB
STM32L083
RB
STM32L083
CZ
STM32L083
VZ
STM32L083
RZ
Flash memory (Kbytes)
Data EEPROM (Kbytes)
RAM (Kbytes)
AES
64 Kbytes
3 Kbytes
128 Kbytes
6 Kbytes
20 Kbytes
1
192 Kbytes
Timers
Generalpurpose
Basic
LPTIMER
RTC/SYSTICK/IWDG/WWDG
SPI/I2S
I 2 C
Communication interfaces
USART
LPUART
USB/(VDD_USB)
GPIOs
4
2
1
1/1/1/1
6(4)
(1)
/1
3
4
1
1/(1)
51 84 40 84 40 84 51
Clocks:
HSE/LSE/HSI/MSI/LSI
12-bit synchronized ADC
Number of channels
12-bit DAC
Number of channels
1
16
1
10
1
16
1/1/1/1/1
2
2
1
10
1
16
LCD
COM x SEG
1
4x52 or
8x48
1
4x18
1
4x52 or
8x48
1
4x32 or 8x28
1
4x18
1
4x52 or
8x48
1
4x32 or
8x28
(2)
Comparators
Capacitive sensing channels
24 17 24
2
24 17 24 24
Max. CPU frequency 32 MHz
Operating voltage 1.8 V to 3.6 V (down to 1.65 V at power-down) with BOR option 1.65 to 3.6 V without BOR option
Operating temperatures
Packages
LQFP100,
UFBGA100
LQFP48,
UFQFPN48
1. 4 SPI interfaces are USARTs operating in SPI master mode.
2. On TFBGA64, only 4x31 or 8x27 COMxSEG are available.
Ambient temperature: –40 to +125 °C
Junction temperature: –40 to +130 °C
LQFP100,
UFBGA100
LQFP64
LQFP48,
UFQFPN48
LQFP100,
UFBGA100
LQFP64,
TFBGA64
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Description
SWD
PA[0:15]
PB[0:15]
PC[0:15]
PD[0:15]
PE[0:15]
PH[0:1], [9:10]
OSC_IN,
OSC_OUT
WKUPx
OSC32_IN,
OSC32_OUT
PVD_IN
VREF_OUT
NRST
VDDA
VDD
Figure 1. STM32L083xx block diagram
GPIO PORT D
GPIO PORT E
HSE
PLL
LSE
SWD
CORTEX M0+ CPU
Fmax:32MHz
GPIO PORT A
GPIO PORT B
GPIO PORT C
GPIO PORT H
MPU
NVIC
HSI 16M
MSI
RESET & CLK
TSC
Temp sensor
FLASH
EEPROM
BOOT
RAM
DMA1
FIREWALL
DBG
EXTI
BRIDGE
A
P
B
2
ADC1
SPI1
USART1
TIM21
TIM22
COMP1
COMP2
CRC
RNG
AES
HSI 48M
LSI
BRIDGE
RAM 1K
TIM6
TIM7
WWDG
CRS
IWDG
RTC
BCKP REG
LPTIM1
A
P
B
1
USB 2.0 FS
DAC1
DAC2
I2C1
I2C2
I2C3
USART2
USART4
USART5
LPUART1
SPI2/I2S
TIM2
TIM3
LCD
PMU
REGULATOR
STM32L083xx
AINx
MISO, MOSI,
SCK, NSS
RX, TX, RTS,
CTS, CK
2ch
2ch
INP, INM, OUT
INP, INM, OUT
IN1, IN2,
ETR, OUT
DP, DM, OE,
CRS_SYNC,
VDD_USB
OUT1
OUT1
SCL, SDA,
SMBA
SCL, SDA
SCL, SDA,
SMBA
RX, TX, RTS,
CTS, CK
RX, TX, RTS,
CTS, CK
RX, TX, RTS,
CTS, CK
RX, TX, RTS,
CTS
MISO/MCK,
MOSI/SD,
SCK/CK, NSS/
WS
4ch
4ch
COMx, SEGx,
LCD_VLCDx
MSv35432V1
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2.2
Description
Ultra-low-power device continuum
The ultra-low-power family offers a large choice of core and features, from 8-bit proprietary core up to Arm
®
Cortex
®
-M4, including Arm
®
Cortex
®
-M3 and Arm
®
Cortex
®
-M0+. The
STM32Lx series are the best choice to answer your needs in terms of ultra-low-power features. The STM32 ultra-low-power series are the best solution for applications such as gaz/water meter, keyboard/mouse or fitness and healthcare application. Several built-in features like LCD drivers, dual-bank memory, low-power run mode, operational amplifiers,
128-bit AES, DAC, crystal-less USB and many other definitely help you building a highly cost optimized application by reducing BOM cost. STMicroelectronics, as a reliable and long-term manufacturer, ensures as much as possible pin-to-pin compatibility between all
STM8Lx and STM32Lx on one hand, and between all STM32Lx and STM32Fx on the other hand. Thanks to this unprecedented scalability, your legacy application can be upgraded to respond to the latest market feature and efficiency requirements.
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Functional overview STM32L083xx
The ultra-low-power STM32L083xx support dynamic voltage scaling to optimize its power consumption in Run mode. The voltage from the internal low-drop regulator that supplies the logic can be adjusted according to the system’s maximum operating frequency and the external voltage supply.
There are three power consumption ranges:
• Range 1 (V
DD
range limited to 1.71-3.6 V), with the CPU running at up to 32 MHz
• Range 2 (full V
DD
range), with a maximum CPU frequency of 16 MHz
• Range 3 (full V
DD
range), with a maximum CPU frequency limited to 4.2 MHz
Seven low-power modes are provided to achieve the best compromise between low-power consumption, short startup time and available wakeup sources:
• Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. Sleep mode power consumption at
16 MHz is about 1 mA with all peripherals off.
• Low-power run mode
This mode is achieved with the multispeed internal (MSI) RC oscillator set to the lowspeed clock (max 131 kHz), execution from SRAM or Flash memory, and internal regulator in low-power mode to minimize the regulator's operating current. In Lowpower run mode, the clock frequency and the number of enabled peripherals are both limited.
• Low-power sleep mode
This mode is achieved by entering Sleep mode with the internal voltage regulator in low-power mode to minimize the regulator’s operating current. In Low-power sleep mode, both the clock frequency and the number of enabled peripherals are limited; a typical example would be to have a timer running at 32 kHz.
When wakeup is triggered by an event or an interrupt, the system reverts to the Run mode with the regulator on.
Stop mode with RTC
The Stop mode achieves the lowest power consumption while retaining the RAM and register contents and real time clock. All clocks in the V
CORE domain are stopped, the
PLL, MSI RC, HSE crystal and HSI RC oscillators are disabled. The LSE or LSI is still running. The voltage regulator is in the low-power mode.
Some peripherals featuring wakeup capability can enable the HSI RC during Stop mode to detect their wakeup condition.
The device can be woken up from Stop mode by any of the EXTI line, in 3.5 µs, the processor can serve the interrupt or resume the code. The EXTI line source can be any
GPIO. It can be the PVD output, the comparator 1 event or comparator 2 event
(if internal reference voltage is on), it can be the RTC alarm/tamper/timestamp/wakeup events, the USB/USART/I2C/LPUART/LPTIMER wakeup events.
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Note:
Functional overview
• Stop mode without RTC
The Stop mode achieves the lowest power consumption while retaining the RAM and register contents. All clocks are stopped, the PLL, MSI RC, HSI and LSI RC, HSE and
LSE crystal oscillators are disabled.
Some peripherals featuring wakeup capability can enable the HSI RC during Stop mode to detect their wakeup condition.
The voltage regulator is in the low-power mode. The device can be woken up from Stop mode by any of the EXTI line, in 3.5 µs, the processor can serve the interrupt or resume the code. The EXTI line source can be any GPIO. It can be the PVD output, the comparator 1 event or comparator 2 event (if internal reference voltage is on). It can also be wakened by the USB/USART/I2C/LPUART/LPTIMER wakeup events.
• Standby mode with RTC
The Standby mode is used to achieve the lowest power consumption and real time clock. The internal voltage regulator is switched off so that the entire V
CORE
domain is powered off. The PLL, MSI RC, HSE crystal and HSI RC oscillators are also switched off. The LSE or LSI is still running. After entering Standby mode, the RAM and register contents are lost except for registers in the Standby circuitry (wakeup logic, IWDG,
RTC, LSI, LSE Crystal 32 KHz oscillator, RCC_CSR register).
The device exits Standby mode in 60 µs when an external reset (NRST pin), an IWDG reset, a rising edge on one of the three WKUP pins, RTC alarm (Alarm A or Alarm B),
RTC tamper event, RTC timestamp event or RTC Wakeup event occurs.
• Standby mode without RTC
The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire V
CORE
domain is powered off. The
PLL, MSI RC, HSI and LSI RC, HSE and LSE crystal oscillators are also switched off.
After entering Standby mode, the RAM and register contents are lost except for registers in the Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE Crystal 32 KHz oscillator, RCC_CSR register).
The device exits Standby mode in 60 µs when an external reset (NRST pin) or a rising edge on one of the three WKUP pin occurs.
The RTC, the IWDG, and the corresponding clock sources are not stopped automatically by entering Stop or Standby mode. The LCD is not stopped automatically by entering Stop mode.
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Functional overview STM32L083xx
Table 3. Functionalities depending on the operating power supply range
Functionalities depending on the operating power supply range
Operating power supply range
(1)
DAC and ADC operation
Dynamic voltage scaling range
USB
V
V
V
DD
DD
DD
V
V
= 1.65 to 1.71 V
= 1.71 to 1.8 V
= 1.8 to 2.0 V
DD
DD
(2)
= 2.0 to 2.4 V
= 2.4 to 3.6 V
(2)
ADC only, conversion time up to 570 ksps
ADC only, conversion time up to 1.14 Msps
Conversion time up to
1.14 Msps
Conversion time up to
1.14 Msps
Conversion time up to
1.14 Msps
Range 2 or range 3
Range 1, range 2 or range 3
Range1, range 2 or range 3
Range 1, range 2 or range 3
Range 1, range 2 or range 3
Not functional
Functional
Functional
Functional
Functional
(3)
(3)
(3)
(3)
1. GPIO speed depends on V about I/O speed.
DD
voltage range. Refer to
Table 62: I/O AC characteristics for more information
2. CPU frequency changes from initial to final must respect "fcpu initial <4*fcpu final". It must also respect 5
μ s delay between two changes. For example to switch from 4.2 MHz to 32 MHz, you can switch from 4.2
MHz to 16 MHz, wait 5 μ s, then switch from 16 MHz to 32 MHz.
3. To be USB compliant from the I/O voltage standpoint, the minimum V
DD_USB is 3.0 V.
Table 4. CPU frequency range depending on dynamic voltage scaling
CPU frequency range Dynamic voltage scaling range
16 MHz to 32 MHz (1ws)
32 kHz to 16 MHz (0ws)
8 MHz to 16 MHz (1ws)
32 kHz to 8 MHz (0ws)
32 kHz to 4.2 MHz (0ws)
Range 1
Range 2
Range 3
DS10671 Rev 5
STM32L083xx Functional overview
IPs
CPU
Flash memory
RAM
Backup registers
EEPROM
Brown-out reset
(BOR)
DMA
Programmable
Voltage Detector
(PVD)
Power-on/down reset (POR/PDR)
High Speed
Internal (HSI)
High Speed
External (HSE)
Low Speed Internal
(LSI)
Low Speed
External (LSE)
Multi-Speed
Internal (MSI)
Inter-Connect
Controller
RTC
RTC Tamper
Auto WakeUp
(AWU)
LCD
USB
USART
LPUART
SPI
I2C
ADC
Y
O
O
O
O
O
O
O
O
O
O
Table 5. Functionalities depending on the working mode
(from Run/active down to standby) (1)(2)
Stop
Run/Active Sleep
Lowpower run
Lowpower sleep
Wakeup capability
Y
Y
Y
O
O
Y
Y
--
O
O
Y
Y
Y
O
O
Y
Y
--
O
O
Y
Y
--
--
--
O
O
O
O
O
O
O
O
O
--
O O
--
--
Y
--
--
--
Standby
Wakeup capability
O
O
Y
O
O
O
O
O
O
Y
O
O
O
O
O
Y
O
O
O
O
O
O
O
O
O
O
O
Y
--
O
O
O
Y
Y
O
O
O
O
O
O
--
--
O
--
O
Y
--
O
O
O
Y
O
Y
(3)
--
O
O
--
Y
O
O
O
O
--
O
(4)
O
--
O
(5)
--
Y
O
O
O
O
O
O
--
--
O
--
O
Y
O
O
O
O
O
O
O
-
Y
--
--
O
O
--
--
O
O
O
--
--
--
--
--
--
--
Y
O
O
DS10671 Rev 5
36
Functional overview STM32L083xx
IPs
Table 5. Functionalities depending on the working mode
(from Run/active down to standby) (continued) (1)(2)
Stop
Run/Active Sleep
Lowpower run
Lowpower sleep
Wakeup capability
Standby
Wakeup capability
DAC
Temperature sensor
Comparators
16-bit timers
LPTIMER
IWDG
WWDG
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
--
O
O
--
O
O
O
--
--
--
--
O
--
O
Touch sensing controller (TSC)
SysTick Timer
O O -----
GPIOs
Wakeup time to
Run mode
O
O
0 µs
O
O
0.36 µs
O
O
3 µs
O
O
32 µs
O O
3.5 µs
--
2 pins
50 µs
Consumption
V
DD
=1.8 to 3.6 V
(Typ)
Down to
140 µA/MHz
(from Flash memory)
Down to
37 µA/MHz
(from Flash memory)
Down to
8 µA
Down to
4.5 µA
0.4 µA (No
RTC) V
DD
=1.8 V
0.8 µA (with
RTC) V
DD
=1.8 V
0.4 µA (No
RTC) V
DD
=3.0 V
1 µA (with RTC)
V
DD
=3.0 V
0.28 µA (No
RTC) V
DD
=1.8 V
0.65 µA (with
RTC) V
DD
=1.8 V
0.29 µA (No
RTC) V
DD
=3.0 V
0.85 µA (with
RTC) V
DD
=3.0 V
1. Legend:
“Y” = Yes (enable).
“O” = Optional can be enabled/disabled by software)
“-” = Not available
2. The consumption values given in this table are preliminary data given for indication. They are subject to slight changes.
3. Some peripherals with wakeup from Stop capability can request HSI to be enabled. In this case, HSI is woken up by the peripheral, and only feeds the peripheral which requested it. HSI is automatically put off when the peripheral does not need it anymore.
4. UART and LPUART reception is functional in Stop mode. It generates a wakeup interrupt on Start. To generate a wakeup on address match or received frame event, the LPUART can run on LSE clock while the UART has to wake up or keep running the HSI clock.
5. I2C address detection is functional in Stop mode. It generates a wakeup interrupt in case of address match. It will wake up the HSI during reception.
DS10671 Rev 5
STM32L083xx Functional overview
Several peripherals are directly interconnected. This allows autonomous communication between peripherals, thus saving CPU resources and power consumption. In addition, these hardware connections allow fast and predictable latency.
Depending on peripherals, these interconnections can operate in Run, Sleep, Low-power run, Low-power sleep and Stop modes.
Interconnect source
COMPx
RTC
All clock source
USB
GPIO
Table 6. STM32L0xx peripherals interconnect matrix
Interconnect destination
Interconnect action Run Sleep
Low- power run
Low- power sleep
Stop
TIM2,TIM21,
TIM22
LPTIM
TIMx TIMx
TIM21
LPTIM
TIMx
CRS/HSI48
TIM3
TIMx
LPTIM
ADC,DAC
Timer input channel, trigger from analog signals comparison
Timer input channel, trigger from analog signals comparison
Timer triggered by other timer
Timer triggered by Auto wake-up
Timer triggered by RTC event
Clock source used as input channel for RC measurement and trimming the clock recovery system trims the HSI48 based on USB SOF
USB_SOF is channel input for calibration
Timer input channel and trigger
Timer input channel and trigger
Conversion trigger
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
-
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
-
Y
Y
Y -
-
Y
Y
-
-
-
-
-
-
Y
DS10671 Rev 5
36
Functional overview STM32L083xx
3.3 Arm
®
Cortex
®
-M0+ core with MPU
The Cortex-M0+ processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
• a simple architecture that is easy to learn and program
• ultra-low power, energy-efficient operation
• excellent code density
• deterministic, high-performance interrupt handling
• upward compatibility with Cortex-M processor family
• platform security robustness, with integrated Memory Protection Unit (MPU).
The Cortex-M0+ processor is built on a highly area and power optimized 32-bit processor core, with a 2-stage pipeline Von Neumann architecture. The processor delivers exceptional energy efficiency through a small but powerful instruction set and extensively optimized design, providing high-end processing hardware including a single-cycle multiplier.
The Cortex-M0+ processor provides the exceptional performance expected of a modern 32bit architecture, with a higher code density than other 8-bit and 16-bit microcontrollers.
Owing to its embedded Arm core, the STM32L083xx are compatible with all Arm tools and software.
Nested vectored interrupt controller (NVIC)
The ultra-low-power STM32L083xx embed a nested vectored interrupt controller able to handle up to 32 maskable interrupt channels and 4 priority levels.
The Cortex-M0+ processor closely integrates a configurable Nested Vectored Interrupt
Controller (NVIC), to deliver industry-leading interrupt performance. The NVIC:
• includes a Non-Maskable Interrupt (NMI)
• provides zero jitter interrupt option
• provides four interrupt priority levels
The tight integration of the processor core and NVIC provides fast execution of Interrupt
Service Routines (ISRs), dramatically reducing the interrupt latency. This is achieved through the hardware stacking of registers, and the ability to abandon and restart loadmultiple and store-multiple operations. Interrupt handlers do not require any assembler wrapper code, removing any code overhead from the ISRs. Tail-chaining optimization also significantly reduces the overhead when switching from one ISR to another.
To optimize low-power designs, the NVIC integrates with the sleep modes, that include a deep sleep function that enables the entire device to enter rapidly stop or standby mode.
This hardware block provides flexible interrupt management features with minimal interrupt latency.
DS10671 Rev 5
STM32L083xx
3.4
3.4.1
3.4.2
Note:
Functional overview
Reset and supply management
Power supply schemes
• V
DD
= 1.65 to 3.6 V: external power supply for I/Os and the internal regulator. Provided externally through V
DD
pins.
• V
SSA
, V
DDA
= 1.65 to 3.6 V: external analog power supplies for ADC reset blocks, RCs and PLL. V
DDA
and V
SSA
must be connected to V
DD
and V
SS
, respectively.
• V
DD_USB
= 1.65 to 3.6V: external power supply for USB transceiver, USB_DM (PA11) and USB_DP (PA12). To guarantee a correct voltage level for USB communication
V
DD_USB
must be above 3.0V. If USB is not used this pin must be tied to V
DD
On packages without VDD_USB pin, V
DD_USB voltage.
or V
SS
.
voltage is internally connected to V
DD
Power supply supervisor
The devices have an integrated ZEROPOWER power-on reset (POR)/power-down reset
(PDR) that can be coupled with a brownout reset (BOR) circuitry.
Two versions are available:
• The version with BOR activated at power-on operates between 1.8 V and 3.6 V.
• The other version without BOR operates between 1.65 V and 3.6 V.
After the V
DD
threshold is reached (1.65 V or 1.8 V depending on the BOR which is active or not at power-on), the option byte loading process starts, either to confirm or modify default thresholds, or to disable the BOR permanently: in this case, the VDD min value becomes
1.65 V (whatever the version, BOR active or not, at power-on).
When BOR is active at power-on, it ensures proper operation starting from 1.8 V whatever the power ramp-up phase before it reaches 1.8 V. When BOR is not active at power-up, the power ramp-up should guarantee that 1.65 V is reached on V
DD the POR area.
at least 1 ms after it exits
Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To reduce the power consumption in Stop mode, it is possible to automatically switch off the internal reference voltage (V
REFINT
V
DD reset circuit.
) in Stop mode. The device remains in reset mode when
is below a specified threshold, V
POR/PDR
or V
BOR
, without the need for any external
The start-up time at power-on is typically 3.3 ms when BOR is active at power-up, the startup time at power-on can be decreased down to 1 ms typically for devices with BOR inactive at power-up.
The devices feature an embedded programmable voltage detector (PVD) that monitors the
V
DD/VDDA
power supply and compares it to the V
PVD
threshold. This PVD offers 7 different levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An interrupt can be generated when V
V
DD/VDDA
is higher than the V
PVD
DD/VDDA
drops below the V
PVD
threshold and/or when
threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.
DS10671 Rev 5
36
Functional overview STM32L083xx
The regulator has three operation modes: main (MR), low power (LPR) and power down.
• MR is used in Run mode (nominal regulation)
• LPR is used in the Low-power run, Low-power sleep and Stop modes
• Power down is used in Standby mode. The regulator output is high impedance, the kernel circuitry is powered down, inducing zero consumption but the contents of the registers and RAM are lost except for the standby circuitry (wakeup logic, IWDG, RTC,
LSI, LSE crystal 32 KHz oscillator, RCC_CSR).
The clock controller distributes the clocks coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness. It features:
• Clock prescaler
To get the best trade-off between speed and current consumption, the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler.
• Safe clock switching
Clock sources can be changed safely on the fly in Run mode through a configuration register.
• Clock management
To reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory.
• System clock source
Three different clock sources can be used to drive the master clock SYSCLK:
– 1-25 MHz high-speed external crystal (HSE), that can supply a PLL
– 16 MHz high-speed internal RC oscillator (HSI), trimmable by software, that can supply a PLLMultispeed internal RC oscillator (MSI), trimmable by software, able to generate 7 frequencies (65 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.1
MHz, 4.2 MHz). When a 32.768 kHz clock source is available in the system (LSE), the MSI frequency can be trimmed by software down to a ±0.5% accuracy.
• Auxiliary clock source
Two ultra-low-power clock sources that can be used to drive the LCD controller and the real-time clock:
– 32.768 kHz low-speed external crystal (LSE)
– 37 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.
The LSI clock can be measured using the high-speed internal RC oscillator for greater precision.
• RTC and LCD clock source
The LSI, LSE or HSE sources can be chosen to clock the RTC and the LCD, whatever the system clock.
• USB clock source
A 48 MHz clock trimmed through the USB SOF or LSE supplies the USB interface.
DS10671 Rev 5
STM32L083xx Functional overview
• Startup clock
After reset, the microcontroller restarts by default with an internal 2.1 MHz clock (MSI).
The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts.
• Clock security system (CSS)
This feature can be enabled by software. If an HSE clock failure occurs, the master clock is automatically switched to HSI and a software interrupt is generated if enabled.
Another clock security system can be enabled, in case of failure of the LSE it provides an interrupt or wakeup event which is generated if enabled.
• Clock-out capability (MCO: microcontroller clock output)
It outputs one of the internal clocks for external use by the application.
Several prescalers allow the configuration of the AHB frequency, each APB (APB1 and
APB2) domains. The maximum frequency of the AHB and the APB domains is 32 MHz. See
Figure 2 for details on the clock tree.
DS10671 Rev 5
36
Functional overview
@V33
LSI RC
LSE OSC
Enable Watchdog
LSI tempo
LSE tempo
Figure 2. Clock tree
Watchdog LS
RTCSEL
RTC2 enable
RTC
LCD enable
STM32L083xx
Legend:
HSE = High-speed external clock signal
HSI = High-speed internal clock signal
LSI = Low-speed internal clock signal
LSE = Low-speed external clock signal
MSI = Multispeed internal clock signal
@V18
@V33
MSI RC
Level shifters
@V18
MSI
/ 2,4,8,16
@V33
HSI16 RC
Level shifters
@V18 ck_rchs
/ 1,4
HSI16
@V33
HSE OSC
Level shifters
@V18
@V33
1 MHz Clock
Detector
@V33
RC 48MHz
Level shifters
@V18
Clock
Recovery
System
LSU
LSD
HSI48
LSU LSD LSD
1 MHz
LSD
LSI
LSE
MSI
HSI16
HSE
PLLSRC ck_pllin PLL
X
3,4,6,8,12,16,
24,32,48
/ 2,3,4
Level shifters
@V
DDCORE
HSE present or not
Dedicated 48MHz PLL output
HSI48MSEL
MCOSEL
ADC enable
LCDCLK
ADCCLK
/ 1,2,4,8,16
MCO not deepsleep
CK_PWR not deepsleep not (sleep or deepsleep)
FCLK
System
Clock not (sleep or deepsleep)
/ 8
HCLK
Clock
Source
Control
AHB
PRESC
/ 1,2,…, 512
APB1
PRESC
/ 1,2,4,8,16
32 MHz max.
PCLK1 to APB1 peripherals
Peripheral clock enable
If (APB1 presc=1) x1 else x2) to TIMx
Peripheral clock enable
PCLK2 to APB2
32 MHz peripherals max.
APB2
PRESC
/ 1,2,4,8,16
Peripheral clock enable
If (APB2 presc=1) x1 else x2) to TIMx
LSI Peripheral clock enable
SYSCLK
SysTick
Timer
LSE
HSI16
Peripheral clock enable
LPTIMCLK
PCLK Peripheral clock enable
LPUART/
UARTCLK
I2CCLK usb_en rng_en
48MHz
USBCLK
48MHz RNG
MSv35411V1
DS10671 Rev 5
STM32L083xx Functional overview
The real time clock (RTC) and the 5 backup registers are supplied in all modes including standby mode. The backup registers are five 32-bit registers used to store 20 bytes of user application data. They are not reset by a system reset, or when the device wakes up from
Standby mode.
The RTC is an independent BCD timer/counter. Its main features are the following:
• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format
• Automatically correction for 28, 29 (leap year), 30, and 31 day of the month
• Two programmable alarms with wake up from Stop and Standby mode capability
• Periodic wakeup from Stop and Standby with programmable resolution and period
• On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master clock.
• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision.
• Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal inaccuracy
• 2 anti-tamper detection pins with programmable filter. The MCU can be woken up from
Stop and Standby modes on tamper event detection.
• Timestamp feature which can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be woken up from Stop and Standby modes on timestamp event detection.
The RTC clock sources can be:
• A 32.768 kHz external crystal
• A resonator or oscillator
• The internal low-power RC oscillator (typical frequency of 37 kHz)
• The high-speed external clock
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions, and can be individually remapped using dedicated alternate function registers. All GPIOs are high current capable.
Each GPIO output, speed can be slowed (40 MHz, 10 MHz, 2 MHz, 400 kHz). The alternate function configuration of I/Os can be locked if needed following a specific sequence in order to avoid spurious writing to the I/O registers. The I/O controller is connected to a dedicated
IO bus with a toggling speed of up to 32 MHz.
Extended interrupt/event controller (EXTI)
The extended interrupt/event controller consists of 29 edge detector lines used to generate interrupt/event requests. Each line can be individually configured to select the trigger event
(rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 84 GPIOs can be connected to the 16 configurable interrupt/event lines. The 13 other lines are connected to PVD, RTC,
USB, USARTs, I2C, LPUART, LPTIMER or comparator events.
DS10671 Rev 5
36
Functional overview STM32L083xx
3.8 Memories
The STM32L083xx devices have the following features:
• 20 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states. With the enhanced bus matrix, operating the RAM does not lead to any performance penalty during accesses to the system bus (AHB and APB buses).
• The non-volatile memory is divided into three arrays:
– 64, 128 or 192 Kbytes of embedded Flash program memory
– 6 Kbytes of data EEPROM
– Information block containing 32 user and factory options bytes plus Kbytes of system memory
Flash program and data EEPROM are divided into two banks. This allows writing in one bank while running code or reading data from the other bank.
The user options bytes are used to write-protect or read-out protect the memory (with
4 Kbyte granularity) and/or readout-protect the whole memory with the following options:
• Level 0 : no protection
• Level 1 : memory readout protected.
The Flash memory cannot be read from or written to if either debug features are connected or boot in RAM is selected
• Level 2 : chip readout protected, debug features (Cortex-M0+ serial wire) and boot in
RAM selection disabled (debugline fuse)
The firewall protects parts of code/data from access by the rest of the code that is executed outside of the protected area. The granularity of the protected code segment or the nonvolatile data segment is 256 bytes (Flash memory or EEPROM) against 64 bytes for the volatile data segment (RAM).
The whole non-volatile memory embeds the error correction code (ECC) feature.
At startup, BOOT0 pin and nBOOT1 option bit are used to select one of three boot options:
• Boot from Flash memory
• Boot from System memory
• Boot from embedded RAM
The boot loader is located in System memory. It is used to reprogram the Flash memory by using USB (PA11, PA12), USART1(PA9, PA10) or USART2(PA2, PA3). See STM32™ microcontroller system memory boot mode AN2606 for details.
DS10671 Rev 5
STM32L083xx Functional overview
The flexible 7-channel, general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports circular buffer management, avoiding the generation of interrupts when the controller reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with software trigger support for each channel. Configuration is done by software and transfer sizes between source and destination are independent.
The DMA can be used with the main peripherals: AES, SPI, I
2
C, USART, LPUART, general-purpose timers, DAC, and ADC.
3.11 Liquid crystal display (LCD)
The LCD drives up to 8 common terminals and 48 segment terminals to drive up to 384 pixels.
• Internal step-up converter to guarantee functionality and contrast control irrespective of
V
DD
. This converter can be deactivated, in which case the V the voltage to the LCD
LCD
pin is used to provide
• Supports static, 1/2, 1/3, 1/4 and 1/8 duty
• Supports static, 1/2, 1/3 and 1/4 bias
• Phase inversion to reduce power consumption and EMI
• Up to 8 pixels can be programmed to blink
• Unneeded segments and common pins can be used as general I/O pins
• LCD RAM can be updated at any time owing to a double-buffer
• The LCD controller can operate in Stop mode
• V
LCD
rails decoupling capability
3.12 Analog-to-digital converter (ADC)
A native 12-bit, extended to 16-bit through hardware oversampling, analog-to-digital converter is embedded into STM32L083xx device. It has up to 16 external channels and 3 internal channels (temperature sensor, voltage reference, V
LCD
voltage measurement).
Three channels, PA0, PA4 and PA5, are fast channels, while the others are standard channels.
The ADC performs conversions in single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs.
The ADC frequency is independent from the CPU frequency, allowing maximum sampling rate of 1.14 MSPS even with a low CPU speed. The ADC consumption is low at all frequencies (~25 µA at 10 kSPS, ~240 µA at 1MSPS). An auto-shutdown function guarantees that the ADC is powered off except during the active conversion phase.
The ADC can be served by the DMA controller. It can operate from a supply voltage down to
1.65 V.
The ADC features a hardware oversampler up to 256 samples, this improves the resolution to 16 bits (see AN2668).
DS10671 Rev 5
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Functional overview STM32L083xx
An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all scanned channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.
The events generated by the general-purpose timers (TIMx) can be internally connected to the ADC start triggers, to allow the application to synchronize A/D conversions and timers.
The temperature sensor (T
SENSE temperature.
) generates a voltage V
SENSE that varies linearly with
The temperature sensor is internally connected to the ADC_IN18 input channel which is used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode.
Table 7. Temperature sensor calibration values
Calibration value name Description Memory address
TSENSE_CAL1
TSENSE_CAL2
TS ADC raw data acquired at temperature of 30 °C,
V
DDA
= 3 V
TS ADC raw data acquired at temperature of 130 °C
V
DDA
= 3 V
0x1FF8 007A - 0x1FF8 007B
0x1FF8 007E - 0x1FF8 007F
3.13.1 Internal voltage reference (V
REFINT
)
The internal voltage reference (V
REFINT
ADC and Comparators. V
REFINT enables accurate monitoring of the V
) provides a stable (bandgap) voltage output for the
is internally connected to the ADC_IN17 input channel. It for ADC). The precise voltage of V
DD
value (when no external voltage, V
REFINT
REF+
, is available
is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode.
Table 8. Internal voltage reference measured values
Calibration value name Description Memory address
VREFINT_CAL
Raw data acquired at temperature of 25 °C
V
DDA
= 3 V
0x1FF8 0078 - 0x1FF8 0079
DS10671 Rev 5
STM32L083xx Functional overview
3.13.2 V
LCD
voltage monitoring
This embedded hardware feature allows the application to measure the V
LCD
supply voltage using the internal ADC channel ADC_IN16. As the V
LCD
voltage may be higher than V
DDA and thus outside the ADC input range, the ADC input is connected to LCD_VLCD1 (which
, provides 1/3V
LCD
when the LCD is configured 1/3Bias and 1/4V
LCD
when the LCD is configured 1/4Bias or 1/2Bias).
Two 12-bit buffered DACs can be used to convert digital signal into analog voltage signal output. An optional amplifier can be used to reduce the output signal impedance.
This digital Interface supports the following features:
• One data holding register (for each channel)
• Left or right data alignment in 12-bit mode
• Synchronized update capability
• Noise-wave generation
• Triangular-wave generation
• Dual DAC channels with independent or simultaneous conversions
• DMA capability (including the underrun interrupt)
• External triggers for conversion
• Input reference voltage V
REF+
Six DAC trigger inputs are used in the STM32L083xx. The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels.
The STM32L083xx embed two comparators sharing the same current bias and reference voltage. The reference voltage can be internal or external (coming from an I/O).
• One comparator with ultra low consumption
• One comparator with rail-to-rail inputs, fast or slow mode.
• The threshold can be one of the following:
– DAC output
– External I/O pins
– Internal reference voltage (V
REFINT
)
– submultiple of Internal reference voltage(1/4, 1/2, 3/4) for the rail to rail comparator.
Both comparators can wake up the devices from Stop mode, and be combined into a window comparator.
The internal reference voltage is available externally via a low-power / low-current output buffer (driving current capability of 1 µA typical).
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Functional overview STM32L083xx
3.16 Touch sensing controller (TSC)
The STM32L083xx provide a simple solution for adding capacitive sensing functionality to any application. These devices offer up to 24 capacitive sensing channels distributed over 8 analog I/O groups.
Capacitive sensing technology is able to detect the presence of a finger near a sensor which is protected from direct touch by a dielectric (such as glass, plastic). The capacitive variation introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. It consists of charging the sensor capacitance and then transferring a part of the accumulated charges into a sampling capacitor until the voltage across this capacitor has reached a specific threshold. To limit the CPU bandwidth usage, this acquisition is directly managed by the hardware touch sensing controller and only requires few external components to operate.
The touch sensing controller is fully supported by the STMTouch touch sensing firmware library, which is free to use and allows touch sensing functionality to be implemented reliably in the end application.
Group
Table 9. Capacitive sensing GPIOs available on STM32L083xx devices
Capacitive sensing signal name
Pin name
Group
Capacitive sensing signal name
Pin name
1
2
3
4
TSC_G1_IO1
TSC_G1_IO2
TSC_G1_IO3
TSC_G1_IO4
TSC_G2_IO1
TSC_G2_IO2
TSC_G2_IO3
TSC_G2_IO4
TSC_G3_IO1
TSC_G3_IO2
TSC_G3_IO3
TSC_G3_IO4
TSC_G4_IO1
TSC_G4_IO2
TSC_G4_IO3
TSC_G4_IO4
PA5
PA6
PA7
PC5
PB0
PB1
PA0
PA1
PA2
PA3
PA4
(1)
PB2
PA9
PA10
PA11
PA12
5
6
7
8
TSC_G5_IO1
TSC_G5_IO2
TSC_G5_IO3
TSC_G5_IO4
TSC_G6_IO1
TSC_G6_IO2
TSC_G6_IO3
TSC_G6_IO4
TSC_G7_IO1
TSC_G7_IO2
TSC_G7_IO3
TSC_G7_IO4
TSC_G8_IO1
TSC_G8_IO2
TSC_G8_IO3
TSC_G8_IO4
1. This GPIO offers a reduced touch sensing sensitivity. It is thus recommended to use it as sampling capacitor I/O.
PC0
PC1
PC2
PC3
PC6
PC7
PC8
PC9
PB3
PB4
PB6
PB7
PB11
PB12
PB13
PB14
DS10671 Rev 5
STM32L083xx Functional overview
3.17 AES
The AES Hardware Accelerator can be used to encrypt and decrypt data using the AES algorithm (compatible with FIPS PUB 197, 2001 Nov 26).
• Key scheduler
• Key derivation for decryption
• 128-bit data block processed
• 128-bit key length
• 213 clock cycles to encrypt/decrypt one 128-bit block
• Electronic codebook (ECB), cypher block chaining (CBC), and counter mode (CTR) supported by hardware.
The AES can be served by the DMA controller.
3.18 Timers and watchdogs
The ultra-low-power STM32L083xx devices include three general-purpose timers, one low- power timer (LPTIM), one basic timer, two watchdog timers and the SysTick timer.
Table 10 compares the features of the general-purpose and basic timers.
Timer
TIM2,
TIM3
TIM21,
TIM22
TIM6,
TIM7
Counter resolution
16-bit
16-bit
16-bit
Table 10. Timer feature comparison
Counter type Prescaler factor
DMA request generation
Capture/compare channels
Complementary outputs
Up, down, up/down
Up, down, up/down
Up
Any integer between
1 and 65536
Any integer between
1 and 65536
Any integer between
1 and 65536
Yes
No
Yes
4
2
0
No
No
No
There are four synchronizable general-purpose timers embedded in the STM32L083xx device (see
TIM2, TIM3
TIM2 and TIM3 are based on 16-bit auto-reload up/down counter. It includes a 16-bit prescaler. It features four independent channels each for input capture/output compare,
PWM or one-pulse mode output.
The TIM2/TIM3 general-purpose timers can work together or with the TIM21 and TIM22 general-purpose timers via the Timer Link feature for synchronization or event chaining.
Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs.
TIM2/TIM3 have independent DMA request generation.
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Functional overview STM32L083xx
These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors.
TIM21 and TIM22
TIM21 and TIM22 are based on a 16-bit auto-reload up/down counter. They include a 16-bit prescaler. They have two independent channels for input capture/output compare, PWM or one-pulse mode output. They can work together and be synchronized with the TIM2/TIM3, full-featured general-purpose timers.
They can also be used as simple time bases and be clocked by the LSE clock source
(32.768 kHz) to provide time bases independent from the main CPU clock.
The low-power timer has an independent clock and is running also in Stop mode if it is clocked by LSE, LSI or an external clock. It is able to wakeup the devices from Stop mode.
This low-power timer supports the following features:
• 16-bit up counter with 16-bit autoreload register
• 16-bit compare register
• Configurable output: pulse, PWM
• Continuous / one shot mode
• Selectable software / hardware input trigger
• Selectable clock source
– Internal clock source: LSE, LSI, HSI or APB clock
– External clock source over LPTIM input (working even with no internal clock source running, used by the Pulse Counter Application)
• Programmable digital glitch filter
• Encoder mode
3.18.3 Basic timer (TIM6, TIM7)
These timers can be used as a generic 16-bit timebase.
This timer is dedicated to the OS, but could also be used as a standard downcounter. It is based on a 24-bit downcounter with autoreload capability and a programmable clock source. It features a maskable system interrupt generation when the counter reaches ‘0’.
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 37 kHz internal RC and, as it operates independently of the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. The counter can be frozen in debug mode.
DS10671 Rev 5
STM32L083xx Functional overview
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.
3.19.1 I
2
C bus
Up to three I 2 C interfaces (I2C1 and I2C3) can operate in multimaster or slave modes.
Each I 2 C interface can support Standard mode (Sm, up to 100 kbit/s), Fast mode (Fm, up to
400 kbit/s) and Fast Mode Plus (Fm+, up to 1 Mbit/s) with 20 mA output drive on some I/Os.
7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2 addresses, 1 with configurable mask) are also supported as well as programmable analog and digital noise filters.
Pulse width of suppressed spikes
Benefits
Drawbacks
Table 11. Comparison of I2C analog and digital filters
Analog filter Digital filter
≥ 50 ns
Available in Stop mode
Variations depending on temperature, voltage, process
Programmable length from 1 to 15
I2C peripheral clocks
1. Extra filtering capability vs. standard requirements.
2. Stable length
Wakeup from Stop on address match is not available when digital filter is enabled.
In addition, I2C1 and I2C3 provide hardware support for SMBus 2.0 and PMBus 1.1: ARP capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts verifications and ALERT protocol management. I2C1/I2C3 also have a clock domain independent from the CPU clock, allowing the I2C1/I2C3 to wake up the MCU from Stop mode on address match.
Each I2C interface can be served by the DMA controller.
for an overview of I2C interface features.
Table 12. STM32L083xx I 2 C implementation
I2C features
(1)
I2C1 I2C2
7-bit addressing mode
10-bit addressing mode
Standard mode (up to 100 kbit/s)
Fast mode (up to 400 kbit/s)
X
X
X
X
X
X
X
X
I2C3
X
X
X
X
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Functional overview STM32L083xx
Table 12. STM32L083xx I 2 C implementation (continued)
I2C features (1) I2C1 I2C2 I2C3
Fast Mode Plus with 20 mA output drive I/Os (up to 1
Mbit/s)
Independent clock
SMBus
Wakeup from STOP
X
X
X
X
X
-
-
-
(2)
1. X = supported.
2. See
Table 16: STM32L083xx pin definition on page 42 for the list of I/Os that feature Fast Mode Plus
capability
X
X
X
X
The four USART interfaces (USART1, USART2, USART4 and USART5) are able to communicate at speeds of up to 4 Mbit/s.
They provide hardware management of the CTS, RTS and RS485 driver enable (DE) signals, multiprocessor communication mode, master synchronous communication and single-wire half-duplex communication mode. USART1 and USART2 also support
SmartCard communication (ISO 7816), IrDA SIR ENDEC, LIN Master/Slave capability, auto baud rate feature and has a clock domain independent from the CPU clock, allowing to wake up the MCU from Stop mode using baudrates up to 42 Kbaud.
All USART interfaces can be served by the DMA controller.
Table 13 for the supported modes and features of USART interfaces.
Table 13. USART implementation
USART modes/features
(1)
USART1 and USART2 USART4 and USART5
Hardware flow control for modem
Continuous communication using DMA
Multiprocessor communication
Synchronous mode
(2)
Smartcard mode
Single-wire half-duplex communication
IrDA SIR ENDEC block
LIN mode
Dual clock domain and wakeup from Stop mode
Receiver timeout interrupt
Modbus communication
Auto baud rate detection (4 modes)
Driver Enable
1. X = supported.
2. This mode allows using the USART as an SPI master.
X
X
X
X
X
X
X
X
X
X
X
X
X
-
-
-
X
X
X
X
X
-
-
-
-
X
DS10671 Rev 5
STM32L083xx Functional overview
The devices embed one Low-power UART. The LPUART supports asynchronous serial communication with minimum power consumption. It supports half duplex single wire communication and modem operations (CTS/RTS). It allows multiprocessor communication.
The LPUART has a clock domain independent from the CPU clock. It can wake up the system from Stop mode using baudrates up to 46 Kbaud. The Wakeup events from Stop mode are programmable and can be:
• Start bit detection
• Or any received data frame
• Or a specific programmed data frame
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while having an extremely low energy consumption. Higher speed clock can be used to reach higher baudrates.
LPUART interface can be served by the DMA controller.
3.19.4 Serial peripheral interface (SPI)/Inter-integrated sound (I2S)
Up to two SPIs are able to communicate at up to 16 Mbits/s in slave and master modes in full-duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes.
The USARTs with synchronous capability can also be used as SPI master.
One standard I2S interfaces (multiplexed with SPI2) is available. It can operate in master or slave mode, and can be configured to operate with a 16-/32-bit resolution as input or output channels. Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When the
I2S interfaces is configured in master mode, the master clock can be output to the external
DAC/CODEC at 256 times the sampling frequency.
The SPIs can be served by the DMA controller.
for the differences between SPI1 and SPI2.
Hardware CRC calculation
I2S mode
TI mode
1. X = supported.
Table 14. SPI/I2S implementation
SPI features
(1)
SPI1
X
-
X
SPI2
X
X
X
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Functional overview STM32L083xx
The STM32L083xx embed a full-speed USB device peripheral compliant with the USB specification version 2.0. The internal USB PHY supports USB FS signaling, embedded DP pull-up and also battery charging detection according to Battery Charging Specification
Revision 1.2. The USB interface implements a full-speed (12 Mbit/s) function interface with added support for USB 2.0 Link Power Management. It has software-configurable endpoint setting with packet memory up to 1 Kbyte and suspend/resume support. It requires a precise 48 MHz clock which can be generated from the internal main PLL (the clock source must use a HSE crystal oscillator) or by the internal 48 MHz oscillator in automatic trimming mode. The synchronization for this oscillator can be taken from the USB data stream itself
(SOF signalization) which allows crystal-less operation.
The STM32L083xx embed a special block which allows automatic trimming of the internal
48 MHz oscillator to guarantee its optimal accuracy over the whole device operational range. This automatic trimming is based on the external synchronization signal, which could be either derived from USB SOF signalization, from LSE oscillator, from an external signal on CRS_SYNC pin or generated by user software. For faster lock-in during startup it is also possible to combine automatic trimming with manual trimming action.
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.
3.22 Serial wire debug port (SW-DP)
An Arm SW-DP interface is provided to allow a serial wire debugging tool to be connected to the MCU.
DS10671 Rev 5
STM32L083xx Pin descriptions
Figure 3. STM32L083xx LQFP100 pinout
VDD VS PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA
PE2
PE3
PE4
PE5
PE6
V LCD
PC13
PC14
-OSC32_IN
PC1
5-OSC32_OUT
PH9
PH10
PH0
-OSC_IN
PH1
-OSC_OUT
NR
ST
PC0
PC1
PC2
PC3
VSSA
VREF
-
VREF+
VDDA
PA0
PA1
PA2
13
14
15
16
9
10
11
12
7
8
5
6
3
4
1
2
21
22
23
24
25
17
18
19
20
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
71
70
VDD
69
75
74
73
72
LQFP100
56
55
54
53
60
59
58
57
52
51
64
63
62
61
68
67
66
65
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
PD13
PD12
PD11
PD10
PD9
PD8
PB 15
PB 14
PB 13
PB 12
VDD
_USB
VSS
VDD
PA13
PA12
PA 11
PA10
PA
9
PA8
PC9
PC8
PC7
PC6
PD15
PD14
VDD PA PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE
MSv35413V2
1. The above figure shows the package top view.
2. The I/O pins supplied by VDD_USB are shown in grey.
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Pin descriptions
Figure 4. STM32L083xx UFBGA100 ballout
1 2 3 4 5 6 7 8 9 1 0 11 1 2
PE3 PE1 PB8 BOOT0 PD7 PD5 PB4 PB3 PA15 PA14 PA13 PA12 A
B PE4
PE2 PB9 PB7 PB6
H
J
C PC13 PE5 PE0
D
E
F
G
PC14-
OSC32
_IN
PC15-
PE6 VSS
OSC32
_OUT
VLCD VSS
PH0-
OSC_IN
PH1-
OSC_
OUT
PH9
PH10
VDD PB5
PC0 NRST VDD
VSSA PC1 PC2
PD6 PD4 PD3 PD1 PC12 PC10 PA11
PD2 PD0 PC11
PA9
PC8
PD15
PD12
VDD
PA8
PC7
VSS
VDD_
USB
PD14
PD11
PA10
PC9
PC6
VSS
VDD
PD13
PD10
K
L
M
VREF
-
PC3 PA2
VREF
+
PA0 PA3
VDDA PA1 PA4
PA5
PA6
PA7
PC4
PC5 PB2
PB0 PB1
PD9 PD8 PB15 PB14 PB13
PE8 PE10 PE12 PB10 PB11 PB12
PE7 PE9 PE11 PE13 PE14 PE15
STM32L083xx
MSv35414V3
1. The above figure shows the package top view.
2. The I/O pins supplied by VDD_USBare shown in grey.
DS10671 Rev 5
STM32L083xx
Figure 5. STM32L083xx LQFP64 pinout
Pin descriptions
V
LCD
PC13
PC14-OSC32_IN
PC15-OSC32_OUT
PH0 -OSC_IN
PH1-OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA
VDDA
PA0
PA1
PA2
4
5
1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
2 47
3 46
45
44
6 43
7 42
8 41
9
10
LQFP64
40
39
11
12
38
37
13 36
14 35
15 34
16
17 18 19 20 21 22 23 24 25 26 27 28
33
29 30 31 32
VDD_USB
VSS
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
PB15
PB14
PB13
PB12
MS31485V3
1. The above figure shows the package top view.
2. The I/O pins supplied by VDD_USB are shown in grey.
DS10671 Rev 5
57
Pin descriptions
A
B
C
D
E
Figure 6. STM32L083xx TFBGA64 ballout
1 2
PC14-
OSC32
_IN
PC15-
OSC32
_OUT
PC13
VLCD
PH0-
OSC_IN
VSS
PH1-
OSC_
OUT
VDD
NRST PC1
3
PB9
PB8
PB7
PB6
PC0
4
PB4
PB5
VSS
5
PB3
VDD VDD
6
PA15
BOOT
0
PD2 PC11
PC12 PA10
VSS VSS
VDD_
USB
7
PA14 PA13
PC10 PA12
PA9
PA8
PC7
8
PA11
PC9
PC8
F
G
H
VSSA PC2 PA2 PA5 PB0 PC6 PB15 PB14
VREF
+
PA0
VDDA PA1
PA3
PA4
PA6
PA7
PB1
PC4
PB2
PC5
PB10 PB13
PB11 PB12
STM32L083xx
MSv37829V2
1. The above figure shows the package top view.
2. the I/O pins supplied by VDD_USB are shown in grey.
DS10671 Rev 5
STM32L083xx
Figure 7. STM32L083xx LQFP48 pinout
Pin descriptions
V
LCD
PC13
PC14-OSC32_IN
PC15-OSC32_OUT
PH0-OSC_IN
PH1-OSC_OUT
NRST
VSSA
VDDA
PA0
PA1
PA2
2
3
1
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
4 33
5 32
6 LQFP48 31
7 30
8 29
9 28
10 27
11
12
13 14 15 16 17 18 19 20 21 22 23 24
26
25
VDD_USB
VSS
PA13
PA12
PA11
PA10
PA9
PA8
PB15
PB14
PB13
PB12
MS31484V3
1. The above figure shows the package top view.
2. The I/O pins supplied by VDD_USB are shown in grey.
Figure 8. STM32L083xx UFQFPN48
VLCD
PC13
PC14-OSC32_IN
PC15-OSC32_OUT
PH0-OSC_IN
PH1-OSC_OUT
NRST
VSSA
VDDA
PA0
PA1
PA2
5
6
7
1
2
3
4
8
9
10
11
12
UFQFPN48
32
31
30
36
35
34
33
29
28
27
26
25
VDD_USB
VSS
PA13
PA12
PA11
PA10
PA9
PA8
PB15
PB14
PB13
PB12
1. The above figure shows the package top view.
2. The I/O pins supplied by VDD_USB are shown in grey.
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Pin descriptions STM32L083xx
Table 15. Legend/abbreviations used in the pinout table
Name Abbreviation Definition
Pin name
Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name
Pin type
I/O structure
Notes
Pin functions
Alternate functions
Additional functions
I/O
FT
FTf
TC
Input / output pin
5 V tolerant I/O
5 V tolerant I/O, FM+ capable
Standard 3.3V I/O
B
RST
Dedicated BOOT0 pin
Bidirectional reset pin with embedded weak pull-up resistor
Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset.
Functions selected through GPIOx_AFR registers
Functions directly selected/enabled through peripheral registers
Pin number
Table 16. STM32L083xx pin definition
Pin name
(function after reset)
Alternate functions Additional functions
-
-
-
1
2
-
-
-
-
-
-
-
1 B2
-
-
2 A2
-
-
3
4
5
6
7
1
2
B2
A1
B1
C2
D2
E2
C1
PE2
PE3
PE4
PE5
PE6
VLCD
PC13
I/O FT LCD_SEG38, TIM3_ETR
I/O FT -
TIM22_CH1,
LCD_SEG39, TIM3_CH1
I/O FT TIM22_CH2, TIM3_CH2
-
-
I/O FT -
-
I/O FT TIM21_CH1, TIM3_CH3 -
I/O FT TIM21_CH2, TIM3_CH4 RTC_TAMP3/WKUP3
S -
RTC_TAMP1/RTC_TS/
RTC_OUT/WKUP2
DS10671 Rev 5
STM32L083xx
Pin number
Table 16. STM32L083xx pin definition (continued)
Pin descriptions
Pin name
(function after reset)
Alternate functions Additional functions
3
4
-
-
5
6
7
-
-
-
-
3
4
-
-
7
A1
B1
-
-
E1
8
9
10
5 C1 12
14
D1
E1
F2
11 G2
F1
6 D1 13 G1
H2
PC14-
OSC32_IN
(PC14)
I/O FT
PC15-
OSC32_OUT
(PC15)
I/O TC -
-
PH9
PH10
I/O FT -
I/O FT -
PH0-OSC_IN
(PH0)
I/O TC -
PH1-
OSC_OUT
(PH1)
NRST
I/O
I/O
TC
-
-
-
8
9
10
11
E3
E2
F2
-
15
16
17
18
H1
J2
J3
K2
PC0
PC1
PC2
PC3
-
-
USB_CRS_SYNC
-
-
-
I/O FTf -
I/O FTf -
I/O FTf -
I/O FT -
-
LPTIM1_IN1,
LCD_SEG18,
EVENTOUT,
TSC_G7_IO1,
LPUART1_RX,
I2C3_SCL
LPTIM1_OUT,
LCD_SEG19,
EVENTOUT,
TSC_G7_IO2,
LPUART1_TX,
I2C3_SDA
LPTIM1_IN2,
LCD_SEG20,
SPI2_MISO/I2S2_MCK,
TSC_G7_IO3
LPTIM1_ETR,
LCD_SEG21,
SPI2_MOSI/I2S2_SD,
TSC_G7_IO4
OSC32_IN
OSC32_OUT
-
-
OSC_IN
OSC_OUT
-
ADC_IN10
ADC_IN11
ADC_IN12
ADC_IN13
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Pin descriptions
Pin number
Table 16. STM32L083xx pin definition (continued)
STM32L083xx
Pin name
(function after reset)
Alternate functions Additional functions
10 14 G2 23 L2
11 15 H2 24 M2
12
13
-
-
8
-
-
9
12 F1 19
-
-
G1
20
21
J1
K1
L1
13 H1 22 M1
14
16
17
F3
G3
25
26
18 C2 27
19 D2 28
20 H3 29
K3
L3
E3
H3
M3
VSSA
VREF-
VREF+
VDDA
PA0
PA1
PA2
PA3
VSS
VDD
PA4
S
S
S
S
I/O
I/O
I/O
I/O
S
S
I/O
-
-
-
-
TC
FT
FT
FT
-
-
TC
-
-
-
-
-
-
-
-
-
-
(1)
-
-
-
-
-
-
-
TIM2_CH1,
TSC_G1_IO1,
USART2_CTS,
TIM2_ETR,
USART4_TX,
COMP1_OUT
-
COMP1_INM,
ADC_IN0,
RTC_TAMP2/WKUP1
EVENTOUT,
LCD_SEG0, TIM2_CH2,
TSC_G1_IO2,
USART2_RTS/
USART2_DE,
TIM21_ETR,
USART4_RX
COMP1_INP, ADC_IN1
TIM21_CH1,
LCD_SEG1, TIM2_CH3,
TSC_G1_IO3,
USART2_TX,
LPUART1_TX,
COMP2_OUT
COMP2_INM,
ADC_IN2
TIM21_CH2,
LCD_SEG2, TIM2_CH4,
TSC_G1_IO4,
USART2_RX,
LPUART1_RX
COMP2_INP, ADC_IN3
-
-
SPI1_NSS,
TSC_G2_IO1,
USART2_CK,
TIM22_ETR
COMP1_INM,
COMP2_INM,
ADC_IN4, DAC_OUT1
DS10671 Rev 5
STM32L083xx
Pin number
Table 16. STM32L083xx pin definition (continued)
Pin descriptions
Pin name
(function after reset)
Alternate functions Additional functions
15
16
17 23 H4 32 M4
-
-
18
24 H5 33 K5
25 H6 34 L5
26 F5 35 M5
19 27 G5 36 M6
20
21
22
28
F4
G4
G6
30
31
37
K4
L4
L6
38 M7
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PE7
I/O TC -
I/O FT -
I/O FT -
I/O FT -
I/O FT -
I/O FT -
I/O FT -
I/O FT -
I/O FT -
SPI1_SCK, TIM2_ETR,
TSC_G2_IO2,
TIM2_CH1
SPI1_MISO,
LCD_SEG3, TIM3_CH1,
TSC_G2_IO3,
LPUART1_CTS,
TIM22_CH1,
EVENTOUT,
COMP1_OUT
SPI1_MOSI,
LCD_SEG4, TIM3_CH2,
TSC_G2_IO4,
TIM22_CH2,
EVENTOUT,
COMP2_OUT
EVENTOUT,
LCD_SEG22,
LPUART1_TX
LCD_SEG23,
LPUART1_RX,
TSC_G3_IO1
EVENTOUT,
LCD_SEG5, TIM3_CH3,
TSC_G3_IO2
LCD_SEG6, TIM3_CH4,
TSC_G3_IO3,
LPUART1_RTS/
LPUART1_DE
LPTIM1_OUT,
TSC_G3_IO4,
I2C3_SMBA
LCD_SEG45,
USART5_CK/
USART5_RTS/
USART5_DE
COMP1_INM,
COMP2_INM,
ADC_IN5, DAC_OUT2
ADC_IN6
ADC_IN7
ADC_IN14
ADC_IN15
LCD_VLCD3,
ADC_IN8, VREF_OUT
ADC_IN9, VREF_OUT
LCD_VLCD2
-
DS10671 Rev 5
57
Pin descriptions
Pin number
Table 16. STM32L083xx pin definition (continued)
STM32L083xx
Pin name
(function after reset)
Alternate functions Additional functions
-
-
-
-
-
39
40
L7
M8
41 L8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
42 M9
43 L9
44 M10
45 M11
46 M12
21
22
23
24
29
30
31
32
G7
H7
D6
E5
47
48
49
50
L10
L11
F12
G12
PE10
PE11
PE12
PE13
PE14
PE15
PE8
PE9
PB10
PB11
VSS
VDD
I/O
I/O
I/O
I/O
I/O
S
S
FT
FT
FT
FT
FT
-
-
-
-
-
-
-
LCD_SEG46,
USART4_TX
TIM2_CH1,
LCD_SEG47,
TIM2_ETR,
USART4_RX
TIM2_CH2,
LCD_SEG40,
USART5_TX
I/O FT -
TIM2_CH3,
USART5_RX
I/O FT TIM2_CH4, SPI1_NSS
I/O FT LCD_SEG41, SPI1_SCK
I/O FT -
LCD_SEG42,
SPI1_MISO
I/O FT -
LCD_SEG43,
SPI1_MOSI
LCD_SEG10,
TIM2_CH3, TSC_SYNC,
LPUART1_TX,
SPI2_SCK, I2C2_SCL,
LPUART1_RX
EVENTOUT,
LCD_SEG11,
TIM2_CH4,
TSC_G6_IO1,
LPUART1_RX,
I2C2_SDA,
LPUART1_TX
-
-
-
-
-
-
-
-
LCD_VLCD1
LCD_VLCD3
-
-
-
DS10671 Rev 5
STM32L083xx
Pin number
Table 16. STM32L083xx pin definition (continued)
Pin descriptions
Pin name
(function after reset)
Alternate functions Additional functions
25
26
27
33
34
35
H8
G8
F8
51
52
53
L12
K12
K11
28 36 F7 54 K10
-
-
-
-
-
-
-
-
-
-
-
55 K9
56 K8
57 J12
58 J11
-
-
-
-
-
-
-
-
59 J10
60 H12
61 H11
PB12
PB13
PB14
PB15
PD8
PD9
PD10
PD11
PD12
PD13
PD14
I/O FT -
I/O FTf -
I/O FTf -
I/O FT -
I/O FT -
I/O FT -
I/O FT -
I/O FT -
I/O FT -
I/O FT -
I/O FT -
SPI2_NSS/I2S2_WS,
LCD_SEG12,
LPUART1_RTS/
LPUART1_DE,
TSC_G6_IO2,
I2C2_SMBA,
EVENTOUT
SPI2_SCK/I2S2_CK,
LCD_SEG13, MCO,
TSC_G6_IO3,
LPUART1_CTS,
I2C2_SCL, TIM21_CH1
SPI2_MISO/I2S2_MCK,
LCD_SEG14, RTC_OUT,
TSC_G6_IO4,
LPUART1_RTS/
LPUART1_DE,
I2C2_SDA, TIM21_CH2
SPI2_MOSI/I2S2_SD,
LCD_SEG15,
RTC_REFIN
LPUART1_TX,
LCD_SEG28
LPUART1_RX,
LCD_SEG29
LCD_SEG30
LPUART1_CTS,
LCD_SEG31
LPUART1_RTS/
LPUART1_DE,
LCD_SEG32
LCD_SEG33
LCD_SEG34
LCD_VLCD1
-
-
-
-
-
-
-
-
-
-
DS10671 Rev 5
57
Pin descriptions
Pin number
Table 16. STM32L083xx pin definition (continued)
STM32L083xx
Pin name
(function after reset)
Alternate functions Additional functions
-
-
-
62 H10
37
38
39
F6
E7
E8
63
64
65
E12
E11
E10
40 D8 66 D12
29
30 42 C7 68 D10
31 43 C6 69 C12
32
41
44
D7
C8
67
70
D11
B12
PD15
PC6
PC7
PC8
PC9
PA8
PA9
PA10
PA11
I/O
I/O
I/O
I/O
I/O FTf
I/O FTf
I/O FTf
I/O FTf
I/O
FT
FT
FT
FT
FT
-
-
-
-
-
-
-
-
(2)
USB_CRS_SYNC,
LCD_SEG35
TIM22_CH1,
LCD_SEG24,
TIM3_CH1,
TSC_G8_IO1
TIM22_CH2,
LCD_SEG25,
TIM3_CH2,
TSC_G8_IO2
TIM22_ETR,
LCD_SEG26,
TIM3_CH3,
TSC_G8_IO3
TIM21_ETR,
LCD_SEG27,
USB_NOE/TIM3_CH4,
TSC_G8_IO4,
I2C3_SDA
MCO, LCD_COM0,
USB_CRS_SYNC,
EVENTOUT,
USART1_CK, I2C3_SCL
MCO, LCD_COM1,
TSC_G4_IO1,
USART1_TX, I2C1_SCL,
I2C3_SMBA
LCD_COM2,
TSC_G4_IO2,
USART1_RX, I2C1_SDA
SPI1_MISO,
EVENTOUT,
TSC_G4_IO3,
USART1_CTS,
COMP1_OUT
-
-
-
-
-
-
-
-
USB_DM
DS10671 Rev 5
STM32L083xx
Pin number
Table 16. STM32L083xx pin definition (continued)
Pin descriptions
Pin name
(function after reset)
Alternate functions Additional functions
33
34 46 A8 72 A11 PA13
73 C11 VDD
35 47 D5 74 F11 VSS
36 48 E6 75 G11 VDD_USB
37 49 A7 76 A10 PA14
38
-
-
-
-
45
50
51
52
53
-
B8
A6
B7
B6
C5
-
71
77
78
79
80
81
A12
A9
B11
C10
B10
C9
PA12
PA15
PC10
PC11
PC12
PD0
I/O
I/O
S
S
S
I/O
I/O
I/O
I/O
I/O
I/O
FT
FT
FT
FT
FT
FT
FT
FT
(2)
-
-
-
-
-
-
-
-
-
-
SPI1_MOSI,
EVENTOUT,
TSC_G4_IO4,
USART1_RTS/
USART1_DE,
COMP2_OUT
SWDIO, USB_NOE,
LPUART1_RX
-
-
-
SWCLK, USART2_TX,
LPUART1_TX
SPI1_NSS,
LCD_SEG17,
TIM2_ETR, EVENTOUT,
USART2_RX,
TIM2_CH1,
USART4_RTS/
USART4_DE
LPUART1_TX,
LCD_COM4/LCD_SEG2
8/LCD_SEG48,
USART4_TX
LPUART1_RX,
LCD_COM5/LCD_SEG2
9/LCD_SEG49,
USART4_RX
LCD_COM6/LCD_SEG3
0/LCD_SEG50,
USART5_TX,
USART4_CK
TIM21_CH1,
SPI2_NSS/I2S2_WS
USB_DP
-
-
-
-
-
-
-
-
-
-
DS10671 Rev 5
57
Pin descriptions
Pin number
Table 16. STM32L083xx pin definition (continued)
STM32L083xx
Pin name
(function after reset)
Alternate functions Additional functions
-
-
-
-
-
-
54 B5 83 C8
39
40
-
-
-
-
-
-
55
56
-
-
-
-
-
-
A5
A4
82
84
B9
B8
85 B7
86
87
88
A6
B6
A5
89
90
A8
A7
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PB3
PB4
I/O FT -
I/O FT -
I/O FT -
I/O FT -
I/O FT -
I/O FT -
I/O FT -
I/O FT -
I/O FTf -
SPI2_SCK/I2S2_CK
LPUART1_RTS/
LPUART1_DE,
LCD_COM7/LCD_SEG3
1/LCD_SEG51,
TIM3_ETR,
USART5_RX
USART2_CTS,
LCD_SEG44,
SPI2_MISO/I2S2_MCK
USART2_RTS/
USART2_DE,
SPI2_MOSI/I2S2_SD
USART2_TX
USART2_RX
USART2_CK,
TIM21_CH2
SPI1_SCK, LCD_SEG7,
TIM2_CH2,
TSC_G5_IO1,
EVENTOUT,
USART1_RTS/
USART1_DE,
USART5_TX
SPI1_MISO,
LCD_SEG8, TIM3_CH1,
TSC_G5_IO2,
TIM22_CH1,
USART1_CTS,
USART5_RX, I2C3_SDA
-
-
-
-
-
-
-
COMP2_INM
COMP2_INP
DS10671 Rev 5
STM32L083xx
Pin number
Table 16. STM32L083xx pin definition (continued)
Pin descriptions
Pin name
(function after reset)
Alternate functions Additional functions
41
42
43
44
45
46
-
-
57
58
59
60
61
62
-
-
C4
D3
C3
B4
B3
A3
-
-
91
92
93
94
95
96
97
98
C5
B5
B4
A4
A3
B3
C3
A2
47 63 D4 99 D3
48 64 E4 100 C4
PB5
PB6
PB7
BOOT0
PB8
PB9
PE0
PE1
VSS
VDD
I/O
I
I/O
I/O
S
S
FT
I/O FTf
I/O FTf
I/O FTf
I/O FTf
FT
FT
-
-
-
-
-
-
-
-
-
-
-
-
SPI1_MOSI,
LCD_SEG9,
LPTIM1_IN1,
I2C1_SMBA,
TIM3_CH2/TIM22_CH2,
USART1_CK,
USART5_CK,
USART5_RTS/
USART5_DE
USART1_TX, I2C1_SCL,
LPTIM1_ETR,
TSC_G5_IO3
USART1_RX,
I2C1_SDA, LPTIM1_IN2,
TSC_G5_IO4,
USART4_CTS
-
LCD_SEG16,
TSC_SYNC, I2C1_SCL
LCD_COM3,
EVENTOUT, I2C1_SDA,
SPI2_NSS/I2S2_WS
LCD_SEG36,
EVENTOUT
LCD_SEG37,
EVENTOUT
-
-
COMP2_INP
COMP2_INP
COMP2_INP, PVD_IN
1. PA4 offers a reduced touch sensing sensitivity. It is thus recommended to use it as sampling capacitor I/O.
2. These pins are powered by VDD_USB. For all characteristics that refer to V
DD
, V
DD_USB
must be used instead.
-
-
-
-
-
-
-
DS10671 Rev 5
57
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
AF0
EVENTOUT
TIM21_CH1
TIM21_CH2
SPI1_NSS
SPI1_SCK
SPI1_MISO
SPI1_MOSI
MCO
MCO
-
SPI1_MISO
SPI1_MOSI
SWDIO
SWCLK
SPI1_NSS
AF1
LCD_SEG0
LCD_SEG1
LCD_SEG2
-
-
LCD_SEG3
LCD_SEG4
LCD_COM0
LCD_COM1
LCD_COM2
-
-
-
-
LCD_SEG17
Table 17. Alternate functions port A
AF2
Port
PA0
SPI1/SPI2/I2S2/
USART1/2/
LPUART1/USB/
LPTIM1/TSC/
TIM2/21/22/
EVENTOUT/
SYS_AF
SPI1/SPI2/I2S2/
I2C1/LCD/
TIM2/21
SPI1/SPI2/I2S2/
LPUART1/
USART5/USB/L
PTIM1/TIM2/3/E
VENTOUT/
SYS_AF
TIM2_CH1
TIM2_CH2
TIM2_CH3
TIM2_CH4
-
TIM2_ETR
TIM3_CH1
TIM3_CH2
USB_CRS_
SYNC
-
-
EVENTOUT
EVENTOUT
USB_NOE
-
TIM2_ETR
AF3
I2C1/TSC/
EVENTOUT
AF4 AF5
TSC_G1_IO1 USART2_CTS
TSC_G1_IO2
TSC_G1_IO3
USART2_RTS/
USART2_DE
USART2_TX
TIM2_ETR
TIM21_ETR
TSC_G1_IO4
TSC_G2_IO1
USART2_RX
USART2_CK
-
-
TIM22_ETR
TSC_G2_IO2 TIM2_CH1
TSC_G2_IO3 LPUART1_CTS TIM22_CH1
TSC_G2_IO4 TIM22_CH2
EVENTOUT
TSC_G4_IO1
TSC_G4_IO4
USART1_TX
TSC_G4_IO2 USART1_RX
TSC_G4_IO3 USART1_CTS
USART1_RTS/
USART1_DE
-
-
USART2_TX
EVENTOUT
AF6
I2C1/USART1/2
/LPUART1/
TIM3/22/
EVENTOUT
SPI2/I2S2/I2C2/
USART1/
TIM2/21/22
I2C1/2/
LPUART1/
USART4/
UASRT5/TIM21
/
EVENTOUT
I2C3/LPUART1/
COMP1/2/
TIM3
USART1_CK
USART2_RX
-
-
-
-
-
-
-
TIM2_CH1
USART4_TX
USART4_RX
LPUART1_TX COMP2_OUT
LPUART1_RX
-
-
-
-
EVENTOUT
EVENTOUT
-
COMP1_OUT
COMP2_OUT
-
I2C1_SCL
I2C1_SDA
-
-
LPUART1_RX
LPUART1_TX
USART4_RTS/
USART4_DE
AF7
COMP1_OUT
-
-
-
-
I2C3_SCL
I2C3_SMBA
-
COMP1_OUT
COMP2_OUT
Port
PB0
PB1
PB2
PB3
PB4
PB5
AF0
SPI1/SPI2/I2S2/
USART1/2/
LPUART1/USB/
LPTIM1/TSC/
TIM2/21/22/
EVENTOUT/
SYS_AF
EVENTOUT
-
-
SPI1_SCK
SPI1_MISO
SPI1_MOSI
AF1
Table 18. Alternate functions port B
AF2 AF3
SPI1/SPI2/I2S2/I
2C1/LCD/
TIM2/21
SPI1/SPI2/I2S2/
LPUART1/
USART5/USB/L
PTIM1/TIM2/3/E
VENTOUT/
SYS_AF
I2C1/TSC/
EVENTOUT
LCD_SEG5
LCD_SEG6
-
LCD_SEG7
LCD_SEG8
TIM3_CH3
TIM3_CH4
LPTIM1_OUT
TIM2_CH2
TIM3_CH1
TSC_G3_IO2
TSC_G3_IO3
TSC_G3_IO4
TSC_G5_IO1
TSC_G5_IO2
AF4
I2C1/USART1/2/
LPUART1/
TIM3/22/
EVENTOUT
LCD_SEG9 LPTIM1_IN1 I2C1_SMBA
PB6
PB7
PB8
PB9
PB10
PB11
USART1_TX
USART1_RX
-
-
-
EVENTOUT
PB12 SPI2_NSS/I2S2_WS
PB13 SPI2_SCK/I2S2_CK
PB14
SPI2_MISO/
I2S2_MCK
PB15
SPI2_MOSI/
I2S2_SD
LCD_SEG15
I2C1_SCL
I2C1_SDA
LCD_SEG16
LCD_COM3
LCD_SEG10
LCD_SEG11
LCD_SEG12
LCD_SEG13
LCD_SEG14
LPTIM1_ETR
LPTIM1_IN2
-
TSC_G5_IO3
TSC_G5_IO4
TSC_SYNC
EVENTOUT -
TIM2_CH3
TIM2_CH4
LPUART1_RTS/
LPUART1_DE
MCO
TSC_SYNC
TSC_G6_IO1
TSC_G6_IO2
TSC_G6_IO3
RTC_OUT TSC_G6_IO4
RTC_REFIN -
-
LPUART1_RTS/
LPUART1_DE
-
EVENTOUT
TIM22_CH1
TIM3_CH2/
TIM22_CH2
-
-
I2C1_SCL
I2C1_SDA
LPUART1_TX
LPUART1_RX
LPUART1_CTS
LPUART1_RTS/
LPUART1_DE
-
AF5 AF6 AF7
SPI2/I2S2/I2C2/
USART1/
TIM2/21/22
I2C1/2/
LPUART1/
USART4/
UASRT5/TIM21/
EVENTOUT
I2C3/LPUART1/
COMP1/2/
TIM3
-
-
-
USART1_RTS/
USART1_DE
USART1_CTS
USART1_CK
-
-
-
SPI2_NSS/
I2S2_WS
SPI2_SCK
-
I2C2_SMBA
I2C2_SCL
I2C2_SDA
-
-
-
-
USART5_TX
USART5_RX
USART5_CK,
USART5_RTS/
USART5_DE
-
USART4_CTS
-
-
I2C2_SCL
I2C2_SDA
EVENTOUT
TIM21_CH1
TIM21_CH2
-
-
-
I2C3_SMBA
-
I2C3_SDA
-
-
-
-
-
LPUART1_RX
LPUART1_TX
-
-
-
-
Port
PC0
PC1
PC2
PC10
PC11
AF0
SPI1/SPI2/I2S2/
USART1/2/
LPUART1/USB/
LPTIM1/TSC/
TIM2/21/22/
EVENTOUT/
SYS_AF
LPTIM1_IN1
LPTIM1_OUT
LPTIM1_IN2
LPTIM1_ETR
EVENTOUT
TIM22_CH1
TIM22_CH2
TIM22_ETR
TIM21_ETR
LPUART1_TX
LPUART1_RX
AF1
SPI1/SPI2/I2S2/I2C1/
LCD/
TIM2/21
Table 19. Alternate functions port C
AF2
SPI1/SPI2/I2S2/
LPUART1/
USART5/USB/
LPTIM1/TIM2/3
/EVENTOUT/SYS_AF
AF3
I2C1/TSC/
EVENTOUT
LCD_SEG18
LCD_SEG19
LCD_SEG20
LCD_SEG21
LCD_SEG22
LCD_SEG23
LCD_SEG24
LCD_SEG25
LCD_SEG26
LCD_SEG27
LCD_COM4/LCD_SEG
28/LCD_SEG48
LCD_COM5/LCD_SEG
29/LCD_SEG49
LCD_COM6/LCD_SEG
30/LCD_SEG50
EVENTOUT
EVENTOUT
SPI2_MISO/
I2S2_MCK
SPI2_MOSI/
I2S2_SD
TSC_G7_IO1
TSC_G7_IO2
TSC_G7_IO3
TSC_G7_IO4
LPUART1_TX
LPUART1_RX
TIM3_CH1
TIM3_CH2
TIM3_CH3
TSC_G3_IO1
TSC_G8_IO1
TSC_G8_IO2
TSC_G8_IO3
USB_NOE/TIM3_CH4 TSC_G8_IO4
USART5_TX
AF4
I2C1/USART1/2/
LPUART1/
TIM3/22/
EVENTOUT
PC12
PC13
PC14
PC15
PC3
PC4
PC5
PC6
PC7
PC8
PC9
AF5 AF6
SPI2/I2S2
/I2C2/
USART1/
TIM2/21/22
I2C1/2/
LPUART1/
USART4/
UASRT5/TIM21/E
VENTOUT
I2C3/LPUART1/
COMP1/2/
TIM3
LPUART1_RX
LPUART1_TX
USART4_TX
USART4_RX
USART4_CK
AF7
I2C3_SCL
I2C3_SDA
I2C3_SDA
Port
PD0
PD1
PD2
AF0
SPI1/SPI2/I2S2/
USART1/2/
LPUART1/USB/
LPTIM1/TSC/
TIM2/21/22/
EVENTOUT/
SYS_AF
TIM21_CH1
-
LPUART1_RTS/
LPUART1_DE
AF1
SPI1/SPI2/I2S2/I2C1/
LCD/TIM2/21
SPI2_NSS/I2S2_WS
SPI2_SCK/I2S2_CK
LCD_COM7/
LCD_SEG31/
LCD_SEG51
LCD_SEG44 PD3 USART2_CTS
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD4
PD12
USART2_RTS/
USART2_DE
USART2_TX
USART2_RX
USART2_CK
LPUART1_TX
LPUART1_RX
-
LPUART1_CTS
LPUART1_RTS/
LPUART1_DE
PD13
PD14
-
-
PD15 USB_CRS_SYNC
SPI2_MOSI/I2S2_SD
-
-
TIM21_CH2
LCD_SEG28
LCD_SEG29
LCD_SEG30
LCD_SEG31
LCD_SEG32
LCD_SEG33
LCD_SEG34
LCD_SEG35
Table 20. Alternate functions port D
AF2
SPI1/SPI2/I2S2/
LPUART1/
USART5/USB/
LPTIM1/TIM2/3
/EVENTOUT/
SYS_AF
-
-
TIM3_ETR
SPI2_MISO/
I2S2_MCK
-
-
-
-
-
-
-
-
-
-
-
-
AF3
I2C1/TSC/
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AF4
I2C1/USART1/2/
LPUART1/
TIM3/22/
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AF5 AF6 AF7
SPI2/I2S2
/I2C2/
USART1/
TIM2/21/22
I2C1/2/
LPUART1/
USART4/
UASRT5/TIM21/E
VENTOUT
I2C3/LPUART1/
COMP1/2/TIM3
-
-
-
-
-
USART5_RX
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
Port
PE0
PE1
PE2
PE3
PE4
PE5
PE6
AF0 AF1
Table 21. Alternate functions port E
AF2
SPI1/SPI2/I2S2/
USART1/2/
LPUART1/USB/
LPTIM1/TSC/
TIM2/21/22/
EVENTOUT/
SYS_AF
SPI1/SPI2/I2S2/I2C1
/LCD/TIM2/21
-
-
-
TIM22_CH1
TIM22_CH2
TIM21_CH1
TIM21_CH2
LCD_SEG36
LCD_SEG37
LCD_SEG38
LCD_SEG39
-
-
-
SPI1/SPI2/I2S2/
LPUART1/
USART5/USB/
LPTIM1/TIM2/3
/EVENTOUT/
SYS_AF
EVENTOUT
EVENTOUT
TIM3_ETR
TIM3_CH1
TIM3_CH2
TIM3_CH3
TIM3_CH4
AF3
I2C1/TSC/
EVENTOUT
-
-
-
-
-
-
-
AF4
I2C1/USART1/2/
LPUART1/
TIM3/22/
EVENTOUT
-
-
-
-
-
-
-
AF5
-
-
-
-
-
-
-
AF6
SPI2/I2S2
/I2C2/
USART1/
TIM2/21/22
I2C1/2/
LPUART1/
USART4/
UASRT5/TIM21/
EVENTOUT
PE7 -
-
TIM2_CH1
TIM2_CH2
TIM2_CH3
TIM2_CH4
-
-
-
LCD_SEG45
LCD_SEG46
LCD_SEG47
LCD_SEG40
-
-
LCD_SEG41
LCD_SEG42
LCD_SEG43
-
-
TIM2_ETR
-
-
SPI1_NSS
SPI1_SCK
SPI1_MISO
SPI1_MOSI
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
USART5_CK,
USART5_RTS/
USART5_DE
USART4_TX
USART4_RX
USART5_TX
USART5_RX
-
-
-
-
AF7
I2C3/LPUART1/
COMP1/2/TIM3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Port
PH0
PH1
AF0
SPI1/SPI2/
I2S2/USART1/2/
LPUART1/USB/
LPTIM1/TSC/
TIM2/21/22/
EVENTOUT/
SYS_AF
USB_CRS_SYNC
-
AF1
-
-
Table 22. Alternate functions port H
AF2
SPI1/SPI2/I2S2
/I2C1/LCD/TIM2/21
SPI1/SPI2/I2S2/
LPUART1/
USART5/USB/
LPTIM1/TIM2/3/
EVENTOUT/
SYS_AF
-
-
AF3
I2C1/TSC/
EVENTOUT
-
-
AF4
-
-
AF5
I2C1/USART1/2/
LPUART1/
TIM3/22/
EVENTOUT
SPI2/I2S2/I2C2/
USART1/
TIM2/21/22
-
-
AF6
I2C1/2/
LPUART1/
USART4/
UASRT5/TIM21/
EVENTOUT
I2C3/
LPUART1/
COMP1/2/
TIM3
-
-
AF7
-
-
Memory mapping STM32L083xx
Refer to the product line reference manual for details on the memory mapping as well as the boundary addresses for all peripherals.
DS10671 Rev 5
STM32L083xx Electrical characteristics
6.1.1
Unless otherwise specified, all voltages are referenced to V
SS
.
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T
A the selected temperature range).
= 25 °C and T
A
= T
A max (given by
Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3 σ ).
Unless otherwise specified, typical data are based on T
A
= 25 °C, V
DD
1.65 V tested.
≤ V
DD
= 3.6 V (for the
≤ 3.6 V voltage range). They are given only as design guidelines and are not
Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2 σ )
.
Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.
6.1.5
The loading conditions used for pin parameter measurement are shown in
.
Pin input voltage
The input voltage measurement on a pin of the device is described in
Figure 9. Pin loading conditions Figure 10. Pin input voltage
MCU pin
MCU pin
C = 50 pF
V
IN ai17851c ai17852c
DS10671 Rev 5
123
Electrical characteristics
6.1.6 Power supply scheme
Figure 11. Power supply scheme
STM32L083xx
GP I/Os
100 nF
+ 1 μF
N × 100 nF
+ 1 × 10 μF
V
DD
V
DD
V
SS
V
DDA
V
DDA
V
REF
V
REF+
100 nF
+ 1 μF
V
REF-
V
SSA
V
LCD
V
SS
V
SS
V
DD_USB
Standby-power circuitry
(OSC32,RTC,Wake-up logic, RTC backup registers)
OUT
IN
IO
Logic
Kernel logic
(CPU,
Digital &
Memories)
Regulator
ADC/
DAC
LCD
USB transceiver
Analog:
RC,PLL,COMP,
….
MSv33790V1
DS10671 Rev 5
STM32L083xx
6.1.7
Electrical characteristics
Optional LCD power supply scheme
Figure 12. Optional LCD power supply scheme
V
DD
VSEL
N x 100 nF
+ 1 x 10 μF
V
DD
Step-up
Converter
Option 1 V
LCD
100 nF
LCD
V
LCD
Option 2
C
EXT
V
SS
MSv33791V1
1. Option 1: LCD power supply is provided by a dedicated VLCD supply source, VSEL switch is open.
2. Option 2: LCD power supply is provided by the internal step-up converter, VSEL switch is closed, an external capacitance is needed for correct behavior of this converter.
Figure 13. Current consumption measurement scheme
VDDA
IDD
N × 100 nF
+ 1 × 10 μF
NxVDD
NxVSS
MSv34711V1
DS10671 Rev 5
123
Electrical characteristics
6.2 Absolute maximum ratings
STM32L083xx
Stresses above the absolute maximum ratings listed in
Table 23: Voltage characteristics
,
Table 24: Current characteristics
, and
Table 25: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 Qualification Standard. Extended mission profiles are available on demand.
Symbol
Table 23. Voltage characteristics
Definition Min Max Unit
|V
V
V
REF+
–V
DDA
V
|
|
DD
V
Δ
Δ
V
DDA
V
–V
IN
(2)
DD
-V
SS
SS
|
DDx
|
ESD(HBM)
|
External main supply voltage
(including V
DDA
, V
DD_USB
, V
DD
)
(1)
Input voltage on FT and FTf pins
Input voltage on TC pins
Input voltage on BOOT0
Input voltage on any other pin
Variations between different V
DDx power pins
Variations between any V
DDx and V pins
(3)
DDA
power
Variations between all different ground pins including V
REF-
pin
Allowed voltage difference for V
REF+
> V
DDA
Electrostatic discharge voltage
(human body model)
V
V
–0.3
SS
SS
V
V
SS
− 0.3
0.3
SS
− 0.3
-
-
-
-
−
4.0
V
DD
+4.0
4.0
V
DD
+ 4.0
4.0
50
300
50
0.4
1. All main power (V
DD
,V
DD_USB
, V ) and ground (V
SS
, V
SSA
) pins must always be connected to the
2. V
IN maximum must always be respected. Refer to
Table 24 for maximum allowed injected current values.
3. It is recommended to power V between V from V
DD
DD
and V
DDA
DDA
DD
and V
DDA from the same source. A maximum difference of 300 mV
DD_USB is independent
V mV
V
DS10671 Rev 5
STM32L083xx Electrical characteristics
Symbol
Σ I
Σ I
I
I
Σ I
VDD
(2)
VSS
(2)
VDD_USB
VDD(PIN)
VSS(PIN)
Table 24. Current characteristics
Ratings
Total current into sum of all V
DD
power lines (source)
(1)
Total current out of sum of all V
SS
ground lines (sink)
(1)
Total current into V
DD_USB
power lines (source)
Maximum current into each V
DD
power pin (source) (1)
Maximum current out of each V
SS
ground pin (sink)
(1)
Output current sunk by any I/O and control pin except FTf pins
Output current sunk by FTf pins
Max.
105
105
25
100
100
16
Unit
I
IO
Output current sourced by any I/O and control pin
Total output current sunk by sum of all IOs and control pins except PA11 and PA12
(2)
22
-16
90 mA
Σ I
IO(PIN)
Total output current sunk by PA11 and PA12 25
Total output current sourced by sum of all IOs and control pins
(2)
-90
I
INJ(PIN)
Σ I
INJ(PIN)
Injected current on FT, FTf, RST and B pins
Injected current on TC pin
Total injected current (sum of all I/O and control pins)
(5)
-5/+0
(3)
± 5 (4)
± 25
1. All main power (V , V
DDA
) and ground (V supply, in the permitted range.
SS
, V
SSA
) pins must always be connected to the external power
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count
LQFP packages.
3. Positive current injection is not possible on these I/Os. A negative injection is induced by V must never be exceeded. Refer to
for maximum allowed input voltage values.
IN
<V
SS
. I
INJ(PIN)
4. A positive injection is induced by V must never be exceeded. Refer to
Table 23: Voltage characteristics
for the maximum allowed input voltage values.
IN
> V
DD
while a negative injection is induced by V
IN
< V
SS
. I
INJ(PIN)
5. When several inputs are submitted to a current injection, the maximum Σ I positive and negative injected currents (instantaneous values).
INJ(PIN)
is the absolute sum of the
Symbol
T
STG
T
J
Table 25. Thermal characteristics
Ratings
Storage temperature range
Maximum junction temperature
Value
–65 to +150
150
Unit
°C
°C
DS10671 Rev 5
123
Electrical characteristics STM32L083xx
6.3.1 General operating conditions
Symbol f
HCLK f
PCLK1 f
PCLK2
V
DD
Parameter
Table 26. General operating conditions
Internal AHB clock frequency
Internal APB1 clock frequency
Internal APB2 clock frequency
Standard operating voltage
Conditions Min
-
-
-
BOR detector disabled
BOR detector enabled, at power-on 1.8
BOR detector disabled, after power-on 1.65
0
0
0
1.65
V
DDA
V
DDA
Analog operating voltage (DAC not used)
Analog operating voltage (all features)
Must be the same voltage as V
DD
Must be the same voltage as V
DD
(1)
1.65
1.8
V
DD_
USB
V
IN
P
D
Standard operating voltage, USB domain
(2)
Input voltage on FT, FTf and RST pins
(3)
Input voltage on BOOT0 pin
Input voltage on TC pin
Power dissipation at T
A
= 85 °C
(range 6) or T
A
= 105 °C (range 7)
(4)
Power dissipation at T
A
= 125 °C
Max
3.6
3.6
USB peripheral used 3.0
3.6
USB peripheral not used
2.0 V ≤
DD
≤ 3.6 V
1.65 V ≤
DD
2.0 V
-
0
-0.3
-0.3
3.6
5.5
5.2
0 5.5
-0.3
V
DD
+0.3
UFBGA100 351
LQFP100 -
TFBGA64 -
LQFP64 -
LQFP48 -
UFQFPN48
UFBGA100 -
LQFP100 -
TFBGA64 -
LQFP64 -
122
78
109
LQFP48 93
UFQFPN48 -179
488
313
435
370
714
88
32
32
32
3.6
3.6
3.6
Unit
MHz
V
V
V
V
V mW
DS10671 Rev 5
STM32L083xx Electrical characteristics
Symbol
Table 26. General operating conditions (continued)
Parameter Conditions Min Max Unit
T
A
Temperature range
Maximum power dissipation (range 6)
Maximum power dissipation (range 7)
–40
–40
85
105
Maximum power dissipation (range 3) –40 125
T
J
–40
–40
–40
105
125
130
°C
Junction temperature range (range 6) -40 °C ≤
A
85 °
Junction temperature range (range 7) -40 °C ≤
A
105 °C
Junction temperature range (range 3) -40 °C ≤
A
125 °C
1. It is recommended to power V
DD
and V
DDA
from the same source. A maximum difference of 300 mV between V can be tolerated during power-up and normal operation.
DD
and V
DDA
2. V
- When V
- When V
must respect the following conditions:
DD
DD
is powered-on (V
is powered-down (V
- In operating mode, V
- If the USB is not used, V
DD
< V
DD
DD_USB
< V
), V
DD_min
), V
DD_USB
must range from V
should be always lower than V
should be always lower than V
DD.
DD_min DD_max
DD.
- If the USB is not used and PA11/PA12 are not used as standard I/Os, VDD_USB must be connected to a V supply voltage (VDD_USB must not be left floating).
to be able to use PA11 and PA12 as standard I/Os.
SS
or V
DD
power
3. To sustain a voltage higher than V
DD
+0.3V, the internal pull-up/pull-down resistors must be disabled.
4. If T
A
is lower, higher P
D
values are allowed as long as T
J
does not exceed T
J
max (see Table 90: Thermal characteristics on
DS10671 Rev 5
123
Electrical characteristics STM32L083xx
6.3.2 Embedded reset and power control block characteristics
The parameters given in the following table are derived from the tests performed under the
ambient temperature condition summarized in Table 26
.
Symbol t
VDD
(1)
T
RSTTEMPO
(1)
V
POR/PDR
V
BOR0
V
BOR1
Table 27. Embedded reset and power control block characteristics
Parameter Conditions Min Typ
V
DD
rise time rate
V
DD
fall time rate
Reset temporization
Power-on/power down reset threshold
BOR detector enabled
BOR detector disabled
BOR detector enabled
BOR detector disabled
V
DD
rising, BOR enabled
V
DD
rising, BOR disabled
(2)
Falling edge
Rising edge
Falling edge
0
0
-
0
20
0.4
1
-
-
2
-
-
Max Unit
∞
1000
µs/V
∞
1000
3.3
ms
0.7
1.6
1.5
1.65
1.3
1.5
1.65
1.67
1.7
1.74
Brown-out reset threshold 0
Rising edge
Falling edge
1.69
1.76
1.8
1.87
1.93
1.97
Brown-out reset threshold 1
Rising edge 1.96
2.03
2.07
V
BOR2
V
BOR3
V
BOR4
V
PVD0
V
PVD1
V
PVD2
V
PVD3
V
PVD4
V
PVD5
Brown-out reset threshold 2
Brown-out reset threshold 3
Brown-out reset threshold 4
Programmable voltage detector threshold 0
PVD threshold 1
PVD threshold 2
PVD threshold 3
PVD threshold 4
PVD threshold 5
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
2.22
2.30
2.35
2.31
2.41
2.44
2.45
2.55
2.6
2.54
2.66
2.7
2.68
2.8
2.85
2.78
2.9
2.95
1.8
1.85
1.88
1.88
1.94
1.99
1.98
2.04
2.09
2.08
2.14
2.18
2.20
2.24
2.28
2.28
2.34
2.38
2.39
2.44
2.48
2.47
2.54
2.58
2.57
2.64
2.69
2.68
2.74
2.79
2.77
2.83
2.88
2.87
2.94
2.99
V
DS10671 Rev 5
STM32L083xx Electrical characteristics
Table 27. Embedded reset and power control block characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit
V
V
PVD6 hyst
PVD threshold 6
Hysteresis voltage
Falling edge
Rising edge
BOR0 threshold
All BOR and PVD thresholds excepting BOR0
2.97
3.08
-
-
3.05
3.15
40
100
-
-
3.09
3.20
V mV
1. Guaranteed by characterization results.
2. Valid for device version without BOR at power up. Please see option "D" in Ordering information scheme for more details.
The parameters given in
Table 29 are based on characterization results, unless otherwise
specified.
Table 28. Embedded internal reference voltage calibration values
Calibration value name Description Memory address
VREFINT_CAL
Raw data acquired at temperature of 25 °C
V
DDA
= 3 V
0x1FF8 0078 - 0x1FF8 0079
Symbol
V
REFINT out
(2)
T
VREFINT
V
VREF_MEAS
A
VREF_MEAS
T
Coeff
(4)
A
Coeff
(4)
V
DDCoeff
(4)
T
S_vrefint
(4)(5)
T
ADC_BUF
(4)
I
BUF_ADC
(4)
I
VREF_OUT
(4)
C
VREF_OUT
(4)
Table 29. Embedded internal reference voltage
(1)
Parameter Conditions Min Typ
Internal reference voltage
Internal reference startup time
V
DDA
V
and V
REF+
REFINT
voltage during
factory measure
– 40 °C < T
J
< +125 °C 1.202
1.224
2
2.99
3
Accuracy of factory-measured
V
REFINT value
(3)
Temperature coefficient
Long-term stability
Including uncertainties due to ADC and
V
DDA
/V
REF+
values
–40 °C < T
J
< +125 °C
1000 hours, T= 25 °C
-
-
-
25
-
-
3.0 V < V
DDA
< 3.6 V Voltage coefficient
ADC sampling time when reading the internal reference voltage
Startup time of reference voltage buffer for ADC
-
5
-
10
-
Consumption of reference voltage buffer for ADC
VREF_OUT output current
(6)
VREF_OUT output load
-
-
-
-
-
13.5
-
-
Max
1.242
3
3.01
±5
100
1000
2000 ppm/°C ppm ppm/V
-
10
25
1
50
Unit
V ms
V mV
µs
µs
µA
µA pF
DS10671 Rev 5
123
Electrical characteristics STM32L083xx
Symbol
Table 29. Embedded internal reference voltage (1) (continued)
Parameter Conditions Min Typ Max Unit
I
LPBUF
(4)
Consumption of reference voltage buffer for VREF_OUT and COMP
730 1200 nA
V
REFINT_DIV1
(4)
V
REFINT_DIV2
(4)
V
REFINT_DIV3
(4)
1/4 reference voltage
1/2 reference voltage
3/4 reference voltage -
-
24
49
74
25
50
75
26
51
76
V
%
REFINT
1. Refer to
Table 41: Peripheral current consumption in Stop and Standby mode
for the value of the internal reference current consumption (I
REFINT
).
2. Guaranteed by test in production.
3. The internal V
REF
value is individually measured in production and stored in dedicated EEPROM bytes.
4. Guaranteed by design.
5. Shortest sampling time can be determined in the application by multiple iterations.
6. To guarantee less than 1% VREF_OUT deviation.
6.3.4 Supply current characteristics
The current consumption is a function of several parameters and factors such as the operating voltage, temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code.
The current consumption is measured as described in
Figure 13: Current consumption measurement scheme
.
All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to Dhrystone 2.1 code if not specified otherwise.
The current consumption values are derived from the tests performed under ambient temperature and V
DD
supply voltage conditions summarized in Table 26: General operating conditions
unless otherwise specified.
The MCU is placed under the following conditions:
• All I/O pins are configured in analog input mode
• All peripherals are disabled except when explicitly mentioned
• The Flash memory access time and prefetch is adjusted depending on fHCLK frequency and voltage range to provide the best CPU performance unless otherwise specified.
• When the peripherals are enabled f
APB1
= f
APB2
= f
APB
• When PLL is ON, the PLL inputs are equal to HSI = 16 MHz (if internal clock is used) or
HSE = 16 MHz (if HSE bypass mode is used)
• The HSE user clock applied to OSCI_IN input follows the characteristic specified in
Table 43: High-speed external user clock characteristics
• For maximum current consumption V
DD
= V
DDA
= 3.6 V is applied to all supply pins
• For typical current consumption V
DD specified otherwise
= V
DDA
= 3.0 V is applied to all supply pins if not
The parameters given in
are derived from tests performed under ambient temperature and V
DD
supply voltage conditions summarized in
DS10671 Rev 5
STM32L083xx Electrical characteristics
Table 30. Current consumption in Run mode, code with data processing running from
Flash memory
Symbol Parameter Condition f
HCLK
(MHz)
Typ Max
(1)
Unit
I
DD
(Run from Flash memory)
Supply current in Run mode code executed from Flash memory
Range3,
Vcore=1.2 V
VOS[1:0]=11 f
HSE
= f
HCLK
up to
16MHz included, f
HSE
= f
HCLK
/2 above
16 MHz (PLL ON)
(2)
Range2,
Vcore=1.5 V
VOS[1:0]=10
MSI clock source
Range1,
Vcore=1.8 V
VOS[1:0]=01
Range3,
Vcore=1.2 V
VOS[1:0]=11
16
8
4
8
1
2
4
16
32
0,065
0,524
4,2
250
380
670
0,86
1,7
3,1
2,1
3,8
7,2
130
210
770
190
345
650
0,8
1,55
2,95
1,9
3,55
6,65
39
115
700
µA mA
µA
HSI clock source
(16MHz)
Range2,
Vcore=1.5 V
VOS[1:0]=10
Range1,
Vcore=1.8 V
VOS[1:0]=01
1. Guaranteed by characterization results at 125 °C, unless otherwise specified.
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).
16
32
2,9
7,15
3,2
7,4 mA
DS10671 Rev 5
123
Electrical characteristics STM32L083xx
Symbol Parameter
Table 31. Current consumption in Run mode vs code type, code with data processing running from Flash memory
Conditions f
HCLK
I
DD
(Run from
Flash memory)
Supply current in
Run mode, code executed from Flash memory f
HSE
= f
HCLK
up to
16 MHz included, f
HSE
= f
HCLK
/2 above 16
MHz (PLL ON)
(1)
Range 3,
V
CORE
=1.2 V,
VOS[1:0]=11
Range 1,
V
CORE
=1.8 V,
VOS[1:0]=01
Dhrystone
CoreMark
Fibonacci while(1) while(1), 1WS, prefetch OFF
Dhrystone
CoreMark
Fibonacci while(1) while(1), prefetch
OFF
4 MHz
32 MHz
1. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).
Typ Unit
650
655
485
385
µA
375
6,65
6,9
6,75
5,8 mA
5,5
Figure 14. I
DD
vs V
DD
, at T
A
= 25/55/85/105 °C, Run mode, code running from
Flash memory, Range 2, HSE, 1WS
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0
1.65
1.8
2 2.2
2.4
2.6
-40 °C
25 °C
55 °C
85 °C
105 °C
125 °C
2.8
3 3.2
3.4
VDD (V)
3.6
MSv37843V1
DS10671 Rev 5
STM32L083xx Electrical characteristics
Figure 15. I
DD
vs V
DD
, at T
A
= 25/55/85/105 °C, Run mode, code running from
Flash memory, Range 2, HSI16, 1WS
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0
1.65
1.8
2 2.2
2.4
2.6
-40 °C
25 °C
55 °C
85 °C
105 °C
125 °C
2.8
3 3.2
3.4
VDD (V)
3.6
MSv37844V1
Table 32. Current consumption in Run mode, code with data processing running from RAM
Symbol Parameter Condition f
HCLK
(MHz)
Typ Max
(1)
Unit
I
DD
(Run from RAM)
Supply current in Run mode code executed from RAM, Flash memory switched off f
HSE
= f
HCLK
up to
16 MHz included, f
HSE
= f
HCLK
/2 above
16 MHz (PLL ON)
(2)
Range2,
Vcore=1.5 V
VOS[1:0]=10
MSI clock
Range3,
Vcore=1.2 V
VOS[1:0]=11
Range1,
Vcore=1.8 V
VOS[1:0]=01
Range3,
Vcore=1.2 V
VOS[1:0]=11
8
16
8
16
4
4
1
2
32
0,065
0,524
4,2
1,35
2,7
1,7
3,2
175
315
570
0,71
6,65
38
105
615
1,6
3
1,9
3,7
230
360
630
0,78
7,1
98
160
710
µA mA
µA
HSI clock source
(16 MHz)
Range2,
Vcore=1.5 V
VOS[1:0]=10
Range1,
Vcore=1.8 V
VOS[1:0]=01
1. Guaranteed by characterization results at 125 °C, unless otherwise specified.
16
32
2,85
6,85
3
7,3 mA
DS10671 Rev 5
123
Electrical characteristics
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).
STM32L083xx
Symbol
I
DD
(Run from
RAM)
Table 33. Current consumption in Run mode vs code type, code with data processing running from RAM
(1)
Parameter Conditions f
HCLK
Dhrystone
Supply current in
Run mode, code executed from
RAM, Flash memory switched off f
HSE
= f
HCLK
up to
16 MHz included, f
HSE
= f
HCLK
/2 above
16 MHz (PLL ON)
(2)
Range 3,
V
CORE
=1.2 V,
VOS[1:0]=11
Range 1,
V
CORE
=1.8 V,
VOS[1:0]=01
CoreMark
Fibonacci while(1)
Dhrystone
CoreMark
Fibonacci
4 MHz
32 MHz while(1)
1. Guaranteed by characterization results, unless otherwise specified.
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).
Typ Unit
570
670
410
375
6,65
6,95
5,9
5,2
µA mA
DS10671 Rev 5
STM32L083xx Electrical characteristics
Symbol
I
DD
(Sleep)
Parameter
Supply current in
Sleep mode, Flash memory switched
OFF
Table 34. Current consumption in Sleep mode
Condition f
HCLK
(MHz) f
HSE
= f
HCLK
up to
16 MHz included, f
HSE
= f
HCLK
/2 above
16 MHz (PLL ON)
(2)
MSI clock
Range3,
Vcore=1.2 V
VOS[1:0]=11
Range2,
Vcore=1.5 V
VOS[1:0]=10
Range1,
Vcore=1.8 V
VOS[1:0]=01
Range3,
Vcore=1.2 V
VOS[1:0]=11
8
16
8
16
4
4
1
2
32
0,065
0,524
4,2
HSI clock source
(16 MHz)
Range2,
Vcore=1.5 V
VOS[1:0]=10
Range1,
Vcore=1.8 V
VOS[1:0]=01
16
32
Typ
305
590
370
715
43,5
72
130
160
1650
18
31,5
140
665
1750
Supply current in
Sleep mode, Flash memory switched
ON f
HSE
= f
HCLK
up to
16MHz included, f
HSE
= f
HCLK
/2 above
16 MHz (PLL ON)
(2)
MSI clock
Range3,
Vcore=1.2 V
VOS[1:0]=11
Range2,
Vcore=1.5 V
VOS[1:0]=10
Range1,
Vcore=1.8 V
VOS[1:0]=01
Range3,
Vcore=1.2 V
VOS[1:0]=11
8
16
32
0,065
0,524
4,2
1
2
4
4
8
16
380
730
1650
29,5
44,5
150
57,5
84
150
170
315
605
HSI clock source
(16MHz)
Range2,
Vcore=1.5 V
VOS[1:0]=10
Range1,
Vcore=1.8 V
VOS[1:0]=01
16
32
680
1750
1. Guaranteed by characterization results at 125 °C, unless otherwise specified.
Max (1)
380
690
460
840
110
140
200
220
2000
93
110
230
850
Unit
2200
µA
2100
470
860
2000
110
120
240
130
160
220
240
400
710
930
DS10671 Rev 5
123
Electrical characteristics
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).
STM32L083xx
Symbol Parameter
Table 35. Current consumption in Low-power run mode
Condition f
HCLK
(MHz)
I
DD
(LP Run)
Supply current in
Low-power run mode
All peripherals
OFF, code executed from
RAM, Flash memory switched
OFF, V
DD
from
1.65 to 3.6 V
All peripherals
OFF, code executed from
Flash memory,
VDD from 1.65 V to 3.6 V
MSI clock = 65 kHz, f
HCLK
= 32 kHz
MSI clock = 65 kHz, f f
HCLK f
HCLK f
HCLK
= 65kHz
MSI clock=131 kHz,
= 131 kHz
MSI clock = 65 kHz,
= 32 kHz
MSI clock = 65 kHz, f
HCLK
= 65 kHz
MSI clock =
131 kHz,
HCLK
= 131 kHz
T
A
= − 40 to 25°C
T
A
= 85°C
T
A
= 105°C
T
A
= 125°C
T
A
= − 40 to 25°C
T
A
= 85°C
T
A
= 105°C
T
A
= 125°C
T
A
= − 40 to 25°C
T
A
= 55°C
T
A
= 85°C
T
A
= 105°C
T
A
= 125°C
T
A
= − 40 to 25°C
T
A
= 85°C
T
A
= 105°C
T
A
= 125°C
T
A
= − 40 to 25°C
T
A
= 85°C
T
A
= 105°C
T
A
= 125°C
T
A
= − 40 to 25°C
T
A
= 55°C
T
A
= 85°C
T
A
= 105°C
T
A
= 125°C
1. Guaranteed by characterization results at 125 °C, unless otherwise specified.
0,032
0,065
0,131
0,032
0,065
0,131
Typ Max
(1)
Unit
53,5
24,5
30
38,5
26,5
27,5
31
37,5
14,5
19,5
26
42
9,45
14
21
36,5
64,5
45
48
51
58
30,5
36,5
45
59,5
79,5
µA
170
34
82
90
30
60
66
77
18
60
65
160
12
58
64
160
120
56
96
110
120
40
88
96
120
150
DS10671 Rev 5
STM32L083xx Electrical characteristics
IDD (mA)
4,5E-02
4,0E-02
3,5E-02
3,0E-02
2,5E-02
2,0E-02
1,5E-02
1,0E-02
5,0E-03
0
1,65
Figure 16. I
DD
vs V
DD
, at T
A
= 25 °C, Low-power run mode, code running from RAM, Range 3, MSI (Range 0) at 64 KHz, 0 WS
1,8 2 2,2 2,4 2,8 3 3,2 3,4 2,6
-40
25
55
85
105
125
3,6
VDD (V)
MSv37845V2
Table 36. Current consumption in Low-power sleep mode
Symbol Parameter Condition Typ
Max
(1)
Unit
I
DD
(LP Sleep)
Supply current in
Low-power sleep mode
All peripherals
OFF, code executed from
Flash memory, V
DD from 1.65 to 3.6 V
MSI clock = 65 kHz, f
HCLK
= 32 kHz,
Flash memory OFF
T
A
= − 40 to 25°C 4,7 -
MSI clock = 65 kHz, f
HCLK
= 32 kHz
MSI clock = 65 kHz, f
HCLK
= 65 kHz
MSI clock = 131kHz, f
HCLK
= 131 kHz
T
A
= − 40 to 25°C 17
T
A
= 85°C
24
19,5 30
T
A
= 105°C 23 47
T
A
= 125°C 32,5
T
A
= − 40 to 25°C 17
70
24
T
A
= 85°C 20 31
T
A
= 105°C 23,5 47
T
A
= 125°C 32,5 70
T
A
= − 40 to 25°C 19,5 27
T
A
= 55°C 20,5 28
22,5 33 T
A
= 85°C
T
A
= 105°C
T
A
= 125°C
26
35
50
73
1. Guaranteed by characterization results at 125 °C, unless otherwise specified.
µA
DS10671 Rev 5
123
Electrical characteristics STM32L083xx
Symbol
Table 37. Typical and maximum current consumptions in Stop mode
Parameter Conditions Typ Max
(1)
Unit
I
DD
(Stop) Supply current in Stop mode
T
A
= − 40 to 25°C
T
A
= 55°C
T
A
= 85°C
T
A
= 105°C
T
A
= 125°C
1. Guaranteed by characterization results at 125 °C, unless otherwise specified.
0,43 1,00
0,735 2,50
2,25
5,3
4,90
13,00
12,5 28,00
µA
Figure 17. I
DD
vs V
DD
, at T
A
= 25/55/ 85/105/125 °C, Stop mode with RTC enabled and running on LSE Low drive
1.6E-02
1.4E-02
1.2E-02
1.0E-02
8.0E-03
6.0E-03
4.0E-03
2.0E-03
0
1.65
1.8
2 2.2
2.4
2.6
-40 °C
25 °C
55 °C
85 °C
105 °C
125 °C
2.8
3 3.2
3.4
3.6
VDD (V)
MSv37846V1
DS10671 Rev 5
STM32L083xx Electrical characteristics
Figure 18. I
DD
vs V
DD
, at T
A
= 25/55/85/105/125 °C, Stop mode with RTC disabled, all clocks OFF
1.4E-02
1.2E-02
1.0E-02
8.0E-03
6.0E-03
4.0E-03
2.0E-03
0
1.65
3.6
VDD (V)
1.8
2 2.2
2.4
2.6
-40 °C
25 °C
55 °C
85 °C
105 °C
125 °C
2.8
3 3.2
3.4
MSv37847V1
Symbol
Table 38. Typical and maximum current consumptions in Standby mode
Parameter Conditions
I
DD
(Standby)
Supply current in Standby mode
Independent watchdog and LSI enabled
Independent watchdog and LSI OFF
T
A
= − 40 to 25°C
T
A
= 55 °C
T
A
= 85 °C
T
A
= 105 °C
T
A
= 125 °C
T
A
= − 40 to 25°C
T
A
= 55 °C
T
A
= 85 °C
T
A
= 105 °C
T
A
= 125 °C
1. Guaranteed by characterization results at 125 °C, unless otherwise specified
Typ
0,855
-
-
-
-
0,29
0,32
0,5
0,94
2,6
Max
(1)
8,50
0,60
1,20
2,30
1,70
2,90
3,30
4,10
3,00
7,00
Unit
µA
DS10671 Rev 5
123
Electrical characteristics STM32L083xx
Symbol
Table 39. Average current consumption during Wakeup parameter System frequency
Current consumption during wakeup
I
DD
(Wakeup from
Stop)
Supply current during Wakeup from
Stop mode
I
DD
(Reset) Reset pin pulled down
HSI 1
HSI/4 0,7
MSI clock = 4,2 MHz 0,7
MSI clock = 1,05 MHz
MSI clock = 65 KHz
-
0,4
0,1
0,21
I
DD
(Power-up) BOR ON 0,23
I
DD
(Wakeup from
StandBy)
With Fast wakeup set
With Fast wakeup disabled
MSI clock = 2,1 MHz
MSI clock = 2,1 MHz
0,5
0,12
Unit mA
DS10671 Rev 5
STM32L083xx Electrical characteristics
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in the following tables. The
MCU is placed under the following conditions:
• all I/O pins are in input mode with a static value at V
DD
or V
SS
(no load)
• all peripherals are disabled unless otherwise mentioned
• the given value is calculated by measuring the current consumption
– with all peripherals clocked OFF
– with only one peripheral clocked on
Table 40. Peripheral current consumption in Run or Sleep mode
(1)
Typical consumption, V
DD
= 3.0 V, T
A
= 25 °C
Peripheral Range 1,
V
CORE
=1.8 V
VOS[1:0] = 01
Range 2,
V
CORE
=1.5 V
VOS[1:0] = 10
Range 3,
V
CORE
=1.2 V
VOS[1:0] = 11
Low-power sleep and run
APB1
CRS
DAC1/2
I2C1
I2C3
LCD1
LPTIM1
LPUART1
SPI2
USART2
USART4
USART5
USB
TIM2
TIM3
TIM6
TIM7
WWDG
8
9
14.5
5
5
8.5
2.5
4
11
11
4
10
10.5
12
3.5
3.5
3
6.5
4.5
12
4
4
4.5
2
3.5
9.5
9
3.5
8.5
8.5
10
3
3
2
5.5
3.5
9.5
3
3
4
2
3
7.5
7
3
6.5
7
8
2.5
2.5
2
6
4
11
5
5
4.5
2
2.5
9
9
2.5
8
9
11
2
2
2
Unit
µA/MHz
(f
HCLK
)
DS10671 Rev 5
123
Electrical characteristics STM32L083xx
Table 40. Peripheral current consumption in Run or Sleep mode (1) (continued)
Typical consumption, V
DD
= 3.0 V, T
A
= 25 °C
Peripheral Range 1,
V
CORE
=1.8 V
VOS[1:0] = 01
Range 2,
V
CORE
=1.5 V
VOS[1:0] = 10
Range 3,
V
CORE
=1.2 V
VOS[1:0] = 11
Low-power sleep and run
Unit
APB2
ADC1
(2)
SPI1
USART1
TIM21
TIM22
FIREWALL
DBGMCU
5.5
4
14.5
7.5
7
1.5
1.5
1
1
6
6
5
3
11.5
1
1
5
5
3.5
3
9.5
5.5
6
0.5
0.5
4
2.5
12
µA/MHz
(f
HCLK
)
SYSCFG
GPIOA
GPIOB
Cortex-
M0+ core
I/O port
GPIOC
GPIOD
GPIOE
GPIOH
CRC
FLASH
2.5
3.5
3.5
8.5
1
8
1.5
1.5
0
(3)
2
3
2.5
6.5
0.5
6
1
1
0
2
2.5
2
5.5
0.5
5
1
1
1.5
2.5
2.5
7
0.5
6
0.5
1
µA/MHz
(f
HCLK
)
AHB
DMA1
RNG
10
5.5
8
1
6.5
0.5
8.5
0.5
µA/MHz
(f
HCLK
)
TSC
AES
3
0
2.5
0
2
3
All enabled
PWR
204
2.5
162
2
130
2
202
1
µA/MHz
(f
HCLK
)
µA/MHz
(f
HCLK
)
1. Data based on differential I enabled, in the following conditions: f
(range 3), f
HCLK
DD
measurement between all peripherals OFF an one peripheral with clock
HCLK
= 32 MHz (range 1), f
= 64kHz (Low-power run/sleep), f
APB1
HCLK
= 16 MHz (range 2), f
= f
HCLK
, f
APB2
= f
HCLK
HCLK
= 4 MHz
, default prescaler value for each peripheral. The CPU is in Sleep mode in both cases. No I/O pins toggling. Not tested in production.
2. HSI oscillator is OFF for this measure.
3. Current consumption is negligible and close to 0 µA.
DS10671 Rev 5
STM32L083xx Electrical characteristics
Table 41. Peripheral current consumption in Stop and Standby mode
(1)
Typical consumption, T
A
= 25 °C
Symbol Peripheral
V
DD
=1.8 V V
DD
=3.0 V
I
DD(PVD / BOR)
I
REFINT
-
-
-
-
-
LSE Low drive
(2)
LSI
IWDG
0.7
-
0.11
0.27
0.2
1.2
1.7
0,13
0.31
0.3
Unit
LPTIM1, Input 100 Hz 0.01
0,01
µA
LPTIM1, Input 1 MHz 11 12
-
-
-
LPUART1
RTC
LCD1 (static duty)
-
0.16
0.15
0,5
0,3
0.15
µA
LCD1 (1/8 duty) 1.6
2.6
1. LCD, LPTIM, LPUART peripherals can operate in Stop mode but not in Standby mode.
2. LSE Low drive consumption is the difference between an external clock on OSC32_IN and a quartz between OSC32_IN and OSC32_OUT.-
6.3.5 Wakeup time from low-power mode
The wakeup times given in the following table are measured with the MSI or HSI16 RC oscillator. The clock source used to wake up the device depends on the current operating mode:
• Sleep mode: the clock source is the clock that was set before entering Sleep mode
• Stop mode: the clock source is either the MSI oscillator in the range configured before entering Stop mode, the HSI16 or HSI16/4.
• Standby mode: the clock source is the MSI oscillator running at 2.1 MHz
All timings are derived from tests performed under ambient temperature and V
DD voltage conditions summarized in
supply
DS10671 Rev 5
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Electrical characteristics STM32L083xx
Symbol
Table 42. Low-power mode wakeup timings
Parameter Conditions t
WUSLEEP t
WUSLEEP_
LP
Wakeup from Sleep mode
Wakeup from Low-power sleep mode, f
HCLK
= 262 kHz f
HCLK
= 32 MHz f
HCLK
= 262 kHz
Flash memory enabled f
HCLK
= 262 kHz
Flash memory switched OFF
Wakeup from Stop mode, regulator in Run mode f
HCLK
= f
MSI
= 4.2 MHz f
HCLK
= f
HSI
= 16 MHz f
HCLK
= f
HSI
/4 = 4 MHz f
HCLK
= f
MSI
= 4.2 MHz
Voltage range 1 f
HCLK
= f
MSI
= 4.2 MHz
Voltage range 2 f
HCLK
= f
MSI
= 4.2 MHz
Voltage range 3 t t
WUSTOP
WUSTDBY
Wakeup from Stop mode, regulator in lowpower mode
Wakeup from Stop mode, regulator in lowpower mode, code running from RAM f
HCLK
= f
MSI
= 2.1 MHz f
HCLK
= f
MSI
= 1.05 MHz f
HCLK
= f
MSI
= 524 kHz f
HCLK
= f
MSI
= 262 kHz f
HCLK
= f
MSI
= 131 kHz f
HCLK
= MSI = 65 kHz f
HCLK
= f
HSI
= 16 MHz f
HCLK
= f
HSI
/4 = 4 MHz f
HCLK
= f
HSI
= 16 MHz f
HCLK
= f
HSI
/4 = 4 MHz f
HCLK
= f
MSI
= 4.2 MHz
Wakeup from Standby mode
FWU bit = 1
Wakeup from Standby mode
FWU bit = 0 f f
HCLK
HCLK
= MSI = 2.1 MHz
= MSI = 2.1 MHz
5.0
5.0
4.9
8.0
4.9
7.9
4.7
7.3
13
28
51
100
190
65
2.2
Typ
7
7
9
5.0
4.9
8.0
5.0
8
8
7
11
7
10
8
13
23
38
65
120
260
130
3
10
8
7
11
8
Max
8
8
Unit
Number of clock cycles
µs ms
DS10671 Rev 5
STM32L083xx Electrical characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.The
external clock signal has to respect the I/O characteristics in Section 6.3.12
. However, the
recommended clock input waveform is shown in Figure 19 .
Symbol f
HSE_ext
Table 43. High-speed external user clock characteristics (1)
Parameter Conditions Min Typ Max Unit
User external clock source frequency
CSS is ON or
PLL is used
CSS is OFF,
PLL not used
1
0
8
8
32
32
MHz
MHz
V
HSEH
V
HSEL t w(HSE) t w(HSE) t r(HSE) t f(HSE)
C in(HSE)
DuCy
(HSE)
I
L
OSC_IN input pin high level voltage
OSC_IN input pin low level voltage
OSC_IN high or low time
OSC_IN rise or fall time
OSC_IN input capacitance
Duty cycle
OSC_IN Input leakage current
1. Guaranteed by design.
-
V
SS
≤ V
IN
≤ V
DD
0.7V
DD
V
SS
12
-
-
45
-
-
-
2.6
-
-
-
V
DD
0.3V
DD
-
20
-
55
±1
V ns pF
%
µA
Figure 19. High-speed external clock source AC timing diagram
V
HSEH
V
HSEL
90%
10% t r(HSE)
T
HSE t f(HSE)
EXTER NAL
CLOCK SOURC E f
HSE_ext
OSC _IN t
W(HSE)
I
L
STM32Lxx t
W(HSE) t ai18232c
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Electrical characteristics STM32L083xx
Low-speed external user clock generated from an external source
The characteristics given in the following table result from tests performed using a lowspeed external clock source, and under ambient temperature and supply voltage conditions summarized in
Symbol
Table 44. Low-speed external user clock characteristics (1)
Parameter Conditions f
LSE_ext
V
LSEH
User external clock source frequency
OSC32_IN input pin high level voltage
V
LSEL
OSC32_IN input pin low level voltage
t w(LSE) t w(LSE) t r(LSE) t f(LSE)
C
IN(LSE)
DuCy
I
L
(LSE)
OSC32_IN high or low time
OSC32_IN rise or fall time
OSC32_IN input capacitance
Duty cycle
-
OSC32_IN Input leakage current V
SS
≤ V
IN
≤ V
DD
1. Guaranteed by design, not tested in production
-
Min
1
0.7V
DD
V
SS
465
-
-
45
-
Typ
32.768
-
-
-
-
0.6
-
-
Max Unit
1000 kHz
V
DD
0.3V
DD
-
10
-
55
±1
V ns pF
%
µA
Figure 20. Low-speed external clock source AC timing diagram
V
LSEH
V
LSEL
90%
10% t r(LSE)
T
LSE t f(LSE) t
W(LSE) t
W(LSE) t
EXTER NAL
CLOCK SOURC E f
LSE_ext
OSC32_IN
I
L
STM32Lxx ai18233c
DS10671 Rev 5
STM32L083xx Electrical characteristics
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 1 to 25 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in
the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).
Symbol
Table 45. HSE oscillator characteristics (1)
Parameter t f
OSC_IN
R
F
G m
Oscillator frequency
Feedback resistor
Maximum critical crystal transconductance
Startup time
Conditions
-
-
Startup
V
DD
is stabilized
Min Typ Max Unit
1
200
-
-
2
25 MHz
-
700 k Ω
µA
/V
ms
1. Guaranteed by design.
2. Guaranteed by characterization results. t
SU(HSE)
is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
For C
L1
and C
L2
, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 21
). C
L1
and C
L2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C
L1
and C
L2
. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing
C
L1
and C
L2
. Refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com
.
Figure 21. HSE oscillator circuit diagram f
HSE
to core
R m
C
O
L m
C m
Resonator
C
L1
OSC_IN
R
F g m
Consumption control
Resonator
STM32
OSC_OUT
C
L2 ai18235b
DS10671 Rev 5
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Electrical characteristics STM32L083xx
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in
the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).
Symbol Parameter
Table 46. LSE oscillator characteristics (1)
Conditions
(2)
Min
(2)
Typ Max Unit f
LSE
LSE oscillator frequency 32.768
kHz
LSEDRV[1:0]=00 lower driving capability
LSEDRV[1:0]= 01 medium low driving capability
-
-
-
-
0.5
0.75
G m
Maximum critical crystal transconductance
1.7
µA/V
LSEDRV[1:0] = 10 medium high driving capability
LSEDRV[1:0]=11 higher driving capability
2.7
t
SU(LSE)
(3) Startup time V
DD
is stabilized 2 -
1. Guaranteed by design.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers”.
3. Guaranteed by characterization results. t
SU(LSE)
is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. To increase speed, address a lower-drive quartz with a high- driver mode.
s
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com
.
Figure 22. Typical application with a 32.768 kHz crystal
Resonator with integrated capacitors
C
L1
OSC32_IN f
LSE
32.768 kHz resonator
Drive programmable amplifier
OSC32_OUT
C
L2
Note:
MS30253V2
An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one.
DS10671 Rev 5
STM32L083xx
6.3.7
Electrical characteristics
Internal clock source characteristics
The parameters given in
Table 47 are derived from tests performed under ambient
temperature and V
DD
supply voltage conditions summarized in
High-speed internal 16 MHz (HSI16) RC oscillator
Symbol
Table 47. 16 MHz HSI16 oscillator characteristics
Parameter Conditions Min Typ Max Unit f
HSI16
TRIM
(1)(2)
ACC
Frequency
HSI16 usertrimmed resolution
Accuracy of the factory-calibrated
HSI16 oscillator
V
DD
= 3.0 V
Trimming code is not a multiple of 16 -
-
Trimming code is a multiple of 16
V
DDA
= 3.0 V, T
A
= 25 °C
V
DDA
= 3.0 V, T
A
= 0 to 55 °C
V
DDA
= 3.0 V, T
A
= -10 to 70 °C
V
DDA
= 3.0 V, T
A
= -10 to 85 °C
V
DDA
= 3.0 V, T
A
= -10 to 105 °C
V
DDA
T
A
= 1.65 V to 3.6 V
= − 40 to 125 °C
-
-1 (3)
-1.5
-2
-2.5
-4
-5.45
16
± 0.4
0.7
-
-
%
± 1.5
%
1 (3) %
-
-
-
-
-
-
1.5
2
2
2
3.25
MHz
%
%
%
%
% t
SU(HSI16)
(2)
HSI16 oscillator startup time
I
DD(HSI16)
(2)
HSI16 oscillator power consumption
-
-
-
3.7
100
6
140
1. The trimming step differs depending on the trimming code. It is usually negative on the codes which are multiples of 16 (0x00, 0x10, 0x20, 0x30...0xE0).
2. Guaranteed by characterization results.
3. Guaranteed by test in production.
µs
µA
-60
Figure 23. HSI16 minimum and maximum value versus temperature
-40
4.00%
3.00%
2.00%
1.00%
-20
0.00%
-1.00%
0
-2.00%
-3.00%
-4.00%
-5.00%
-6.00%
20 40 60 80 100 120 140
1.65V min
3V typ
3.6V max
1.65V max
3.6V min
MSv34791V1
DS10671 Rev 5
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Electrical characteristics STM32L083xx
High-speed internal 48 MHz (HSI48) RC oscillator
Symbol
Table 48. HSI48 oscillator characteristics
(1)
Parameter Conditions f
HSI48
TRIM t su(HSI48)
Frequency
HSI48 user-trimming step
DuCy
(HSI48)
Duty cycle
ACC
HSI48
Accuracy of the HSI48 oscillator (factory calibrated before CRS calibration)
HSI48 oscillator startup time
I
DDA(HSI48)
HSI48 oscillator power consumption
T
A
= 25 °C
1. V
DDA
= 3.3 V, T
A
= –40 to 125 °C unless otherwise specified.
2. Guaranteed by design.
3. Guaranteed by characterization results.
Min
-
0.09
(2)
45 (2)
-4
(3)
-
-
Typ
48
0.14
-
-
-
330
Low-speed internal (LSI) RC oscillator
Symbol
Table 49. LSI oscillator characteristics
Parameter Min Typ f
LSI
(1)
LSI frequency 26 38
D
LSI
(2) t su(LSI)
(3)
I
DD(LSI)
(3)
LSI oscillator frequency drift
0°C ≤ T
A
≤
LSI oscillator startup time
LSI oscillator power consumption
-10
-
-
-
-
400
1. Guaranteed by test in production.
2. This is a deviation for an individual part, once the initial frequency has been measured.
3. Guaranteed by design.
Max
56
4
200
510
Multi-speed internal (MSI) RC oscillator
Symbol f
MSI
Table 50. MSI oscillator characteristics
Parameter Condition
Frequency after factory calibration, done at
V
DD
= 3.3 V and T
A
= 25 °C
MSI range 0
MSI range 1
MSI range 2
MSI range 3
MSI range 4
MSI range 5
MSI range 6
Max
-
0.2
(2)
55 (2)
4
(3)
6
(2)
380
(2)
Unit
MHz
%
%
%
µs
µA
Unit kHz
%
µs nA
Typ
65.5
131
262
524
1.05
2.1
4.2
Max Unit
-
-
-
-
-
-
kHz
MHz
DS10671 Rev 5
STM32L083xx Electrical characteristics
Symbol
ACC
MSI
Table 50. MSI oscillator characteristics (continued)
Parameter Condition Typ
± 0.5
Frequency error after factory calibration
MSI oscillator frequency drift
0 °C ≤ T
A
≤ 85 °C
± 3
D
TEMP(MSI)
(1)
MSI oscillator frequency drift
V
DD
= 3.3 V, − 40 °C T
A
≤
MSI range 0
MSI range 1
MSI range 2
MSI range 3
MSI range 4
MSI range 5
MSI range 6
Max Unit
-
-
− 8.9
+7.0
− 7.1
+5.0
− 6.4
+4.0
− 6.2
+3.0
− 5.2
+3.0
− 4.8
+2.0
− 4.7
+2.0
%
%
D
VOLT(MSI)
(1)
MSI oscillator frequency drift
1.65 V ≤ V
DD
≤ 3.6 V, T
A
= 25 °C
2.5
%/V
I
DD(MSI)
(2) t
SU(MSI)
MSI oscillator power consumption
MSI oscillator startup time
MSI range 0
MSI range 1
MSI range 2
MSI range 3
MSI range 4
MSI range 5
MSI range 6
MSI range 0
MSI range 1
MSI range 2
MSI range 3
MSI range 4
MSI range 5
MSI range 6,
Voltage range 1 and 2
MSI range 6,
Voltage range 3
15
10
6
5
15
30
20
0.75
1
1.5
2.5
4.5
8
3.5
5 -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
µA
µs
DS10671 Rev 5
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Electrical characteristics STM32L083xx
Symbol
Table 50. MSI oscillator characteristics (continued)
Parameter Condition t
STAB(MSI)
(2) f
OVER(MSI)
MSI oscillator stabilization time
MSI oscillator frequency overshoot
MSI range 0
MSI range 1
MSI range 2
MSI range 3
MSI range 4
MSI range 5
MSI range 6,
Voltage range 1 and 2
MSI range 3,
Voltage range 3
Any range to range 5
Any range to range 6
1. This is a deviation for an individual part, once the initial frequency has been measured.
2. Guaranteed by characterization results.
Typ
-
-
-
-
-
-
-
-
-
-
Max Unit
40
20
10
4
2.5
2
µs
2
3
4
6
MHz
The parameters given in
Table 51 are derived from tests performed under ambient
temperature and V
DD
supply voltage conditions summarized in
Table 51. PLL characteristics
Value
Symbol Parameter Unit
Min Typ Max
(1) f
PLL_IN
PLL input clock (2)
PLL input clock duty cycle
2
45
-
-
24
55
MHz
% f
PLL_OUT
PLL output clock 2 32 MHz t
LOCK
PLL input = 16 MHz
PLL VCO = 96 MHz
115 160 µs
I
I
Jitter
DDA
DD
(PLL)
(PLL)
Cycle-to-cycle jitter
Current consumption on V
DDA
Current consumption on V
DD
-
-
220
120
± 600
450
150 ps
µA
1. Guaranteed by characterization results.
2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by f
PLL_OUT
.
DS10671 Rev 5
STM32L083xx Electrical characteristics
RAM memory
Table 52. RAM and hardware registers
Symbol Parameter
VRM Data retention mode
(1)
Conditions
STOP mode (or RESET)
Min
1.65
Typ Max Unit
-
1. Minimum supply voltage without losing data stored in RAM (in Stop mode or under Reset) or in hardware registers (only in Stop mode).
V
Flash memory and data EEPROM
Symbol
Table 53. Flash memory and data EEPROM characteristics
Parameter Conditions t
V
I
DD prog
DD
Operating voltage
Read / Write / Erase
-
Programming time for word or half-page
Erasing
Programming
Average current during the whole programming / erase operation
Maximum current (peak) during the whole programming / erase operation
T
A
= 25 °C, V
DD
= 3.6 V
1. Guaranteed by design.
Min
1.65
-
-
-
-
Typ Max (1)
-
3.28
3.28
500
1.5
3.6
3.94
3.94
700
2.5
Unit
V ms
µA mA
Symbol
Table 54. Flash memory and data EEPROM endurance and retention
Value
Parameter Conditions
Min
(1)
N
CYC
(2)
Cycling (erase / write)
Program memory
Cycling (erase / write)
EEPROM data memory
Cycling (erase / write)
Program memory
Cycling (erase / write)
EEPROM data memory
T
A
= -40°C to 105 °C
T
A
= -40°C to 125 °C
10
100
0.2
2
Unit kcycles
DS10671 Rev 5
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Electrical characteristics STM32L083xx
Table 54. Flash memory and data EEPROM endurance and retention (continued)
Value
Symbol Parameter Conditions Unit
Min
(1) t
RET
(2)
Data retention (program memory) after
10 kcycles at T
A
= 85 °C
Data retention (EEPROM data memory) after 100 kcycles at T
A
= 85 °C
Data retention (program memory) after
10 kcycles at T
A
= 105 °C
Data retention (EEPROM data memory) after 100 kcycles at T
A
= 105 °C
Data retention (program memory) after
200 cycles at T
A
= 125 °C
Data retention (EEPROM data memory) after 2 kcycles at T
A
= 125 °C
T
RET
= +85 °C
T
RET
= +105 °C
T
RET
= +125 °C
1. Guaranteed by characterization results.
2. Characterization is done according to JEDEC JESD22-A117.
30
30
10 years
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:
• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB : A Burst of Fast Transient voltage (positive and negative) is applied to V
V
SS
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard.
DD
and
A device reset allows normal operations to be resumed.
The test results are given in Table 55
. They are based on the EMS levels and classes defined in application note AN1709.
Table 55. EMS characteristics
Symbol
V
V
FESD
EFTB
Parameter Conditions
Level/
Class
Voltage limits to be applied on any I/O pin to induce a functional disturbance
Fast transient voltage burst limits to be applied through 100 pF on V
DD
and V pins to induce a functional disturbance
SS
V
DD
= 3.3 V, LQFP100, T
A
= +25 °C, f
HCLK
= 32 MHz conforms to IEC 61000-4-2
V
DD
= 3.3 V, LQFP100, T
A
= +25 f
°C,
HCLK
= 32 MHz conforms to IEC 61000-4-4
3B
4A
DS10671 Rev 5
STM32L083xx Electrical characteristics
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
• Corrupted program counter
• Unexpected reset
• Critical data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 56. EMI characteristics
Symbol Parameter
S
EMI
Conditions
Peak level
V
DD
= 3.6 V,
T
A
= 25 °C,
LQFP100 package compliant with IEC 61967-2
Monitored frequency band
0.1 to 30 MHz
30 to 130 MHz
130 MHz to 1 GHz
EMI Level
Max vs. frequency range at
32 MHz
9
2
-7
14
Unit dBµV
-
DS10671 Rev 5
123
Electrical characteristics STM32L083xx
Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the ANSI/JEDEC standard.
Symbol
Table 57. ESD absolute maximum ratings
Ratings Conditions Class
Maximum value
(1)
Unit
V
ESD(HBM)
Electrostatic discharge voltage (human body model)
V
ESD(CDM)
Electrostatic discharge voltage (charge device model)
1. Guaranteed by characterization results.
T
A
= +25 °C, conforming to
ANSI/JEDEC JS-001
T
A
= +25 °C, conforming to
ANSI/ESD STM5.3.1.
2
C4
2000
500
V
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up performance:
• A supply overvoltage is applied to each power supply pin
• A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Symbol
LU
Parameter
Table 58. Electrical sensitivities
Conditions
Static latch-up class T
A
= +125 °C conforming to JESD78A
Class
II level A
DS10671 Rev 5
STM32L083xx Electrical characteristics
As a general rule, current injection to the I/O pins, due to external voltage below V
SS
(for standard pins) should be avoided during normal product operation.
or above V
DD
However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of –5 µA/+0 µA range), or other functional failure (for example reset occurrence oscillator frequency deviation).
The test results are given in the Table 59
.
Symbol
I
INJ
Table 59. I/O current injection susceptibility
Functional susceptibility
Description
Negative injection
Positive injection
-0 NA (1) Injected current on BOOT0
Injected current on PA0, PA4, PA5, PC15,
PH0 and PH1
Injected current on any other FT, FTf pins
Injected current on any other pins
-5
-5
(2)
-5
(2)
0
+5
1. Current injection is not possible.
2. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.
Unit mA
DS10671 Rev 5
123
Electrical characteristics STM32L083xx
General input/output characteristics
Unless otherwise specified, the parameters given in
Table 60 are derived from tests
performed under the conditions summarized in Table 26
. All I/Os are CMOS and TTL compliant.
Table 60. I/O static characteristics
Parameter Conditions Min Typ Max Unit Symbol
V
V
V
IL
IH hys
Input low level voltage
Input high level voltage
TC, FT, FTf, RST
I/Os
BOOT0 pin
All I/Os
I/O Schmitt trigger voltage hysteresis
(2)
Standard I/Os
BOOT0 pin
V
SS
≤ V
IN
≤ V
DD
All I/Os except for
PA11, PA12, BOOT0 and FTf I/Os
V
SS
≤ V
IN
≤ V
DD
,
PA11 and PA12 I/Os
-
-
0.7 V
DD
-
-
-
-
-
-
-
10% V
DD
(3)
0.01
-
-
0.3V
0.14V
-
-
-
DD
DD
(1)
±50
-50/+250
V
SS
≤ V
IN
≤ V
FTf I/Os
DD ±100
I lkg
Input leakage current
(4)
V
DD
≤ V
IN
≤ 5 V
All I/Os except for
PA11, PA12, BOOT0 and FTf I/Os
V
DD
≤ V
IN
≤ 5 V
FTf I/Os
-
-
-
200
500
V
DD
≤ V
IN
≤ 5 V
PA11, PA12 and
BOOT0
10
R
PU
R
PD
C
IO
Weak pull-up equivalent resistor
Weak pull-down equivalent resistor
I/O pin capacitance
(5)
(5)
V
IN
=
V
IN
=
-
V
SS
V
DD
25
25
-
45
45
5
65
65
-
1. Guaranteed by characterization.
2. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization results.
3. With a minimum of 200 mV. Guaranteed by characterization results.
4. The max. value may be exceeded if negative current is injected on adjacent pins.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
MOS/NMOS contribution to the series resistance is minimum (~10% order).
V nA nA
µA k Ω k Ω pF
DS10671 Rev 5
STM32L083xx Electrical characteristics
Figure 24. V
IH
/V
IL
versus VDD (CMOS I/Os)
V
IL
/V
IH
(V)
V
IHmin
2.0
CMOS standard requirements V
DD
IHmin
= 0.7V
DD
+0.59 (all pins
V
IHmin
= 0.39V
DD
+0.38 for except BOOT0, PC15, PH0/1
V
IHmin
BOOT0, PC15, PH0/1
V
ILmax
= 0.3V
DD
1.3
Input range not guaranteed
CMOS standard requirements V
ILmax
= 0.3V
DD V
ILmax
0.7
0.6
V
DD
(V)
2.0
2.7
3.0
3.3
3.6
MSv34789V1
Figure 25. V
IH
/V
IL
versus VDD (TTL I/Os)
V
IL
/V
IH
(V)
V
IHmin
2.0
TTL standard requirements V
IHmin
= 2 V
V
IHmin
= 0.39V
DD
+0.59 (all pins
V
IHmin
BOOT0, PC15, PH0/1
V
ILmax
= 0.3V
DD
1.3
Input range not guaranteed
V
ILmax
0.8
0.7
TTL standard requirements V
ILmax
= 0.8 V
V
DD
(V)
2.0
2.7
3.0
3.3
3.6
MSv34790V1
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source up to ±15 mA with the non-standard V
OL
/V
OH
specifications given in Table 61
.
In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in
:
• The sum of the currents sourced by all the I/Os on V
DD,
I consumption of the MCU sourced on V
DD,
VDD( Σ )
). plus the maximum Run cannot exceed the absolute maximum rating
• The sum of the currents sunk by all the I/Os on V
SS
I consumption of the MCU sunk on V
SS
VSS( Σ )
plus the maximum Run
cannot exceed the absolute maximum rating
DS10671 Rev 5
123
Electrical characteristics STM32L083xx
Output voltage levels
Unless otherwise specified, the parameters given in
Table 61 are derived from tests
performed under ambient temperature and V
DD
Table 26 . All I/Os are CMOS and TTL compliant.
supply voltage conditions summarized in
Symbol
Table 61. Output voltage characteristics
Parameter Conditions Min Max Unit
V
V
OL
(1)
OH
(3)
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
CMOS port
(2)
,
I
IO
= +8 mA
2.7 V ≤ V
DD
≤ 3.6 V
V
DD
-
-0.4
0.4
-
V
V
V
V
V
V
V
OL
(1)
OH
(3)(4)
OL
(1)(4)
OH
(3)(4)
OL
(1)(4)
OH
(3)(4)
OLFM+
(1)(4)
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
Output low level voltage for an FTf
I/O pin in Fm+ mode
TTL port
(2)
,
I
IO
=+ 8 mA
2.7 V ≤ V
DD
≤ 3.6 V
TTL port
(2)
,
I
IO
= -6 mA
2.7 V ≤ V
DD
≤ 3.6 V
I
IO
= +15 mA
2.7 V ≤ V
DD
≤ 3.6 V
I
IO
= -15 mA
2.7 V ≤ V
DD
≤ 3.6 V
I
IO
= +4 mA
1.65 V ≤ V
DD
< 3.6 V
I
IO
= -4 mA
1.65 V ≤ V
DD
≤ 3.6 V
I
IO
= 20 mA
2.7 V ≤ V
DD
≤ 3.6 V
I
IO
= 10 mA
1.65 V ≤ V
DD
≤ 3.6 V
V
V
-
2.4
DD
DD
-
-
-
-
-1.3
-0.45
0.4
-
1.3
-
0.45
-
0.4
0.4
1. The I
IO
current sunk by the device must always respect the absolute maximum rating specified in Table 24
. must not exceed Σ I
IO(PIN)
.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. The I
IO
current sourced by the device must always respect the absolute maximum rating specified in
. The sum of the currents sourced by all the I/Os (I/O ports and control pins) must always be respected and must not exceed Σ I
IO(PIN)
.
4. Guaranteed by characterization results.
V
DS10671 Rev 5
STM32L083xx Electrical characteristics
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in
and
Unless otherwise specified, the parameters given in
Table 62 are derived from tests
performed under ambient temperature and V
DD
supply voltage conditions summarized in
Table 62. I/O AC characteristics (1)
OSPEEDRx[1:0] bit value
(1)
Symbol Parameter Conditions Min Max
(2)
Unit
00
01
10
11 f f
F
F max(IO)out t t max(IO)out t t max(IO)out max(IO)out t t t t f(IO)out r(IO)out f(IO)out r(IO)out f(IO)out r(IO)out f(IO)out r(IO)out
Maximum frequency
(3)
Output rise and fall time
Maximum frequency
Maximum frequency
Maximum frequency
(3)
Output rise and fall time
(3)
Output rise and fall time
(3)
Output rise and fall time
C
L
= 50 pF, V
DD
= 2.7 V to 3.6 V
C
L
= 50 pF, V
DD
= 1.65 V to 2.7 V
C
L
= 50 pF, V
DD
= 2.7 V to 3.6 V
C
L
= 50 pF, V
DD
= 1.65 V to 2.7 V
C
L
= 50 pF, V
DD
= 2.7 V to 3.6 V
C
L
= 50 pF, V
DD
= 1.65 V to 2.7 V
C
L
= 50 pF, V
DD
= 2.7 V to 3.6 V
C
L
= 50 pF, V
DD
= 1.65 V to 2.7 V
C
L
= 50 pF, V
DD
= 2.7 V to 3.6 V
C
L
= 50 pF, V
DD
= 1.65 V to 2.7 V
C
L
= 50 pF, V
DD
= 2.7 V to 3.6 V
C
L
= 50 pF, V
DD
= 1.65 V to 2.7 V
C
L
= 30 pF, V
DD
= 2.7 V to 3.6 V
C
L
= 50 pF, V
DD
= 1.65 V to 2.7 V
C
L
= 30 pF, V
DD
= 2.7 V to 3.6 V
C
L
= 50 pF, V
DD
= 1.65 V to 2.7 V
Fm+ configuration
-
(4) f max(IO)out t t t f(IO)out t r(IO)out f max(IO)out t f(IO)out r(IO)out
EXTIpw
Maximum frequency
(3)
Output fall time
Output rise time
Maximum frequency
(3)
Output fall time
Output rise time
Pulse width of external signals detected by the
EXTI controller
C
C
L
L
= 50 pF, V
= 50 pF, V
DD
DD
= 2.5 V to 3.6 V
= 1.65 V to 3.6 V
8 ns
1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the line reference manual for a description of GPIO Port configuration register.
2. Guaranteed by design.
3. The maximum frequency is defined in Figure 26 .
4. When Fm+ configuration is set, the I/O speed control is bypassed. Refer to the line reference manual for a detailed description of Fm+ I/O configuration.
400
100
125
320
2
0.6
30 kHz ns
MHz
65
10
2
13
28
35 ns
MHz ns
10
6
17
MHz ns
1
10
30
MHz ns
350 KHz
15 ns
60
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DS10671 Rev 5
123
Electrical characteristics STM32L083xx
Figure 26. I/O AC characteristics definition
90% 10%
50%
10%
50%
90%
EXTERNAL
OUTPUT
ON CL tr(IO)out
T tf(IO)out
Maximum frequency is achieved if (tr + tf) ≤ (2/3)T and if the duty cycle is (45-55%) when loaded by C L specified in the table “ I/O AC characteristics ”. ai14131d
6.3.14 NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, R
PU
, except when it is internally driven low (see Table 63 ).
Unless otherwise specified, the parameters given in
Table 63 are derived from tests
performed under ambient temperature and V
DD
supply voltage conditions summarized in
V
V
V
Symbol
IL(NRST)
(1)
IH(NRST)
(1)
OL(NRST)
(1) voltage
Table 63. NRST pin characteristics
Parameter
NRST input low level voltage
NRST input high level voltage
NRST output low level
Conditions
-
-
I
OL
= 2 mA
2.7 V < V
DD
< 3.6 V
I
OL
= 1.5 mA
1.65 V < V
DD
< 2.7 V
Min
V
-
-
SS
1.4
Typ
-
-
-
-
Max Unit
0.8
V
DD
0.4
V
V hys(NRST)
(1)
NRST Schmitt trigger voltage hysteresis
10%V
DD
(2)
mV
R
PU
Weak pull-up equivalent resistor
(3)
V
IN
= V
SS
25 45 65 k Ω
V
F(NRST)
(1)
V
NF(NRST)
(1)
NRST input filtered pulse
NRST input not filtered pulse -
-
350 -
50
-
1. Guaranteed by design.
2. 200 mV minimum value
3. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is around 10%.
ns ns
DS10671 Rev 5
STM32L083xx Electrical characteristics
Figure 27. Recommended NRST pin protection
([WHUQDO
UHVHWFLUFXLW
)
1567
9
''
5
38
)LOWHU
,QWHUQDOUHVHW
069
1. The reset network protects the device against parasitic resets.
2. The external capacitor must be placed as close as possible to the device.
3. The user must ensure that the level on the NRST pin can go below the V
Table 63 . Otherwise the reset will not be taken into account by the device.
max level specified in
Note:
Unless otherwise specified, the parameters given in
Table 64 are derived from tests
performed under ambient temperature, f
PCLK frequency and V summarized in
Table 26: General operating conditions .
DDA
supply voltage conditions
It is recommended to perform a calibration after each power-up.
Symbol
V
DDA
V
REF+
V
REF-
I
DDA (ADC) f
ADC f
S
(3) f
TRIG
(3)
V
AIN
Parameter
Table 64. ADC characteristics
Conditions
Analog supply voltage for
ADC ON
Sampling rate
External trigger frequency
Fast channel
Standard channel
Positive reference voltage
Negative reference voltage -
1.14 Msps
Current consumption of the
ADC on V
DDA and V
REF+ 10 ksps
1.14 Msps
Current consumption of the
ADC on V
DD
(2)
10 ksps
Voltage scaling Range 1
ADC clock frequency Voltage scaling Range 2
Voltage scaling Range 3
12-bit resolution f
ADC
= 16 MHz,
12-bit resolution
-
Conversion voltage range -
Min
-
1.65
1.75
(1)
1.65
-
-
-
-
-
0.14
0.14
0.14
0.01
-
0
Typ
-
-
-
-
1
-
-
0
200
40
70
-
-
-
Unit
V
V
µA
MHz
MHz kHz
1/f
ADC
V
Max
-
16
-
-
8
4
1.14
3.6
3.6
V
DDA
-
-
941
17
V
REF+
DS10671 Rev 5
123
Electrical characteristics STM32L083xx
Symbol
Table 64. ADC characteristics (continued)
Parameter Conditions Min Typ Max Unit
R
AIN
(3)
External input impedance
See Equation 1 and
50 k Ω
R
ADC
(3)(4) Sampling switch resistance 1 k Ω
C
ADC
(3)
Internal sample and hold capacitor
8 pF t
CAL
(3)(5) Calibration time f
ADC
= 16 MHz
-
5.2
83
µs
1/f
ADC
ADC clock = HSI16
1.5 ADC cycles + 2 f
PCLK
cycles
f
1.5 ADC cycles + 3
PCLK
cycles
-
W
LATENCY
(6)
ADC_DR register write latency ADC clock = PCLK/2
ADC clock = PCLK/4 -
4.5
8.5
-
f
PCLK cycle f
PCLK cycle t latr
(3)
Trigger conversion latency f
ADC
= f
PCLK
/2 = 16 MHz f
ADC
= f
PCLK
/4 = 8 MHz
0.266
µs f
ADC
= f
PCLK
/2 8.5
0.516
µs f
ADC
= f
PCLK
/4 f
ADC
= f
HSI16
= 16 MHz 0.252
16.5
0.260
1/f
PCLK
µs
Jitter
ADC
ADC jitter on trigger conversion f
ADC
= f
HSI16
1 1/f
HSI16 t
S
(3) t
UP_LDO
t
STAB
Sampling time
Internal LDO power-up time
ADC stabilization time f
ADC
= 16 MHz
-
-
-
0.093
1.5
-
-
-
14
10.03
160.5
10
µs
1/f
ADC
µs
1/f
ADC f
ADC
= 16 MHz,
12-bit resolution
0.875
10.81
µs t
ConV
(3)
Total conversion time
(including sampling time)
12-bit resolution
14 to 173 (t
S
for sampling +12.5 for successive approximation)
1/f
ADC
1. V
DDA
minimum value can be decreased in specific temperature conditions. Refer to
2. A current consumption proportional to the APB clock frequency has to be added (see
Table 40: Peripheral current consumption in Run or Sleep mode
).
3. Guaranteed by design.
4. Standard channels have an extra protection resistance which depends on supply voltage. Refer to
.
5. This parameter only includes the ADC timing. It does not take into account register access latency.
6. This parameter specifies the latency to transfer the conversion result into the ADC_DR register. EOC bit is set to indicate the conversion is complete and has the same latency.
DS10671 Rev 5
STM32L083xx Electrical characteristics
Equation 1: R
AIN
max formula
R
AIN
< f
ADC
× C
T
ADC
S
× ln ( 2 )
– R
ADC
The simplified formula above ( Equation 1 ) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
T s
(cycles) t
S
(µs)
1.5
3.5
7.5
12.5
19.5
39.5
0.09
0.22
0.47
0.78
1.22
2.47
79.5
4.97
160.5
10.03
1. Guaranteed by design.
R
AIN
max for fast channels
(k Ω )
Table 65. R
AIN
max for f
ADC
= 16 MHz (1)
R
AIN
max for standard channels (k Ω )
V
DD
>
2.7 V
V
DD
>
2.4 V
V
DD
>
2.0 V
V
DD
>
1.8 V
V
DD
>
1.75 V
V
DD
> 1.65 V and
T
A
> − 10 °C
0.5
< 0.1
NA NA NA NA NA
V
DD
> 1.65 V and
T
A
> 25 °C
NA
1
2.5
4
6.5
13
27
50
0.2
1.7
3.2
5.7
12.2
26.2
49.2
< 0.1
1.5
3
5.5
12
26
49
NA
< 0.1
1
3.5
10
24
47
NA
NA
NA
NA
NA
< 0.1
32
NA
NA
NA
NA
NA
NA
< 0.1
NA
NA
NA
NA
NA
NA
< 0.1
NA
NA
NA
< 0.1
5
19
42
Table 66. ADC accuracy (1)(2)(3)
Symbol Parameter
ET Total unadjusted error
EO Offset error
EG Gain error
EL Integral linearity error
ED Differential linearity error
Effective number of bits
ENOB
Effective number of bits (16-bit mode oversampling with ratio =256)
(4)
SINAD Signal-to-noise distortion
Signal-to-noise ratio
SNR
Signal-to-noise ratio (16-bit mode oversampling with ratio =256)
THD Total harmonic distortion
Conditions Min Typ
1.65 V < V
DDA range 1/2/3
= V
REF+
< 3.6 V,
-
-
-
-
1
10.2
11
2
1
1
1.5
11.3
12.1
63
63
70
-
69
69
76
-85
Max
4
2.5
2
2.5
1.5
-
-
-
-
-73
Unit
LSB bits dB
DS10671 Rev 5
123
4
3
2
1
7
6
5
0
Electrical characteristics STM32L083xx
Symbol
Table 66. ADC accuracy (1)(2)(3)
(continued)
Parameter Conditions Min Typ Max Unit
ET Total unadjusted error
EO Offset error
EG Gain error
EL Integral linearity error
ED Differential linearity error
ENOB Effective number of bits
SINAD Signal-to-noise distortion
SNR Signal-to-noise ratio
THD Total harmonic distortion
1.65 V < V range 1/2/3
REF+
<V
DDA
< 3.6 V,
-
-
-
-
-
10.0
11.0
62
61
-
2
1
1
1.5
1
69
69
-85
5
2.5
2
3
2
-
-
-
-65
LSB bits dB
1. ADC DC accuracy values are measured after internal calibration.
2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for I accuracy.
INJ(PIN)
and Σ I
INJ(PIN)
in
does not affect the ADC
3. Better performance may be achieved in restricted V
DDA
, frequency and temperature ranges.
4. This number is obtained by the test board without additional noise, resulting in non-optimized value for oversampling mode.
Figure 28. ADC accuracy characteristics
V
SSA
4095
4094
4093
E
O
E
T
E
L
1 LSB
IDEAL
1 2 3 4 5 6
7
(2)
E
D
(3)
(1)
E
G
4093 4094 4095 4096
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
E
T
= total unajusted error : maximum deviation
between the actual and ideal transfer curves.
E
O
= offset error : maximum deviation
between the first actual transition and
the first ideal one.
E
G
= gain error : deviation between the last
ideal transition and the last actual one.
E
D
= differential linearity error : maximum
deviation between actual steps and the ideal ones.
E
L
= integral linearity error : maximum deviation
between any actual transition and the end point
correlation line.
V
DDA
MS19880V2
DS10671 Rev 5
STM32L083xx Electrical characteristics
Figure 29. Typical connection diagram using the ADC
RAIN(1)
VAIN
AINx
Cparasitic
VDDA
VT
VT
IL±50nA
Sample and hold ADC converter
RADC
12-bit converter
CADC
MSv34712V1
1. Refer to Table 64: ADC characteristics
for the values of R
AIN
, R
ADC
and C
ADC
.
2. C parasitic this, f
represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
ADC
should be reduced.
parasitic
value will downgrade conversion accuracy. To remedy
General PCB design guidelines
Power supply decoupling should be performed as shown in
or
, depending on whether V
REF+
is connected to V
DDA
or not. The 10 nF capacitors should be ceramic (good quality). They should be placed as close as possible to the chip.
Figure 30. Power supply and reference decoupling (V
REF+ not connected to V
DDA
)
STM32Lxx
VREF+
1 μF // 100 nF VDDA
1 μF // 100 nF
VSSA / VREF–
MS39601V1
DS10671 Rev 5
123
Electrical characteristics STM32L083xx
Figure 31. Power supply and reference decoupling (V
REF+ connected to V
DDA
)
STM32Lxx
V
REF+
/V
DDA
1 μF // 100 nF
V
REF–
/V
SSA
MS39602V1
DS10671 Rev 5
STM32L083xx Electrical characteristics
Data guaranteed by design, not tested in production, unless otherwise specified.
Symbol
V
DDA
V
REF+
V
REF-
I
DDVREF+
(1)
I
DDA
(2)
R
L
(3)
C
L
(3)
R
O
Parameter
Table 67. DAC characteristics
Conditions
Analog supply voltage -
Reference supply voltage
Lower reference voltage -
V
REF+
must always be below V
DDA
Current consumption on V
REF+ supply
V
REF+
= 3.3 V
No load, middle code
(0x800)
No load, worst code
(0x000)
Current consumption on V supply,
V
DDA
= 3.3 V
Resistive load
Capacitive load
DDA
No load, middle code
(0x800)
No load, worst code
(0xF1C)
DAC output
ON
R
L connected to V
SSA
R
L connected to V
DDA
DAC output buffer ON
Output impedance DAC output buffer OFF
Min
1.8
1.8
-
-
-
-
5
25
-
12
DAC output buffer ON 0.2
Typ
-
-
V
SSA
130
220
210
320
-
-
-
-
16
Max
3.6
3.6
220
350
320
520
-
-
50
20
µA
µA k Ω pF k Ω
V
DDA
– 0.2
V
Unit
V
V
V
V
DAC_OUT
Voltage on DAC_OUT output
DAC output buffer OFF 0.5
-
V
REF+
1LSB
– mV
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Electrical characteristics STM32L083xx
Symbol
DNL
(2)
INL
(2)
Offset
(2)
Offset1
(2)
Gain
(2) dGain/dT
(2)
Gain error temperature coefficient
TUE
(2)
Table 67. DAC characteristics (continued)
Parameter Conditions Min
Differential non linearity
(4)
Integral non linearity
(5)
Offset error at code 0x800
(6)
Offset error at code 0x001
(7) dOffset/dT
(2)
Offset error temperature coefficient (code 0x800)
Gain error
(8)
Total unadjusted error
C
L
≤
L
≥ 5 k Ω
DAC output buffer ON
No R
LOAD
, C
L
≤ 50 pF
DAC output buffer OFF
C
L
≤
L
≥ 5 k Ω
DAC output buffer ON
No R
LOAD
, C
L
≤ 50 pF
DAC output buffer OFF
C
L
≤
L
≥ 5 k Ω
DAC output buffer ON
No R
LOAD
, C
L
≤ 50 pF
DAC output buffer OFF
No R
LOAD
, C
L
≤ 50 pF
DAC output buffer OFF
V
DDA
= 3.3V
V
REF+
= 3.0 V
T
A
= 0 to 50 ° C
DAC output buffer OFF
V
DDA
= 3.3V
V
REF+
= 3.0 V
T
A
= 0 to 50 ° C
DAC output buffer ON
C
L
≤
L
≥ 5 k Ω
DAC output buffer ON
No R
LOAD
, C
L
≤ 50 pF
DAC output buffer OFF
V
DDA
= 3.3V
V
REF+
= 3.0 V
T
A
= 0 to 50 ° C
DAC output buffer OFF
V
DDA
= 3.3V
V
REF+
= 3.0 V
T
A
= 0 to 50 ° C
DAC output buffer ON
C
L
≤
L
≥ 5 k Ω
DAC output buffer ON
No R
LOAD
, C
L
≤ 50 pF
DAC output buffer OFF
-
-
-
-
-
-
-
-20
0
-
Typ Max
3
3
4
4
±25
±8
±5
0
50
+0.1 / -0.2% +0.2 / -0.5%
-10
-40
-
-
1.5
1.5
2
2
±10
±5
±1.5
-10
20
+0 / -0.2% +0 / -0.4%
-2
-8
12
8
0
0
30
12
Unit
LSB
µV/°C
%
µV/°C
LSB
DS10671 Rev 5
STM32L083xx Electrical characteristics
Symbol
Table 67. DAC characteristics (continued)
Parameter Conditions Min Typ Max Unit t t
SETTLING
Update rate
WAKEUP
PSRR+
Settling time (full scale: for a
12-bit code transition between the lowest and the highest input codes till DAC_OUT reaches final value ±1LSB
C
L
≤
L
≥ 5 k Ω
Max frequency for a correct
DAC_OUT change (95% of final value) with 1 LSB variation in the input code
C
L
≤
L
≥ 5 k Ω
Wakeup time from off state
(setting the ENx bit in the DAC
Control register)
(9)
C
L
≤
L
≥ 5 k Ω
V
DDA
supply rejection ratio
(static DC measurement)
C
L
≤
L
≥ 5 k Ω -
-
-
7
-
9
-60
12
1
15
-35
µs
Msps
µs dB
1. Guaranteed by characterization results.
2. Guaranteed by design, not tested in production.
3. Connected between DAC_OUT and V
SSA
.
4. Difference between two consecutive codes - 1 LSB.
5. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095.
6. Difference between the value measured at Code (0x800) and the ideal value = V
REF+
/2.
7. Difference between the value measured at Code (0x001) and the ideal value.
8. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when buffer is OFF, and from code giving 0.2 V and (V
DDA
– 0.2) V when buffer is ON.
9. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).
Figure 32. 12-bit buffered/non-buffered DAC
Buffered/Non-buffered DAC
Buffer
(1)
R L
12-bit digital to analog converter
DAC_OUTx
C L
MSv45341V1
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register.
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Electrical characteristics STM32L083xx
6.3.17 Temperature sensor characteristics
Table 68. Temperature sensor calibration values
Calibration value name Description Memory address
TS_CAL1
TS_CAL2
TS ADC raw data acquired at temperature of 30 °C, V
DDA
= 3 V
TS ADC raw data acquired at temperature of 130 °C, V
DDA
= 3 V
0x1FF8 007A - 0x1FF8 007B
0x1FF8 007E - 0x1FF8 007F
Symbol
Table 69. Temperature sensor characteristics
Parameter Min Typ Max Unit
T
L
(1)
Avg_Slope
(1)
V
SENSE
linearity with temperature
Average slope
Voltage at 130°C ±5°C
(2)
± 1
1.48
1.61
1.75
mV/°C
V
130
I
DDA (TEMP)
(3) t
START
(3)
T
S_temp
(4)(3)
Current consumption
Startup time
ADC sampling time when reading the temperature
640
-
-
10
670
3.4
-
-
1. Guaranteed by characterization results.
2. Measured at V
DD
= 3 V ±10 mV. V130 ADC conversion result is stored in the TS_CAL2 byte.
3. Guaranteed by design.
4. Shortest sampling time can be determined in the application by multiple iterations.
± 2
700
6
10
-
°C mV
µA
µs
6.3.18 Comparators
Symbol Parameter
Table 70. Comparator 1 characteristics
Conditions Min
(1)
Typ Max
(1)
Unit
V
DDA
V
IN
Analog supply voltage
Comparator 1 input voltage range
-
1.65
0.6
V
3.6
DDA
V
V t
START td
Comparator startup time
Propagation delay
Voffset Comparator offset
(2)
-
-
-
-
7
3
10
10
µs d
Voffset
/dt
Comparator offset variation in worst voltage stress conditions
Current consumption
(3)
-
V
DDA
= 3.6 V, V
IN+
V
IN-
= V
REFINT
, T
A
= 0 V,
= 25 ° C
-
-
0
± 3
1.5
± 10
10 mV mV/1000 h
I
COMP1
160 260 nA
1. Guaranteed by characterization.
2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the non-inverting input set to the reference.
3. Comparator consumption only. Internal reference voltage not included.
DS10671 Rev 5
STM32L083xx Electrical characteristics
Symbol t t
V t
DDA
V
IN
START d slow d fast
Table 71. Comparator 2 characteristics
Parameter
Analog supply voltage
Comparator 2 input voltage range
Comparator startup time
Propagation delay
Propagation delay
(2)
(2)
in slow mode
in fast mode
Conditions
Fast mode
Slow mode
-
-
1.65 V ≤
DDA
2.7 V
2.7 V ≤
DDA
3.6 V
1.65 V ≤
DDA
2.7 V
2.7 V ≤
DDA
3.6 V
Min
-
-
-
-
-
1.65
0
-
-
Typ
1.8
2.5
0.8
1.2
± 4
15
20
-
-
Max
(1)
3.6
V
DDA
20
25
3.5
6
2
4
± 20
Unit
V
V
µs
V offset
Comparator offset error mV dThreshold/
I dt
COMP2
Threshold voltage temperature coefficient
Current consumption
(3)
V
DDA
V- = V
= 3.3V, T
A
REFINT
,
3/4 V
1/2 V
REFINT
REFINT
1/4 V
REFINT
.
,
,
= 0 to 50 ° C,
Fast mode
Slow mode
-
-
-
15
3.5
0.5
30
5
2 ppm
/°C
µA
1. Guaranteed by characterization results.
2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the non-inverting input set to the reference.
3. Comparator consumption only. Internal reference voltage (required for comparator operation) is not included.
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Electrical characteristics STM32L083xx
TIM timer characteristics
The parameters given in the
Table 72 are guaranteed by design.
Refer to Section 6.3.13: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Symbol
Table 72. TIMx characteristics (1)
Parameter Conditions Min t res(TIM) f
EXT
Timer resolution time
Timer external clock frequency on CH1 to CH4 f
TIMxCLK
= 32 MHz
-
1
f
TIMxCLK
= 32 MHz 31.25
0
0
Res
TIM t
COUNTER
Timer resolution
16-bit counter clock period when internal clock is selected (timer’s prescaler disabled)
1
f
TIMxCLK
= 32 MHz 0.0312
t
MAX_COUNT
Maximum possible count
f
TIMxCLK
= 32 MHz
1. TIMx is used as a general term to refer to the TIM2, TIM6, TIM21, and TIM22 timers.
-
-
Max Unit
-
f
TIMxCLK
16
16
65536
/2 t
TIMxCLK ns
MHz
MHz bit t
TIMxCLK
µs 2048
65536 × 65536 t
TIMxCLK
134.2
s
I
2
C interface characteristics
The I
2
C interface meets the timings requirements of the I
2
C-bus specification and user manual rev. 03 for:
• Standard-mode (Sm) : with a bit rate up to 100 kbit/s
• Fast-mode (Fm) : with a bit rate up to 400 kbit/s
• Fast-mode Plus (Fm+) : with a bit rate up to 1 Mbit/s.
The I
2
C timing requirements are guaranteed by design when the I
2
C peripheral is properly configured (refer to the reference manual for details). The SDA and SCL I/O requirements are met with the following restrictions: the SDA and SCL I/O pins are not "true" open-drain.
When configured as open-drain, the PMOS connected between the I/O pin and VDDIOx is disabled, but is still present. Only FTf I/O pins support Fm+ low level output current maximum requirement (refer to
Section 6.3.13: I/O port characteristics
for the I2C I/Os characteristics).
All I
2
C SDA and SCL I/Os embed an analog filter (see
for the analog filter characteristics).
DS10671 Rev 5
STM32L083xx
Note:
Electrical characteristics
The analog spike filter is compliant with I
2
C timings requirements only for the following voltage ranges:
• Fast mode Plus: 2.7 V ≤ V
DD
≤ 3.6 V and voltage scaling Range 1
• Fast mode:
– 2 V ≤ V
DD
3.6 V and voltage scaling Range 1 or Range 2.
– V
DD
< 2 V, voltage scaling Range 1 or Range 2, C load
< 200 pF.
In other ranges, the analog filter should be disabled. The digital filter can be used instead.
In Standard mode, no spike filter is required.
Symbol
Table 73. I2C analog filter characteristics (1)
Parameter Conditions t
AF
Maximum pulse width of spikes that are suppressed by the analog filter
Range 1
Range 2
Range 3
1. Guaranteed by characterization results.
2. Spikes with widths below t
AF(min) are filtered.
3. Spikes with widths above t
AF(max)
are not filtered
Min
50 (2)
Max
100
(3)
-
-
Unit ns
SPI characteristics
Unless otherwise specified, the parameters given in the following tables are derived from tests performed under ambient temperature, f
conditions summarized in Table 26
.
PCLKx frequency and V
DD
supply voltage
Refer to Section 6.3.12: I/O current injection characteristics for more details on the
input/output alternate function characteristics (NSS, SCK, MOSI, MISO).
Symbol f
SCK
1/t c(SCK)
Duty
(SCK)
Table 74. SPI characteristics in voltage Range 1 (1)
Parameter Conditions Min Typ
SPI clock frequency
Master mode
Slave mode receiver
Slave mode
Transmitter
1.71<V
DD
<3.6V
Slave mode
Transmitter
2.7<V
DD
<3.6V
-
-
-
-
-
-
Duty cycle of SPI clock frequency
Slave mode 30 50
Max
16
16
12
(2)
16 (2)
70
Unit
MHz
%
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Electrical characteristics STM32L083xx
Symbol
Table 74. SPI characteristics in voltage Range 1 (1) (continued)
Parameter Conditions Min Typ Max Unit t t su(NSS) h(NSS)
NSS setup time
NSS hold time
Slave mode, SPI presc = 2
Slave mode, SPI presc = 2
4*Tpclk
2*Tpclk -
-
-
t w(SCKH) t w(SCKL) t su(MI) t su(SI) t h(MI) t h(SI) t a(SO t dis(SO)
SCK high and low time
Data input setup time
Data input hold time
Data output access time
Data output disable time
Master mode
Master mode
Slave mode
Master mode
Slave mode
Slave mode
Slave mode
Tpclk-2
0
3
7
3.5
15
10
Tpclk
-
-
-
-
-
-
Tpclk+
2
-
-
-
-
36
30 ns t v(SO)
Data output valid time
Slave mode
1.65 V<V
DD
<3.6 V
Slave mode
2.7 V<V
DD
<3.6 V
Master mode
-
18
18
41
25 t v(MO) t h(SO) t h(MO)
Data output hold time
Slave mode
Master mode
-
10
0
4
-
-
7
-
-
1. Guaranteed by characterization results.
2. The maximum SPI clock frequency in slave transmitter mode is determined by the sum of t v(SO)
and t su(MI) which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master having t su(MI)
= 0 while Duty
(SCK)
= 50%.
DS10671 Rev 5
STM32L083xx Electrical characteristics
Symbol
Table 75. SPI characteristics in voltage Range 2 (1)
Parameter Conditions Min Typ Max Unit
1/t f
SCK c(SCK)
SPI clock frequency
Master mode
Slave mode Transmitter
1.65<V
DD
<3.6V
Slave mode Transmitter
2.7<V
DD
<3.6V
-
8
8
8
(2)
MHz
Duty
(SCK)
Duty cycle of SPI clock frequency
NSS setup time
Slave mode 30 50 70 % t su(NSS) t h(NSS) t w(SCKH) t w(SCKL) t su(MI) t su(SI) t h(MI) t h(SI) t a(SO t dis(SO)
NSS hold time
SCK high and low time
Data input setup time
Data input hold time
Data output access time
Data output disable time
Slave mode, SPI presc = 2
Slave mode, SPI presc = 2
Master mode
Master mode
Slave mode
Master mode
Slave mode
Slave mode
Slave mode
4*Tpclk
2*Tpclk
Tpclk-2
0
3
11
4.5
18
12
Tpclk
-
-
-
-
-
-
-
-
-
-
-
-
Tpclk+2
-
-
52
42 t v(SO) t v(MO) t h(SO) t h(MO)
Data output valid time
Data output hold time
Slave mode
Master mode
Slave mode
Master mode
-
-
13
3
20
5
-
-
56.5
9
-
-
1. Guaranteed by characterization results.
2. The maximum SPI clock frequency in slave transmitter mode is determined by the sum of t with a master having t su(MI)
= 0 while Duty
(SCK)
= 50%.
v(SO)
and t su(MI)
which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates ns
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Electrical characteristics STM32L083xx
Symbol
Table 76. SPI characteristics in voltage Range 3 (1)
Parameter Conditions Min Typ Max Unit
f
1/t
SCK c(SCK)
SPI clock frequency
Master mode
Slave mode
-
2
2
(2)
MHz
Duty
(SCK)
Duty cycle of SPI clock frequency
Slave mode 30 50 70 % t su(NSS) t h(NSS) t w(SCKH) t w(SCKL) t su(MI) t su(SI) t h(MI) t h(SI) t a(SO t dis(SO)
NSS setup time
NSS hold time
SCK high and low time
Data input setup time
Data input hold time
Data output access time
Data output disable time
Slave mode, SPI presc = 2
Slave mode, SPI presc = 2
Master mode
Master mode
Slave mode
Master mode
Slave mode
Slave mode
Slave mode
4*Tpclk
2*Tpclk
Tpclk-2
1.5
6
13.5
16
30
40
-
-
Tpclk
-
-
-
-
-
-
Tpclk+2
-
-
-
-
-
-
70
80 ns t v(SO)
Slave mode 30 70
Data output valid time t v(MO) t h(SO) t h(MO)
Data output hold time
Master mode
Slave mode
Master mode
-
25
8
7
-
-
9
-
-
1. Guaranteed by characterization results.
2. The maximum SPI clock frequency in slave transmitter mode is determined by the sum of t with a master having t su(MI)
= 0 while Duty
(SCK)
= 50%.
v(SO)
and t su(MI)
which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates
DS10671 Rev 5
STM32L083xx Electrical characteristics
Figure 33. SPI timing diagram - slave mode and CPHA = 0
NSS input t w(SCKH) t c(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1 t a(SO)
MISO output t su(NSS) t w(SCKL)
First bit OUT t h(SI) t v(SO) t su(SI)
MOSI input First bit IN t h(SO)
Next bits OUT
Next bits IN t r(SCK) t h(NSS) t f(SCK)
Last bit OUT t dis(SO)
Last bit IN
MSv41658V1
Figure 34. SPI timing diagram - slave mode and CPHA = 1 (1)
NSS input t su(NSS) t w(SCKH) t c(SCK) t f(SCK) t h(NSS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
MISO output
MOSI input t a(SO) t w(SCKL) t v(SO)
First bit OUT t su(SI) t h(SI)
First bit IN t h(SO)
Next bits OUT
Next bits IN t r(SCK) t dis(SO)
Last bit OUT
Last bit IN
MSv41659V1
1. Measurement points are done at CMOS levels: 0.3V
DD
and 0.7V
DD.
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Electrical characteristics
Figure 35. SPI timing diagram - master mode (1)
NSS input
High tc(SCK)
CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
MISO
INP UT
MOSI
OUTPUT tsu(MI) tw(SCKH) tw(SCKL)
MSB IN th(MI)
MSB OUT tv(MO)
BIT6 IN
B I T1 OUT th(MO)
1. Measurement points are done at CMOS levels: 0.3V
DD
and 0.7V
DD.
tr(SCK) tf(SCK)
LSB IN
LSB OUT
STM32L083xx ai14136d
DS10671 Rev 5
STM32L083xx Electrical characteristics
I2S characteristics
Table 77. I2S characteristics
(1)
Symbol Parameter Conditions f
MCK f
CK
I2S Main clock output
I2S clock frequency
-
Master data: 32 bits
Slave data: 32 bits
D
CK
I2S clock frequency duty cycle
Slave receiver t v(WS) t h(WS) t su(WS) t h(WS) t su(SD_MR) t su(SD_SR) t h(SD_MR) t h(SD_SR) t v(SD_ST) t v(SD_MT) t h(SD_ST) t h(SD_MT)
WS valid time
WS hold time
WS setup time
WS hold time
Data input setup time
Data input hold time
Data output valid time
Data output hold time
Master mode
Master mode
Slave mode
Slave mode
Master receiver
Slave receiver
Master receiver
Slave receiver
Slave transmitter (after enable edge)
Master transmitter (after enable edge)
Slave transmitter (after enable edge)
Master transmitter (after enable edge)
1. Guaranteed by characterization results.
2. 256xFs maximum value is equal to the maximum clock frequency.
256 x 8K 256xFs
(2)
-
64xFs
64xFs
30
6.5
18
15.5
-
-
6
2
-
11
0
18
1.5
70
-
-
-
77
8
-
-
-
-
15
-
-
MHz
MHz
% ns
Note: Refer to the I2S section of the product reference manual for more details about the sampling frequency (Fs), f
MCK
, f
CK
and D
CK
values. These values reflect only the digital peripheral behavior, source clock precision might slightly change them. DCK depends mainly on the
ODD bit value, digital contribution leads to a min of (I2SDIV/(2*I2SDIV+ODD) and a max of
(I2SDIV+ODD)/(2*I2SDIV+ODD). Fs max is supported for each mode/condition.
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Electrical characteristics
Figure 36. I 2 S slave timing diagram (Philips protocol) (1)
STM32L083xx
1. Measurement points are done at CMOS levels: 0.3 × V
DD and 0.7 × V
DD
.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.
Figure 37. I 2 S master timing diagram (Philips protocol) (1)
1. Guaranteed by characterization results.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.
DS10671 Rev 5
STM32L083xx Electrical characteristics
USB characteristics
The USB interface is USB-IF certified (full speed).
Symbol
Table 78. USB startup time
Parameter t
STARTUP
(1)
USB transceiver startup time
1. Guaranteed by design.
Max
1
Unit
µs
Symbol
Table 79. USB DC electrical characteristics
Parameter Conditions Min.
(1)
Input levels
V
DD
V
DI
(2)
V
CM
(2)
V
SE
(2)
USB operating voltage
Differential input sensitivity I(USB_DP, USB_DM)
Differential common mode range Includes V
Single ended receiver threshold
Output levels
-
DI range
-
V
OL
(3)
V
OH
(3)
Static output level low
Static output level high
R
L
R
L
of 1.5
k Ω to 3.6 V
of 15 k Ω to V
SS
1. All the voltages are measured from the local ground potential.
2. Guaranteed by characterization results.
3. Guaranteed by test in production.
4. R
L
is the load connected on the USB drivers.
(4)
(4)
3.0
0.2
0.8
1.3
-
2.8
Max.
(1) Unit
3.6
-
2.5
2.0
0.3
3.6
Figure 38. USB timings: definition of data signal rise and fall time
V
V
V
Cross over points
Differential data lines
V
CRS
V
SS t f t r ai14137b
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Electrical characteristics STM32L083xx
Table 80. USB: full speed electrical characteristics
Driver characteristics
(1)
Symbol Parameter Conditions Min Max t r t f t rfm
V
CRS
Rise time
Fall Time
(2)
(2)
Rise/ fall time matching
Output signal crossover voltage
C
L
C
L
= 50 pF
= 50 pF t r
/t f
4
4
90
1.3
20
20
110
2.0
1. Guaranteed by design.
2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
Unit ns ns
%
V
Symbol
V
LCD
V
LCD0
V
LCD1
V
LCD2
V
LCD3
V
LCD4
V
LCD5
V
LCD6
V
LCD7
C ext
The devices embed a built-in step-up converter to provide a constant LCD reference voltage independently from the V
DD
V
LCD
voltage. An external capacitor C
pin to decouple this converter.
ext
must be connected to the
I
LCD
(1)
R
Htot
(2)
R
L
(2)
V
44
Table 81. LCD controller characteristics
Parameter Min Typ
LCD external voltage
LCD internal reference voltage 0
LCD internal reference voltage 1
LCD internal reference voltage 2
LCD internal reference voltage 3
LCD internal reference voltage 4
LCD internal reference voltage 5
LCD internal reference voltage 6
LCD internal reference voltage 7
V
LCD
external capacitance
Supply current at V
DD
= 2.2 V
Supply current at V
DD
= 3.0 V
Low drive resistive network overall value
High drive resistive network total value
Segment/Common highest level voltage
-
0.1
-
-
5.28
192
-
-
-
-
-
-
-
-
-
3.55
-
3.3
3.1
6.6
240
-
-
2.6
2.73
2.86
2.98
3.12
3.26
3.4
Unit
V
µF
µA
M Ω k Ω
V
Max
-
7.92
288
V
LCD
-
2
-
-
-
3.6
-
-
-
-
-
DS10671 Rev 5
STM32L083xx Electrical characteristics
Symbol
Table 81. LCD controller characteristics (continued)
Parameter Min Typ Max Unit
V
34
V
23
V
12
V
13
V
14
V
0
Segment/Common 3/4 level voltage
Segment/Common 2/3 level voltage
Segment/Common 1/2 level voltage
Segment/Common 1/3 level voltage
Segment/Common 1/4 level voltage
Segment/Common lowest level voltage
-
-
-
-
-
0
3/4 V
2/3 V
1/2 V
1/3 V
1/4 V
-
LCD
LCD
LCD
LCD
LCD
-
-
-
-
-
-
V
Δ Vxx
(3)
Segment/Common level voltage error
T
A
= -40 to 85 ° C
± 50 mV
1. LCD enabled with 3 V internal step-up active, 1/8 duty, 1/4 bias, division ratio= 64, all pixels active, no LCD connected.
2. Guaranteed by design.
3. Guaranteed by characterization results.
DS10671 Rev 5
123
Package information STM32L083xx
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at www.st.com
.
ECOPACK is an ST trademark.
Figure 39. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline
SEATING PLANE
C c
0.25 mm
GAUGE PLANE ccc C
D
D1
D3
L1
L K
76
75 51
50
100
PIN 1
IDENTIFICATION
1 e
25
26
1L_ME_V5
1. Drawing is not to scale. Dimensions are in millimeters.
Table 82. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data millimeters inches
(1)
Symbol
Min Typ Max Min Typ Max
A
A1
-
0.050
-
1.600
0.150
-
0.0020
-
0.0630
0.0059
DS10671 Rev 5
STM32L083xx Package information
Table 82. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data (continued) millimeters inches (1)
Symbol
Min Typ Max Min Typ Max e
L
E1
E3
L1 k ccc
D
D1
D3
E
A2 b c
1.350
0.170
0.090
15.800
13.800
-
15.800
13.800
-
-
0.450
-
0.0°
-
1.400
0.220
-
16.000
14.000
12.000
16.000
14.000
12.000
0.500
0.600
1.000
3.5°
-
1.450
0.270
0.200
16.200
14.200
-
16.200
14.200
-
-
0.750
-
7.0°
0.080
1. Values in inches are converted from mm and rounded to 4 decimal digits.
0.5433
-
-
0.0177
-
0.0°
-
0.0531
0.0067
0.0035
0.6220
0.5433
-
0.6220
0.5512
0.4724
0.0197
0.0236
0.0394
3.5°
-
0.0551
0.0087
-
0.6299
0.5512
0.4724
0.6299
0.5591
-
-
0.0295
-
7.0°
0.0031
0.0571
0.0106
0.0079
0.6378
0.5591
-
0.6378
Figure 40. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint
75 51
76 50
0.5
0.3
16.7
14.3
100
1
1. Dimensions are expressed in millimeters.
DS10671 Rev 5
12.3
16.7
25
26
1.2
ai14906c
144
Package information STM32L083xx
Device marking for LQFP100
The following figure gives an example of topside marking versus pin 1 position identifier location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below.
Figure 41. LQFP100 marking example (package top view)
Product identification
(1)
STM32L083
VZT6 R
Revision code
Date code
Y WW
Pin 1 indentifier
MSv37842V1
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.
DS10671 Rev 5
STM32L083xx
7.2
Package information
UFBGA100 package information
Figure 42. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package outline
Z Seating plane ddd Z
A4
A3 A2 e
E1
Z
A1 A
A1 ball identifier
A1 ball index area
X
E
A
Z
D1 D
M e
12
Y
BOTTOM VIEW
1
Øb (100 balls)
Ø eee
M Z Y X
Ø fff M Z
TOP VIEW
A0C2_ME_V5
1. Drawing is not to scale.
Table 83. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data millimeters inches
(1)
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
A -
A1 -
A2 -
A3 -
-
0.110 -
0.450 -
0.130
-
-
-
-
-
0.0177
0.0236
0.0043
-
0.0051
0.0094
0.0126 -
0.2165 -
0.2165 e - -
Z 0.750 0.0295 -
DS10671 Rev 5
144
Package information STM32L083xx
Table 83. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) millimeters inches (1)
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
ddd eee fff -
-
-
-
0.080
0.150
0.050
-
-
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
-
-
0.0031
0.0059
0.0020
Figure 43. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package recommended footprint
Dpad
Dsm
A0C2_FP_V1
Pitch
Dpad
Dsm
Table 84. UFBGA100 recommended PCB design rules (0.5 mm pitch BGA)
Dimension Recommended values
Stencil opening
Stencil thickness
0.5
0.280 mm
0.370 mm typ. (depends on the soldermask registration tolerance)
0.280 mm
Between 0.100 mm and 0.125 mm
DS10671 Rev 5
STM32L083xx Package information
Device marking for UFBGA100
The following figure gives an example of topside marking versus ball A 1 position identifier location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below.
Figure 44. UFBGA100 marking example (package top view)
Product identification
(1)
STM32L
083VZI6
Ball 1 indentifier
Date code
Y WW
R
Revision code
MSv40301V1
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.
DS10671 Rev 5
144
Package information
7.3 LQFP64 package information
STM32L083xx
Figure 45. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline
SEATING PLANE
C
0.25 mm
GAUGE PLANE ccc C
D
D1
D3 L1
L
K
48 33
32 b
49
64 17
PIN 1
IDENTIFICATION
1 e
16
5W_ME_V3
D
D1 b c
A
A1
A2
D3
E
E1
1. Drawing is not to scale.
Table 85. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data millimeters inches
(1)
Symbol
Min Typ
-
0.050
1.350
-
-
1.400
0.170
0.090
0.220
-
- 12.000
10.000
-
-
-
7.500
12.000
10.000
Max
1.600
0.150
1.450
0.270
0.200
-
-
-
-
-
Min
-
0.0020
0.0531
0.0067
0.0035
-
-
-
-
-
Typ
-
-
0.0551
0.0087
-
0.4724
0.3937
0.2953
0.4724
0.3937
Max
0.0630
0.0059
0.0571
0.0106
0.0079
-
-
-
-
-
DS10671 Rev 5
STM32L083xx Package information
Table 85. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data (continued) millimeters inches (1)
Symbol
Min Typ Max Min
L
L1 ccc
E3 e
K
-
-
0°
0.450
-
-
7.500
0.500
3.5°
0.600
1.000
-
-
-
7°
0.750
-
0.080
1. Values in inches are converted from mm and rounded to 4 decimal digits.
-
-
0°
0.0177
-
-
Typ
0.2953
0.0197
3.5°
0.0236
0.0394
-
Max
-
-
7°
0.0295
-
0.0031
Figure 46. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat recommended footprint
48
0.5
33
32
0.3
49
12.7
10.3
64
10.3
17
1.2
1
7.8
12.7
16 ai14909c
1. Dimensions are expressed in millimeters.
DS10671 Rev 5
144
Package information STM32L083xx
Device marking for LQFP64
The following figure gives an example of topside marking versus pin 1 position identifier location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below.
Figure 47. LQFP64 marking example (package top view)
Product identification
(1)
R
STM32L
083RZT6
Revision code
Date code
Y WW
Pin 1 identifier
MSv37840V1
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.
DS10671 Rev 5
STM32L083xx
7.4
Package information
TFBGA64 package information
Figure 48. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch thin profile fine pitch ball grid array package outline
A E1
E e F
H
F
B
D
Øb (64 balls)
Ø
Ø eee fff
M
M
C B A
C
A e
D1
1 8
TOP VIEW
A1 ball index area
A1 ball identifier
BOTTOM VIEW
C Seating plane ddd C
A4
A2
SIDE VIEW
A1 A
R8_ME_V4
1. Drawing is not to scale.
Table 86. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch thin profile fine pitch ball grid array package outline millimeters inches
(1)
Symbol
Min Typ Max Min Typ Max
A4 b
D
D1
A
A1
A2
E
E1 e
F
-
0.150
-
-
0.250
4.850
-
4.850
-
-
-
-
-
0.200
-
0.300
5.000
3.500
5.000
3.500
0.500
0.750
1.200
-
-
0.600
0.350
5.150
-
5.150
-
-
-
-
0.0059
-
-
0.0098
0.1909
-
0.1909
-
-
-
-
-
0.0079
-
0.0118
0.1969
0.1378
0.1969
0.1378
0.0197
0.0295
0.0472
-
-
0.0236
0.0138
0.2028
-
0.2028
-
-
-
DS10671 Rev 5
144
Package information STM32L083xx
Table 86. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch thin profile fine pitch ball grid array package outline (continued) millimeters inches (1)
Symbol
Min Typ Max Min Typ Max ddd eee fff -
-
-
-
-
0.080
0.150
0.050
-
-
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
-
-
0.0031
0.0059
0.0020
Figure 49. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch, thin profile fine pitch ball
,grid array recommended footprint
Dpad
Dsm
R8_FP_V1
Pitch
Dpad
Dsm
Table 87. TFBGA64 recommended PCB design rules (0.5 mm pitch BGA)
Dimension Recommended values
Stencil opening
Stencil thickness
Pad trace width
0.5
0.280 mm
0.370 mm typ. (depends on the soldermask registration tolerance)
0.280 mm
Between 0.100 mm and 1.125 mm
0.100 mm
DS10671 Rev 5
STM32L083xx Package information
Device marking for TFBGA64
The following figure gives an example of topside marking versus ball A 1 position identifier location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below.
Figure 50. TFBGA64 marking example (package top view)
Product identification
(1)
E083RZH6
Ball A1
Date code = Year + week
Y WW
R
Revision code
MSv37818V1
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.
DS10671 Rev 5
144
Package information
7.5 LQFP48 package information
STM32L083xx
Figure 51. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline
SEATING
PLANE
C ccc C b
37
36
D
D1
D3
25
24
0.25 mm
GAUGE PLANE
K
L1
L
48
PIN 1
IDENTIFICATION
1
1. Drawing is not to scale.
12 e
13
5B_ME_V2
DS10671 Rev 5
STM32L083xx Package information
Table 88. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data millimeters inches
(1)
Symbol
Min Typ Max Min Typ Max e
L
L1
D3
E
E1
E3 k ccc b c
D
D1
A
A1
A2
-
0.050
1.350
0.170
0.090
8.800
6.800
-
8.800
6.800
-
-
0.450
-
0°
-
-
-
1.400
0.220
-
9.000
7.000
5.500
9.000
7.000
5.500
0.500
0.600
1.000
3.5°
-
1.600
0.150
1.450
0.270
0.200
9.200
7.200
-
9.200
7.200
-
-
0.750
-
7°
0.080
1. Values in inches are converted from mm and rounded to 4 decimal digits.
-
0.3465
0.2677
-
-
0.0177
-
0°
-
-
0.0020
0.0531
0.0067
0.0035
0.3465
0.2677
0.2165
0.3543
0.2756
0.2165
0.0197
0.0236
0.0394
3.5°
-
-
-
0.0551
0.0087
-
0.3543
0.2756
-
0.3622
0.2835
-
-
0.0295
-
7°
0.0031
0.0630
0.0059
0.0571
0.0106
0.0079
0.3622
0.2835
Figure 52. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat recommended footprint
0.50
1.20
0.30
37
36 25
24
0.20
7.30
9.70
5.80
7.30
48
1
13
12
1.20
5.80
9.70
ai14911d
1. Dimensions are expressed in millimeters.
DS10671 Rev 5
144
Package information STM32L083xx
Device marking for LQFP48
The following figure gives an example of topside marking versus pin 1 position identifier location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below.
Figure 53. LQFP48 marking example (package top view)
Product identification
(1)
STM32L
083CBT6
Date code
Y WW
Revision code
Pin 1 indentifier
R
MSv40302V1
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.
DS10671 Rev 5
STM32L083xx
7.6
Package information
UFQFPN48 package information
Figure 54. UFQFPN48 - 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package outline
Pin 1 identifier laser marking area
D
E E
T e b
Detail Y ddd
A
A1
Seating plane
D
Y
Exposed pad area
D2
1
C 0.500x45° pin1 corner
48
Detail Z
L
R 0.125 typ.
E2
1
48
Z
A0B9_ME_V3
1. Drawing is not to scale.
2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this back-side pad to PCB ground.
DS10671 Rev 5
144
Package information STM32L083xx
Table 89. UFQFPN48 - 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data millimeters inches
(1)
Symbol
Min Typ Max Min Typ Max
E
D2
E2
L
A
A1
D
T b e ddd
0.500
0.000
6.900
6.900
5.500
5.500
0.300
-
0.200
-
-
0.550
0.020
7.000
7.000
5.600
5.600
0.400
0.152
0.250
0.500
-
0.600
0.050
7.100
7.100
5.700
5.700
0.500
-
0.300
-
0.080
1. Values in inches are converted from mm and rounded to 4 decimal digits.
0.0197
0.0000
0.2717
0.2717
0.2165
0.2165
0.0118
-
0.0079
-
-
0.0217
0.0008
0.2756
0.2756
0.2205
0.2205
0.0157
0.0060
0.0098
0.0197
-
0.0236
0.0020
0.2795
0.2795
0.2244
0.2244
0.0197
-
0.0118
-
0.0031
Figure 55. UFQFPN48 - 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package recommended footprint
7.30
6.20
1
48 37
36
7.30
6.20
0.20
0.30
0.55
12
13
5.60
5.80
1. Dimensions are expressed in millimeters.
5.60
0.50
24
25
0.75
5.80
A0B9_FP_V2
DS10671 Rev 5
STM32L083xx Package information
Device marking for UFQFPN48
The following figure gives an example of topside marking versus pin 1 position identifier location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below.
Figure 56. UFQFPN48 marking example (package top view)
Product identification
(1)
STM32L083
CZU6
Pin 1 indentifier
Date code
Y WW
R
Revision code
MSv63964V1
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.
DS10671 Rev 5
144
Package information STM32L083xx
The maximum chip-junction temperature, T
J using the following equation:
max, in degrees Celsius, may be calculated
T
J
max = T
A
max + (P
D
max × Θ
JA
)
Where:
• T
A
max is the maximum ambient temperature in ° C,
• Θ
JA
is the package junction-to-ambient thermal resistance, in ° C/W,
• P
D
max is the sum of P
INT
max and P
I/O max (P
D
max = P
INT
max + P
I/O max),
• P
INT
max is the product of I
DD and internal power.
V
DD
, expressed in Watts. This is the maximum chip
P
I/O
max represents the maximum power dissipation on output pins where:
P
I/O
max = Σ (V
OL
× I
OL
) + Σ ((V
DD
– V
OH
) × I
OH
), taking into account the actual V
OL application.
/ I
OL
and V
OH
/ I
OH of the I/Os at low and high level in the
Symbol
Θ
JA
Table 90. Thermal characteristics
Parameter
Thermal resistance junction-ambient
LQFP48 - 7 x 7 mm / 0.5 mm pitch
Thermal resistance junction-ambient
UFQFPN48 - 7 x 7 mm / 0.5 mm pitch
Thermal resistance junction-ambient
LQFP64 - 10 x 10 mm / 0.5 mm pitch
Thermal resistance junction-ambient
TFBGA64 - 5 x 5 mm / 0.5 mm pitch
Thermal resistance junction-ambient
LQFP100 - 14 x 14 mm / 0.5 mm pitch
Thermal resistance junction-ambient
UFBGA100 - 7 x 7 mm / 0.5 mm pitch
Value
54
28
46
64
41
57
Unit
°C/W
DS10671 Rev 5
STM32L083xx
Figure 57. Thermal resistance
PD (mW)
2500
2000
1500
1000
500
0
4000
3500
3000
125 100 75 50
Temperature (°C)
25 0
Package information
UFQFPN48
LQFP48
LQFP64
TFBGA64
LQFP100
UFBGA100
MSv35433V5
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
DS10671 Rev 5
144
Ordering information STM32L083xx
Example: STM32 L 083 R Z T 6 D TR
Device family
STM32 = Arm-based 32-bit microcontroller
Product type
L = Low power
Device subfamily
083 = USB + LCD + AES
Pin count
C = 48/49 pins
R = 64 pins
V = 100 pins
Flash memory size
8 = 64 Kbytes
B = 128 Kbytes
Z = 192 Kbytes
Package
T = LQFP
H = TFBGA
I = UFBGA
U = UFQFPN
Temperature range
6 = Industrial temperature range, –40 to 85 °C
7 = Industrial temperature range, –40 to 105 °C
3 = Industrial temperature range, –40 to 125 °C
Options
No character = V
DD
range: 1.8 to 3.6 V and BOR enabled
D = V
DD
range: 1.65 to 3.6 V and BOR disabled
Packing
TR = tape and reel
No character = tray or tube
For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office.
DS10671 Rev 5
STM32L083xx Revision history
Date
03-Aug-2015
26-Oct-2015
Revision
Table 91. Document revision history
Changes
1
2
Initial release
Added UFBGA100 package.
Changed confidentiality level to public.
Updated datasheet status to “production data”.
Modified ultra-low-power platform features on cover page.
Changed LCD_VLCD1 into LCD_VLCD2 in Section 3.13.2: V
In
Section 6: Electrical characteristics , updated notes related to
values guaranteed by characterization.
Updated | Δ V
SS
| definition to include V
REF-
in
Added Σ V
DD_USB and updated Σ I
IO(PIN) in
Updated Table 56: EMI characteristics .
Updated f
TRIG
and V
AIN
maximum value, added V
REF+
and V
REF-
in
.
Updated Figure 56: UFQFPN48 marking example (package top view) .
DS10671 Rev 5
148
Revision history STM32L083xx
Date
22-Mar-2016
Table 91. Document revision history (continued)
Revision Changes
3
Updated number of SPIs on cover page and in
Table 2: Ultra-lowpower STM32L083xxx device features and peripheral counts
.
Changed minimum comparator supply voltage to 1.65 V on cover page. Added minimum DAC supply voltage on cover page.
Added number of fast and standard channels in Section 3.12:
Analog-to-digital converter (ADC)
.
Updated Section 3.19.2: Universal synchronous/asynchronous receiver transmitter (USART)
and Section 3.19.4: Serial peripheral interface (SPI)/Inter-integrated sound (I2S)
to mention the fact that
USARTs with synchronous mode feature can be used as SPI master interfaces.
Added baudrate allowing to wake up the MCU from Stop mode in
Section 3.19.2: Universal synchronous/asynchronous receiver transmitter (USART) and
Section 3.19.3: Low-power universal asynchronous receiver transmitter (LPUART)
.
Section 6.3.15: 12-bit ADC characteristics :
–
Table 64: ADC characteristics :
Distinction made between V
DDA
for fast and standard channels;
related to R
ADC
Updated f
Updated t
TRIG
..
S and t
CONV
.
.
– Updated equation 1 description.
ADC
= 16 MHz and distinction made between fast and standard channels.
Updated R
O
and added Note
.
Added Table 71: USART/LPUART characteristics .
DS10671 Rev 5
STM32L083xx Revision history
Date
12-Sep-2017
Table 91. Document revision history (continued)
Revision Changes
4
Memories and I/Os moved after Core in Features
.
and added note related to GPIO speed.
Updated V
DD_USB
in
Section 3.4.1: Power supply schemes .
In
, renamed USB_OE into USB_NOE.
In
, replaced memory mapping schematic by reference to the reference manual.
Added mission profile compliance with JEDEC JESD47 in
Section 6.2: Absolute maximum ratings .
Updated minimum and maximum values of I/O weak pull-up equivalent resistor (R
PU
) and weak pull-down equivalent resistor
(R
PD
) in Table 60: I/O static characteristics .
Updated minimum and maximum values of NRST weak pull-up equivalent resistor (R
PU
) in Table 63: NRST pin characteristics
.
Added note 2 . related to the position of the external capacitor below
Figure 27: Recommended NRST pin protection
.
Updated R
AIN
in Table 64: ADC characteristics
.
Updated Figure 32: 12-bit buffered/non-buffered DAC and added
note below figure.
Updated t
AF
maximum value for range 1 in
Table 73: I2C analog filter characteristics .
Removed Table 90: USART/LPUART characteristics .
NSS timing waveforms updated in Figure 33: SPI timing diagram - slave mode and CPHA = 0
and
Figure 34: SPI timing diagram - slave mode and CPHA = 1
.
.
Added reference to optional marking or inset/upset marks in all package device marking sections. Updated note below marking schematics.
DS10671 Rev 5
148
Revision history STM32L083xx
Date
14-Nov-2019
Table 91. Document revision history (continued)
Revision Changes
5
Updated Arm logo and added Arm word mark notice in
Removed Cortex logo.
Updated Table 5: Functionalities depending on the working mode
(from Run/active down to standby) to change I2C functionality to
disabled in Low-power Run and Low-power Sleep modes.
Updated V
DD_USB
.
description in
Replaced LCD_VLCD2 by LCD_VLCD1 in
Section 3.13.2: V voltage monitoring .
Changed USARTx_RTS, USARTx_RTS_DE into
USARTx_RTS/USARTx_DE, and LPUART1_RTS,
LPUART1_RTS_DE into LPUART1_RTS/LPUART1_DE in
and in all alternate function tables. In
Table 16: STM32L083xx pin definition changed PB2 and PB12/PE11
additional functions to LCD_VLCD2 and LCD_VLCD1, respectively.
Updated V
DD_USB
.
in Table 26: General operating
Removed R
10K and R
400K from
Updated t
AF
maximum value for range 1 in
Table 73: I2C analog filter characteristics .
Updated paragraph introducing all package marking schematics to add the new sentence “The printed markings may differ depending on the supply chain.”
DS10671 Rev 5
STM32L083xx
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