The M95M01 devices can operate with a supply range from 2.5 V up to 5.5 V, and are guaranteed over the -40 °C/+125 °C temperature range. They are compliant with the

Automotive standard AEC-Q100 Grade 1.

Figure 1.

Logic diagram

VCC

HOLD

M95xxx

VSS

AI01789C

The SPI bus signals are C, D and Q, as shown in

Figure 1 and Table 1

. The device is selected when Chip Select (S) is driven low. Communications with the device can be interrupted when the HOLD is driven low.

Table 1.

Signal names

Signal name

Serial Clock

Serial Data Input

Serial Data Output

Chip Select

Write Protect

HOLD Hold

Supply voltage

Ground

Function

Input

Output

Input

Direction

6/37 Doc ID 023153 Rev 1

M95M01-125 Description

Figure 2.

8-pin package connections (top view)

M95xxx

VSS

AI01790D

VCC

HOLD

See

Section 10: Package mechanical data section for package dimensions, and how to identify pin 1.

Obsolete Product(s) - Obsolete Product(s)

Doc ID 023153 Rev 1 7/37

Memory organization M95M01-125

The memory is organized as shown in the following figure.

Figure 3.

Block diagram

HOLD

Control logic

I/O shift register

High voltage generator

Address register and counter

Data register

Status

EEPROM area

1 page

X decoder

AI01272d

Obsolete Product(s) - Obsolete Product(s)

8/37 Doc ID 023153 Rev 1

M95M01-125 Signal description

3.1

3.2

3.3

3.4

During all operations, V

must be held stable and within the specified valid range:

(min) to V

(max).

All of the input and output signals must be held high or low (according to voltages of V

, V

or V

OL described next.

, as specified in Section 9: DC and AC parameters ). These signals are

Serial Data Output (Q)

This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C).

Serial Data Input (D)

This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be written. Values are latched on the rising edge of Serial Clock

(C).

Serial Clock (C)

This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on

Serial Data Output (Q) change from the falling edge of Serial Clock (C).

Chip Select (S)

When this input signal is high, the device is deselected and Serial Data Output (Q) is at high impedance. The device is in the Standby Power mode, unless an internal Write cycle is in progress. Driving Chip Select (S) low selects the device, placing it in the Active Power mode.

After power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction. deselecting the device.

During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data

Input (D) and Serial Clock (C) are Don’t Care.

To start the Hold condition, the device must be selected, with Chip Select (S) driven low.

Doc ID 023153 Rev 1 9/37

Signal description

3.6

M95M01-125

Write Protect (W)

The main purpose of this input signal is to freeze the size of the area of memory that is protected against Write instructions (as specified by the values in the BP1 and BP0 bits of the Status Register).

This pin must be driven either high or low, and must be stable during all Write instructions.

3.7 V

supply voltage

is the supply voltage.

3.8 V

ground

is the reference for all signals, including the V

supply voltage.

Obsolete Product(s) - Obsolete Product(s)

10/37 Doc ID 023153 Rev 1

M95M01-125

4 Connecting to the SPI bus

Connecting to the SPI bus

All instructions, addresses and input data bytes are shifted in to the device, most significant bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C) after Chip Select (S) goes low.

All output data bytes are shifted out of the device, most significant bit first. The Serial Data

Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction

(such as the Read from Memory Array and Read Status Register instructions) have been clocked into the device.

Figure 4.

Bus master and memory devices on the SPI bus

SPI Interface with

(CPOL, CPHA) =

(0, 0) or (1, 1)

SDO

SDI

SCK

SPI Bus Master

C Q D V

R SPI Memory

Device

R SPI Memory

Device

R SPI Memory

Device

CS3 CS2 CS1

S W HOLD S W HOLD S W HOLD

AI12836b

The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.

Figure 4 shows an example of three memory devices connected to an SPI bus master. Only

one memory device is selected at a time, so only one memory device drives the Serial Data

Output (Q) line at a time. The other memory devices are high impedance.

The pull-up resistor R (represented in Figure 4

) ensures that a device is not selected if the

Bus Master leaves the S line in the high impedance state.

same time (for example, if the Bus Master is reset during the transmission of an instruction), the clock line (C) must be connected to an external pull-down resistor so that, if all inputs/outputs become high impedance, the C line is pulled low (while the S line is pulled t high): this ensures that S and C do not become high at the same time, and so, that the

SHCH

requirement is met. The typical value of R is 100 k

Doc ID 023153 Rev 1 11/37

Connecting to the SPI bus M95M01-125

●

These devices can be driven by a microcontroller with its SPI peripheral running in either of the following two modes:

CPOL=0, CPHA=0

CPOL=1, CPHA=1

For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C).

●

The difference between the two modes, as shown in

Figure 5 , is the clock polarity when the

bus master is in Stand-by mode and not transferring data:

C remains at 0 for (CPOL=0, CPHA=0)

C remains at 1 for (CPOL=1, CPHA=1)

Figure 5.

SPI modes supported

CPOL CPHA

0 0 C

1 1 C

MSB

AI01438B

Obsolete Product(s) - Obsolete Product(s)

12/37 Doc ID 023153 Rev 1

M95M01-125 Operating features

5.1

5.1.1

Supply voltage (V

)

Operating supply voltage V

Prior to selecting the memory and issuing instructions to it, a valid and stable V

voltage within the specified [V

(min), V

(max)] range must be applied (see Operating conditions in

Section 9: DC and AC parameters ). This voltage must remain stable and valid until the

end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (t

). In order to secure a stable DC supply voltage, it is recommended to decouple the V

line with a suitable capacitor (usually of the order of

10 nF to 100 nF) close to the V

device pins.

In order to prevent erroneous instruction decoding and inadvertent Write operations during power-up, a power-on-reset (POR) circuit is included. At power-up, the device does not respond to any instruction until VCC reaches the POR threshold voltage. This threshold is lower than the minimum V

operating voltage (see Operating conditions in

Section 9: DC and AC parameters

●

At power-up, when V

CC following state:

passes over the POR threshold, the device is reset and is in the in Standby Power mode, deselected,

Status Register values:

– The Write Enable Latch (WEL) bit is reset to 0.

– The Write In Progress (WIP) bit is reset to 0.

– The SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits).

It is important to note that the device must not be accessed until V

reaches a valid and stable level within the specified [V

(min), V

(max)] range, as defined under Operating

conditions in Section 9: DC and AC parameters .

When the power supply is turned on, V

rises continuously from V

to V

. During this time, the Chip Select (S) line is not allowed to float but should follow the V therefore recommended to connect the S line to V

voltage. It is

Figure 4 ).

via a suitable pull-up resistor (see

Obsolete Product(s) - Obsolete Product(s)

In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edgesensitive as well as level-sensitive: after power-up, the device does not become selected until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select

(S) must have been high, prior to going low to start the first operation.

The V

voltage has to rise continuously from 0 V up to the minimum V

operating voltage

defined under Operating conditions in Section 9: DC and AC parameters

, and the rise time must not vary faster than 1 V/µs.

Doc ID 023153 Rev 1 13/37

Operating features M95M01-125

5.1.4 Power-down

●

During power-down (continuous decrease of the V

supply voltage below the minimum

operating voltage defined under Operating conditions in Section 9: DC and AC parameters ), the device must be:

deselected (Chip Select S should be allowed to follow the voltage applied on V

CC in Standby Power mode (there should not be any internal write cycle in progress).

5.2 Active Power and Standby Power modes

When Chip Select (S) is low, the device is selected, and in the Active Power mode. The device consumes I

When Chip Select (S) is high, the device is deselected. If a Write cycle is not currently in progress, the device then goes into the Standby Power mode, and the device consumption drops to I

CC1

, as specified in DC characteristics (see Section 9: DC and AC parameters

The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence.

To enter the Hold condition, the device must be selected, with Chip Select (S) low.

During the Hold condition, the Serial Data Output (Q) is high impedance, and the Serial

Data Input (D) and the Serial Clock (C) are Don’t Care.

Normally, the device is kept selected for the whole duration of the Hold condition.

Deselecting the device while it is in the Hold condition has the effect of resetting the state of the device, and this mechanism can be used if required to reset any processes that had been in progress.

(a)(b)

Figure 6.

Hold condition activation c

HOLD

Hold condition

Hold condition Obsolete Product(s) - Obsolete Product(s) ai02029E

The Hold condition starts when the Hold (HOLD) signal is driven low when Serial Clock (C) is already low (as shown in

Figure 6 ).

14/37 a.

This resets the internal logic, except the WEL and WIP bits of the Status Register.

In the specific case where the device has shifted in a Write command (Inst + Address + data bytes, each data byte being exactly 8 bits), deselecting the device also triggers the Write cycle of this decoded command.

Doc ID 023153 Rev 1

M95M01-125 Operating features

The Hold condition ends when the Hold (HOLD) signal is driven high when Serial Clock (C) is already low.

Figure 6 also shows what happens if the rising and falling edges are not timed to coincide

with Serial Clock (C) being low.

The Status Register contains a number of status and control bits that can be read or set (as

appropriate) by specific instructions. See Section 6.3: Read Status Register (RDSR) for a

detailed description of the Status Register bits.

5.5 Data protection and protocol control

The device features the following data protection mechanisms:

● Before accepting the execution of the Write and Write Status Register instructions, the device checks whether the number of clock pulses comprised in the instructions is a multiple of eight.

●

All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit.

The Block Protect (BP1, BP0) bits in the Status Register are used to configure part of the memory as read-only.

● The Write Protect (W) signal is used to protect the Block Protect (BP1, BP0) bits in the

Status Register.

For any instruction to be accepted, and executed, Chip Select (S) must be driven high after the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising edge of Serial Clock (C).

Two points should be noted in the previous sentence:

● The “last bit of the instruction” can be the eighth bit of the instruction code, or the eighth bit of a data byte, depending on the instruction (except for Read Status Register

(RDSR) and Read (READ) instructions).

● The “next rising edge of Serial Clock (C)” might (or might not) be the next bus transaction for some other device on the SPI bus.

Table 2.

Write-protected block size

Status Register bits

Protected block Protected array addresses

BP1 BP0 Obsolete Product(s) - Obsolete Product(s)

0 0 none none

Upper quarter

Upper half

Whole memory

1.80.00h - 1.FF.FFh

1.00.00h - 1.FF.FFh

0.00.00h - 1.FF.FFh

Doc ID 023153 Rev 1 15/37

Instructions

6 Instructions

M95M01-125

Each instruction starts with a single-byte code, as summarized in Table 3

If an invalid instruction is sent (one not contained in

Table 3 ), the device automatically

deselects itself.

Table 3.

Instruction set

Instruction Description Instruction format

RDSR

WRSR

READ

WRITE

Read Status Register

Write Status Register

Read from Memory Array

Write to Memory Array

Table 4.

Address range bits

Address significant bits

Upper MSBs are Don’t Care.

0000 0101

0000 0001

0000 0011

0000 0010

A16-A0

(1)

Obsolete Product(s) - Obsolete Product(s)

16/37 Doc ID 023153 Rev 1

M95M01-125

6.1

Instructions

Write Enable (WREN)

The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.

The only way to do this is to send a Write Enable instruction to the device.

As shown in

Figure 7 , to send this instruction to the device, Chip Select (S) is driven low,

and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state. It waits for the device to be deselected, by Chip Select (S) being driven high.

Figure 7.

Write Enable (WREN) sequence

0 1 2 3 4 5 6 7

Instruction

High Impedance

AI02281E

Obsolete Product(s) - Obsolete Product(s)

Doc ID 023153 Rev 1 17/37

Instructions

6.2

M95M01-125

Write Disable (WRDI)

One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction to the device.

As shown in

Figure 8 , to send this instruction to the device, Chip Select (S) is driven low,

and the bits of the instruction byte are shifted in, on Serial Data Input (D).

The device then enters a wait state. It waits for a the device to be deselected, by Chip Select

(S) being driven high.

The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:

●

Power-up

WRDI instruction execution

WRSR instruction completion

WRITE instruction completion.

Figure 8.

Write Disable (WRDI) sequence

0 1 2 3 4 5 6 7

Instruction

High Impedance

AI03750D

Obsolete Product(s) - Obsolete Product(s)

18/37 Doc ID 023153 Rev 1

M95M01-125

6.3

Instructions

Read Status Register (RDSR)

The Read Status Register (RDSR) instruction is used to read the Status Register. The

Status Register may be read at any time, even while a Write or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the

Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register continuously, as shown in

Figure 9 .

Figure 9.

Read Status Register (RDSR) sequence

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Instruction

High Impedance

Status Register Out Status Register Out

7 6 5 4 3 2 1 0

MSB

6 5 4 3 2 1 0 7

AI02031E

The status and control bits of the Status Register are as follows:

The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write

Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0, no such cycle is in progress.

The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.

When set to 1, the internal Write Enable Latch is set. When set to 0, the internal Write

Enable Latch is reset, and no Write or Write Status Register instruction is accepted.

The WEL bit is returned to its reset state by the following events:

Power-up ●

Write Disable (WRDI) instruction completion ●

●

Write Status Register (WRSR) instruction completion

Obsolete Product(s) - Obsolete Product(s)

6.3.3 BP1, bits

The Block Protect (BP1, BP0) bits are non volatile. They define the size of the area to be software-protected against Write instructions. These bits are written with the Write Status

Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to 1, the relevant memory area (as defined in

Table 2 ) becomes protected against Write

(WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the

Hardware Protected mode has not been set.

Doc ID 023153 Rev 1 19/37

Instructions M95M01-125

6.4

The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write

Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W) signal enable the device to be put in the Hardware Protected mode (when the Status

Register Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven low). In this mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution.

Table 5.

SRWD

Status Register format b0

Status Register Write Protect

Block Protect bits

Write Enable Latch bit

Write In Progress bit

Write Status Register (WRSR)

The Write Status Register (WRSR) instruction is used to write new values to the Status

The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) low, followed by the instruction code, the data byte on Serial Data input (D) and Chip Select (S) driven high. Chip Select (S) must be driven high after the rising edge of Serial Clock (C) that latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock (C).

Otherwise, the Write Status Register (WRSR) instruction is not executed.

The instruction sequence is shown in

Figure 10

Figure 10.

Write Status Register (WRSR) sequence

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

High Impedance

Status

7 6 5 4 3 2 1 0

MSB

AI02282D

20/37 Doc ID 023153 Rev 1

M95M01-125 Instructions

Driving the Chip Select (S) signal high at a byte boundary of the input data triggers the selftimed Write cycle that takes t

to complete (as specified in AC tables under

Section 9: DC and AC parameters

While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write in progress (WIP) bit: the WIP bit is 1 during the self-timed

Write cycle t

, and 0 when the Write cycle is complete. The WEL bit (Write Enable Latch) is also reset at the end of the Write cycle t

The Write Status Register (WRSR) instruction enables the user to change the values of the

BP1, BP0 and SRWD bits:

● The Block Protect (BP1, BP0) bits define the size of the area that is to be treated as

read-only, as defined in Table 2

● The SRWD (Status Register Write Disable) bit, in accordance with the signal read on the Write Protect pin (W), enables the user to set or reset the Write protection mode of

the Status Register itself, as defined in Table 6

. When in Write-protected mode, the

Write Status Register (WRSR) instruction is not executed.

The contents of the SRWD and BP1, BP0 bits are updated after the completion of the

WRSR instruction, including the t

Write cycle.

The Write Status Register (WRSR) instruction has no effect on the b6, b5, b4, b1, b0 bits in the Status Register. Bits b6, b5, b4 are always read as 0.

Table 6.

Protection modes

W signal

SRWD bit

Mode

Write protection of the

Status Register

Memory content

Protected area

(1)

Unprotected area

(1)

Softwareprotected

(SPM)

Status Register is writable (if the WREN instruction has set the

WEL bit).

The values in the BP1 and BP0 bits can be changed.

Hardwareprotected

(HPM)

Status Register is

Hardware writeprotected.

The values in the BP1 and BP0 bits cannot be changed.

Write-protected

Ready to accept

Write instructions

Ready to accept

Write instructions

As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register. See

Table 2 .

Obsolete Product(s) - Obsolete Product(s)

The protection features of the device are summarized in Table 6 .

When the Status Register Write Disable (SRWD) bit in the Status Register is 0 (its initial delivery state), it is possible to write to the Status Register (provided that the WEL bit has previously been set by a WREN instruction), regardless of the logic level applied on the

Write Protect (W) input pin.

Doc ID 023153 Rev 1 21/37

Instructions M95M01-125

When the Status Register Write Disable (SRWD) bit in the Status Register is set to 1, two cases should be considered, depending on the state of the Write Protect (W) input pin:

● If Write Protect (W) is driven high, it is possible to write to the Status Register (provided that the WEL bit has previously been set by a WREN instruction).

● If Write Protect (W) is driven low, it is not possible to write to the Status Register even if the WEL bit has previously been set by a WREN instruction. (Attempts to write to the

Status Register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory area, which are Software-protected (SPM) by the

Block Protect (BP1, BP0) bits in the Status Register, are also hardware-protected against data modification.

●

Regardless of the order of the two events, the Hardware-protected mode (HPM) can be entered by: either setting the SRWD bit after driving the Write Protect (W) input pin low, or driving the Write Protect (W) input pin low after setting the SRWD bit.

Once the Hardware-protected mode (HPM) has been entered, the only way of exiting it is to pull high the Write Protect (W) input pin.

If the Write Protect (W) input pin is permanently tied high, the Hardware-protected mode

(HPM) can never be activated, and only the Software-protected mode (SPM), using the

Block Protect (BP1, BP0) bits in the Status Register, can be used.

6.5 Read from Memory Array (READ)

As shown in

Figure 11

, to send this instruction to the device, Chip Select (S) is first driven low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data

Input (D). The address is loaded into an internal address register, and the byte of data at that address is shifted out, on Serial Data Output (Q).

Figure 11.

Read from Memory Array (READ) sequence

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39

Instruction 24-bit address

High Impedance

23 22 21

MSB

3 2 1 0

MSB

6 5

Data Out 1

4 3 2 1 0 7

Data Out 2

AI13878

If Chip Select (S) continues to be driven low, the internal address register is incremented automatically, and the byte of data at the new address is shifted out.

22/37 Doc ID 023153 Rev 1

M95M01-125 Instructions

When the highest address is reached, the address counter rolls over to zero, allowing the

Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a single READ instruction.

The Read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip

Select (S) signal can occur at any time during the cycle.

The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.

6.6 Write to Memory Array (WRITE)

As shown in

Figure 12

, to send this instruction to the device, Chip Select (S) is first driven low. The bits of the instruction byte, address byte, and at least one data byte are then shifted in, on Serial Data Input (D).

The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input data. The self-timed Write cycle, triggered by the Chip Select (S) rising edge, continues for a period t

(as specified in AC characteristics in Section 9: DC and AC parameters

), at the end of which the Write in Progress (WIP) bit is reset to 0.

Figure 12.

Byte Write (WRITE) sequence

)NSTRUCTION BITADDRESS $ATABYTE

(IGHIMPEDANCE

-36

In the case of Figure 12

, Chip Select (S) is driven high after the eighth bit of the data byte has been latched in, indicating that the instruction is being used to write a single byte.

However, if Chip Select (S) continues to be driven low, as shown in Figure 13

, the next byte of input data is shifted in, so that more than a single byte, starting from the given address Obsolete Product(s) - Obsolete Product(s)

Each time a new data byte is shifted in, the least significant bits of the internal address counter are incremented. If more bytes are sent than will fit up to the end of the page, a condition known as “roll-over” occurs. In case of roll-over, the bytes exceeding the page size are overwritten from location 0 of the same page.

Doc ID 023153 Rev 1 23/37

Instructions M95M01-125

Note:

●

The instruction is not accepted, and is not executed, under the following conditions:

● if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable instruction just before), if a Write cycle is already in progress, if the device has not been deselected, by driving high Chip Select (S), at a byte boundary (after the eighth bit, b0, of the last data byte that has been latched in),

● if the addressed page is in the region protected by the Block Protect (BP1 and BP0) bits.

The self-timed write cycle t

is internally executed as a sequence of two consecutive events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is read as “0” and a programmed bit is read as “1”.

Figure 13.

Page Write (WRITE) sequence

0 1 2 3 4 5 6 7 8 9 10

Instruction

28 29 30 31 32 33 34 35 36 37 38 39

24-bit address Data byte 1

3 2 1 0 7 6 5 4 3 2 1 0

Data byte 2 Data byte 3 Data byte N

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 6 5 4 3 2 1 0

-36

Obsolete Product(s) - Obsolete Product(s)

24/37 Doc ID 023153 Rev 1

M95M01-125 Instructions

M95M01 devices offer an Error Correction Code (ECC) logic. The ECC is an internal logic function which is transparent for the SPI communication protocol.

The ECC logic is implemented on each group of four EEPROM bytes

(c)

. Inside a group, if a single bit out of the four bytes happens to be erroneous during a Read operation, the ECC detects this bit and replaces it with the correct value. The read reliability is therefore much improved.

Even if the ECC function is performed on groups of four bytes, a single byte can be written/cycled independently. In this case, the ECC function also writes/cycles the three other bytes located in the same group

(c)

. As a consequence, the maximum cycling budget is

defined at group level and the cycling can be distributed over the four bytes of the group: the sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain below the maximum value defined in

Table 11

Obsolete Product(s) - Obsolete Product(s) c.

A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer.

Doc ID 023153 Rev 1 25/37

Power-up and delivery state

7 Power-up and delivery state

M95M01-125

●

After power-up, the device is in the following state:

●

Standby power mode, deselected (after power-up, a falling edge is required on Chip Select (S) before any instructions can be started), not in the Hold condition, the Write Enable Latch (WEL) is reset to 0,

Write In Progress (WIP) is reset to 0.

The SRWD, BP1 and BP0 bits of the Status Register are unchanged from the previous power-down (they are non-volatile bits).

The device is delivered with the memory array set to all 1s (each byte = FFh). The Status

Obsolete Product(s) - Obsolete Product(s)

26/37 Doc ID 023153 Rev 1

M95M01-125 Maximum rating

Stressing the device outside the ratings listed in Table 7

may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Table 7.

Symbol

Absolute maximum ratings

Parameter Min.

Max.

Unit

Ambient operating temperature –40 130 °C

STG

LEAD

ESD

Storage temperature

Lead temperature during soldering

Output voltage

Input voltage

Supply voltage

DC output current (Q = 0)

DC output current (Q = 1)

Electrostatic discharge voltage (human body model)

(2)

–65

See note

–0.50

150

(1)

+0.6

6.5

4000

°C

V mA mA

Compliant with JEDEC Std J-STD-020 (for small body, Sn-Pb or Pb assembly), with the ST ECOPACK®

7191395 specification, and with the European directive on Restrictions on Hazardous Substances (RoHS)

2002/95/EU.

Positive and negative pulses applied on different combinations of pin connections, according to AEC-

Q100-002 (compliant with JEDEC Std JESD22-A114, C1=100 pF, R1=1500

, R2=500

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DC and AC parameters

9 DC and AC parameters

M95M01-125

This section summarizes the operating conditions and the DC/AC characteristics of the device.

Table 8.

Symbol

Table 9.

Symbol

Operating conditions (M95M01-W, device grade 3)

Parameter Min.

Supply voltage

Ambient operating temperature

2.5

–40

AC measurement conditions

Parameter

Load capacitance

Input rise and fall times

Input pulse voltages

Input and output timing reference voltages

Max.

5.5

125

Min.

Max.

100

0.2 V

to 0.8 V

0.3 V

to 0.7 V

Unit

°C

Unit pF ns

Figure 14.

AC measurement I/O waveform

)NPUTVOLTAGELEVELS

6##

)NPUTANDOUTPUT

TIMINGREFERENCELEVELS

6##

!)#

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M95M01-125

Note:

DC and AC parameters

Table 10.

Capacitance

Symbol Parameter Test conditions

(1)

OUT

Output capacitance (Q)

Input capacitance (D)

Input capacitance (other pins)

OUT

= 0 V

Sampled only, not 100% tested, at T

= 25 °C and a frequency of 5 MHz.

Min.

Table 11.

Memory cell characteristics

Symbol Parameter Test condition

N cycle

Endurance TA = 25 °C, 2.5 V < V cc

< 5.5 V

Min.

1,000,000

Max.

Unit

Write cycle

Unit pF pF pF

This parameter is not tested but established by characterization and qualification. For endurance estimates in a specific application, please refer to AN2014.

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DC and AC parameters M95M01-125

Table 12.

DC characteristics (M95M01-W, device grade 3)

Symbol Parameter

Test conditions specified in Table 8

CC0

(1)

CC1

Input leakage current

Output leakage current

Supply current (Read)

Supply current (Write)

Supply current

(Standby Power mode)

= V

or V

S = V

, V

OUT

= V

or V

C = 0.1V

/0.9V

at 5 MHz,

= 2.5 V, Q = open

C = 0.1 V

/0.9V

at 5 MHz,

= 5 V, Q = open

During t

, S = V

2.5 V < V

< 5.5 V

S = V

, V

= V

or V

2.5 V < V

< 5.5 V

Input low voltage

Input high voltage

Output low voltage

Output high voltage

= 2.5 V and I

= 1.5 mA or

= 5 V and I

= 2 mA

= 2.5 V and I

= –0.4 mA or

= 5 V and I

= –2 mA

Characterized only, not tested in production.

Min.

Max.

Unit

± 2

µA

µA mA mA mA

µA

–0.45

0.3 V

0.7 V

+1 V

0.8 V

0.4

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M95M01-125 DC and AC parameters

Table 13.

AC characteristics (M95M01-W, device grade 3)

Test conditions specified in Table 8

and

Table 9

Symbol Alt.

Parameter Min.

Max.

Unit f

SCK t

CSS1 t

CSS2 t

CS t

CSH t

CLH t

CLL t

RC t

FC t

DSU t

Clock frequency

S active setup time

S not active setup time

S deselect time

S active hold time

S not active hold time

Clock high time

Clock low time

Clock rise time

Clock fall time

Data in setup time

Data in hold time

Clock low hold time after HOLD not active

Clock low hold time after HOLD active

Clock low setup time before HOLD active

Clock low setup time before HOLD not active

D.C.

MHz f

C t

SLCH t

SHCH t

SHSL t

CHSH t

CHSL t

(1) t

(1)

CLCH

(2) t

CHCL

(2)

DVCH t

CHDX t

HHCH t

HLCH t

CLHL t

CLHH t

SHQZ

(2)

CLQV t

CLQX t

QLQH

(2)

QHQL

(2)

HHQV t

HLQZ

(2)

W t

DIS t

V t

HO t

RO t

FO t

LZ t

HZ t

Output disable time

Clock low to output valid

Output hold time

Output rise time

Output fall time

HOLD high to output valid

HOLD low to output High-Z

Write time

+ t

must never be less than the shortest possible clock period, 1 / f

(max)

Characterized only, not tested in production.

Obsolete Product(s) - Obsolete Product(s) ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns

µs

µs ns ns ns ns ns ns

Doc ID 023153 Rev 1 31/37

DC and AC parameters

Figure 15.

Serial input timing

S tCHSL

C tDVCH

D tSLCH

MSB IN tCHCL tCHDX tCH tCL tCHSH

LSB IN tCLCH tSHSL tSHCH

M95M01-125

High impedance

AI01447d

Figure 16.

Hold timing

S tHLCH

C tCLHL tHLQZ tHHCH tCLHH tHHQV

HOLD

AI01448c

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M95M01-125

Figure 17.

Serial output timing

C tCLQV tCLQX

Q tCLCH

ADDR

LSB IN

DC and AC parameters tCHCL tCH tCL tQLQH tQHQL tSHSL tSHQZ

AI01449f

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Package mechanical data

10 Package mechanical data

M95M01-125

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK

packages, depending on their level of environmental compliance. ECOPACK

® specifications, grade definitions and product status are available at: www.st.com

ECOPACK

is an ST trademark.

Figure 18.

SO8N – 8-lead plastic small outline, 150 mils body width, package outline h x 45˚

A2 A c ccc b e

0.25 mm

GAUGE PLANE k

E1 E

SO-A

Drawing is not to scale.

Table 14.

SO8N – 8-lead plastic small outline, 150 mils body width, mechanical data millimeters inches

(1)

Symbol

Typ Min Max Typ Min Max

0.0689

0.0098

c ccc

A2 b

4.900

6.000

3.900

1.270

0.100

1.250

0.280

0.170

4.800

5.800

3.800

0.250

0°

0.400

1.750

0.250

0.480

0.230

0.100

5.000

6.200

4.000

0.500

8°

1.270

0.1929

0.2362

0.1535

0.0500

e h k

L1 1.040

0.0409

Values in inches are converted from mm and rounded to four decimal digits.

0.0039

0.0492

0.0110

0.0067

0.1890

0.2283

0.1496

0.0098

0°

0.0157

0.0189

0.0091

0.0039

0.1969

0.2441

0.1575

0.0197

8°

0.0500

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M95M01-125 Part numbering

Table 15.

Ordering information scheme

Example: M95M01

Device type

M95 = SPI serial access EEPROM

Device function

1 Mbit (131072 x 8)

Operating voltage

W = V

= 2.5 to 5.5 V

Package

MN = SO8 (150 mil width)

Device grade

3 = Device tested with high reliability certified flow.

Automotive temperature range (–40 to 125 °C)

Option

T = Tape and reel packing

Plating technology

P = RoHS compliant and halogen-free (ECOPACK®)

Process

/A= Manufacturing technology code

W MN 3 T P /A

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Revision history

Table 16.

Document revision history

Date Revision

20-Jun-2012 1 Initial release.

Changes

M95M01-125

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M95M01-125

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Doc ID 023153 Rev 1 37/37

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Automotive 1-Mbit serial SPI bus EEPROM

−

Features

Contents

List of tables

List of figures

1 Description

3.1

3.2

3.3

3.4

Serial Data Output (Q)

Serial Data Input (D)

Serial Clock (C)

Chip Select (S)

3.6

Write Protect (W)

3.7 V

supply voltage

3.8 V

ground

4 Connecting to the SPI bus

5.1

Supply voltage (V

)

5.2 Active Power and Standby Power modes

5.5 Data protection and protocol control

6 Instructions

6.1

Write Enable (WREN)

6.2

Write Disable (WRDI)

6.3

Read Status Register (RDSR)

6.4

Write Status Register (WRSR)

6.5 Read from Memory Array (READ)

6.6 Write to Memory Array (WRITE)

7 Power-up and delivery state

9 DC and AC parameters

10 Package mechanical data

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