STMicroelectronics LED7707 Datasheet
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LED7707
6-rows 85 mA LEDs driver with boost regulator for LCD panels backlight
Datasheet
-
production data
Applications
• LCD monitors and TV panels
• PDAs panel backlight
• GPS panel backlight
VFQFPN-24 4x4
Description
Features
• Boost section
– 4.5 V to 36 V input voltage range
– Internal power MOSFET
– Internal +5 V LDO for device supply
– Up to 36 V output voltage
– Constant frequency peak current-mode control
– 250 kHz to 1 MHz adjustable switching frequency
– External synchronization for multi-device application
– Pulse-skip power saving mode at light load
– Programmable soft-start
– Programmable OVP protection
The LED7707 consists of a high efficiency monolithic boost converter and six controlled current generators (rows) specifically designed to supply LED arrays used in the backlighting of
LCD panels. The device can manage an output voltage up to 36 V (i.e. 10 white LEDs per row).
The generators can be externally programmed to sink up to 85 mA and can be dimmed via a PWM signal (1% dimming duty-cycle at 1 kHz can be managed). The device can detect and manage open circuit and short-circuit LED faults and leave unused rows floating. Basic protections (output overvoltage, internal MOSFET overcurrent and thermal shutdown) are provided.
– Stable with ceramic output capacitors
– Thermal shutdown
•
Backlight driver section
– Six rows with 85 mA maximum current capability (adjustable)
– Rows disable option
– Less than 10 µs minimum dimming on-time
– ±2% current matching between rows
– LED failure (open and short-circuit) detection
Table 1. Device summary
Order code Package Packing
LED7707
LED7707TR
VFQFPN-24 4x4 (exposed pad)
Tube
Tape and reel www.st.com
Contents
Switching frequency selection and synchronization . . . . . . . . . . . . . . . 16
Slope compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Flywheel diode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Switching frequency setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Output capacitor choice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Overvoltage protection divider setting . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Power dissipation estimate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
List of tables
List of figures
Figure 11.
Effect of slope compensation on small inductor current perturbation (D > 0.5) . . . . . . . . . 19
Poor phase margin (a) and properly damped (b) load transient responses . . . . . . . . . . . . 29
Efficiency versus DIM duty cycle, VIN = 12 V, 6 rows, 10 white LEDs (60 mA) in series, FSW
Efficiency versus DIM duty cycle, VIN = 18 V, 6 rows, 10 white LEDs (60 mA) in series, FSW
Efficiency versus DIM duty cycle, VIN = 24 V, 6 rows, 10 white LEDs (60 mA) in series, FSW
Efficiency versus DIM duty cycle, VIN = 24 V, 6 rows, 10 white LEDs (60 mA) in series, FSW
Soft-start waveforms (EN, SS, and V
OUT
monitored)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Boost section switching signals (LX, SYNC and inductor current monitored), VIN = 12 V, 10
1 Typical application circuit
Figure 1. Application circuit
2.1 Connections
Figure 2. Pin connection (through top view)
COMP
RILIM
BILIM
FSW
MODE
AVCC
1
24
6
7
LED7706
19
18
12
13
OVSEL
PGND
ROW6
ROW5
ROW4
ROW3
4
5
6
7
2
3
N°
1
Pin
COMP
RILIM
BILIM
FSW
MODE
AVCC
LDO5
Table 1. Pin functions
Function
Error amplifier output. A simple RC series between this pin and ground is needed to compensate the loop of the boost regulator.
Output generators current limit setting. The output current of the rows can be programmed connecting a resistor to SGND.
Boost converter current limit setting. The internal MOSFET current limit can be programmed connecting a resistor to SGND.
Switching frequency selection and external sync input. A resistor to SGND is used to set the desired switching frequency. The pin can also be used as
external synchronization input. See Section 5.1.5 on page 16 for details.
Current generators fault management selector. It allows to detect and manage
LEDs failures. See
Section 5.3.2 on page 24 for details.
+ 5 V analog supply. Connect to LDO5 through a simple RC filter.
+ 5 V LDO output and power section supply. Bypass to SGND with a
1 µF ceramic capacitor.
N°
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SGND
ROW1
ROW2
ROW3
ROW4
ROW5
ROW6
PGND
OVSEL
LX
DIM
EN
Pin
VIN
SLOPE
FAULT
SYNC
SS
Table 1. Pin functions (continued)
Function
Input voltage. Connect to the main supply rail.
Slope compensation setting. A resistor between the output of the boost converter and this pin is needed to avoid sub-harmonic instability.
Refer to Section 6.1 on page 27 for details.
Signal ground. Supply return for the analog circuitry and the current generators.
Row driver output #1.
Row driver output #2.
Row driver output #3.
Row driver output #4.
Row driver output #5.
Row driver output #6.
Power ground. Source of the internal power MOSFET.
Overvoltage selection. Used to set the desired 0 V threshold by an external divider. See
Section 5.1.4 on page 16 for details.
Switching node. Drain of the internal power MOSFET.
Dimming input. Used to externally set the brightness by using a PWM signal.
Enable input. When low, the device is turned off. If tied high or left open, the device is turned on and a soft-start sequence takes place.
Fault signal output. Open drain output. The pin goes low when a fault
condition is detected (see Section 5.3.1 on page 23 for details).
Synchronization output. Used as external synchronization output.
Soft-start. Connect a capacitor to SGND to set the desired soft-start duration.
Table 2. Absolute maximum ratings
(1)
Parameter Symbol Value Unit
V
V
AVCC
LDO5
V
V
IN
LX
AVCC to SGND
LDO5 to SGND
PGND to SGND
VIN to PGND
LX to SGND
LX to PGND
RILIM, BILIM, SYNC, OVSEL, SS to SGND
EN, DIM, SW, MODE, FAULT to SGND
ROWx to PGND/ SGND
SLOPE to VIN
SLOPE to SGND
-0.3 to 6
-0.3 to 6
-0.3 to 0.3
-0.3 to 40
-0.3 to 40
-0.3 to 40
-0.3 to V
AVCC
+ 0.3
-0.3 to 6
-0.3 to 40
V
IN
- 0.3 to V
IN
+ 6
-0.3 to 40
V
P
TOT
Internal switch maximum RMS current
(flowing through LX node)
Power dissipation @ T
A
= 25 °C
Maximum withstanding voltage range test condition:
CDF-AEC-Q100-002- “human body model” acceptance criteria: “normal performance”
2.0 A
2.3
(2)
±1000
1.
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
2.
Power dissipation referred to the device mounted on the demonstration board described in section 5.5.
W
V
Table 3. Thermal data
Parameter Symbol
R thJA
T
STG
T
J
Thermal resistance junction-to-ambient
Storage temperature range
Junction operating temperature range
Value
42
-50 to 150
-40 to 150
Unit
°C/W
°C
°C
V
IN
= 12 V; T
J
= 25 °C and LDO5 connected to AVCC if not otherwise specified
(a)
Symbol Parameter
Table 4. Electrical characteristics
Conditions Min.
Typ.
Max.
Unit
Supply section
V
I
V
BST
V
LDO5
V
I
V
IN
AVCC
IN,Q
IN,SHDN
UVLO,ON
Input voltage range
Boost section output voltage
LDO output and IC supply voltage
EN high
I
LDO5
= 0 mA
Operating quiescent current
R
RILIM
= 51 kW, R
BILIM
= 220 kW,
R
SLOPE
= 680 kW,
DIM tied to SGND
Operating current in shutdown
LDO5 under voltage lock out upper threshold
EN low
V
UVLO,OFF
LDO5 under voltage lock out lower threshold
LDO linear regulator
Line regulation
LDO dropout voltage
LDO maximum output current
I
6 V ≤
LDO5
V
IN
≤ 36 V, I
LDO5
V
LDO5
> V
UVLO,ON
V
LDO5
< V
UVLO,OFF
= 30 mA
= 10 mA (-10% drop)
Boost section t
ON,min f
SW
Minimum switching on-time
Default switching frequency
Minimum FSW sync frequency
FSW sync input low level
FSW sync input high level
FSW sync input hysteresis
FSW sync min ON time
FSW connected to AVCC
SYNC output duty-cycle
FSW connected to AVCC
(Internal oscillator selected)
4.5
4.4
3.5
25
570
240
5
1
20
4.0
3.7
80
40
20
660
220
30
34
36
36
5.5
30
4.3
30
120
60
30
200
770
350
270
40
V
V
V mA mA
V mV mA ns kHz mV
%
% a.
Specification referred to T
J
from 0 °C to +85 °C. Specification over the 0 to +85 °C T
J
range are assured by design, characterization and statistical correlation.
Symbol Parameter
Table 4. Electrical characteristics
Conditions
SYNC output high level
SYNC output low level
Power switch
I
SYNC
= 10 mA
I
SYNC
= -10 mA
K
B
LX current coefficient R
BILIM
= 600 kW
R
DS(on)
Internal MOSFET on-resistance
OC and OV protections
V
TH,OVP
Overvoltage protection reference threshold
Soft-start and power management
EN, turn-on threshold
EN, turn-off threshold
DIM, high level threshold
DIM, low level threshold
EN, pull-up current
SS, charge current
SS, end-of-startup threshold
SS, reduced switching frequency release threshold
Current generators section
K
R
∆
K
R
(1)
V
IFB
V rowx,
FAULT
V
FAULT,
LOW
Current generators gain
Current generators gain accuracy
Feedback regulation voltage
LED short-circuit detection threshold
FAULT pin low-level voltage
Thermal shutdown
MODE tied to SGND
I
FAULT,SINK
= 4 mA
T
SHDN
Thermal shutdown turn-off temperature
Thermal shutdown hysteresis
1.
I
ROW
= K
R
/ R
RILIM
, DI
ROW
/I
ROW
»
DK
R
/K
R
+ DR
RILIM
/R
RILIM
Min.
Typ.
Max.
Unit
V
AVCC
-20V mV
20
1
×
10
6
1.2
×
1
0
6
1.4
×
1
0
6
280
V
500 mW
1.145
0.8
1.3
4
1.8
2.5
5
2.4
0.8
1.6
V
0.8
6
2.6
mA
V
1850
700
V
±2.0
%
750 mV
4.0
V
250 380 mV
150
30
V
°C
The device can be divided into two sections: the boost section and the backlight driver section. These sections are described in the next paragraphs.
Figure 3 provides an overview of the internal blocks of the device.
Figure 3. Simplified block diagram
+ +
+ +
_ _
+ + g m
_ _
+ +
÷
2
V
ROW1
V
ROW5
V
ROW4
V
ROW3
V
ROW2
V
TH,FLT
The LED7707 is a monolithic LEDs driver for the backlight of LCD panels and it consists of a boost converter and six PWM-dimmable current generators.
The boost section is based on a constant switching frequency, peak current-mode architecture. The boost output voltage is controlled such that the lowest row's voltage, referred to SGND, is equal to an internal reference voltage (700 mV typ.). The input voltage range is from 4.5 V up to 36 V. In addition, the LED7707 has an internal LDO that supplies the internal circuitry of the device and is capable to deliver up to 40 mA. The input of the
LDO is the VIN pin.
The LDO5 pin is the LDO output and the supply for the power MOSFET driver at the same time. The AVCC pin is the supply for the analog circuitry and should be connected to the
LDO output through a simple RC filter in order to improve the noise rejection.
Figure 4. AVCC filtering
Two loops are involved in regulating the current sunk by the generators.
The main loop is related to the boost regulator and uses a constant frequency peak current-
mode architecture to regulate the power rail that supplies the LEDs ( Figure 5
), while an internal current loop regulates the same current (flowing through the LEDs) at each row according to the set value (RILIM pin).
Table 5. Main loop and current loop diagram
V IN
COMP
Slope
LX ROWx
PWM
E/A
0.7V
Error amplifier
Minimum voltage drop selector
SGND
RILIM
AM00582v1
A dedicated circuit automatically selects the lowest voltage drop among all the rows and provides this voltage to the main loop that, in turn, regulates the output voltage. In fact, once the reference generator has been detected, the error amplifier compares its voltage drop to the internal reference voltage and varies the COMP output. The voltage at the COMP pin determines the inductor peak current at each switching cycle. The output voltage of the boost regulator is thus determined by the total forward voltage of the LEDs strings (see
Equation 1
V
BST
=
N
ROWS max i
=
1
( m
LEDS j
Σ
= 1
V
F , j
)
+
700 mV where the first term represents the highest total forward voltage drop over N active rows and the second is the voltage drop across the leading generator (700 mV typ.).
The device continues to monitor the voltage drop across all the rows and automatically switches to the current generator having the lowest voltage drop.
Figure 5. Calculation of the output voltage of the boost regulator
Row with the highest voltage drop across LEDs
V
IN
Boost controller
Current generators section
I
LED max
Σ
V
F
V
BOOST
700 mV
Leading generator
AM00583v1
The LED7707 is enabled by the EN pin. This pin is active high and, when forced to SGND, the device is turned off. This pin is connected to a permanently active 2.5 µA current source; when sudden device turn-on at power-up is required, this pin must be left floating or connected to a delay capacitor. Starting from an ON state, when the LED7707 is turned off, it quickly discharges the Soft-Start capacitor and turns off the power-MOSFET, the current generators and the LDO. The power consumption is thus reduced to 20 µA only.
In applications where the dimming signal is used to turn on and off the device, the EN pin
can be connected to the DIM pin as shown in Figure 6
.
Figure 6. External sync waveforms
DIM
BAS69
EN
220k 100n
LED7707
SGND
AM00584v1
5.1.3 Soft-start
The soft-start function is required to perform a correct start-up of the system, controlling the inrush current required to charge the output capacitor and to avoid output voltage overshoot.
The soft-start duration is set connecting an external capacitor between the SS pin and ground. This capacitor is charged with a 5 mA (typ.) constant current, forcing the voltage on the SS pin to ramp up. When this voltage increases from zero to nearly 1.2 V, the current limit of the power MOSFET is proportionally released from zero to its final value. However, because of the limited minimum on-time of the switching section, the inductor might saturate due to current runaway. To solve this problem the switching frequency is reduced to one half of the nominal value at the beginning of the soft-start phase. The nominal switching frequency is restored after the SS pin voltage has crossed 0.8 V.
Figure 7. Soft-start sequence waveforms in case of floating rows t t ss t t
AM00585v1
During the soft-start phase the floating rows detection is also performed. In presence of one or more floating rows, the voltage across the involved current generator drops to zero. This voltage becomes the inverting input of the error amplifier through the minimum voltage drop selector (see
Figure 5 ). As a consequence the error amplifier is unbalanced and the loop
reacts by increasing the output voltage. When it reaches the floating row detection (FRD)
threshold (which coincides with the OVP threshold, see Section 5.1.4
managed according to
Section 5.3 on page 23 ). After the SS voltage reaches a
2.4 V threshold, the start-up finishes and all the protections turn active. The soft-start capacitor C
SS
can be calculated according to equation 2.
Equation 2
C
SS
≅
I
SS
⋅ t
2 .
4
SS
Where I
SS
= 5 µA and t
SS
is the desired soft-start duration.
An adjustable overvoltage protection is available. It can be set feeding the OVSEL pin with a partition of the output voltage. The voltage of the central tap of the divider is thus compared to a fixed 1.145 V threshold. When the voltage of the OVSEL pin exceeds the OV threshold, the switching activity is suspended. It is resumed as OVSEL returns below the OV threshold. A 10 mV hysteresis is provided. No device turn-off is performed. Normally, the value of the high-side resistors of the divider is in the order of 100 k
Ω
to reduce the output capacitor discharge when the boost converter is off (during the off phase of the dimming cycle), whereas the low-side resistor can be calculated as:
Equation 3
R
2
= R
1
⋅
V
OUT , MAX
1 .
145 V
+ 4 V − 1 .
145 V
An additional filtering capacitor C
F
(typically in the 100 pF - 330 pF range) may be required
to improve noise rejection at the OVSEL pin (see Figure 8
).
Figure 8. OVP threshold setting
V IN V OUT
LX
OVSEL
LED7707
SGND
R 1
C OUT
R 2
C F
5.1.5 Switching frequency selection and synchronization
The switching frequency of the boost converter can be set in the 250 kHz-1 MHz range by connecting the FSW pin to ground through a resistor. Calculation of the setting resistor is made using equation 4 and should not exceed the 100 k Ω - 400 k Ω range.
Equation 4
R
FSW
=
F
SW
2 .
5
In addition, when the FSW pin is tied to AVCC, the LED7707 uses a default 660 kHz fixed switching frequency, allowing to save a resistor in minimum component-count applications.
Figure 9. Multiple device synchronization
SLAVE
R
FSW
MASTER
AVCC
FSW
LED7707
SGND
SYNC FSW SYNC
LED7707
SYNC
SGND
Sync Out
AM00587v1
The FSW pin can also be used as synchronization input, allowing the LED7707 to operate both as master or slave device. If a clock signal with a 220 kHz minimum frequency is applied to this pin, the device locks synchronized. The signal provided to the FSW pin must cross the 270 mV threshold in order to be recognized. The minimum pulse width which allows the synchronizing pulses to be detected is 270 ns. An internal time-out allows synchronization as long as the external clock frequency is greater than 220 kHz.
Keeping the FSW pin voltage lower than 270 mV for more than 4.5 µs results in a stop of the device switching activity. Normal operation is resumed as soon as FSW rises above the mentioned threshold and the soft-start sequence is repeated.
The SYNC pin is a synchronization output and provides a 35 % (typ.) duty-cycle clock when the LED7707 is used as master or a replica of the FSW pin when used as slave. It is used to connect multiple devices in a daisy-chain configuration or to synchronize other switching converters running in the system with the LED7707 (master operation). When an external synchronization clock is applied to the FSW pin, the internal oscillator is over-driven: each
switching cycle begins at the rising edge of clock, while the slope compensation ( Figure 10 )
ramp starts at the falling edge of the same signal. Thus, to prevent sub-harmonic instability
), the external synchronization clock is required to have a 40 % maximum duty-cycle when the boost converter is working in continuous-conduction mode (CCM) in order to assure that the slope compensation is effective (starts with duty-cycle lower than
40%)
Figure 10. External sync waveforms
FSW pin voltage (ext. sync)
270mV threshold
Slave SYNC pin voltage
270ns minimum
Slave LX pin voltage
AM00588v1
The constant frequency, peak current-mode topology has the advantage of very easy loop compensation with output ceramic caps (reduced cost and size of the application) and fast transient response. In addition, the intrinsic peak-current measurement simplifies the current limit protection, avoiding undesired saturation of the inductor.
On the other side, this topology has a drawback: there is an inherent open loop instability when operating with a duty-ratio greater than 0.5. This phenomenon is known as “Sub-
Harmonic Instability” and can be avoided by adding an external ramp to the one coming from the sensed current. This compensating technique, based on the additional ramp, is
called “slope compensation”. In Figure 11
, where the switching duty-cycle is higher than 0.5, the small perturbation DI
L
dies away in subsequent cycles thanks to the slope compensation and the system reverts to a stable situation.
The SLOPE pin allows to properly set the amount of slope compensation connecting a simple resistor R
SLOPE between the SLOPE pin and the output. The compensation ramp starts at 35% (typ.) of each switching period and its slope is given by the following equation:
Equation 5
S
E
= K
S
V
OUT
− V
IN
R
SLOPE
− V
BE
Where K
S
= 5.8 × 10
10
s
-1
, V
BE
= 2 V (typ.) and S
E
is the slope ramp in [A/s].
To avoid sub-harmonic instability, the compensating slope should be at least half the slope of the inductor current during the off-phase when the duty-cycle is greater than 50%. The value of R
SLOPE can be calculated according to equation 6.
Equation 6
R
SLOPE
≤
2
⋅
K
S
⋅
L
(
⋅
(
V
V
OUT
OUT
−
−
V
IN
V
IN
)
−
V
BE
)
Figure 11. Effect of slope compensation on small inductor current perturbation (D>
0.5) slope compensation (S
E
)
I I
Δ
I t t
The design of the external components, especially the inductor and the flywheel diode, must be optimized in terms of size relying on the programmable peak current limit. The LED7707 improves the reliability of the final application giving the way to limit the maximum current flowing into the critical components. A simple resistor connected between the BILIM pin and ground sets the desired value. The voltage at the BILIM pin is internally fixed to 1.23 V and the current limit is proportional to the current flowing through the setting resistor, according to the following equation:
Equation 7
I
BOOST , PEAK
=
K
B
R
BILIM where
K
B
=
⋅ 6
V
The maximum allowed current limit is 5 A, resulting in a minimum setting resistor
R
BILIM
> 240 kW. The maximum guaranteed RMS current in the power switch is 2 A.
In a boost converter the RMS current through the internal MOSFET depends on both the input and output voltages, according to equations 8a (DCM) and 8b (CCM).
The current limitation works by clamping the COMP pin voltage proportionally to R
BILIM
Peak inductor current is limited to the above threshold decreased by the slope
. compensation contribution.
Equation 8 a
I
MOS , rms
=
V
IN
F
SW
⋅
D
⋅ L
D
3
Equation 8 b
I
MOS , rms
= I
OUT
D
(
1
−
D
)
2
+
1
12
I
OUT
V
OUT
⋅ f
SW
⋅ L
2
(
D
(
1 − D
) )
3
In order to avoid damage due to high junction temperature, a thermal shutdown protection is implemented. When the junction temperature rises above 150 °C (typ.), the device turns off both the control logic and the boost converter and holds the FAULT pin low. The LDO is kept alive and normal operation is automatically resumed after the junction temperature has been reduced by 30 °C.
The LED7707 is a LEDs driver with six channels (rows); each row is able to drive multiple
LEDs in series (max. 36 V) and to sink up to 85 mA maximum current, allowing to manage different kinds of LEDs.
The LEDs current can be set by connecting an external resistor (R
RILIM
) between the RILIM pin and ground. The voltage across the RILIM pin is internally set to 1.23 V and the rows current is proportional to the RILIM current according to the following equation:
Equation 9
I
ROWx
=
K
R
R
RILIM
Where K
R
= 1850 V.
better shows the relationship between I
ROW
and R
RILIM
and helps to choose the correct value of the resistor to set the desired row current.
Figure 12. Row current vs R
RILIM
AM00590v1
The maximum current mismatch between the rows is ± 2 % @ I rowx
= 60 mA.
The LED7707 allows parallelism different rows if required by the application. If the maximum current provided by a single row (85 mA) is not enough for the load, two or more current generators can be connected together, as shown in
. To keep the parallelism generators stable, the row current should be higher than 10 mA. The connection between channels in parallel must be done as close as possible to the device in order to minimize parasitic inductance.
V IN
Figure 13. Rows parallelism for higher current
Dimming
Fault
Enable
VCC
BILIM
RILIM
SS
COMP
SGND
LED7707
ROW0
ROW1
ROW2
ROW3
ROW4
ROW5
Faults Management Selection
Sync Output
High Current WLEDs
AM00591v1
The brightness control of the LEDs is performed by a pulse-width modulation of the rows current. When a PWM signal is applied to the DIM pin, the current generators are turned on and off mirroring the DIM pin behavior. Actually, the minimum dimming duty-cycle depends on the dimming frequency.
The PWM dimming ratio is limited by the minimum conduction time of the current generators in closed loop operation. A 10 µs minimum on-time is suggested for proper device operations assuming I
ROWs
= 20 mA, otherwise higher dimming ratio may be required.
Thus, the minimum dimming duty-cycle depends on the dimming frequency according to the following formula:
Equation 10
D
DIM , min
= 10 μ s ⋅ f
DIM
For example, at a dimming frequency of 1 kHz, 1% of dimming duty-cycle can be managed.
During the off-phase of the PWM signal the boost converter is paused and the current generators are turned off. The output voltage can be considered almost constant because of the relatively slow discharge of the output capacitor. During the start-up sequence (see
) the dimming duty-cycle is forced to 100% to detect floating rows regardless of the applied dimming signal.
Figure 14. PWM dimming waveforms
The main loop keeps the row having the lowest voltage drop regulated to about 700 mV.
This value slightly depends on the voltage across the remaining active rows. After the softstart sequence, all protections turn active and the voltage across the active current generators is monitored to detect shorted LEDs.
The FAULT pin is an open-collector output, (with 4 mA current capability) active low, which gives information regarding faulty conditions eventually detected. This pin can be used either to drive a status LED or to warn the host system.
The FAULT pin status is strictly related to the MODE pin setting (see
for details).
5.3.3
The MODE pin is a digital input and can be connected to AVCC or SGND in order to choose the desired fault detection and management. The LED7707 can manage a faulty condition in two different ways, according to the application needs.
summarizes how the device detects and handles the internal protections related to the boost section (overcurrent, overtemperature and overvoltage) and to the current generators section (open and shorted LEDs).
FAULT
Internal MOSFET over-current
Output over-voltage
Thermal shutdown
LED short circuit
Open row(s)
Table 6. Faults management summary
MODE to GND MODE to VCC
FAULT pin HIGH
Power MOS turned OFF
FAULT pin LOW
Device turned OFF, latched condition
FAULT pin LOW. device turned OFF.
Automatic restart after 30 C temperature drop.
FAULT pin LOW, device turned
OFF (100s masking time), latched condition (Vth = 4.0 V)
-
FAULT pin LOW
Device turned OFF at first occurrence, latched condition
FAULT pin HIGH faulty row(s) disconnected.
Open LED fault
In case a row is not connected or a LED fails open, the device has two different behaviors according to the MODE pin status. If the MODE pin is high (i.e. connected to AVCC), the
FAULT pin is set high as soon as the device recognizes the event; the open row is excluded from the control loop and the device continues to work properly with the remaining rows.
Thus, if less than six rows are used in the application, the MODE pin must be set high.
Connecting the MODE pin to SGND, the LED7707 behaves in a different manner: as soon as an open row is detected the FAULT pin is tied low and the device is turned off. The internal logic latches this status: to restore the normal operation, the device must be restarted by toggling the EN pin or performing a power-on reset (POR occurs when the voltage at the LDO5 pin falls below the lower UVLO threshold and subsequently rises above the upper one).
shows an example of open channel detection in case of MODE connected to
AVCC.
At the point marked as “1” in Figure 15
, the row opens (row current drops to zero). From this point on the output voltage is increased as long as the output voltage reaches the floating
row detection threshold (see Section 5.1.3 on page 15 ). Then (point marked as “2”) the
faulty row is disconnected and the device keeps on working only with the remaining rows.
Figure 15. Open channel detection (MODE to AVCC)
When a LED is shorted, the voltage across the related current generator increases of an amount equal to the missing voltage drop of the faulty LED. Since the feedback voltage on each active generator is constantly compared with a fault threshold V
TH,FAULT
, the device detects the faulty condition and acts according to the MODE pin status.
A 100 µs masking time is introduced to support ESD capacitors eventually connected across the LEDs strings.
If the MODE pin is low, the fault threshold is V
TH,FAULT
= 4.0 V. When the voltage across a row is higher than this threshold for more than 100 ms, the FAULT pin is set low and the device is turned off. The internal logic latches this status until the EN pin is toggled or a POR is performed.
In case the MODE pin is connected to AVCC, the LED short-circuit protection is disabled.
The LED7707 simply keeps on regulating the set current without affecting the FAULT pin.
Despite the higher power dissipation, this option is useful to avoid undesired triggering of the shorted-LED protection simply due to the high voltage drop spread across the LEDs.
shows an example of shorted LED detection in case MODE is connected to GND.
At the point marked as “1” in Figure 16 one LED fails becoming a short-circuit. The voltage
across the current generator of the channel where the failed LED is connected increases by an amount equal to the forward voltage of the faulty LED. Since the voltage across the current generator is above the threshold (4 V), the device is turned off and the fault pin is set low (point “2”). Note that, once a new dimming cycle starts (point “3”), the device waits the masking time (approximately 100 ms) and then sets the FAULT pin low and turns off.
Figure 16. Shorted LED detection (MODE to GND)
The boost section of the LED7707 is a fixed frequency, current-mode converter. During normal operation, a minimum voltage selection circuit compares all the voltage drops across the active current generators and provides the minimum one to the error amplifier. The output voltage of the error amplifier determines the inductor peak current in order to keep its inverting input equal to the reference voltage (700 mV typ). The compensation network consists of a simple RC series (R
COMP
- C
COMP
) between the COMP pin and ground.
The calculation of R
COMP and C
COMP is fundamental to achieve optimal loop stability and dynamic performance of the boost converter and is strictly related to the operating conditions.
The compensation network can be quickly calculated using equations 11 to 16. Once both
R
COMP
and C
COMP
have been determined, a fine-tuning phase may be required in order to get the optimal dynamic performance from the application.
The first parameter to be fixed is the switching frequency. Normally, a high switching frequency allows reducing the size of the inductor and positively affects the dynamic response of the converter (wider bandwidth) but increases the switching losses. For most of applications, the fixed value (660 kHz) represents a good trade-off between power dissipation and dynamic response, allowing to save an external resistor at the same time. In low-profile applications, the inductor value is often kept low to reduce the number of turns; an inductor value in the 4.7 µH-15 µH range is a good starting choice.
In order to avoid instability due to interaction between the DC-DC converter's loop and the current generators' loop, the bandwidth of the boost should not exceed the bandwidth of the current generators. A unity-gain frequency (f
U
) in the order of 30-40 kHz is acceptable. Also, take care not to exceed the CCM-mode right half-plane zero (RHPZ).
Equation 11 f
U
≤
0 .
2
⋅
F
SW
Equation 12 f
U
≤
0 .
2
⋅
M
2
R
2
π ⋅
L
=
0 .
2
⋅
V
IN , min
2
V
OUT
2
π ⋅
L
V
OUT
I
OUT
Equation 13a
M
=
V
IN , min
V
OUT
Equation 14b
R =
V
OUT
I
OUT
Where V
IN,min is the minimum input voltage and I
OUT
is the overall output current.
Note that, the lower the inductor value (and the higher the switching frequency), the higher the bandwidth can be achieved. The output capacitor is directly involved in the loop of the boost converter and must be large enough to avoid excessive output voltage drop in case of a sudden line transition from the maximum to the minimum input voltages.
However a more significant requirement concerns the output voltage ripple.
The output capacitor should be chosen in accordance with the following expression:
Equation 15
C
OUT
>
(
I
L , peak
2
⋅
− I
OUT
Δ
V
OUT
)
⋅
, max
T
OFF where
Δ
V
OUT, max
is the maximum acceptable output voltage ripple, I
L, peak
is the peak inductor current, T
OFF
is the off-time of the switching cycle (for an extensive explanation see
).
Once the output capacitor has been chosen, the R
COMP
can be calculated as:
Equation 16
R
COMP
=
G
2 π
M
⋅
⋅ f
U g
EA
⋅ C
⋅
M
Where GM = 2.7 S and g
EA
= 375 µs
Equation 15 places the loop bandwidth at f
U
. Then, the C
COMP
capacitor is determined to place the frequency of the compensation zero 5 times lower than the loop bandwidth:
Equation 17
C
COMP
=
2
π ⋅ f
Z
1
⋅
R
COMP
Where f
Z
= f
U
/5.
In most of the applications an experimental approach is also very valid to compensate the circuit. A simple technique to optimize different applications is to choose C and to replace R
COMP
COMP
= 4.7 nF
with a 10 k
Ω
trimmer adjusting its value to properly damp the output transient response. Insufficient damping will result in excessive ringing at the output and poor phase margin.
(a and b) give an example of compensation adjustment for a typical application.
Figure 17. Poor phase margin (a) and properly damped (b) load transient responses a) b)
V IN = 12V
C
IN
Figure 18. Load transient response measurement set-up
6.8
μ H
V BOOST
2 x 4.7
μ
F
MLCC
+5V
VCC
BILIM
RILIM
SS
COMP
SGND
LED7707
ROW1
ROW2
ROW3
ROW4
ROW5
ROW6
Up to 10 WLEDs per row
R
L
=
V BST
100mA
500Hz
AM00592v1
In order to prevent the device from exceeding the thermal shutdown threshold (150 °C), it is important to estimate the junction temperature through the following equation:
Equation 18
T
J
=
T
A
+
R th , JA
⋅
P
D , tot where T
A
is the ambient temperature, R th,JA is the equivalent thermal resistance junction to ambient and P
D,tot
is the power dissipated by the device.
The R th,JA
measured on the application demonstration board (described in Section 6.5
) is
42 °C/W.
The P
D,tot
has several contributions, listed below.
Conduction losses due to the R
DS(on)
of the internal power switch, equal to:
Equation 19
P
D , cond
=
R
DSon
⋅
I
2
IN
⋅
D
⋅
D
DIM where D is defined as:
Equation 20
D = 1 −
V
IN
V
OUT and D
DIM
is the duty cycle of the PWM dimming signal.
Switching losses due to the power MOSFET turn on and off, calculated as:
Equation 21
P
D , sw
= V
OUT
⋅ I
IN
⋅ f sw
⋅
( t r
+
2 t f
)
⋅ D
DIM where t r
and t f
are the power MOSFET rise time and fall time respectively.
Current generators losses. This contribution is strictly related to the LEDs used in the application. Only the contribution of the leading current generator (“master” current generator) can be predicted, regardless of the LEDs forward voltage:
Equation 22
P
GEN , Master
= I
ROW
⋅ V
IFB
⋅ D
DIM where I
ROW
is the current flowing through the row, whereas V master current generator (typically 700 mV).
IFB
is the voltage across the
The voltages across the other current generators depend on the spread of the LEDs forward voltage. The worst case for power dissipation (maximum forward voltage LEDs in the master row, minimum forward voltage LEDs in all other rows) can be estimated as:
Equation 23
P
GEN
= I
ROW
⋅
( n
ROWs
− 1
)
⋅
(
V
IFB
+ Δ V f , LEDs
⋅ n
LEDs
)
⋅ D
DIM where n
ROWs
is the number of active rows,
Δ
V f,LEDs
is the spread of the LEDs forward voltage and n
LEDs
is the number of LEDs per row.
LDO losses, due to the dissipation of the 5 V linear regulator:
Equation 24
P
D , LDO
=
(
V
IN
− V
LDO
)
⋅ I
LDO
The LED7707 is housed in a 24 leads 4x4-VFQFPN package with exposed pad that allows good thermal performance. However it is also important to design properly the demonstration board layout in order to assure correct heat dissipation.
shows a picture of the LED7707 application demonstration board taken using an infrared camera. The chip temperature, in those application conditions, is kept below 50 °C.
Figure 19. Demonstration board thermographic analysis
Being the LED7707 mostly dedicated to backlighting, real-estate applications dictate severe constrain in selecting the optimal inductor. The inductor choice must take into account different parameters like conduction losses (DCR), core losses (ferrite or iron-powder), saturation current and magnetic-flux shielding (core shape and technology).
The switching frequency of the LED7707 can be set in the 200 kHz-1 MHz range, allowing a wide selecting room for the inductance value. Low switching frequencies takes to high inductance value, resulting in significant DCR and size. On the other hand, high switching frequencies result in significant core losses. The suggested range is 4.7-22 µH, even if the best trade off between the different loss contributions varies from manufacturer to manufacturer.
A 6.8 µH inductor has been experimentally found as the most suitable for applications running at a 660 kHz switching frequency.
Manufacturer
Coilcraft
Coilcraft
Wurth
Table 7. Recommended inductors
Part number Description
LPS6235-682MLC
XPL7030-682ML
7440650068
6.8 μ H, 75 m Ω , 2.7 A
6.8 μ H, 60 m Ω , 5.8 A
6.8 μ H, 33 m Ω , 3.6 A
Size
6x6 mm
7x7 mm
10x10 mm
The input and output capacitors should have very low ESR (ceramic capacitors) in order to minimize the ripple voltage. The boost converter of the LED7707 has been designed to support ceramic capacitors. The required capacitance depends on the programmed LED current and the minimum dimming frequency (the boost converter is off when the DIM pin is
6.3.3 low and the output capacitor is slowly discharged). Considering the worst case (i.e. 200 Hz dimming frequency and 85 mA/channel), two 4.4 µF MLCCs are suitable for almost all applications. Particular care must be taken when selecting the rated voltage and the dielectric type of the output capacitors: 50 V rated MLCC may show a significant capacitance drop when biased, especially in case of Y5V dielectric.
As in most of boost converters, the input capacitor is less critical, although it is necessary to reduce the switching noise on the supply rail. The input capacitor is also important for the internal LDO of the LED7707 and must be kept as close as possible to the chip. The rated voltage of the input capacitor can be chosen according to the supply voltage range; a 10 µF
X5R MLCC is recommended.
Manufacturer
Taiyo Yuden
Murata
Table 8. Recommended capacitors
Part number Description
UMK325BJ106KM-T Ceramic, 35V, X5R, 20%
GRM31CR71H225KA88B Ceramic, 50V, X7R, 20%
Package
SMD 1210
SMD 1206
Notes
C
IN
C
OUT
Flywheel diode selection
The flywheel diode must be a Schottky type to minimize the losses. This component is subject to an average current equal to the output one and must sustain a reverse voltage equal to the maximum output rail voltage. Considering all the channels sinking 75 mA each
(i.e. 450 mA output current) and the maximum output voltage (36 V), the STP1L40M
(I f,ave
= 1 A, V r
= 40 V) diode is a good choice. Smaller diodes can be used in applications involving lower output voltage and/or lower output current.
6.4.1
In order to help the design of an application using the LED7707, in this section a simple step-by-step design example is provided.
A possible application could be the LED backlight in a 17” LCD panel using the LED7707.
Here below the possible application conditions are listed:
• V
IN
= 12 ± 10%
•
4 strings of 42 white LEDs (60 mA) each (arranged in 6 rows, 7LEDs per row)
• V
F, LEDs
= 3.5 V ± 200 mV
Switching frequency setting
To reduce the number of the external components, the default switching frequency is selected (660 kHz typ.) by connecting the FSW pin to AVCC pin.
However, in case a different switching frequency is required, a resistor from FSW pin and ground can be connected, according to the equation (5).
6.4.2 Row current setting
Considering the equation 9 in Section 5.2.1
RILIM
resistor can be calculated as:
Equation 25
R
RILIM
=
K
R
I
ROW
=
1850
60 mA
V
=
30 .
83 k
Ω
The closest standard commercial value is 30 k Ω . The actual value of the row current will be a little lower (61.7 mA).
The boost section, as all DC-DC converters, can work in CCM (continuous conduction mode) or in DCM (discontinuous conduction mode) depending on load current, input and output voltage and other parameters, among which the inductor value.
In a boost converter it is usually preferable to work in DCM.
Once the load, the input and output voltage, and the switching frequency are fixed, the inductor value defining the boundary between DCM and CCM operation can be calculated as:
Equation 26
L
B
=
R
0
⋅ D
2
⋅
(
1 − D
)
2
⋅
F
SW where D is the duty-cycle defined as:
Equation 27
D
=
1
−
V
IN
V
OUT
=
0
0
.
59
.
50
@
@
V
IN , min
V
IN , max
=
=
10 .
8 V
13 .
2 V where as R
0 is:
Equation 28
R
0
=
V
OUT
I
OUT
=
74
Ω and
Equation 29
I
OUT
= 6 ⋅ I
ROW
= 360 mA
The output voltage in the above calculations is considered as the maximum value (LED with the maximum forward voltage connected to the leading generator):
6.4.4
Equation 30
V
OUT , max
=
7
⋅
V
F , LEDs , max
+
700 mV
=
26 .
6 V
Considering the input voltage range, the lower L
B will be at the lower input voltage. Hence the condition to assure the DCM operation becomes:
Equation 31
L
<
L
B
(
V
IN , min
)
=
5 .
6
μ
H
An inductor value of 4.7 µH could be a suitable value, considering also a margin from the boundary condition.
It is important to highlight that the inductor choice involves not only the value itself but the saturation current (higher than the current limit, see
), the rated RMS current
(the compliance with the saturation current might be not enough; also the thermal performances must be taken into account), the DCR (which affects the efficiency) and the size (in some application might be a strict requirement).
However the DCR can’t be reduced keeping the size small. Hence a trade off between these two requirements must be achieved according to the application.
Output capacitor choice
The choice of the output capacitor is mainly affected by the desired output voltage ripple.
Since the voltage across the LEDs can be considered almost constant, this ripple is transferred across the current generators, affecting their dynamic response.
The output ripple can be estimated as (neglecting the contribution of ESR of C
OUT
, very low in case of MLCC):
Equation 32
Δ V
OUT
=
(
I
L , peak
2
− I
OUT
⋅ C
OUT
)
⋅ T
OFF
` where I
L, peak
is the inductor peak current (see
) calculated as:
Equation 33
I
L , peak
=
V
IN
F sw
⋅ D
⋅ L
=
1
1
.
915 A
.
762 A
@
@
V
IN , min
V
IN , max
=
=
10 .
8 V
13 .
2 V whereas D, working in DCM, is:
Equation 34
D
=
2
⋅
F sw
⋅
L
⋅
M ( M
−
1 )
R
0
=
0
0 .
55
.
414
@
@
V
IN , min
V
IN , max
=
=
10 .
8 V
13 .
2 V defining M as:
Equation 35
M =
V
OUT
V
IN
2 .
463
2 .
015
@
@
V
IN , min
V
IN , max
=
=
10 .
8 V
13 .
2 V
Figure 20. Inductor current in DCM operation
I
L
I
L, peak
T
ON
t
T
OFF
T
SW
= 1/F
SW
AM00593v1
T
OFF
can be calculated as:
Equation 36
T
OFF
=
T
SW
⋅
D
2
=
569 .
7 ns
618 .
2 ns
@
@
V
IN , min
V
IN , max
=
=
10 .
8 V
13 .
2 V defining D
2
as:
Equation 37
D
2
=
2 ⋅
R
0
F
SW
⋅
(
M
⋅ L
−
⋅
1
)
M
=
0
0
.
376
.
408
@
@
V
IN , min
V
IN , max
=
=
10 .
8 V
13 .
2 V
The worst case for the output voltage ripple is when input voltage is lower (V
IN,min
= 10.8 V).
A simple way to select the C
OUT value is fixing a maximum voltage ripple.
In order to affect as less as possible the current generators, it would be better to fix the maximum ripple lower than the typical voltage across the generators.
For example considering Δ V
OUT lower than 70 mV (i.e. the 10% of the voltage across the leading generator), the required capacitance is:
Equation 38
C
OUT
>
(
I
L , peak
2 ⋅
− I
OUT
)
⋅ T
OFF
Δ V
OUT , max
= 6 .
33 μ F
A margin from the calculated value should be taken into account because of the capacitance drop due to the applied voltage when MLCCs are used.
One 10 µF MLCC (or two 4.7 µF MLCCs) can be a good choice for this application.
In case a dimming duty cycle different from 100% is used, a further contribution to the capacitor discharge (during the off time of the dimming cycle) should be considered.
6.4.6
The input capacitor of a boost converter is less critical than the output capacitor, due to the fact that the inductor is in series with the input, and hence, the input current waveform is continuous.
A low ESR capacitor is always recommended.
A capacitor of 10 µF is tentatively a good choice for most of the applications.
Overvoltage protection divider setting
The over-voltage protection (OVP) divider provides a partition of the output voltage to the
OVSEL pin. The OVP divider setting not only fixes the OVP threshold, but also the openchannel detection threshold.
The proper OVP divider setting can be calculated by the equation (3):
Equation 39
R
2
= R
1
⋅
V
OUT , MAX
1 .
145 V
+ 4 V − 1 .
145 V where V
OUT, MAX
is the maximum output voltage considering the worst case (all LEDs with the maximum V
F
= V
F,max
= 3.7 V on the same row):
Equation 40
V
OUT , OVP
= nLED ⋅ V
F , max
+ 700 mV = 26 .
6 V
R
1 can be chosen is in the order of hundreds of kilo-ohms to reduce the leakage current in the resistor divider. For example, setting R standard commercial value is R
2
= 22 k Ω .
1
= 510 k Ω leads to R
2
= 21.89 k Ω . The closest
For the compensation network, the suggestions provided in Section 6.1
are always valid.
In this condition, tentatively the following value of R3 and C8 (see
) are usually a good choice for the loop stability:
R3 = 2.4 k Ω
C8 = 4.7 nF
The boost current limit is set to protect the internal power switch against excessive current.
The slope compensation may reduce the programmed current limit. Hence, to take into account this effect, as a rule of thumb, the current limit can be set as twice as much the
maximum inductor peak current (see Section 6.4.4
6.4.9
I
BOOST, PEAK
> 3.83 A
Therefore, using equation (7) and choosing I
BOOST, PEAK
= 4 A, R
BILIM
is:
Equation 41
R
BILIM
=
K
B
I
BOOST , PEAK
=
300 k
Ω
Power dissipation estimate
As explained in section 5.2, there are several contributions to the total power dissipation.
Neglecting the power dissipated by the LDO (surely less significant compared with the other contributions), equation (18), (20), (21) and (22) help to estimate the overall power dissipation.
Before starting the power dissipation estimate it is important to highlight that the following calculations are considering the worst case (the actual value of the dissipated power would require measurements). Therefore the power dissipation is estimated according to the following assumptions:
1.
Minimum input voltage (10.8 V), which leads to maximum input current (and also D will have the higher value, see
)
R
DS(on)
of the internal power MOSFET
3. LEDs in the row of the leading generator will have the maximum forward voltage, whereas all other LEDs in the other rows will have the minimum forward voltage
4. 100% dimming signal duty cycle is considered
The conduction and switching losses on the internal power switch can be calculated as:
Equation 42
P
D , cond
= R
DSon
⋅ I
2
IN
⋅ D ⋅ D
DIM
= 216 mW
Equation 43
P
D , sw
=
V
OUT
⋅
I
IN
⋅ f sw
⋅
( t r
+ t f
)
⋅
D
DIM
2
=
233 mW where t r
= t f
= 15 ns
The power dissipation related to the current generators is given by:
Equation 44
P
GEN , Master
=
I
ROW
⋅
V
IFB
⋅
D
DIM
=
42 mW
Equation 45
P
GEN
=
I
ROW
⋅
( n
ROWs
−
1
)
⋅
(
V
IFB
+ Δ
V f , LEDs
⋅ n
LEDs
)
⋅
D
DIM
=
630 mW
Note:
Equation 46
P
D , tot
≅
P
D , cond
+
P
D , sw
+
P
GEN , Master
+
P
GEN
=
1 .
12 W
The junction temperature can be estimated by equation (18) considering T
A
= 25 °C:
Equation 47
T
J
=
T
Amb
+
R th , JA
⋅
P
D , tot
=
72
°
C
In order to estimate also the efficiency, other contributions to the power dissipation must be added to P
D, tot
(which represents only the power dissipated by the device), that is:
Equation 48
P
DISS , Diode
=
V
F , Diode
⋅
I
IN
⋅
D
2
=
133 mW where V
F, Diode
= 0.4 V
Equation 49
P
DISS , Ind
=
DCR
⋅
I
2
Ind , RMS
≅
DCR
⋅
I
2
IN
=
63 mW where DCR = 80 m Ω (typical DCR of the recommended inductors).
Therefore the total dissipated power is:
Equation 50
P
DISS , TOTAL
=
P
D , tot
+
P
DISS , Diode
+
P
DISS , Ind
=
1 .
316 W
Considering the input power as the result of input voltage multiplied by the input current, the estimated efficiency is:
Equation 51
η =
P
IN
−
P
DISS , TOT
P
IN
=
0 .
862
It is important to remind that the previous calculations consider the worst case, especially for the power dissipated on the current generators.
Statistical analysis (confirmed by bench measurements) shows that the series connection of more LEDs on each channel leads to compensation effects.
The hypothesis 3 above mentioned is thus rather unlikely.
Therefore P
GEN
is significantly lower and the overall efficiency is typically around 90%.
1.
A careful PCB layout is important for proper operation. In this section some guidelines are provided in order to achieve a good layout.
2. The device has two different ground pins: signal ground (SGND) and power ground
(PGND). The PGND pin handles the switching current related to the boost section; for this reason the PCB traces should be kept as short as possible and with adequate width.
3. The signal ground is the return for the device supply and the current generators and can be connected to the thermal pad.
4. The heat dissipation area (adequate to the application conditions) should be placed backside respect to the device and with the lowest thermal impedance possible (i.e.
PCB traces in the backside should be avoided). The dissipation area is thermally and electrically connected to the thermal pad by several vias (nine vias are recommended).
5. The signal and power grounds must be connected together in a single point as close as possible to the PGND pin to reduce ground loops.
6. The R-C components of the compensation network should be placed as close as possible to the COMP pin in order to avoid noise issue and instability of the compensation.
7. Noise sensitive signals (i.e. feedbacks and compensation) should be routed as short as possible to minimize noise collection. The LED7707 pinout makes it easy to separate power components (e.g. inductor, diode) from signal ones.
8. The LX switching node should have and adequate width for high efficiency.
9. The critical power path inductor-LX-PGND must be as short as possible by mounting the inductor, the diode and COUT as close as possible each other.
10. The capacitors of the compensated divider connected to the OVSEL pin should be placed as close as possible to the OVSEL pin.
11. In order to assure good performance in terms of row current accuracy/mismatch, the
PCB traces from the rows pins to the LEDs should have similar length and width.
12. The capacitors of the filter connected to LDO5 and VIN pins should be mounted as close as possible to the mentioned pins.
Figure 21 and Figure 22 shows the demonstration board layout (top view and bottom view
respectively).
Figure 21. Demonstration board layout (top view)
Figure 22. Demonstration board layout (bottom view)
shows the LED7707 demonstration board application circuit, whereas
lists the used components and their value.
Figure 23. LED7707 demonstration board schematic
Component
C1
Table 9. LED7707 demonstration board component list
Description Package Part number MFR
Ceramic, 35 V
X5R, 20 %
SMD 1210 UMK325BJ106KM-T Taiyo Yuden
Ceramic, 50 V
X7R, 20 %
SMD 1206
SMD 1206
GRM31CR71H475KA88B
GRM31CR71H225KA88B
Murata
C9
C10
C11
C12
C13
R1
R2
C2, C3
C4
C5
C6
C7
C8
R3
R4
R5
R6
Ceramic, 25 V
X5R, 20%
Chip resistor
0.1 W, 1%
SMD 0603
SMD 0603
R7
Chip resistor
0.1 W, 1%
SMD 0603
R8
R9, R10
R11
R12
R13
L1
D1
D2
D3
U1
J2
J8
SW1, SW2
SW3
6u8, 60 m Ω , 5.8 A 7x7 mm
Schottky, 40 V, 1 A DO216-AA
Red LED, 3 mA
Signal Schottky
SMD 0603
SOD-523
QFN4x4 Integrated circuit
PCB pad jumper
Header 8
Jumper 3
Push button
SIL 8
SIL 3
6x6 mm
XPL7030-682ML
STPS1L40M
LED7707
FSM4JSMAT
Standard
Standard
Standard
Coilcraft
ST
Standard
BAS69
ST
Standard
Standard
TYCO
Value
10 µF
360 k Ω
680 k Ω
100 k
Ω
1.2 k Ω
N.M.
N.M.
6.8 µF
STPS1L40M
4.7 µF
N.M.
1 µF
100 nF
3.3 nF
4.7 nF
N.M.
220 pF
4.7 nF
N.M.
15 pF
510 k Ω
16 k Ω
2.4 k Ω
4.7
Ω
330 k Ω
24 k
Ω
N.M.
LED7707
Figure 24. Efficiency versus DIM duty cycle, V
IN
= 12 V, 6 rows, 10 white LEDs (60 mA) in series,
F
SW
= 660 kHz
Figure 25. Efficiency versus DIM duty cycle, V
IN
= 18 V, 6 rows, 10 white LEDs (60 mA) in series,
F
SW
= 660 kHz
Figure 26. Efficiency versus DIM duty cycle, V
IN
= 24 V, 6 rows, 10 white LEDs (60 mA) in series,
F
SW
= 825 kHz
Figure 27. Efficiency versus DIM duty cycle, V
IN
= 24 V, 6 rows, 10 white LEDs (60 mA) in series,
F
SW
= 825 kHz
Figure 28. Soft-start waveforms (EN, SS, and
V
OUT
monitored)
Figure 29. Boost section switching signals (LX,
SYNC and inductor current monitored), V
IN
= 12
V, 10 LEDs
Figure 30. Dimming waveforms (F
DIM
= 200 Hz) Figure 31. Dimming waveforms (F
DIM
= 1 kHz)
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK
®
is an ST trademark.
Figure 32. VFQFPN-24 4x4 mm package outline
b
D
D2
A
A1
A3
E
E2 e
L ddd
Dim.
Table 10. VFQFPN-24 4x4 mm mechanical data mm
Min.
Typ.
0.80
0.00
0.18
3.85
2.40
3.85
2.40
0.30
0.90
0.02
0.20
0.25
4.00
2.50
4.00
2.50
0.50
0.40
Max.
1.00
0.05
0.30
4.15
2.60
4.15
2.60
0.50
0.08
Date
18-Sep-2008
20-Oct-2008
10-Apr-2009
11-Sep-2018
15-Oct-2018
Table 11. Document revision history
Revision Changes
1
2
3
4
5
Initial release.
Updated Table 3 and Table 5.
Removed Table 4.
Updated Table 4, Table 5, Figure 3, Figure 4, Figure 8,
Figure 9 and Table 9.
Updated Section 5.2.1: Current generators.
Minor text changes.
Updated Section 5.2.2: PWM dimming .
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