STMicroelectronics M48Z58Y Datasheet
Publicité
Publicité
M48Z58, M48Z58Y
28
28
1
SOH28
5 V, 64 Kbit (8 Kbit x 8) ZEROPOWER® SRAM
Datasheet production data
•
Pin and function compatible with JEDEC standard 32 Kbit x 8 SRAMs
•
RoHS compliant
•
Lead-free second level interconnect
1
PDIP 28.7
Battery CAPHAT™
SNAPHAT ® battery
Features
•
Integrated, ultra low power SRAM, power-fail control circuit, and battery
•
READ cycle time equals WRITE cycle time
•
Automatic power-fail chip deselect and WRITE protection
•
WRITE protect voltages:
(V
PFD
= power-fail deselect voltage)
•
M48Z35: V
CC
4.5 V
≤
V
PFD
= 4.75 to 5.5 V;
≤
4.75 V
•
M48Z35Y: 4.5 to 5.5 V;
4.2 V
≤
V
PFD
≤
4.5 V
•
Self-contained battery in the CAPHAT
™
DIP package
•
Packaging includes a 28-lead SOIC and
SNAPHAT
®
top (to be ordered separately)
•
SOIC package provides direct connection for a
SNAPHAT
®
top which contains the battery
Description
The M48Z58/Y ZEROPOWER® RAM is an 8 Kbit x 8 non-volatile static RAM that integrates powerfail deselect circuitry and battery control logic on a single die. The monolithic chip is available in two special packages to provide a highly integrated battery-backed memory solution.
The M48Z58/Y is a non-volatile pin and function equivalent to any JEDEC standard 8 K x 8 SRAM.
It also easily fits into many ROM, EPROM, and
EEPROM sockets, providing the non-volatility of
PROMs without any requirement for special
WRITE timing or limitations on the number of
WRITEs that can be performed.
The 28-pin, 600 mil DIP CAPHAT™ houses the
M48Z58/Y silicon with a long life lithium button cell in a single package.
The 28-pin, 330 mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT® housing containing the battery. The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the
SNAPHAT housing after reflow prevents potential battery damage due to the high temperatures required for device surface-mounting.
The SNAPHAT housing is keyed to prevent reverse insertion.
The SOIC and battery packages are shipped separately in plastic anti-static tubes or in tape & reel form.
For the 28-lead SOIC, the battery package (e.g.,
SNAPHAT) part number is “M4Z28-BR00SH1.
October 2020
This is information on a product in full production.
DocID02559 Rev 12 1/21 www.st.com
Contents
Contents
M48Z58, M48Z58Y
noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 10
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/21 DocID02559 Rev 12
M48Z58, M48Z58Y
1 Diagram
Figure 1. Logic diagram
VCC
A0-A12
13
W
E
G
M48Z58
M48Z58Y
8
DQ0-DQ7
A0-A12
DQ0-DQ7
E
G
W
V
CC
V
SS
NC
VSS
Table 1. Signal names
Address inputs
Data inputs / outputs
Chip enable input
Output enable input
WRITE enable input
Supply voltage
Ground
Not connected internally
Diagram
AI01176B
DocID02559 Rev 12 3/21
21
Pin connection
2 Pin connection
Figure 2. DIP connections
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
9
10
11
7
8
5
6
3
4
1
2
12
13
14
M48Z58
M48Z58Y
20
19
18
24
23
22
21
17
16
15
28
27
26
25
VCC
W
NC
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Figure 3. SOIC connections
NC
A0
DQ0
DQ1
DQ2
VSS
A12
A7
A6
A5
A4
A3
A2
A1
1
6
7
8
9
4
5
2
3
10
11
12
13
14
M48Z58Y
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
W
NC
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
M48Z58, M48Z58Y
AI01177B
AI01178B
4/21 DocID02559 Rev 12
M48Z58, M48Z58Y Pin connection
Figure 4. Block diagram
LITHIUM
CELL
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
POWER
VPFD
8K x 8
SRAM ARRAY
VCC VSS
A0-A12
DQ0-DQ7
E
W
G
AI01394
DocID02559 Rev 12 5/21
21
Operation modes
3 Operation modes
Note:
3.1
M48Z58, M48Z58Y
The M48Z58/Y also has its own power-fail detect circuit. The control circuitry constantly monitors the single 5 V supply for an out of tolerance condition. When V
CC
is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low V
CC
. As V
CC
falls below battery switchover voltage (V
SO
), the control circuitry connects the battery which maintains data until valid power returns.
Mode V
CC
Deselect
WRITE
READ
4.75 to 5.5 V or
4.5 to 5.5 V
READ
Deselect V
SO
to V
PFD
(min)
(1)
Deselect
≤
V
SO
(1)
Table 2. Operating modes
E G W
V
IH
V
IL
V
IL
V
IL
X
X
X
X
V
IL
V
IH
X
X
X
V
IL
V
IH
V
IH
X
X
DQ0-
DQ7
Power
High Z
D
IN
D
OUT
High Z
High Z
Standby
Active
Active
Active
CMOS standby
High Z Battery backup mode
X = V
IH
or V
IL;
V
SO
= battery backup switchover voltage.
READ mode
The M48Z58/Y is in the READ mode whenever W (WRITE enable) is high, E (chip enable) is low. Thus, the unique address specified by the 13 address inputs defines which one of the
8,192 bytes of data is to be accessed. Valid data will be available at the data I/O pins within address access time (t
AVQV
) after the last address input signal is stable, providing that the E and G access times are also satisfied. If the E and G access times are not met, valid data will be available after the latter of the chip enable access time (t
ELQV
) or output enable access time (t
GLQV
).
The state of the eight three-state data I/O signals is controlled by E and G. If the outputs are activated before t
AVQV
, the data lines will be driven to an indeterminate state until t
AVQV
. If the address inputs are changed while E and G remain active, output data will remain valid for output data hold time (t
AXQX
) but will go indeterminate until the next address access.
6/21 DocID02559 Rev 12
M48Z58, M48Z58Y Operation modes
A0-A12
Figure 5. READ mode AC waveforms tAVAV
VALID tAVQV tELQV tAXQX tEHQZ
E tELQX tGLQV tGHQZ
G tGLQX
DQ0-DQ7 VALID
AI01385
Note: WRITE enable (W) = high.
Symbol
Table 3. READ mode AC characteristics
M48Z02/M48Z12
Parameter
(1)
Min.
Max.
t
AVAV t
AVQV t
ELQ t
GLQV t
ELQX
(2) t
GLQX
(2) t
EHQZ
(2) t
GHQZ
(2) t
AXQX
READ cycle time
Address valid to output valid
Chip enable low to output valid
Output enable low to output valid
Chip enable low to output transition
Output enable low to output transition
Chip enable high to output Hi-Z
Output enable high to output Hi-Z
Address transition to output transition
70
5
5
10
70
70
35
25
25
1. Valid for ambient operating temperature: T
A
= 0 to 70 °C; V
CC
= 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted).
2. C
L
)
Unit ns ns ns ns ns ns ns ns ns
DocID02559 Rev 12 7/21
21
Operation modes M48Z58, M48Z58Y
3.2 WRITE mode
The M48Z58/Y is in the WRITE mode whenever W and E are low. The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of t
EHAX
from chip enable or t
WHAX
from WRITE enable prior to the initiation of another READ or WRITE cycle. Data-in must be valid t
DVWH
prior to the end of WRITE and remain valid for t
WHDX
afterward. G should be kept high during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G, a low on W will disable the outputs t
WLQZ
after W falls.
Figure 6. WRITE enable controlled, WRITE AC waveform
A0-A12 tAVAV
VALID tAVWH tAVEL tWHAX
E tWLWH tAVWL
W tWLQZ tWHQX
DQ0-DQ7 tWHDX
DATA INPUT tDVWH
AI01386
A0-A12
Figure 7. Chip enable controlled, WRITE AC waveforms tAVEL tAVAV
VALID tAVEH tELEH tEHAX
E tAVWL
W tEHDX
DQ0-DQ7 DATA INPUT tDVEH
AI01387B
8/21 DocID02559 Rev 12
M48Z58, M48Z58Y Operation modes
Table 4. WRITE mode AC characteristics
M48Z35/M48Z35Y
Parameter
(1)
-70 Symbol
Min.
Max.
t
DVEH t
WHDX t
EHDX t
WLQZ
(2)(3) t
AVWH t
AVEH t
WHQX
(2)(3) t
AVAV t
AVWL t
AVEL t
WLWH t
ELEH t
WHAX t
EHAX t
DVWH
WRITE cycle time
Address valid to WRITE enable low
Address valid to chip enable 1 low
WRITE enable pulse width
Chip enable low to chip enable 1 high
WRITE enable high to address transition
Chip enable high to address transition
Input valid to WRITE enable high
Input valid to chip enable high
WRITE enable high to input transition
Chip enable high to input transition
WRITE enable low to output Hi-Z
Address valid to WRITE enable high
Address valid to chip enable high
WRITE enable high to output transition
70
0
0
50
55
0
0
30
30
5
5
60
60
5
25
1. Valid for ambient operating temperature: T
A
= 0 to 70 °C; V
CC
= 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted).
2. C
L
)
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
3.3
Note:
Data retention mode
With valid V
CC
applied, the M48Z58/Y operates as a conventional BYTEWIDE™ static
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when V
CC
falls within the V
PFD
(max), V
PFD
(min) window. All outputs become high impedance, and all inputs are treated as “Don't care.”
A power failure during a WRITE cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM's content. At voltages below V
PFD
(min), the user can be assured the memory will be in a write protected state, provided the V
CC
fall time is not less than t
F
. The M48Z58/Y may respond to transient noise spikes on V into the deselect window during the time the device is sampling V
CC
CC
that reach
. Therefore, decoupling of the power supply lines is recommended.
When V
CC
drops below V
SO
, the control circuit switches power to the internal battery which preserves data. The internal button cell will maintain data in the M48Z58/Y for an accumulated period of at least 10 years when V
CC
is less than V
SO
.
As system power returns and V
CC
rises above V
SO power supply is switched to external V
CC
, the battery is disconnected, and the
. Normal RAM operation can resume t rec
after V
CC exceeds V
PFD
(max).
For more information on battery storage life refer to the application note AN1012.
DocID02559 Rev 12 9/21
21
Operation modes
3.4
M48Z58, M48Z58Y
V
CC
noise and negative going transients
I
CC
transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the V
CC
bus. These transients can be reduced if capacitors are used to store energy which stabilizes the V
CC
bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 µF (see
Figure 8 ) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on V
CC
that drive it to values below V
SS
by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, ST recommends connecting a schottky diode from V
CC
to V
SS
(cathode connected to V
CC
, anode to V
SS
). (Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount).
Figure 8. Supply voltage protection
VCC
VCC
0.1
µ F DEVICE
VSS
AI02169
10/21 DocID02559 Rev 12
M48Z58, M48Z58Y
4 Maximum ratings
Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Symbol
Table 5. Absolute maximum ratings
Parameter Value Unit
T
A
Ambient operating temperature 0 to 70 °C
T
STG
Storage temperature (V
CC
off, oscillator off)
SNAPHAT
® top
CAPHAT
®
DIP
SOH28
–40 to 85
–40 to 85
–40 to 85
°C
°C
°C
T
SLD
(1) (2)
V
IO
V
CC
I
O
P
D
Lead solder temperature for 10 seconds
Input or output voltages
Supply voltage
Output current
Power dissipation
260
–0.3 to 7
–0.3 to 7
20
1
°C
V
V mA
W
1. For DIP package, soldering temperature of the IC leads is to not exceed 260 °C for 10 seconds.
Furthermore, the devices shall not be exposed to IR reflow nor preheat cycles (as performed as part of wave soldering). ST recommends the devices be hand-soldered or placed in sockets to avoid heat damage to the batteries.
2. For SOH28 package, lead-free (Pb-free) lead finish: reflow at peak temperature of 260 °C (the time above
255 °C must not exceed 30 seconds).
Caution: Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup mode.
Caution: Do NOT wave solder SOIC to avoid damaging SNAPHAT
®
sockets.
DocID02559 Rev 12 11/21
21
DC and AC parameters
5 DC and AC parameters
Note:
M48Z58, M48Z58Y
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC characteristic
tables are derived from tests performed under the measurement conditions listed in Table 6 .
Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters.
Table 6. Operating and AC measurement conditions
Parameter M48Z35 M48Z35Y
Supply voltage (V
CC
)
Ambient operating temperature (T
A
)
Load capacitance (C
L
)
Input rise and fall times
Input pulse voltages
Input and output timing ref. voltages
4.75 to 5.5
0 to 70
100
≤ 5
0 to 3
1.5
4.5 to 5.5
0 to 70
100
≤ 5
0 to 3
1.5
Unit
V
°C pF ns
V
V
Output Hi-Z is defined as the point where data is no longer driven.
Figure 9. AC measurement load circuit
5V
DEVICE
UNDER
TEST
1k Ω
1.9k
Ω
OUT
CL = 100pF or 5pF
12/21
CL includes JIG capacitance
Symbol
Table 7. Capacitance
Parameter
(1)(2)
Min.
Max.
C
IN
C
IO
(3)
Input capacitance
Input / output capacitance -
10
10
1. Effective capacitance measured with power supply at 5 V. Sampled only, not 100% tested.
2. At 25 °C, f = 1 MHz.
3. Outputs deselected.
AI01030
Unit pF pF
DocID02559 Rev 12
M48Z58, M48Z58Y DC and AC parameters
Symbol Parameter
Table 8. DC characteristics
Test condition
(1)
Min.
Max.
I
LI
I
LO
(2)
I
CC
I
CC1
I
CC2
V
IL
V
V
V
IH
OL
OH
Input leakage current
Output leakage current
Supply current
Supply current (standby) TTL
Supply current (standby) CMOS
Input low voltage
Input high voltage
Output low voltage
Output high voltage
0 V
≤
V
IN
≤
V
CC
0 V ≤ V
OUT
≤ V
CC
Outputs open
E = V
E = V
CC
IH
– 0.2 V
I
OL
= 2.1 mA
I
OH
= –1 mA
–0.3
2.2
2.4
±1
±1
50
3
3
0.8
V
CC
+ 0.3
0.4
1. Valid for ambient operating temperature: T
A
= 0 to 70 °C; V
CC
= 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted).
2. Outputs deselected.
Unit mA
V
V
V
V
µA
µA mA mA
Figure 10. Power down/up mode AC waveforms
VCC
VPFD (max)
VPFD (min)
VSO
INPUTS tPD tF
RECOGNIZED tFB tDR tRB
DON'T CARE
HIGH-Z tR trec
RECOGNIZED
OUTPUTS VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
AI01168C
DocID02559 Rev 12 13/21
21
DC and AC parameters M48Z58, M48Z58Y
Symbol
Table 9. Power down/up AC characteristics
Parameter
(1)
Min.
Max.
Unit t
PD t
F
(2) t
FB
(3) t
R t
RB t rec
E or W at V
V
PFD
V
PFD
V
PFD
V
SS
V
to V
PFD
PFD
IH
before power down
(max) to V
PFD
(min) to V
SS
(min) to V
PFD
(min) V
CC
V
CC
(min) V
CC
fall time
(max) V
fall time
CC
rise time rise time
(max) to inputs recognized
0
300
10
10
1
40 200
µs
µs
µs
µs
µs ms
1. Valid for ambient operating temperature: T
A noted).
= 0 to 70 °C; V
CC
= 4.75 to 5.5 V or 4.5 to 5.5 V (except where
2. V
PFD
(max) to V
PFD
(min) fall time of less than t
F
may result in deselection/write protection not occurring until 200 µs after V
CC
passes V
PFD
(min).
3. V
PFD
(min) to V
SS
fall time of less than t
FB
may cause corruption of RAM data.
Symbol
Table 10. Power down/up trip points DC characteristics
Parameter
(1)(2)
Min.
Typ.
Max.
Unit
M48Z58 4.5
4.6
4.75
V
V
PFD
Power-fail deselect voltage
M48Z58Y 4.2
4.35
4.5
V
V
SO t
DR
(3)
Battery backup switchover voltage
Expected data retention time 10
3.0
V
Years
1. All voltages referenced to V
SS
.
2. Valid for ambient operating temperature: T
A noted).
= 0 to 70 °C; V
CC
= 4.75 to 5.5 V or 4.5 to 5.5 V (except where
3. At 25 °C, V
CC
= 0 V.
14/21 DocID02559 Rev 12
M48Z58, M48Z58Y
6 Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK is an ST trademark.
Figure 11. PDIP 28.7 – 28-pin plastic DIP, battery CAPHAT™, package outline
Note:
A2 A
B1 e3
B
D
A1 e1
L eA
C
N
E
1
PCDIP
Drawing is not to scale.
Table 11. PDIP 28.7 – 28 pin plastic DIP, battery CAPHAT™, package mech. data mm inches
Symb
Typ.
Min.
Max.
Typ.
Min.
Max.
B1
C
D
E
A
A1
A2
B e1 e3 eA
L
N
33.02
8.89
0.38
8.38
0.38
1.14
0.20
39.37
17.83
2.29
15.24
3.05
28
9.65
0.76
8.89
0.53
1.78
0.31
39.88
18.34
2.79
16.00
3.81
1.3
0.350
0.015
0.330
0.015
0.045
0.008
1.550
0.702
0.090
0.600
0.120
28
0.380
0.030
0.350
0.021
0.070
0.012
1.570
0.722
0.110
0.630
0.150
DocID02559 Rev 12 15/21
21
Package mechanical data M48Z58, M48Z58Y
Table 12. SOH28 – 28-lead plastic small outline, battery SNAPHAT
®
, pack. outline
A2 A
C
B e
CP eB
N
D
Note:
E H
A1 α L
1
SOH-A
Drawing is not to scale.
Table 13. SOH28 – 28-lead plastic small outline, battery SNAPHAT
®
, pack. mech. data mm inches
Symbol
Typ.
Min.
Max.
Typ.
Min.
Max.
a
N
CP e eB
H
L
D
E
B
C
A
A1
A2
1.27
0.05
2.34
0.36
0.15
17.71
8.23
–
3.20
11.51
0.41
0°
28
3.05
0.36
2.69
0.51
0.32
18.49
8.89
–
3.61
12.70
1.27
8°
0.10
0.050
0.002
0.092
0.014
0.006
0.697
0.324
–
0.126
0.453
0.016
0°
28
0.120
0.014
0.106
0.020
0.012
0.728
0.350
–
0.142
0.500
0.050
8°
0.004
16/21 DocID02559 Rev 12
M48Z58, M48Z58Y Package mechanical data
Table 14. SH – 4-pin SNAPHAT
®
housing for 48 mAh battery, package outline eA
D
A1
A
B eB
A3
A2
L
Note:
E
SHZP-A
Drawing is not to scale.
Table 15. SH – 4-pin SNAPHAT® housing for 48 mAh battery, pack. mech. data mm inches
Symbol
Typ.
Min.
Max.
Typ.
Min.
Max.
A3
B
D
E eA
A
A1
A2 eB
L
6.73
6.48
0.46
21.21
14.22
15.55
3.20
2.03
9.78
7.24
6.99
0.38
0.56
21.84
14.99
15.95
3.61
2.29
0.265
0.255
0.018
0.835
0.560
0.612
0.126
0.080
0.385
0.285
0.275
0.015
0.022
0.860
0.590
0.628
0.142
0.090
DocID02559 Rev 12 17/21
21
Part numbering
7 Part numbering
M48Z58, M48Z58Y
Order code
M48Z58-70PC1
M48Z58Y-70PC1
M48Z58Y-70MH1F
Package
PDIP 28.7
SOH28
Table 16. Ordering information
Temperature range
Speed
0 to 70 °C 70
Supply voltage
V
CC
= 4.75 to 5.5 V; V
PFD
= 4.5 to 4.75 V
V
CC
= 4.5 to 5.5 V; V
PFD
= 4.2 to 4.5 V
V
CC
= 4.75 to 5.5 V; V
PFD
= 4.5 to 4.75 V
Caution: Do not place the SNAPHAT battery package “M4Zxx-BR00SH1” in conductive foam as it will drain the lithium button-cell battery.
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
Part number
M4Z28-BR00SH1
M4Z32-BR00SH1
Table 17. SNAPHAT® battery table
Description
Lithium battery (48 mAh) SNAPHAT
®
Lithium battery (120 mAh) SNAPHAT
®
Package
SH
SH
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8 Environmental information
Figure 12. Recycling symbols
Environmental information
This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry) button cell battery fully encapsulated in the final product.
Recycle or dispose of batteries in accordance with the battery manufacturer's instructions and local/national disposal and recycling regulations.
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Revision history
9 Revision history
M48Z58, M48Z58Y
Date
March 1999
10-Feb-2000
22-Feb-2000
14-Sep-2001
29-May-2002
16-Sep-2002
02-Apr-2003
23-Mar-2004
23-Nov-2004
09-Jun-2005
14-Dec-2005
06-Nov-2007
10-Mar-2009
14-Oct-2010
07-Jun-2011
21-Oct-2020
Revision
Table 18. Document revision history
Changes
2.1
2.2
3
4
1
1.1
1.2
2
5
6
7
8
9
10
11
12
First issue
2-socket SOH and 2-pin SH packages removed
Data retention mode paragraph changed
Reformatted; added temperature information (Table 7, 8, 3, 4, 9, 10)
Modify reflow time and temperature footnotes (Table 5)
Remove footnote from ordering information (Table 15) v2.2 template applied; test condition updated (Table 10)
Reformatted; updated lead-free information (Table 5, 15)
Remove references to industrial temperature grade (Table 3, 4, 5, 6, 8,
9, 10, 15)
Removal of SNAPHAT
®
, industrial temperature sales types (Table 3,
4, 5, 6, 7, 8, 10, 15)
Updated lead-free text (Table 15)
Reformatted; added lead-free second level interconnect information to cover page and Section 5: Package mechanical data; updated Table
5, 15, 16.
Section 5: Package mechanical data; updated Table 5, 15, 16.
Updated Table 5, text in Section 5: Package mechanical data; added
Section 7: Environmental information; minor reformatting.
Updated Section 3, Table 11; reformatted document.
Updated footnote 1 of Table 5: Absolute maximum ratings; updated
Section 7: Environmental information
Added
Table 16: Ordering information
.
Updated package name.
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