STMicroelectronics STM32F303RC Datasheet
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STM32F303xB STM32F303xC
Arm
®
-based Cortex
®
-M4 32b MCU+FPU, up to 256KB Flash+
48KB SRAM, 4 ADCs, 2 DAC ch., 7 comp, 4 PGA, timers, 2.0-3.6 V
Datasheet
-
production data
Features
• Core: Arm ® Cortex ® -M4 32-bit CPU with FPU
(72 MHz max), single-cycle multiplication and
HW division, 90 DMIPS (from CCM), DSP instruction and MPU (memory protection unit)
• Operating conditions:
– V
DD
, V
DDA
voltage range: 2.0 V to 3.6 V
• Memories
– 128 to 256 Kbytes of Flash memory
– Up to 40 Kbytes of SRAM, with HW parity check implemented on the first 16 Kbytes.
– Routine booster: 8 Kbytes of SRAM on instruction and data bus, with HW parity check (CCM)
• CRC calculation unit
• Reset and supply management
– Power-on/power-down reset (POR/PDR)
– Programmable voltage detector (PVD)
– Low-power modes: Sleep, Stop and
Standby
– V
BAT
supply for RTC and backup registers
• Clock management
– 4 to 32 MHz crystal oscillator
– 32 kHz oscillator for RTC with calibration
– Internal 8 MHz RC with x 16 PLL option
– Internal 40 kHz oscillator
• Up to 87 fast I/Os
– All mappable on external interrupt vectors
– Several 5 V-tolerant
• Interconnect matrix
• 12-channel DMA controller
• Four ADCs 0.20 µS (up to 39 channels) with selectable resolution of 12/10/8/6 bits, 0 to
3.6 V conversion range, single ended/differential input, separate analog supply from 2 to 3.6 V
• Two 12-bit DAC channels with analog supply from 2.4 to 3.6 V
LQFP48 (7 × 7 mm)
LQFP64 (10 × 10 mm)
LQFP100 (14 × 14 mm)
WLCSP100 (0.4 mm pitch)
• Seven fast rail-to-rail analog comparators with analog supply from 2 to 3.6 V
• Four operational amplifiers that can be used in
PGA mode, all terminals accessible with analog supply from 2.4 to 3.6 V
• Up to 24 capacitive sensing channels supporting touchkey, linear and rotary touch sensor s
• Up to 13 timers
– One 32-bit timer and two 16-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
– Two 16-bit 6-channel advanced-control timers, with up to 6 PWM channels, deadtime generation and emergency stop
– One 16-bit timer with 2 IC/OCs, 1
OCN/PWM, deadtime generation and emergency stop
– Two 16-bit timers with IC/OC/OCN/PWM, deadtime generation and emergency stop
– Two watchdog timers (independent, window)
– SysTick timer: 24-bit downcounter
– Two 16-bit basic timers to drive the DAC
• Calendar RTC with Alarm, periodic wakeup from Stop/Standby
• Communication interfaces
– CAN interface (2.0B Active)
– Two I
2
C Fast mode plus (1 Mbit/s) with
20 mA current sink, SMBus/PMBus, wakeup from STOP
October 2018
This is information on a product in full production.
DS9118 Rev 14
www.st.com
STM32F303xB STM32F303xC
– Up to five USART/UARTs (ISO 7816 interface, LIN, IrDA, modem control)
– Up to three SPIs, two with multiplexed half/full duplex I2S interface, 4 to 16 programmable bit frames
– USB 2.0 full speed interface
– Infrared transmitter
• Serial wire debug, Cortex ®
JTAG
-M4 with FPU ETM,
• 96-bit unique ID
Table 1. Device summary
Reference Part number
STM32F303xB
STM32F303xC
STM32F303CB, STM32F303RB, STM32F303VB
STM32F303CC, STM32F303RC, STM32F303VC
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STM32F303xB STM32F303xC
Contents
Contents
® Cortex ® -M4 core with FPU with embedded Flash and SRAM . . . . 14
Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Cyclic redundancy check (CRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power supply supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Direct memory access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 20
Fast analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
REFINT
) . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
OPAMP reference voltage (VREFOPAMP) . . . . . . . . . . . . . . . . . . . . . . 22
Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Fast comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Advanced timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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Contents STM32F303xB STM32F303xC
General-purpose timers (TIM2, TIM3, TIM4, TIM15, TIM16, TIM17) . . . 24
Basic timers (TIM6, TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 25
Inter-integrated circuit interface (I 2
C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Universal synchronous/asynchronous receiver transmitter (USART) . . . 27
Universal asynchronous receiver transmitter (UART) . . . . . . . . . . . . . . . 27
Serial peripheral interface (SPI)/Inter-integrated sound interfaces (I2S) . 28
Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 31
Embedded trace macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 61
Embedded reset and power control block characteristics . . . . . . . . . . . 61
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STM32F303xB STM32F303xC
Contents
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
WLCSP100 - 0.4 mm pitch wafer level chip scale package information 135
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 140
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
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List of tables
List of tables
STM32F303xB STM32F303xC
STM32F303xB/STM32F303xC family device features and peripheral counts . . . . . . . . . . 12
STM32F303xB/STM32F303xC peripheral interconnect matrix . . . . . . . . . . . . . . . . . . . . . 17
2
C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Capacitive sensing GPIOs available on STM32F303xB/STM32F303xC devices . . . . . . . 30
No. of capacitive sensing channels available on STM32F303xB/STM32F303xC devices . 30
STM32F303xB/STM32F303xC memory map, peripheral register boundary addresses . . 54
Typical and maximum current consumption from V
DD
supply at V
Typical and maximum current consumption from the V
DDA
DD
= 3.6V . . . . . . . . . . . 64
supply . . . . . . . . . . . . . . . . . . 65
consumption in Stop and Standby modes. . . . . . . . . . . . . . . . 66
consumption in Stop and Standby modes. . . . . . . . . . . . . . . 66
Typical and maximum current consumption from V
BAT
supply. . . . . . . . . . . . . . . . . . . . . . 67
Typical current consumption in Run mode, code with data processing running from Flash 68
Typical current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . 69
LSE oscillator characteristics (f
= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
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2 S characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
LQPF100 – 14 x 14 mm, low-profile quad flat package mechanical data. . . . . . . . . . . . . 126
LQFP64 – 10 x 10 mm, low-profile quad flat package mechanical data. . . . . . . . . . . . . . 129
LQFP48 – 7 x 7 mm, low-profile quad flat package mechanical data. . . . . . . . . . . . . . . . 132
WLCSP100 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . 137
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List of figures
List of figures
STM32F303xB STM32F303xC
current consumption (LSE and RTC ON/LSEDRV[1:0] = ’00’) . . . . . . . . . . . 67
2
C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
SPI timing diagram - slave mode and CPHA = 1
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
SPI timing diagram - master mode
2
2
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
S slave timing diagram (Philips protocol)
(1)
S master timing diagram (Philips protocol)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
LQFP100 – 14 x 14 mm, low-profile quad flat package recommended footprint . . . . . . . 127
LQFP100 – 14 x 14 mm, low-profile quad flat package top view example . . . . . . . . . . . . 128
LQFP64 – 10 x 10 mm, low-profile quad flat package recommended footprint . . . . . . . . 130
LQFP64 – 10 x 10 mm, low-profile quad flat package top view example . . . . . . . . . . . . . 131
LQFP48 - 7 x 7 mm, low-profile quad flat package recommended footprint. . . . . . . . . . . 133
LQFP48 - 7 x 7 mm, low-profile quad flat package top view example . . . . . . . . . . . . . . . 134
WLCSP100 – 100L, 4.166 x 4.628 mm 0.4 mm pitch wafer level chip scale
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STM32F303xB STM32F303xC List of figures
WLCSP100 – 100L, 4.166 x 4.628 mm 0.4 mm pitch wafer level chip scale
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Introduction
1 Introduction
STM32F303xB STM32F303xC
This datasheet provides the ordering information and mechanical device characteristics of the STM32F303xB/STM32F303xC microcontrollers.
This STM32F303xB/STM32F303xC datasheet should be read in conjunction with the
STM32F303x, STM32F358xC and STM32F328x4/6/8 reference manual (RM0316). The reference manual is available from the STMicroelectronics website www.st.com
.
For information on the Arm ®(a) Cortex ® -M4 core with FPU, refer to:
• Cortex ® -M4 with FPU Technical Reference Manual , available from the http://www.arm.com website.
• STM32F3xxx and STM32F4xxx Cortex ® available from our website www.st.com
.
-M4 programming manual (PM0214)
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
DS9118 Rev 14
STM32F303xB STM32F303xC
2 Description
Description
The STM32F303xB/STM32F303xC family is based on the high-performance Arm ® Cortex ® -
M4 32-bit RISC core with FPU operating at a frequency of up to 72 MHz, and embedding a floating point unit (FPU), a memory protection unit (MPU) and an embedded trace macrocell
(ETM). The family incorporates high-speed embedded memories (up to 256 Kbytes of Flash memory, up to 40 Kbytes of SRAM) and an extensive range of enhanced I/Os and peripherals connected to two APB buses.
The devices offer up to four fast 12-bit ADCs (5 Msps), seven comparators, four operational amplifiers, up to two DAC channels, a low-power RTC, up to five general-purpose 16-bit timers, one general-purpose 32-bit timer, and two timers dedicated to motor control. They also feature standard and advanced communication interfaces: up to two I 2 Cs, up to three
SPIs (two SPIs are with multiplexed full-duplex I2Ss), three USARTs, up to two UARTs, CAN and USB. To achieve audio class accuracy, the I2S peripherals can be clocked via an external PLL.
The STM32F303xB/STM32F303xC family operates in the -40 to +85 °C and -40 to +105 °C temperature ranges from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving mode allows the design of low-power applications.
The STM32F303xB/STM32F303xC family offers devices in four packages ranging from
48 pins to 100 pins.
The set of included peripherals changes with the device chosen.
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Description STM32F303xB STM32F303xC
Table 2. STM32F303xB/STM32F303xC family device features and peripheral counts
Peripheral STM32F303Cx STM32F303Rx STM32F303Vx
Flash (Kbytes)
SRAM (Kbytes) on data bus
CCM (Core Coupled Memory)
RAM (Kbytes)
Advanced control
Timers
General purpose
128
32
256
40
128
32
8
256
2 (16-bit)
40
128
32
256
40
Basic
PWM channels (all) (1)
PWM channels (except complementary)
SPI (I2S)
(2)
I
2
C
Communication interfaces
USART
UART
CAN
USB
Normal I/Os
(TC, TTa)
GPIOs
5-volt tolerant
I/Os (FT, FTf)
31
22
0
5 (16-bit)
1 (32-bit)
2 (16-bit)
3(2)
2
3
1
1
33
24
2
20
17
27
25
45 in LQFP100
37 in WLCSP100
42 in LQFP100
40 in WLCSP100
DMA channels
Capacitive sensing channels 17
12
18
4
24
12-bit ADCs
Number of channels 15 22
39 in LQFP100
32 in WLCSP100
12-bit DAC channels
Analog comparator
Operational amplifiers
CPU frequency
Operating voltage
2
7
4
72 MHz
2.0 to 3.6 V
Operating temperature
Packages
Ambient operating temperature: - 40 to 85 °C / - 40 to 105 °C
Junction temperature: - 40 to 125 °C
LQFP48 LQFP64
LQFP100
WLCSP100
1. This total number considers also the PWMs generated on the complementary output channels
2. The SPI interfaces can work in an exclusive way in either the SPI mode or the I
2
S audio mode.
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STM32F303xB STM32F303xC Description
TRADECLK
TRACED[0-3] as AF
JTRST
JTDI
JTCK/SWCLK
JTMS/SWDIO
JTDO
As AF
V
REF+
V
REF-
PA[15:0]
PB[15:0]
PC[15:0]
PD[15:0]
PE[15:0]
PF[7:0]
XX Groups of
4 channels as AF
XX AF
Figure 1. STM32F303xB/STM32F303xC block diagram
TPIU
SWJTAG
ETM
Trace/Trig
MPU/FPU
Cortex M4 CPU
F max
: 72 MHz
Ibus
Dbus
System
NVIC
GP DMA1
7 channels
GP DMA2
5 channels
Temp. sensor
12-bit ADC1
12-bit ADC2
IF
12-bit ADC3
12-bit ADC4
IF
GPIO PORT A
GPIO PORT B
GPIO PORT C
GPIO PORT D
GPIO PORT E
GPIO PORT F
Touch Sensing
Controller
EXT.IT
WKUP
CCM RAM
8KB
SRAM
40 KB
FLASH 256 KB
64 bits
@V
DDA
RC HS 8MHz
RC LS
PLL
POR
Reset
Int.
V
DD18
Power
Voltage reg.
3.3 V to 1.8V
@V
DDIO
Supply
Supervision
POR /PDR
PVD
@V
DDA
@V
DDIO
XTAL OSC
4 -32 MHz
Ind. WDG32K
Standby interface
Reset & clock control
AHBPCLK
APBP1CLK
APBP2CLK
HCLK
FCLK
USARTCLK
I2CCLK
ADC SAR
1/2/3/4 CLK
RTC
AWU
@VSW
XTAL 32kHz
Backup
Reg
(64Byte)
Backup interface
CRC
TIMER2
(32-bit/PWM)
TIMER 3
TIMER 4
AHB2
APB2
AHB2
APB1
WinWATCHDOG
USB SRAM 512B
SPI2/I2S
SPI3/I2S
USART2
USART3
UART4
UART5
I2C1
I2C2 bx CAN &
512B SRAM
USB 2.0 FS
TIMER 15
TIMER 16
TIMER 17
TIMER6
TIMER7
IF 12bit DAC1
@V
DDA
2 Channels,1 Comp
Channel, BRK as AF
1 Channel, 1 Comp
Channel, BRK as AF
1 Channel, 1 Comp
Channel, BRK as AF
4 Channels,
4 Comp channels,
ETR, BRK as AF
4 Channels,
4 Comp channels,
ETR, BRK as AF
MOSI, MISO,
SCK,NSS as AF
RX, TX, CTS, RTS,
SmartCard as AF
TIMER 1 / PWM
TIMER 8 / PWM
SPI1
USART1
SYSCFG CTL
@V
DDA
GP Comparator...
GP Comparator 1
OpAmp1
OpAmp2
OpAmp3
OpAmp4
@V
DDA
V
DDIO
= 2 to 3.6 V
V
SS
NRESET
V
DDA
V
SSA
OSC_IN
OSC_OUT
V
BAT
= 1.65V to 3.6V
OSC32_IN
OSC32_OUT
ANTI-TAMP
DAC1_CH1 as AF
DAC1_CH2 as AF
INxx / OUTxx
INxx / OUTxx
INxx / OUTxx
INxx / OUTxx
4 Channels, ETR as AF
4 Channels, ETR as AF
4 Channels, ETR as AF
MOSI/SD, MISO/ext_SD,
SCK/CK, NSS/WS, MCLK as AF
MOSI/SD, MISO/ext_SD,
SCK/CK, NSS/WS, MCLK as AF
RX, TX, CTS, RTS, as AF
RX, TX, CTS, RTS, as AF
RX, TX as AF
RX, TX as AF
SCL, SDA, SMBA as AF
SCL, SDA, SMBA as AF
CAN TX, CAN RX
USB_DP, USB_DM
MS18960V4
Xx Ins, 7 OUTs as AF
1. AF: alternate function on I/O pins.
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Functional overview STM32F303xB STM32F303xC
3.1 Arm
®
Cortex
SRAM
®
-M4 core with FPU with embedded Flash and
The Arm Cortex-M4 processor with FPU is the latest generation of Arm processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of
MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.
The Arm Cortex-M4 32-bit RISC processor with FPU features exceptional code-efficiency, delivering the high-performance expected from an Arm core in the memory size usually associated with 8- and 16-bit devices.
The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution.
Its single precision FPU speeds up software development by using metalanguage development tools, while avoiding saturation.
With its embedded Arm core, the STM32F303xB/STM32F303xC family is compatible with all Arm tools and software.
Figure 1 shows the general block diagram of the STM32F303xB/STM32F303xC family
devices.
3.2 Memory protection unit (MPU)
The memory protection unit (MPU) is used to separate the processing of tasks from the data protection. The MPU can manage up to 8 protection areas that can all be further divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory.
The memory protection unit is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-time operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
3.3 Embedded Flash memory
All STM32F303xB/STM32F303xC devices feature up to 256 Kbytes of embedded Flash memory available for storing programs and data. The Flash memory access time is adjusted to the CPU clock frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above).
DS9118 Rev 14
STM32F303xB STM32F303xC Functional overview
STM32F303xB/STM32F303xC devices feature up to 48 Kbytes of embedded SRAM with hardware parity check. The memory can be accessed in read/write at CPU clock speed with
0 wait states, allowing the CPU to achieve 90 Dhrystone Mips at 72 MHz (when running code from the CCM (Core Coupled Memory) RAM).
• 8 Kbytes of CCM RAM mapped on both instruction and data bus, used to execute critical routines or to access data (parity check on all of CCM RAM).
• 40 Kbytes of SRAM mapped on the data bus (parity check on first 16 Kbytes of SRAM).
At startup, Boot0 pin and Boot1 option bit are used to select one of three boot options:
• Boot from user Flash
• Boot from system memory
• Boot from embedded SRAM
The boot loader is located in the system memory. It is used to reprogram the Flash memory by using USART1 (PA9/PA10), USART2 (PD5/PD6) or USB (PA11/PA12) through DFU
(device firmware upgrade).
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.
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Functional overview STM32F303xB STM32F303xC
3.7.1
3.7.2
Power supply schemes
• V
SS
, V
DD
= 2.0 to 3.6 V : external power supply for I/Os and the internal regulator. It is provided externally through V
DD pins.
• V
SSA
, V
DDA
= 2.0 to 3.6 V: external analog power supply for ADC, DACs, comparators operational amplifiers, reset blocks, RCs and PLL. The minimum voltage to be applied to V
DDA
differs from one analog peripheral to another.
Table 3 provides the summary of
the V
DDA
ranges for analog peripherals. The V
DDA greater or equal to the V
DD
voltage level must be always
voltage level and must be provided first.
• V
BAT
= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when V
DD is not present.
Table 3. External analog supply values for analog peripherals
Analog peripheral Minimum V
DDA supply Maximum V
DDA supply
ADC / COMP 2.0 V 3.6 V
DAC / OPAMP 2.4 V 3.6V
Power supply supervision
The device has an integrated power-on reset (POR) and power-down reset (PDR) circuits.
They are always active, and ensure proper operation above a threshold of 2 V. The device remains in reset mode when the monitored supply voltage is below a specified threshold,
V POR/PDR , without the need for an external reset circuit.
• The POR monitors only the V
DD that V
DDA
supply voltage. During the startup phase it is required
should arrive first and be greater than or equal to V
DD
.
• The PDR monitors both the V
DD
and V
DDA
supply voltages, however the V
DDA
power supply supervisor can be disabled (by programming a dedicated Option bit) to reduce the power consumption if the application design ensures that V
DDA equal to V
DD
.
is higher than or
The device features an embedded programmable voltage detector (PVD) that monitors the
V
DD power supply and compares it to the V PVD threshold. An interrupt can be generated when V
DD drops below the V
PVD threshold and/or when V
DD is higher than the V
PVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.
The regulator has three operation modes: main (MR), low-power (LPR), and power-down.
• The MR mode is used in the nominal regulation mode (Run)
• The LPR mode is used in Stop mode.
• The power-down mode is used in Standby mode: the regulator output is in high impedance, and the kernel circuitry is powered down thus inducing zero consumption.
The voltage regulator is always enabled after reset. It is disabled in Standby mode.
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STM32F303xB STM32F303xC Functional overview
Note:
The STM32F303xB/STM32F303xC supports three low-power modes to achieve the best compromise between low-power consumption, short startup time and available wakeup sources:
• Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.
• Stop mode
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode.
The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output, the USB wakeup, the RTC alarm, COMPx, I2Cx or U(S)ARTx.
• Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin or an RTC alarm occurs.
The RTC, the IWDG and the corresponding clock sources are not stopped by entering Stop or Standby mode.
Several peripherals have direct connections between them. This allows autonomous communication between peripherals, saving CPU resources thus power supply consumption. In addition, these hardware connections allow fast and predictable latency.
Table 4. STM32F303xB/STM32F303xC peripheral interconnect matrix
Interconnect source
Interconnect destination
Interconnect action
Timers synchronization or chaining
TIMx
COMPx
ADCx
TIMx
ADCx
DAC1
DMA
Compx
TIMx
TIMx
Conversion triggers
Memory to memory transfer trigger
Comparator output blanking
Timer input: OCREF_CLR input, input capture
Timer triggered by analog watchdog
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Functional overview STM32F303xB STM32F303xC
Table 4. STM32F303xB/STM32F303xC peripheral interconnect matrix (continued)
Interconnect source
Interconnect destination
Interconnect action
GPIO
RTCCLK
HSE/32
MC0
CSS
CPU (hard fault)
COMPx
PVD
GPIO
TIM16
TIM1, TIM8,
TIM15, 16, 17
Clock source used as input channel for HSI and
LSI calibration
Timer break
GPIO
DAC1
TIMx
ADCx
DAC1
COMPx
External trigger, timer break
Conversion external trigger
Comparator inverting input
Note: For more details about the interconnect actions, please refer to the corresponding sections in the reference manual (RM0316).
3.9 Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example with failure of an indirectly used external oscillator).
Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the high speed APB domains is 72 MHz, while the maximum allowed frequency of the low speed
APB domain is 36 MHz.
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STM32F303xB STM32F303xC Functional overview
Figure 2. Clock tree
HSI
SYSCLK
FLITFCLK to Flash programming interface to I2Cx (x = 1,2)
SYSCLK
Ext. clock
I2SSRC to I2Sx (x = 2,3)
I2S_CKIN
OSC_OUT
OSC_IN
OSC32_IN
OSC32_OUT
8 MHz
HSI RC
HSI
/2
PLLSRC
PLLMUL
PLL x2,x3,..
x16
HSI
PLLCLK
HSE
SW prescaler
/1,2,..512
SYSCLK
CSS
/2,/3,...
/16
HCLK
/8
APB1 prescaler
/1,2,4,8,16
4-32 MHz
HSE OSC
USB prescaler
/1,1.5
PCLK1
If (APB1 prescaler
=1) x1 else x2
PCLK1
SYSCLK
HSI
LSE
USBCLK to USB interface to AHB bus, core, memory and DMA to cortex System timer
FHCLK Cortex free running clock to APB1 peripherals to TIM 2,3,4,6,7 to U(S)ARTx (x = 2..5)
APB2 prescaler
/1,2,4,8,16
PCLK2 to APB2 peripherals
/32
LSE OSC
32.768kHz
RTCCLK
LSE
RTCSEL[1:0] to RTC
LSI RC
40kHz
LSI
IWDGCLK to IWDG
If (APB2 prescaler
=1) x1 else x2
PCLK2
SYSCLK
HSI
LSE to TIM 15,16,17 to USART1 x2 TIM1/8
MCO
Main clock output
MCO
/2 PLLCLK
HSI
LSI
HSE
SYSCLK
ADC
Prescaler
/1,2,4
ADC
Prescaler
/1,2,4,6,8,10,12,16,
32,64,128,256 to ADCxy
(xy = 12, 34)
MS19989V5
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Functional overview STM32F303xB STM32F303xC
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current capable except for analog inputs.
The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers.
Fast I/O handling allows I/O toggling up to 36 MHz.
The flexible general-purpose DMA is able to manage memory-to-memory, peripheral-tomemory and memory-to-peripheral transfers. The DMA controller supports circular buffer management, avoiding the generation of interrupts when the controller reaches the end of the buffer.
Each of the 12 DMA channels is connected to dedicated hardware DMA requests, with software trigger support for each channel. Configuration is done by software and transfer sizes between source and destination are independent.
The DMA can be used with the main peripherals: SPI, I 2
DAC and ADC.
C, USART, general-purpose timers,
3.12.1 Nested vectored interrupt controller (NVIC)
The STM32F303xB/STM32F303xC devices embed a nested vectored interrupt controller
(NVIC) able to handle up to 66 maskable interrupt channels and 16 priority levels.
The NVIC benefits are the following:
• Closely coupled NVIC gives low latency interrupt processing
• Interrupt entry vector table address passed directly to the core
• Closely coupled NVIC core interface
• Allows early processing of interrupts
• Processing of late arriving higher priority interrupts
• Support for tail chaining
• Processor state automatically saved
• Interrupt entry restored on interrupt exit with no instruction overhead
The NVIC hardware block provides flexible interrupt management features with minimal interrupt latency.
DS9118 Rev 14
STM32F303xB STM32F303xC Functional overview four fast analog-to-digital converters 5 MSPS, with selectable resolution between 12 and 6 bit, are embedded in the STM32F303xB/STM32F303xC family devices. The ADCs have up to 39 external channels. Some of the external channels are shared between ADC1&2 and between ADC3&4. Channels can be configured to be either single-ended input or differential input. The ADCs can perform conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs.
The ADCs have also internal channels: Temperature sensor connected to ADC1 channel
16, V
BAT/2
connected to ADC1 channel 17, Voltage reference V
REFINT
connected to the 4
ADCs channel 18, VOPAMP1 connected to ADC1 channel 15, VOPAMP2 connected to
ADC2 channel 17, VREFOPAMP3 connected to ADC3 channel 17 and VREFOPAMP4 connected to ADC4 channel 17.
Additional logic functions embedded in the ADC interface allow:
• Simultaneous sample and hold
• Interleaved sample and hold
• Single-shunt phase current reading techniques.
The ADC can be served by the DMA controller. 3 analog watchdogs per ADC are available.
An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.
The events generated by the general-purpose timers and the advanced-control timers
(TIM1 and TIM8) can be internally connected to the ADC start trigger and injection trigger, respectively, to allow the application to synchronize A/D conversion and timers.
The temperature sensor (TS) generates a voltage V
SENSE temperature.
that varies linearly with
The temperature sensor is internally connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode.
3.13.2 Internal voltage reference (V
REFINT
)
The internal voltage reference (V
REFINT
ADC and Comparators. V
REFINT
is internally connected to the ADCx_IN18, x=1...4 input channel. The precise voltage of V
REFINT
) provides a stable (bandgap) voltage output for the
is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode.
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Functional overview STM32F303xB STM32F303xC
3.13.3 V
BAT
battery voltage monitoring
This embedded hardware feature allows the application to measure the V
BAT
battery voltage using the internal ADC channel ADC1_IN17. As the V and thus outside the ADC input range, the V
BAT
BAT
voltage may be higher than V
pin is internally connected to a bridge divider by 2. As a consequence, the converted digital value is half the V
BAT
voltage.
DDA
,
Every OPAMP reference voltage can be measured using a corresponding ADC internal channel: VREFOPAMP1 connected to ADC1 channel 15, VREFOPAMP2 connected to
ADC2 channel 17, VREFOPAMP3 connected to ADC3 channel 17, VREFOPAMP4 connected to ADC4 channel 17.
Two 12-bit buffered DAC channels can be used to convert digital signals into analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration.
This digital interface supports the following features:
• Two DAC output channels
• 8-bit or 10-bit monotonic output
• Left or right data alignment in 12-bit mode
• Synchronized update capability
• Noise-wave generation
• Triangular-wave generation
• Dual DAC channel independent or simultaneous conversions
• DMA capability (for each channel)
• External triggers for conversion
The STM32F303xB/STM32F303xC embeds four operational amplifiers with external or internal follower routing and PGA capability (or even amplifier and filter capability with external components). When an operational amplifier is selected, an external ADC channel is used to enable output measurement.
The operational amplifier features:
• 8.2 MHz bandwidth
• 0.5 mA output capability
• Rail-to-rail input/output
• In PGA mode, the gain can be programmed to be 2, 4, 8 or 16.
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STM32F303xB STM32F303xC Functional overview
3.16 Fast comparators (COMP)
The STM32F303xB/STM32F303xC devices embed seven fast rail-to-rail comparators with programmable reference voltage (internal or external), hysteresis and speed (low speed for low-power) and with selectable output polarity.
The reference voltage can be one of the following:
• External I/O
• DAC output pin
•
for the value and precision of the internal reference voltage.
All comparators can wake up from STOP mode, generate interrupts and breaks for the timers and can be also combined per pair into a window comparator
3.17 Timers and watchdogs
The STM32F303xB/STM32F303xC includes two advanced control timers, up to six generalpurpose timers, two basic timers, two watchdog timers and a SysTick timer. The table below compares the features of the advanced control, general purpose and basic timers.
Timer type
Advanced
Generalpurpose
Generalpurpose
Generalpurpose
Generalpurpose
Basic
Timer
TIM1,
TIM8
TIM2
TIM3, TIM4
TIM15
TIM16, TIM17
TIM6,
TIM7
Table 5. Timer feature comparison
Counter resolution
Counter type
Prescaler factor
DMA request generation
16-bit
32-bit
16-bit
16-bit
16-bit
16-bit
Up, Down,
Up/Down
Up, Down,
Up/Down
Up, Down,
Up/Down
Up
Up
Up
Any integer between 1 and 65536
Any integer between 1 and 65536
Any integer between 1 and 65536
Any integer between 1 and 65536
Any integer between 1 and 65536
Any integer between 1 and 65536
Yes
Yes
Yes
Yes
Yes
Yes
Capture/ compare
Channels
Complementary outputs
4
4
4
2
1
0
Yes
No
No
1
1
No
Note: TIM1/8 can have PLL as clock source, and therefore can be clocked at 144 MHz.
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Functional overview STM32F303xB STM32F303xC
The advanced-control timers (TIM1 and TIM8) can each be seen as a three-phase PWM multiplexed on six channels. They have complementary PWM outputs with programmable inserted dead-times. They can also be seen as complete general-purpose timers. The four independent channels can be used for:
• Input capture
• Output compare
• PWM generation (edge or center-aligned modes) with full modulation capability (0-
100%)
• One-pulse mode output
In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled to turn off any power switches driven by these outputs.
Many features are shared with those of the general-purpose TIM timers (described in
using the same architecture, so the advanced-control timers can work
together with the TIM timers via the Timer Link feature for synchronization or event chaining.
There are up to six synchronizable general-purpose timers embedded in the
STM32F303xB/STM32F303xC (see Table 5
for differences). Each general-purpose timer can be used to generate PWM outputs, or act as a simple time base.
• TIM2, 3, and TIM4
These are full-featured general-purpose timers:
– TIM2 has a 32-bit auto-reload up/downcounter and 32-bit prescaler
– TIM3 and 4 have 16-bit auto-reload up/downcounters and 16-bit prescalers.
These timers all feature 4 independent channels for input capture/output compare,
PWM or one-pulse mode output. They can work together, or with the other generalpurpose timers via the Timer Link feature for synchronization or event chaining.
The counters can be frozen in debug mode.
All have independent DMA request generation and support quadrature encoders.
• TIM15, 16 and 17
These three timers general-purpose timers with mid-range features:
They have 16-bit auto-reload upcounters and 16-bit prescalers.
– TIM15 has 2 channels and 1 complementary channel
– TIM16 and TIM17 have 1 channel and 1 complementary channel
All channels can be used for input capture/output compare, PWM or one-pulse mode output.
The timers can work together via the Timer Link feature for synchronization or event chaining. The timers have independent DMA request generation.
The counters can be frozen in debug mode.
These timers are mainly used for DAC trigger generation. They can also be used as a generic 16-bit time base.
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STM32F303xB STM32F303xC Functional overview
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode.
The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.
This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features:
• A 24-bit down counter
• Autoreload capability
• Maskable system interrupt generation when the counter reaches 0.
• Programmable clock source
The RTC and the 16 backup registers are supplied through a switch that takes power from either the V
DD
supply when present or the V
BAT
pin. The backup registers are sixteen 32-bit registers used to store 64 bytes of user application data when V
DD
power is not present.
They are not reset by a system or power reset, or when the device wakes up from Standby mode.
The RTC is an independent BCD timer/counter.It supports the following features:
• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format.
• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision.
• Automatic correction for 28, 29 (leap year), 30 and 31 days of the month.
• Two programmable alarms with wake up from Stop and Standby mode capability.
• On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master clock.
• Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal inaccuracy.
• Three anti-tamper detection pins with programmable filter. The MCU can be woken up from Stopand Standby modes on tamper event detection.
• Timestamp feature which can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be woken up from Stop and Standby modes on timestamp event detection.
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Functional overview STM32F303xB STM32F303xC
• 17-bit Auto-reload counter for periodic interrupt with wakeup from STOP/STANDBY capability.
The RTC clock sources can be:
• A 32.768 kHz external crystal
• A resonator or oscillator
• The internal low-power RC oscillator (typical frequency of 40 kHz)
• The high-speed external clock divided by 32.
circuit interface (I
2
C)
Up to two I 2 C bus interfaces can operate in multimaster and slave modes. They can support standard (up to 100 KHz), fast (up to 400 KHz) and fast mode + (up to 1 MHz) modes.
Both support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses
(2 addresses, 1 with configurable mask). They also include programmable analog and digital noise filters.
Pulse width of suppressed spikes
Benefits
Drawbacks
Table 6. Comparison of I2C analog and digital filters
Analog filter Digital filter
50 ns
Available in Stop mode
Variations depending on temperature, voltage, process
Programmable length from 1 to 15
I2C peripheral clocks
1. Extra filtering capability vs. standard requirements.
2. Stable length
Wakeup from Stop on address match is not available when digital filter is enabled.
In addition, they provide hardware support for SMBUS 2.0 and PMBUS 1.1: ARP capability,
Host notify protocol, hardware CRC (PEC) generation/verification, timeouts verifications and
ALERT protocol management. They also have a clock domain independent from the CPU clock, allowing the I2Cx (x=1,2) to wake up the MCU from Stop mode on address match.
The I2C interfaces can be served by the DMA controller.
for the features available in I2C1 and I2C2.
Table 7. STM32F303xB/STM32F303xC I 2 C implementation
I2C features
(1)
I2C1
7-bit addressing mode
10-bit addressing mode
Standard mode (up to 100 kbit/s)
Fast mode (up to 400 kbit/s)
Fast Mode Plus with 20mA output drive I/Os (up to 1 Mbit/s)
Independent clock
X
X
X
X
X
X
I2C2
X
X
X
X
X
X
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Table 7. STM32F303xB/STM32F303xC I 2 C implementation (continued)
I2C features (1) I2C1 I2C2
SMBus
Wakeup from STOP
1. X = supported.
X
X
X
X
(USART)
The STM32F303xB/STM32F303xC devices have three embedded universal synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3).
The USART interfaces are able to communicate at speeds of up to 9 Mbits/s.
They provide hardware management of the CTS and RTS signals, they support IrDA SIR
ENDEC, the multiprocessor communication mode, the single-wire half-duplex communication mode and have LIN Master/Slave capability. The USART interfaces can be served by the DMA controller.
The STM32F303xB/STM32F303xC devices have 2 embedded universal asynchronous receiver transmitters (UART4, and UART5). The UART interfaces support IrDA SIR
ENDEC, multiprocessor communication mode and single-wire half-duplex communication mode. The UART4 interface can be served by the DMA controller.
for the features available in all U(S)ART interfaces.
Table 8. USART features
USART modes/features
(1)
Hardware flow control for modem
Continuous communication using DMA
Multiprocessor communication
Synchronous mode
Smartcard mode
Single-wire half-duplex communication
IrDA SIR ENDEC block
LIN mode
Dual clock domain and wakeup from Stop mode
Receiver timeout interrupt
Modbus communication
Auto baud rate detection
Driver Enable
1. X = supported.
USART1 USART2 USART3
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
UART4
X
X
X
X
X
-
-
-
-
X
-
X
X
UART5
X
X
X
X
X
-
-
-
-
X
-
-
X
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Functional overview STM32F303xB STM32F303xC
3.22 Serial peripheral interface (SPI)/Inter-integrated sound interfaces (I2S)
Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in full-duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits.
Two standard I2S interfaces (multiplexed with SPI2 and SPI3) supporting four different audio standards can operate as master or slave at half-duplex and full duplex communication modes. They can be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data resolution and synchronized by a specific signal. Audio sampling frequency from 8 kHz up to 192 kHz can be set by 8-bit programmable linear prescaler. When operating in master mode it can output a clock for an external audio component at 256 times the sampling frequency.
for the features available in SPI1, SPI2 and SPI3.
Table 9. STM32F303xB/STM32F303xC SPI/I2S implementation
SPI features
(1)
SPI1 SPI2
Hardware CRC calculation
Rx/Tx FIFO
NSS pulse mode
I2S mode
TI mode
1. X = supported.
X
X
X
-
X
X
X
X
X
X
SPI3
X
X
X
X
X
3.23 Controller area network (CAN)
The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and
14 scalable filter banks.
3.24 Universal serial bus (USB)
The STM32F303xB/STM32F303xC devices embed an USB device peripheral compatible with the USB full-speed 12 Mbs. The USB interface implements a full-speed (12 Mbit/s) function interface. It has software-configurable endpoint setting and suspend/resume support. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator). The USB has a dedicated 512-bytes SRAM memory for data transmission and reception.
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STM32F303xB STM32F303xC Functional overview
The STM32F303xB/STM32F303xC devices provide an infrared transmitter solution. The solution is based on internal connections between TIM16 and TIM17 as shown in the figure below.
TIM17 is used to provide the carrier frequency and TIM16 provides the main signal to be sent. The infrared output signal is available on PB9 or PA13.
To generate the infrared remote control signals, TIM16 channel 1 and TIM17 channel 1 must be properly configured to generate correct waveforms. All standard IR pulse modulation modes can be obtained by programming the two timers output compare channels.
Figure 3. Infrared transmitter
TIMER 16
(for envelop)
OC
PB9/PA13
OC
TIMER 17
(for carrier)
MSv30365V1
3.26 Touch sensing controller (TSC)
The STM32F303xB/STM32F303xC devices provide a simple solution for adding capacitive sensing functionality to any application. These devices offer up to 24 capacitive sensing channels distributed over 8 analog I/O groups.
Capacitive sensing technology is able to detect the presence of a finger near a sensor which is protected from direct touch by a dielectric (glass, plastic, ...). The capacitive variation introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. It consists of charging the sensor capacitance and then transferring a part of the accumulated charges into a sampling capacitor until the voltage across this capacitor has reached a specific threshold. To limit the CPU bandwidth usage this acquisition is directly managed by the hardware touch sensing controller and only requires few external components to operate.
The touch sensing controller is fully supported by the STMTouch touch sensing firmware library which is free to use and allows touch sensing functionality to be implemented reliably in the end application.
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Table 10. Capacitive sensing GPIOs available on STM32F303xB/STM32F303xC devices
Group
Capacitive sensing signal name
Pin name
Group
Capacitive sensing signal name
Pin name
1
2
3
4
TSC_G1_IO1
TSC_G1_IO2
TSC_G1_IO3
TSC_G1_IO4
TSC_G2_IO1
TSC_G2_IO2
TSC_G2_IO3
TSC_G2_IO4
TSC_G3_IO1
TSC_G3_IO2
TSC_G3_IO3
TSC_G3_IO4
TSC_G4_IO1
TSC_G4_IO2
TSC_G4_IO3
TSC_G4_IO4
PA7
PC5
PB0
PB1
PB2
PA9
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA10
PA13
PA14
5
6
7
8
TSC_G5_IO1
TSC_G5_IO2
TSC_G5_IO3
TSC_G5_IO4
TSC_G6_IO1
TSC_G6_IO2
TSC_G6_IO3
TSC_G6_IO4
TSC_G7_IO1
TSC_G7_IO2
TSC_G7_IO3
TSC_G7_IO4
TSC_G8_IO1
TSC_G8_IO2
TSC_G8_IO3
TSC_G8_IO4
PB14
PE2
PE3
PE4
PE5
PD12
PB3
PB4
PB6
PB7
PB11
PB12
PB13
PD13
PD14
PD15
Table 11. No. of capacitive sensing channels available on
STM32F303xB/STM32F303xC devices
Number of capacitive sensing channels
Analog I/O group
STM32F303Vx STM32F303Rx STM32F303Cx
G1
G2
G3
G4
G5
G6
G7
G8
Number of capacitive sensing channels
3
3
3
3
3
3
3
3
24
3
3
3
0
0
3
3
3
18
3
3
3
0
0
3
3
2
17
DS9118 Rev 14
STM32F303xB STM32F303xC Functional overview
The Arm SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.
The Arm embedded trace macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the
STM32F303xB/STM32F303xC through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using a high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. TPA hardware is commercially available from common development tool vendors. It operates with third party debugger software tools.
DS9118 Rev 14
55
Pinouts and pin description
4 Pinouts and pin description
STM32F303xB STM32F303xC
Figure 4. STM32F303xB/STM32F303xC LQFP48 pinout
VBAT
PC13
PC14/OSC32_IN
PC15/OSC32_OUT
PF0/OSC_IN
PF1/OSC_OUT
NRST
VSSA/VREF-
VDDA
PA0
PA1
PA2
2
3
1
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
4 33
5 32
6
LQFP48
31
7 30
8 29
9 28
10 27
11
12
26
25
13 14 15 16 17 18 19 20 21 22 23 24
VDD
VSS
PA13
PA12
PA11
PA10
PA9
PA8
PB15
PB14
PB13
PB12
MSv40448V1
DS9118 Rev 14
STM32F303xB STM32F303xC Pinouts and pin description
Figure 5. STM32F303xB/STM32F303xC LQFP64 pinout
VBAT
PC13
PC14/OSC32_IN
PC15/OSC32_OUT
PF0/OSC_IN
PF1/OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA/VREF-
VDDA
PA0
PA1
PA2
4
5
1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
2 47
3 46
6
45
44
43
7 42
8 41
9
LQFP64
40
10 39
11 38
12 37
13 36
14 35
15 34
16
17 18 19 20 21 22 23 24 25 26 27 28
33
29 30 31 32
PA8
PC9
PC8
PC7
PC6
PB15
PB14
PB13
PB12
VDD
VSS
PA13
PA12
PA11
PA10
PA9
MS40449V2
DS9118 Rev 14
55
Pinouts and pin description STM32F303xB STM32F303xC
Figure 6. STM32F303xB/STM32F303xC LQFP100 pinout
PE2
PE3
PE4
PE5
PE6
VBAT
PC13
PC14/OSC32_IN
PC15/OSC32_OUT
PF9
PF10
PF0/OSC_IN
PF1/OSC_OUT
NRST
PC0
PC1
PC2
PC3
PF2
VSSA/VREF-
VREF+
VDDA
PA0
PA1
PA2
19
20
21
22
23
24
25
13
14
15
16
17
18
7
8
9
10
11
12
3
4
1
2
5
6
LQFP100
VDD
VSS
PF6
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12
57
56
55
54
53
52
51
63
62
61
60
59
58
69
68
67
66
65
64
75
74
73
72
71
70
MS40450V1
DS9118 Rev 14
STM32F303xB STM32F303xC Pinouts and pin description
Figure 7. STM32F303xB/STM32F303xC WLCSP100 pinout
A
D
E
F
B
C
G
H
J
K
1
VSS
VSS
PF6
PA12
PA10
PC8
PD15
PD12
VSS
VSS
2
VSS
3
PC12
PA15
PA14
VDD
PD0
PD1
PC11
PA11
PC7
PA13
PC9
PD14 PD13
PD11 PD10
PB14
VSS
PB13
PB11
PD7
PC10
PC6
PD9
PB15
PB12
PB10
4
PD2
PD3
PD4
5
PB3
6
PB5
PB4 PB6
PB9
PB7
PB8 PE2
PE8
PA9
PA8 PC5
PE12 PC4
PE11 PA6
VDD
PB2
PB0
PB1
7 8
BOOT0 PE1
VDD
9
VDD
VSS
10
VDD
PE0
VSS
PE3
PE6
PA2
PA3
VDD PE5 VDD
PE4 PC13
PC14
OSC32IN
VBAT
PC15
OSC32OUT
PF2
NRST
PF9
PF10
PE7
PF1
OSCOUT
PF0
OSCIN
PC2 PC1 PC0
PC3 PA5
PA4
VSSA
VREF+
PA0
PA1 VDDA
PA7 VSS
MSv40453V1
DS9118 Rev 14
55
Pinouts and pin description STM32F303xB STM32F303xC
Name
Pin name
Pin type
I/O structure
Notes
Table 12. Legend/abbreviations used in the pinout table
Abbreviation Definition
Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name
S
I
Supply pin
Input only pin
I/O
FT
FTf
TTa
Input / output pin
5 V tolerant I/O
5 V tolerant I/O, FM+ capable
3.3 V tolerant I/O directly connected to ADC
TC
B
Standard 3.3V I/O
Dedicated BOOT0 pin
RST Bidirectional reset pin with embedded weak pull-up resistor
Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset
Alternate functions
Pin functions
Additional functions
Functions selected through GPIOx_AFR registers
Functions directly selected/enabled through peripheral registers
Pin number
Table 13. STM32F303xB/STM32F303xC pin definitions
Pin functions
Pin name
(function after reset)
Alternate functions Additional functions
3
4
5
6
1
2
D6
D7
C8
B9
E7
D8
-
-
-
1
-
-
-
-
-
1
-
PE2
PE3
PE4
PE5
PE6
V
BAT
I/O FT
I/O FT
I/O FT
I/O FT
(1)
(1)
(1)
(1)
I/O FT
(1)
S -
TRACECK, TIM3_CH1,
TSC_G7_IO1, EVENTOUT
TRACED0, TIM3_CH2,
TSC_G7_IO2, EVENTOUT
TRACED1, TIM3_CH3,
TSC_G7_IO3, EVENTOUT
TRACED2, TIM3_CH4,
TSC_G7_IO4, EVENTOUT
-
-
-
-
TRACED3, EVENTOUT WKUP3, RTC_TAMP3
Backup power supply
DS9118 Rev 14
STM32F303xB STM32F303xC Pinouts and pin description
Pin number
Table 13. STM32F303xB/STM32F303xC pin definitions (continued)
Pin functions
Pin name
(function after reset)
Alternate functions Additional functions
C9
C10
D9
D10
E10
F10
F9
E9
-
7
8
9
10
11
12
13
14
J8 21
J10 22
-
2
3
4
-
-
5
6
7
G10 15 8
G9 16 9
G8 17 10
H10 18 11
E8 19 -
H8 20 12
-
-
13
2
3
4
-
-
5
6
7
8
-
-
-
-
-
-
-
9
H9 23 14 10
PC13
(2)
I/O TC - TIM1_CH1N
WKUP2, RTC_TAMP1,
RTC_TS, RTC_OUT
OSC32_IN
(PC14)
OSC32_
OUT
(PC15)
I/O TC
I/O TC -
-
-
OSC32_IN
OSC32_OUT
PF9
PF10
I/O FT
I/O FT
(1)
(1)
TIM15_CH1, SPI2_SCK,
EVENTOUT
TIM15_CH2, SPI2_SCK,
EVENTOUT
-
-
PF0-
OSC_IN
(PF0)
PF1-
OSC_OUT
(PF1)
I/O FTf - I2C2_SCL
NRST
I/O FTf
I/O
RS
T
I/O TTa
- TIM1_CH3N, I2C2_SDA,
(1)
OSC_IN
OSC_OUT
Device reset input / internal reset output (active low)
PC0
PC1
PC2
PC3
PF2
I/O TTa
I/O TTa
I/O TTa
I/O TTa
(1)
(1)
(1)
(1)
EVENTOUT
EVENTOUT
COMP7_OUT, EVENTOUT
TIM1_BKIN2, EVENTOUT
EVENTOUT
ADC12_IN6, COMP7_INM
ADC12_IN7, COMP7_INP
ADC12_IN8
ADC12_IN9
ADC12_IN10
VSSA/
VREF-
VREF+
(3)
VDDA
VDDA/
VREF+
S
S
S
S
-
-
-
-
-
-
-
Analog ground/Negative reference voltage
Positive reference voltage
Analog power supply
Analog power supply/Positive reference voltage
PA0 I/O TTa
(4)
USART2_CTS,
TIM2_CH1_ETR,TIM8_BKIN,
TIM8_ETR,TSC_G1_IO1,
COMP1_OUT, EVENTOUT
ADC1_IN1, COMP1_INM,
RTC_ TAMP2, WKUP1,
COMP7_INP
DS9118 Rev 14
55
Pinouts and pin description STM32F303xB STM32F303xC
Pin number
Table 13. STM32F303xB/STM32F303xC pin definitions (continued)
Pin functions
Pin name
(function after reset)
Alternate functions Additional functions
J9 24 15 11
F7 25 16 12
G7 26 17
27 18
K9,
K10
-
K8 28 19
13
-
-
-
J7 29 20 14
H7 30 21 15
H6 31 22 16
K7 32 23 17
G6 33 24 -
PA1
PA2
PA3
PF4
VSS
VDD
PA4
PA5
PA6
PA7
PC4
I/O TTa
I/O TTa
I/O TTa
(4)
(5)
USART2_RTS_DE,
TIM2_CH2, TSC_G1_IO2,
TIM15_CH1N, RTC_REFIN,
EVENTOUT
USART2_TX, TIM2_CH3,
TIM15_CH1, TSC_G1_IO3,
COMP2_OUT, EVENTOUT
USART2_RX, TIM2_CH4,
TIM15_CH2, TSC_G1_IO4,
EVENTOUT
I/O TTa
(1)
COMP1_OUT, EVENTOUT
ADC1_IN2, COMP1_INP,
OPAMP1_VINP,
OPAMP3_VINP
ADC1_IN3, COMP2_INM,
OPAMP1_VOUT
ADC1_IN4, OPAMP1_VINP,
COMP2_INP,
OPAMP1_VINM
ADC1_IN5
S Digital ground
S -
I/O TTa
I/O TTa
I/O TTa
I/O TTa
I/O TTa
-
(5)
(4)
(5)
(4)
(5)
SPI1_NSS,
Digital power supply
SPI3_NSS,I2S3_WS,
USART2_CK, TSC_G2_IO1,
TIM3_CH2, EVENTOUT
SPI1_SCK, TIM2_CH1_ETR,
TSC_G2_IO2, EVENTOUT
ADC2_IN1, DAC1_OUT1,
OPAMP4_VINP,
COMP1_INM, COMP2_INM,
COMP3_INM, COMP4_INM,
COMP5_INM, COMP6_INM,
COMP7_INM
ADC2_IN2, DAC1_OUT2
OPAMP1_VINP,
OPAMP2_VINM,
OPAMP3_VINP
COMP1_INM, COMP2_INM,
COMP3_INM, COMP4_INM,
COMP5_INM, COMP6_INM,
COMP7_INM
SPI1_MISO, TIM3_CH1,
TIM8_BKIN, TIM1_BKIN,
TIM16_CH1, COMP1_OUT,
TSC_G2_IO3, EVENTOUT
SPI1_MOSI, TIM3_CH2,
TIM17_CH1, TIM1_CH1N,
TIM8_CH1N, TSC_G2_IO4,
COMP2_OUT, EVENTOUT
ADC2_IN3, OPAMP2_VOUT
ADC2_IN4, COMP2_INP,
OPAMP2_VINP,
OPAMP1_VINP
(1)
USART1_TX, EVENTOUT ADC2_IN5
DS9118 Rev 14
STM32F303xB STM32F303xC Pinouts and pin description
Pin number
Table 13. STM32F303xB/STM32F303xC pin definitions (continued)
Pin functions
Pin name
(function after reset)
Alternate functions Additional functions
F6
J6
K6
K4
34
35
36
47
25
26
27
29
-
18
19
K5 37 28 20
F8 38
E6 39
40
-
-
-
-
-
41
H5 42
G5 43
44
45
-
-
-
-
-
-
-
-
-
46 -
21
K3 48 30 22
K1,
J1,
K2
49 31 23
J5 50 32 24
J4 51 33 25
PC5
PB0
PB1
PE10
PE11
PE12
PE13
PE14
PB2
PE7
PE8
PE9
PE15
PB10
PB11
VSS
VDD
PB12
I/O TTa
I/O TTa
(1)
I/O TTa -
(4)
(5)
USART1_RX, TSC_G3_IO1,
EVENTOUT
TIM3_CH3, TIM1_CH2N,
TIM8_CH2N,TSC_G3_IO2,
EVENTOUT
TIM3_CH4, TIM1_CH3N,
TIM8_CH3N, COMP4_OUT,
TSC_G3_IO3, EVENTOUT
ADC2_IN11, OPAMP2_VINM,
OPAMP1_VINM
ADC3_IN12, COMP4_INP,
OPAMP3_VINP,
OPAMP2_VINP
ADC3_IN1, OPAMP3_VOUT-
I/O TTa - TSC_G3_IO4, EVENTOUT
ADC2_IN12, COMP4_INM,
OPAMP3_VINM
ADC3_IN13, COMP4_INP
COMP4_INM, ADC34_IN6
I/O TTa
I/O TTa
I/O TTa
(1)
(1)
(4)
(1)
(1)
I/O TTa
I/O TTa
I/O TTa
I/O TTa
I/O TTa
(1)
(1)
(1)
(4)
(1)
I/O TTa
(1)
TIM1_ETR, EVENTOUT
TIM1_CH1N, EVENTOUT
TIM1_CH1, EVENTOUT
TIM1_CH2N, EVENTOUT
TIM1_CH2, EVENTOUT
TIM1_CH3N, EVENTOUT
TIM1_CH3, EVENTOUT
TIM1_CH4, TIM1_BKIN2,
EVENTOUT
USART3_RX, TIM1_BKIN,
EVENTOUT
ADC3_IN2
ADC3_IN14
ADC3_IN15
ADC3_IN16
ADC3_IN3
ADC4_IN1
ADC4_IN2
I/O TTa -
USART3_TX, TIM2_CH3,
TSC_SYNC, EVENTOUT
COMP5_INM,
OPAMP4_VINM,
OPAMP3_VINM
I/O TTa -
USART3_RX, TIM2_CH4,
TSC_G6_IO1, EVENTOUT
COMP6_INP, OPAMP4_VINP
S Digital ground
S -
I/O TTa
-
(4)
(5)
Digital power supply
SPI2_NSS,I2S2_WS,I2C2_S
MBA, USART3_CK,
TIM1_BKIN, TSC_G6_IO2,
EVENTOUT
ADC4_IN3, COMP3_INM,
OPAMP4_VOUT
DS9118 Rev 14
55
Pinouts and pin description STM32F303xB STM32F303xC
Pin number
Table 13. STM32F303xB/STM32F303xC pin definitions (continued)
Pin functions
Pin name
(function after reset)
Alternate functions Additional functions
J3 52 34 26
J2 53 35 27
H4 54 36 28
55
G4 56
H3 57
H2
H1
G3
G2
G1
F4 63 37 -
F2
F1
F3
58
59
60
61
62
64
65
66
-
-
-
-
-
-
-
-
38
39
40
-
-
-
-
-
-
-
-
-
-
-
PB13
PB14
PB15
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PC6
PC7
PC8
PC9
I/O TTa
I/O TTa
I/O TTa
I/O TTa
I/O TTa
I/O TTa
I/O TTa
I/O TTa
I/O TTa
I/O TTa
I/O TTa
I/O FT
I/O FT
I/O FT
I/O FT
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
SPI2_SCK,I2S2_CK,USART3
_CTS, TIM1_CH1N,
TSC_G6_IO3, EVENTOUT
SPI2_MISO,I2S2ext_SD,
USART3_RTS_DE,
TIM1_CH2N, TIM15_CH1,
TSC_G6_IO4, EVENTOUT
SPI2_MOSI, I2S2_SD,
TIM1_CH3N, RTC_REFIN,
TIM15_CH1N, TIM15_CH2,
EVENTOUT
USART3_TX, EVENTOUT
USART3_RX, EVENTOUT
USART3_CK, EVENTOUT
USART3_CTS, EVENTOUT
ADC3_IN5, COMP5_INP,
OPAMP4_VINP,
OPAMP3_VINP
COMP3_INP, ADC4_IN4,
OPAMP2_VINP
ADC4_IN5, COMP6_INM
ADC4_IN12, OPAMP4_VINM
ADC4_IN13
ADC34_IN7, COMP6_INM
ADC34_IN8, COMP6_INP,
OPAMP4_VINP
USART3_RTS_DE,
TIM4_CH1, TSC_G8_IO1,
EVENTOUT
TIM4_CH2, TSC_G8_IO2,
EVENTOUT
TIM4_CH3, TSC_G8_IO3,
EVENTOUT
SPI2_NSS, TIM4_CH4,
TSC_G8_IO4, EVENTOUT
I2S2_MCK, COMP6_OUT,
TIM8_CH1, TIM3_CH1,
EVENTOUT
I2S3_MCK, TIM8_CH2,
TIM3_CH2, COMP5_OUT,
EVENTOUT
TIM8_CH3, TIM3_CH3,
COMP3_OUT, EVENTOUT
TIM8_CH4,
TIM8_BKIN2,TIM3_CH4,
I2S_CKIN, EVENTOUT
ADC34_IN9, COMP5_INP
ADC34_IN10, COMP5_INM
COMP3_INP, ADC34_IN11,
OPAMP2_VINP
COMP3_INM
-
-
-
-
DS9118 Rev 14
STM32F303xB STM32F303xC Pinouts and pin description
Pin number
Table 13. STM32F303xB/STM32F303xC pin definitions (continued)
Pin functions
Pin name
(function after reset)
Alternate functions Additional functions
F5 67 41 29
E5 68 42 30
E1 69 43 31
E2 70 44 32
D1 71 45 33
E3 72 46 34
C1 73 -
A1,
A2,
B1
74 47 35
D2 75 48 36
C2 76 49 37
PA8
PA9
PA10
PA11
PA12
PA13
PF6
VSS
VDD
PA14
I/O FT
I/O FTf
I/O FTf
I/O FT
I/O FT
I/O FT
I/O FTf
-
-
-
-
-
-
(1)
I2C2_SMBA,I2S2_MCK,
USART1_CK, TIM1_CH1,
TIM4_ETR, MCO,
COMP3_OUT, EVENTOUT
I2C2_SCL,I2S3_MCK,
USART1_TX, TIM1_CH2,
TIM2_CH3, TIM15_BKIN,
TSC_G4_IO1, COMP5_OUT,
EVENTOUT
I2C2_SDA, USART1_RX,
TIM1_CH3, TIM2_CH4,
TIM8_BKIN, TIM17_BKIN,
TSC_G4_IO2, COMP6_OUT,
EVENTOUT
USART1_CTS, USB_DM,
CAN_RX, TIM1_CH1N,
TIM1_CH4, TIM1_BKIN2,
TIM4_CH1, COMP1_OUT,
EVENTOUT
USART1_RTS_DE, USB_DP,
CAN_TX, TIM1_CH2N,
TIM1_ETR, TIM4_CH2,
TIM16_CH1, COMP2_OUT,
EVENTOUT
USART3_CTS, TIM4_CH3,
TIM16_CH1N, TSC_G4_IO3,
IR_OUT, SWDIO-JTMS,
EVENTOUT
I2C2_SCL,
USART3_RTS_DE,
TIM4_CH4, EVENTOUT
S
-
Ground
S
-
I/O FTf -
Digital power supply
I2C1_SDA, USART2_TX,
TIM8_CH2,TIM1_BKIN,
TSC_G4_IO4, SWCLK-JTCK,
EVENTOUT
-
-
-
-
-
-
-
-
DS9118 Rev 14
55
Pinouts and pin description STM32F303xB STM32F303xC
Pin number
Table 13. STM32F303xB/STM32F303xC pin definitions (continued)
Pin functions
Pin name
(function after reset)
Alternate functions Additional functions
B2 77 50 38
E4
D3
78
79
51
52
A3 80 53
B3 81
C3 82
A4 83 54
-
-
-
-
-
-
B4 84 -
C4
-
-
D4
85
86
87
88
-
-
-
-
-
-
-
-
-
-
-
A5 89 55 39
PC12
PD0
PD1
PD2
PD4
PD5
PD6
PD7
PA15
PC10
PC11
PD3
PB3
I/O FTf
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT -
-
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
I2C1_SCL, SPI1_NSS,
SPI3_NSS, I2S3_WS, JTDI,
USART2_RX, TIM1_BKIN,
TIM2_CH1_ETR, TIM8_CH1,
EVENTOUT
SPI3_SCK, I2S3_CK,
USART3_TX, UART4_TX,
TIM8_CH1N, EVENTOUT
SPI3_MISO, I2S3ext_SD,
USART3_RX, UART4_RX,
TIM8_CH2N, EVENTOUT
SPI3_MOSI, I2S3_SD,
USART3_CK, UART5_TX,
TIM8_CH3N, EVENTOUT
CAN_RX, EVENTOUT
CAN_TX, TIM8_CH4,
TIM8_BKIN2,EVENTOUT
UART5_RX, TIM3_ETR,
TIM8_BKIN, EVENTOUT
USART2_CTS,
TIM2_CH1_ETR,
EVENTOUT
USART2_RTS_DE,
TIM2_CH2, EVENTOUT
USART2_TX, EVENTOUT
USART2_RX, TIM2_CH4,
EVENTOUT
USART2_CK, TIM2_CH3,
EVENTOUT
SPI3_SCK, I2S3_CK,
SPI1_SCK, USART2_TX,
TIM2_CH2, TIM3_ETR,
TIM4_ETR, TIM8_CH1N,
TSC_G5_IO1, JTDO-
TRACESWO, EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
DS9118 Rev 14
STM32F303xB STM32F303xC Pinouts and pin description
Pin number
Table 13. STM32F303xB/STM32F303xC pin definitions (continued)
Pin functions
Pin name
(function after reset)
Alternate functions Additional functions
B5 90 56 40
A6 91 57 41
B6 92 58 42
C5 93 59 43
A7 94 60 44
D5 95 61 45
C6 96 62 46
B7 97 -
A8 98 -
C7 99 63 47
A9,
A10,
B10,
B8
100 64 48
PB4
PB5
PB6
PB7
BOOT0
PB8
PB9
PE0
PE1
VSS
I/O FT
I/O FT
I/O FTf
I/O FTf
I
I/O FTf
I/O FTf
I/O FT
I/O FT
S
B
-
-
-
-
-
-
-
-
(1)
(1)
SPI3_MISO, I2S3ext_SD,
SPI1_MISO, USART2_RX,
TIM3_CH1, TIM16_CH1,
TIM17_BKIN, TIM8_CH2N,
TSC_G5_IO2, NJTRST,
EVENTOUT
SPI3_MOSI, SPI1_MOSI,
I2S3_SD, I2C1_SMBA,
USART2_CK, TIM16_BKIN,
TIM3_CH2, TIM8_CH3N,
TIM17_CH1, EVENTOUT
I2C1_SCL, USART1_TX,
TIM16_CH1N, TIM4_CH1,
TIM8_CH1,TSC_G5_IO3,
TIM8_ETR, TIM8_BKIN2,
EVENTOUT
I2C1_SDA, USART1_RX,
TIM3_CH4, TIM4_CH2,
TIM17_CH1N, TIM8_BKIN,
TSC_G5_IO4, EVENTOUT
Boot memory selection
I2C1_SCL, CAN_RX,
TIM16_CH1, TIM4_CH3,
TIM8_CH2, TIM1_BKIN,
TSC_SYNC, COMP1_OUT,
EVENTOUT
I2C1_SDA, CAN_TX,
TIM17_CH1, TIM4_CH4,
TIM8_CH3, IR_OUT,
COMP2_OUT, EVENTOUT
USART1_TX, TIM4_ETR,
TIM16_CH1, EVENTOUT
USART1_RX, TIM17_CH1,
EVENTOUT
Ground
-
-
-
-
-
-
-
-
VDD S Digital power supply
DS9118 Rev 14
55
Pinouts and pin description STM32F303xB STM32F303xC
1. Function availability depends on the chosen device.
When using the small packages (48 and 64 pin packages), the GPIO pins which are not present on these packages, must not be configured in analog mode.
2. PC13, PC14 and PC15 are supplied through the power switch. Since the switch sinks only a limited amount of current
(3 mA), the use of GPIO PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF
- These GPIOs must not be used as current sources (e.g. to drive an LED).
After the first backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the Backup registers which is not reset by the main reset. For details on how to manage these GPIOs, refer to the Battery backup domain and BKP register description sections in the RM0316 reference manual.
3. The VREF+ functionality is available only on the 100 pin package. On the 64-pin and 48-pin packages, the VREF+ is internally connected to VDDA.
4. Fast ADC channel.
5. These GPIOs offer a reduced touch sensing sensitivity. It is thus recommended to use them as sampling capacitor I/O.
DS9118 Rev 14
Table 14. Alternate functions for port A
Port
&
Pin
Name
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF14 AF15
PA0
PA1
RTC_
REFIN
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11 -
-
-
-
-
-
-
-
-
-
MCO
TIM2_
CH1_
ETR
TIM2_
CH2
TIM2_
CH3
TIM2_
CH4
-
TSC_
G1_IO1
-
-
-
TSC_
G1_IO2
TSC_
G1_IO3
-
TSC_
G1_IO4
TIM3_
CH2
TSC_
G2_IO1
TIM2_
CH1_
ETR
-
TSC_
G2_IO2
TIM16_
CH1
TIM3_
CH1
TSC_
G2_IO3
TIM17_
CH1
TIM3_
CH2
TSC_
G2_IO4
-
-
TIM17_
BKIN
-
-
-
-
TSC_
G4_IO1
TSC_
G4_IO2
-
-
-
-
-
-
-
TIM8_
BKIN
TIM8_
CH1N
I2C2_
SMBA
I2C2_
SCL
I2C2_
SDA
-
-
-
-
-
SPI1_
NSS
SPI1_
SCK
SPI1_
MISO
SPI1_
MOSI
I2S2_
MCK
I2S3_
MCK
-
-
-
-
-
-
SPI3_NSS,
I2S3_WS
-
TIM1_BKIN
TIM1_CH1
TIM1_CH2
TIM1_CH3
TIM1_CH1N
TIM1_CH1N
USART2_
CTS
USART2_
RTS_DE
USART2_
TX
USART2_
RX
USART2_
CK
-
COMP1
_OUT
COMP2
_OUT
-
-
-
TIM8_
BKIN
TIM15_
CH1N
TIM15_
CH1
TIM15_
CH2
-
-
TIM8_
ETR
-
-
-
-
-
-
-
COMP1
_OUT
COMP2
_OUT
USART1_
CK
COMP3
_OUT
USART1_
TX
COMP5
_OUT
USART1_
RX
COMP6
_OUT
USART1_
CTS
COMP1
_OUT
-
-
-
-
-
TIM15_
BKIN
TIM4_
ETR
TIM2_
CH3
-
TIM2_
CH4
CAN_RX
TIM4_
CH1
-
-
-
-
-
-
-
-
-
-
TIM8_BKIN -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM1_CH4
TIM1_
BKIN2
USB_
DM
EVENT
OUT
EVENT
OUT
EVENT
OUT
EVENT
OUT
EVENT
OUT
EVENT
OUT
EVENT
OUT
EVENT
OUT
EVENT
OUT
EVENT
OUT
EVENT
OUT
EVENT
OUT
Table 14. Alternate functions for port A (continued)
Port
&
Pin
Name
AF0 AF1 AF2 AF3
PA12
PA13
PA14
-
SWDIO
-JTMS
SWCLK
-JTCK
TIM16_
CH1
TIM16_
CH1N
-
PA15 JTDI
TIM2_
CH1_
ETR
-
-
-
TIM8_
CH1
-
-
TSC_
G4_IO3
TSC_
G4_IO4
AF4
-
-
I2C1_
SDA
I2C1_
SCL
AF5
-
IR_
OUT
TIM8_
CH2
-
TIM1_BKIN
SPI1_
NSS
AF6
TIM1_CH2N
SPI3_NSS,
I2S3_WS
AF7 AF8 AF9 AF10
USART1_
RTS_DE
COMP2
_OUT
USART3_
CTS
USART2_
TX
-
-
CAN_TX
-
TIM4_
CH2
TIM4_
CH3
-
USART2_
RX
-
TIM1_
BKIN
-
AF11
TIM1_ETR -
-
-
-
AF12 AF14 AF15
-
-
-
USB_
DP
-
-
EVENT
OUT
EVENT
OUT
EVENT
OUT
-
EVENT
OUT
Table 15. Alternate functions for port B
Port
&
Pin
Name
AF0 AF1 AF2 AF3 AF4 AF5
PB0
PB1
PB2
PB3
PB4
PB5
JTDO-
TRACES
WO
TIM2_
CH2
NJTRST
-
TIM16_
CH1
TIM16_
BKIN
PB6
PB7
PB8
PB9
PB10
PB11 -
-
-
-
-
-
TIM16_
CH1N
TIM17_
CH1N
TIM16_
CH1
TIM17_
CH1
TIM2_
CH3
TIM2_
CH4
TIM4_
ETR
TIM3_
CH1
TIM3_
CH2
TIM4_
CH1
TIM4_
CH2
TIM4_
CH3
TIM4_
CH4
-
-
PB12
-
-
-
-
-
-
-
-
TIM3_
CH3
TIM3_
CH4
-
TSC_
G3_IO2
TSC_
G3_IO3
TSC_
G3_IO4
TIM8_
CH2N
TIM8_
CH3N
-
-
TSC_
TSC_
G5_IO2
TIM8_
CH3N
TSC_
G5_IO3
TSC_
G5_IO4
TSC_
SYNC
TSC_
SYNC
TSC_
G5_IO1
G6_IO1
TSC_
G6_IO2
TIM8_
CH1N
TIM8_
CH2N
I2C1_
SMBA
I2C1_SCL TIM8_CH1
I2C1_
SDA
I2C1_SCL
I2C1_
SDA
I2C2_
-
-
SMBA
SPI1_
SCK
SPI1_
MISO
SPI1_
MOSI
TIM8_
BKIN
-
-
-
-
-
-
-
SPI2_NSS,
I2S2_WS
AF6
TIM1_CH2N
TIM1_CH3N
SPI3_MISO,
I2S3ext_SD
SPI3_MOSI,
I2S3_SD
TIM8_
ETR
-
USART2_
RX
USART2_
CK
USART1_
TX
USART1_
RX
TIM1_
BKIN
-
SPI3_SCK,
I2S3_CK
-
IR_OUT
-
-
-
-
AF7
-
-
-
USART2_
TX
USART3_
TX
USART3_
RX
USART3_
CK
AF8
COMP4_
OUT
-
-
-
-
-
-
-
-
-
-
AF9
-
-
-
-
-
-
-
-
-
-
-
COMP1_
OUT
COMP2_
OUT
CAN_RX
CAN_TX
AF10
-
-
-
-
-
-
TIM3_
ETR
TIM17_
BKIN
TIM17_
CH1
TIM8_
BKIN2
TIM3_
CH4
TIM8_
CH2
TIM8_
CH3
AF12 AF15
-
-
-
-
-
-
-
-
-
-
-
-
TIM1_
BKIN
EVENT
OUT
EVENT
OUT
EVENT
OUT
EVENT
OUT
EVENT
OUT
EVENT
OUT
EVENT
OUT
EVENT
OUT
EVENT
OUT
EVENT
OUT
EVENT
OUT
EVENT
OUT
EVENT
OUT
Table 15. Alternate functions for port B (continued)
Port
&
Pin
Name
PB13
AF0 AF1 AF2 AF3 AF4
-
PB14 -
PB15
RTC_
REFIN
-
TIM15_
CH1
TIM15_
CH2
-
TIM15_
CH1N
TSC_
G6_IO3
TSC_
G6_IO4
-
-
-
TIM1_
CH3N
AF5 AF6
SPI2_SCK,
I2S2_CK
SPI2_MISO,
I2S2ext_SD
SPI2_MOSI,
I2S2_SD
TIM1_
CH1N
TIM1_
CH2N
-
AF7
USART3_
CTS
USART3_
RTS_DE
-
AF8
-
-
-
-
-
-
AF9
-
-
-
AF10 AF12 AF15
-
-
-
EVENT
OUT
EVENT
OUT
EVENT
OUT
Port &
Pin
Name
AF1
PC0
PC1
PC2
PC3
PC4
PC5
PC6
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
PC7
PC8
EVENTOUT
EVENTOUT
PC9 EVENTOUT
PC10 EVENTOUT
PC11 EVENTOUT
PC12 EVENTOUT
PC13
PC14
PC15
-
-
-
AF2
-
-
-
-
-
-
TIM3_CH1
TIM3_CH2
TIM3_CH3
TIM3_CH4
-
-
-
-
-
-
Table 16. Alternate functions for port C
AF3 AF4 AF5
-
-
COMP7_OUT
-
-
TSC_G3_IO1
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM8_CH1
-
-
-
TIM8_CH2
TIM8_CH3
TIM8_CH4
TIM8_CH1N
TIM8_CH2N
TIM8_CH3N
TIM1_CH1N
-
-
-
-
I2S_CKIN
UART4_TX
UART4_RX
UART5_TX
-
-
-
-
-
-
-
-
-
-
AF6
-
-
-
TIM1_BKIN2
-
-
I2S2_MCK
I2S3_MCK
-
TIM8_BKIN2
SPI3_SCK, I2S3_CK
SPI3_MISO, I2S3ext_SD
SPI3_MOSI, I2S3_SD
-
-
-
AF7
-
-
-
-
USART1_TX
USART1_RX
COMP6_OUT
COMP5_OUT
COMP3_OUT
-
USART3_TX
USART3_RX
USART3_CK
-
-
-
Port &
Pin Name
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PD4
PD5
PD6
PD7
PD0
PD1
PD2
PD3
AF1
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
AF2
-
-
TIM3_ETR
TIM2_CH1_ETR
TIM2_CH2
-
TIM2_CH4
TIM2_CH3
TIM4_CH1
TIM4_CH2
TIM4_CH3
TIM4_CH4
-
-
-
-
Table 17. Alternate functions for port D
AF3 AF4 AF5
-
-
-
-
TSC_G8_IO1
TSC_G8_IO2
TSC_G8_IO3
TSC_G8_IO4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM8_CH4
TIM8_BKIN
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
UART5_RX
-
-
-
-
-
AF6
-
TIM8_BKIN2
-
-
-
-
-
-
-
SPI2_NSS
-
-
-
-
-
-
AF7
CAN_RX
CAN_TX
-
USART2_CTS
USART2_RTS_DE
USART2_TX
USART2_RX
USART2_CK
USART3_TX
USART3_RX
USART3_CK
USART3_CTS
USART3_RTS_DE
-
-
-
Port &
Pin Name
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PE4
PE5
PE6
PE7
PE0
PE1
PE2
PE3
AF0
-
-
-
-
-
-
-
-
-
-
TRACECK
TRACED0
TRACED1
TRACED2
TRACED3
-
AF1
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
Table 18. Alternate functions for port E
AF2 AF3
TIM4_ETR
-
TIM3_CH1
TIM3_CH2
TIM3_CH3
TIM3_CH4
TIM1_ETR
TIM1_CH1N
TIM1_CH1
TIM1_CH2N
TIM1_CH2
TIM1_CH3N
TIM1_CH3
TIM1_CH4
TIM1_BKIN -
-
-
-
-
-
-
-
-
-
TSC_G7_IO1
TSC_G7_IO2
TSC_G7_IO3
TSC_G7_IO4
-
-
AF4
-
-
-
-
-
-
-
-
TIM16_CH1
TIM17_CH1
-
-
-
-
-
-
AF6
-
-
TIM1_BKIN2
-
-
-
-
-
-
-
-
-
-
-
-
-
AF7
USART1_TX
USART1_RX
-
-
-
-
-
-
-
-
-
USART3_RX
-
-
-
-
Port &
Pin Name
PF0
PF1
PF2
PF4
PF6
PF9
PF10
AF1
-
-
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
AF2
-
-
-
COMP1_OUT
TIM4_CH4
-
-
Table 19. Alternate functions for port F
AF3 AF4 AF5
-
-
-
-
-
TIM15_CH1
TIM15_CH2
I2C2_SDA
I2C2_SCL
-
-
I2C2_SCL
-
-
-
SPI2_SCK
SPI2_SCK
-
-
-
-
AF6
TIM1_CH3N
-
-
-
-
-
-
AF7
-
-
-
-
USART3_RTS_DE
-
-
STM32F303xB STM32F303xC Memory mapping
Figure 8. STM32F303xB/STM32F303xC memory map
0x5000
07FF
AHB3
0xFFFF FFFF
7
Cortex-M4 with FPU
Internal
Peripherals
0xE000 0000
0x5000 0000
0x4800 1800
0x4800 0000
Reserved
AHB2
Reserved
6
0x4002 43FF
AHB1
0xC000 0000
0x4002 0000
Reserved
5
0x4001 6C00
APB2
0xA000 0000
0x4001 0000
Reserved
4
0x4000 A000
APB1
0x8000 0000
0x4000 0000
3
0x6000 0000
2
0x4000 0000
Peripherals
1
0x2000 0000
0
0x0000 0000
SRAM
CODE
Reserved
0x1FFF FFFF
Option bytes
0x1FFF F800
System memory
0x1FFF D800
0x1000 2000
Reserved
CCM RAM
0x1000 0000
Reserved
0x0804 0000
Flash memory
0x0800 0000
Reserved
0x0004 0000
0x0000 0000
Flash, system memory or SRAM, depending on BOOT configuration
MSv30355V2
DS9118 Rev 14
55
Memory mapping STM32F303xB STM32F303xC
Table 20. STM32F303xB/STM32F303xC memory map, peripheral register boundary addresses (1)
Bus Boundary address
Size
(bytes)
Peripheral
AHB3
AHB2
AHB1
APB2
0x5000 0400 - 0x5000 07FF
0x5000 0000 - 0x5000 03FF
0x4800 1800 - 0x4FFF FFFF
0x4800 1400 - 0x4800 17FF
0x4800 1000 - 0x4800 13FF
0x4800 0C00 - 0x4800 0FFF
0x4800 0800 - 0x4800 0BFF
0x4800 0400 - 0x4800 07FF
0x4800 0000 - 0x4800 03FF
0x4002 4400 - 0x47FF FFFF
0x4002 4000 - 0x4002 43FF
0x4002 3400 - 0x4002 3FFF
0x4002 3000 - 0x4002 33FF
0x4002 2400 - 0x4002 2FFF
0x4002 2000 - 0x4002 23FF
0x4002 1400 - 0x4002 1FFF
0x4002 1000 - 0x4002 13FF
0x4002 0800 - 0x4002 0FFF
0x4002 0400 - 0x4002 07FF
0x4002 0000 - 0x4002 03FF
0x4001 8000 - 0x4001 FFFF
0x4001 4C00 - 0x4001 7FFF
0x4001 4800 - 0x4001 4BFF
0x4001 4400 - 0x4001 47FF
0x4001 4000 - 0x4001 43FF
0x4001 3C00 - 0x4001 3FFF
0x4001 3800 - 0x4001 3BFF
0x4001 3400 - 0x4001 37FF
0x4001 3000 - 0x4001 33FF
0x4001 2C00 - 0x4001 2FFF
0x4001 0800 - 0x4001 2BFF
0x4001 0400 - 0x4001 07FF
0x4001 0000 - 0x4001 03FF
1 K
32 K
13 K
1 K
1 K
1 K
3 K
1 K
3 K
1 K
2 K
1 K
1 K
1 K
1 K
1 K
1 K
9 K
1 K
1 K
1 K
1 K
~132 M
1 K
1 K
1 K
1 K
1 K
1 K
~128 M
1 K
3 K
1 K
Reserved
Flash interface
Reserved
RCC
Reserved
DMA2
DMA1
Reserved
Reserved
TIM17
TIM16
TIM15
ADC3 - ADC4
ADC1 - ADC2
Reserved
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
Reserved
TSC
Reserved
CRC
Reserved
USART1
TIM8
SPI1
TIM1
Reserved
EXTI
SYSCFG + COMP + OPAMP
DS9118 Rev 14
STM32F303xB STM32F303xC Memory mapping
Table 20. STM32F303xB/STM32F303xC memory map, peripheral register boundary addresses (1) (continued)
Bus Boundary address
Size
(bytes)
Peripheral
APB1
0x4000 8000 - 0x4000 FFFF
0x4000 7800 - 0x4000 7FFF
0x4000 7400 - 0x4000 77FF
0x4000 7000 - 0x4000 73FF
0x4000 6800 - 0x4000 6FFF
0x4000 6400 - 0x4000 67FF
0x4000 6000 - 0x4000 63FF
0x4000 5C00 - 0x4000 5FFF
0x4000 5800 - 0x4000 5BFF
0x4000 5400 - 0x4000 57FF
0x4000 5000 - 0x4000 53FF
0x4000 4C00 - 0x4000 4FFF
0x4000 4800 - 0x4000 4BFF
0x4000 4400 - 0x4000 47FF
0x4000 4000 - 0x4000 43FF
0x4000 3C00 - 0x4000 3FFF
0x4000 3800 - 0x4000 3BFF
0x4000 3400 - 0x4000 37FF
0x4000 3000 - 0x4000 33FF
0x4000 2C00 - 0x4000 2FFF
0x4000 2800 - 0x4000 2BFF
0x4000 1800 - 0x4000 27FF
0x4000 1400 - 0x4000 17FF
0x4000 1000 - 0x4000 13FF
0x4000 0C00 - 0x4000 0FFF
0x4000 0800 - 0x4000 0BFF
0x4000 0400 - 0x4000 07FF
0x4000 0000 - 0x4000 03FF
1. The gray color is used for reserved Flash memory addresses.
I2S2ext
IWDG
WWDG
RTC
Reserved
TIM7
TIM6
Reserved
TIM4
TIM3
TIM2
Reserved
Reserved
DAC (dual)
PWR
Reserved bxCAN
USB SRAM 512 bytes
USB device FS
I2C2
I2C1
UART5
UART4
USART3
USART2
I2S3ext
SPI3/I2S3
SPI2/I2S2
1 K
1 K
1 K
1 K
1 K
1 K
1 K
1 K
1 K
4 K
1 K
1 K
1 K
1 K
1 K
1 K
1 K
1 K
1 K
1 K
1 K
32 K
2 K
1 K
1 K
2 K
1 K
1 K
DS9118 Rev 14
55
Electrical characteristics STM32F303xB STM32F303xC
6.1.1
Unless otherwise specified, all voltages are referenced to V
SS
.
Minimum and maximum values
Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T
A the selected temperature range).
= 25 °C and T
A
= T
A max (given by
Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3 σ ).
Unless otherwise specified, typical data are based on T
A are given only as design guidelines and are not tested.
= 25 °C, V
DD
= V
DDA
= 3.3 V. They
Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2 σ )
.
Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.
The loading conditions used for pin parameter measurement are shown in
.
6.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in
Figure 9. Pin loading conditions Figure 10. Pin input voltage
MCU pin MCU pin
C = 50 pF
V
IN
MS19210V1 MS19211V1
DS9118 Rev 14
STM32F303xB STM32F303xC
6.1.6 Power supply scheme
1.65 – 3.6 V
Figure 11. Power supply scheme
V
BAT
Power switch
Electrical characteristics
Backup circuitry
(LSE, RTC,
Wakeup logic,
Backup registers)
GP I/Os
OUT
IN
I/O logic
Kernel logic
(CPU, digital
& memories)
4 x 100 nF
+ 1 x 4.7 μF
V
DDA
V
DD
4 x V
DD
4 x V
SS
V
DDA
Regulator
10 nF
+ 1 μF
V
REF+
V
REF-
ADC/DAC
Analog: RCs,
PLL,comparators, OPAMP,
....
V
SSA
MS19875V5
1. Dotted lines represent the internal connections on low pin count packages, joining the dedicated supply pins.
Caution: Each power supply pair (V
DD
/V
SS
, V
DDA
/V
SSA
etc..) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below the appropriate pins on the underside of the PCB to ensure the good functionality of the device.
DS9118 Rev 14
125
Electrical characteristics STM32F303xB STM32F303xC
Figure 12. Current consumption measurement scheme
IDD_VBAT
VBAT
IDD
VDD
IDDA
VDDA
MS19213V1
6.2 Absolute maximum ratings
Stresses above the absolute maximum ratings listed in
Table 21: Voltage characteristics
,
Table 22: Current characteristics
, and
Table 23: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Symbol
Table 21. Voltage characteristics (1)
Ratings Min Max Unit
V
V
V
REF+
|V
V
|
DD
DD
V
Δ
–V
–V
IN
(3)
V
–V
SS
DDA
DDA
(2)
DDx
SSX
− V
|
SS
ESD(HBM)
|
External main supply voltage (including V
DDA, and V
DD
)
V
BAT
Allowed voltage difference for V
DD
> V
DDA
Allowed voltage difference for V
REF+
> V
DDA
Input voltage on FT and FTf pins
Input voltage on TTa pins
Input voltage on any other pin
Input voltage on Boot0 pin
Variations between different V
Electrostatic discharge voltage (human body model)
DD power pins
Variations between all the different ground pins
(4)
-0.3
4.0
-
-
V
SS
− 0.3
V
SS
− 0.3
V
SS
− 0.3
0
0.4
0.4
V
DD
+ 4.0
4.0
4.0
9
-
50
50 see
Section 6.3.12: Electrical sensitivity characteristics
1. All main power (V
V
V
DDA
DDA
DD
, V
DDA
) and ground (V
SS
, V
SSA
) pins must always be connected to the external power supply, in the
must power on before or at the same time as V
must be greater than or equal to V
DD
.
DD
DDA
and V
in the power up sequence.
DD
:
V mV
-
DS9118 Rev 14
STM32F303xB STM32F303xC Electrical characteristics
2. V
REF+ must be always lower or equal than V
DDA
(V
REF+
≤ V
DDA)
. If unused then it must be connected to V
DDA
.
3. V
IN
maximum must always be respected. Refer to
Table 22: Current characteristics for the maximum allowed injected
current values.
4. Include VREF- pin.
Symbol
Table 22. Current characteristics
Ratings Max.
Unit
Σ
I
Σ
I
IO(PIN)
I
Σ I
I
I
I
VDD
VSS
VDD
VSS
IO(PIN)
INJ(PIN)
Total current into sum of all V
DD power lines (source)
Total current out of sum of all V
SS
ground lines (sink)
Maximum current into each V
DD power line (source)
(1)
Maximum current out of each V
SS ground line (sink)
(1)
Output current sunk by any I/O and control pin
Output current source by any I/O and control pin
Total output current sunk by sum of all IOs and control pins (2)
Total output current sourced by sum of all IOs and control pins
(2)
Injected current on FT, FTf and B pins
(3)
Injected current on TC and RST pin
(4)
Injected current on TTa pins
(5)
Total injected current (sum of all I/O and control pins)
(6)
−
160
100
− 100
25
−
−
160
25
80
80
-5/+0
± 5
± 5 mA
Σ I
INJ(PIN)
± 25
1. All main power (V permitted range.
DD
, V
DDA
) and ground (V
SS
and V
SSA
) pins must always be connected to the external power supply, in the
2. This current consumption must be correctly distributed over all I/Os and control pins.The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.
3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.
4. A positive injection is induced by V
> V
DD
while a negative injection is induced by V < V
SS
. I
INJ(PIN)
must never be
5. A positive injection is induced by V
IN
> V
DDA
while a negative injection is induced by V
Table 21: Voltage characteristics
IN
< V
SS
. I (PIN) must never be
for the maximum allowed input voltage values. Negative injection disturbs the analog performance of the device. See note
(2)
below
.
6. When several inputs are submitted to a current injection, the maximum negative injected currents (instantaneous values).
Σ I
INJ(PIN)
is the absolute sum of the positive and
Symbol
T
STG
T
J
Table 23. Thermal characteristics
Ratings
Storage temperature range
Maximum junction temperature
Value
–65 to +150
150
Unit
°C
°C
DS9118 Rev 14
125
Electrical characteristics STM32F303xB STM32F303xC
6.3.1 General operating conditions
Symbol
Table 24. General operating conditions
Parameter Conditions Min Max Unit f f f
HCLK
PCLK1
PCLK2
V
V
V
DD
DDA
BAT
V
P
T
T
IN
D
A
J
Internal AHB clock frequency
Internal APB1 clock frequency
Internal APB2 clock frequency
Standard operating voltage
Analog operating voltage
(OPAMP and DAC not used)
Analog operating voltage
(OPAMP and DAC used)
-
-
Must have a potential equal to or higher than
V
DD
Backup operating voltage
-
-
I/O input voltage
Power dissipation at T
85 °C for suffix 6 or T
A
105 °C for suffix 7
(2)
A
=
=
-
TC I/O
TTa I/O
FT and FTf I/O
(1)
BOOT0
WLCSP100
LQFP100
LQFP64
Ambient temperature for 6 suffix version
LQFP48
Maximum power dissipation
Low-power dissipation
(3)
Ambient temperature for 7 suffix version
Junction temperature range
Maximum power dissipation
Low-power dissipation
(3)
6 suffix version
7 suffix version
0
0
0
2
2
2.4
72
36
72
3.6
3.6
3.6
1.65
3.6
–0.3
V
DD
+0.3
–0.3
V
DDA
+0.3
–0.3
5.5
-
-
0
-
-
5.5
500
488
444
364
–40 85
–40 105
–40 105
–40 125
–40
–40
105
125
MHz
V
V
V
V mW
°C
°C
°C
1. To sustain a voltage higher than V
DD
+0.3 V, the internal pull-up/pull-down resistors must be disabled.
2. If T is lower, higher P
D
values are allowed as long as T
J
does not exceed T
Jmax
(see
3. In low-power dissipation state, T
A
can be extended to this range as long as T
Section 7.5: Thermal characteristics ).
J
does not exceed T
Jmax
(see
DS9118 Rev 14
STM32F303xB STM32F303xC Electrical characteristics
6.3.3
The parameters given in
Table 25 are derived from tests performed under the ambient
temperature condition summarized in
Symbol t
VDD t
VDDA
Table 25. Operating conditions at power-up / power-down
Parameter Conditions Min Max
V
DD
rise time rate
V
DD
fall time rate
V
DDA
rise time rate
V
DDA
fall time rate
-
-
0
20
0
20
∞
∞
∞
∞
Unit
µs/V
Embedded reset and power control block characteristics
The parameters given in
Table 26 are derived from tests performed under ambient
temperature and V
DD
supply voltage conditions summarized in
Symbol
Table 26. Embedded reset and power control block characteristics
Parameter Conditions Min Typ Max Unit
V
POR/PDR
(1)
V
PDRhyst
(1) t
RSTTEMPO
(3)
Power on/power down reset threshold
PDR hysteresis
POR reset temporization
Falling edge
Rising edge
-
-
1.8
(2)
1.84
-
1.5
1.88
1.92
40
2.5
1.96
2.0
-
4.5
1. The PDR detector monitors V monitors only V
DD
.
DD
and also V
DDA
(if kept enabled in the option bytes). The POR detector
2. The product behavior is guaranteed by design down to the minimum V
POR/PDR
value.
3. Guaranteed by design.
V
V mV ms
DS9118 Rev 14
125
Electrical characteristics STM32F303xB STM32F303xC
Symbol
V
PVD0
V
PVD1
V
PVD2
V
PVD3
V
PVD4
V
PVD5
V
PVD6
V
PVD7
Table 27. Programmable voltage detector characteristics
Parameter Conditions Min
(1)
Typ Max
(1)
PVD threshold 0
PVD threshold 1
PVD threshold 2
PVD threshold 3
PVD threshold 4
PVD threshold 5
PVD threshold 6
PVD threshold 7
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
-
2.47
2.37
2.57
2.47
2.66
2.56
2.28
2.18
2.38
2.28
2.1
2
2.19
2.09
2.76
2.66
V
PVDhyst
(2)
IDD(PVD)
PVD hysteresis
PVD current consumption
1. Guaranteed by characterization results.
2. Guaranteed by design.
-
2.18
2.26
2.08
2.16
2.28
2.37
2.18
2.27
2.38
2.48
2.28
2.38
2.48
2.58
2.38
2.48
2.58
2.69
2.48
2.59
2.68
2.79
2.58
2.69
2.78
2.9
2.68
2.8
2.88
2.78
100
3
2.9
-
0.15
0.26
Unit
V mV
µA
DS9118 Rev 14
STM32F303xB STM32F303xC Electrical characteristics
6.3.5
The parameters given in
Table 28 are derived from tests performed under ambient
temperature and V
DD
supply voltage conditions summarized in
Symbol
V
REFINT
Table 28. Embedded internal reference voltage
Parameter Conditions Min Typ Max
Internal reference voltage
–40 °C < T
A
< +105 °C 1.2
1.23
1.25
–40 °C < T
A
< +85 °C 1.2
1.23 1.24
(1)
T
V
S_vrefint
RERINT
ADC sampling time when reading the internal reference voltage
Internal reference voltage spread over the temperature range
T
Coeff
Temperature coefficient
1. Guaranteed by characterization results.
2. Guaranteed by design.
-
V
DD
= 3 V ±10 mV
-
2.2
-
-
-
-
-
10
(2)
Unit
V
V
µs mV
100
(2) ppm/°C
Table 29. Internal reference voltage calibration values
Calibration value name Description Memory address
V
REFINT_CAL
Raw data acquired at temperature of 30 °C
V
DDA
= 3.3 V
0x1FFF F7BA - 0x1FFF F7BB
Supply current characteristics
The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code.
The current consumption is measured as described in
Figure 12: Current consumption measurement scheme
.
All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to CoreMark code.
Typical and maximum current consumption
The MCU is placed under the following conditions:
• All I/O pins are in input mode with a static value at V
DD
or V
SS
(no load)
• All peripherals are disabled except when explicitly mentioned
• The Flash memory access time is adjusted to the f
HCLK
frequency (0 wait state from 0 to 24 MHz,1 wait state from 24 to 48 MHz and 2 wait states from 48 to 72 MHz)
• Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling)
• When the peripherals are enabled f
PCLK2
= f
HCLK
and f
PCLK1
= f
HCLK/2
• When f
HCLK
> 8 MHz, the PLL is ON and the PLL input is equal to HSI/2 (4 MHz) or
HSE (8 MHz) in bypass mode.
DS9118 Rev 14
125
Electrical characteristics STM32F303xB STM32F303xC
The parameters given in
Table 34 are derived from tests performed under
ambient temperature and supply voltage conditions summarized in
Table 30. Typical and maximum current consumption from V
DD
supply at V
DD
= 3.6V
All peripherals enabled All peripherals disabled
Symbol Parameter Conditions
I
DD f
HCLK
Typ
Max @ T
A
(1)
25 °C 85 °C 105 °C
Typ
Max @ T
A
(1)
25 °C 85 °C 105 °C
72 MHz 61.2
65.8
67.6
64 MHz 54.7
59.1
60.2
Supply current in
Run mode, executing from Flash
External clock (HSE bypass)
48 MHz 41.7
45.1
46.2
32 MHz 28.1
31.5
32.5
24 MHz 21.4
8 MHz
1 MHz
7.4
1.3
64 MHz 49.7
23.7
8.4
1.6
54.4
24.4
8.6
1.8
55.4
48 MHz 37.9
42.2
43.0
Internal clock (HSI)
68.5
61.1
47.2
32.7
25.2
9.4
2.6
27.8
24.6
19.2
12.9
10.0
3.6
0.8
30.3
27.2
21.1
14.6
11.4
4.1
1.0
30.7
27.6
21.4
14.8
11.4
4.4
1.2
56.3
24.5
27.2
27.4
43.5
18.9
21.4
21.5
31.5
28.3
21.8
15.3
32 MHz 25.8
29.2
29.2
24 MHz 19.7
22.3
22.6
30.0
12.7
14.2
14.6
23.2
6.7
7.7
7.9
15.2
8.5
8 MHz 6.9
7.8
72 MHz 60.8 66.2
(2)
8.3
64 MHz 54.3
59.1
62.2
8.8
69.7
70.4
(2)
63.3
3.5
4.0
27.4 31.7
24.3
(2)
28.3
4.4
28.7
5.0
32.2
32.5
(2)
28.8
12.1
5.0
2.1
28.1
21.6
Supply current in
Run mode, executing from RAM
External clock (HSE bypass)
48 MHz 41.0
45.6
47.3
32 MHz 27.6
24 MHz 20.8
8 MHz 6.9
7.8
1 MHz 0.9
64 MHz 49.2
32.4
23.9
1.2
53.9
32.4
24.3
8.7
1.5
55.2
48 MHz 37.3
40.8
41.4
Internal clock (HSI)
32 MHz 25.1
27.6
29.1
24 MHz 19.0
21.6
22.1
8 MHz 6.4
7.3
7.9
47.9
32.9
12.3
15.0
15.2
25.0
9.3
11.3
11.4
9.0
2.3
57.4
44.1
8.4
18.3
3.1
0.4
23.9
18.2
3.0
21.6
3.7
0.6
27.8
21.0
3.5
21.9
4.2
1.0
28.2
21.6
30.1
12.0
14.0
14.5
22.9
6.3
7.2
7.7
4.0
22.1
15.4
12.0
4.9
1.8
28.4
21.9
15.1
8.1
4.7
Unit mA
DS9118 Rev 14
STM32F303xB STM32F303xC Electrical characteristics
Table 30. Typical and maximum current consumption from V
DD
supply at V
DD
= 3.6V (continued)
All peripherals enabled All peripherals disabled
Symbol Parameter Conditions f
HCLK
Typ
Max @ T
A
(1)
25 °C 85 °C 105 °C
Typ
Max @ T
A
(1)
25 °C 85 °C 105 °C
I
DD
Supply current in
Sleep mode, executing from Flash or RAM
72 MHz 44.0
48.4
49.4
64 MHz 39.2
43.3
44.0
External clock (HSE bypass)
48 MHz 29.6
32.7
33.3
32 MHz 19.7
23.3
23.3
24 MHz 14.9
17.6
17.8
8 MHz 4.9
5.7
6.1
1 MHz 0.6
64 MHz 34.2
0.9
38.1
1.2
39.2
48 MHz 25.8
28.7
29.6
Internal clock (HSI)
32 MHz 17.4
19.4
19.9
24 MHz 13.2
15.1
15.6
8 MHz 4.5
5.0
5.6
50.5
45.2
34.3
23.5
18.3
6.9
2.1
40.3
30.3
20.7
15.9
6.2
1. Guaranteed by characterization results unless otherwise specified.
2. Data based on characterization results and tested in production with code executing from RAM.
6.6
7.5
6.0
6.8
4.5
5.2
3.1
3.5
2.4
2.8
0.8
1.0
0.1
0.3
5.7
6.3
4.3
4.8
2.9
3.2
1.5
1.8
0.7
0.9
7.9
7.2
5.6
4.0
3.3
1.4
0.6
6.8
5.2
3.7
2.2
1.2
Unit mA
3.9
2.2
1.5
7.5
5.9
4.5
2.9
2.1
8.7
7.9
6.3
4.8
Table 31. Typical and maximum current consumption from the V
DDA
supply
V
DDA
= 2.4 V V
DDA
= 3.6 V
Symbol Parameter
Conditions
(1) f
HCLK
Typ
Max @ T
A
(2)
25 °C 85 °C 105 °C
Typ
Max @ T
A
(2)
25 °C 85 °C 105 °C
Unit
I
DDA
Supply current in
Run/Sleep mode, code executing from Flash or RAM
HSE bypass
HSI clock
72 MHz 225 276
64 MHz 198 249
48 MHz 149 195
32 MHz 102 145
24 MHz 80 119
8 MHz
1 MHz
2
2
3
3
64 MHz 270 323
48 MHz 220 269
32 MHz 173 218
24 MHz 151 194
8 MHz 73 97
289
261
204
152
124
4
5
337
280
228
200
99
297
268
211 159 209 222
157 110 154 162
128
6
7
103
245
216
86
3
3
88
302
270
126
4
4
105
319
284
131
5
6
344 299 354 371
286 244 293 309
233 193 239 251
204 169 211 219
110
1. Current consumption from the V
PLL is off, I
DDA
DDA
supply is independent of whether the peripherals are on or off. Furthermore when the
is independent from the frequency.
2. Guaranteed by characterization results.
µA
9
9
381
318
257
225
116
329
293
230
169
135
DS9118 Rev 14
125
Electrical characteristics STM32F303xB STM32F303xC
Table 32. Typical and maximum V
DD
consumption in Stop and Standby modes
Typ @V
DD
(V
DD
=V
DDA
) Max
(1)
Symbol Parameter Conditions
2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V
T
A
=
25 °C
T
A
=
85 °C
T
A
=
105 °C
Unit
I
DD
Supply current in
Stop mode
Regulator in run mode, all oscillators OFF
Regulator in low-power mode, all oscillators OFF
20.05 20.33 20.42 20.50 20.67 20.80 44.2
(2)
7.63 7.77 7.90 8.07 8.17 8.33 30.6
(2)
Supply current in
Standby mode
LSI ON and IWDG ON 0.80 0.96 1.09 1.23 1.37 1.51
-
LSI OFF and IWDG OFF 0.60 0.74 0.83 0.93 1.02 1.11 5.0
(2)
1. Guaranteed by characterization results unless otherwise specified.
2. Data based on characterization results and tested in production.
350 735
(2)
335 720
(2)
-
7.8
-
13.3
(2)
µA
Table 33. Typical and maximum V
DDA
consumption in Stop and Standby modes
Typ @V
DD
(V
DD
= V
DDA
) Max
(1)
Symbol Parameter Conditions
2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V
T
A
=
25 °C
T
A
=
85 °C
T
A
=
105 °C
Unit
Supply current in
Stop mode
Regulator in run mode, all oscillators OFF
1.81 1.95 2.07 2.20 2.35 2.52
3.7
Regulator in low-power mode, all oscillators
OFF
1.81 1.95 2.07 2.20 2.35 2.52
3.7
LSI ON and IWDG ON 2.22 2.42 2.59 2.78
3.0
3.24
Supply current in
Standby mode
LSI OFF and IWDG
OFF
1.69 1.82 1.94 2.08 2.23 2.40
I
DDA
Supply current in
Stop mode
Regulator in run mode, all oscillators OFF
1.05 1.08 1.10 1.15 1.22 1.29
Regulator in low-power mode, all oscillators
OFF
1.05 1.08 1.10 1.15 1.22 1.29
LSI ON and IWDG ON 1.44 1.52 1.60 1.71 1.84 1.98
Supply current in
Standby mode
LSI OFF and IWDG
OFF
1. Guaranteed by characterization results.
0.93 0.95 0.98 1.02 1.08 1.15
3.5
-
-
-
-
5.5
5.5
-
5.4
-
-
-
-
8.8
8.8
-
-
-
-
-
9.2
µA
The total consumption is the sum of IDD and IDDA.
DS9118 Rev 14
STM32F303xB STM32F303xC Electrical characteristics
Symbol
Table 34. Typical and maximum current consumption from V
BAT
supply
Para meter
Conditions
(1)
Typ @V
BAT
1.65V 1.8V 2V 2.4V 2.7V
3V 3.3V 3.6V
@V
Max
BAT
= 3.6 V
(2)
T
A
=
25°C
T
A
=
85°C
T
A
=
105°C
Unit
I
DD_VBAT
Backup domain supply current
LSE & RTC
ON; "Xtal mode" lower driving capability;
LSEDRV[1:
0] = '00'
LSE & RTC
ON; "Xtal mode" higher driving capability;
LSEDRV[1:
0] = '11'
0.48
0.83
0.50 0.52 0.58
0.86 0.90 0.98
0.65 0.72 0.80 0.90
1.03 1.10 1.20 1.30
1. Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values.
2. Guaranteed by characterization results.
1.1
1.5
1.5
2.2
2.0
2.9
µA
Figure 13. Typical V
BAT
current consumption (LSE and RTC ON/LSEDRV[1:0] = ’00’)
1.4
1.2
1
0.8
0.6
0.4
0.2
0
1.65 V
1.8 V
2 V
2.4 V
2.7 V
3 V
3.3 V
3.6 V
25°C 60°C
T
A
(°C)
85°C 105°C
MS31124V1
DS9118 Rev 14
125
Electrical characteristics STM32F303xB STM32F303xC
Typical current consumption
The MCU is placed under the following conditions:
• V
DD
= V
DDA
= 3.3 V
• All I/O pins available on each package are in analog input configuration
• The Flash access time is adjusted to f
HCLK
frequency (0 wait states from 0 to 24 MHz,
1 wait state from 24 to 48 MHz and 2 wait states from 48 MHz to 72 MHz), and Flash prefetch is ON
• When the peripherals are enabled, f
APB1
= f
AHB/2
, f
APB2
= f
AHB
• PLL is used for frequencies greater than 8 MHz
• AHB prescaler of 2, 4, 8,16 and 64 is used for the frequencies 4 MHz, 2 MHz, 1 MHz,
500 kHz and 125 kHz respectively.
Table 35. Typical current consumption in Run mode, code with data processing running from
Flash
Typ
Symbol Parameter Conditions f
HCLK Peripherals enabled
Peripherals disabled
Unit
I
DD
I
DDA
(1) (2)
Supply current in
Run mode from
V
DD
supply
Supply current in
Run mode from
V
DDA
supply
Running from HSE crystal clock 8 MHz, code executing from
Flash
72 MHz
64 MHz
48 MHz
32 MHz
24 MHz
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz
125 kHz
72 MHz
64 MHz
48 MHz
32 MHz
24 MHz
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz
125 kHz
61.3
54.8
41.9
28.5
21.8
14.9
7.7
4.5
2.8
1.9
1.4
1.1
240.3
210.9
155.8
105.7
82.1
58.8
2.4
2.4
2.4
2.4
2.4
2.4
28.0
25.4
19.3
13.3
10.4
7.2
3.9
2.5
1.7
1.3
1.1
0.9
239.5
210.3
155.6
105.6
82.0
58.8
2.4
2.4
2.4
2.4
2.4
2.4
mA
µA
1. V
DDA
monitoring is ON.
2. When peripherals are enabled, the power consumption of the analog part of peripherals such as ADC, DAC, Comparators,
OpAmp etc. is not included. Refer to the tables of characteristics in the subsequent sections.
DS9118 Rev 14
STM32F303xB STM32F303xC Electrical characteristics
Table 36. Typical current consumption in Sleep mode, code running from Flash or RAM
Typ
Symbol Parameter Conditions f
HCLK Peripherals enabled
Peripherals disabled
Unit
I
I
DD
DDA
(1) (2)
Supply current in
Sleep mode from
V
DD
supply
Supply current in
Sleep mode from
V
DDA
supply
Running from HSE crystal clock 8 MHz, code executing from
Flash or RAM
500 kHz
125 kHz
72 MHz
64 MHz
48 MHz
32 MHz
24 MHz
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz
125 kHz
72 MHz
64 MHz
48 MHz
32 MHz
24 MHz
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
44.1
39.7
30.3
20.5
15.4
10.6
5.4
3.2
2.1
1.5
1.2
1.0
239.7
210.5
155.0
105.3
81.9
58.7
2.4
2.4
2.4
2.4
2.4
2.4
mA
µA
1. V
DDA
monitoring is ON.
2. When peripherals are enabled, the power consumption of the analog part of peripherals such as ADC, DAC, Comparators,
OpAmp etc. is not included. Refer to the tables of characteristics in the subsequent sections.
0.8
0.8
238.5
209.6
155.6
105.2
81.8
58.6
2.4
2.4
2.4
2.4
2.4
2.4
7.0
2.0
1.1
1.0
0.9
0.8
6.3
4.9
3.5
2.8
DS9118 Rev 14
125
Electrical characteristics STM32F303xB STM32F303xC
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in
Table 54: I/O static characteristics
.
For the output pins, any external pull-down or external load must also be considered to estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode.
I/O dynamic current consumption
When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin:
I
SW
= V
DD
× f
SW
× C where
I
SW
is the current sunk by a switching I/O to charge/discharge the capacitive load
V
DD
is the MCU supply voltage f
SW
is the I/O switching frequency
C is the total capacitance seen by the I/O pin: C = C
INT
+ C
EXT
+C
S
The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency.
DS9118 Rev 14
STM32F303xB STM32F303xC Electrical characteristics
Symbol
I
SW
Table 37. Switching output I/O current consumption
Parameter Conditions
(1)
I/O toggling frequency (f
SW
)
2 MHz
Typ
0.90
I/O current consumption
V
DD
= 3.3 V
C ext
= 0 pF
C = C
INT
+ C
EXT
+ C
S
V
DD
C ext
C = C
INT
= 3.3 V
= 10 pF
+ C
EXT
+C
S
V
DD
C ext
C = C
INT
= 3.3 V
= 22 pF
+ C
EXT
+C
S
V
DD
C ext
C = C
INT
= 3.3 V
= 33 pF
+ C
EXT
+ C
S
V
DD
C ext
C = C
INT
= 3.3 V
= 47 pF
+ C
EXT
+ C
S
4 MHz
8 MHz
18 MHz
36 MHz
48 MHz
2 MHz
4 MHz
8 MHz
18 MHz
36 MHz
48 MHz
2 MHz
4 MHz
8 MHz
18 MHz
36 MHz
2 MHz
4 MHz
8 MHz
18 MHz
36 MHz
2 MHz
4 MHz
8 MHz
18 MHz
36 MHz
1.30
1.79
3.01
5.99
1.10
1.31
2.97
0.93
1.06
1.47
2.26
0.93
1.16
1.60
2.51
3.39
5.99
1.03
2.06
3.47
8.35
1.20
1.54
2.46
4.51
9.98
1. CS = 5 pF (estimated value).
Unit mA
DS9118 Rev 14
125
Electrical characteristics STM32F303xB STM32F303xC
On-chip peripheral current consumption
The MCU is placed under the following conditions:
• all I/O pins are in analog input configuration
• all peripherals are disabled unless otherwise mentioned
• the given value is calculated by measuring the current consumption
– with all peripherals clocked off
– with only one peripheral clocked on
• ambient operating temperature at 25°C and V
DD
= V
DDA
= 3.3 V.
Table 38. Peripheral current consumption
Typical consumption (1)
Peripheral
BusMatrix
(2)
DMA1
DMA2
CRC
GPIOA
GPIOB
GPIOC
GPIOD
GPIOE
GPIOF
3.3
3.0
TSC 5.5
ADC1&2 17.3
ADC3&4 18.8
APB2-Bridge (3)
3.6
SYSCFG 7.3
10.0
10.3
2.2
8.8
I
DD
12.6
7.6
6.1
2.1
TIM1
SPI1
TIM8
USART1
TIM15
TIM16
TIM17
APB1-Bridge
(3)
TIM2
TIM3
TIM4
10.1
11.0
6.1
49.1
38.8
38.3
40.0
8.8
36.4
23.3
17.1
Unit
µA/MHz
DS9118 Rev 14
STM32F303xB STM32F303xC Electrical characteristics
Table 38. Peripheral current consumption (continued)
Typical consumption (1)
Peripheral
I
DD
TIM6
TIM7
WWDG
SPI2
SPI3
USART2
USART3
UART4
UART5
I2C1
I2C2
USB
CAN
PWR
DAC
40.2
36.5
30.8
10.5
9.7
12.1
6.4
40.4
40.0
41.9
10.4
26.2
33.4
5.7
15.4
Unit
µA/MHz
1. The power consumption of the analog part (I
DDA
) of peripherals such as ADC, DAC, Comparators, OpAmp etc. is not included. Refer to the tables of characteristics in the subsequent sections.
2. BusMatrix is automatically active when at least one master is ON (CPU, DMA1 or DMA2).
3. The APBx bridge is automatically active when at least one peripheral is ON on the same bus.
DS9118 Rev 14
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Electrical characteristics STM32F303xB STM32F303xC
6.3.6 Wakeup time from low-power mode
The wakeup times given in Table 39
are measured starting from the wakeup event trigger up to the first instruction executed by the CPU:
• For Stop or Sleep mode: the wakeup event is WFE.
• WKUP1 (PA0) pin is used to wakeup from Standby, Stop and Sleep modes.
All timings are derived from tests performed under ambient temperature and V
DD voltage conditions summarized in
supply
Symbol
Table 39. Low-power mode wakeup timings
Typ @V
DD,
V
DD
= V
DDA
Parameter Conditions
2.0 V 2.4 V 2.7 V 3 V 3.3 V 3.6 V
Max Unit t
WUSTOP
Wakeup from
Stop mode t
WUSTANDBY
(1)
Wakeup from
Standby mode
Regulator in run mode
Regulator in low-power mode
LSI and
IWDG OFF
4.1
7.9
69.2
3.9
6.7
60.3
3.8
6.1
56.4
3.7
5.7
53.7
3.6
5.4
51.7
3.5
5.2
50
4.5
9
100
µs t
WUSLEEP
Wakeup from
Sleep mode
6 -
CPU clock cycles
1. Guaranteed by characterization results.
DS9118 Rev 14
STM32F303xB STM32F303xC Electrical characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO. The
external clock signal has to respect the I/O characteristics in Section 6.3.14
. However, the
recommended clock input waveform is shown in Figure 14 .
Symbol
Table 40. High-speed external user clock characteristics
Parameter f
HSE_ext
User external clock source frequency
(1)
V
HSEH
V
HSEL t w(HSEH) t w(HSEL) t r(HSE) t f(HSE)
OSC_IN input pin high level voltage
OSC_IN input pin low level voltage
OSC_IN high or low time
OSC_IN rise or fall time
1. Guaranteed by design.
(1)
(1)
Conditions
-
Min
1
0.7V
DD
V
SS
15
-
Typ Max Unit
8
-
-
-
-
32
V
DD
0.3V
DD
-
20
MHz
V ns
Figure 14. High-speed external clock source AC timing diagram tw(HSEH)
VHSEH
VHSEL
90%
10% tr(HSE)
THSE tf(HSE) tw(HSEL) t
MS19214V2
DS9118 Rev 14
125
Electrical characteristics STM32F303xB STM32F303xC
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO. The
external clock signal has to respect the I/O characteristics in Section 6.3.14
. However, the
recommended clock input waveform is shown in Figure 15
Symbol
Table 41. Low-speed external user clock characteristics
Parameter f
LSE_ext
V
LSEH
User External clock source frequency
(1)
OSC32_IN input pin high level voltage
V
LSEL
OSC32_IN input pin low level voltage t w(LSEH) t w(LSEL) t r(LSE) t f(LSE)
OSC32_IN high or low time
OSC32_IN rise or fall time
1. Guaranteed by design.
(1)
(1)
Conditions
-
Min
0.7V
DD
V
SS
450
-
-
Typ
32.768
-
-
-
-
Max
1000
V
DD
0.3V
DD
-
50
Unit kHz
V ns
Figure 15. Low-speed external clock source AC timing diagram tw(LSEH)
VLSEH
VLSEL
90%
10% tr(LSE)
TLSE tf(LSE) tw(LSEL) t
MS19215V2
DS9118 Rev 14
STM32F303xB STM32F303xC Electrical characteristics
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in
application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).
Symbol
Table 42. HSE oscillator characteristics
Parameter Conditions
(1)
Min
(2)
Typ Max
(2)
Unit f
OSC_IN
I
R
F
DD
Oscillator frequency
Feedback resistor
HSE current consumption
-
-
During startup
(3)
V
DD
=3.3 V, Rm= 30 Ω ,
CL=10 pF@8 MHz
V
DD
=3.3 V, Rm= 45 Ω ,
CL=10 pF@8 MHz
V
DD
=3.3 V, Rm= 30 Ω ,
CL=5 pF@32 MHz
V
DD
=3.3 V, Rm= 30 Ω ,
CL=10 pF@32 MHz
4
-
-
-
-
-
-
8
200
-
0.4
0.5
0.8
1
32
8.5
-
-
-
-
MHz k Ω mA
V
DD
=3.3 V, Rm= 30 Ω ,
CL=20 pF@32 MHz
1.5
g m t
SU(HSE)
(4)
Oscillator transconductance
Startup time
Startup
V
DD
is stabilized
10
-
-
2 -
mA/V ms
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Guaranteed by design.
3. This consumption level occurs during the first 2/3 of the t
SU(HSE)
startup time.
4. t
SU(HSE)
is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
DS9118 Rev 14
125
Electrical characteristics
Note:
STM32F303xB STM32F303xC
For C
L1
and C
L2
, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 16
). C
L1
and C
L2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C
L1
and C
L2
. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing
C
L1
and C
L2
.
For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com
.
Figure 16. Typical application with an 8 MHz crystal
Resonator with integrated capacitors
C
L1
OSC_IN f
HSE
8 MHz resonator
R
F
Bias controlled gain
R
EXT
(1) OSC_OUT
C
L2
MS19876V1
1. R
EXT
value depends on the crystal characteristics.
DS9118 Rev 14
STM32F303xB STM32F303xC Electrical characteristics
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in
application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).
Symbol
Table 43. LSE oscillator characteristics (f
LSE
= 32.768 kHz)
Parameter Conditions
(1)
Min
(2)
Typ Max
(2)
Unit
I
DD
LSE current consumption
LSEDRV[1:0]=00 lower driving capability
LSEDRV[1:0]=10 medium low driving capability
LSEDRV[1:0]=01 medium high driving capability
LSEDRV[1:0]=11 higher driving capability
LSEDRV[1:0]=00 lower driving capability
-
-
-
-
5
0.5
-
-
-
-
0.9
1
1.3
1.6
-
µA g m
Oscillator transconductance
LSEDRV[1:0]=10 medium low driving capability
LSEDRV[1:0]=01 medium high driving capability
8
15 -
-
-
-
µA/V
LSEDRV[1:0]=11 higher driving capability
25 t
SU(LSE)
(3)
Startup time V
DD
is stabilized 2 s
1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers”.
2. Guaranteed by design.
3. t
SU(LSE)
is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer.
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com
.
DS9118 Rev 14
125
Electrical characteristics STM32F303xB STM32F303xC
Figure 17. Typical application with a 32.768 kHz crystal
Resonator with integrated capacitors
C
L1
OSC32_IN f
LSE
32.768 kHz resonator
Drive programmable amplifier
OSC32_OUT
C
L2
Note:
6.3.8
MS30253V2
An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one.
Internal clock source characteristics
The parameters given in
Table 44 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 24
.
High-speed internal (HSI) RC oscillator
Symbol
Table 44. HSI oscillator characteristics
(1)
Parameter Conditions Min f
HSI
TRIM
DuCy
(HSI)
Frequency
HSI user trimming step
Duty cycle
-
-
-
-
-
45 (2)
ACC
HSI
Accuracy of the HSI oscillator
T
A
= -40 to
105°C
-2.8
(3)
T
A
= -10 to 85°C -1.9
(3)
T
A
= 0 to 85°C -1.9
(3)
T
A
= 0 to 70°C -1.3
(3)
T
A
= 0 to 55°C
T
A
= 25°C
(4)
-1 (3)
-1
1
(2)
I t su(HSI)
DDA(HSI)
HSI oscillator startup time
HSI oscillator power consumption
-
1. V
DDA
= 3.3 V, T
A
= –40 to 105 °C unless otherwise specified.
2. Guaranteed by design.
3. Guaranteed by characterization results.
4. Factory calibrated, parts not soldered.
-
Typ
-
80
8
-
-
-
-
-
-
-
-
Max
-
1
(2)
55 (2)
3.8
(3)
2.3
(3)
2
(3)
2
(3)
2 (3)
1
2
(2)
100
(2)
Unit
MHz
%
%
%
µs
µA
DS9118 Rev 14
STM32F303xB STM32F303xC Electrical characteristics
Figure 18. HSI oscillator accuracy characterization results for soldered parts
4%
MAX
MIN
3%
2%
1%
0%
-40
-1%
-2%
-3%
-4%
-20 0 20 40 60 80 100 120
MS30985V4
Low-speed internal (LSI) RC oscillator
Symbol
Table 45. LSI oscillator characteristics (1)
Parameter Min f
LSI t su(LSI)
(2)
I
DD(LSI)
(2)
Frequency 30
LSI oscillator startup time
LSI oscillator power consumption
1. V
DDA
= 3.3 V, T
A
= –40 to 105 °C unless otherwise specified.
2. Guaranteed by design.
-
-
Typ
40
-
0.75
Max
50
85
1.2
Unit kHz
µs
µA
DS9118 Rev 14
125
Electrical characteristics STM32F303xB STM32F303xC
The parameters given in
Table 46 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 24
.
Table 46. PLL characteristics
Value
Symbol Parameter
PLL input clock
(1)
PLL input clock duty cycle
PLL multiplier output clock
PLL lock time
Cycle-to-cycle jitter
Typ Max
24
(2)
60 (2)
72
200
(2)
300
(2)
Unit f
PLL_IN f
PLL_OUT t
LOCK
Jitter
Min
1
(2)
40 (2)
16
(2)
-
-
-
-
-
-
-
MHz
%
MHz
µs ps
1. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by f
PLL_OUT
.
2. Guaranteed by design.
Flash memory
The characteristics are given at T
A
= –40 to 105 °C unless otherwise specified.
Symbol
Table 47. Flash memory characteristics
Parameter Conditions t
I prog t
ERASE t
ME
DD
16-bit programming time T
A
= –40 to +105 °C
Page (2 KB) erase time T
A
= –40 to +105 °C
Mass erase time T
A
= –40 to +105 °C
Write mode
Supply current
Erase mode
1. Guaranteed by design.
Min
40
20
20
-
-
Typ Max
(1)
53.5
-
-
-
-
60
40
40
10
12
Unit
µs ms ms mA mA
Symbol
Table 48. Flash memory endurance and data retention
Value
Parameter Conditions
Min
(1)
N t
END
RET
Endurance
Data retention
T
A
= –40 to +85 °C (6 suffix versions)
T
A
= –40 to +105 °C (7 suffix versions)
1 kcycle
(2)
at T
A
= 85 °C
1 kcycle
(2)
at T
A
= 105 °C
10 kcycles
(2)
at T
A
= 55 °C
1. Guaranteed by characterization results.
2. Cycling performed over the whole temperature range.
10
30
10
20
Unit kcycles
Years
DS9118 Rev 14
STM32F303xB STM32F303xC Electrical characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:
• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB : A Burst of Fast Transient voltage (positive and negative) is applied to V
V
SS
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard.
DD
and
A device reset allows normal operations to be resumed.
The test results are given in Table 49
. They are based on the EMS levels and classes defined in the application note AN1709.
Table 49. EMS characteristics
Symbol Parameter Conditions
Level/
Class
V
FESD
V
EFTB
Voltage limits to be applied on any I/O pin to induce a functional disturbance
Fast transient voltage burst limits to be applied through 100 pF on V
DD
and V pins to induce a functional disturbance
SS
V
DD
= 3.3 V, LQFP100, T f
HCLK
A
= +25°C,
= 72 MHz conforms to IEC 61000-4-2
V
DD
= 3.3 V, LQFP100, T f
HCLK
A
= +25°C,
= 72 MHz conforms to IEC 61000-4-4
3B
4A
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
• Corrupted program counter
• Unexpected reset
• Critical Data corruption (control registers...)
DS9118 Rev 14
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Electrical characteristics STM32F303xB STM32F303xC
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 50. EMI characteristics
Symbol Parameter
S
EMI
Conditions
Monitored frequency band
Peak level
V
DD
= 3.6 V, T
A
= 25 °C,
LQFP100 package compliant with IEC
61967-2
0.1 to 30 MHz
30 to 130 MHz
130 MHz to 1GHz
SAE EMI Level
Max vs. [f
HSE
/f
HCLK
]
8/72 MHz
7
20
27
4
Unit dBµV
-
Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114, ANSI/ESD STM5.3.1
standard.
Symbol
Table 51. ESD absolute maximum ratings
Ratings Conditions Packages Class
Maximum value (1)
Unit
V
ESD(HBM)
Electrostatic discharge voltage
(human body model)
T
A
= +25 °C, conforming to ANSI/ESDA/JEDEC JS-001
V
ESD(CDM)
Electrostatic discharge voltage
(charge device model)
T
A
= +25 °C, conforming to ANSI/ESDA/JEDEC JS-002
1. Guaranteed by characterization results.
All
All
2
C2a
2000
500
V
DS9118 Rev 14
STM32F303xB STM32F303xC Electrical characteristics
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up performance:
• A supply overvoltage is applied to each power supply pin
• A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Symbol
LU
Parameter
Table 52. Electrical sensitivities
Conditions
Static latch-up class T
A
= +105 °C conforming to JESD78A
Class
II level A
As a general rule, current injection to the I/O pins, due to external voltage below V
SS above V
DD
or
(for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of –5 µA/+0 µA range), or other functional failure (for example reset occurrence or oscillator frequency deviation).
The test results are given in Table 53
.
DS9118 Rev 14
125
Electrical characteristics
Note:
STM32F303xB STM32F303xC
Symbol
I
INJ
Table 53. I/O current injection susceptibility
Functional susceptibility
Description
Negative injection
Positive injection
Unit
Injected current on BOOT0
Injected current on PC0, PC1, PC2, PC3, PF2, PA0,
PA1, PA2, PA3, PF4, PA4, PA5, PA6, PA7, PC4, PC5,
PB2 with induced leakage current on other pins from this group less than -50 µA
Injected current on PB0, PB1, PE7, PE8, PE9, PE10,
PE11, PE12, PE13, PE14, PE15, PB12, PB13, PB14,
PB15, PD8, PD9, PD10, PD11, PD12, PD13, PD14 with induced leakage current on other pins from this group less than -50 µA
Injected current on PC0, PC1, PC2, PC3, PF2, PA0,
PA1, PA2, PA3, PF4, PA4, PA5, PA6, PA7, PC4, PC5,
PB2, PB0, PB1, PE7, PE8, PE9, PE10, PE11, PE12,
PE13, PE14, PE15, PB12, PB13, PB14, PB15, PD8,
PD9, PD10, PD11, PD12, PD13, PD14 with induced leakage current on other pins from this group less than
400 µA
Injected current on any other FT and FTf pins
Injected current on any other pins
– 0
– 5
– 5
-
– 5
– 5
NA
-
-
+5
NA
+5 mA
It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.
DS9118 Rev 14
STM32F303xB STM32F303xC Electrical characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in
Table 54 are derived from tests
performed under the conditions summarized in Table 24
. All I/Os are CMOS and TTL compliant.
Symbol
V
V
IL
IH
Parameter
Low level input voltage
High level input voltage
Table 54. I/O static characteristics
Conditions
TC and TTa I/O
FT and FTf I/O
BOOT0
All I/Os except BOOT0
TC and TTa I/O
FT and FTf I/O
BOOT0
All I/Os except BOOT0
TC and TTa I/O
Min Typ
-
-
-
-
-
-
0.445 V
DD
+0.398
(1)
0.5 V
DD
+0.2
(1)
0.2 V
DD
+0.95
(1)
0.7 V
DD
(2)
-
-
-
-
-
-
-
-
200
(1)
100
(1)
300
(1)
Max
0.3 V
DD
+0.07
(1)
0.475 V
DD
-0.2 (1)
0.3 V
DD
–0.3
(1)
0.3 V
DD
(2)
-
-
-
-
-
Unit
V
V
I hys lkg
Schmitt trigger hysteresis
Input leakage current
(3)
FT and FTf I/O
BOOT0
TC, FT and FTf I/O
TTa I/O in digital mode
V
SS
≤ V
IN
≤ V
DD
TTa I/O in digital mode
V
DD
≤ V
IN
≤ V
DDA
TTa I/O in analog mode
V
SS
≤ V
IN
≤ V
DDA
FT and FTf I/O
(4)
V
DD
≤ V
IN
≤ 5 V
-
-
-
-
-
-
-
-
-
-
±0.1
1
±0.2
10 mV
µA
R
R
PU
PD
Weak pull-up equivalent resistor
(5)
Weak pull-down equivalent resistor (5)
V
V
IN
=
IN
=
V
V
SS
DD
25
25
40
40
55
55 k k
Ω
Ω
C
IO
I/O pin capacitance 5 -
1. Data based on design simulation.
2. Tested in production.
.
4. To sustain a voltage higher than V
DD
+0.3 V, the internal pull-up/pull-down resistors must be disabled.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimum (~10% order).
pF
DS9118 Rev 14
125
Electrical characteristics STM32F303xB STM32F303xC
All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 19 and Figure 20
for standard I/Os.
V
IL
/V
IH
(V)
Figure 19. TC and TTa I/O input characteristics - CMOS port
V
IHmin
2.0
1.3
Tested in production
CMOS standard requirements V
IH min = 0.7V
DD
V
IHmin
= 0.445V
DD
+0.398
Based on design simulations
DD
+0.07
V
ILmax
= 0.3V
Based on design simulations
Area not determined
CMOS standard requirements V IL max = 0.3V
DD
V
ILmax
0.7
0.6
Tested in production
V
DD
(V)
2.0
2.7
3.0
3.3
3.6
MS30255V2
V
IL
/V
IH
(V)
Figure 20. TC and TTa I/O input characteristics - TTL port
V
IHmin
2.0
1.3
Area not determined
TTL standard requirements V IH min = 2V
V
IHmin
= 0.445V
DD
+0.398
Based on design simulations
V
ILmax
= 0.3V
DD
+0.07
Based on design simulations
V
ILmax
0.8
0.7
2.0
2.7
TTL standard requirements V IL max = 0.8V
V
DD
(V)
3.0
3.3
3.6
MS30256V2
DS9118 Rev 14
STM32F303xB STM32F303xC Electrical characteristics
Figure 21. Five volt tolerant (FT and FTf) I/O input characteristics - CMOS port
V
IL
/V
IH
(V)
2.0
1.0
0.5
2.0
Area not determined
IH min = 0.7V
DD
CMOS standard requirements V
V
IHmin
= 0.5V
DD
+0.2
Based on design simulations
DD
-0.2
V
ILmax
= 0.475V
Based on design simulations
CMOS standard requirements V
IL max = 0.3V
DD
V
DD
(V)
2.7
3.6
MS30257V3
Figure 22. Five volt tolerant (FT and FTf) I/O input characteristics - TTL port
V
IL
/V
IH
(V)
2.0
1.0
0.8
0.5
TTL standard requirements V IH min = 2V
V
IHmin
= 0.5V
DD
+0.2
Based on design simulations
Area not determined
V
ILmin
= 0.475V
DD
-0.2
Based on design simulations
TTL standard requirements V IL max = 0.8V
V
DD
(V)
2.0
2.7
3.6
MS30258V2
DS9118 Rev 14
125
Electrical characteristics STM32F303xB STM32F303xC
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or source up to +/- 20 mA (with a relaxed V
OL/
V
OH
).
In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in
:
• The sum of the currents sourced by all the I/Os on V
DD, consumption of the MCU sourced on V
DD,
Σ I
VDD
plus the maximum Run cannot exceed the absolute maximum rating
• The sum of the currents sunk by all the I/Os on V
SS consumption of the MCU sunk on V
Σ I
VSS
(see
SS
plus the maximum Run
cannot exceed the absolute maximum rating
Output voltage levels
Unless otherwise specified, the parameters given in
Table 55 are derived from tests
performed under ambient temperature and V
DD
supply voltage conditions summarized in
Table 24 . All I/Os (FT, TTa and TC unless otherwise specified) are CMOS and TTL
compliant.
Symbol
Table 55. Output voltage characteristics
Parameter Conditions Min Max Unit
V
V
V
V
OL
(1)
OH
(3)
OL
(1)
OH
(3)
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
CMOS port
(2)
I
IO
= +8 mA
2.7 V < V
DD
< 3.6 V
TTL port (2)
I
IO
= +8 mA
2.7 V < V
DD
< 3.6 V
V
DD
-
-
–0.4
2.4
0.4
-
-
0.4
V
OL
(1)(4)
V
OH
(3)(4)
V
OL
(1)(4)
V
OH
(3)(4)
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
I
IO
= +20 mA
2.7 V < V
DD
I
IO
2 V < V
DD
< 3.6 V
= +6 mA
< 2.7 V
V
DD
-
-
–1.3
V
DD
–0.4
1.3
-
-
0.4
V
OLFM+
(1)(4)
Output low level voltage for an FTf I/O pin in
FM+ mode
I
IO
= +20 mA
2.7 V < V
DD
< 3.6 V
0.4
1. The I
I
IO
IO
(I/O ports and control pins) must not exceed Σ I
IO(PIN)
.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. The I of I
IO
IO
(I/O ports and control pins) must not exceed Σ I
IO(PIN)
.
4. Data based on design simulation.
V
DS9118 Rev 14
STM32F303xB STM32F303xC Electrical characteristics
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in
and
Unless otherwise specified, the parameters given are derived from tests performed under ambient temperature and V
DD
supply voltage conditions summarized in Table 24
.
Table 56. I/O AC characteristics (1)
OSPEEDRy [1:0] value
(1)
Symbol Parameter Conditions Min Max Unit x0
01 f max(IO)out t f(IO)out t r(IO)out f max(IO)out t f(IO)out t r(IO)out
Maximum frequency (2)
Output high to low level fall time
Output low to high level rise time
Maximum frequency
(2)
Output high to low level fall time
Output low to high level rise time
C
L
C
L
C
L
C
L
= 50 pF, V
= 50 pF, V
= 50 pF, V
= 50 pF, V
DD
= 2 V to 3.6 V
DD
= 2 V to 3.6 V
DD
= 2 V to 3.6 V
DD
= 2 V to 3.6 V
-
-
-
-
-
-
2 (3)
125
(3)
125
(3)
10
(3)
25
(3)
25
(3)
MHz ns
MHz ns
11 f max(IO)out t t f(IO)out r(IO)out
Maximum frequency
Output high to low level fall time
Output low to high level rise time
(2)
C
L
= 30 pF, V
DD
= 2.7 V to 3.6 V
C
L
= 50 pF, V
DD
= 2.7 V to 3.6 V
C
L
= 50 pF, V
DD
= 2 V to 2.7 V
C
L
= 30 pF, V
DD
= 2.7 V to 3.6 V
C
L
= 50 pF, V
DD
= 2.7 V to 3.6 V
C
L
= 50 pF, V
DD
= 2 V to 2.7 V
C
L
= 30 pF, V
DD
= 2.7 V to 3.6 V
C
L
= 50 pF, V
DD
= 2.7 V to 3.6 V
C
L
= 50 pF, V
DD
= 2 V to 2.7 V
-
-
-
-
-
-
-
-
-
-
FM+ configuration
-
(4) f max(IO)out t t t f(IO)out r(IO)out
EXTIpw
Maximum frequency
(2)
Output high to low level fall time
Output low to high level rise time
Pulse width of external signals detected by the
EXTI controller
C
L
= 50 pF, V
DD
= 2 V to 3.6 V
10
-
-
(3)
12
34
-
1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the RM0316 reference manual for a description of
GPIO Port configuration register.
2. The maximum frequency is defined in Figure 23 .
3. Guaranteed by design.
4. The I/O speed configuration is bypassed in FM+ I/O mode. Refer to the STM32F303x STM32F313xx reference manual
RM0316 for a description of FM+ I/O mode configuration.
50
(3)
30
(3)
20 (3)
5
(3)
8
(3)
12
(3)
5
(3)
8
(3)
12 (3)
2
MHz
MHz
MHz ns
MHz ns ns
DS9118 Rev 14
125
Electrical characteristics STM32F303xB STM32F303xC
Figure 23. I/O AC characteristics definition
10%
50%
90% 10%
50%
90%
EXTERNAL
OUTPUT
ON 50pF tr(IO)out
T tf(IO)out
Maximum frequency is achieved if (tr + tf) ≤ 2/3)T and if the duty cycle is (45-55%) when loaded by 50pF ai14131c
6.3.15 NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, R
PU
(see
Unless otherwise specified, the parameters given in
Table 57 are derived from tests
performed under ambient temperature and V
DD
supply voltage conditions summarized in
Symbol
Table 57. NRST pin characteristics
Parameter Conditions Min Typ Max
V
IL(NRST)
(1)
NRST Input low level voltage -
0.3V
0.07
+
V
IH(NRST)
(1)
NRST Input high level voltage -
0.445V
0.398
+
-
V hys(NRST)
R
PU
V
F(NRST)
(1)
V
NF(NRST)
(1)
NRST Schmitt trigger voltage hysteresis
Weak pull-up equivalent resistor
(2)
NRST Input filtered pulse
NRST Input not filtered pulse
V
IN
= V
SS
-
-
-
25
-
500
(1)
200
40
-
-
55
100
(1)
-
-
1. Guaranteed by design.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order)
.
Unit
V mV k Ω ns ns
DS9118 Rev 14
STM32F303xB STM32F303xC Electrical characteristics
Figure 24. Recommended NRST pin protection
External reset circuitry
(1)
0.1 μF
NRST
(2)
V
DD
R
PU
Filter
Internal reset
MS19878V1
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the V
Table 57 . Otherwise the reset will not be taken into account by the device.
max level specified in
The parameters given in
Table 58 are guaranteed by design.
Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Symbol
Table 58. TIMx (1)(2) characteristics
Parameter Conditions Min Max Unit t t res(TIM) f
EXT
Res
TIM
COUNTER
Timer resolution time
Timer external clock frequency on CH1 to CH4
Timer resolution
-
f
TIMxCLK
= 72 MHz f
TIMxCLK
= 144 MHz x=1.8
TIM2
f
TIMxCLK
= 72 MHz
TIMx (except TIM2)
1
13.9
6.95
1
16-bit counter clock period
f
TIMxCLK
= 72 MHz 0.0139
f
TIMxCLK
= 144 MHz x=1.8
0.0069
0
0
-
-
-
-
f
TIMxCLK
36
16
32
65536
910
455
/2 t t
TIMxCLK ns ns
MHz
MHz bit
TIMxCLK
µs
µs t
MAX_COUNT
Maximum possible count with 32-bit counter
f
TIMxCLK
= 72 MHz f
TIMxCLK
= 144 MHz x=1.8
-
-
-
65536 × 65536 t
59.65
29.825
TIMxCLK
1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3, TIM4, TIM8, TIM15, TIM16 and TIM17 timers.
2. Guaranteed by design.
s s
DS9118 Rev 14
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Electrical characteristics STM32F303xB STM32F303xC
Table 59. IWDG min/max timeout period at 40 kHz (LSI) (1)
Prescaler divider PR[2:0] bits
Min timeout (ms) RL[11:0]=
0x000
Max timeout (ms) RL[11:0]=
0xFFF
/4
/8
/16
/32
/64
/128
/256
0
1
2
3
4
5
7
0.1
0.2
0.4
0.8
1.6
3.2
6.4
409.6
819.2
1638.4
3276.8
6553.6
13107.2
26214.4
1. These timings are given for a 40 kHz clock but the microcontroller’s internal RC frequency can vary from 30 to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.
Prescaler
Table 60. WWDG min-max timeout value @72 MHz (PCLK)
(1)
WDGTB Min timeout value Max timeout value
1
2
4
8
1. Guaranteed by design.
0
1
2
3
0.05687 3.6409
0.1137 7.2817
0.2275 14.564
0.4551 29.127
DS9118 Rev 14
STM32F303xB STM32F303xC Electrical characteristics
I
2
C interface characteristics
The I
2
C interface meets the timings requirements of the I
2
C-bus specification and user manual rev.03 for:
• Standard-mode (Sm) : with a bit rate up to 100 Kbits/s
• Fast-mode (Fm) : with a bit rate up to 400 Kbits/s
• Fast-mode Plus (Fm+) : with a bit rate up to 1Mbits/s
The I
2
C timings requirements are guaranteed by design when the I
2
C peripheral is properly configured (refer to Reference manual).
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDDIOx is disabled, but is still present. Only FTf I/O pins support
Fm+ low level output current maximum requirement. Refer to
Section 6.3.14: I/O port characteristics .
All I
2
C I/Os embed an analog filter. refer to the
Table 62: I2C analog filter characteristics .
Symbol
Table 61. I2C timings specification (see I2C specification, rev.03, June 2007)
(1)
Standard mode Fast mode Fast Mode Plus
Parameter
Min Max Min Max Min Max t f
SCL t
LOW t
HIGH
SCL clock frequency
Low period of the SCL clock t r
High Period of the SCL clock
Rise time of both SDA and SCL signals t f
Fall time of both SDA and SCL signals t
HD;DAT
Data hold time t
VD;DAT
Data valid time t
VD;ACK
Data valid acknowledge time t t
SU;DAT
Data setup time
HD:STA
Hold time (repeated) START condition t
SU:STA
SU:STO t t
BUF
C b
SP
Set-up time for a repeated START condition
Set-up time for STOP condition
Bus free time between a
STOP and START condition
Capacitive load for each bus line
Pulse width of spikes that are suppressed by the analog filter for
Standard and Fast mode
0
4.7
4
-
-
0
-
-
250
4.0
4.7
4.0
4.7
-
0
100
-
1000
300
-
3.45
(2)
3.45
(2)
-
-
-
-
-
400
50
(3)
0
1.3
0.6
-
-
0
-
-
100
0.6
0.6
0.6
1.3
-
0
400
-
300
300
-
0.9
(2)
0.9
(2)
-
-
-
-
-
400
50
(3)
0
0.5
0.26
-
-
0
-
-
50
0.26
0.26
0.26
0.5
-
-
1000 KHz
µs
µs
120
120
-
0.45
(2)
0.45
(2)
-
550
-
-
-
-
Unit ns ns
µs
µs
µs
µs pF ns
µs
µs
µs ns
DS9118 Rev 14
125
Electrical characteristics STM32F303xB STM32F303xC
1. The I2C characteristics are the requirements from I2C bus specification rev03. They are guaranteed by design when
I2Cx_TIMING register is correctly programmed (Refer to the RM0316 reference manual).
2. The maximum tHD;DAT could be 3.45 µs, 0.9 µs and 0.45 µs for standard mode, fast mode and fast mode plus, but must be less than the maximum of tVD;DAT or tVD;ACK by a transition time.
3. The minimum width of the spikes filtered by the analog filter is above t
SP
(max).
Symbol
Table 62. I2C analog filter characteristics
(1)
Parameter t
AF
Pulse width of spikes that are suppressed by the analog filter
1. Guaranteed by design.
Min
50
Max
260
Figure 25. I 2 C bus AC waveforms and measurement circuit
Unit ns
VDD_I2C VDD_I2C
Rp Rp MCU
I2C bus
Rs
Rs
SDA
SCL t f t r
SDA
SCL
70%
30%
SDA t
SU;STA t f t
HD;STA
S
70%
30%
1 / f
SCL
1st clock cycle
70%
30% t
70%
30% t
HD;DAT
HD;STA t
SP
SCL
S r t
SU;DAT t r
70%
30% t
LOW t
VD;ACK
9th clock t
HIGH t
SU;STO
70%
30%
P t
VD;DAT t
BUF
S
1. Rs: Series protection resistors, Rp: Pull-up resistors, VDD_I2C: I2C bus supply.
continued
9th clock continued
MS19879V3
DS9118 Rev 14
STM32F303xB STM32F303xC Electrical characteristics
SPI/I
2
S characteristics
Unless otherwise specified, the parameters given in
2 S are derived from tests performed under ambient temperature, f
PCLKx
supply voltage conditions summarized in Table 24
.
frequency and V
DD
Refer to Section 6.3.14: I/O port characteristics
for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I 2 S).
Symbol Parameter
Table 63. SPI characteristics (1)
Conditions
1/t f
SCK c(SCK)
SPI clock frequency
Master mode, SPI1
2.7<V
DD
<3.6
Slave mode, SPI1
2.7<V
DD
<3.6
Master mode, SPI1/2/3
2<V
DD
<3.6
Slave mode, SPI1/2/3
2<V
DD
<3.6
DuCy(
SCK
) Duty cycle of SPI clock frequency Slave mode t su(NSS) t h(NSS) t w(SCKH) t w(SCKL) t su(MI) t su(SI) t h(MI) t h(SI) t a(SO) t dis(SO)
NSS setup time
NSS hold time
SCK high and low time
Data input setup time
Data input hold time
Data output access time
Data output disable time
Slave mode, SPI presc = 2
Slave mode, SPI presc = 2
Master mode
Master mode
Slave mode
Master mode
Slave mode
Slave mode
Slave mode
Slave mode t v(SO)
Data output valid time
Slave mode, SPI1
2.7<V
DD
<3.6V
Master mode t v(MO) t h(SO) t h(MO)
Data output hold time
1. Guaranteed by characterization results.
Slave mode
Master mode
Min
30
4*Tpclk
2*Tpclk
5.5
6.5
5
5
0
0
-
-
11
0
-
-
-
-
-
-
12
1.5
-
-
50
-
-
-
-
-
-
4*Tpclk
24
27
3
-
-
70
-
-
Tpclk-2 Tpclk Tpclk+2
-
-
Typ
-
12
Max
24
24
18
18
18
Unit
MHz
% ns
DS9118 Rev 14
125
Electrical characteristics STM32F303xB STM32F303xC
Figure 26. SPI timing diagram - slave mode and CPHA = 0
Figure 27. SPI timing diagram - slave mode and CPHA = 1 (1)
NSS input t
SU(NSS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1 t w(SCKH) t w(SCKL) t c(SCK) t h(NSS)
MISO
OUTPUT
MOSI
INPUT t a(SO) t su(SI) t v(SO)
MSB OUT t h(SI)
MSB IN t h(SO)
BIT6 OUT
BIT 1 IN t r(SCK) t f(SCK) t dis(SO)
LSB OUT
LSB IN
1. Measurement points are done at 0.5V
DD
and with external C
L
= 30 pF.
ai14135b
DS9118 Rev 14
STM32F303xB STM32F303xC
Figure 28. SPI timing diagram - master mode (1)
Electrical characteristics
NSS input
High tc(SCK)
CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
MISO
INP UT
MOSI
OUTPUT tsu(MI) tw(SCKH) tw(SCKL)
MSB IN th(MI)
MSB OUT tv(MO)
BIT6 IN
B I T1 OUT th(MO)
1. Measurement points are done at 0.5V
DD
and with external C
L
= 30 pF.
tr(SCK) tf(SCK)
LSB IN
LSB OUT ai14136c
DS9118 Rev 14
125
Electrical characteristics STM32F303xB STM32F303xC
Symbol f
CK
1/t c(CK) t r(CK) t f(CK) t w(CKH) t w(CKL) t v(WS) t h(WS) t su(WS) t h(WS)
Duty Cycle t su(SD_MR) t su(SD_SR) t h(SD_MR) t h(SD_SR) t v(SD_ST) t h(SD_ST) t v(SD_MT) t h(SD_MT)
Table 64. I 2 S characteristics (1)
Parameter Conditions
I
2
S clock frequency
I 2 S clock rise and fall time
I
2
S clock high time
I
2
S clock low time
WS valid time
WS hold time
WS setup time
WS hold time
I
2
S slave input clock duty cycle
Data input setup time
Data input setup time
Master data: 16 bits, audio freq=48 kHz
Slave
Capacitive load
C
L
= 30 pF
Master f
PCLK
= 36 MHz, audio frequency =
48 kHz
Master mode
Master mode
Slave mode
Slave mode
Slave mode
Data input hold time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
Master receiver
Slave receiver
Master receiver
Slave receiver
Slave transmitter
(after enable edge)
Slave transmitter
(after enable edge)
Master transmitter
(after enable edge)
Master transmitter
(after enable edge)
1. Guaranteed by characterization results.
Min
1.496
0
-
331
332
4
0
4
4
30
0
0
9
2
-
12
-
2
Max
1.503
12.288
8
-
-
-
-
-
-
70
-
-
-
-
29
Unit
MHz ns
% ns
-
3
-
DS9118 Rev 14
STM32F303xB STM32F303xC Electrical characteristics
Figure 29. I 2 S slave timing diagram (Philips protocol) (1)
1. Measurement points are done at 0.5V
DD
and with external C
L
=30 pF.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.
Figure 30. I 2 S master timing diagram (Philips protocol) (1)
1. Measurement points are done at 0.5V
DD
and with external C
L
=30 pF.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.
DS9118 Rev 14
125
Electrical characteristics STM32F303xB STM32F303xC
USB characteristics
Table 65. USB startup time
Symbol Parameter t
STARTUP
(1)
USB transceiver startup time
1. Guaranteed by design.
Symbol
Max
1
Table 66. USB DC electrical characteristics
Parameter Conditions Min.
(1)
Unit
µs
Max.
(1)
Unit
Input levels
V
DD
V
DI
(4)
V
CM
(4)
V
SE
(4)
USB operating voltage
(2)
Differential input sensitivity
Differential common mode range
Single ended receiver threshold
Output levels
-
I(USB_DP, USB_DM)
Includes V
DI range
-
3.0
(3)
0.2
0.8
1.3
3.6
-
2.5
2.0
V
V
V
OL
V
OH
Static output level low
Static output level high
R
L
of 1.5
k Ω to 3.6 V (5)
R
L
of 15 k Ω to V
SS
(5)
-
2.8
0.3
3.6
1. All the voltages are measured from the local ground potential.
2. To be compliant with the USB 2.0 full-speed electrical specification, the USB_DP (D+) pin should be pulled up with a 1.5 k Ω resistor to a 3.0-to-3.6 V voltage range.
3. The STM32F303xB/STM32F303xC USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics which are degraded in the 2.7-to-3.0 V V
DD
voltage range.
4. Guaranteed by design.
5. R
L
is the load connected on the USB drivers.
V
Figure 31. USB timings: definition of data signal rise and fall time
Cross over points
Differential data lines
V
CRS
V
SS t f t r ai14137b
DS9118 Rev 14
STM32F303xB STM32F303xC Electrical characteristics
Symbol
Table 67. USB: Full-speed electrical characteristics (1)
Parameter Conditions Min Typ Max Unit
Driver characteristics t r t f t rfm
V
CRS
Output driver
Impedance
(3)
Rise time
Fall time
(2)
(2)
Rise/ fall time matching
Output signal crossover voltage
Z
DRV
C
L
C
L
= 50 pF
= 50 pF t r
-
/t f driving high and low
4
4
90
1.3
28
-
-
-
-
40
20
20
110
2.0
44 Ω
1. Guaranteed by design.
2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter
7 (version 2.0).
3. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-), the matching impedance is already included in the embedded driver.
ns ns
%
V
CAN (controller area network) interface
Refer to Section 6.3.14: I/O port characteristics
for more details on the input/output alternate function characteristics (CAN_TX and CAN_RX).
DS9118 Rev 14
125
Symbol
V
DDA
I
DDA
V
REF+
V
REF-
I
REF
Unless otherwise specified, the parameters given in Table 68
are guaranteed by design, with conditions summarized in
Parameter
Analog supply voltage for ADC
ADC current consumption on VDDA pin
)
Positive reference voltage
Negative reference voltage
ADC current consumption on VREF+ pin
)
Table 68. ADC characteristics
Conditions Min
-
Single-ended mode,
5 MSPS
Single-ended mode,
1 MSPS
Single-ended mode,
200 KSPS
Differential mode,
5 MSPS
Differential mode,
1 MSPS
Differential mode,
200 KSPS
-
-
Single-ended mode,
5 MSPS
Single-ended mode,
1 MSPS
Single-ended mode,
200 KSPS
Differential mode,
5 MSPS
Differential mode,
1 MSPS
Differential mode,
200 KSPS
2
2
-
-
-
-
-
-
-
-
-
-
-
-
-
Typ
-
907
194
51.5
887.5
212
51
-
0
104
20.4
3.3
174
34.6
6
Max
3.6
1033.0
285.5
70
1009
285
69.5
V
DDA
-
139
37
11.3
235
52.6
13.6
Unit
V
µA
V
µA
f
TRIG
(1)
V
AIN
R
AIN
(1)
C
ADC
(1) t
STAB
(1) t
CAL
(1)
Symbol f
ADC f
S
(1) t latr
(1) t latrinj
(1)
Parameter
ADC clock frequency
Sampling rate
External trigger frequency
Conversion voltage range
(2)
External input impedance
Internal sample and hold capacitor
Table 68. ADC characteristics (continued)
Conditions Min
-
Resolution = 12 bits,
Fast Channel
Resolution = 10 bits,
Fast Channel
Resolution = 8 bits,
Fast Channel
Resolution = 6 bits,
Fast Channel
f
ADC
= 72 MHz
Resolution = 12 bits
Resolution = 12 bits
-
-
-
0.14
0.01
0.012
0.014
0.0175
-
-
-
-
0
Power-up time
Calibration time
Trigger conversion latency
Regular and injected channels without conversion abort
Trigger conversion latency
Injected channels aborting a regular conversion
f
ADC
= 72 MHz
-
CKMODE = 00
CKMODE = 01
CKMODE = 10
CKMODE = 11
CKMODE = 00
CKMODE = 01
CKMODE = 10
CKMODE = 11
2.5
-
-
-
1.5
-
-
-
-
-
Typ
-
-
-
-
-
5
-
-
1
3
-
-
-
1.56
112
2
-
-
-
2.5
2
2.25
2.125
3.5
3
3.25
3.125
Max
72
5.14
6
7.2
9
5.14
14
V
REF+
100
-
Unit
MHz
MSPS
MHz
1/f
ADC
V k Ω pF conversion cycle
µs
1/f
ADC
1/f
ADC
1/f
ADC
1/f
ADC
1/f
ADC
1/f
ADC
1/f
ADC
1/f
ADC
1/f
ADC
Symbol Parameter
Table 68. ADC characteristics (continued)
Conditions Min Typ Max Unit
T t
S
(1)
ADCVREG_STUP
(1)
Sampling time
ADC Voltage Regulator Start-up time f
ADC
= 72 MHz
-
f
ADC
= 72 MHz
Resolution = 12 bits
0.021
1.5
-
0.19
-
-
-
-
8.35
601.5
10
8.52
µs
1/f
ADC
µs
µs t
CONV
(1)
CMIR
(1)
Total conversion time (including sampling time)
Common Mode Input signal Range
Resolution = 12 bits
ADC differential mode
14 to 614 (t
S
for sampling + 12.5 for successive approximation)
(V
SSA
+V
REF+
-10%
)/2
(V
SSA
+V
REF+
)/2
(V
SSA
+V
REF+
+ 10%
)/2
1/f
ADC
V
1. Data guaranteed by design.
2. V can be internally connected to V further details.
DDA
and V
REF-
can be internally connected to V
SSA
, depending on the package. Refer to Section 4: Pinouts and pin description for
STM32F303xB STM32F303xC Electrical characteristics
Figure 32. ADC typical current consumption on VDDA pin
1000
900
800
700
600
500
400
300
200
100
0
Single-ended mode
Differential mode
5 1 0.2
Clock frequency (MSPS)
Figure 33. ADC typical current consumption on VREF+ pin
MS36607V1
200
180
160
140
120
100
80
60
40
20
0
Single-ended mode
Differential mode
5 1
Clock frequency (MSPS)
0.2
MS36606V1
DS9118 Rev 14
125
Electrical characteristics STM32F303xB STM32F303xC
Resolution
Sampling cycle @
72 MHz
12 bits
10 bits
8 bits
6 bits
601.5
1.5
2.5
4.5
7.5
19.5
61.5
181.5
601.5
601.5
1.5
2.5
4.5
7.5
19.5
61.5
181.5
1.5
2.5
4.5
7.5
19.5
61.5
181.5
1.5
2.5
4.5
7.5
19.5
61.5
181.5
601.5
1. Guaranteed by characterization results.
2. All fast channels, expect channels on PA2, PA6, PB1, PB12.
8354.17
20.83
34.72
62.50
104.17
270.83
854.17
2520.83
8354.17
8354.17
20.83
34.72
62.50
104.17
270.83
854.17
2520.83
20.83
34.72
62.50
104.17
270.83
854.17
2520.83
20.83
34.72
62.50
104.17
270.83
854.17
2520.83
8354.17
Table 69. Maximum ADC R
AIN
(1)
Sampling time [ns] @
72 MHz Fast channels
(2)
R
AIN
max (k Ω )
Slow channels
100.00
0.100
0.390
0.820
1.80
4.70
15.0
47.0
100.0
82.0
NA
0.180
0.560
1.20
3.30
12.00
33.00
NA
0.082
0.390
0.82
2.70
8.2
27.0
NA
NA
0.220
0.560
1.80
6.80
18.0
68.0
100.00
0.270
0.560
1.200
2.20
5.60
18.0
56.0
100.00
100.0
0.150
0.390
0.820
1.50
3.90
12.00
39.00
0.082
0.270
0.560
1.20
3.30
10.0
33.0
0.018
0.150
0.470
0.820
2.70
8.20
22.0
82.0
Other channels
(3)
82.00
0.150
0.330
0.820
1.50
3.90
12.0
39.0
100.0
68.0
0.039
0.180
0.470
1.00
2.70
8.20
27.00
NA
0.100
0.330
0.68
2.20
6.8
22.0
NA
0.022
0.180
0.470
1.50
4.70
15.0
47.0
DS9118 Rev 14
STM32F303xB STM32F303xC Electrical characteristics
3. Channels available on PA2, PA6, PB1, PB12.
Table 70. ADC accuracy - limited test conditions, 100-pin packages
(1)(2)
Symbol Parameter Conditions
Min
(3)
Typ
Max
(3)
Unit
ET
EO
EG
ED
EL
ENOB
(4)
SINAD
(4)
Total unadjusted error
Offset error
Gain error
Differential linearity error
Integral linearity error
Effective number of bits
Signal-tonoise and distortion ratio
ADC clock freq. ≤
Sampling freq. ≤
V
DDA
= V
REF+
= 3.3 V
25°C
100-pin package
Single ended
Differential
Single ended
Differential
Single ended
Differential
Single ended
Differential
Single ended
Differential
Single ended
Differential
Single ended
Differential
Fast channel 5.1 Ms - ± 3.5
± 4.5
Slow channel 4.8 Ms - ± 4 ± 4.5
Fast channel 5.1 Ms - ± 3 ± 3
Slow channel 4.8 Ms - ± 3 ± 3
Fast channel 5.1 Ms - ± 1 ± 1.5
Slow channel 4.8 Ms - ± 1 ± 2.5
Fast channel 5.1 Ms - ± 1 ± 1.5
Slow channel 4.8 Ms - ± 1 ± 1.5
Fast channel 5.1 Ms - ± 3 ± 4
Slow channel 4.8 Ms - ± 3.5
± 4
Fast channel 5.1 Ms - ± 1.5
± 2.5
Slow channel 4.8 Ms - ± 2 ± 2.5
Fast channel 5.1 Ms - ± 1 ± 1.5
Slow channel 4.8 Ms - ± 1 ± 1.5
Fast channel 5.1 Ms - ± 1 ± 1
Slow channel 4.8 Ms - ± 1 ± 1
Fast channel 5.1 Ms - ± 1.5
± 2
Slow channel 4.8 Ms - ± 1.5
± 3
Fast channel 5.1 Ms - ± 1 ± 1.5
Slow channel 4.8 Ms - ± 1 ± 1.5
Fast channel 5.1 Ms 10.7 10.8
-
Slow channel 4.8 Ms 10.7 10.8
-
Fast channel 5.1 Ms 11.2 11.3
-
Slow channel 4.8 Ms 11.1 11.3
-
Fast channel 5.1 Ms 66 67
Slow channel 4.8 Ms 66 67 -
-
Fast channel 5.1 Ms 69 70
Slow channel 4.8 Ms 69 70 -
-
LSB bits dB
DS9118 Rev 14
125
Electrical characteristics STM32F303xB STM32F303xC
Table 70. ADC accuracy - limited test conditions, 100-pin packages (1)(2) (continued)
Symbol Parameter Conditions
Min
(3)
Typ
Max
(3)
Unit
SNR
THD
(4)
(4)
Signal-tonoise ratio
Total harmonic distortion
ADC clock freq. ≤ 72 MHz
Sampling freq ≤ 5 Msps
V
DDA
= V
REF+
= 3.3 V
25°C
100-pin package
Single ended
Differential
Single ended
Differential
Fast channel 5.1 Ms 66 67
Slow channel 4.8 Ms 66 67
Fast channel 5.1 Ms 69 70
Slow channel 4.8 Ms 69 70
Fast channel 5.1 Ms -76
-
-76
Slow channel 4.8 Ms - -76 -76
Fast channel 5.1 Ms -80 -80
Slow channel 4.8 Ms - -80 -80
-
-
- dB
1. ADC DC accuracy values are measured after internal calibration.
2. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for I accuracy.
INJ(PIN)
and Σ I
INJ(PIN)
in
does not affect the ADC
3. Guaranteed by characterization results.
4. Value measured with a -0.5 dB full scale 50 kHz sine wave input signal.
DS9118 Rev 14
STM32F303xB STM32F303xC Electrical characteristics
Symbol Parameter
ET
EO Offset error
EL
ENOB
(5)
Total unadjusted error
Integral linearity error
Effective number of bits
Table 71. ADC accuracy, 100-pin packages (1)(2)(3)
EG Gain error
ED
Differential linearity error
ADC clock freq. ≤ 72 MHz,
Sampling freq. ≤ 5 Msps
2 V ≤ V
DDA
, V
REF+
≤ 3.6 V
100-pin package
Conditions
Single
Ended
Differential
Single
Ended
Differential
Single
Ended
Differential
Single
Ended
Differential
Single
Ended
Differential
Single
Ended
Differential
Min
(4)
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms 10.4
Slow channel 4.8 Ms 10.2
Fast channel 5.1 Ms 10.8
Slow channel 4.8 Ms 10.8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max
(4)
± 3
± 3
± 1.5
± 1.5
± 2
± 6
± 6
± 4
± 3
± 3
± 2
± 6.5
± 6.5
± 4
± 1.5
± 1.5
± 2
± 3
± 2
± 2
-
-
-
-
Unit
LSB bits
DS9118 Rev 14
125
Electrical characteristics STM32F303xB STM32F303xC
Symbol Parameter
Table 71. ADC accuracy, 100-pin packages (1)(2)(3) (continued)
Conditions Min (4) Max (4) Unit
SINAD
(5)
SNR
THD
(5)
(5)
Signal-tonoise and distortion ratio
Signal-tonoise ratio
Total harmonic distortion
ADC clock freq. ≤ 72 MHz,
Sampling freq. ≤ 5 Msps,
2 V ≤ V
DDA
, V
REF+
≤ 3.6 V
100-pin package
Single
Ended
Differential
Single
Ended
Differential
Single
Ended
Differential
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
64
63
67
67
64
64
67
67
-
-
-
- dB
1. ADC DC accuracy values are measured after internal calibration.
2. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for I accuracy.
INJ(PIN)
and Σ I
INJ(PIN)
in
does not affect the ADC
3. Better performance may be achieved in restricted V
DDA
, frequency and temperature ranges.
4. Guaranteed by characterization results.
5. Value measured with a -0.5 dB full scale 50 kHz sine wave input signal.
-
-
-
-
-
-
-
-
-74
-74
-78
-76
DS9118 Rev 14
STM32F303xB STM32F303xC Electrical characteristics
Table 72. ADC accuracy - limited test conditions, 64-pin packages (1)(2)
Symbol Parameter Conditions
Min
(3)
Typ
Max
(3)
Unit
ET
EO
EG
ED
EL
ENOB
(4)
SINAD
(4)
Total unadjusted error
Offset error
Gain error
Differential linearity error
Integral linearity error
Effective number of bits
Signal-tonoise and distortion ratio
ADC clock freq. ≤
Sampling freq. ≤
V
DDA
= 3.3 V
25°C
64-pin package
Fast channel 5.1 Ms
Single ended
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Differential
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Single ended
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Differential
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Single ended
Slow channel 4.8 Ms
Differential
-
-
-
-
-
±4
±1.5
±3
±4.5
±5.5
±6
±3.5
±4
±2
±4
Differential
Single ended
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Differential
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Single ended
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Differential
Single ended
-
-
-
-
-
-
-
-
±5 ±5.5
LSB
±3
±3 ±3.5
±1 ±1
±1
±1
±1
±1.5
±2
±3
±1
±1
±1
±2
±3
±1.5 ±1.5
Slow channel 4.8 Ms ±1.5
±2
Fast channel 5.1 Ms 10.8 10.8
-
Slow channel 4.8 Ms 10.8 10.8
-
Fast channel 5.1 Ms 11.2 11.3
bit
Slow channel 4.8 Ms 11.2 11.3
-
Fast channel 5.1 Ms 66 67 -
Single ended
-
±3.5
±4
±2 ±2
±1.5
±2
±1.5
±2
Slow channel 4.8 Ms 66 67
Fast channel 5.1 Ms 69 70 -
dB
Differential
Slow channel 4.8 Ms 69 70 -
DS9118 Rev 14
125
Electrical characteristics STM32F303xB STM32F303xC
Table 72. ADC accuracy - limited test conditions, 64-pin packages (1)(2) (continued)
Symbol Parameter Conditions
Min
(3)
Typ
Max
(3)
Unit
SNR
THD
(4)
(4)
Signal-tonoise ratio
Total harmonic distortion
ADC clock freq. ≤ 72 MHz
Sampling freq ≤ 5 Msps
V
DDA
= 3.3 V
25°C
64-pin package
Single ended
Fast channel 5.1 Ms 66 67
Slow channel 4.8 Ms 66 67
Fast channel 5.1 Ms 69 70
Differential
-
Slow channel 4.8 Ms 69 70
Fast channel 5.1 Ms -80
-
-80
Single ended
-
-
Slow channel 4.8 Ms
Fast channel 5.1 Ms -
-78 -77
-83 -82
Differential
Slow channel 4.8 Ms -81 -80 dB
1. ADC DC accuracy values are measured after internal calibration.
2. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for I accuracy.
INJ(PIN)
and Σ I
INJ(PIN)
in
3. Guaranteed by characterization results.
4. Value measured with a -0.5 dB full scale 50 kHz sine wave input signal.
DS9118 Rev 14
STM32F303xB STM32F303xC Electrical characteristics
Symbol Parameter
Table 73. ADC accuracy, 64-pin packages (1)(2)(3)
Conditions Min
(4)
ET
EO
EG
ED
EL
ENOB
(5)
SINAD
(5)
Total unadjusted error
Offset error
Gain error
Differential linearity error
Integral linearity error
Effective number of bits
Signal-tonoise and distortion ratio
Fast channel 5.1 Ms
Single ended
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Differential
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Single ended
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Differential
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Single ended
Slow channel 4.8 Ms
Differential
ADC clock freq. ≤ 72 MHz,
Sampling freq. ≤ 5 Msps
2.0 V ≤ V
DDA
≤ 3.6 V
64-pin package
Single ended
Differential
Single ended
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Differential
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Single ended
-
Differential
-
-
-
-
-
-
10.4
Slow channel 4.8 Ms 10.4
Fast channel 5.1 Ms 10.8
-
-
-
-
Slow channel 4.8 Ms 10.8
Fast channel 5.1 Ms 64
Single ended
-
-
-
-
-
-
-
-
-
Slow channel 4.8 Ms
Fast channel 5.1 Ms
63
67
Differential
Slow channel 4.8 Ms 67
Max
(4)
-
-
-
-
-
±2.5
-
-
-
±1.5
±3
±3.5
±2
±4
±1.5
±1.5
±1.5
±6.5
±6.5
±4
±4.5
±3
±3
±2.5
±2.5
±6
±6
±3.5
Unit
LSB bits dB
DS9118 Rev 14
125
Electrical characteristics STM32F303xB STM32F303xC
Symbol Parameter
Table 73. ADC accuracy, 64-pin packages (1)(2)(3) (continued)
Conditions Min
(4)
Max
(4)
Unit
SNR
THD
(5)
(5)
Signal-tonoise ratio
Total harmonic distortion
Single ended
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
ADC clock freq. ≤ 72 MHz,
Sampling freq ≤ 5 Msps,
2 V ≤ V
DDA
≤ 3.6 V
64-pin package
Differential
Single ended
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Differential
Slow channel 4.8 Ms
64
64
67
67
-
-
-
-
-
-
-
-
-75
-75
-79
-78
1. ADC DC accuracy values are measured after internal calibration.
2. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for I accuracy.
INJ(PIN)
and Σ I
INJ(PIN)
in
3. Better performance may be achieved in restricted V
DDA
, frequency and temperature ranges.
4. Guaranteed by characterization results.
5. Value measured with a -0.5 dB full scale 50 kHz sine wave input signal.
dB
Symbol Parameter
Table 74. ADC accuracy at 1MSPS (1)(2)
Test conditions Typ Max
(3)
Unit
ET
EO
EG
ED
EL
Total unadjusted error
Offset error
Gain error
Differential linearity error
Integral linearity error
Fast channel
Slow channel
ADC Freq ≤ 72 MHz
Sampling Freq ≤ 1MSPS
2.4 V ≤ V
DDA
= V
REF+
≤ 3.6 V
Single-ended mode
Fast channel
Slow channel
Fast channel
Slow channel
Fast channel
Slow channel
Fast channel
Slow channel
±2.5
±3.5
±1
±1.5
±2
±3
±0.7
±0.7
±1
±1.2
±5
±5
±2.5
±2.5
±3
±4
±2
±2
±3
±3
LSB
1. ADC DC accuracy values are measured after internal calibration.
2. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.. Any positive injection current within the limits specified for IINJ(PIN) and ∑
IINJ(PIN) in Section 6.3.14: I/O port characteristics does not affect the ADC
accuracy.
3. Guaranteed by characterization results.
DS9118 Rev 14
STM32F303xB STM32F303xC Electrical characteristics
4095
4094
4093
Figure 34. ADC accuracy characteristics
[1LSB
IDEAL
=
V
REF+
4096
V
DDA
(or depending on package)
4096
E
G
(1) Example of an actu al transfe r curve
(2) The ideal transfer cu rve
(3) End point correlation line
7
6
5
4
3
2
1
E
O
0
V
SSA
1 2 3 4 5 6
E
T
E
L
1 LSB
IDEAL
7
(2)
E
D
(3)
(1)
4093 4094 4095 4096
V
DDA
E
T
= Total unadjusted Error: maximum deviation between the actual and the ideal transfer curves.
E
O
= Offset Error: deviation between the first actual transition and the last actual one.
E
G
= Gain Error: deviation between the last ideal transition and the last actual one.
E
D
= Differential Linearity Error: maximum deviation between actual steps and the ideal one.
E
L
= Integral Linearity Error: maximum deviation between any actual transition and the end-point correlation line.
ai14395e
V
AIN
R
AIN(1)
Figure 35. Typical connection diagram using the ADC
V
DD
AINx
C parasitic
V
T
0.6 V
V
T
0.6 V
I
L
± 1 μA
Sample and hold ADC converter
R
ADC
12-bit converter
C
ADC
MS19881V3
1. Refer to Table 68 for the values of R
AIN
.
2. C parasitic
represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 this, f
ADC pF). A high C
should be reduced.
parasitic
value will downgrade conversion accuracy. To remedy
General PCB design guidelines
Power supply decoupling should be performed as shown in
Figure 11 . The 10 nF capacitor
should be ceramic (good quality) and it should be placed as close as possible to the chip.
DS9118 Rev 14
125
Electrical characteristics STM32F303xB STM32F303xC
Symbol Parameter
Table 75. DAC characteristics
Conditions
V
DDA
R
LOAD
(1)
R
O
(1)
C
LOAD
(1)
Output impedance
Capacitive load
V
DAC_OUT
(1)
Voltage on DAC_OUT output
I
DDA
(3)
Analog supply voltage
Resistive load
DAC DC current consumption in quiescent mode (Standby mode)
(2)
-
DAC output buffer ON
Connected to V
SSA
Connected to V
DDA
DAC output buffer OFF
DAC output buffer ON
Corresponds to 12-bit input code (0x0E0) to (0xF1C) at
V
DDA
= 3.6 V and (0x155) and (0xEAB) at
V
DDA
ON.
= 2.4 V DAC output buffer
DAC output buffer OFF
With no load, middle code
(0x800) on the input.
With no load, worst code
(0xF1C) on the input.
DNL
INL
(3)
(3)
Differential non linearity
Difference between two consecutive code-1LSB)
Given for a 10-bit input code
Given for a 12-bit input code
Integral non linearity
(difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095)
Given for a 10-bit input code
Given for a 12-bit input code
Offset (3)
-
Offset error (difference between measured value at
Code (0x800) and the ideal value = V
DDA
/2)
Given for a 10-bit input code at
V
DDA
= 3.6 V
Given for a 12-bit input code at
V
DDA
= 3.6 V
Gain error
(3)
Gain error Given for a 12-bit input code t
SETTLING
(3)
Settling time (full scale: for a
12-bit input code transition between the lowest and the highest input codes when
DAC_OUT reaches final value ±1LSB
C
LOAD
R
LOAD
≤
50 pF,
≥
5 k Ω
Update rate (3)
Max frequency for a correct
DAC_OUT change when small variation in the input code (from code i to i+1LSB)
C
LOAD
R
LOAD
≤
50 pF,
≥
5 k Ω
Min
2.4
5
25
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Typ
-
-
-
-
-
0.2 -
-
-
-
-
-
-
-
-
-
3
-
Max
3.6
-
-
15
50
V
DDA
– 0.2
0.5
V
DDA
- 1LSB mV
380 µA
480
±0.5
±2
±1
±4
±10
±3
±12
±0.5
4
1
Unit
V k Ω k Ω pF
V
µA
LSB
LSB
LSB
LSB mV
LSB
LSB
%
µs
MS/s
DS9118 Rev 14
STM32F303xB STM32F303xC Electrical characteristics
Symbol
Table 75. DAC characteristics (continued)
Parameter Conditions Min Typ Max t
WAKEUP
(3)
PSRR+
(1)
Wakeup time from off state
(Setting the ENx bit in the
DAC Control register)
C
LOAD
R
LOAD
≤
50 pF,
≥
5 k Ω
Power supply rejection ratio
(to V
DDA
) (static DC measurement
C
LOAD
=
50 pF,
No R
LOAD
≥
5 k Ω,
-
6.5
–67
10
–40
1. Guaranteed by design.
2. Quiescent mode refers to the state of the DAC a keeping steady value on the output, so no dynamic consumption is involved.
3. Guaranteed by characterization results.
Unit
µs dB
Figure 36. 12-bit buffered /non-buffered DAC
Buffered/Non-buffered DAC
Buffer(1)
R L
12-bit digital to analog converter
DAC_OUTx
C L ai17157V3
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
DS9118 Rev 14
125
Electrical characteristics STM32F303xB STM32F303xC
Symbol
V
DDA
V
IN
V
BG
V
SC t
S_SC t
START t
D
V offset dV offset
/dT
I
DD(COMP)
Parameter
Table 76. Comparator characteristics (1)
Conditions
Analog supply voltage
Comparator input voltage range
Scaler input voltage
Scaler offset voltage
V
REFINT
scaler startup time from power down
COMP current consumption
-
-
-
-
First V
REFINT
scaler activation after device power on
Next activations
Comparator startup time
Startup time to reach propagation delay specification
Ultra-low-power mode
Propagation delay for
200 mV step with 100 mV overdrive
Low-power mode
Medium power mode
High speed mode
V
DDA
≥ 2.7 V
V
DDA
< 2.7 V
Propagation delay for full range step with 100 mV overdrive
Ultra-low-power mode
Low-power mode
Medium power mode
High speed mode
V
DDA
≥ 2.7 V
V
DDA
< 2.7 V
Comparator offset error
Offset error temperature coefficient
-
-
Ultra-low-power mode
Low-power mode
Medium power mode
High speed mode
Min Typ Max Unit
2 3.6
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.2
±5
V
DDA
1
(2)
V
-
±10 mV s
0.2
ms
60 µs
1.2
3
10
75
2 4.5
0.7
0.3
50
1.5
0.6
100
µs ns
100 240
2 7
0.7
2.1
µs
0.3
90
1.2
180
18 ns
110 300
± 4 ± 10
mV
µV/°
C
1.5
5
15
100
µA
DS9118 Rev 14
STM32F303xB STM32F303xC Electrical characteristics
Symbol
Table 76. Comparator characteristics (1) (continued)
Parameter Conditions Min Typ Max Unit
V hys
Comparator hysteresis
No hysteresis
(COMPxHYST[1:0]=00)
-
Low hysteresis
(COMPxHYST[1:0]=01)
High speed mode
All other power modes
Medium hysteresis
(COMPxHYST[1:0]=10)
High speed mode
All other power modes
High hysteresis
(COMPxHYST[1:0]=11)
High speed mode
All other power modes
-
3
5
7
9
18
19
1. Data guaranteed by design.
2. For more details and conditions, see
Maximum V
REFINT
scaler startup time from power down.
0
8
15
31
-
13
10
26
19
49
40 mV
Figure 37. Maximum V
REFINT
scaler startup time from power down
DS9118 Rev 14
MS36682V1
125
Electrical characteristics STM32F303xB STM32F303xC
Symbol
Table 77. Operational amplifier characteristics (1)
Parameter Condition
Δ
VI
CMIR
VI
I
V
DDA
OFFSET
OFFSET
LOAD
IDDOPAMP
Analog supply voltage
Common mode input range
Input offset voltage
Input offset voltage drift
Drive current
Consumption
Maximum calibration range
After offset calibration
-
-
25°C, No Load on output.
All voltage/Temp.
25°C, No Load on output.
All voltage/Temp.
-
-
No load, quiescent mode
TS_OPAMP_VOUT
ADC sampling time when reading the OPAMP output.
CMRR Common mode rejection ratio t t
PSRR
GBW
SR
R
LOAD
C
LOAD
VOH
VOL ϕ
SAT
SAT m
OFFTRIM
WAKEUP
Power supply rejection ratio
Bandwidth
Slew rate
Resistive load
Capacitive load
DC
-
-
-
-
-
-
High saturation voltage
(2)
R load
= min,
Input at V
DDA
.
R load
= 20K,
Input at V
DDA
.
Rload = min, input at 0V
High saturation voltage
Phase margin
Offset trim time: during calibration, minimum time needed between two steps to have 1 mV accuracy
Rload = 20K, input at 0V.
-
-
Wake up time from OFF state.
C
LOAD
R
LOAD
≤
≥
50 pf,
4 k
Follower
Ω, configuration
Min
2.4
0
-
-
-
73
-
-
4
-
V
DDA
-100
V
-
-
-
-
-
400
DDA
-
-
-
-
-
-20
Typ
-
-
-
-
62
-
-
-
-
-
2.8
-
90
117
8.2
4.7
-
-
-
-
5
-
690
-
100
20
-
2
Max
3.6
V
DDA
4
Unit
V
V
6
1.6
mV
-
-
-
-
-
-
50
-
3
-
500
1450
µV/°C
µA
µA ns dB dB
MHz
V/µs k Ω pF mV
° ms
5 µs
DS9118 Rev 14
STM32F303xB STM32F303xC Electrical characteristics
Symbol
PGA gain
Table 77. Operational amplifier characteristics (1) (continued)
Parameter Condition Min Typ
Non inverting gain value -
R network
Gain=2
R2/R1 internal resistance values in
PGA mode
(3)
Gain=4
Gain=8
Gain=16
PGA gain error PGA gain error
I bias
OPAMP input bias current
PGA BW
PGA bandwidth for different non inverting gain
-
-
PGA Gain = 2,
Cload = 50pF,
Rload = 4 K Ω
PGA Gain = 4,
Cload = 50pF,
Rload = 4 K Ω
PGA Gain = 8,
Cload = 50pF,
Rload = 4 K Ω
PGA Gain = 16,
Cload = 50pF,
Rload = 4 K Ω
@ 1KHz, Output loaded with
4 K Ω
-
-
-
-
-
-
-
-
-1%
-
-
-
-
-
4
2
1
0.5
109
5.4/5.4
16.2/5.4
37.8/5.4
40.5/2.7
-
-
8
16
2
4
Max
-
-
-
-
1%
± 0.2
(4)
-
-
-
-
-
-
-
-
k Ω
µA
MHz
Unit
-
-
-
en Voltage noise density
@ 10KHz,
Output loaded with 4 K Ω
43 -
Hz
1. Guaranteed by design.
2. The saturation voltage can be also limited by the Iload (drive current).
3. R2 is the internal resistance between OPAMP output and OPAMP inverting input.
R1 is the internal resistance between OPAMP inverting input and ground.
The PGA gain =1+R2/R1
4. Mostly TTa I/O leakage, when used in analog mode.
DS9118 Rev 14
125
Electrical characteristics STM32F303xB STM32F303xC
Figure 38. OPAMP voltage noise versus frequency
6.3.22 Temperature sensor characteristics
Symbol
T
L
(1)
Avg_Slope
(1)
V
25 t
START
(1)
T
S_temp
(1)(2)
Table 78. TS characteristics
Parameter
V
SENSE
linearity with temperature
Average slope
Voltage at 25 °C
Startup time
ADC sampling time when reading the temperature
Min
-
4.0
1.34
4
2.2
Typ
-
1. Guaranteed by design.
2. Shortest sampling time can be determined in the application by multiple iterations.
± 1
4.3
1.43
-
Max
± 2
4.6
1.52
10
-
Table 79. Temperature sensor calibration values
Calibration value name Description Memory address
TS_CAL1
TS_CAL2
TS ADC raw data acquired at temperature of 30 °C,
V
DDA
= 3.3 V
TS ADC raw data acquired at temperature of 110 °C
V
DDA
= 3.3 V
0x1FFF F7B8 - 0x1FFF F7B9
0x1FFF F7C2 - 0x1FFF F7C3
Unit
°C mV/°C
V
µs
µs
DS9118 Rev 14
STM32F303xB STM32F303xC Electrical characteristics
6.3.23 V
BAT monitoring characteristics
Symbol
Table 80. V
BAT
monitoring characteristics
Parameter Min Typ
T
R
Q
Er
(1)
S_vbat
(1)(2)
Resistor bridge for V
BAT
Ratio on V
BAT
measurement
Error on Q
ADC sampling time when reading the V
BAT
1mV accuracy
-
-
-1
2.2
1. Guaranteed by design.
2. Shortest sampling time can be determined in the application by multiple iterations.
50
2
-
-
Max
-
-
+1
-
Unit
K Ω
%
µs
DS9118 Rev 14
125
Package information STM32F303xB STM32F303xC
7.1
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
LQFP100 – 14 x 14 mm, low-profile quad flat package information
Figure 39. LQFP100 – 14 x 14 mm, low-profile quad flat package outline
SEATING PLANE
C c
0.25 mm
GAUGE PLANE ccc C
D
D1
D3
L1
L K
76
75 51
50
100
PIN 1
IDENTIFICATION
1 25
26 e
1L_ME_V5
1. Drawing is not to scale.
Table 81. LQPF100 – 14 x 14 mm, low-profile quad flat package mechanical data inches
(1)
Symbol millimeters
Min Typ Max Min Typ Max
A
A1
-
0.05
-
1.60
0.15
-
0.002
-
0.063
0.0059
DS9118 Rev 14
STM32F303xB STM32F303xC Package information
Table 81. LQPF100 – 14 x 14 mm, low-profile quad flat package mechanical data (continued) inches
(1)
Symbol millimeters
Min Typ Max Min Typ Max
D1
D3
E
E1
E3
A2 b c
D e
L
L1
K ccc
1.35
0.17
0.09
15.80
13.80
-
15.80
13.80
-
-
0.45
-
0°
-
1.40
0.22
-
16.00
14.00
12.00
16.00
14.00
12.00
0.50
0.60
1.00
3.5°
-
1.45
0.27
0.2
16.2
14.2
-
16.2
14.2
-
-
0.75
-
7°
0.08
0.0531
0.0067
0.0035
0.622
0.5433
-
0.622
0.5433
-
-
0.0177
-
0°
-
0.0551
0.0087
-
0.6299
0.5512
0.4724
0.6299
0.5512
0.4724
0.0197
0.0236
0.0394
3.5°
-
0.0571
0.0106
0.0079
0.6378
0.5591
-
0.6378
0.5591
-
-
0.0295
-
7°
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 40. LQFP100 – 14 x 14 mm, low-profile quad flat package recommended footprint
75 51
76 50
0.5
0.3
16.7
14.3
1. Dimensions are in millimeters.
100
1
12.3
16.7
25
26
1.2
ai14906c
DS9118 Rev 14
142
Package information STM32F303xB STM32F303xC
LQFP100 device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.
Figure 41. LQFP100 – 14 x 14 mm, low-profile quad flat package top view example
Product identification
(1)
STM32F303
VCT6 R
Date code
Y WW
Revision code
Pin 1 indentifier
MSv36501V2
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.
DS9118 Rev 14
STM32F303xB STM32F303xC
7.2
Package information
LQFP64 – 10 x 10 mm, low-profile quad flat package information
Figure 42. LQFP64 – 10 x 10 mm, low-profile quad flat package outline
SEATING PLANE
C
0.25 mm
GAUGE PLANE ccc C
D
D1
D3 L1
L
K
48 33
32 b
49
64 17
PIN 1
IDENTIFICATION
1 e
16
5W_ME_V3
1. Drawing is not to scale.
Symbol
Table 82. LQFP64 – 10 x 10 mm, low-profile quad flat package mechanical data millimeters inches
(1)
Min Typ Max Min Typ Max b c
D
D1
A
A1
A2
D3
E
-
0.05
1.350
0.17
0.09
-
-
-
-
-
-
1.40
1.60
0.15
1.45
0.22
0.27
- 0.20
12.00
10.00
-
-
7.50
12.00
-
-
-
0.0020
0.0531
0.0067
0.0035
-
-
-
-
-
-
0.0551
0.0087
0.4724
0.3937
0.2953
0.4724
0.0630
0.0059
0.0571
0.0106
0.0079
-
-
-
-
DS9118 Rev 14
142
Package information STM32F303xB STM32F303xC
Table 82. LQFP64 – 10 x 10 mm, low-profile quad flat package mechanical data
(continued) millimeters inches (1)
Symbol
Min Typ Max Min Typ Max
K
L
L1 ccc
E1
E3 e -
-
-
0°
0.45
-
10.00
7.50
0.50
3.5°
0.60
- 1.00
-
-
-
-
7°
0.75
-
0.08
1. Values in inches are converted from mm and rounded to 4 decimal digits.
-
-
-
0°
0.0177
-
-
0.3937
0.2953
0.0197
3.5°
0.0236
0.0394
-
-
-
-
7°
0.0295
-
0.0031
Figure 43. LQFP64 – 10 x 10 mm, low-profile quad flat package recommended footprint
48 33
0.3
49
0.5
32
12.7
10.3
64
10.3
17
1.2
1
7.8
12.7
16 ai14909c
1. Dimensions are in millimeters.
DS9118 Rev 14
STM32F303xB STM32F303xC Package information
LQFP64 device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.
Figure 44. LQFP64 – 10 x 10 mm, low-profile quad flat package top view example
Product identification
(1)
Revision code
R
STM32F303
RCT6
Date code
Y WW
Pin 1 indentifier
MSv36502V1
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.
DS9118 Rev 14
142
Package information
7.3
STM32F303xB STM32F303xC
LQFP48 – 7 x 7 mm, low-profile quad flat package information
Figure 45. LQFP48 – 7 x 7 mm, low-profile quad flat package outline
SEATING
PLANE
C ccc C b
37
36
D
D1
D3
25
24
0.25 mm
GAUGE PLANE
K
L1
L
48
PIN 1
IDENTIFICATION
1
13
12 e
5B_ME_V2
D1
D3
E b c
D
A
A1
A2
1. Drawing is not to scale.
Symbol
Table 83. LQFP48 – 7 x 7 mm, low-profile quad flat package mechanical data millimeters inches
(1)
Min Typ Max Min Typ Max
- 1.60
0.05
1.35
-
1.40
0.15
1.45
0.17
0.09
8.80
6.80
-
8.80
0.22
-
9.00
7.00
5.50
9.00
0.27
0.20
9.20
7.20
-
9.20
0.0020
0.0531
0.0067
0.0035
0.3465
0.2677
-
0.3465
-
0.0551
0.0087
-
0.3543
0.2756
0.2165
0.3543
0.0059
0.0571
0.0106
0.0079
0.3622
0.2835
-
0.3622
DS9118 Rev 14
STM32F303xB STM32F303xC Package information
Symbol
Table 83. LQFP48 – 7 x 7 mm, low-profile quad flat package mechanical data
(continued) millimeters inches
(1)
Min Typ Max Min Typ Max
E1
E3 e
L
L1
K ccc
6.80
-
-
0.45
-
0°
-
7.00
5.50
0.50
0.60
1.00
3.5°
-
7.20
-
-
0.75
-
7°
0.08
1. Values in inches are converted from mm and rounded to 4 decimal digits.
0.2677
-
-
0.0177
-
0°
-
0.2756
0.2165
0.0197
0.0236
0.0394
3.5°
-
0.2835
-
-
0.0295
-
7°
0.0031
Figure 46. LQFP48 - 7 x 7 mm, low-profile quad flat package recommended footprint
0.50
1.20
0.30
37
36 25
24
0.20
7.30
9.70
5.80
7.30
48
1 12
13
1.20
5.80
9.70
ai14911d
1. Dimensions are in millimeters.
DS9118 Rev 14
142
Package information STM32F303xB STM32F303xC
LQFP48 device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.
Figure 47. LQFP48 - 7 x 7 mm, low-profile quad flat package top view example
Product identification
(1)
STM32F303
CCT6
Date code
Y WW
Pin 1 identification
Revision code
R
MS36605V1
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.
DS9118 Rev 14
STM32F303xB STM32F303xC
7.4
Package information
WLCSP100 - 0.4 mm pitch wafer level chip scale package information
Figure 48. WLCSP100 – 100L, 4.166 x 4.628 mm 0.4 mm pitch wafer level chip scale package outline
A1 BALL LOCATION
A
DETAIL A
K
BOTTOM VIEW
FRONT VIEW
SIDE VIEW
A1 ORIENTATION
REFERENCE
(4X) aaa
TOP VIEW
WAFER BACK SIDE
1. Drawing is not to scale.
DETAIL A
ROTATED 90°
WLCSP100L_A01Q_ME_V1
DS9118 Rev 14
142
Package information STM32F303xB STM32F303xC
Table 84. WLCSP100 – 100L, 4.166 x 4.628 mm 0.4 mm pitch wafer level chip scale package mechanical data inches
(1)
Symbol millimeters
Min Typ Max Typ Min Max e2
F
G
N
E e e1
A
A1
A2
A3
(2)
Ø b
(3)
D aaa bbb ccc ddd eee
0.525
-
-
-
0.22
4.166
4.628
-
-
-
-
-
-
-
-
-
-
-
0.555
0.17
0.38
0.025
0.25
4.201
4.663
0.4
3.6
3.6
0.3005
0.5315
100
0.1
0.1
0.1
0.05
0.05
0.585
4.698
-
-
-
-
-
-
-
-
-
-
-
0.28
4.236
-
-
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Back side coating.
3. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
-
-
-
-
-
-
-
0.0207
-
-
-
-
-
-
-
-
-
-
0.0219
0.0067
0.0150
0.0010
0.0098
0.1654
0.1836
0.0157
0.1417
0.1417
0.0118
0.0209
3.9370
0.0039
0.0039
0.0039
0.0020
0.0020
0.0230
-
-
-
0.0110
0.1668
0.1850
-
-
-
-
-
-
-
-
-
-
-
DS9118 Rev 14
STM32F303xB STM32F303xC Package information
Figure 49. WLCSP100 – 100L, 4.166 x 4.628 mm 0.4 mm pitch wafer level chip scale
package recommended footprint
Dpad
Dsm
WLCSP100L_A01Q_FP_V1
Table 85. WLCSP100 recommended PCB design rules (0.4 mm pitch)
Dimension Recommended values
Pitch
Dpad
Dsm
Stencil thickness
0.4 mm
0.225 mm
0.290 mm
0.1 mm
DS9118 Rev 14
142
Package information STM32F303xB STM32F303xC
WLCSP100 device marking
The following figure gives an example of topside marking orientation versus ball A1 identifier location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.
Figure 50. WLCSP100, 0.4 mm pitch wafer level chip scale package top view example
Ball A1 identifier
Product identification(1)
32F303VC6
Revision code
Y WW R
MSv40444V1
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.
DS9118 Rev 14
STM32F303xB STM32F303xC Package information
The maximum chip junction temperature (T
J max) must never exceed the values given in
Table 24: General operating conditions on page 60
.
The maximum chip-junction temperature, T
J using the following equation:
max, in degrees Celsius, may be calculated
T
J
max = T
A
max + (P
D
max x Θ
JA
)
Where:
• T
A
max is the maximum ambient temperature in °C,
• Θ
JA
is the package junction-to-ambient thermal resistance, in ° C/W,
• P
D
max is the sum of P
INT
max and P
I/O max (P
D
max = P
INT
max + P
I/O max),
• P
INT
max is the product of I
DD and internal power.
V
DD
, expressed in Watts. This is the maximum chip
P
I/O
max represents the maximum power dissipation on output pins where:
P
I/O
max = Σ (V
OL
× I
OL
) + Σ ((V
DD
– V
OH
) × I
OH
), taking into account the actual V
OL application.
/ I
OL
and V
OH
/ I
OH of the I/Os at low and high level in the
Symbol
Θ
JA
Table 86. Package thermal characteristics
Parameter Value
Thermal resistance junction-ambient
LQFP64 - 10 × 10 mm / 0.5 mm pitch
Thermal resistance junction-ambient
LQFP48 - 7 × 7 mm
Thermal resistance junction-ambient
LQFP100 - 14 × 14 mm / 0.5 mm pitch
Thermal resistance junction-ambient
WLCSP100 - 0.4 mm pitch
45
55
41
40
Unit
°C/W
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org
DS9118 Rev 14
142
Package information
7.5.2 Selecting the product temperature range
STM32F303xB STM32F303xC
When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Section 8: Ordering information .
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature.
As applications do not commonly use the STM32F303xB/STM32F303xC at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application.
The following examples show how to calculate the temperature range needed for a given application.
Example 1: High-performance application
Assuming the following application conditions:
Maximum ambient temperature T
Amax
I
DDmax
= 50 mA, V
DD
= 82 °C (measured according to JESD51-2),
= 3.5 V, maximum 3 I/Os used at the same time in output at low level with I
OL
= 8 mA, V
OL
= 0.4 V and maximum 2 I/Os used at the same time in output at low level with I
OL
= 20 mA, V
OL
= 1.3 V
P
INTmax
= 50 mA × 3.5 V= 175 mW
P
IOmax
= 3 × 8 mA × 0.4 V + 2 × 20 mA × 1.3 V = 61.6 mW
This gives: P
INTmax
= 175 mW and P
IOmax
= 61.6 mW:
P
Dmax
= 175 + 61.6 = 236.6 mW
Thus: P
Dmax
= 236.6 mW
Using the values obtained in Table 86
T
Jmax
is calculated as follows:
– For LQFP64, 45°C/W
T
Jmax
= 82 °C + (45°C/W × 236.6 mW) = 82 °C + 10.65 °C = 92.65 °C
This is within the range of the suffix 6 version parts (–40 < T
J
< 105 °C).
In this case, parts must be ordered at least with the temperature range suffix 6 (see
Section 8: Ordering information
).
DS9118 Rev 14
STM32F303xB STM32F303xC Package information
Example 2: High-temperature application
Using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature T
J specified range.
remains within the
Assuming the following application conditions:
Maximum ambient temperature T
Amax
I
DDmax
= 20 mA, V
DD
= 115 °C (measured according to JESD51-2),
= 3.5 V, maximum 9 I/Os used at the same time in output at low level with I
OL
= 8 mA, V
OL
= 0.4 V
P
INTmax
= 20 mA × 3.5 V= 70 mW
P
IOmax
= 9 × 8 mA × 0.4 V = 28.8 mW
This gives: P
INTmax
= 70 mW and P
IOmax
= 28.8 mW:
P
Dmax
= 70 + 28.8 = 98.8 mW
Thus: P
Dmax
= 98.8 mW
Using the values obtained in Table 86
T
Jmax
is calculated as follows:
– For LQFP100, 41°C/W
T
Jmax
= 115 °C + (41°C/W × 98.8 mW) = 115 °C + 4.05 °C = 119.05 °C
This is within the range of the suffix 7 version parts (–40 < T
J
< 125 °C).
In this case, parts must be ordered at least with the temperature range suffix 7 (see
Section 8: Ordering information
).
DS9118 Rev 14
142
Ordering information STM32F303xB STM32F303xC
Table 87. Ordering information scheme
STM32 F 303 R Example:
Device family
STM32 = Arm-based 32-bit microcontroller
Product type
F = general-purpose
Device subfamily
303 = STM32F303xx
Pin count
C = 48 pins
R = 64 pins
V = 100 pins
B T 6 xxx
Flash memory size
B = 128 Kbytes of Flash memory
C = 256 Kbytes of Flash memory
Package
T = LQFP
Y = WLCSP
Temperature range
6 = Industrial temperature range, –40 to 85 °C
7 = Industrial temperature range, –40 to 105 °C
Options xxx = programmed parts
TR = tape and reel
For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office.
DS9118 Rev 14
STM32F303xB STM32F303xC Revision history
Date
22-Jun-2012
07-Sep-2012
21-Sep-2012
Revision
1
2
3
Table 88. Document revision history
Changes
Initial release
Modified Features on cover page.
Modified Table 2: STM32F301xx family device features and peripheral counts
Added clock tree to Section 3.9: Clocks and startup
Added Table 10: STM32F302xB/STM32F302xC I2C implementation
Added Table 11: USART features
Added Table 12: STM32F302xB/STM32F302xC SPI/I2S implementation
Modified Table 13: Capacitive sensing GPIOs available on
STM32F302xB/STM32F302xC devices
Modified Figure 7 , Figure 8 and Figure 9: STM32F302xB/STM32F302xC
LQFP100 pinout
Modified Table 16: STM32F302xB/STM32F302xC pin definitions
Modified Figure 11: Power supply scheme
Modified Table 21: Voltage characteristics
Modified Table 22: Current characteristics
Modified Table 25: Operating conditions at power-up / power-down
Added footnote to
Table 31: Typical and maximum current consumption from the V
Added footnote to Table 35 and
Table 36: Typical current consumption in
Sleep mode, code running from Flash or RAM
Removed table “Switching output I/O current consumption” and table
“Peripheral current consumption”
Added note under
Figure 17: Typical application with a 32.768 kHz crystal
Updated Table 44: HSI oscillator characteristics
Updated Wakeup time from low-power mode and Table 39: Low-power mode wakeup timings
Updated Table 47: Flash memory characteristics
Updated Table 52: Electrical sensitivities
Updated Table 53: I/O current injection susceptibility
Updated Table 54: I/O static characteristics
Updated Table 55: Output voltage characteristics
Updated Table 57: NRST pin characteristics
Updated Table 63: SPI characteristics
Updated Table 64: I 2 S characteristics
Corrected LQFP100 in Section 7.2.3: Selecting the product temperature range
Updated Table 63: SPI characteristics
DS9118 Rev 14
148
Revision history STM32F303xB STM32F303xC
Date
05-Dec-2012
Table 88. Document revision history (continued)
Revision Changes
4
Updated first page
Removed references to VDDSDx and VSSSD
Added reference to PM0214 in Section 1
Moved Temp. sensor calibartion values to
Updated Table 3: STM32F303xx family device features and peripheral counts
Updated Section 3.4: Embedded SRAM
Updated Section 3.2: Memory protection unit (MPU)
Updated Section 3.24: Universal serial bus (USB)
Modified Section 3.26: Touch sensing controller (TSC)
Updated heading of Table 11: USART features
Updated Table 16: STM32F302xB/STM32F302xC pin definitions
Added notes to PC13, PC14 and PC15 in Table 16:
STM32F302xB/STM32F302xC pin definitions
Updated Figure 11: Power supply scheme
Modified Table 21: Voltage characteristics
Modified Table 22: Current characteristics
Modified Table 24: General operating conditions
current consumption (LSE and RTC
Updated Section 6.3.14: I/O port characteristics
Updated Table 30: Typical and maximum current consumption from V
and Table 31: Typical and maximum current
Table 32: Typical and maximum V
and
Table 33: Typical and maximum V
consumption in Stop and Standby modes
Updated Table 34: Typical and maximum current consumption from V
current consumption (LSE and RTC
and Table 36: Typical current consumption in Sleep mode, code running from Flash or RAM
Added Table 38: Peripheral current consumption
Added Table 37: Switching output I/O current consumption
Updated Section 6.3.6: Wakeup time from low-power mode
Modified ESD absolute maximum ratings
Modified Table 55: Output voltage characteristics
Updated Table 56: I/O AC characteristics
Updated Table 53: I/O current injection susceptibility
Updated Table 58: TIMx characteristics
Updated Section 7.4: WLCSP100 - 0.4 mm pitch wafer level chip scale package information
Added Table 69: Maximum ADC RAIN
Added Table 70: ADC accuracy - limited test conditions, 100-pin packages
Updated Table 64: ADC accuracy - limited test conditions 2)
Updated Table 75: DAC characteristics
Updated Table 77: Operational amplifier characteristics
Updated figures and tables in
Section 7: Package information
DS9118 Rev 14
STM32F303xB STM32F303xC Revision history
Date
08-Jan-2013
24-Jun-2013
13-Nov-2013
Table 88. Document revision history (continued)
Revision Changes
5
6
7
Updated V hys
and I lkg in
Table 54: I/O static characteristics .
Updated V
IL(NRST)
, V
IH(NRST)
, and V
NF(NRST)
Updated Table 70: ADC accuracy - limited test conditions, 100-pin packages
and Table 64: ADC accuracy - limited test conditions 2) .
Replaced Cortex-M4F with Cortex M4 with FPU
Updated Core, Memories and SPI bullet points in Features
Removed 8KB CCM SRAM from STM32F302xx devices, updated
Figure 2: STM32F303xB/STM32F303xC block diagram and Table 3:
STM32F303xx family device features and peripheral counts
Updated Section 3.4: Embedded SRAM
Added VREF+ in Section 3.14: Digital-to-analog converter (DAC)
Removed DMA support for UART5 in Table 11: USART features
Added ‘reference clock detection’ bullet in Section 3.18: Real-time clock
(RTC) and backup registers
Added paragraph ‘The touch sensing controller is fully...’ in Section 3.26:
Touch sensing controller (TSC)
Updated Comparison of I2C analog and digital filters
Updated Section 3.10: General-purpose input/outputs (GPIOs)
Added ‘EVENTOUT’ in Table 16: STM32F302xB/STM32F302xC pin definitions and added note to ‘VREF+’ pin
Updated Σ I
VDD
in Table 22: Current characteristics and
Updated Table 61: I2C timings specification (see I2C specification, rev.03, June 2007)
C bus AC waveforms and measurement circuit
Added VREF+ row to Table 68: ADC characteristics , replaced VDDA
with VREF+, updated t conv
and added note to ‘conversion voltage range
Added VREF+ row to Table 75: DAC characteristics and replaced VDDA
with VREF+
Added ‘PGA BW’ and ‘en’ in Table 77: Operational amplifier characteristics
Removed STM32F302xB/STM32F302xC products (now in a separate datasheet).
Added I2S feature for SPI2 and SPI3
Added t
SP
to Table 61: I2C timings specification (see I2C specification, rev.03, June 2007)
.
Renamed t
SP
to t
AN
in
Table 62: I2C analog filter characteristics .
Added t
STAB
in Table 68: ADC characteristics
Renamed V
OPAMPx
to
VREFOPAMPx
Updated Table 71: ADC accuracy, 100-pin packages .
Updated ADC channel names in Section 3.13.1
, Section 3.13.2
and
Section 3.13.3
.
DS9118 Rev 14
148
Revision history STM32F303xB STM32F303xC
Date
18-Apr-2014
09-Dec-2014
29-Jan-2015
Table 88. Document revision history (continued)
Revision Changes
8
9
10
Updated Table 50: EMI characteristics
conditions :3.3v replaced by 3.6V.
Updated Section 6.3.17: Communications interfaces
I
2
C interface.
Updated Table 77: Operational amplifier characteristics
adding
TS_OPAMP_VOUT row.
Updated Section 3.13: Fast analog-to-digital converter (ADC) . updated Arm and Cortex trademark.
Updated Table 32: Typical and maximum V
with Max value at 85°C and 105°C.
Updated Table 70: ADC accuracy - limited test conditions, 100-pin packages
and Table 71: ADC accuracy, 100-pin packages for 100-pin
package.
Added Table 72: ADC accuracy - limited test conditions, 64-pin packages
and Table 73: ADC accuracy, 64-pin packages
for 64-pin package.
Added Table 74: ADC accuracy at 1MSPS
for 1MSPS sampling frequency.
Updated Table 63: SPI characteristics .
Updated Table 75: DAC characteristics
.
Updated core description in cover page.
Updated HSI characteristics Table 44: HSI oscillator characteristics
and
Figure 18: HSI oscillator accuracy characterization results for soldered parts .
Updated Table 58: TIMx characteristics .
Updated Table 16: STM32F302xB/STM32F302xC pin definitions adding note for I/Os featuring an analog output function
(DAC_OUT,OPAMP_OUT).
Updated Table 68: ADC characteristics adding IDDA & IREF
consumptions.
Added Figure 32: ADC typical current consumption on VDDA pin and
Figure 33: ADC typical current consumption on VREF+ pin .
Added Section 3.8: Interconnect matrix .
Updated Figure 5: Clock tree .
Added note after
Table 32: Typical and maximum V
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at: www.st.com. ECOPACK
with new LQFP100,
LQFP64, LQFP48 package marking.
Updated Table 16: STM32F302xB/STM32F302xC pin definitions and alternate functions tables replacing usart_rts by usart_rts_de.
Updated Section 6.3.20: Comparator characteristics modifying ts_sc
characteristics in
and adding Figure 37: Maximum VREFINT scaler startup time from power down .
Updated I
DD
data in
Table 42: HSE oscillator characteristics .
DS9118 Rev 14
STM32F303xB STM32F303xC Revision history
Date
17-Apr-2015
11-Dec-2015
Table 88. Document revision history (continued)
Revision Changes
11
12
Updated Section 7: Package information : with new package information
structure adding 1 sub paragraph for each package.
Updated Figure 41: LQFP100 – 14 x 14 mm, low-profile quad flat package top view example
removing gate mark.
Added note for all packages about the device marking orientation: “the following figure gives an example of topside marking orientation versus pin 1 identifier location”.
Updated Table 82: LQFP64 – 10 x 10 mm, low-profile quad flat package mechanical data .
Added WLCSP100:
– Updated cover page.
– Updated Table 2: STM32F303xB/STM32F303xC family device features and peripheral counts
.
– Added Figure 7: STM32F303xB/STM32F303xC WLCSP100 pinout .
– Updated Table 13: STM32F303xB/STM32F303xC pin definitions
.
– Updated Table 24: General operating conditions
.
– Added Section 7.4: WLCSP100 - 0.4 mm pitch wafer level chip scale package information .
– Updated Table 86: Package thermal characteristics .
– Updated Table 87: Ordering information scheme .
removing all VDD and VSS indexes.
Updated all the notes removing ‘not tested in production’.
Updated Table 68: ADC characteristics adding V
REFreference.
negative voltage
Update
Table 21: Voltage characteristics adding table note 4.
DS9118 Rev 14
148
Revision history STM32F303xB STM32F303xC
Date
06-May-2016
30-Oct-2018
Table 88. Document revision history (continued)
Revision Changes
13
14
Updated Table 43: LSE oscillator characteristics (f
LSEDRV[1:0] bits.
Updated Table 28: Embedded internal reference voltage
V
REFINT internal reference voltage (min and typ values).
Updated Figure 5: STM32F303xB/STM32F303xC LQFP64 pinout
replacing VSS by PF4.
Updated Table 51: ESD absolute maximum ratings ESD CDM at class 3
and 4 including WLCSP100 package information.
Updated Table 13: STM32F303xB/STM32F303xC pin definitions :
– Adding ‘digital power supply’ in the Pin function column at the line corresponding to K8/28/19 pins.
– Adding VSS digital ground line with WLCSP100 K9 and K10 pins connected.
– Replacing in VDD line for WLCSP100: ‘A10, B10’ by ‘A9, A10, B10,
B8’.
Updated Figure 21: Five volt tolerant (FT and FTf) I/O input characteristics - CMOS port
.
Updated Table 77: Operational amplifier characteristics
high saturation and low saturation voltages.
Updated Table 13: STM32F303xB/STM32F303xC pin definitions adding
note ‘Fast ADC channel’ for ADCx_IN1..5.
Updated Table 75: DAC characteristics
resistive load.
Updated Table 68: ADC characteristics adding CMIR parameter and
modifying tSTAB parameter characteristics.
Updated Table 51: ESD absolute maximum ratings ESD class.
Updated cover on 2 pages.
Updated Section 1: Introduction
with Arm logo.
Updated Section 7: Package information adding information:
– Other optional marking or inset/upset marks.
– The printed markings may differ depending on the supply chain.
– Updated note 1 below all the package device marking figures.
DS9118 Rev 14
STM32F303xB STM32F303xC
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