STMicroelectronics TSV772 Datasheet
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TSV772
Datasheet
High bandwidth (20 MHz) low offset (200 µV) rail-to-rail 5 V Op Amp
TSV772
MiniSO8
Maturity status link
TSV772
TSV772
DFN8 2x2 mm
2
2
2
2
2
TSV772
SO8
Package
•
•
DFN8
MiniSO8
SO8
MiniSO8
SO8
TSV7722
TSV792
Related products
Low rail 22 MHz amplifier
Rail-to-rail amplifier with higher GBW 50 MHz
Features
• Gain bandwidth product 20 MHz, unity gain stable
• Low input offset voltage: 50 µV typ., 200 µV max.
• Low input bias current: 2 pA typ.
• Low noise: 7 nV/√Hz
• Slew rate: 13 V/µs
• Wide supply voltage range: 2.0 V to 5.5 V
• Rail-to-rail input and output
• 4 kV HBM ESD tolerance
• Input common-mode range includes low rail
• Extended temperature range: -40 °C to +125 °C
• Automotive grade versions available
• Benefits:
– Accuracy of measurement virtually unaffected by noise or input bias current
– Signal conditioning for high frequencies
Application
• High bandwidth low-side and high-side current sensing
• Photodiode amplifiers
• A/D converters input buffers
• Power management in solar powered systems
• Automotive high bandwidth signal conditioning
• Active filters
Description
The TSV772 is a dual 20 MHz-bandwidth unity-gain-stable amplifier. The rail-to-rail input stage and the slew rate of 13 V/µs make the TSV772 ideal for low-side current measurement. The excellent accuracy provided by maximum input voltage of 200 µV allows amplifying accurately small-amplitude input signal.
The TSV772 can operate from a 2.0 V to 5.5 V single supply and is fully characterized for an output capacitor of 47 pF, for easy usage as an A/D converter input buffer.
DS13842 - Rev 2 - November 2021
For further information contact your local STMicroelectronics sales office.
www.st.com
TSV772
Pin description
1
1.1
Pin description
TSV772 dual operational amplifier
Figure 1. Pin connections (top view)
OUT1 1
IN12
IN1+ 3
VCC4
8 VCC+
7 OUT2
6 IN2-
5 IN2+
OUT1 1
IN12
IN1+ 3
VCC4
NC
MiniSO8 and SO8 DFN8 2 x 2 mm (1)
1. The exposed pad of the DFN8 2x2 can be connected to VCC- or left floating.
Pin n°
1
2
3
4
5
6
7
8
Pin name
OUT1
IN1-
IN1+
VCC-
IN2+
IN2-
OUT2
VCC+
Table 1. Pin description
Description
Output channel 1
Inverting input channel 1
Non-inverting input channel 1
Negative supply voltage
Non-inverting input channel 2
Inverting input channel 2
Output channel 2
Positive supply voltage
8 VCC+
7
6
OUT2
IN2-
5 IN2+
DS13842 - Rev 2 page 2/30
2
TSV772
Absolute maximum ratings and operating conditions
Absolute maximum ratings and operating conditions
Table 2. Absolute maximum ratings
Symbol
Value Unit
V
CC
V id
V
IN
I
IN
T stg
Supply voltage
Input voltage differential (V
IN+
Input pins voltage
Input current
Storage temperature
- V
IN-
)
-0.3 to 6.0
± V
CC
(V
CC
-) - 0.3 V to V
± 10
150
CC+
+ 0.3
V
V
V mA
°C
R th-ja
Thermal resistance junction-to-ambient
DFN8 (2 mm x 2 mm)
MiniSO8
SO8
-
76
127
113
°C / W
T j
ESD
Maximum junction temperature
HBM: human body model
CDM: charged device model
150
4
1.5
1. All voltage values are with respect to VCC- pin, unless otherwise specified.
2. The maximum input voltage value may be extended to the condition that the input current is limited to ±10 mA.
3. R th j-a
are typical values obtained with a PCB according to JEDEC 2s2p without vias.
4. Human Body Model: the test HBM is done in accordance with the standards ESDA-JS-001-2017 and Q100-002.
5. Charged device model: the test CDM is done in accordance with the standards ESDA-JS-002-2018 and Q100-011.
°C kV kV
Symbol
V
CC
V icm
T oper
Table 3. Operating conditions
Parameter
Supply voltage
Common-mode input voltage range
Operating free air temperature range
Value
2.0 to 5.5 V
V
CC-
– 0.2 V to V
CC+
+ 0.1 V
-40 °C to +125 °C
DS13842 - Rev 2 page 3/30
TSV772
Electrical characteristics
3
Electrical characteristics
Table 4. Electrical characteristics at V
CC
= 5.0 V, V icm
= V
OUT
= V
CC
/ 2, T = 25 °C, R
C
L
= 47 pF (unless otherwise specified)
L
= 10 kΩ connected to V
CC
/ 2 and
Symbol Parameter Min.
Typ.
Max.
Unit
V io
∆V io
/∆T Input offset voltage drift
I ib
I io
A
VD
CMR1
CMR2
SVR
V
OH
V
OL
Input offset voltage
Input bias current
Input offset current
Open loop gain
Common-mode rejection ratio
20.log(∆V io
/∆V icm
)
Supply voltage rejection ratio
20.log(∆V io
/∆V
CC
)
High level output voltage drop
(V
OH
= V
CC+
- V
OUT
)
Low level output voltage drop
(V
OL
= V
OUT
)
Conditions
DC performance
T = 25 °C
-40 °C ≤ T ≤ 125 °C
-40 °C ≤ T ≤ 125 °C
T = 25 °C
-40 °C ≤ T ≤ 125 °C
T = 25 °C
-40 °C ≤ T ≤ 125 °C
V
CC-
+100 mV ≤ V
OUT
≤ V
CC+
-100 mV,
T = 25 °C
V
CC-
+100 mV ≤ V
OUT
≤ V
CC+
-100 mV,
-40 °C ≤ T ≤ 125 °C
R
L
= 2 kΩ, V
CC-
+ 200 mV ≤ V
OUT
≤ V
CC+
-200 mV,
T = 25 °C
R
L
= 2 kΩ, V
CC-
+ 200 mV ≤ V
OUT
≤ V
CC+
-200 mV,
40 °C ≤ T ≤ 125 °C
V
CC-
-0.1 V ≤ V icm
≤ V
CC+
-1.8 V,
T = 25 °C
V
CC-
-0.1 V ≤ V icm
≤ V
CC+
-1.8 V,
-40 °C ≤ T ≤ 125 °C
V
CC-
-0.1 V ≤ V icm
≤ V
CC+
,
T = 25 °C
V
CC-
-0.1 V ≤ V icm
≤ V
CC+
,
-40 °C ≤ T ≤ 125 °C
2.0 V ≤ V
CC
≤ 5.5 V, T = 25 °C, V icm
= 0 V
2.0 V ≤ V
CC
≤ 5.5 V, -40 °C ≤ T ≤ 125 °C,
V icm
= 0 V
T = 25 °C
-40 °C ≤ T ≤ 125 °C
T = 25 °C
-40 °C ≤ T ≤ 125 °C
110
95
105
90
98
90
81
76
90
90
2
75
1
20
120
110
100
92
110
110
±200
±700
±5
10
20
10
20
µV
µV/°C pA pA dB dB dB mV
I
OUT
I sink
(R
L
connected to V
CC+
)
I
V source
(R
CC-
)
L
connected to
T = 25 °C
-40 °C ≤ T ≤ 125 °C
T = 25 °C
-40 °C ≤ T ≤ 125 °C
45
30
45
30
65
65 mA
DS13842 - Rev 2 page 4/30
Symbol
I
CC
Parameter
Supply current (per channel,
R
L
> 1 MΩ)
Conditions
T = 25 °C
-40 °C ≤ T ≤ 125 °C
AC performance
GBP
SR t s t rec
CR
Φ m
GM
Gain bandwidth product
Slew rate
Settling time
Overload recovery time
A
V
R
L
= 4.7 kΩ, AV = -1 V/V, to 0.1%, V in
= 1 Vp-p
R
L
= 4.7 kΩ, AV = -1 V/V, to 0.01%, V in
V
OUT
100 mV from rail, A
V
= +1
V
OUT
= 4 Vpp, A
V
= +101, f = 1 kHz
C in
Cross talk
Phase margin
Gain margin
Differential input capacitance
Common-mode input capacitance en Input voltage noise density en p-p Input noise voltage
1. Slew rate value is the average of rising and falling values.
2. Settling time at 0.01% is guaranteed by design.
f = 1 kHz f = 10 kHz
0.1 Hz ≤ f ≤ 10 Hz
Min.
17
11
20
13
300
470
235
120
50
9
6.5
2.5
13
7
7
TSV772
Electrical characteristics
Typ.
1.9
Max.
2.1
2.1
Unit mA nV/√Hz
µVpp
MHz
V/µs ns ns dB degrees dB pF
DS13842 - Rev 2 page 5/30
TSV772
Electrical characteristics
Table 5. Electrical characteristics at V
CC+
= 3.3 V, V icm
= V
OUT
= V
CC
/ 2, T = 25 °C, R
C
L
= 47 pF (unless otherwise specified)
L
= 10 kΩ connected to V
CC
/ 2 and
Symbol Parameter Min.
Typ.
Max.
Unit
V io
I ib
I io
A
VD
CMR1
CMR2
V
OH
V
OL
Input offset voltage
∆V io
/∆T Input offset voltage drift
Input bias current
Input offset current
Open loop gain
Common-mode rejection ratio
20.log(∆V io
/∆V icm
)
High level output voltage drop
(V
OH
= V
CC+
- V
OUT
)
Low level output voltage drop
(V
OL
= V
OUT
)
Conditions
DC performance
T = 25 °C
-40 °C ≤ T ≤ 125 °C
-40 °C ≤ T ≤ 125 °C
T = 25 °C
-40 °C ≤ T ≤ 125 °C
T = 25 °C
-40 °C ≤ T ≤ 125 °C
V
CC-
+100 mV ≤ V
OUT
≤ V
CC+
-100 mV, T = 25 °C
V
CC-
+100 mV ≤ V
OUT
≤ V
CC+
-100 mV,
-40 °C ≤ T ≤ 125 °C
R
L
= 2 kΩ, V
CC-
+ 200 mV ≤ V
OUT
≤ V
CC+
-200 mV,
T = 25 °C
R
L
= 2 kΩ, V
CC-
+ 200 mV ≤ V
OUT
≤ V
CC+
-200 mV,
-40 °C ≤ T ≤ 125 °C
V
CC-
-0.1 V ≤ V icm
≤ V
CC+
-1.8 V,
T = 25 °C
V
CC-
-0.1 V ≤ V icm
≤ V
CC+
-1.8 V,
-40 °C ≤ T ≤ 125 °C
V
CC-
-0.1 V ≤ V icm
≤ V
CC+
, T = 25 °C
V
CC-
-0.1 V ≤ V icm
≤ V
CC+
, -40 °C ≤ T ≤ 125 °C
T = 25 °C
-40 °C ≤ T ≤ 125 °C
T = 25 °C
-40 °C ≤ T ≤ 125 °C
105
90
100
85
93
85
77
70
1.8
60
1
20
115
108
98
90
±200
±700
±5
10
20
10
20
µV
µV/°C pA pA dB dB mV
I
OUT
I
CC
I sink
(R
L
connected to V
CC+
)
I source
(R
L
connected to
V
CC-
)
Supply current (per channel, R
L
> 1 MΩ)
T = 25 °C
-40 °C ≤ T ≤ 125 °C
T = 25 °C
-40 °C ≤ T ≤ 125 °C
T = 25 °C
-40 °C ≤ T ≤ 125 °C
AC performance
45
30
45
30
60
65
1.8
2.0
2.0
mA mA
GBP
SR t s t rec
Gain bandwidth product
Slew rate
Settling time
Overload recovery time
A
V
R
L
= 4.7 kΩ, AV = -1 V/V, to 0.1%, V in
= 1 Vp-p
R
L
= 4.7 kΩ, A
V
= -1 V/V, to 0.01%, V in
= 1 Vp-p
V
OUT
100 mV from rail, A
V
= +1
17
11
20
13
310
480
260
MHz
V/µs ns ns
DS13842 - Rev 2 page 6/30
Symbol
Φ m
GM
C in
Parameter
Phase margin
Gain margin
Differential input capacitance
Common-mode input capacitance
Conditions en Input voltage noise density en p-p Input noise voltage
1. Slew rate value is the average of rising and falling values.
2. Settling time at 0.01% is guaranteed by design.
f = 1 kHz f = 10 kHz
0.1 Hz ≤ f ≤ 10 Hz
Min.
TSV772
Electrical characteristics
Typ.
48
9
6.5
2.5
13
7
7
Max.
Unit degrees dB pF nV/√Hz
µVpp
DS13842 - Rev 2 page 7/30
TSV772
Electrical characteristics
Table 6. Electrical characteristics at V
CC+
= 2.0 V, V icm
= V
OUT
= V
CC
/2, T = 25 °C, R
C
L
= 47 pF (unless otherwise specified)
L
= 10 kΩ connected to V
CC
/ 2 and
Symbol Parameter Min.
Typ.
Max.
Unit
V io
Input offset voltage
(V icm
= 0 V)
∆V io
/∆T Input offset voltage drift
I ib
I io
A
VD
Input bias current
Input offset current
Open loop gain
Conditions
DC Performance
T = 25 °C
-40 °C ≤ T ≤ 125 °C
-40 °C ≤ T ≤ 125 °C
T = 25 °C
-40 °C ≤ T ≤ 125 °C
T = 25 °C
-40 °C ≤ T ≤ 125 °C
V
CC-
+100 mV ≤ V
OUT
≤ V
CC+
-100 mV, T = 25 °C
V
CC-
+100 mV ≤ V
OUT
≤ V
CC+
-100 mV,
-40 °C ≤ T ≤ 125 °C
R
L
= 2 kΩ, V
CC-
+ 200 mV ≤ V
OUT
≤ V
CC+
-200 mV,
T = 25 °C
R
L
= 2 kΩ, V
CC-
+ 200 mV ≤ V
OUT
≤ V
CC+
-200 mV,
40 °C ≤ T ≤125 °C
V
CC-
-0.1 V ≤ V icm
≤ V
CC+
, T = 25 °C
95
80
90
80
73
1
40
1
15
94
±200
±700
±5
µV
µV/°C pA pA dB
CMR
V
OH
V
OL
I
OUT
I
CC
Common-mode rejection ratio
20.log(∆V io
/∆V icm
)
High level output voltage drop
(V
OH
= V
CC+
- V
OUT
)
Low level output voltage drop
(V
OL
= V
OUT
)
I
V sink
(R
CC+
)
L
connected to
I source
(R
L
connected to
V
CC-
)
Supply current (per channel, R
L
> 1 MΩ,
V icm
= 0 V)
V
CC-
-0.1 V ≤ V icm
≤ V
CC+
, -40 °C ≤ T ≤ 125 °C
T = 25 °C
-40 °C ≤ T ≤ 125 °C
T = 25 °C
-40 °C ≤ T ≤ 125 °C
T = 25 °C
-40 °C ≤ T ≤ 125 °C
T = 25 °C
-40 °C ≤ T ≤ 125 °C
T = 25 °C
-40 °C ≤ T ≤ 125 °C
67
45
30
45
30
86
60
65
1.7
10
20
10
20
1.9
1.9
dB mV mA mA
AC performance
GBP
SR t s t rec
Φ m
GM
C in
Gain bandwidth product
Slew rate
Settling time
Overload recovery time
Phase margin
Gain margin
Differential input capacitance
AV = 1 V/V, 10% to 90%
R
L
= 4.7 kΩ, AV = -1 V/V, to 0.1%, V in
= 1 Vp-p
R
L
= 4.7 kΩ, A
V
= -1 V/V, to 0.01%, V in
= 1 Vp-p
V
OUT
50 mV from initial value, A
V
= +1
17
9
20
11
450
570
300
47
8
6.5
MHz
V/µs ns ns degrees dB pF
DS13842 - Rev 2 page 8/30
Symbol
C in
Parameter
Common-mode input capacitance
Conditions en
Input voltage noise density en p-p Input noise voltage
1. Slew rate value is the average of rising and falling values.
2. Settling time at 0.01% is guaranteed by design.
f = 1 kHz f = 10 kHz
0.1 Hz ≤ f ≤ 10 Hz
Min.
TSV772
Electrical characteristics
Typ.
2.5
30
14
10
Max.
Unit pF nV/√Hz
µVpp
DS13842 - Rev 2 page 9/30
4
TSV772
Typical performance characteristics
Typical performance characteristics
R
L
= 10 kΩ connected to V
CC
/ 2 and C
L
= 47 pF, unless otherwise specified.
Figure 2. Supply current vs. supply voltage Figure 3. Input offset voltage distribution at V
CC
= 5 V
Figure 4. Input offset voltage distribution at V
CC
= 2 V Figure 5. Input offset voltage vs. temperature at V
CC
= 5 V
Figure 6. Input offset voltage vs. temperature at V
CC
= 2 V
Figure 7. Input offset voltage thermal drift distribution at
V
CC
= 5 V
DS13842 - Rev 2 page 10/30
Figure 8. Input offset voltage thermal drift distribution at
V
CC
= 2 V
TSV772
Typical performance characteristics
Figure 9. Input offset voltage vs. supply voltage
-200
Figure 10. Input offset voltage vs. common-mode voltage at V
CC
= 5 V
Figure 11. Input offset voltage vs. common-mode voltage at V
CC
= 2 V
Figure 12. Input bias current vs. temperature
Figure 13. Input bias current vs. common-mode voltage at
V
CC
= 5 V
DS13842 - Rev 2 page 11/30
Figure 14. Output current vs. output voltage at V
CC
= 5 V
TSV772
Typical performance characteristics
Figure 15. Output current versus output voltage at
V
CC
= 2 V
Figure 16. Output saturation voltage (V
OL
) vs. supply voltage
Figure 17. Output saturation voltage (V
OH
) vs. supply voltage
Figure 18. Positive slew rate at V
CC
= 5 V Figure 19. Negative slew rate at V
CC
= 5 V
DS13842 - Rev 2 page 12/30
Figure 20. Slew rate vs. V
CC
TSV772
Typical performance characteristics
Figure 21. Open loop bode diagram at V
CC
= 5 V
Figure 22. Open loop bode diagram at V
CC
= 2 V Figure 23. Closed loop bode diagram at V
CC
= 5 V
Figure 24. Closed loop bode diagram at V
CC
= 2 V
Figure 25. Phase margin vs. common-mode voltage and load current at V
CC
= 5 V
12
10
8
6
4
20
18
16
14
-6
-8
-10
-12
-14
-16
-18
-20
-2
-4
2
0
68
53
63
58
Rl=2k W
T=25°C
Iout is positive when current is sourced
48
53
58
63
68
73
78
83
88
1 2
Vicm (V)
3 4
DS13842 - Rev 2 page 13/30
Figure 26. Phase margin vs. capacitive load
TSV772
Typical performance characteristics
Figure 27. Small step response at V
CC
= 5 V
Figure 28. Small step response at V
CC
= 2 V Figure 29. Desaturation from low rail at V
CC
= 5 V
Figure 30. Desaturation from high rail at V
CC
= 5 V Figure 31. Settling time output high to low at V
CC
= 5 V
DS13842 - Rev 2 page 14/30
TSV772
Typical performance characteristics
Figure 32. Settling time output low to high at V
CC
= 5 V Figure 33. Small step overshoot vs. load capacitance
Figure 34. Linearity vs. load resistance at V
CC
= 5 V Figure 35. Noise vs. frequency
Figure 36. Noise vs. time at V
CC
= 5 V
Frequency (Hz)
Figure 37. THD+N vs. frequency
DS13842 - Rev 2 page 15/30
Figure 38. THD+N vs. output voltage
TSV772
Typical performance characteristics
Figure 39. CMRR vs. frequency at V
CC
= 5 V
Figure 40. PSRR vs. frequency at V
CC
= 5 V Figure 41. Turn-on time at V cc
= 5 V
Figure 42. Turn-on time at V
CC
= 2 V
DS13842 - Rev 2 page 16/30
5
5.1
5.2
5.3
TSV772
Application information
Application information
Operating voltages
The TSV772 device can operate from 2.0 to 5.5 V. The parameters are fully specified at 2.0 V, 3.3 V and 5 V power supplies. However, the parameters are very stable over the full V
CC
range and several characterization curves show the TSV772 device characteristics over the full operating range. Additionally, the main specifications are guaranteed in extended temperature range from -40 to 125 °C.
The TSV772 device is rail-to-rail input and output and features two input transistor pairs, allowing the op amp to operate over all the common mode range, from V cc-
- 0.2 V, to V cc+
+ 0.1 V. The input pair transition typically occurs at Vcc+ - 1 V, as seen in
Figure 10. Input offset voltage vs. common-mode voltage at V
Figure 11. Input offset voltage vs. common-mode voltage at V
. The precision and dynamic performances are particularly optimized on the low pair, from V cc-
- 0.1 V to V cc+
- 1.8 V, and operating in this V icm
range is advised for the best performance whenever possible. Besides, operating near the pair transition should be avoided when precision is a concern, as CMRR can be lower in these conditions.
Input offset voltage drift over the temperature
The input voltage drift variation over the temperature is defined as the offset variation related to the offset value measured at 25 °C. The operational amplifier is one of the main circuits of the signal conditioning chain, and the amplifier input offset (V io
) is a major contributor to the chain accuracy. The signal chain accuracy at 25 °C can be compensated during the production at the application level. The maximum input voltage drift over the temperature enables the system designer to anticipate the effect of temperature variations.
The maximum input voltage drift overtemperature is computed using the following equation:
(1)
Where T = -40 °C and 125 °C.
The datasheet maximum value is guaranteed by a measurement on a representative sample size ensuring a C pk
(process capability index) greater than 1.3. The absolute worst case value between -40 °C and 125 °C is reported in the datasheet.
Unused channel
When one of the two channels of the TSV772 is not used, it must be properly connected in order to avoid internal oscillations that can negatively impact the signal integrity on the other channel, as well as the current consumption. Two different configurations can be used:
Gain or buffer configuration: the channel can be set in gain, the input can be set to any voltage within the V icm operating range.
Comparator configuration: the channel can be set to a comparator configuration (without negative feedback). In this case, positive and negative inputs can be set to any value provided these values are significantly different
(100 mV or more, to avoid oscillation between positive and negative state and within operating range) and the differential input is lower than the maximum specified in the operating range.
DS13842 - Rev 2 page 17/30
5.4
TSV772
EMI rejection
EMI rejection
The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI immunity of operational amplifiers. An adverse effect that is common to many op amps is a change in the offset voltage as a result of RF signal rectification. EMIRR is defined in
:
EMIRR = 20 . log
Vin pp
∆ Vio
(2)
The TSV772 has been specially designed to minimize susceptibility to EMIRR and shows a low sensitivity. As can be seen in
Figure 43. EMIRR on In+, In- and Out pins
, EMI rejection ratio has been measured on both inputs and output, from 400 MHz to 2.4 GHz.
Figure 43. EMIRR on In+, In- and Out pins
5.5
EMIRR performances might be improved by adding small capacitances (in the pF range) on the inputs, power supply and output pins.
These capacitances help to minimize the impedance of these nodes at high frequencies.
Maximum power dissipation
The usable output load current drive is limited by the maximum power dissipation allowed by the device package.
The absolute maximum junction temperature for the TSV772 is 150 °C. The junction temperature can be estimated as follows:
TJ = PD × θJA + TA (3)
T
J
is the die junction temperature
P
D
is the power dissipated in the package
θ
JA
is the junction-to-ambient thermal resistance of the package
T
A
is the ambient temperature
The power dissipated in the package P
D
is the sum of the quiescent power dissipated and the power dissipated by the output stage transistor. It is calculated as follows:
P
P
D
D
= V
= V
CC
CC
× I
× I
CC
CC
+ V
CC +
− V
OUT
+ V
OUT
− V
CC −
× ILoad
× ILoad
when the op amp is sourcing the current.
when the op amp is sinking the current.
Do not exceed the 150 °C maximum junction temperature for the device. Exceeding the junction temperature limit can cause degradation in the parametric performance or even destroy the device.
DS13842 - Rev 2 page 18/30
5.6
TSV772
Capacitive load and stability
Capacitive load and stability
Stability analysis must be performed for large capacitive loads over 47 pF; increasing the load capacitance to high values produces gain peaking in the frequency response, with overshoot and ringing in the step response.
Generally, unity gain configuration is the worst situation for stability and the ability to drive large capacitive loads.
For additional capacitive load drive capability in unity-gain configuration, stability can be improved by inserting a small resistor R
ISO
(10 Ω to 33 Ω) in series with the output (see
loads. However, if there is a resistive load in parallel with the capacitive load, a voltage divider is created introducing a gain error at the output and slightly reducing the output swing. The error introduced is proportional to the ratio R
ISO
/ R
L
. R
ISO
modifies the maximum capacitive load acceptable from a stability point of view, as
described in Figure 44. Test configuration for R
:
Figure 44. Test configuration for R
ISO
5.7
Please note that R
ISO
= 33 Ω is sufficient to make the TSV772 stable whatever the capacitive load.
Resistor values for high speed op amp design
Due to its high gain bandwidth product (GBP), this op amp is particularly sensitive to parasitic impedances.
Board parasitics should be taken into account in any sensitive design. Indeed, excessive parasitic (both capacitive and inductive) in the op amp frequency range can alter performances and stability. These issues can often be mitigated by lowering the resistive impedances. More specifically, the RC network created by the schematic resistors (Rf and Rg) and the parasitic capacitances of both the op amp (as documented in Table 1 to Table 5 and illustrated in
Figure 45 ) and the PCB can generate a pole below or in the same order of magnitude than
the closed-loop bandwidth of the circuit. In this case, the feedback circuit is not able to fully play its role at high frequency, and the application can be unstable. This issue can happen when the schematic gain is low (typically <
5), or the device is used in follower mode with a resistor in the feedback. In these cases, it is advised to use a low value feedback resistor (Rf), typically 1 kΩ.
Figure 45. Inverting amplifier configuration with parasitic input capacitances
DS13842 - Rev 2 page 19/30
5.8
TSV772
Settling time
Also, some designs use an input resistor on the positive input, generally of the same value than the input resistance on the negative input. This resistor can be useful to balance the input currents on the positive and negative inputs, and reduce the impact of those input currents on precision. However, this is not useful on the
TSV772 as the input currents are very low. Furthermore, this resistor can also interact with the input capacitances to generate a pole. The frequency of this pole should be kept higher than the closed-loop bandwidth frequency.
The macromodel provided takes into account the circuit parasitic capacitors. Thus, a transient SPICE simulation
(100 mV step) is an easy way to evaluate the stability of the application. However, this cannot replace a hardware evaluation of the application circuit.
Settling time
Settling time in an application can be defined as the amount of time between the input changes, and the output reaching its final value. It is usually defined with a given tolerance, so the output stability is reached when the output stays within the given range around the final value. In Figure 30 and Figure 31, the settling time is measured in an inverting configuration, using the so-called “false summing node” circuit.
Figure 46. Settling time measurement configuration
5.9
5.10
This circuit is used with a step input voltage from a positive or negative value, to 0 V. The measurement point being (V in
+ V out
) / 2, and V out
being in an ideal circuit equal to V in
; the measurement point gives half of the error on V out
, comparatively to V in
. This error is compared to the tolerance, 0.1% for this circuit, to deduce the settling time. This characteristic is particularly useful when driving an ADC. It is related to the slew rate, GBP and stability of the circuit. It also varies with the circuit gain, the circuit load, and the input voltage step value. However, computing the value of the settling time in a given configuration is not straightforward. The macromodel can give a good estimation, but prototyping can be needed for fine circuit optimization.
PCB layout recommendations
Particular attention must be paid to the layout of the PCB tracks connected to the amplifier, load, and power supply. The power and ground traces are critical as they must provide adequate energy and grounding for all circuits. The best practice is to use short and wide PCB traces to minimize voltage drops and parasitic inductance. In addition, to minimizing parasitic impedance over the entire surface, a multi-via technique that connects the bottom and top layer ground planes together in many locations is often used. The copper traces that connect the output pins to the load and supply pins should be as wide as possible to minimize trace resistance.
Decoupling capacitor
In order to ensure op amp full functionality, it is mandatory to place a decoupling capacitor of at least 22 nF as close as possible to the op amp supply pins. A good decoupling helps to reduce electromagnetic interference impact.
DS13842 - Rev 2 page 20/30
5.11
TSV772
Macro model
Macro model
Accurate macromodels of the TSV772 device are available on the STMicroelectronics’ website at: www.st.com.
These models are a trade-off between accuracy and complexity (that is, time simulation) of the TSV772 operational amplifier. They emulate the nominal performance of a typical device within the specified operating conditions mentioned in the datasheet. They also help to validate a design approach and to select the right operational amplifier, but they do not replace on-board measurements.
DS13842 - Rev 2 page 21/30
6
6.1
TSV772
Typical applications
Typical applications
Low-side current sensing
Power management mechanisms are found in most electronic systems. Current sensing is useful for protecting applications. The low-side current sensing method consists of placing a sense resistor between the load and the circuit ground. The resulting voltage drop is amplified using the TSV772 (see
Figure 47. Low-side current sensing schematic ).
Figure 47. Low-side current sensing schematic
6.2
V out
can be expressed as follows:
VOut = Rsℎunt . I 1 −
− Vio . 1 +
Rf1
Rg1
Rg2
Rg2 + Rf2 . 1 +
Rf1
Rg1 + Ip .
Rg2 . Rf2
Rg2 + Rf2 . 1 +
Rf1
Rg1 − In . Rf1
Assuming that R f2
= R f1
= R f
and R g2
= R g1
= R g
, this equation can be simplified as follows:
(4)
VOut = Rsℎunt . I .
Rf
Rg − Vio . 1 +
Rf
Rg + Rf . Iio
(5)
The main advantage of using the TSV772 for a low-side current sensing relies on its low V io
, compared to general purpose operational amplifiers. For the same current and targeted accuracy, the shunt resistor can be chosen with a lower value, resulting in lower power dissipation, lower drop in the ground path, and lower cost. Particular attention must be paid to the matching and precision of R g1
, R measurement.
g2
, R f1
, and R f2
, to maximize the accuracy of the
Photodiode transimpedance amplification
The TSV7722, with high bandwidth and slew rate, is well suited for photodiode signal conditioning in a transimpedance amplifier circuit. This application is useful in high performance UV sensors, smoke detectors or particle sensors.
DS13842 - Rev 2 page 22/30
DS13842 - Rev 2
TSV772
Photodiode transimpedance amplification
Figure 48. Photodiode transimpedance amplifier circuit
The transimpedance amplifier circuit converts the small photodiode output current in the nA range, into a voltage
signal readable by an ADC following Eq. (6) :
Vout = Rf . Ipℎotodiode (6)
The feedback resistance is usually in the MΩ range, in order to get a large enough voltage output range.
However, together with the diode parasitic capacitance, the op amp input capacitances and the PCB stray capacitance, this feedback network creates a pole that makes the circuit oscillate. Using a small (few pF) capacitor in parallel with the feedback resistor is mandatory to stabilize the circuit. The value of this capacitor can be tuned to optimize the application settling time with a SPICE simulation using the op amp macromodel, or by prototyping.
For more details on tuning this circuit, please read the application note AN4451.
page 23/30
7
7.1
TSV772
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
DFN8 2x2 package information
Figure 49. DFN8 2x2 package outline
DS13842 - Rev 2
Ref.
A
A1
A3 b
D
D2
E
E2 e
L ddd
Min.
0.51
0.18
1.85
1.45
1.85
0.75
0.225
Table 7. DFN8 2x2 package mechanical data
Dimensions
Millimeters
Typ.
0.55
Max.
0.60
0.05
Min.
0.020
0.15
0.25
2.00
1.60
2.00
0.90
0.50
0.325
0.30
2.15
1.70
2.15
1.00
0.425
0.08
0.007
0.073
0.057
0.073
0.030
0.009
Inches
Typ.
0.022
0.006
0.010
0.079
0.063
0.079
0.035
0.020
0.013
Max.
0.024
0.002
0.012
0.085
0.067
0.085
0.039
0.017
0.003
page 24/30
Figure 50. DFN8 2x2 recommended footprint
TSV772
DFN8 2x2 package information
DS13842 - Rev 2 page 25/30
7.2
SO8 package information
Figure 51. SO8 package outline
TSV772
SO8 package information
DS13842 - Rev 2
Dim.
L
L1 k ccc
E1 e h
A
A1
A2 b c
D
E
0.1
1.25
0.28
0.17
4.8
5.8
3.8
Min.
0.25
0.4
0 mm
4.9
6
3.9
1.27
Typ.
Table 8. SO-8 mechanical data
Inches
Min.
Max.
1.75
0.25
0.48
0.23
5
6.2
4
0.004
0.049
0.011
0.007
0.189
0.228
0.15
0.5
1.27
0.01
0.016
1.04
8 °
0.1
1 °
Typ.
0.193
0.236
0.154
0.05
0.04
Max.
0.069
0.01
0.019
0.01
0.197
0.244
0.157
0.02
0.05
8 °
0.004
page 26/30
8
TSV772
Ordering information
Ordering information
Table 9. Order code
Order code
TSV772IQ2T
TSV772IST
TSV772IDT
TSV772IYST
TSV772IYDT
Temperature range
-40 to +125 °C
-40 to +125 °C Automotive grade
Package
DFN8 2x2
MiniSO8
SO8
MiniSO8
SO8
Marking
K5R
K5R
TSV772I
K231
TSV772Y
1. Qualification and characterization according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC
Q001 & Q 002 or equivalent are on-going.
DS13842 - Rev 2 page 27/30
Revision history
Date
12-Oct-2021
25-Nov-2021
Revision
1
2
Table 10. Document revision history
Changes
Initial release.
Updated CDM value in Table 2 and
.
TSV772
DS13842 - Rev 2 page 28/30
TSV772
Contents
Contents
DS13842 - Rev 2 page 29/30
TSV772
IMPORTANT NOTICE – PLEASE READ CAREFULLY
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2021 STMicroelectronics – All rights reserved
DS13842 - Rev 2 page 30/30
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