STMicroelectronics TSU104 Datasheet
STMicroelectronics TSU101 offers ultra-low power consumption, making it ideal for long-life battery-powered applications. With a supply voltage range of 1.5V to 5.5V and a typical current consumption of 580nA per channel at 1.8V, it's perfect for power-sensitive designs. Its unity gain stability, rail-to-rail input and output, and fast desaturation make it suitable for various applications, including battery-powered devices, sensor signal conditioning, and portable electronics.
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TSU101, TSU102, TSU104
Nanopower, rail-to-rail input and output, 5 V CMOS operational amplifiers
Datasheet - production data
Features
•
Submicro ampere current consumption:
580 nA typ per channel at 25 °C at
V
CC
= 1.8 V
•
Low supply voltage: 1.5 V - 5.5 V
•
Unity gain stable
•
Rail-to-rail input and output
•
Gain bandwidth product: 8 kHz typ
•
Low input bias current: 5 pA max at 25 °C
•
High tolerance to ESD: 2 kV HBM
•
Industrial temperature range:
-40 °C to 85 °C
Benefits
•
42 years of typical equivalent lifetime
(for TSU101) if supplied by a 220 mAh coin type Lithium battery
•
Tolerance to power supply transient drops
•
Accurate signal conditioning of high impedance sensors
•
Application performances guaranteed over industrial temperature range
•
Fast desaturation
Applications
•
Ultra long life battery-powered applications
•
Power metering
•
UV and photo sensors
•
Electrochemical and gas sensors
•
Pyroelectric passive infrared (PIR) detection
•
Battery current sensing
•
Medical instrumentation
•
RFID readers
Description
The TSU101, TSU102, and TSU104 operational amplifiers offer an ultra low-power consumption of 580 nA typical and 750 nA maximum per channel when supplied by 1.8 V. Combined with a supply voltage range of 1.5 V to 5.5 V, these features allow the TSU10x series to be efficiently supplied by a coin type Lithium battery or a regulated voltage in low-power applications.
The 8 kHz gain bandwidth of these devices make them ideal for sensor signal conditioning, battery supplied, and portable applications.
September 2015 DocID024317 Rev 3
This is information on a product in full production.
1/33
www.st.com
Contents TSU101, TSU102, TSU104
Contents
1 Package pin connections ................................................................ 3
2 Absolute maximum ratings and operating conditions ................. 4
3 Electrical characteristics ................................................................ 5
4 Application information ................................................................ 17
Operating voltages .......................................................................... 17
Input offset voltage drift over temperature ....................................... 17
Long term input offset voltage drift .................................................. 18
Schematic optimization aiming for nanopower ................................ 19
PCB layout considerations .............................................................. 20
Using the TSU10x series with sensors ............................................ 20
Fast desaturation ............................................................................ 22
Using the TSU10x series in comparator mode ................................ 22
ESD structure of TSU10x series ..................................................... 22
5 Package information ..................................................................... 23
SC70-5 (or SOT323-5) package information ................................... 24
SOT23-5 package information ........................................................ 25
DFN8 2x2 package information ....................................................... 26
MiniSO8 package information ......................................................... 27
QFN16 3x3 package information ..................................................... 28
TSSOP14 package information ....................................................... 30
6 Ordering information ..................................................................... 31
7 Revision history ............................................................................ 32
2/33 DocID024317 Rev 3
TSU101, TSU102, TSU104
1 Package pin connections
Package pin connections
Figure 1: Pin connections for each package (top view)
DocID024317 Rev 3 3/33
Absolute maximum ratings and operating conditions
2
TSU101, TSU102, TSU104
Absolute maximum ratings and operating conditions
Symbol
V
CC
V id
V in
I in
Table 1: Absolute maximum ratings (AMR)
Parameter
(V
CC-
Value
6
±V
CC
) - 0.2 to (V
10
CC+
) + 0.2
T stg
T j
Storage temperature
Maximum junction temperature
SC70-5
SOT23-5
-65 to 150
150
205
250
R thja
Thermal resistance junction to
DFN8 2x2
MiniSO8
QFN16 3x3
TSSOP14
117
190
45
100
2000
200
ESD
All other packages except SC70-5
SC70-5
1000
900
200
Notes:
(1)
All voltage values, except the differential voltage are with respect to the network ground terminal.
(2)
The differential voltage is the non-inverting input terminal with respect to the inverting input terminal.
(3)
((V
CC+
) - V in
) must not exceed 6 V, (V in
- V
CC-
) must not exceed 6 V.
(4)
The input current must be limited by a resistor in series with the inputs.
(5)
R th
are typical values.
(6)
Short-circuits can cause excessive heating and destructive dissipation.
(7)
Related to ESDA/JEDEC JS-001 Apr. 2010
(8)
Related to JEDEC JESD22-A115C Nov.2010
(9)
Related to JEDEC JESD22-C101-E Dec. 2009
(10)
Related to JEDEC JESD78C Sept. 2010
Symbol
Table 2: Operating conditions
Parameter Value
Unit
V mA
°C
°C/W
V mA
Unit
V
CC
V icm
T oper
Supply voltage
Common mode input voltage range
Operating free air temperature range
1.5 to 5.5
(V
CC-
) - 0.1 to (V
CC+
) + 0.1
-40 to 85
V
°C
4/33 DocID024317 Rev 3
TSU101, TSU102, TSU104
Electrical characteristics
3
Symbol
V io
ΔV io
/ΔT
Input offset voltage drift
ΔV io
Long-term input offset voltage drift
I io
I ib
CMR
A vd
V
OH
V
OL
I out
I
CC
Electrical characteristics
Table 3: Electrical characteristics at VCC+ = 1.8 V with VCC- = 0 V, Vicm = VCC/2,
Tamb = 25 °
C, and RL = 1 MΩ connected to VCC/2 (unless otherwise specified)
Parameter Conditions Min. Typ. Max. Unit
DC performance
Input offset voltage
Common mode rejection ratio 20 log (ΔV icm
/ΔV io
)
Large signal voltage gain
High level output voltage,
(drop from V
CC+
)
Low level output voltage
Output sink current
Output source current
Supply current,
(per channel)
-40 °C < T< 85 °C
-40 °C < T< 85 °C
-40 °C < T< 85 °C
-40 °C < T< 85 °C
V icm
= 0 to 0.6 V, V out
= V
CC
/2
-40 °C < T< 85 °C
V icm
= 0 to 1.8 V, V out
= V
CC
/2
-40 °C < T< 85 °C
V out
= 0.3 V to ((V
CC+
) - 0.3 V),
R
L
= 100 kΩ
-40 °C < T< 85 °C
R
L
= 100 kΩ
-40 °C < T< 85 °C
R
L
= 100 kΩ
-40 °C < T< 85 °C
V out
= V
CC
, V
ID
= -200 mV
-40 °C < T< 85 °C
V out
= 0 V, V
ID
= 200 mV
-40 °C < T< 85 °C
No load, V out
= V
CC
/2
-40 °C < T< 85 °C
AC performance
-3
-3.4
4
4
4
4
65
65
55
55
95
95
0.1
0.18
1
1
85
74
115
5
5
580
3
3.4
5
750
800
40
40
40
40
5
30
5
30 mV
μV/°C
µV/
√month pA dB mV mA nA
GBP
F u ϕ m
G m
Gain bandwidth product
Unity gain frequency
Phase margin
Gain margin
R
L
= 1
MΩ, C
L
= 60 pF
8
8
60
10 kHz
Degrees dB
SR e n
Slew rate (10 % to 90 %)
Equivalent input noise voltage
R
L
= 1
MΩ, C
L
= 60 pF
V out
= 0.3 V to ((V
CC+
) - 0.3 V) f = 100 Hz f = 1 kHz
3
265
265
V/ms nV/√Hz
DocID024317 Rev 3 5/33
Electrical characteristics
Symbol Parameter
∫e n i n t rec
Low-frequency peak-topeak input noise
Equivalent input noise current
Overload recovery time
Conditions
Bandwidth: f = 0.1 to 10 Hz f = 100 Hz f = 1 kHz
100 mV from rail in comparator,
R
L
= 100 kΩ, V
ID
= ±V
CC
,
-40 °C < T< 85 °C
TSU101, TSU102, TSU104
Min. Typ. Max. Unit
µV pp
9
0.64
4.4 fA/√Hz
30 µs
Notes:
(1)
Typical value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using the Arrhenius law and assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration.
(2)
Guaranteed by design.
6/33 DocID024317 Rev 3
TSU101, TSU102, TSU104
Electrical characteristics
Table 4: Electrical characteristics at VCC+ = 3.3 V with VCC- = 0 V, Vicm = VCC/2,
Tamb = 25 °
C, and RL = 1 MΩ connected to VCC/2 (unless otherwise specified)
Symbol Parameter Conditions Min. Typ. Max. Unit
DC performance
V io
Input offset voltage
ΔV io
/ΔT
Input offset voltage drift
ΔV io
Long-term input offset voltage drift
-40 °C < T< 85 °C
-40 °C < T< 85 °C
-3
-3.4
0.1
0.36
3
3.4
5 mV
μV/°C
µV/
√month
I io
I ib
CMR
A vd
V
OH
V
OL
I out
I
CC
Common mode rejection ratio 20 log (ΔV icm
/ΔV io
)
Large signal voltage gain
High level output voltage
(drop from V
CC+
)
Low level output voltage
Output sink current
Output source current
Supply current,
(per channel)
-40 °C < T< 85 °C
-40 °C < T< 85 °C
V icm
= 0 to 2.1 V, V out
= V
CC
/2
-40 °C < T< 85 °C
V icm
= 0 to 3.3 V, V out
= V
CC
/2
-40 °C < T< 85 °C
V out
= 0.3 V to ((V
CC+
) - 0.3 V),
R
L
= 100 kΩ
-40 °C < T< 85 °C
R
L
= 100 kΩ
-40 °C < T< 85 °C
R
L
= 100 kΩ
-40 °C < T< 85 °C
V out
= V
CC
, V
ID
= -200 mV
-40 °C < T< 85 °C
V out
= 0 V, V
ID
= 200 mV
-40 °C < T< 85 °C
No load, V out
= V
CC
/2
-40 °C < T< 85 °C
AC performance
6
8
8
6
70
70
60
60
105
105
1
1
92
77
120
9
11
600
40
40
40
40
800
850
5
30
5
30 pA dB mV mA nA
GBP
F u ϕ m
G m
Gain bandwidth product
Unity gain frequency
Phase margin
Gain margin
R
L
= 1
MΩ, C
L
= 60 pF
8
8
60
11 kHz
Degrees dB
SR e n
Slew rate (10 % to 90 %)
Equivalent input noise voltage
R
L
= 1
MΩ, C
L
= 60 pF,
V out
= 0.3 V to ((V
CC+
) - 0.3 V) f = 100 Hz f = 1 kHz
3
260
255
V/ms nV/√Hz
∫e n
Low-frequency peak-topeak input noise
Bandwidth: f = 0.1 to 10 Hz 8.6 µV pp
DocID024317 Rev 3 7/33
Electrical characteristics
Symbol
i n t rec
Parameter
Equivalent input noise current
Overload recovery time
Conditions
f = 100 Hz f = 1 kHz
100 mV from rail in comparator,
R
L
= 100 kΩ, V
ID
= ±V
CC
,
-40 °C < T< 85 °C
TSU101, TSU102, TSU104
Min. Typ. Max.
0.55
3.8
Unit
fA/√Hz
30 µs
Notes:
(1)
Typical value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using the Arrhenius law and assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration.
(2)
Guaranteed by design.
8/33 DocID024317 Rev 3
TSU101, TSU102, TSU104
Electrical characteristics
Table 5: Electrical characteristics at VCC+ = 5 V with VCC- = 0 V, Vicm = VCC/2,
Tamb = 25 °
C, and RL = 1 MΩ connected to VCC/2 (unless otherwise specified)
Symbol Parameter Conditions Min. Typ. Max. Unit
DC performance
V io
Input offset voltage
ΔV io
/ΔT
Input offset voltage drift
ΔV io
Long-term input offset voltage drift
-40 °C < T< 85 °C
-40 °C < T< 85 °C
-3
-3.4
0.1
1.1
3
3.4
5 mV
μV/°C
µV/
√month
I io
I ib
CMR
SVR
A vd
V
OH
V
OL
I out
I
CC
Common mode rejection ratio 20 log (ΔV icm
/ΔV io
)
Supply voltage rejection ratio
Large signal voltage gain
High level output voltage,
(drop from V
CC+
)
Low level output voltage
Output sink current
Output source current
Supply current,
(per channel)
-40 °C < T< 85 °C
-40 °C < T< 85 °C
V icm
= 0 to 3.8 V, V out
= V
CC
/2
-40 °C < T< 85 °C
V icm
= 0 to 5 V, V out
= V
CC
/2
-40 °C < T< 85 °C
V
CC
= 1.5 to 5.5 V, V icm
= 0 V
-40 °C < T< 85 °C
V out
= 0.3 V to ((V cc+
) - 0.3 V),
R
L
= 100 kΩ
-40 °C < T< 85 °C
R
L
= 100 kΩ
-40 °C < T< 85 °C
R
L
= 100 kΩ
-40 °C < T< 85 °C
V out
= V
CC
, V
ID
= -200 mV
-40 °C < T< 85 °C
V out
= 0 V, V
ID
= 200 mV
-40 °C < T< 85 °C
No load, V out
= V
CC
/2
-40 °C < T< 85 °C
AC performance
70
70
65
65
70
70
110
110
6
6
8
8
1
1
90
82
90
130
9
11
650 850
950
40
40
40
40
5
30
5
30 pA dB mV mA nA
GBP
F u ϕ m
G m
Gain bandwidth product
Unity gain frequency
Phase margin
Gain margin
R
L
= 1
MΩ, C
L
= 60 pF
9
8.6
60
12 kHz
Degrees dB
SR e n
Slew rate (10 % to 90 %)
Equivalent input noise voltage
R
L
= 1
MΩ, C
L
= 60 pF,
V out
= 0.3 V to ((V
CC+
) - 0.3 V) f = 100 Hz f = 1 kHz
3
240
225
V/ms nV√Hz
DocID024317 Rev 3 9/33
Electrical characteristics
Symbol Parameter Conditions
TSU101, TSU102, TSU104
Min. Typ. Max. Unit
∫e n
Low-frequency peak-to-peak input noise
Bandwidth: f = 0.1 to 10 Hz 8.1 µV pp i n t rec
Equivalent input noise current f = 100 Hz 0.18
EMIRR
Overload recovery time
Electromagnetic interference rejection
f = 1 kHz
100 mV from rail in comparator,
R
L
= 100 kΩ, V
ID
= ±V
CC
,
-40 °C < T< 85 °C
V in
= -10 dBm, f = 400 MHz
V in
= -10 dBm, f = 900 MHz
V in
= -10 dBm, f = 1.8 GHz
V in
= -10 dBm, f = 2.4 GHz
3.5
30
73
88
80
80 fA√Hz
µs dB
Notes:
(1)
Typical value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using the Arrhenius law and assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration.
(2)
Guaranteed by design.
(3)
Based on evaluations performed only in conductive mode.
10/33 DocID024317 Rev 3
TSU101, TSU102, TSU104
Figure 2: Supply current vs. supply voltage
Electrical characteristics
Figure 3: Supply current vs. input common mode voltage
Figure 4: Supply current in saturation mode
0.5
0.3
0.1
0.9
0.7
Temperature
85°C/65°C/45°C/25°C/-5°C/-40°C
Vcc=3.3V
Follower configuration
Figure 5: Input offset voltage distribution
Input voltage (mV)
Figure 6: Input offset voltage vs common mode voltage Figure 7: Input offset voltage vs temperature at 3.3 V supply voltage
DocID024317 Rev 3 11/33
Electrical characteristics
Figure 8: Input offset voltage temperature coefficient distribution
TSU101, TSU102, TSU104
Figure 9: Input bias current vs. temperature at mid VICM
Figure 10: Input bias current vs. temperature at low VICM
Figure 11: Input bias current vs. temperature at high VICM
Figure 12: Output characteristics at 1.8 V supply voltage
Figure 13: Output characteristics at 3.3 V supply voltage
12/33 DocID024317 Rev 3
TSU101, TSU102, TSU104
Figure 14: Output characteristics at 5 V supply voltage
Electrical characteristics
Figure 15: Output voltage vs. input voltage close to the rails
Temperature
85°C/65°C/45°C/25°C/-5°C/-40°C
Figure 16: Output saturation with a sine wave on input
Vcc=3.3V
Follower configuration
Input voltage (mV)
Figure 17: Desaturation time
Figure 18: Phase reversal free Figure 19: Slew rate vs. supply voltage
DocID024317 Rev 3 13/33
Electrical characteristics
Figure 20: Output swing vs. input signal frequency
TSU101, TSU102, TSU104
Figure 21: Triangulation of a sine wave
Figure 22: Large signal response at 3.3 V supply voltage
Figure 23: Small signal response at 3.3 V supply voltage
Figure 24: Overshoot vs. capacitive load at 3.3 V supply voltage
Figure 25: Phase margin vs. capacitive load at 3.3 V supply voltage
14/33 DocID024317 Rev 3
TSU101, TSU102, TSU104
Figure 26: Bode diagram for different feedback values
Electrical characteristics
Figure 27: Bode diagram at 1.8 V supply voltage
Figure 28: Bode diagram at 3.3 V supply voltage Figure 29: Bode diagram at 5 V supply voltage
Figure 30: Gain bandwidth product vs. input common mode voltage
Figure 31: In-series resistor (Riso) vs. capacitive load
DocID024317 Rev 3 15/33
Electrical characteristics
Figure 32: Noise at 1.8 V supply voltage in follower configuration
TSU101, TSU102, TSU104
Figure 33: Noise at 3.3 V supply voltage in follower configuration
Figure 34: Noise at 5 V supply voltage in follower configuration
Figure 35: Noise amplitude on 0.1 to 10 Hz frequency range
16/33
Figure 36: Channel separation on TSU102
Figure 37: Channel separation on TSU104
DocID024317 Rev 3
TSU101, TSU102, TSU104
4
4.1
4.2
4.3
Application information
Application information
Operating voltages
The TSU101, TSU102, and TSU104 series of amplifiers can operate from 1.5 V to 5.5 V.
Their parameters are fully specified at 1.8 V, 3.3 V, and 5 V supply voltages and are very stable in the full V
CC
range. Additionally, main specifications are guaranteed on the industrial temperature range from -40 to 85 ° C.
Rail-to-rail input
The TSU101, TSU102, and TSU104 series is built with two complementary PMOS and
NMOS input differential pairs. Thus, these devices have a rail-to-rail input, and the input common mode range is extended from (V
CC-
) - 0.1 V to (V
CC+
) + 0.1 V.
The devices have been designed to prevent phase reversal behavior.
Input offset voltage drift over temperature
The maximum input voltage drift over the temperature variation is defined as the offset variation related to the offset value measured at 25 °C. The operational amplifier is one of the main circuits of the signal conditioning chain, and the amplifier input offset is a major contributor to the chain accuracy. The signal chain accuracy at 25 °C can be compensated during production at application level. The maximum input voltage drift over temperature enables the system designer to anticipate the effects of temperature variations.
The maximum input voltage drift over temperature is computed using
Equation 1
∆V
∆T io
= ma x
V io
T
– io
(
25
T – 25 °C
°C
) with T = -40 °C and 85 °C.
The datasheet maximum value is guaranteed by measurements on a representative sample size ensuring a C pk
(process capability index) greater than 2.
DocID024317 Rev 3 17/33
Application information
4.4
TSU101, TSU102, TSU104
Long term input offset voltage drift
To evaluate product reliability, two types of stress acceleration are used:
•
Voltage acceleration, by changing the applied voltage
•
Temperature acceleration, by changing the die temperature (below the maximum junction temperature allowed by the technology) with the ambient temperature.
The voltage acceleration has been defined based on JEDEC results, and is defined using
Equation 2
A
FV
= e
S
– V
U
)
Where:
A
FV
is the voltage acceleration factor b is the voltage acceleration constant in 1/V, constant technology parameter (β = 1)
V
S
is the stress voltage used for the accelerated test
V
U
is the voltage used for the application
The temperature acceleration is driven by the Arrhenius model, and is defined in
Equation 3
A
FT
= e
E k
.
1
T
U
–
1
T
S
Where:
A
FT
is the temperature acceleration factor
E a
is the activation energy of the technology based on the failure rate k is the Boltzmann constant (8.6173 x 10
-5
eVk
-1
)
T
U
is the temperature of the die when V
U
is used (°K)
T
S
is the temperature of the die under temperature stress (°K)
The final acceleration factor, A
F
, is the multiplication of the voltage acceleration factor and
the temperature acceleration factor (
Equation 4
A
F
=
A
FT
× A
FV
A
F is calculated using the temperature and voltage defined in the mission profile of the product. The A
F
to calculate the number of months of
use equivalent to 1000 hours of reliable stress duration.
Equation 5
Months
=
A
F
× 1000 h × 12 months /
(
24 h × 365.25 days
)
18/33 DocID024317 Rev 3
TSU101, TSU102, TSU104
Application information
To evaluate the op-amp reliability, a follower stress condition is used where V
CC
is defined as a function of the maximum operating voltage and the absolute maximum rating
(as recommended by JEDEC rules).
The V io
drift (in µV) of the product after 1000 h of stress is tracked with parameters at
different measurement conditions (see
Equation 6
V
CC
= maxV op with V icm
= V
CC
/
2
The long term drift parameter (ΔV io
), estimating the reliability performance of the product, is obtained using the ratio of the V io
(input offset voltage value) drift over the square root of
the calculated number of months (
Equation 7
∆V io
=
V io dr ift
( month s
) where V io
drift is the measured drift value in the specified test conditions after 1000 h stress duration.
4.5 Schematic optimization aiming for nanopower
To benefit from the full performance of the TSU10 series, the impedances must be maximized so that current consumption is not lost where it is not required.
For example, an aluminum electrolytic capacitance can have significantly high leakage.
This leakage may be greater than the current consumption of the op-amp. For this reason, ceramic type capacitors are preferred.
For the same reason, big resistor values should be used in the feedback loop. However, there are three main limitations to be considered when choosing a resistor.
1. When the TSU10x series is used with a sensor: the resistance connected between the sensor and the input must remain much higher than the impedance of the sensor itself.
2.
Noise generated: a 100 kΩ resistor generates 40 nV/√Hz, a bigger resistor value generates even more noise.
3. Leakage on the PCB: leakage can be generated by moisture. This can be improved by using a specific coating process on the PCB.
DocID024317 Rev 3 19/33
Application information
4.6
TSU101, TSU102, TSU104
PCB layout considerations
For correct operation, it is advised to add 10 nF decoupling capacitors as close as possible to the power supply pins.
Minimizing the leakage from sensitive high impedance nodes on the inputs of the TSU10x series can be performed with a guarding technique. The technique consists of surrounding high impedance tracks by a low impedance track (the ring). The ring is at the same electrical potential as the high impedance node.
Therefore, even if some parasitic impedance exists between the tracks, no leakage current
can flow through them as they are at the same potential (see
Figure 38: Guarding on the PCB
4.7 Using the TSU10x series with sensors
The TSU10x series has MOS inputs, thus input bias currents can be guaranteed down to
5 pA maximum at ambient temperature. This is an important parameter when the operational amplifier is used in combination with high impedance sensors.
The TSU101, TSU102, and TSU104 series is perfectly suited for trans-impedance
Figure 39: "Trans-impedance amplifier schematic"
configuration allows a current to be converted into a voltage value with a gain set by the user. It is an ideal choice for portable electrochemical gas sensing or photo/UV sensing applications. The TSU10x series, using trans-impedance configuration, is able to provide a voltage value based on the physical parameter sensed by the sensor.
20/33 DocID024317 Rev 3
TSU101, TSU102, TSU104
Application information
Electrochemical gas sensors
The output current of electrochemical gas sensors is generally in the range of tens of nA to hundreds of µA. As the input bias current of the TSU101, TSU102, and TSU104 is very low
) compared to these current values, the TSU10x
series is well adapted for use with the electrochemical sensors of two or three electrodes.
Figure 40: "Potentiostat schematic using the TSU101 (or TSU102)"
(electronic hardware required to control a three-electrode cell) schematic using the
TSU101, TSU102, and TSU104. In such a configuration, the devices minimize leakage in the reference electrode compared to the current being measured on the working electrode.
Figure 39: Trans-impedance amplifier schematic
Figure 40: Potentiostat schematic using the TSU101 (or TSU102)
DocID024317 Rev 3 21/33
Application information
TSU101, TSU102, TSU104
4.8 Fast desaturation
When the TSU101, TSU102, and TSU104 operational amplifiers go into saturation mode, they take a short period of time to recover, typically thirty microseconds. When recovering after saturation, the TSU10x series does not exhibit any voltage peaks that could generate
issues (such as false alarms) in the application (see
internal gain of the amplifier decreases smoothly when the output signal gets close to the
V
CC+
or V
CC-
Thus, to maintain signal integrity, the user should take care that the output signal stays at
100 mV from the supply rails.
With a trans-impedance schematic, a voltage reference can be used to keep the signal away from the supply rails.
4.9 Using the TSU10x series in comparator mode
The TSU10x series can be used as a comparator. In this case, the output stage of the
device always operates in saturation mode. In addition,
consumption is not bigger and even decreases smoothly close to the rails. The TSU101,
TSU102, and TSU104 are obviously operational amplifiers and are therefore optimized to be used in linear mode. We recommend to use the TS88 series of nanopower comparators if the primary function is to perform a signal comparison only.
4.10 ESD structure of TSU10x series
The TSU101, TSU102, and TSU104 are protected against electrostatic discharge (ESD)
). These diodes must be considered
at application level especially when signals applied on the input pins go beyond the power supply rails (V
CC+
or V
CC-
).
Figure 41: ESD structure
Current through the diodes must be limited to a maximum of 10 mA as stated in
"Absolute maximum ratings (AMR)"
. A serial resistor or a Schottky diode can be used on
the inputs to improve protection but the 10 mA limit of input current must be strictly observed.
22/33 DocID024317 Rev 3
TSU101, TSU102, TSU104
5 Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
is an ST trademark.
DocID024317 Rev 3 23/33
Package information
5.1
TSU101, TSU102, TSU104
SC70-5 (or SOT323-5) package information
Figure 42: SC70-5 (or SOT323-5) package outline
SIDE VIEW
DIMENSIONS IN MM
GAUGE PLANE
COPLANAR LEADS
SEATING PLANE
24/33
Ref.
c
D
E
E1
A
A1
A2 b e e1
L
<
TOP VIEW
Min.
0.80
0.80
0.15
0.10
1.80
1.80
1.15
0.26
0°
Table 6: SC70-5 (or SOT323-5) mechanical data
Dimensions
Millimeters
Typ. Min.
0.315
Inches
Typ.
0.90
2.00
2.10
1.25
0.65
1.30
0.36
Max.
1.10
0.10
1.00
0.30
0.22
2.20
2.40
1.35
0.46
8°
0.315
0.006
0.004
0.071
0.071
0.045
0.010
0°
0.035
0.079
0.083
0.049
0.025
0.051
0.014
Max.
0.043
0.004
0.039
0.012
0.009
0.087
0.094
0.053
0.018
8°
DocID024317 Rev 3
TSU101, TSU102, TSU104
5.2 SOT23-5 package information
Figure 43: SOT23-5 package outline
Package information
Ref.
e
E
F
L
K
A
A1
A2
B
C
D
D1
Min.
0.90
0.90
0.35
0.09
2.80
2.60
1.50
0.10
0 degrees
1.05
0.40
0.15
2.90
1.90
0.95
2.80
1.60
0.35
Table 7: SOT23-5 mechanical data
Dimensions
Millimeters
Typ.
1.20
Min.
0.035
Max.
1.45
0.15
1.30
0.50
0.20
3.00
0.035
0.014
0.004
0.110
3.00
1.75
0.102
0.059
0.60 0.004
10 degrees 0 degrees
Inches
Typ.
0.047
0.041
0.016
0.006
0.114
0.075
0.037
0.110
0.063
0.014
Max.
0.057
0.006
0.051
0.020
0.008
0.118
0.118
0.069
0.024
10 degrees
DocID024317 Rev 3 25/33
Package information
5.3 DFN8 2x2 package information
Figure 44: DFN8 2x2 package outline
TSU101, TSU102, TSU104
26/33
Ref.
D
E e
L
N
A
A1 b
Min.
0.70
0.00
0.15
0.045
Table 8: DFN8 2x2 mechanical data
Dimensions
Millimeters
Typ.
0.75
0.02
0.20
2.00
2.00
0.50
0.55
Max.
0.80
0.05
0.25
0.65
Min.
0.028
0.000
0.006
0.018
8
Inches
Typ.
0.030
0.001
0.008
0.079
0.079
0.020
0.022
DocID024317 Rev 3
Max.
0.031
0.002
0.010
0.026
TSU101, TSU102, TSU104
5.4 MiniSO8 package information
Figure 45: MiniSO8 package outline
Package information
Ref.
L
L1
L2 k
D
E
E1 e ccc
A
A1
A2 b c
Min.
0
0.75
0.22
0.08
2.80
4.65
2.80
0.40
0°
3.00
4.90
3.00
0.65
0.60
0.95
0.25
Table 9: MiniSO8 mechanical data
Dimensions
Millimeters
Typ. Min.
0.85
Max.
1.1
0.15
0.95
0.40
0.23
3.20
5.15
3.10
0.80
0
0.030
0.009
0.003
0.11
0.183
0.11
0.016
0° 8°
0.10
Inches
Typ.
0.033
0.118
0.193
0.118
0.026
0.024
0.037
0.010
Max.
0.043
0.006
0.037
0.016
0.009
0.126
0.203
0.122
0.031
8°
0.004
DocID024317 Rev 3 27/33
Package information
5.5 QFN16 3x3 package information
TSU101, TSU102, TSU104
Figure 46: QFN16 3x3 mm package outline
28/33
The exposed pad is not internally connected and can be set to ground.
DocID024317 Rev 3
TSU101, TSU102, TSU104
Ref.
D2
E
E2 e
L
A
A1
A3 b
D
Min.
0.80
0
0.18
2.90
1.50
2.90
1.50
0.30
Package information
Table 10: QFN16 3x3 mm mechanical data
Dimensions
Millimeters
Typ.
0.90
Max.
1.00
0.05
0.20
Min.
0.031
0
3.00
3.00
0.30
3.10
1.80
3.10
1.80
0.007
0.114
0.059
0.114
0.059
0.50
0.50 0.012
Inches
Typ.
0.035
0.008
0.118
0.118
0.020
Max.
0.039
0.002
0.012
0.122
0.071
0.122
0.071
0.020
Figure 47: QFN16 3x3 mm recommended footprint
DocID024317 Rev 3 29/33
Package information
5.6 TSSOP14 package information
Figure 48: TSSOP14 package outline
TSU101, TSU102, TSU104
30/33
Ref.
E1 e
L
L1 k aaa b c
D
E
A
A1
A2
Min.
0.05
0.80
0.19
0.09
4.90
6.20
4.30
0.45
0°
Table 11: TSSOP14 mechanical data
Dimensions
Millimeters
Typ. Min.
1.00
5.00
6.40
4.40
0.65
0.60
1.00
Max.
1.20
0.15
1.05
0.30
0.20
5.10
6.60
4.50
0.75
0.002
0.031
0.007
0.004
0.193
0.244
0.169
0.018
8°
0.10
0°
Inches
Typ.
0.004
0.039
0.197
0.252
0.173
0.0256
0.024
0.039
Max.
0.047
0.006
0.041
0.012
0.0089
0.201
0.260
0.176
0.030
8°
0.004
DocID024317 Rev 3
TSU101, TSU102, TSU104
6 Ordering information
Order code
TSU101ICT
TSU101ILT
TSU101RICT
TSU101RILT
TSU102IQ2T
TSU102IST
TSU104IQ4T
TSU104IPT
Table 12: Order codes
Temperature range Package
-40 °C to 85 °C
SC70-5
SΟΤ23-5
SC70-5
SΟΤ23-5
DFN8 2x2
MiniSO8
QFN16 3x3
TSSOP14
Ordering information
Packing
Tape and reel
Marking
K22
K160
K24
K169
K24
K160
K160
TSU104I
DocID024317 Rev 3 31/33
Revision history
7
TSU101, TSU102, TSU104
Revision history
Date
Table 13: Document revision history
Revision Changes
16-Apr-2013
02-Jul-2013
04-Sep-2015
1
2
3
Initial release
Added the TSU102 and TSU104 devices and updated the datasheet accordingly.
Added the silhouettes, pin connections, and package information for DFN8 2x2, MiniSO8, QFN16 3x3, and
TSSOP14.
Replaced QFN16 3x3 package information (outline, mechanical data, and footprint).
32/33 DocID024317 Rev 3
TSU101, TSU102, TSU104
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Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.
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ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2015 STMicroelectronics – All rights reserved
DocID024317 Rev 3 33/33
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