STMicroelectronics L6566A Datasheet

L6566A

Multi-mode controller for SMPS with PFC front-end

Datasheet

−

production data

Features

■

■

■

■

■

■

■

■

■

■

■

■

■

Selectable multi-mode operation: fixed frequency or quasi-resonant

Onboard 700 V high-voltage startup

Advanced light load management

Low quiescent current (< 3 mA)

Adaptive UVLO

Line feedforward for constant power capability vs. mains voltage

Pulse-by-pulse OCP, shutdown on overload

(latched or auto-restart)

Transformer saturation detection

Switched supply rail for PFC controller

Latched or auto-restart OVP

Brownout protection

-600/+800 mA totem pole gate-driver with active pull-down during UVLO

SO16N package

Applications

SO16N

■

■

■

■

■

■

Notebook, TV and LCD monitor adapters

High power chargers

PDP/LCD TVs

Consumer appliances, such as DVD players,

VCRs, set-top boxes

IT equipment, games, auxiliary power supplies

Power supplies in excess of 150 W

Figure 1.

Block diagram

HV

V CC

5

Vcc_PFC

1

I charge

6

VREF

10

VOLTAGE

REGULATOR

&

ADAPTIVE UVLO

SS

14

SOFT-START

&

FAULT MNGT

TIME

OUT

COMP

9

LOW CLAMP

& DISABLE

OFF2

VFF

15

OVP

LINE VOLTAGE

FEEDFORWARD

Reference voltages

Internal supply

UVLO

OCP2

V CC

Vth

+

PWM

+

OCP

V CC

+

400 uA IC_LATCH

UVLO_SHF

AC_FAIL

-

+

5.7V

+

-

BURST-MODE

Hiccup-mode

OCP logic

OCP2

-

6.4V

1 mA

7.7V

1.5 V

-

Q

LEB

V CC

14V

OVPL

7

4

OSC 13

MODE/SC 12

50 mV

100 mV

ZCD

11

OSCILLATOR

MODE SELECTION

&

TURN-ON LOGIC

ZERO CURRENT

DETECTOR -

+

OVP

OVERVOLTAGE

PROTECTION

TIME

OUT OVPL

LATCH

S

IC_LATCH

R

Q

OFF2

DRIVER

4.5V

8

16

AC_OK

3 V

15 µA 0.450V

0.485V

-

+

AC_FAIL

UVLO

DISABLE

3

CS

GD

DIS

GND

March 2012

This is information on a product in full production.

Doc ID 13794 Rev 4 1/52 www.st.com

52

4

5

6

7

1

2

Contents

Contents

3

L6566A

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1

Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.1

Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.2

Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.1

High-voltage startup generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.2

Zero current detection and triggering block; oscillator block . . . . . . . . . . 19

5.3

Burst-mode operation at no load or very light load . . . . . . . . . . . . . . . . . . 22

5.4

Adaptive UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.5

PWM control block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.6

PWM comparator, PWM latch and voltage feedforward blocks . . . . . . . . 25

5.7

Hiccup-mode OCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.8

PFC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.9

Latched disable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.10

Soft-start and delayed latched shutdown upon overcurrent . . . . . . . . . . . 31

5.11

OVP block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.12

Brownout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.13

Slope compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5.14

Summary of L6566A power management functions . . . . . . . . . . . . . . . . 38

Application examples and ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

2/52 Doc ID 13794 Rev 4

L6566A

8

9

Contents

Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Doc ID 13794 Rev 4 3/52

List of tables

List of tables

L6566A

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

L6566A light load management features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

L6566A protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

External circuits that determine IC behavior upon OVP and OCP . . . . . . . . . . . . . . . . . . . 44

SO16N dimentions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 9.

Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 10.

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

4/52 Doc ID 13794 Rev 4

L6566A

List of figures

List of figures

Figure 1.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 2.

Typical system block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3.

Pin connection (through top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 4.

Multi-mode operation with QR option active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 5.

High-voltage startup generator: internal schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 6.

Timing diagram: normal power-up and power-down sequences . . . . . . . . . . . . . . . . . . . . 18

Figure 7.

Timing diagram showing short-circuit behavior (SS pin clamped at 5 V) . . . . . . . . . . . . . . 19

Figure 8.

Zero current detection block, triggering block, oscillator block and related logic . . . . . . . . 19

Figure 9.

Drain ringing cycle skipping as the load is gradually reduced . . . . . . . . . . . . . . . . . . . . . . 20

Figure 10.

Operation of ZCD, triggering and oscillator blocks (QR option active) . . . . . . . . . . . . . . . . 22

Figure 11.

Load-dependent operating modes: timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 12.

Addition of an offset to the current sense lowers the burst-mode operation threshold . . . . 24

Figure 13.

Adaptive UVLO block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 14.

Possible feedback configurations that can be used with the L6566A . . . . . . . . . . . . . . . . . 25

Figure 15.

Externally controlled burst-mode operation by driving the COMP pin: timing diagram. . . . 26

Figure 16.

Typical power capability change vs. input voltage in QR flyback converters . . . . . . . . . . . 27

Figure 17.

Left: overcurrent setpoint vs. VFF voltage; right: line feedforward function block. . . . . . . . 28

Figure 18.

Hiccup-mode OCP: timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 19.

Possible interfaces between the L6566A and a PFC controller . . . . . . . . . . . . . . . . . . . . . 31

Figure 20.

Operation after latched disable activation: timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 21.

Soft-start pin operation under different operating conditions and settings . . . . . . . . . . . . . 33

Figure 22.

OVP function: internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 23.

OVP function: timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 24.

Maximum allowed duty cycle vs. switching frequency for correct OVP detection. . . . . . . . 36

Figure 25.

Brownout protection: internal block diagram and timing diagram . . . . . . . . . . . . . . . . . . . . 37

Figure 26.

AC voltage sensing with the L6566A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 27.

Slope compensation waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 28.

Typical low-cost application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 29.

Typical full-feature application schematic (QR operation) . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 30.

Typical full-feature application schematic (FF operation) . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 31.

Frequency foldback at light load (FF operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 32.

Latched shutdown upon mains overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 33.

Package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 34.

Recommended footprint (dimensions are in mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Doc ID 13794 Rev 4 5/52

Description

1 Description

L6566A

The L6566A is an extremely versatile current-mode primary controller IC specifically designed for high-performance offline flyback converters operated from front-end power factor correction (PFC) stages in applications in compliance with EN61000-3-2 or JEITA-

MITI regulations.

Both fixed-frequency (FF) and quasi-resonant (QR) operation are supported. The user can choose either of the two depending on application needs.

The device features an externally programmable oscillator; it defines the converter's switching frequency in FF mode and the maximum allowed switching frequency in QR mode.

When FF operation is selected, the IC works like a standard current-mode controller with a maximum duty cycle limited to 70% (min.).

QR operation, when selected, occurs and is achieved through a transformer demagnetization sensing input that triggers MOSFET turn-on. Under some conditions, ZVS

(zero-voltage switching) can be achieved. The converter's power capability rise with the input voltage is compensated by line voltage feedforward. At medium and light load, as the

QR operating frequency equals the oscillator frequency, a function (valley skipping) is activated to prevent further frequency rise and keep the operation as close to ZVS as possible.

With either FF or QR operation, at very light load the IC enters a controlled burst-mode operation that, along with the built-in non-dissipative high-voltage startup circuit and a reduced quiescent current, helps keep the consumption from the mains low and meet energy saving recommendations.

To allow the meeting of energy saving recommendations in two-stage power-factorcorrected systems as well, the L6566A provides an interface with the PFC controller that enables the re-regulator to be turned off at light load.

An innovative adaptive UVLO helps minimize the issues related to fluctuations in the selfsupply voltage due to transformer parasites.

The protection functions included in this device are: not-latched input undervoltage

(brownout), output OVP (auto-restart or latch-mode selectable), a first-level OCP with delayed shutdown to protect the system during overload or short-circuit conditions (autorestart or latch-mode selectable), and a second-level OCP which is invoked when the transformer saturates or the secondary diode fails short. A latched disable input allows easy implementation of OTP with an external NTC, while an internal thermal shutdown prevents

IC overheating.

Programmable soft-start, leading-edge blanking on the current sense input for greater noise immunity, slope compensation (in FF mode only), and a shutdown function for externally controlled burst-mode operation or remote ON/OFF control are all features of this device.

6/52 Doc ID 13794 Rev 4

L6566A

Figure 2.

Typical system block diagram

PFC PRE-REGULATOR

Rectified

M a in s

Volt a ge

FLYBACK DC-DC CONVERTER

PWM/QR controller i s t u rned off in c as e of PFC' s a nom a lo us oper a tion, for sa fety

L6562A

L656 3S

L6564

L6566A

PFC i s au tom a tic a lly t u rned off a t light lo a d to e as e compli a nce with energy sa ving s pecific a tion s .

V o u tdc

Description

Doc ID 13794 Rev 4 7/52

Pin settings

2.1 Connections

Figure 3.

Pin connection (through top view)

L6566A

8/52

Table 1.

N° Pin

Pin functions

1

2

3

4

HVS

N.C.

GND

GD

Function

High-voltage startup. The pin, able to withstand 700 V, is to be tied directly to the rectified mains voltage. A 1 mA internal current source charges the capacitor connected between the Vcc pin (5) and GND pin (3) until the voltage on the Vcc pin reaches the turn-on threshold, it is then shut down. Normally, the generator is reenabled when the Vcc voltage falls below 5 V, to ensure a low power throughput during short-circuit. Otherwise, when a latched protection is tripped, the generator is re-enabled 0.5 V below the turn-on threshold, to keep the latch supplied; or, when the IC is turned off by the COMP pin (9) pulled low, the generator is active just below the UVLO threshold to allow a faster restart.

Not internally connected. Provision for clearance on the PCB to meet safety requirements.

Ground. Current return for both the signal part of the IC and the gate-drive. All of the ground connections of the bias components should be tied to a track going to this pin and kept separate from any pulsed current return.

Gate driver output. The totem pole output stage is able to drive power MOSFETs and IGBTs with a peak current capability of 800 mA source/sink.

Doc ID 13794 Rev 4

L6566A Pin settings

Table 1.

N° Pin

Pin functions (continued)

Function

5 Vcc

Supply voltage of both the signal part of the IC and the gate-driver. The internal high-voltage generator charges an electrolytic capacitor connected between this pin and GND (pin 3) as long as the voltage on the pin is below the turn-on threshold of the IC, after which it is disabled and the chip is turned on. The IC is disabled as the voltage on the pin falls below the UVLO threshold. This threshold is reduced at light load to counteract the natural reduction of the self-supply voltage. Sometimes a small bypass capacitor (0.1 µF typ.) to GND may be useful in order to get a clean bias voltage for the signal part of the IC.

6 Vcc_PFC

Supply pin output. This pin is intended for supplying the PFC controller IC in systems comprising a PFC pre-regulator or other compatible circuitry. It is internally connected to the Vcc pin (5) via a controlled switch. The switch is closed as the IC starts up and opens when the voltage at the COMP pin is lower than a threshold

(light load), whenever the IC is shut down (either latched or not) and during UVLO.

If not used, the pin is left floating.

7

8

9

CS

DIS

COMP

Input to the PWM comparator. The current flowing in the MOSFET is sensed through a resistor, the resulting voltage is applied to this pin and compared with an internal reference to determine MOSFET turn-off. The pin is equipped with 150 ns min. blanking time after the gate-drive output goes high for improved noise immunity. A second comparison level located at 1.5 V latches the device off and reduces its consumption in case of transformer saturation or secondary diode short-circuit. The information is latched until the voltage on the Vcc pin (5) goes below the UVLO threshold, and so resulting in intermittent operation. A logic circuit improves sensitivity to temporary disturbances.

IC’s latched disable input. Internally, the pin connects a comparator that, when the voltage on the pin exceeds 4.5 V, latches off the IC and brings its consumption to a lower value. The latch is cleared as the voltage on the Vcc pin (5) goes below the

UVLO threshold, but the HV generator keeps the Vcc voltage high (see pin 1 description). It is then necessary to recycle the input power to restart the IC. For a quick restart, pull pin 16 (AC_OK) below the disable threshold (see pin 16 description). Bypass the pin with a capacitor to GND (pin 3) to reduce noise pickup. Ground the pin if the function is not used.

Control input for loop regulation. The pin is driven by the phototransistor (emittergrounded) of an optocoupler to modulate its voltage by modulating the current sunk. A capacitor placed between the pin and GND (3), as close to the IC as possible to reduce noise pick-up, sets a pole in the output-to-control transfer function. The dynamic of the pin is in the 2.5 to 5 V range. A voltage below an internally defined threshold activates burst-mode operation. The voltage at the pin is bottom-clamped at about 2 V. If the clamp is externally overridden and the voltage is pulled below 1.4 V, the IC shuts down.

10 VREF

An internal generator furnishes an accurate voltage reference (5 V ± 2%) that can be used to supply few mA to an external circuit. A small film capacitor (0.1 µF typ.), connected between this pin and GND (3), is recommended to ensure the stability of the generator and to prevent noise from affecting the reference. This reference is internally monitored by a separate auxiliary reference and any failure or drift causes the IC to latch off.

Doc ID 13794 Rev 4 9/52

Pin settings L6566A

Table 1.

N° Pin

Pin functions (continued)

Function

11 ZCD

Transformer demagnetization sensing input for quasi-resonant operation and OVP input. The pin is externally connected to the transformer’s auxiliary winding through a resistor divider. A negative-going edge triggers MOSFET turn-on if QR mode is selected.

A voltage exceeding 5 V shuts the IC down and brings its consumption to a lower value (OVP). Latch-off or auto-restart mode is selectable externally. This function is strobed and digitally filtered to increase noise immunity.

12 MODE/SC

Operating mode selection. If the pin is connected to the VREF pin (7) quasi-resonant operation is selected and the oscillator (pin 13, OSC) determines the maximum allowed operating frequency.

Fixed-frequency operation is selected if the pin is not tied to VREF, in which case the oscillator determines the actual operating frequency, the maximum allowed duty cycle is set at 70% min. and the pin delivers a voltage ramp synchronized to the oscillator when the gate-drive output is high; the voltage delivered is zero while the gate-drive output is low. The pin is to be connected to pin CS (7) via a resistor for slope compensation.

13

14

15

16

OSC

SS

VFF

AC_OK

Oscillator pin. The pin is an accurate 1 V voltage source, and a resistor connected from the pin to GND (pin 3) defines a current. This current is internally used to set the oscillator frequency that defines the maximum allowed switching frequency of the L6566A, if working in QR mode, or the operating switching frequency if working in FF mode.

Soft-start current source. At startup, a capacitor Css between this pin and GND

(pin 3) is charged with an internal current generator. During the ramp, the internal reference clamp on the current sense pin (7, CS) rises linearly starting from zero to its final value, therefore causing the duty cycle to increase progressively, starting also from zero. During soft-start the adaptive UVLO function and all functions monitoring the COMP pin are disabled. The soft-start capacitor is discharged whenever the supply voltage of the IC falls below the UVLO threshold. The same capacitor is used to delay IC shutdown (latch-off or auto-restart mode selectable) after detecting an overload condition (OLP).

Line voltage feedforward input. The information on the converter’s input voltage is fed into the pin through a resistor divider and is used to change the setpoint of the pulse-by-pulse current limitation (the higher the voltage, the lower the setpoint).

The linear dynamics of the pin ranges from 0 to 3 V. A voltage higher than 3 V makes the IC stop switching. If feedforward is not desired, tie the pin to GND (pin 3) directly if a latch-mode OVP is not required (see pin 11, ZCD) or through a resistor if a latch-mode OVP is required. Bypass the pin with a capacitor to GND (pin 3) to reduce noise pick-up.

Brownout protection input. A voltage below 0.45 V shuts down (not latched) the IC, lowers its consumption, opens the Vcc_PFC pin (6), and clears the latch set by latched protection (DIS > 4.5 V, SS > 6.4 V, VFF > 6.4 V). IC operation is reenabled as the voltage exceeds 0.45 V. The comparator is provided with current hysteresis: an internal 15 µA current generator is ON as long as the voltage on the pin is below 0.45 V and is OFF if this value is exceeded. Bypass the pin with a capacitor to GND (pin 3) to reduce noise pick-up. Tie to Vcc with a 220 to 680 k

Ω resistor if the function is not used.

10/52 Doc ID 13794 Rev 4

L6566A Electrical data

Table 2.

Symbol

Absolute maximum ratings

Pin Parameter

V

HVS

I

HVS

V

CC

V

Vcc_PFC

I

Vcc_PFC

V max

V max

I

ZCD

V

MODE/SC

V

OSC

P

TOT

T

STG

T

J

1

1

5

6

6

Voltage range (referred to ground)

Startup current

IC supply voltage (Icc = 20 mA)

Voltage range

Max. source current (continuous)

7, 8, 10, 14 Analog inputs and outputs

9, 15, 16 Maximum pin voltage (Ipin ≤

11 Zero current detector max. current

12

13

Voltage range

Voltage range

Power dissipation @T

A

= 50 °C

Storage temperature

Junction operating temperature range

Table 3.

Symbol

R thJA

Thermal data

Parameter

Thermal resistance junction to ambient

Value

-0.3 to 700

Self-limited

Self-limited

-0.3 to Vcc

30

-0.3 to 7

Self-limited

±5

-0.3 to 5.3

-0.3 to 3.3

0.75

-55 to 150

-40 to 150

Unit

V

V mA

V

W

°C

°C mA

V

V

Value

120

Unit

°C/W

Doc ID 13794 Rev 4 11/52

Electrical characteristics L6566A

(T

J

= -25 to 125 °C, V

CC

= 12 V, C

GND, unless otherwise specified.)

O

= 1 nF; MODE/SC = V

REF

, R

T

= 20 k Ω from OSC to

Table 4.

Symbol

Electrical characteristics

Supply voltage

Parameter Test condition Min.

Vcc

On

Vcc

Off

I

Vcc qdis

Operating range after turn-on

Turn-on threshold

Turn-off threshold

Hys

V

Z

Hysteresis

Zener voltage

Supply current

I start-up

I q

Icc

Startup current

Quiescent current

Operating supply current

Quiescent current

V

COMP

> V

COMPL

V

COMP

= V

COMPO

(1)

(1)

V

COMP

> V

COMPL

(1)

V

COMP

= V

COMPO

V

COMP

> V

COMPL

Icc = 20 mA, IC disabled

Before turn-on, Vcc = 13 V

After turn-on, V

ZCD

= V

CS

= 1 V

MODE/SC open

IC disabled

(2)

IC latched off

23

330

10.6

8

13

9.4

7.2

High-voltage startup generator

V

HV

V

HVstart

I charge

Breakdown voltage

Start voltage

Vcc charge current

I

HV, ON

ON-state current

I

HV, OFF

OFF-state leakage current

V

CCrestart

Vcc restart voltage

I

HV

< 100 µA

I

Vcc

< 100 µA

V

HV

> V

Hvstart

, Vcc > 3 V

V

HV

> V

Hvstart

, Vcc > 3 V

V

HV

> V

Hvstart

, Vcc = 0

V

HV

= 400 V

Vcc falling

(1)

IC latched off

(1)

Disabled by

V

COMP

< V

COMPOFF

700

65

0.55

4.4

12.5

9.4

Reference voltage

V

REF

Output voltage

V

REF

Total variation

(1)

T

J

= 25 °C; I

REF

= 1 mA

I

REF

= 1 to 5 mA,

Vcc = 10.6 to 23 V

4.95

4.9

Typ.

Max.

Unit

14

10

7.6

4

25

200

2.6

4

440

80

0.85

5

13.5

10

5

100

1

1.6

0.8

40

5.6

14.5

10.6

23

23

15

10.6

8.0

27

250

2.8

4.6

2500

500

5.05

5.1

V

V

V

V

µA

V

µA mA mA

µA

V

V mA mA

V

V

V

12/52 Doc ID 13794 Rev 4

L6566A Electrical characteristics

Table 4.

Symbol

Electrical characteristics (continued)

Parameter

I

REF

Short-circuit current

Sink capability in UVLO

V

OV

Overvoltage threshold

Internal oscillator

Test condition

V

REF

= 0

Vcc = 6 V; Isink = 0.5 mA f sw

V

OSC

Oscillation frequency

Voltage reference

Operating range

T

J

= 25 °C, V

ZCD

MODE/SC = open

= 0,

Vcc=12 to 23 V, V

ZCD

= 0,

MODE/SC = open

(1)

D max

Maximum duty cycle

MODE/SC = open,

V

COMP

= 5 V

Brownout protection

Vth Threshold voltage

I

Hys

V

AC_OK_CL

Current hysteresis

Clamp level

Line voltage feedforward

Voltage falling (turn-off)

Voltage rising (turn-on)

Vcc > 5 V, V

VFF

= 0.3 V

(1)

I

AC_OK

= 100 µA

I

VFF

Input bias current

V

VFF

= 0 to 3 V, V

ZCD

< V

ZCDth

V

ZCD

> V

ZCDth

V

V

VFF

V

OFF

VFFlatch

Kc

Linear operation range

IC disable voltage

Latch-off/clamp level

Control voltage gain

(3)

Feedforward gain

(3)

K

FF

Current sense comparator

I

CS t

LEB td

(H-L)

Input bias current

Leading edge blanking

Delay to output

V

ZCD

> V

ZCDth

V

VFF

= 1 V, V

COMP

= 4 V

V

VFF

= 1 V, V

COMP

= 4 V

V

CS

= 0

V

CSx

V

CSdis

Overcurrent setpoint

Hiccup-mode OCP level

Min.

10

5.3

10

95

93

0.97

70

Typ.

0.2

5.7

100

100

1

Max.

30

0.5

300

105

107

1.03

75

0.432

0.450

0.468

0.452

0.485

0.518

12 15 18

3 3.15

3.3

-0.7

3

150

V

COMP

= V

COMPHI

, V

VFF

= 0 V 0.92

V

COMP

= V

COMPHI

, V

VFF

= 1.5 V 0.45

V

COMP

= V

COMPHI

, V

VFF

= 3.0 V

(1)

1.4

-1

0 to 3

3.15

6.4

0.4

0.04

250

1

0.5

0

1.5

-1

3.3

-1

300

100

1.08

0.55

0.1

1.6

V

V

µA

V

µA ns ns

V

%

µA mA

V

V

V

V/V

V/V

Unit mA

V

V kHz

V

V

Doc ID 13794 Rev 4 13/52

Electrical characteristics L6566A

Table 4.

Symbol

Electrical characteristics (continued)

Parameter Test condition

PWM control

V

COMPHI

V

COMPLO

V

COMPSH

I

COMP

R

COMP

Upper clamp voltage

Lower clamp voltage

Linear dynamics upper limit

Max. source current

Dynamic resistance

I

COMP

= 0

I

SOURCE

= -1 mA

(1)

V

VFF

= 0 V

V

COMP

= 3.3 V

V

COMP

= 2.6 to 4.8 V

(1)

V

COMPBM

Burst-mode threshold

(1)

MODE/SC = open

Hys

I

CLAMPL

V

COMPOFF

Burst-mode hysteresis

Lower clamp capability

Disable threshold

V

COMP

= 2 V

Voltage falling

Zero current detector/overvoltage protection

V

ZCDH

V

ZCDL

V

ZCDA

V

ZCDT

I

ZCD

I

ZCDsrc

I

ZCDsnk

T

BLANK1

V

ZCDth

T

BLANK2

Upper clamp voltage

Lower clamp voltage

Arming voltage

Triggering voltage

Internal pull-up

Source current capability

Sink current capability

Turn-on inhibit time

OVP threshold

OVP strobe delay

Latched shutdown function

I

ZCD

= 3 mA

I

ZCD

= - 3 mA

(1)

positive-going edge

(1) negative-going edge

V

COMP

< V

COMPSH

V ZCD < 2 V, V

COMP

= V

COMPHI

V

ZCD

= V

ZCDL

V

ZCD

= V

ZCDH

After gate-drive going low

After gate-drive going low

I

OTP

V

OTP

Input bias current

Disable threshold

Thermal shutdown

Vth

Hys

Shutdown threshold

Hysteresis

V

CC

_PFC function

OFF-state leakage current I leak

V

Vcc

-

V

Vcc_PFC

ON-state voltage dropout

V

DIS

= 0 to V

OTP

(1)

V

COMP

V

COMP mA

= 2.5 V, V

Vcc_PFC

= 4 V, I

VCC_PFC

= 0

= 10

Min.

4.8

320

2.52

2.7

-3.5

5.4

85

30

-130

-3

3

4.85

4.32

Typ.

Max.

Unit

5.7

2.0

5

400

25

2.65

2.85

20

1.4

5.7

-0.4

100

50

-100

2.5

5

2

4.5

180

40

0.15

5.2

480

2.78

3

-1.5

6

115

70

-1

-70

5.15

-1

4.68

1

0.3

mV mA

V mA mA

µs

V

µs

µA

V

° C

°

C

µA

V

V

V

V

µA k Ω

V

V

V mV mV

µA

14/52 Doc ID 13794 Rev 4

L6566A Electrical characteristics

Table 4.

Symbol

V

COMPO

V

COMPL

Electrical characteristics (continued)

Parameter

Level for pin 6 open and lower

UVLO off threshold (COMP voltage falling)

Test condition Min.

(1)

2.61

(1)

MODE/SC = open 3.02

(1)

2.9

Level for pin 6 closed and higher UVLO off threshold

(COMP voltage rising)

(1)

MODE/SC = open 3.41

T delay

Pin 6 change of state delay

Mode selection/slope compensation

Closed-to-open

MODE th

SC pk

SC vy

Threshold for QR operation

Ramp peak

(MODE/SC = open)

Ramp starting value

(MODE/SC = open)

Ramp voltage

(MODE/SC = open)

Source capability

(MODE/SC = open)

R

S-COMP

= 3 k

Ω

to GND, GD pin high, V

COMP

= 5 V

R

S-COMP

= 3 k Ω to GND,

GD pin high

GD pin low

V

S-COMP

= V

S-COMPpk

0.8

Soft-start

I

SS1

I

SS2

Charge current

I

SSdis

V

SSclamp

V

SSDIS

V

SSLAT

Gate driver

Discharge current

High saturation voltage

Disable level

Latch-off level

T

J

= 25 °C, V

SS

< 2 V,

V

COMP

= 4 V

T

J

= 25 °C, V

SS

> 2 V,

V

COMP

= V

COMPHi

V

SS

> 2 V

V

COMP

= 4 V

(1)

V

COMP

= V

COMPHi

V

COMP

= V

COMPHi

14

3.5

3.5

4.85

V

GDH

V

GDL

I sourcepk

I sinkpk t f t r

V

GDclamp

Output high-voltage

Output low-voltage

Output source peak current

Output sink peak current

Fall time

Rise time

Output clamp voltage

UVLO saturation

I

GDsource

= 5 mA, Vcc = 12 V

I

GDsink

= 100 mA

I

GDsource

= 5 mA; Vcc = 20 V

Vcc = 0 to V ccon , I sink

= 1 mA

9.8

-0.6

0.8

10

1.

Parameters tracking one another.

2.

See

Table 6 on page 41

and

Table 7 on page 45 .

3.

The voltage feedforward block output is given by: V cs

=

Kc

(

V

COMP

−

2 .

5

)

−

K

FF

V

VFF

3

1.7

0.3

0

20

5

5

2

5

6.4

11

0.75

40

50

11.3

0.9

Typ.

2.75

3.15

3.05

3.55

10

Max.

2.89

3.28

3.2

3.69

Unit

V

V ms

26

6.5

6.5

5.15

15

1.1

V

V

V

V mA

µA

µA

V

V

V

A ns ns

V

V

V

V

A

Doc ID 13794 Rev 4 15/52

Application information L6566A

The L6566A is a versatile peak-current-mode PWM controller specific to offline flyback converters. The device allows either fixed-frequency (FF) or quasi-resonant (QR) operation, selectable with the MODE/SC pin (12): forcing the voltage on the pin over 3 V (e.g. by tying it to the 5 V reference externally available at the VREF pin, 10) activates QR operation, otherwise the device is FF-operated.

Irrespective of the operating option selected by pin 12, the device is able to work in different modes, depending on the converter's load conditions. If QR operation is selected (see

Figure 4 ):

1.

QR mode at heavy load. Quasi-resonant operation lies in synchronizing MOSFET turnon to the transformer's demagnetization by detecting the resulting negative-going edge of the voltage across any winding of the transformer. The system then works close to the boundary between discontinuous (DCM) and continuous conduction (CCM) of the transformer. As a result, the switching frequency is different for different line/load

conditions (see the hyperbolic-like portion of the curves in Figure 4

). Minimum turn-on losses, low EMI emission, and safe behavior in short-circuit are the main benefits of this kind of operation.

2. Valley-skipping mode at medium/light load. The externally programmable oscillator of the L6566A, synchronized to MOSFET turn-on, enables the designer to define the maximum operating frequency of the converter. As the load is reduced, MOSFET turnon no longer occurs on the first valley but on the second one, the third one, and so on.

In this way the switching frequency no longer increases (piecewise linear portion in

Figure 4 ).

3. Burst-mode with no or very light load. When the load is extremely light or disconnected, the converter enters a controlled on/off operation with constant peak current.

Decreasing the load then results in frequency reduction, which can go down even to a few hundred hertz, therefore minimizing all frequency-related losses and making it easier to comply with energy saving regulations or recommendations. Having the peak current very low, no issue of audible noise arises.

Figure 4.

Multi-mode operation with QR option active f osc

Input voltage f sw

Valley-skipping mode

Burst-mode

Quasi-resonant mode

0

0 Pinmax

P in

16/52 Doc ID 13794 Rev 4

L6566A Application information

If FF operation is selected:

1.

FF mode from heavy to light load. The system operates exactly like a standard current mode, at a frequency f sw

determined by the externally programmable oscillator: both

DCM and CCM transformer operations are possible, depending on whether the power that it processes is greater or less than:

Equation 1

Pin

T

=

⎛

⎜⎜⎝

Vin

Vin +

V

R

V

R

⎞

⎟⎟⎠

2

2 f sw

Lp where Vin is the input voltage to the converter, V

R

the reflected voltage (i.e. the regulated output voltage times the primary-to-secondary turn ratio) and Lp the inductance of the primary winding. Pin

T

is the power level that marks the transition from continuous to discontinuous operation mode of the transformer.

2. Burst-mode with no or very light load. This kind of operation is activated in the same way and results in the same behavior as previously described for QR operation.

The L6566A is specifically designed for flyback converters operated from front-end power factor correction (PFC) stages in applications in compliance with EN61000-3-2 or JEITA-

MITI regulations. Pin 6 (Vcc_PFC) provides the supply voltage to the PFC control IC.

5.1 High-voltage startup generator

Figure 5 shows the internal schematic of the high-voltage startup generator (HV generator).

It is made up of a high-voltage N-channel FET, with a gate biased by a 15 M

Ω

resistor, with a temperature-compensated current generator connected to its source.

Figure 5.

High-voltage startup generator: internal schematic

1

HV

L6566A

15 M Ω

Vcc_OK

HV_EN

CONTROL

3

GND

I HV

I charge

5 Vcc

Doc ID 13794 Rev 4 17/52

Application information L6566A

With reference to the timing diagram of

Figure 6

, when power is first applied to the converter the voltage on the bulk capacitor (Vin) builds up and, at about 80 V, the HV generator is enabled to operate (HV_EN is pulled high) so that it draws about 1 mA. This current, minus the device’s consumption, charges the bypass capacitor connected from pin Vcc (5) to ground and causes its voltage to rise almost linearly.

Figure 6.

Timing diagram: normal power-up and power-down sequences

Vin

V

HVstart

Vcc

(pin 5)

Vcc

ON

Vcc

OFF

Vcc restart

Vcc_PFC

(pin 6)

GD

(pin 4)

HV_EN

Vcc_OK

I charge

0.85 mA

Power-on light load

heavy load

Normal operation regulation is lost here t

Power-off t t t t t

As the Vcc voltage reaches the startup threshold (14 V typ.) the low-voltage chip starts operating and the HV generator is cut off by the Vcc_OK signal asserted high. The device is powered by the energy stored in the Vcc capacitor until the self-supply circuit (typically an auxiliary winding of the transformer and a steering diode) develops a voltage high enough to sustain the operation. The residual consumption of this circuit is just the one on the 15 M Ω resistor ( ≈ 10 mW at 400 Vdc), typically 50-70 times lower, under the same conditions, as compared to a standard startup circuit made with external dropping resistors.

At converter power-down the system loses regulation as soon as the input voltage is so low that either peak current or maximum duty cycle limitation is tripped. Vcc then drops and stops IC activity as it falls below the UVLO threshold (10 V typ.). The Vcc_OK signal is deasserted as the Vcc voltage goes below a threshold Vcc restart

located at about 5 V. The HV generator can now restart. However, if Vin < Vin start

, as illustrated in

Figure 6 , HV_EN is de-

asserted too and the HV generator is disabled. This prevents converter restart attempts and ensures monotonic output voltage decay at power-down in systems where brownout

protection (see Section 5.12

) is not used.

The low restart threshold Vcc restart

ensures that, during short-circuits, the restart attempts of

the device have a very low repetition rate, as shown in the timing diagram of Figure 7 on page 19 , and that the converter works safely with extremely low power throughput.

18/52 Doc ID 13794 Rev 4

L6566A Application information

Figure 7.

Timing diagram showing short-circuit behavior (SS pin clamped at 5 V)

Short circuit occurs here Vcc

(pin 5)

Vcc ON

Vcc

OFF

Vcc restart

GD

(pin 4)

Vcc_OK

I charge

0.85 mA

T rep

< 0.03T

rep t t t t

Figure 8.

Zero current detection block, triggering block, oscillator block and related logic

L6566A

COMP

9

VFF

15 line

FFWD

R

Z1

R

Z2

ZCD 11

PWM

5.7V

BLANKING

TIME blanking

START

7 CS

-

100 mV

50 mV

+

Strobe

+

-

5V

MONO

STABLE

S/H

TURN-ON

LOGIC

Reset

4:1

Counter

OSCILLATOR

FAULT

R

S

Q

DRIVER

13

OSC

R T

4 GD

+Vin

Rs

Q

Doc ID 13794 Rev 4 19/52

Application information L6566A

5.2 Zero current detection and triggering block; oscillator block

The zero current detection (ZCD) and triggering blocks switch on the external MOSFET if a negative-going edge falling below 50 mV is applied to the input (pin 11, ZCD). To do so the triggering block must be previously armed by a positive-going edge exceeding 100 mV.

This feature is typically used to detect transformer demagnetization for QR operation, where the signal for the ZCD input is obtained from the transformer’s auxiliary winding used also to supply the L6566A. The triggering block is blanked for T

BLANK

= 2.5 µs after MOSFET turnoff to prevent any negative-going edge that follows leakage inductance demagnetization from triggering the ZCD circuit erroneously.

The voltage at the pin is both top and bottom limited by a double clamp, as illustrated in the

internal diagram of the ZCD block of Figure 8

. The upper clamp is typically located at 5.7 V, while the lower clamp is located at -0.4 V. The interface between the pin and the auxiliary

winding is a resistor divider. Its resistance ratio is properly chosen (see Section 5.11

) and

the individual resistance values (R

Z1

, R

Z2

) are such that the current sourced and sunk by the pin be within the rated capability of the internal clamps ( ± 3 mA).

At converter power-up, when no signal is coming from the ZCD pin, the oscillator starts up the system. The oscillator is programmed externally by means of a resistor (R

T

) connected from pin OSC (13) to ground. With good approximation the oscillation frequency f osc

is:

Equation 2 f osc

≈

2 ⋅ 10

3

R

T

(with f osc

in kHz and R

T

in kW). As the device is turned on, the oscillator starts immediately; at the end of the first oscillator cycle, the voltage on the ZCD pin being zero, the MOSFET is turned on, therefore starting the first switching cycle right at the beginning of the second oscillator cycle. At any switching cycle, the MOSFET is turned off as the voltage on the current sense pin (CS, 7) hits an internal reference set by the line feedforward block, and the transformer starts demagnetization. If this completes (so a negative-going edge appears on the ZCD pin) after a time exceeding one oscillation period T osc

=1/f osc

from the previous turnon, the MOSFET is turned on again - with some delay to ensure minimum voltage at turn-on

– and the oscillator ramp is reset. If, instead, the negative-going edge appears before T osc has elapsed, it is ignored and only the first negative-going edge after T osc

turns on the

MOSFET and synchronizes the oscillator. In this way one or more drain ringing cycles are

skipped (“valley-skipping mode”, Figure 9

) and the switching frequency is prevented from exceeding f osc

.

Figure 9.

Drain ringing cycle skipping as the load is gradually reduced

V

DS

V

DS

V

DS

T

ON

T

FW

T osc

T

V

P in

= P in'

(limit condition)

20/52 t

T osc

P in

= P in''

< P in'

Doc ID 13794 Rev 4 t

T osc

P in

= P in'''

< P in'' t

L6566A

Note:

Application information

When the system operates in valley skipping-mode, uneven switching cycles may be observed under some line/load conditions, due to the fact that the OFF-time of the MOSFET is allowed to change with discrete steps of one ringing cycle, while the OFF-time needed for cycle-by-cycle energy balance may fall in between. Therefore one or more longer switching cycles is compensated by one or more shorter cycles, and vice versa. However, this mechanism is absolutely normal and there is no appreciable effect on the performance of the converter or on its output voltage.

If the MOSFET is enabled to turn on but the amplitude of the signal on the ZCD pin is smaller than the arming threshold for some reason (e.g. a heavy damping of drain oscillations, like in some single-stage PFC topologies, or when a turn-off snubber is used),

MOSFET turn-on cannot be triggered. This case is identical to what happens at startup: at the end of the next oscillator cycle the MOSFET is turned on, and a new switching cycle takes place after skipping no more than one oscillator cycle.

The operation described so far does not consider the blanking time T

BLANK

after MOSFET turn-off, and actually T

BLANK

does not come into play as long as the following condition is met:

Equation 3 where D is the MOSFET duty cycle. If this condition is not met, nothing changes substantially: the time during which MOSFET turn-on is inhibited is extended beyond T osc

by a fraction of T

BLANK

. As a consequence, the maximum switching frequency is a little lower than the programmed value f osc

and valley-skipping mode may take place slightly earlier than expected. However this is quite unusual: setting f osc

= 150 kHz, the phenomenon can be observed at duty cycles higher than 60%. See

Section 5.11

for further implications of

T

BLANK

.

If the voltage on the COMP pin (9) saturates high, which reveals an open control loop, an internal pull-up keeps the ZCD pin close to 2 V during MOSFET OFF-time to prevent noise from false triggering the detection block. When this pull-up is active, the ZCD pin may not be able to go below the triggering threshold, which would stop the converter. To allow autorestart operation, while ensuring minimum operating frequency in these conditions, the oscillator frequency that retriggers MOSFET turn-on is that of the external oscillator divided by 128. Additionally, to prevent malfunction at converter startup, the pull-up is disabled during the initial soft-start (see

Section 5.10

). However, to ensure a correct startup, at the

end of the soft-start phase, the output voltage of the converter must meet the condition:

Equation 4

D

≤

1

−

T

BLANK

T osc

Vout >

Ns

Naux

R

Z 1

I

ZCD where Ns is the turn number of the secondary winding, Naux the turn number of the auxiliary winding, and I

ZCD

the maximum pull-up current (130 μ A).

Doc ID 13794 Rev 4 21/52

Application information L6566A

The operation described so far under different operating conditions for the converter is

illustrated in the timing diagrams of Figure 10

.

If the FF option is selected, the operation is exactly equal to that of a standard current-mode

PWM controller. It works at a frequency fsw = fosc; both DCM and CCM transformer operations are possible, depending on the operating conditions (input voltage and output load) and on the design of the power stage. The MOSFET is turned on at the beginning of each oscillator cycle and is turned off as the voltage on the current sense pin reaches an internal reference set by the line feedforward block. The maximum duty cycle is limited at

70% minimum. The signal on the ZCD pin in this case is used only for detecting feedback loop failures (see

Section 5.11

).

Figure 10.

Operation of ZCD, triggering and oscillator blocks (QR option active)

ZCD

(pin 11)

100 mV

50 mV

Oscillator ramp

ZCD

(pin 11)

100 mV

50 mV

Oscillator ramp

ZCD

(pin 11)

100 mV

50 mV

Oscillator ramp

ZCD blanking time

ZCD blanking time

ZCD blanking time

Arm/Trigger armed trigger

ON-enable

PWM latch

Set

PWM latch

Reset

GD

(pin 4)

Arm/Trigger

ON-enable

PWM latch

Set

PWM latch

Reset

GD

(pin 4)

Arm/Trigger

ON-enable

PWM latch

Set

PWM latch

Reset

GD

(pin 4) b) light load c) start-up a) full load

22/52 Doc ID 13794 Rev 4

L6566A

5.3

Note:

Application information

Burst-mode operation at no load or very light load

When the voltage at the COMP pin (9) falls 20 mV below a threshold fixed internally at a value, V

COMPBM

, depending on the selected operating mode, the L6566A is disabled with the MOSFET kept in OFF-state and its consumption reduced at a lower value to minimize

Vcc capacitor discharge.

The control voltage now increases as a result of the feedback reaction to the energy delivery stop (the output voltage is slowly decaying), the threshold is exceeded and the device restarts switching again. In this way the converter works in burst-mode with a nearly constant peak current defined by the internal disable level. A load decreases and then causes a frequency reduction, which can go down even to a few hundred hertz, therefore minimizing all frequency-related losses and making it easier to comply with energy saving

regulations. This kind of operation, shown in the timing diagrams of Figure 11

along with the others previously described, is noise-free since the peak current is low.

If it is necessary to decrease the intervention threshold of the burst-mode operation, this can be done by adding a small DC offset on the current sense pin as shown in

Figure 12 .

The offset reduces the available dynamics of the current signal; thereby, the value of the sense resistor must be determined taking this offset into account.

Figure 11.

Load-dependent operating modes: timing diagrams

COMP

(pin 9)

20 mV hyster.

V

COMPBM f osc f sw t

MODE/SC=Open

MODE/SC=VREF t

GD

(pin 4)

MODE/SC=Open

MODE/SC=VREF

FF Mode

QR Mode

Burst-mode

Burst-mode

Valley-skipping Mode

FF Mode

QR Mode t

Doc ID 13794 Rev 4 23/52

Application information

Figure 12.

Addition of an offset to the current sense lowers the burst-mode operation threshold

Vcs o = Vref

R

R + Rc

Vref

10

4

L6566A Rc

R

3

7

Rs

L6566A

A major problem when optimizing a converter for minimum no-load consumption is that the voltage generated by the auxiliary winding under these conditions falls considerably as compared even to few mA load. This very often causes the supply voltage Vcc of the control

IC to drop and go below the UVLO threshold so that the operation becomes intermittent, which is undesired. Furthermore, this must be traded off against the need of generating a voltage not exceeding the maximum allowed by the control IC at full load.

To help the designer overcome this problem, the device, besides reducing its own consumption during burst-mode operation, also features a proprietary adaptive UVLO function. It consists of shifting the UVLO threshold downwards at light load, namely when the voltage at the COMP pin falls below a threshold V

COMPO

internally fixed (see

Section 5.8

), so as to have more headroom. To prevent any malfunction during transients

from minimum to maximum load, the normal (higher) UVLO threshold is re-established when the voltage at the COMP pin exceeds V

COMPL

(see

Section 5.8

) and Vcc has

exceeded the normal UVLO threshold (see Figure 13 ). The normal UVLO threshold ensures

that at full load the MOSFET is driven with a proper gate-to-source voltage.

Figure 13.

Adaptive UVLO block

Vcc_PFC

6

Vcc_PFC logic

-

+

COMP

9

-

+

R

S Q

V

COMPL

V

COMPO

Vcc

OFF1

Vcc

5

SW

Vcc

OFF2

(*)

-

+

UVLO

L6566A

VCOMP

(pin 9)

V C OMPL

V C OMPO

Vcc

(pin 5)

Vcc OFF1

Vcc

OFF2

Q t t t

Vcc_PFC

(pin 6)

Tdelay

(*) Vcc

OFF2

< Vcc

OFF1 is selected when Q is high t

24/52 Doc ID 13794 Rev 4

L6566A Application information

The device is specific to secondary feedback. Typically, there is a TL431 on the secondary side and an optocoupler that transfers output voltage information to the PWM control on the primary side, crossing the isolation barrier. The PWM control input (pin 9, COMP) is driven directly by the phototransistor’s collector (the emitter is grounded to GND) to modulate the duty cycle (

Figure 14 , left-hand side circuit).

In applications where a tight output regulation is not required, it is possible to use a primarysensing feedback technique. In this approach the voltage generated by the self-supply

winding is sensed and regulated. This solution, shown in Figure 14

, right-hand side circuit, is cheaper because no optocoupler or secondary reference is needed, but output voltage regulation, especially as a result of load changes, is quite poor. Ideally, the voltage generated by the self-supply winding and the output voltage should be related by the

Naux/Ns turn ratio only. In fact, numerous non-idealities, mainly transformer parasitics, cause the actual ratio to deviate from the ideal one. Line regulation is quite good, in the range of ± 2%, whereas load regulation is about ± 5% and output voltage tolerance is in the range of ±10%.

The dynamic of the pin is in the 2.5 to 5 V range. The voltage at the pin is clamped downwards at about 2 V. If the clamp is externally overridden and the voltage on the pin is pulled below 1.4 V, the L6566A shuts down. This condition is latched as long as the device is supplied. While the device is disabled, however, no energy is coming from the self-supply circuit, therefore the voltage on the Vcc capacitor decays and crosses the UVLO threshold after some time, which clears the latch and lets the HV generator restart. This function is intended for an externally controlled burst-mode operation at light load with a reduced output voltage, a technique typically used in multi-output SMPS, such as those for CRT TVs

or monitors (see the timing diagram Figure 15 ).

Figure 14.

Possible feedback configurations that can be used with the L6566A

Vout

5 Vcc

L6566A

9

COMP

L6566A

9

COMP

Cs

N aux

TL431

Secondary feedback Primary feedback

Doc ID 13794 Rev 4 25/52

Application information L6566A

Figure 15.

Externally controlled burst-mode operation by driving the COMP pin: timing diagram

Vcc

(pin 5)

Vcc

ON

Vcc

OFF

Vcc restart

Standby is commanded here

COMP

(pin 9) t t

GD

(pin 4)

Vcc_OK

I charge

0.85 mA

Vcc_PFC

(pin 6)

Vout t t t t t

5.6 PWM comparator, PWM latch and voltage feedforward blocks

The PWM comparator senses the voltage across the current sense resistor Rs and, by comparing it to the programming signal delivered by the feedforward block, determines the exact instant when the external MOSFET must be switched off. Its output resets the PWM latch, previously set by the oscillator or the ZCD triggering block, which asserts the gatedriver output low. The use of PWM latch avoids spurious switching of the MOSFET that may result from the noise generated (“double-pulse suppression”).

Cycle-by-cycle current limitation is realized with a second comparator (OCP comparator) that also senses the voltage across the current sense resistor Rs and compares this voltage to a reference value V

CSX

. Its output is OR-ed with that of the PWM comparator (see the circuit schematic in

Figure 17 ). In this way, if the programming signal delivered by the

feedforward block and sent to the PWM comparator exceeds V

CSX

, it is the OCP comparator that first resets the PWM latch instead of the PWM comparator. The value of Vcsx, thereby, determines the overcurrent setpoint along with the sense resistor Rs.

The power that QR flyback converters with a fixed overcurrent setpoint (like fixed-frequency systems) are able to deliver changes considerably with the input voltage. Obviously, this is not a problem if the flyback converter runs off a fixed voltage bus generated by the PFC preregulator; however, with a tracking boost PFC (a “boost follower” PFC), the regulated output voltage at maximum mains voltage can be even twice the value at minimum mains voltage.

In this case the issue remains, although it is not as great as without PFC and wide-range mains. With a 1: 2 voltage change, the maximum transferable power at maximum line can

26/52 Doc ID 13794 Rev 4

L6566A Application information be 50% higher than at minimum line, as shown by the upper curve in the diagram of

Figure 16

. The L6566A has the line feedforward function available to solve this issue.

Figure 16.

Typical power capability change vs. input voltage in QR flyback converters

2.5

k = 0

2 system not

compensated k

1.5

Note:

1

system optimally compensated k = k opt

0.5

1 1.5

2 2.5

V in

V inmin

3 3.5

4

It acts on the overcurrent setpoint V csx , so that it is a function of the converter’s input voltage

Vin (output of the PFC pre-regulator) sensed through a dedicated pin (15, VFF): the higher the input voltage, the lower the setpoint. This is illustrated in the diagram on the left-hand

side of Figure 17

: it shows the relationship between the voltage on the VFF and V csx pin

(with the error amplifier saturated high in an attempt to maintain the output voltage regulation):

Equation 5

V csx

=

1

−

V

VFF

3

=

1

− k

3

Vin

If the voltage on the pin exceeds 3 V, switching ceases but the soft-start capacitor is not

discharged. The schematic in Figure 17

also shows how the function is included in the control loop.

With a proper selection of the external divider R1-R2, i.e. of the ratio k = R2 / (R1+R2), it is possible to achieve the optimum compensation described by the lower curve in the diagram of

Figure 16 .

The optimum value of k, k opt

, which minimizes the power capability variation over the input voltage range, is the one that provides equal power capability at the extremes of the range.

The exact calculation is complex, and non-idealities shift the real-world optimum value from the theoretical one. It is therefore more practical to provide a first cut value, easily calculated, and then to fine-tune experimentally.

Assuming that the system operates exactly at the boundary between DCM and CCM, and neglecting propagation delays, the following expression for k opt

can be found:

Doc ID 13794 Rev 4 27/52

Application information L6566A

Equation 6 k opt

= 3 ⋅

V in min

⋅ V in max

+

V

R

(

V in min

+ V in max

)

⋅ V

R

Experience shows that this value is typically lower than the real one. Once the maximum peak primary current, I

PKpmax

, occurring at minimum input voltage Vinmin has been found, the value of Rs can be determined from (2):

Equation 7

Rs

=

1 − k opt

V in min

3

I

PKp max

The converter is then bench tested to find the output power level Pout lim

where regulation is lost (because overcurrent is being tripped) both at Vin = Vin min

and Vin = Vin max

.

Figure 17.

Left: overcurrent setpoint vs. VFF voltage; right: line feedforward function block

V csx

[V]

1.2

1

V

COMP

= Upper clamp

PFC Output Bus

To PFC's OV sensing

R1A

R1B

Optional for

OVP settings

0.8

0.6

0.4

0.2

0

0 0.5

1 1.5

V

VFF

[V]

2 2.5

3 3.5

R2

COMP

9

15

VFF

VOLTAGE

FEED

FORWARD

CS

7

Vcsx

L6566A 1.5 V

+

-

PWM

+

-

OCP

+

-

Hiccup

Rs

Clock/ZCD

R

S

Q DRIVER

DISABLE

4

GD

If Pout lim

@ Vin max

> Pout lim

@ Vin min

the system is still undercompensated and k needs to increase; if Pout lim

@ Vin max

< Pout lim

@ Vin min

the system is overcompensated and k needs to decrease. This continues until the difference between the two values is acceptably low. Once the true k opt

is found in this way, it is possible that Pout lim turns out slightly different from the target; to correct this, the sense resistor Rs needs adjusting and the above tuning process is repeated with the new Rs value. Typically, a satisfactory setting is achieved in no more than a couple of iterations.

In applications where this function is not wanted, e.g. because the PFC stage regulates at a fixed voltage, the VFF pin can be simply grounded, directly or through a resistor, depending on whether one wants the OVP function to be auto-restart or latched mode (see

Section 5.11

). The overcurrent setpoint is then fixed at the maximum value of 1 V. If a lower setpoint is desired to reduce the power dissipation on Rs, the pin can be also biased at a fixed voltage using a divider from VREF (pin 10).

28/52 Doc ID 13794 Rev 4

L6566A Application information

If the FF option is selected, the line feedforward function can be still used to compensate for the total propagation delay Td of the current sense chain (internal propagation delay td

(H-L) plus the turn-off delay of the external MOSFET), which in standard current mode PWM controllers is done by adding an offset on the current sense pin proportional to the input voltage. In that case, the divider ratio k, which is much smaller when compared to that used with the QR option selected, can be calculated with the following equation:

Equation 8 k opt

= 3

Td

Rs Lp where Lp is the inductance of the primary winding. In case a constant maximum power capability vs. the input voltage is not required, the VFF pin can be grounded, directly or through a resistor (see

Section 5.11

), therefore fixing the overcurrent setpoint at 1 V, or biased at a fixed voltage through a divider from VREF to get a lower setpoint.

It is possible to bypass the pin to ground with a small film capacitor (e.g. 1-10 nF) to ensure a clean operation of the IC even in a noisy environment.

The pin is internally forced to ground during UVLO, after activating any latched protection and when the COMP pin is pulled below its low clamp voltage (see

Section 5.5

).

A third comparator senses the voltage on the current sense input and shuts down the device if the voltage on the pin exceeds 1.5 V, a level well above that of the maximum overcurrent setpoint (1 V). Such an anomalous condition is typically generated by either a short-circuit of the secondary rectifier or a shorted secondary winding, or a hard-saturated flyback transformer.

To distinguish an actual malfunction from a disturbance (e.g. induced during ESD tests), the first time the comparator is tripped, the protection circuit enters a “warning state”. If, in the next switching cycle, the comparator is not tripped, a temporary disturbance is assumed and the protection logic is reset in its idle state; if the comparator is tripped again a real malfunction is assumed and the L6566A is stopped. Depending on the time relationship between the detected event and the oscillator, occasionally the device may stop after the third detection.

This condition is latched as long as the device is supplied. While it is disabled, however, no energy is coming from the self-supply circuit; so the voltage on the Vcc capacitor decays and crosses the UVLO threshold after some time, which clears the latch. If the internal startup generator is still off, then the Vcc voltage still needs to go below its restart voltage before the Vcc capacitor is charged again and the device restarted. Ultimately, this results in a low-frequency intermittent operation (hiccup-mode operation), with very low stress on the

power circuit. This special condition is illustrated in the timing diagram of Figure 18 .

Doc ID 13794 Rev 4 29/52

Application information

Figure 18.

Hiccup-mode OCP: timing diagram

Vcc

(pin 5)

Vcc

ON

Secondary diode is shorted here

Vcc

OFF

Vcc restart

V CS

(pin 7)

1.5 V

GD

(pin 4)

OCP latch

Vcc_OK

Vcc_PFC

(pin 6)

L6566A

The device is specifically designed to minimize converter losses under light or no-load conditions, and a special function has been provided to help the designer meet energy saving requirements even in power-factor-corrected systems where a PFC pre-regulator precedes the isolated DC-DC converter.

In fact, EMC regulations require compliance with low-frequency harmonic emission limits at nominal load; no limit is envisaged when the converter operates with a light load. Then the

PFC pre-regulator can be turned off, therefore saving the no-load consumption of this stage

(0.5

÷

1 W).

To do so, the L6566A provides the Vcc_PFC pin (6): this pin is internally connected to the

Vcc pin (5) via a PNP transistor, normally closed, that opens when the voltage V

COMP

falls below V

COMPO

, a threshold internally set at a value depending on whether QR operation or

FF operation is selected. This pin is intended for supplying the PFC controller of the preregulator as shown in

Figure 16

. The switch is thermally protected, so that the IC stops if an external failure causes the pin to be overloaded for too long a time or shorted to ground.

t t t t t t

30/52 Doc ID 13794 Rev 4

L6566A Application information

Figure 19.

Possible interfaces between the L6566A and a PFC controller

Vcc

5

L6566A

6 Vcc_PFC

Vcc

L6561

L6562

L6563

5.9

Vcc

5

L6566A

22 k

Ω

6 Vcc_PFC

4.7k

Ω

RUN

10

L6563

To prevent intermittent operation of the PFC stage, some hysteresis is provided: if the internal switch is open, it is closed (which re-enables the PFC pre-regulator) when V

COMP exceeds V

COMPL

> V

COMPO

. Additionally, to reject V

COMP

undershoots during transients,

V

COMP

must stay below V

COMPO

for more than 1024 oscillator cycles in order for the

Vcc_PFC pin to open. Entering burst-mode (V

COMP

< V

COMPBM

) opens Vcc_PFC immediately.

Besides pin 6 going open, when V

COMP

falls below V

COMPO

the UVLO threshold is set 2.4 V below to compensate for the drop of the voltage delivered by the self-supply circuit that

occurs at light load (see Section 5.4

).

Latched disable function

The device is equipped with a comparator having the non-inverting input externally available at the DIS pin (8) and with the inverting input internally referenced to 4.5 V. As the voltage on the pin exceeds the internal threshold, the device is immediately shut down and its consumption reduced to a low value.

The information is latched and it is necessary to let the voltage on the Vcc pin go below the

UVLO threshold to reset the latch and restart the device. To keep the latch supplied as long as the converter is connected to the input source, the HV generator is activated periodically so that Vcc oscillates between the startup threshold V ccON

and V ccON

- 0.5 V. Activating the

HV generator in this way cuts its power dissipation approximately by three (as compared to the case of continuous conduction) and keeps peak silicon temperature close to the average value.

To let the L6566A restart it is then necessary to disconnect the converter from the input

source. Pulling pin 16 (AC_OK) below the disable threshold (see Section 5.12

) stops the HV

generator until Vcc falls below Vcc restart

, so that the latch can be cleared and a quicker restart is allowed as the input source is removed. This operation is shown in the timing

diagram of Figure 20 .

This function is useful to easily implement a latched overtemperature protection by biasing the pin with a divider from VREF, where the upper resistor is an NTC physically located close to a heating element like the MOSFET, or the transformer. The DIS pin is a highimpedance input, it is therefore prone to pick-up noise, which might give origin to undesired latch-off of the device. It is possible to bypass the pin to ground with a small film capacitor

(e.g. 1-10 nF) to prevent any malfunctioning of this kind.

Doc ID 13794 Rev 4 31/52

Application information

Figure 20.

Operation after latched disable activation: timing diagram

DIS

(pin 8)

4.5V

Vcc

(pin 5)

Vcc

ON

Vcc

ON

-0.5

Vcc

OFF

HV generator is turned on

Vcc restart

GD

(pin 4)

Restart is quicker

Disable latch is reset here

HV generator turn-on is disabled here t t t

Vcc_PFC

(pin 6) t

Vin

V

HVstart

AC_OK

(pin 16)

Vth

Input source is removed here t t

L6566A

5.10 Soft-start and delayed latched shutdown upon overcurrent

At device startup, a capacitor (Css) connected between the SS pin (14) and ground is charged by an internal current generator, I

SS1

, from zero up to about 2 V where it is clamped. During this ramp, the overcurrent setpoint progressively rises from zero to the

value imposed by the voltage on the VFF pin 15, (see Section 5.6

); MOSFET conduction

time increases gradually, therefore controlling the startup inrush current. The time needed for the overcurrent setpoint to reach its steady-state value, referred to as soft-start time, is approximately:

Equation 9

T

SS

=

Css

V csx

( V

VFF

)

=

I

SS 1

I

Css

SS 1

⎜⎜⎝ 1

V

VFF

3

⎞

⎟⎟⎠

During the ramp (i.e. until V

SS

= 2 V) all the functions that monitor the voltage on the COMP pin are disabled.

The soft-start pin is also invoked whenever the control voltage (COMP) saturates high, which reveals an open-loop condition for the feedback system. This condition very often occurs at startup, but may be also caused by either a control loop failure or a converter overload/short-circuit. A control loop failure results in an output overvoltage that is handled by the OVP function of the L6566A (see

Section 5.11

). In the case of QR operation, a short-

circuit causes the converter to run at a very low frequency, then with very low power capability. This causes the self-supply system that powers the device to switch off, so that

32/52 Doc ID 13794 Rev 4

L6566A Application information the converter works intermittently, which is very safe. In case of overload the system has a power capability lower than that at nominal load but the output current may be quite high and overstressing the output rectifier. In the case of FF operation the capability is almost unchanged and both short-circuit and overload conditions are more critical to handle.

The L6566A, regardless of the operating option selected, makes it easier to handle such conditions: the 2 V clamp on the SS pin is removed and a second internal current generator

I

SS2

= I

SS1

/4 keeps on charging Css. As the voltage reaches 5 V, the device is disabled, if it is allowed to reach 2 V

BE

over 5 V, the device is latched off. In the former case the resulting

behavior is identical to that under short-circuit illustrated in Figure 6 ; in the latter case the

result is identical to that of Figure 20 . See

Section 5.9

for additional details.

A diode, with the anode to the SS pin and the cathode connected to the VREF pin (10) is the simplest way to select either auto-restart mode or latch-mode behavior upon overcurrent. If the overload disappears before the Css voltage reaches 5 V, the I

SS2

generator is turned off

and the voltage gradually brought back down to 2 V. Refer to Section 6

(

Figure 7

) for additional hints.

If latch-mode behavior is desired also for converter short-circuit, make sure that the supply voltage of the device does not fall below the UVLO threshold before activating the latch.

Figure 21

shows soft-start pin behavior under different operating conditions and with different settings (latch-mode or auto-restart).

Figure 21.

Soft-start pin operation under different operating conditions and settings

Vcc

(pin 5)

Vcc falls below UVLO before latching off

SS

(pin 14)

2V

COMP

(pin 9)

5V+2Vbe

5V here the IC shuts down here the IC latches off

UVLO t t

GD

(pin 4)

Vcc_PFC

(pin 6) t t

START-UP NORMAL

OPERATION

TEMPORARY

OVERLOAD

NORMAL

OPERATION

OVERLOAD SHUTDOWN

LATCHED

AUTORESTART

RESTART t

Note: Unlike other PWM controllers provided with a soft-start pin, in the L6566A, grounding the SS pin does not guarantee that the gate-driver is disabled.

Doc ID 13794 Rev 4 33/52

Application information L6566A

The OVP function of the L6566A monitors the voltage on the ZCD pin (11) in the MOSFET

OFF-time, during which the voltage generated by the auxiliary winding tracks the converter output voltage. If the voltage on the pin exceeds an internal 5 V reference, a comparator is triggered, an overvoltage condition is assumed and the device is shut down. An internal current generator is activated that sources 1 mA out of the VFF pin (15). If the VFF voltage

is allowed to reach 2 Vbe over 5 V, the L6566A is latched off. See Section 5.9

for more

details on the IC’s behavior under these conditions. If the impedance externally connected to pin 15 is so low that the 5+2 V

BE

threshold cannot be reached or if some means is provided to prevent that, the device is able to restart after the Vcc has dropped below 5 V.

Refer to Section 6

( Table 7

) for additional hints.

Figure 22.

OVP function: internal block diagram

PWM latch

R Q

S Q to triggering block

Monostable

M1 2 µs

ZCD

11

40k Ω

5 V

-

+

5pF

COUT

Monostable

M2

STROBE

0.5 µs

OVP

FF

R Q1

S

L6566A

2-bit counter

Fault

Counter reset

34/52

Figure 23.

OVP function: timing diagram

GD

(pin 4)

Vaux

0

ZCD

(pin 11)

5V

COUT

STROBE

2 µs 0.5 µs

OVP

COUNTER

RESET

COUNTER

STATUS

FAULT

0

Vcc_PFC

(pin 6)

0

NORMAL OPERATION

0 0 → 1 1 → 2 2 → 0

TEMPORARY DISTURBANCE

0 0 → 1 1 → 2 2 → 3 3 → 4

FEEDBACK LOOP FAILURE t t t t t t t t t t

Doc ID 13794 Rev 4

L6566A

Note:

Application information

The ZCD pin is connected to the auxiliary winding through a resistor divider R

Z1

, R

Z2

(see

Figure 8 ). The divider ratio k

OVP

= R

Z2

/ (R

Z1

+ R

Z2

) is chosen equal to:

Equation 10 k

OVP

=

5

Vout

OVP

Ns

Naux where Vout

OVP

is the output voltage value that is to activate the protection, Ns is the turn number of the secondary winding and Naux is the turn number of the auxiliary winding. The value of R

Z1

is such that the current sourced by the ZCD pin be within the rated capability of the internal clamp:

Equation 11

R

Z 1

≥

3

1

⋅ 10

−

3

Naux

Np

Vin max where Vin max

is the maximum DC input voltage and Ns the turn number of the primary winding. See

Section 5.2

for additional details.

To reduce sensitivity to noise and prevent the latch from being erroneously activated, first the OVP comparator is active only for a small time window (typically, 0.5 µs), starting 2 µs after MOSFET turn-off, to reject the voltage spike associated to the positive-going edges of the voltage across the auxiliary winding Vaux; secondly, to stop the L6566A, the OVP comparator must be triggered for four consecutive switching cycles. A counter, which is reset every time the OVP comparator is not triggered in one switching cycle, is provided for this purpose.

Figure 22 shows the internal block diagram, while the timing diagrams in Figure 23

illustrate the operation.

To use the OVP function effectively, i.e. to ensure that the OVP comparator is always interrogated during MOSFET OFF-time, the duty cycle D under open-loop conditions must fulfill the following inequality:

Equation 12

D

+

T

BLANK 2 f sw

≤

1 where T

BLANK2

= 2 µs; this is also illustrated in the diagram of

Figure 24 .

Doc ID 13794 Rev 4 35/52

Application information L6566A

Figure 24.

Maximum allowed duty cycle vs. switching frequency for correct OVP detection

0.8

0.7

0.6

Dmax 0.5

0.4

0.3

0.725

0.2

5

.

10

4

1

.

10

5

1.5

.

10

5

2

.

10

5

2.5

.

10

5 fsw [Hz]

3

.

10

5

3.5

.

10

5

4

.

10

5

36/52 Doc ID 13794 Rev 4

L6566A Application information

Brownout protection is basically a not-latched device shutdown function activated when a condition of mains undervoltage is detected. There are several reasons why it may be desirable to shut down a converter during a brownout condition, which occurs when the mains voltage falls below the minimum specification of normal operation.

Firstly, a brownout condition may cause overheating of the PFC front-end due to an excess of RMS current. Secondly, brownout can also cause the PFC pre-regulator to work open loop. This could be dangerous to the PFC itself and the downstream converter, should the input voltage return abruptly to its rated value, given the slow response of PFC to transient events. Finally, spurious restarts may occur during converter power-down, therefore causing the output voltage not to decay to zero monotonically.

The L6566A shutdown upon brownout is accomplished by means of an internal comparator,

as shown in the block diagram of Figure 25 , which shows the basic circuit usage. The

inverting input of the comparator, available on the AC_OK pin (16), is supposed to sense a voltage proportional to either the RMS or the peak mains voltage; the non-inverting input is internally referenced to 0.485 V with 35 mV hysteresis. If the voltage applied on the AC_OK pin before the device starts operating does not exceed 0.485 V or if it falls below 0.45 V while the device is running, The AC_OK signal goes high, the Vcc_PFC pin is open and the device shuts down, with the soft-start capacitor discharged and the gate-drive output low.

Additionally, in case the device has been latched off by some protection function (in which case Vcc is oscillating between V ccON

and V ccON

- 0.5 V), the AC_OK voltage falling below

0.45 V clears the latch. This feature can be used to allow a quicker restart as the input source is removed.

Figure 25.

Brownout protection: internal block diagram and timing diagram

Sensed voltage

Vcc

L6566A

R

H

AC_OK

16

15 µA

0.485V

0.45V

-

+

R L

5

AC_FAIL

Sensed voltage

Vsen ON

Vsen OFF

VAC_OK

(pin 16)

0.485V

AC_FAIL

I

HYS

15 µA

Vcc

(pin 5)

GD

(pin 4)

Vout

Vcc_PFC

(pin 6)

0.45V

t t t t t t t t

Doc ID 13794 Rev 4 37/52

Application information L6566A

While the brownout protection is active the startup generator keeps on working but, there being no PWM activity, the Vcc voltage continuously oscillates between the startup and the

HV generator restart thresholds, as shown in the timing diagram of Figure 25 .

The brownout comparator is provided with current hysteresis in addition to voltage hysteresis: an internal 15 µA current sink is ON as long as the voltage applied on the

AC_OK pin is such that the AC_FAIL signal is high. This approach provides an additional degree of freedom: it is possible to set the ON threshold and the OFF threshold separately by properly choosing the resistors of the external divider (see Equation 13 and 14 below).

With just voltage hysteresis, instead, fixing one threshold automatically fixes the other one depending on the built-in hysteresis of the comparator.

With reference to

Figure 25

, the following relationships can be established for the ON

(Vsen

ON

) and OFF (Vsen

OFF

) thresholds of the sensed voltage:

Equation 13

Vsen

ON

R

H

− 0 .

485

=

15

⋅

10

− 6 +

0 .

485

R

L which, solved for R

H

and R

L

, yield:

Equation 14

R

H

=

Vsen

ON

− 1 .

15

078

⋅ 10

−

6

⋅ Vsen

OFF

;

Vsen

OFF

R

H

− 0 .

45

=

0 .

45

R

L

R

L

= R

H

Vsen

0 .

45

OFF

− 0 .

45

Figure 26.

AC voltage sensing with the L6566A

Rectified input voltage

For minimum temperature drift

Q

L6561

L6562/A

L6563 3

MULT

Q

R

H

Sensed voltage:

Vsen < 7V

Vcc

5

C

F

AC_OK

16

L6566A

R

L

38/52

It is usually convenient to not use additional dividers connected to high-voltage rails because this could make it difficult to meet no-load consumption targets envisaged by energy-saving regulations.

Figure 26 shows a simple voltage sensing technique that makes

use of the divider already used by the PFC control chip to sense the AC mains voltage with just the addition of an extra tap.

The small-signal NPN Q and the capacitor C

F

create a peak detector, so that the information of the RMS mains voltage can be found across C

F

. The tap position determines the DC voltage to be sensed by the AC_OK pin. It is convenient to use a level as high as possible to minimize the effect of V

BE

changes with temperature. However, it may be necessary to limit the maximum sensed voltage below 7 V to prevent Q’s emitter reverse breakdown; it would not be destructive because the reverse current would be quite small (the resistors seen by

Doc ID 13794 Rev 4

L6566A Application information the base terminal are several ten kW) but this could distort the signal on the MULT pin of the

PFC chip and adversely affect the operation of the pre-regulator. C

F

needs to be quite a big capacitor (in the

μ

F) to have small residual ripple superimposed on the DC level; as a ruleof-thumb, use a time constant (R

L

+ R

H

)·C

F

at least 4-5 times the maximum line cycle period, then fine-tune if needed, considering also transient conditions such as mains missing cycles.

If temperature effects are critical, the NPN Q can be replaced by a PNP-NPN pair arranged as shown in

Figure 26

on the right-hand side; other sensing techniques may also be adopted.

The voltage on the pin is clamped upwards at about 3.15 V; then, if the function is not used, the pin must be connected to Vcc through a resistor (220 to 680 k

Ω

).

The MODE/SC pin (12), when not connected to VREF, provides a voltage ramp during

MOSFET ON-time synchronous to that of the internal oscillator sawtooth, with 0.8 mA minimum current capability. This ramp is intended for implementing additive slope compensation on current sense. This is needed to avoid the sub-harmonic oscillation that arises in all peak-current-mode-controlled converters working at fixed frequency in continuous conduction mode with a duty cycle close to or exceeding 50%.

Figure 27.

Slope compensation waveforms

Internal oscillator

Note:

GD

(pin 4) t

MODE/SC

(pin 12) t t

The compensation is realized by connecting a programming resistor between this pin and the current sense input (pin 7, CS). The CS pin must be connected to the sense resistor with another resistor to make a summing node on the pin. Since no ramp is delivered during

MOSFET OFF-time (see Figure 27 ), no external component other than the programming

resistor is needed to ensure a clean operation at light loads.

The addition of the slope compensation ramp reduces the available dynamics of the current signal; therefore, the value of the sense resistor must be determined taking this into account. Note also that the burst-mode threshold (in terms of power) changes slightly.

If slope compensation is not required with FF operation, the pin is left floating.

Doc ID 13794 Rev 4 39/52

Application information L6566A

5.14 Summary of L6566A power management functions

It has been seen that the device is provided with a number of power management functions: multiple operating mode upon loading conditions, protection functions, as well as interaction with the PFC pre-regulator. To help the user familiarize themselves with these functions, in the following tables all of the themes are summarized with their respective activation mechanisms and the resulting status of the most important pins. This may be useful not only for the correct use of the IC but also for diagnostic purposes: especially at the prototyping/debugging stage, it is quite common to bump into unwanted activation of some functions, and the following tables can be used as a sort of quick troubleshooting guide.

Table 5.

L6566A light load management features

Feature Description

Caused by

IC behavior

Vcc_restar t

(V)

Consump.

(Iqdis,mA)

V

REF

(V)

Burst mode

Controlled

ON-OFF operation for low power consumptio n at light load

V

COMP

<

V

COMPB

M - Hys

Pulseskipping operation

PFC manage ment

PFC OFF at light load,

ON at heavy load

V

COMP

<

V

COMP

O

V

COMP

<

V

COMPL

V

CC_PFC

= 0

V

CC_PFC

= V

CC

N.A.

N.A.

1.34 mA 5

5

SS

V

COMP

(V)

OSC

(V)

FMOD

Unchang ed

V

COMPBM

-HYS

to

V

COMPBM

0/1

Unchang ed unchange d

1

0

0

V

CC

40/52 Doc ID 13794 Rev 4

Table 6.

L6566A protection

Protection Description Caused by

IC behavior

Vcc restart

(V)

IC Iq VREF

(mA) (V)

Short-circuit protection

2

OVP

OLP nd

OCP

Output overvoltage protection

Output overload protection

Output shortcircuit protection

Transformer saturation or shorted secondary diode protection

V

ZCD

>V

ZCDth for 4 consecutive switching cycles

VFF >

VFFlatch

V

COMP

=V

COMPHi

V

SS

> V

SSDIS

V

COMP

=V

COMPHi

V

SS

> V

SSLAT

V

COMP

=V

COMPHi

V

V

SS

>

SSDIS

(4)

V

COMP

=V

COMPHi

V

V

SS

>

SSLAT

(6)

V

CS

> V

CSDIS for 2-3 consecutive switching cycles

Auto restart

(1)

Latched

Auto restart

(2)

Latched

Auto restart

Latched

Latched

5

13.5

5

13.5

5

13.5

5

2.2

0.33

1.46

0.33

1.46

0.33

0.33

5

5

(6)

0

(6)

0

0

0

0

SS

Unchanged

(

6)

0

0

VCOMP

(V)

0

0

<V

V

SS

SSLAT

(3)

V

COMPHi

(6)

<V

V

SS

SSLAT

(6)

V

COMPHi

(5)

0

0

0

0

0

OSC

(V)

0

0

0

0

0

0

FMOD

0

0

0

0

0

0

0

VFF

Unchanged

0

Unchanged

0

Unchanged

0

0

Table 6.

L6566A protection (continued)

Protection Description Caused by

IC behavior

Vcc restart

IC Iq VREF

SS

VCOMP

(V) (mA) (V) (V)

OTP

Brownout

Reference drift

Externally settable overtemperature protection

Internal thermal shutdown

Mains undervoltage protection

V

REF

drift protection

V

T j

> 160 o

C

V

AC_OK

< V th

V

DIS

REF

>V

OTP

> V ov

Latched

Auto restart

(5)

Auto restart

Latched

13.5

5

5

13.5

0.33

0.33

0.33

0.33

0

0

0

0

0

0

0

0

0

0

0

0

Shutdown1

Gate driver disable

V

FF

> V off

Auto restart 5 2.5

5 Unchanged

Shutdown2

Adaptive UVLO

Shutdown by

V

COMP

low

Shutdown by V cc going below V ccoff

(lowering of

V ccoff

threshold at light load)

V

COMP

<

V

COMPOFF

V

( cc

< 9.4 V

VCOMP

V

COMPL

>

)

V cc

< 7.2 V

(

VCOMP

>

V

COMPO

)

Latched

Auto restart

10

5V

0.33

0.18

0

0

0

0

1.

Use One external diode from V

FF

(#15) to AC_OK (#16), cathode to AC_OK2

2.

Use one external diode from SS (#14) to V

REF

(#10), cathode to V

REF

3.

If C ss

and the V cc

capacitor are such that V cc

falls below UVLO before latch tripping ( Figure 21 on page 33

)

4.

If C ss

and the Vcc capacitor are such that the latch is tripped before V cc

falls below UVLO ( Figure 21 on page 33

)

5.

When T

J

< 110 o

C

6.

Discharged to zero by V cc

going below UVLO

Unchanged

0

0

OSC

(V)

0

0

0

0

1

0

0

FMOD

0

0

0

0

VFF

0

0

Unchanged

0

Unchanged Unchanged

0

0

0

0

L6566A Application information

It is worth remembering that “auto-restart” means that the device works intermittently as long as the condition that is activating the function is not removed; “latched” means that the device is stopped as long as the unit is connected to the input power source and the unit must be disconnected for some time from the source in order for the device (and the unit) to restart. Optionally, a restart can be forced by pulling the voltage of pin 16 (AC_OK) below

0.45 V.

Doc ID 13794 Rev 4 43/52

Application examples and ideas

6 Application examples and ideas

L6566A

Figure 28.

Typical low-cost application schematic

PFC Pre-regulator Output bus

Output capacitor of boost

PFC Pre-regulator

R1

D1

DIS

8

VFF 15

MODE/SC

12

FMOD

6

10

VREF

R3 470k

C3

AC_OK

16 1

HVS

5

Vcc

4

GD

IC1

L6566A

13

OSC

14

SS

9

COMP

3

GND

CS

7

11

ZCD

R2

R4

D3

D2

Optional f or

QR operation

C4 R6 C5 C6

Optional f or

QR operation

C2

Q1

R5

T1

D4

C8A,B

Vout

C7 2.2 nF Y1

R7

4

IC3 1

3

TL431

2

C9

R8

R9

R10

Figure 29.

Typical full-feature application schematic (QR operation)

PFC Pre-regulator Output bus

C1 Output capacitor of boost

PFC Pre-regulator

R1

D1

C2

R14

R13 to Vcc pin of

PFC controller

Vcc_PFC to mains v oltage sensing

AC_OK

6

VFF

15

IC1

L6566A

DIS

8

NTC2

10

VREF

12 13

MODE/SC OSC

16

14

SS

1

HVS

5

Vcc

11

4

ZCD

GD

7

CS

9

COMP

3

GND

R18

R2

C3

R3

R4

D3 1N4148

D2

1N4148

Q1

R5

R12

C4 R6 C5 C6

T1

D4

C8A,B

Vout

C7 2.2 nF Y1

R7

IC3 PC817A 1

4

3

TL431

2

C9

R8

R9

R10

44/52 Doc ID 13794 Rev 4

L6566A Application examples and ideas

Figure 30.

Typical full-feature application schematic (FF operation)

PFC Pre-regulator Output bus

T1

C1 Output capacitor of boost

PFC Pre-regulator

R1

C2

D1

D4

C8A,B

R15

R13

R2 to Vcc pin of

PFC controller

Vcc_PFC

6 to mains v oltage sensing

AC_OK

16 1

HVS

5

Vcc

11

4

ZCD

GD

VFF

15

DIS

8

NTC2

10

VREF

13

OSC

IC1

L6566A

14

SS

9

COMP

3

GND

7

CS

MODE/SC

12

R16

C3

R18

R4

R3

D3 1N4148

D2

1N4148

R17

Q1

R5

C7 2.2 nF Y1

IC3 PC817A 1

4

3

2

R12

C4 R6 C5 C6 TL431

Vout

R7

C9

R8

R9

R10

Table 7.

External circuits that determine IC behavior upon OVP and OCP

OVP latched OVP auto-restart

OCP latched

R

H

R

L

SS

14

VREF

10

R

FF

VFF

15

L6566A

R

FF needed if R

L

< 4.7 k Ω

R

H

R

L

SS

AC_OK

14

16

VREF

10

L6566A

VFF

15

Diode needed if R

L

> 4.7 k Ω

OCP auto-restart

R

H

R

L

1N4148

SS

14

R

FF

VFF

15

L6566A

VREF

10

R

FF needed if R

L

< 4.7 k Ω

1N4148

R

H

R

L

SS

AC_OK

14

16

VREF

10

L6566A

VFF

15

Diode needed if R

L

> 4.7 k Ω

Doc ID 13794 Rev 4 45/52

Application examples and ideas

Figure 31.

Frequency foldback at light load (FF operation)

R2

MODE/SC

R1

12

L6566A

10

Vref

COMP

9

OSC

13

R T

BC857

L6566A

Figure 32.

Latched shutdown upon mains overvoltage

Vin

Vcc

5

BC847

L6566A

8 DIS

15 VFF

BC857

>10 Rq

DIS

Vref

10

8

L6566A 15 VFF

Vin

Rq

46/52 Doc ID 13794 Rev 4

L6566A

7 Package mechanical data

Package mechanical data b c

D

A

A1

A2

E

E1 e h

L k ccc

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com

.

ECOPACK is an ST trademark.

Table 8.

SO16N mechanical data

Dim.

Min.

mm

Typ.

Max.

1.75

0.25

0.10

1.25

0.31

0.17

9.80

5.80

3.80

0.25

0.40

0

9.90

6.00

3.90

1.27

0.51

0.25

10.00

6.20

4.00

0.50

1.27

8°

0.10

Doc ID 13794 Rev 4 47/52

Package mechanical data

Figure 33.

Package drawing

L6566A

48/52 Doc ID 13794 Rev 4

0016020_F

L6566A Package mechanical data

Figure 34.

Recommended footprint (dimensions are in mm)

Doc ID 13794 Rev 4 49/52

Order codes

Table 9.

Order codes

Order codes

L6566A

L6566ATR

Package

SO16N

SO16N

Packaging

Tube

Tape and reel

L6566A

50/52 Doc ID 13794 Rev 4

L6566A Revision history

Table 10.

Document revision history

Date

20-Aug-2007

29-May-2008

02-Dec-2008

14-Mar-2012

Revision

1

2

3

4

Changes

First release

Updated V

MODE/SC

value Table 2 on page 11

Updated Figure 1 on page 1 and Section 5.6 on page 27

Modified: Table 4: Electrical characteristics and

Table 8: SO16N mechanical data

; replaced

Figure 33: Package drawing with a more

detailed version; added

Figure 34: Recommended footprint

(dimensions are in mm)

Doc ID 13794 Rev 4 51/52

L6566A

Please Read Carefully:

Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice.

All ST products are sold pursuant to ST’s terms and conditions of sale.

Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.

UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED

WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED

WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS

OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

UNLESS EXPRESSLY APPROVED IN WRITING BY TWO AUTHORIZED ST REPRESENTATIVES, ST PRODUCTS ARE NOT

RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING

APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,

DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE

GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.

Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST.

ST and the ST logo are trademarks or registered trademarks of ST in various countries.

Information in this document supersedes and replaces all information previously supplied.

The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.

© 2012 STMicroelectronics - All rights reserved

STMicroelectronics group of companies

Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -

Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com

52/52 Doc ID 13794 Rev 4