LD39150
Ultra low drop BiCMOS voltage regulator
PPAK
DFN6 (3 x 3 mm)
DPAK
Datasheet
-
production data
Temperature range: -40 to 125 °C
Fast dynamic response to line and load changes
Stable with ceramic capacitor
Available in PPAK, DPAK and DFN6 (3x3 mm)
Applications
Microprocessor power supply
DSPs power supply
Post regulators for switching suppliers
High efficiency linear regulator
Description
Features
1.5 A guaranteed output current
Ultra low dropout voltage (200 mV typ. @ 1.5 A load, 40 mV typ. @ 300 mA load)
Very low quiescent current (1 mA typ. @ 1.5 A load, 1 µA max @ 25 °C in off mode)
Logic-controlled electronic shutdown
Current and thermal internal limit
1.5% output voltage tolerance @ 25 °C
Fixed and ADJ output voltages: 1.8 V, 2.5 V,
3.3 V, ADJ
The LD39150 is a fast ultra low drop linear regulator which operates from 2.5 V to 6 V input supply.
A wide range of output options are available. The low drop voltage, low noise, and ultra low quiescent current make it suitable for low voltage microprocessor and memory applications. The device is developed on a BiCMOS process which allows low quiescent current operation independently of output load current.
Table 1. Device summary
Order codes
Output voltages
DPAK (tape and reel) PPAK (tape and reel) DFN
LD39150DT18-R
LD39150DT25-R
LD39150DT33-R
LD39150PT-R LD39150PU-R
1.8 V
2.5 V
3.3 V
ADJ from 1.22 to 5.0 V
August 2017
This is information on a product in full production.
DocID13159 Rev 5 1/26 www.st.com
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6
7
3
4
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2
Contents
Contents
8
9
10
LD39150
Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7.1
External capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
7.2
Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
7.3
Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
7.4
Thermal note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
7.5
Inhibit input operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
8.1
PPAK package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8.2
DPAK package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8.3
DFN6 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Packaging information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
9.1
DPAK and PPAK packaging information . . . . . . . . . . . . . . . . . . . . . . . . . 21
9.2
DFN6 packaging information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
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LD39150
1 Diagram
Figure 1. Block diagram
Diagram
(*) Not present on ADJ versions.
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26
Pin configuration
2 Pin configuration
Figure 2. Pin connections (top view for DPAK and PPAK, bottom view for DFN)
LD39150
TAB
TAB
CS24140
3
2
5
4
1
TAB
CS24160
3
2
1
CS26660
DFN6 (3 x 3 mm)
PPAK DPAK
Table 2. Pin description
Pin n°
DFN PPAK DPAK
5
3
4
2
1
6
5
2
4
1
3
TAB
SYMBOL NOTE
1
3
2
TAB
V
SENSE
/N.C.
For fixed versions: to be connected with LDO output voltage pins for DFN package and not connected on PPAK
ADJ
V
I
For adjustable version: Error amplifier input pin for V
O
from 1.22 to 5.0 V
LDO input voltage; V
I
from 2.5 V to 6 V, C
I
= 1 µF must be located at a distance of not more than 0.5’’ from input pin.
V
V
O
INH
GND
N.C.
GND
LDO output voltage pins, with minimum C
O
(also refer to C
O
vs ESR stability chart)
= 2.2 µF needed for stability
Inhibit input voltage: ON MODE when V
INH
2 V, OFF MODE when V
INH
0.3 V (Do not leave floating, not internally pulled down/up)
Common ground
Not connected
Electrically connected to GND
Exp.
Pad
Connect to GND (it is not a power GND)
4/26 DocID13159 Rev 5
LD39150
3 Typical application circuits
Typical application circuits
(C
I
and C
O
capacitors must be placed as close as possible to the IC pins)
Figure 3. LD39150 fixed version with inhibit
Note: Inhibit pin is not internally pulled down/up then it must not be left floating. Disable the device when connected to GND or to a positive voltage less than 0.3 V.
Figure 4. LD39150 adjustable version
Note: Set R2 as close as possible to 4.7 k
DocID13159 Rev 5
V
O
= V
REF
(1 + R
1
/R
2
)
5/26
26
Typical application circuits
Figure 5. LD39150 DPAK
LD39150
Figure 6. Timing diagram
6/26 DocID13159 Rev 5
LD39150
4 Maximum
Maximum ratings
Symbol
V
I
V
INH
V
O
V
ADJ
I
O
P
D
T
STG
T
OP
Table 3. Absolute maximum ratings
Parameter
DC input voltage
INHIBIT input voltage
DC output voltage
ADJ pin voltage
Output current
Power dissipation
Storage temperature range
Operating junction temperature range
Value
-0.3 to 6.5
-0.3 to V
I
+0.3 (6.5 V max)
-0.3 to V
I
+0.3 (6.5 V max)
-0.3 to V
I
+0.3 (6.5 V max)
Internally limited
Internally limited
-50 to 150
-40 to 125
Unit mA mW
°C
°C
V
V
V
V
Note: Absolute maximum ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied. All values are referred to GND.
Table 4. Thermal data
Symbol Parameter
R thJA
R thJC
Thermal resistance junction-ambient
Thermal resistance junction-case
1. With PCB ground plane heatsink.
PPAK
100
8
DPAK
100
8
DFN
(1)
40
10
Unit
°C/W
°C/W
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Electrical characteristics LD39150
T
J
= 25 °C, V
I
= V specified.
O
+1 V, C
I
= 1 µF, C
O
= 2.2 µF, I
LOAD
= 10 mA, V
INH
= 2 V, unless otherwise
Symbol
V
I
V
O
V
REF
V
O
V
DROP
I
Q
Parameter
Operating input voltage
Table 5. Electrical characteristics
Parameter
Output voltage tolerance
V
I
= V
O
+1V, I
LOAD
= 10mA to 1.5A
I
V
I
= V
O
LOAD
+1V to 6V, T
J
= -40 to 125°C
= 10mA to 1.5A
Reference voltage
Output voltage LINE regulation
V
O
/ I
LOAD
Output voltage LOAD regulation
Dropout voltage (V
I
- V
O
)
Quiescent current:
ON MODE
Quiescent current:
OFF MODE
V
I
= V
O
+1V to 6V
V
I
= V
O
+1V to 6V, T
J
= -40 to 125°C
I
LOAD
= 10mA to 1.5A
I
LOAD
T
J
= 10mA to 1.5A,
= -40 to 125°C
I
LOAD
= 300mA, T
J
=-40 to 125°C
I
LOAD
= 1.5A, T
J
= -40 to 125°C
I
LOAD
T
J
= 10mA to 1.5A, V
= -40 to 125°C
INH
= 2V
V
INH
= 0.3V
V
INH
= 0.3V, T
J
= -40 to 125°C
Short-circuit protection
I
SC
Inhibit input
Short-circuit protection
V
INH
Inhibit threshold LOW
Inhibit threshold HIGH
T
D-OFF
T
D-ON
I
INH
AC parameters
Current limit
Current limit
Inhibit input current
(1)
R
L
= 0
V
I
= 2.5 to 6V OFF
T
J
= -40 to 125°C
I
LOAD
= 1.5A, V
O
= 3.3V
I
LOAD
= 1.5A, V
O
= 3.3V
V
I
= 6V, V
INH
= 0 to 6V
SVR e
N
Supply voltage rejection
Output noise voltage
V
I
= 4.5 1V,
V
O
= 3.3V,
I
LOAD
= 10mA, f = 120Hz f = 1kHz
B
W
= 10Hz to 100kHz,
C
O
= 2.2µF, V
O
= 2.5V
T
SHDN
Thermal shutdown OFF
Hysteresis
1. Guaranteed by design
Min.
Typ.
Max.
2.5
-1.5
6
1.5
-3 3
Unit
V
% of
V
O(NOM)
2
1.22
0.04
0.1
0.06
0.2
40 80
200 400
1
3
15
15
0.1
65
55
100
170
10
0.2
0.4
2.5
1
5
0.3
1
V
%
%
%/A mV mA
µA
A
V
µs
µA dB
µV
RMS
°C
8/26 DocID13159 Rev 5
LD39150
6
Typical performance characteristics
Typical performance characteristics
T
J
= 25 °C, V
I
= V
O specified.
+ 1 V, C
I
= 1 µF, C
O
= 2.2 µF, I
LOAD
= 10 mA, V
INH
= V
I
, unless otherwise
Figure 7. Output voltage vs temperature Figure 8. Dropout voltage vs temperature
Figure 9. Dropout voltage vs output current Figure 10. Quiescent current vs supply voltage
Figure 11. Quiescent current vs temperature Figure 12. Quiescent current vs temperature
DocID13159 Rev 5 9/26
26
Typical performance characteristics LD39150
Figure 13. Short circuit current vs temperature Figure 14. Output voltage vs input voltage
Figure 15. Stability region vs C
O kHz)
& ESR (at 100 Figure 16. Stability region vs C
O
100 kHz)
& low ESR (at
Figure 17. Load transient Figure 18. Line transient
V
I
= 3.5V, I
O
= 10mA to 1.5A, C
I
= 1µF, C
O
= 2.2µF
10/26
V
I
= 3.5V to 5.5V, I
LOAD
= 10mA, C
O
= 2.2µF
DocID13159 Rev 5
LD39150 Application notes
The LD39150 requires external capacitors for regulator stability. These capacitors must be selected to meet the requirements of minimum capacitance and equivalent series resistance
(see Figure 15 and Figure 16
). The input/output capacitors must be located less than 1cm from the relative pins and connected directly to the input/output ground pins using traces which have no other currents flowing through them.
An input capacitor whose minimum value is 1 µF is required with the LD39150 (amount of capacitance can be increased without limit). This capacitor must be located a distance of not more than 1cm from the input pin of the device and returned to a clean analog ground. Any good quality ceramic, tantalum or film capacitors can be used for this capacitor.
It is possible to use ceramic or tantalum capacitors but the output capacitor must meet the requirement for minimum amount of capacitance and ESR (equivalent series resistance) value. A minimum capacitance of 2.2 µF is a good choice to guarantee the stability of the regulator. Anyway, other C
O
values can be used according to the ( Figure 15 and Figure 16
showing the allowable ESR range as a function of the output capacitance. This curve
)
represents the stability region over the full temperature and I
O
range.
7.5
The output capacitor must maintain its ESR in the stable region over the full operating temperature range to assure stability. Also, capacitors tolerance and variation with temperature must be kept in consideration in order to assure the minimum amount of capacitance at all times.
Inhibit input operation
The inhibit pin can be used to turn OFF the regulator when pulled down, so drastically reducing the current consumption down to less than 1 µA. When the inhibit feature is not used, this pin must be tied to V
I
to keep the regulator output ON at all times. To assure proper operation, the signal source used to drive the inhibit pin must be able to swing above and below the specified thresholds listed in the electrical characteristics section (V
IH
The inhibit pin must not be left floating because it is not internally pulled down/up.
V
IL
).
DocID13159 Rev 5 11/26
26
Package information LD39150
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
12/26 DocID13159 Rev 5
LD39150
8.1 PPAK package information
Figure 19. PPAK outline
Package information
DocID13159 Rev 5
0078180_F
13/26
26
Package information
Dim.
B
B2
C
C2
A
A1
A2
D
D1
E
E1 e
G
G1
H
L2
L4
L5
L6
R
V2
Table 6. PPAK mechanical data mm
Typ.
Min.
2.2
0.9
0.03
0.4
5.2
0.45
0.48
6
5.1
6.4
4.7
1.27
4.9
2.38
9.35
0.8
0.6
1
2.8
0.20
0°
Max.
2.4
1.1
0.23
0.6
5.4
0.6
0.6
6.2
6.6
5.25
2.7
10.1
1
1
8°
LD39150
14/26 DocID13159 Rev 5
LD39150
8.2 DPAK package information
Figure 20. DPAK (TO-252) type A outline
Package information
DocID13159 Rev 5
0068772_K_type_A
15/26
26
Package information
Dim.
D
D1
E
E1 e e1 b b4 c c2
A
A1
A2
H
L
(L1)
L2
L4
R
V2
Table 7. DPAK (TO-252) type A mechanical data mm
Typ.
Min.
2.20
0.90
0.03
0.64
5.20
0.45
0.48
6.00
5.10
6.40
4.70
2.28
4.40
9.35
1.00
2.80
0.80
0.60
0.20
0°
6.60
4.60
10.10
1.50
1.00
8°
Max.
2.40
1.10
0.23
0.90
5.40
0.60
0.60
6.20
LD39150
16/26 DocID13159 Rev 5
LD39150
Figure 21. DPAK footprint (a)
Package information
Footprint_REV_K a. All dimensions are in millimeters
DocID13159 Rev 5 17/26
26
Package information
8.3 DFN6 package information
Figure 22. DFN6 (3 x 3 mm) outline
LD39150
18/26 DocID13159 Rev 5
LD39150
Dim.
b
D
D2
E
E2
A
A1
A3
L
Table 8. DFN6 (3 x 3 mm) mechanical data mm
Typ.
Min.
0.80
0 0.02
0.20
0.23
2.90
2.23
2.90
1.50
3
3
0.30
0.95
0.40
Package information
Max.
1
0.05
0.45
3.10
2.50
3.10
1.75
0.50
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26
Package information
Figure 23. DFN6 footprint (dimensions in mm)
LD39150
20/26 DocID13159 Rev 5
LD39150 Packaging information
9.1 DPAK and PPAK packaging information
Figure 24. Tape for PPAK and DPAK (TO-252)
T
Top cover tape
10 pitches cumulative tolerance on tape +/- 0.2 mm
P0 D P2
B1
K0
For machine ref. only including draft and radii concentric around B0
B0
A0 P1
User direction of feed
D1
F
E
W
User direction of feed
R
Bending radius
AM08852v1
DocID13159 Rev 5 21/26
26
Packaging information
Figure 25. Reel for PPAK and DPAK (TO-252)
REEL DIMENSIONS
40mm min.
Access hole
At slot location
B
D
C
T
A
N
LD39150
Dim.
P0
P1
P2
R
T
W
D1
E
F
K0
A0
B0
B1
D
Full radius Tape slot in core for tape start 25 mm min.
width
G measured at hub
AM08851v2
1.5
1.5
1.65
7.4
2.55
3.9
7.9
1.9
40
0.25
15.7
Table 9. PPAK and DPAK (TO-252) tape and reel mechanical data
Tape Reel mm mm
Dim.
Min.
6.8
10.4
Max.
7
10.6
12.1
1.6
G
N
T
C
D
A
B
Min.
1.5
12.8
20.2
16.4
50
Max.
330
13.2
18.4
22.4
1.85
7.6
2.75
4.1
8.1
2.1
0.35
16.3
Base qty.
Bulk qty.
2500
2500
22/26 DocID13159 Rev 5
LD39150
9.2 DFN6 packaging information
Figure 26. Tape for DFN6
Packaging information
DocID13159 Rev 5 23/26
26
Packaging information
Figure 27. Reel for DFN6
LD39150
24/26
Dim.
A0
B0
K0
Table 10. DFN6 tape and reel mechanical data mm
Min.
3.20
3.20
1
Typ.
3.30
3.30
1.10
Max.
3.40
3.40
1.20
DocID13159 Rev 5
LD39150 Revision history
Date
26-Jan-2007
12-Jan-2009
29-Jan-2013
14-Jan-2014
30-Aug-2017
Revision
1
2
3
4
5
Table 11. Document revision history
Changes
Initial release.
Removed: package DFN8 (4 x 4 mm) and added package DFN6 (3 x 3 mm).
Updated: Table 1 on page 1 .
Document name changed from LD39150XX to LD39150.
Updated Section 8: Package mechanical data .
Added Section 9: Packaging mechanical data
Minor text changes in title, in features and description in cover page.
Removed the following order codes from Table 1: Device summary :
LD39150PT18-R, LD39150PT25-R, LD39150PT33-R, LD39150PU18R,
LD39150PU25R, and LD39150PU33R
DocID13159 Rev 5 25/26
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LD39150
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
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26/26 DocID13159 Rev 5
