STMicroelectronics LDF Datasheet
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LDF
1 A very low drop voltage regulator
Datasheet - production data
Features
Input voltage from 2.6 to 16 V
Very low-dropout voltage (500 mV max. at
1 A load)
Low quiescent current (200 μA typ. @ 1 A load)
Available in 1% precision in PPAK and
DFN6 packages, 2% in DPAK
1 A guaranteed output current
Wide range of output voltages available on request: adjustable from 0.8 V, fixed up to
12 V in 100 mV steps
Logic-controlled electronic shutdown
Power Good (PPAK and DFN packages)
Fast dynamic response to line and load changes
Internal current and thermal protections
Temperature range: -40 °C to 125 °C
Applications
Computer and laptop
Battery-powered equipments
Industrial and medical equipment
Consumer and set-top box
Description
The LDF is a fast, very low drop linear regulator which operates from an input supply voltage in the range of 2.6 V to 16 V.
It is available in fixed and adjustable output voltage versions, from 0.8 V to 12 V.
The LDF features are: high output precision, very low-dropout voltage, low noise, and low quiescent current, therefore suitable for low voltage microprocessors and memory applications.
Enable logic control pin and power-good output are featured on PPAK/DFN packages.
Current and thermal protection are provided.
April 2017 DocID025502 Rev 2
This is information on a product in full production.
1/33 www.st.com
Contents
Contents
LDF
1 Block diagram .................................................................................. 3
2 Pin configuration ............................................................................. 4
3 Typical application .......................................................................... 5
4 Absolute maximum ratings ............................................................. 6
5 Electrical characteristics ................................................................ 7
6 Application information ................................................................ 11
External capacitors .......................................................................... 11
Output capacitor ............................................................................... 11
Output voltage setting for ADJ version ............................................ 11
Enable pin operation ....................................................................... 11
Power Good .................................................................................... 11
7 Typical characteristics .................................................................. 12
8 Package information ..................................................................... 16
DFN6 (3x3) package information .................................................... 16
DFN6 (3x3) packing information ...................................................... 18
DFN6 (2x2) package information .................................................... 20
DFN6 (2x2) packing information ...................................................... 23
PPAK package information ............................................................. 24
DPAK package information ............................................................. 26
PPAK and DPAK packing information ............................................. 29
9 Ordering information ..................................................................... 31
10 Revision history ............................................................................ 32
2/33 DocID025502 Rev 2
LDF
1 Block diagram
Figure 1: Block diagram (generic version)
Block diagram
DocID025502 Rev 2 3/33
Pin configuration
2 Pin configuration
Figure 2: Pin connection (top view)
LDF
4/33
5
2
4
1
3
TAB
Pin n°
PPAK DPAK
-
1
3
-
2
TAB
Pin n°
2
6
1
5
3
4
Exposed pad
Table 1: DPAK, PPAK pin description
Symbol Function
ADJ/PG
V
IN
V
OUT
EN
GND
GND
For adjustable versions: error amplifier input pin
For fixed versions: power-good output
Input voltage
Output voltage
Enable pin logic input: low = shutdown, high = active
Ground
Ground
Table 2: DFN6-2x2 and 3x3 pin description
Symbol Function
ADJ/NC
V
IN
V
OUT
EN
PG
GND
GND
For adjustable versions: error amplifier input pin
For fixed versions: not connected
Input voltage
Output voltage
Enable pin logic input: low = shutdown, high = active
Power-good output
Ground
Ground
DocID025502 Rev 2
LDF
3 Typical application
Figure 3: Fixed versions
Typical application
Figure 4: Adjustable versions (PPAK and DFN6 packages only)
DocID025502 Rev 2 5/33
Absolute maximum ratings
4 Absolute maximum ratings
Symbol
V
IN
V
OUT
V
EN
V
ADJ
V
PG
I
LOAD
P
D
T
STG
T
OP
Table 3: Absolute maximum ratings
Parameter
DC input voltage
DC output voltage
Enable input voltage
ADJ pin voltage
PG pin voltage
Output current
Power dissipation
Storage temperature range
Operating junction temperature range
Value
- 0.3 to 20
- 0.3 to V
IN
+ 0.3
- 0.3 to V
IN
+ 0.3
-0.3 to 2
- 0.3 to V
IN
+ 0.3
Internally limited
Internally limited
- 65 to 150
- 40 to 125
LDF
Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All values are referred to GND.
Symbol
R
R thJA thJC
Parameter
Table 4: Thermal data
Thermal resistance junction-ambient
Thermal resistance junction-case
Value
Unit
PPAK DPAK DFN6-2x2 DFN6-3x3
100
8
100
8
65
6.5
55
10
°C/W
°C/W
Unit
V
V
V
V
V mA mW
°C
°C
6/33 DocID025502 Rev 2
LDF
5
Electrical characteristics
Electrical characteristics
T
J
= 25 °C, V
IN
= V
OUT(NOM)
+ 1 V, C
IN
= 1 μF, C
OUT
= 2.2 μF, I
LOAD
= 10 mA, V
EN
= 2 V, unless otherwise specified.
Symbol
Table 5: LDF (fixed versions) electrical characteristics
Parameter Test conditions Min. Typ. Max. Unit
V
IN
Operating input voltage
2.6 16 V
V
OUT
V
OUT
V
OUT accuracy, PPAK and DFN6 versions
V
OUT
accuracy, DPAK version
ΔV
OUT
Static line regulation
ΔV
OUT
Static load regulation
V
OUT
≤ V
IN
≤ 16 V
I
LOAD
= 10 mA
10 mA ≤ I
LOAD
≤ 1 A
T
J
= -40 to 125 °C
V
OUT
≤ V
IN
≤ 16 V
I
LOAD
= 10 mA
10 mA ≤ I
LOAD
≤ 1 A
T
J
= -40 to 125 °C
V
OUT
≤ V
IN
≤ 16 V
V
OUT
≤ V
IN
≤ 16 V
T
J
= -40 to 125 °C
10 mA ≤ I
LOAD
≤ 1 A
10 mA ≤ I
LOAD
≤ 1 A
T
J
= -40 to 125 °C
-1
-1.5
-2
-3
0.01
0.2
1
1.5
2
3
0.04
0.6
%
%
%
%
%V
%/A
V
DROP
I q
I
SC
V
EN
I
LOAD
= 1 A
-40 °C < T
J
< 125 °C
ON mode: V
EN
= 2 V
I
LOAD
= 10 mA to 1 A
T
J
= -40 to 125 °C
Quiescent current
OFF mode: V
EN
= GND,
PPAK and DFN versions
OFF mode: V
EN
= GND,
PPAK and DFN versions
-40 °C < T
J
< 125 °C
Short-circuit current
Enable input logic low
V
IN
> 3 V
Enable input logic high
V
IN
= 2.6 V to 16 V
-40 °C < T
J
< 125 °C 2
I
EN
Enable pin input current
V
EN
= V
IN
PG
Power-good output threshold
Power-good output voltage low
Rising edge
Falling edge
I
SINK
= 6 mA open drain output
200
200
30
1.5
5
0.92*V
OUT
0.8*V
OUT
0.4
500
800
120
0.8
10 mV
µA
A
V
µA
V
DocID025502 Rev 2 7/33
Electrical characteristics
Symbol
SVR e
N
Parameter
Supply voltage rejection
Output noise voltage
Test conditions
V
IN
= 4.5 V +/- 0.5 V
RIPPLE f = 120 Hz
V
OUT
= 3.3 V
V
IN
= 4.5 V +/- 0.5 V
RIPPLE f = 120 Hz to 100 kHz
V
OUT
= 3.3 V
Bw = 10 Hz to 100 kHz,
I
LOAD
= 100 mA
C
OUT
= 2.2 μF
Min. Typ.
60
45
45
Max.
LDF
Unit dB
μV
RMS
/V
OUT
T
SHDN
Thermal shutdown
Hysteresis
170
10
Notes:
(1)
For V
OUT
< 1.6 V; V
IN
= 2.6 V.
(2)
Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This specification does not apply to output voltages below 1.6 V.
°C
8/33 DocID025502 Rev 2
LDF Electrical characteristics
T
J
= 25 °C, V
IN
= V
OUT(NOM)
+ 1 V, C
IN
= 1 μF, C
OUT
= 2.2 μF, I
LOAD
= 10 mA, V
EN
= 2 V, unless otherwise specified.
Symbol
Table 6: LDF (adjustable version) electrical characteristics
Parameter Test conditions Min. Typ. Max. Unit
V
IN
V
ADJ
Operating input voltage
Reference voltage
Reference voltage tolerance
ΔV
OUT
Static line regulation
V
IN
= V
OUT
V
OUT
≤ V
IN
≤ 16 V
I
LOAD
= 10 mA
2.6
-1
10 mA ≤ I
LOAD
≤ 1 A
T
J
= -40 to 125 °C
V
OUT
≤ V
IN
≤ 16 V
V
OUT
≤ V
IN
≤ 16 V
T
J
= -40 to 125 °C
-1.5
ΔV
OUT
Static load regulation
V
DROP
I q
Quiescent current
10 mA ≤ I
LOAD
≤ 1 A
10 mA ≤ I
LOAD
≤ 1 A
T
J
= -40 to 125 °C
V
OUT
fixed to 2.5 V,
I
LOAD
= 1 A
-40 °C < T
J
< 125 °C
ON mode: V
EN
= 2 V
I
LOAD
= 10 mA to 1 A
T
J
= -40 to 125 °C
OFF mode: V
EN
= GND
PPAK and DFN versions
0.8
0.01
0.2
0.2
200
200
30
16
1
1.5
0.04
0.6
500
800
V
V
%
%V
%/A mV
µA
I
SC
V
EN
I
EN
PG
OFF mode: V
EN
= GND
PPAK and DFN versions
-40 °C < T
J
< 125 °C
Short-circuit current V
IN
> 3 V
Enable input logic low
Enable input logic high
V
IN
= 2.6 V to 16 V
-40 °C < T
J
< 125 °C
Enable pin input current
V
EN
= V
IN
Power-good output threshold
Power-good output voltage low
Rising edge
Falling edge
I
SINK
= 6 mA open drain output
2
1.5
5
0.92*V
ADJ
0.8*V
ADJ
0.4
120
0.8
10
A
V
µA
V
DocID025502 Rev 2 9/33
Electrical characteristics
Symbol Parameter Test conditions
V
IN
= 3 V +/- 0.5 V
RIPPLE f = 120 Hz
V
OUT
= 0.8 V
Min. Typ.
62
Max.
LDF
Unit
SVR
Supply voltage rejection dB e
N
Output noise voltage
V
IN
= 3 V +/- 0.5 V
RIPPLE f = 120 Hz to 100 kHz
V
OUT
= 0.8 V
B w
= 10 Hz to 100 kHz
I
LOAD
= 100 mA
C
OUT
= 2.2 μF
55
50
μV
RMS
/V
OUT
T
SHDN
Thermal shutdown
Hysteresis
170
10
Notes:
(1)
For V
OUT
< 1.6 V; V
IN
= 2.6 V.
(2)
Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This specification does not apply to output voltages below 1.6 V.
°C
10/33 DocID025502 Rev 2
LDF
6
6.1
6.1.1
6.1.2
6.2
6.3
6.4
Application information
Application information
External capacitors
The LDF voltage regulator requires external ceramic capacitors to assure the control loop stability. These capacitors must be selected to meet the requirements of minimum
capacitance and equivalent series resistance (see Figure 25: "Stability plane ADJ (C
ESR)" and Figure 26: "Stability plane 3.3 V (C
, ESR)" . Input/output capacitors should be
located as closer as possible to the relative pins.
Input capacitor
An input capacitor, whose minimum value is 1 μF, must not be located farther than 0.5" from the input pin of the device and returned to a clean analog ground.
Output capacitor
Ceramic capacitors could be used on the output, provided that they must meet the minimum amount of capacitance and E.S.R. (equivalent series resistance) value required.
2.2 μF is suggested as minimum capacitance to guarantee the stability of the regulator.
Anyway, other COUT values can be used according to the Figure 25: "Stability plane ADJ
, ESR)" and Figure 26: "Stability plane 3.3 V (C
, ESR)" showing the allowable ESR
range as a function of the output capacitance. The output capacitor must maintain its ESR in the stable region over the full operating temperature range to assure stability. Besides, capacitor tolerance and temperature variation must be taken into account to assure the minimum amount of capacitance.
Output voltage setting for ADJ version
In the adjustable version, the output voltage can be set from 0.8 V up to the input voltage minus the voltage drop across the pass transistor (dropout voltage), by connecting a resistor divider between the ADJ pin and the output, thus allowing remote voltage sensing.
The resistor divider could be selected by the following equation:
𝑉
𝑂𝑈𝑇
= 𝑉
𝐴𝐷𝐽
⁄ ) 𝑤𝑖𝑡ℎ 𝑉
𝐴𝐷𝐽
= 0.8 𝑉(𝑡𝑦𝑝. )
It is recommended to use resistors with values in the range of 10 kΩ to 100 kΩ. Lower values can also be suitable, but current consumption increases.
Enable pin operation
This pin can be used to turn OFF the regulator when it is pulled down, so to drastically reduce the current consumption. When the enable feature is not used, this pin must be tied to V
IN
to keep the regulator output in ON state every time. To assure the proper operation, the signal source, used to drive the EN pin, must be able to swing above and below the specified thresholds listed in the electrical characteristics (V
EN
). The EN pin must not be left floating because it is not internally pulled down/up.
Power Good
The LDF features an open drain PG pin to sequence either external supplies or loads and to provide fault detection. This pin requires an external resistor (R
PG
) to pull Power Good high when the output is within the power-good tolerance window. Typical values for this resistor range from 10 kΩ to 100 kΩ.
DocID025502 Rev 2 11/33
Typical characteristics LDF
7 Typical characteristics
C
IN
= C
OUT
= 1 μF, V
IN
= V
OUT
+1 V, V
EN
to V
IN
, I
OUT
= 10 mA, unless otherwise specified.
Figure 5: Output voltage vs. temperature, fixed version
Figure 6: Output voltage vs. temperature, adjustable version
Figure 7: Line regulation vs. temperature Figure 8: Load regulation vs. temperature
12/33 DocID025502 Rev 2
LDF
Figure 9: Short-circuit current vs. dropout
Typical characteristics
Figure 10: Dropout voltage vs. temperature
Figure 11: Quiescent current vs. temperature,
I
OUT
= 10 mA
Figure 12: Quiescent current vs. temperature,
I
OUT
= 1 A
Figure 13: Shutdown current vs. temperature
Figure 14: Enable pin current vs. temperature
DocID025502 Rev 2 13/33
Typical characteristics
Figure 15: Enable high threshold vs. temperature
LDF
Figure 16: Enable low threshold vs. temperature
Figure 17: Output voltage vs. input voltage Figure 18: Line transient
Figure 19: Load transient (V
OUT
= 3.3 V) Figure 20: Load transient (V
OUT
= V
ADJ
)
14/33 DocID025502 Rev 2
LDF
Figure 21: Start-up transient
Typical characteristics
Figure 22: Enable transient
Figure 23: SVR vs. frequency (V
OUT
= 5 V) Figure 24: SVR vs. frequency (V
OUT
= V
ADJ
)
Figure 25: Stability plane ADJ (C
OUT
, ESR) Figure 26: Stability plane 3.3 V (C
OUT
, ESR)
DocID025502 Rev 2 15/33
Package information
8
8.1
Package information
LDF
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
DFN6 (3x3) package information
Figure 27: DFN6 (3x3) package outline
16/33 DocID025502 Rev 2
LDF
Dim.
D
D2
E
E2
A
A1
A3 b e
L
Table 7: DFN6 (3x3) mechanical data mm
Min. Typ.
0.80
0 0.02
0.20
0.23
2.90
2.23
2.90
1.50
3
3
0.30
0.95
0.40
Figure 28: DFN6 (3x3) recommended footprint
Package information
Max.
1
0.05
0.45
3.10
2.50
3.10
1.75
0.50
DocID025502 Rev 2 17/33
Package information
8.2 DFN6 (3x3) packing information
Figure 29: DFN6 (3x3) tape outline
LDF
18/33 DocID025502 Rev 2
7875978_N
LDF
Figure 30: DFN6 (3x3) reel outline
Package information
Dim.
A0
B0
K0
7875978_N
Table 8: DFN6 (3x3) tape and reel mechanical data mm
Min.
3.20
3.20
1
Typ.
3.30
3.30
1.10
Max.
3.40
3.40
1.20
DocID025502 Rev 2 19/33
Package information
8.3 DFN6 (2x2) package information
Figure 31: DFN6 (2x2) package outline
LDF
20/33 DocID025502 Rev 2
LDF
Dim.
A
A1 b
D
E e
D2
E2
L
K aaa bbb ccc ddd eee
N
Table 9: DFN6 (2x2) mechanical data mm
Min. Typ.
0.80
0.00
0.25
0.90
0.02
0.30
2.00 BSC
2.00 BSC
0.65 BSC
1.45
0.85
0.20
0.15
0.05
0.10
0.10
0.05
0.08
6
Package information
Max.
1.00
0.05
0.35
1.70
1.10
0.30
DocID025502 Rev 2 21/33
Package information
Figure 32: DFN6 (2x2) recommended footprint
LDF
22/33 DocID025502 Rev 2
LDF
8.4 DFN6 (2x2) packing information
Figure 33: DFN6 (2x2) reel outline
Package information
Dim.
A0
B0
K0
P0
P
A
C
D
N
T
Table 10: DFN6 (2x2) tape and reel mechanical data mm
Min. Typ.
12.8
20.2
60
2.4
2.4
1.3
4
4
DocID025502 Rev 2
Max.
180
13.2
14.4
23/33
Package information
8.5 PPAK package information
Figure 34: PPAK package outline
LDF
24/33 DocID025502 Rev 2
LDF
Dim.
D1
E
E1 e
G
G1
H
B2
C
C2
D
A
A1
A2
B
L2
L4
L5
L6
R
V2
Table 11: PPAK mechanical data mm
Min. Typ.
2.2
0.9
0.03
0.4
5.2
0.45
0.48
6
5.1
6.4
4.7
1.27
4.9
2.38
9.35
0.8
0.6
1
2.8
0.20
0°
Package information
6.6
5.25
2.7
10.1
1
1
8°
Max.
2.4
1.1
0.23
0.6
5.4
0.6
0.6
6.2
DocID025502 Rev 2 25/33
Package information
8.6 DPAK package information
Figure 35: DPAK package outline
LDF
0068772_A_21
26/33 DocID025502 Rev 2
LDF
Dim.
D1
E
E1 e e1
H
L
(L1)
L2
L4
R
V2 b4 c c2
D
A
A1
A2 b
Table 12: DPAK mechanical data mm
Min. Typ.
2.20
0.90
0.03
0.64
5.20
0.45
0.48
6.00
5.10
6.40
4.70
2.28
4.40
9.35
1.00
2.80
0.80
0.60
0.20
0°
Package information
6.60
4.60
10.10
1.50
Max.
2.40
1.10
0.23
0.90
5.40
0.60
0.60
6.20
1.00
8°
DocID025502 Rev 2 27/33
Package information
Figure 36: DPAK recommended footprint (dimensions are in mm)
LDF
28/33 DocID025502 Rev 2
LDF
8.7 PPAK and DPAK packing information
Figure 37: PPAK and DPAK tape
Package information
DocID025502 Rev 2 29/33
Package information
Figure 38: PPAK and DPAK reel
LDF
30/33
Dim.
P0
P1
P2
R
T
W
D1
E
F
K0
A0
B0
B1
D
3.9
7.9
1.9
40
0.25
15.7
1.5
1.5
1.65
7.4
2.55
Table 13: PPAK and DPAK tape and reel mechanical data
Tape Reel mm
Dim.
Min.
6.8
10.4
Max.
7
10.6
12.1
1.6
1.85
7.6
2.75
4.1
8.1
2.1
A
B
C
D
G
N
T
Base qty.
Bulk qty.
Min.
1.5
12.8
20.2
16.4
50
0.35
16.3 mm
Max.
330
13.2
18.4
22.4
2500
2500
DocID025502 Rev 2
LDF
9 Ordering information
Different output voltage versions of the LDF available on request:
PPAK
Table 14: Order code
Package
DPAK DFN6-3x3 DFN6-2x2
LDF18PT-TR
LDF25PT-TR
LDF33PT-TR
LDFPT-TR
LDF33DT-TR
LDFPUR LDFPVR
Ordering information
Output voltage (V)
1.8
2.5
3.3
ADJ
DocID025502 Rev 2 31/33
Revision history
10 Revision history
Date Revision
Table 15: Document revision history
Changes
05-Dec-2013
12-Apr-2017
1
2
Initial release.
Updated Figure 14: "Enable pin current vs. temperature" and
Section 8: "Package information" .
Added Section 6.2: "Output voltage setting for ADJ version" .
Minor text changes.
LDF
32/33 DocID025502 Rev 2
LDF
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2017 STMicroelectronics
– All rights reserved
DocID025502 Rev 2 33/33
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