STL36N60M6
Datasheet
N-channel 600 V, 91 mΩ typ., 25 A MDmesh™ M6
Power MOSFET in a PowerFLAT™ 8x8 HV package
4
3
2
1
5
PowerFLAT™ 8x8 HV
Drain(5)
Gate(1)
Applications
• Switching applications
• LLC converters
• Boost PFC converters
Driver source (2)
Power source (3, 4)
NG1DS2PS34D5Z
Product status link
STL36N60M6
Description
The new MDmesh™ M6 technology incorporates the most recent advancements to the well-known and consolidated MDmesh family of SJ MOSFETs.
STMicroelectronics builds on the previous generation of MDmesh devices through its new M6 technology, which combines excellent R
DS(on)
per area improvement with one of the most effective switching behaviors available, as well as a user-friendly experience for maximum end-application efficiency.
Product summary
Order code STL36N60M6
Marking
Package
Packing
36N60M6
PowerFLAT™ 8x8 HV
Tape and reel
Features
Order code
STL36N60M6
V
DS
600 V
R
DS(on)
max.
110 mΩ
• Reduced switching losses
• Lower R
DS(on)
x area vs previous generation
• Low gate input resistance
• 100% avalanche tested
• Zener-protected
• Excellent switching performance thanks to the extra driving source pin
I
D
25 A
DS11134 - Rev 4 - September 2018
For further information contact your local STMicroelectronics sales office.
www.st.com
STL36N60M6
Electrical ratings
1
Electrical ratings
Table 1. Absolute maximum ratings
Symbol Parameter
V
GS
I
D
I
D
I
DM
(1)
P
TOT
dv/dt (2)
Gate-source voltage
Drain current (continuous) at T
C
Drain current (continuous) at T
C
Drain current (pulsed)
Total dissipation at T
C
= 25 °C
= 25 °C
= 100 °C
dv/dt (3)
T stg
T j
Peak diode recovery voltage slope
MOSFET dv/dt ruggedness
Storage temperature range
Operating junction temperature range
1. Pulse width limited by safe operating area.
2. I
SD
≤ 25 A, di/dt ≤ 400 A/µs; V
DS(peak)
< V
(BR)DSS
, V
DD
= 400 V.
3. V
DS
≤ 480 V
Table 2. Thermal data
Symbol
R thj-case
R thj-pcb
(1)
Parameter
Thermal resistance junction-case
Thermal resistance junction-pcb
1. When mounted on FR-4 board of inch², 2oz Cu.
Symbol
I
AR
E
AS
Table 3. Avalanche characteristics
Parameter
Avalanche current, repetitive or not repetitive
(pulse width limited by T jmax
)
Single pulse avalanche energy (starting T j
= 25 °C, I
D
= I
AR
V
DD
= 50 V)
;
Value
±25
25
15.6
100
160
15
50
-55 to 150
Unit
V
A
A
A
W
V/ns
V/ns
°C
Value
0.78
45
Unit
°C/W
°C/W
Value
5
750
Unit
A mJ
DS11134 - Rev 4 page 2/15
2
STL36N60M6
Electrical characteristics
Electrical characteristics
T
C
= 25 °C unless otherwise specified
Table 4. On/off states
Symbol
V
(BR)DSS
Parameter
Drain-source breakdown voltage
V
GS
= 0 V, I
Test conditions
D
= 1 mA
V
R
I
I
DSS
GSS
GS(th)
DS(on)
Zero gate voltage Drain current
Gate-body leakage current
Gate threshold voltage
Static drain-source onresistance
1. Defined by design, not subject to production test.
V
GS
= 0 V, V
DS
= 600 V
V
GS
= 0 V, V
DS
= 600 V, T
C
= 125 °C (1)
V
DS
V
DS
= 0 V, V
= V
GS
GS
, I
D
= ±25 V
= 250 µA
V
GS
= 10 V, I
D
= 12.5 A
Min.
Typ.
Max.
Unit
600 V
3.25
4
91
1
100
±5
4.75
110
µA
µA
µA
V mΩ
Table 5. Dynamic
Symbol
C iss
C oss
C rss
C oss eq.
(1)
R
G
Q g
Q gs
Q gd
Parameter
Input capacitance
Output capacitance
Reverse transfer capacitance
V
DS
Test conditions
= 100 V, f = 1 MHz, V
GS
Equivalent output capacitance V
DS
= 0 to 480 V, V
GS
= 0 V
Intrinsic gate resistance f = 1 MHz, I
D
= 0 A
Total gate charge
Gate-source charge
Gate-drain charge
= 0 V
V
DD
= 480 V, I
D
= 30 A, V
GS
= 0 to 10 V
(see Figure 14. Test circuit for gate charge behavior )
Min.
-
-
-
-
-
-
-
-
Typ.
1960
93
6
332
1.6
44.3
10.1
25
Max.
-
-
-
-
-
-
-
-
Unit pF pF pF pF
Ω nC nC nC
1. C oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C oss
when V to 80% V
DSS
DS
increases from 0
Symbol t d(on) t r t d(off) t f
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Table 6. Switching times
Test conditions
V
DD
V
GS
= 300 V, I
D
= 15 A R
G
= 4.7 Ω,
= 10 V (see
Figure 13. Switching times test circuit for resistive load
and
Figure 18. Switching time waveform )
Min.
Typ.
Max.
Unit
15.2
ns
5.3
ns
-
50.2
7.3
-
ns ns
DS11134 - Rev 4 page 3/15
STL36N60M6
Electrical characteristics
Table 7. Source-drain diode
Symbol
I
SD
I
SDM
(1)
V
SD
(2)
t rr
Q rr
I
RRM t rr
Q rr
I
RRM
Parameter
Source-drain current
Source-drain current (pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Reverse recovery time
Reverse recovery charge
Reverse recovery current
1. Pulse width is limited by safe operating area
2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
Test conditions
V
GS
= 0 V, I
SD
= 25 A
I
SD
= 30 A, di/dt = 100 A/µs, V
DD
= 60 V
(see Figure 15. Test circuit for inductive load switching and diode recovery times
)
I
SD
T j
= 30 A, di/dt = 100 A/µs, V
DD
= 60 V,
= 150 °C (see
Figure 15. Test circuit for inductive load switching and diode recovery times )
-
-
-
-
-
-
Min.
Typ.
Max.
Unit
25 A
-
100
1.6
A
V
340
5.3
31
430
7.7
36 ns
µC
A ns
µC
A
DS11134 - Rev 4 page 4/15
STL36N60M6
Electrical characteristics (curves)
2.1
Electrical characteristics (curves)
Figure 1. Safe operating area
I
D
(A)
GIPG200920180941SOA
Operation in this area is limited by R
DS(on)
10 2
10 1
10 0
10 -1
10 -1 10 0
T
J
≤150 °C
T
C
V
GS
=25 °C
=10 V single pulse
10 1 10 2 t p
=1 µs t p
=10 µs t p
=100 µs t p
=1 ms t p
=10 ms
V
DS
(V)
I
D
(A)
100
Figure 3. Output characteristics
GADG220320170910OCH
V
GS
= 9, 10V
80
V
GS
= 8V
60
40
V
GS
= 7V
V
GS
= 6V
20
0
V
GS
= 5V
0 2 4 6 8 10 12 14 16 V
DS
(V)
Figure 5. Gate charge vs gate-source voltage
V
GS
(V)
12
10 V
DS
GADG030220171159QVG V
DS
(V)
V
DD
= 480 V
I
D
= 30 A
600
500
8 400
6
4
2
0
0 10 20 30 40 50
300
200
100
0
Q g
(nC)
Figure 2. Thermal impedance
Zth PowerFLAT 8x8 HV
K
δ=0.5
0.2
10
-1
0.1
0.02
0.05
10 -2
10 -5
Single pulse
0.01
10 -4
10
-3
Zth= K*RthJ-c
δ= tp/ Ƭ tp
Ƭ
10
-2 t p
(s)
60
40
20
0
3
I
D
(A)
100
Figure 4. Transfer characteristics
GADG220320170910TCH
V
DS
= 18V
80
4 5 6 7 8 9 V
GS
(V)
Figure 6. Static drain-source on-resistance
R
DS(on)
(mΩ)
97
V
GS
= 10 V
GIPG200920180942RID
91
89
95
93
87
85
0 4 8 12 16 20 24 I
D
(A)
DS11134 - Rev 4 page 5/15
STL36N60M6
Electrical characteristics (curves)
Figure 7. Capacitance variations
C
(pF)
GADG220320170921CVR
10 4
C
ISS
10 3
10 2
10 1
10 0
10 -1 10 0 f= 1MHz
10 1 10 2
C
OSS
C
RSS
V
DS
(V)
Figure 9. Normalized on-resistance vs temperature
R
DS(on)
(norm.)
GIPG300920151317RON
V
GS
= 10 V
2.2
1.8
1.4
1.0
0.6
0.2
-75 -25 25 75 125 T
J
(°C)
Figure 11. Output capacitance stored energy
E
OSS
(µJ)
GADG010220171214EOS
16
12
8
4
0
0 100 200 300 400 500 600 V
DS
(V)
Figure 8. Normalized gate threshold voltage vs temperature
V
GS(th)
(norm.)
1.1
GIPG300920151316VTH
I
D
= 250 µA
1.0
0.9
0.8
0.7
0.6
-75 -25 25 75 125 T
J
(°C)
Figure 10. Normalized V
(BR)DSS
vs temperature
V
(BR)DSS
(norm.)
GIPG300920151318BDV
I
D
= 1 mA
1.08
1.04
1.00
0.96
0.92
0.88
-75 -25 25 75 125 T
J
(°C)
Figure 12. Source-drain diode forward characteristics
V
SD
(V)
1.1
GIPG200920180943SDF
T
J
= -50 ℃
1.0
0.9
0.8
0.7
0.6
0.5
0 4 8
T
J
= 25 ℃
T
J
= 150 ℃
12 16 20 24 I
SD
(A)
DS11134 - Rev 4 page 6/15
STL36N60M6
Test circuits
3
Test circuits
Figure 13. Switching times test circuit for resistive load
R
L
V
GS
V
D
R
G
P
W
GND1
(driver signal)
GND2
(power)
D.U.T.
+
2200
µF
3.3
µF
V DD
AM15855v1
Figure 15. Test circuit for inductive load switching and diode recovery times
25Ω
G
A
D
D.U.T.
S
B
R
G
A
FAST
DIODE
A
B
B
D
L=100µH
G
S
D.U.T.
3.3
µF
+
1000
µF
V
DD
GND1
GND2
AM15857v1
Figure 17. Unclamped inductive waveform
V
(BR)DSS
V
D
I
DM
I
D
V
DD V
DD
AM01472v1
Figure 14. Test circuit for gate charge behavior
V DD
12V
47kΩ
100nF
1kΩ
I G =CONST
V i
≤ V
GS
+
2200
µF 2.7kΩ
100Ω
D.U.T.
V
G
47kΩ
P W
1kΩ
GND1 GND2
AM15856v1
Figure 16. Unclamped inductive load test circuit
L
V D
I D
V i
P w
GND1 GND2
D.U.T.
+
2200
µF
3.3
µF
V DD
AM15858v1
0
Figure 18. Switching time waveform t d(on) t on t r t d(off) t off t f
90% 90%
10%
V
GS
V
DS
90%
10%
0 10%
AM01473v1
DS11134 - Rev 4 page 7/15
4
STL36N60M6
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
. ECOPACK ® is an ST trademark.
DS11134 - Rev 4 page 8/15
4.1
STL36N60M6
PowerFLAT™ 8x8 HV package information
PowerFLAT™ 8x8 HV package information
Figure 19. PowerFLAT™ 8x8 HV package outline
DS11134 - Rev 4
8222871_Rev_4 page 9/15
Ref.
D2
E1
E2 e
L
A
A1
A3 b
D
E
STL36N60M6
PowerFLAT™ 8x8 HV package information
Table 8. PowerFLAT™ 8x8 HV mechanical data
Min.
0.75
0.00
0.10
0.90
7.90
7.90
7.10
2.65
4.25
0.40
Dimensions (in mm)
Typ.
0.85
0.20
1.00
8.00
8.00
7.20
2.75
4.35
2.00 BSC
0.50
Figure 20. PowerFLAT™ 8x8 HV footprint
Max.
0.95
0.05
0.30
1.10
8.10
8.10
7.30
2.85
4.45
0.60
Note: All dimensions are in millimeters.
DS11134 - Rev 4
8222871_REV_4_footprint page 10/15
4.2
STL36N60M6
PowerFLAT™ 8x8 HV packing information
PowerFLAT™ 8x8 HV packing information
Figure 21. PowerFLAT™ 8x8 HV tape
P0 (4.0±0.1) P2 (2.0±0.1)
D0 ( 1.55±0.05) T (0.30±0.05)
E (1.75±0.1)
D1 ( 1.5 Min)
P1 (12.00±0.1) A0 (8.30±0.1)
K0 (1.10±0.1)
Note:
Note: Base and Bulk qu antity 3000 pcs
All dimensions are in millimeters.
Figure 22. PowerFLAT™ 8x8 HV package orientation in carrier tape
8229819_Tape_revA
DS11134 - Rev 4 page 11/15
STL36N60M6
PowerFLAT™ 8x8 HV packing information
Figure 23. PowerFLAT™ 8x8 HV reel
Note: All dimensions are in millimeters.
8229819_Reel_revA
DS11134 - Rev 4 page 12/15
STL36N60M6
Revision history
Date
03-Jul-2015
09-Jul-2015
07-Aug-2015
20-Sep-2018
Revision
1
2
3
4
Table 9. Document revision history
Changes
First release.
Updated Figure 1: "Internal schematic diagram" in cover page .
Text and formatting changes throughout document.
Datasheet promoted from preliminary data to production data.
On cover page:
- updated title description and package silhouette
In section Electrical ratings:
- updated table Avalanche characteristics
In section Electrical characteristics:
- updated tables On/off states, Dynamic, Switching times and Source drain diode
Added section Electrical characteristics (curves)
Modified features table on cover page.
Modified
Table 4. On/off states , Table 5. Dynamic , Table 6. Switching times
and
Table 7. Source-drain diode .
Modified
Section 2.1 Electrical characteristics (curves) .
Minor text changes.
DS11134 - Rev 4 page 13/15
STL36N60M6
Contents
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2.1
Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4.1
PowerFLAT™ 8x8 HV package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2
PowerFLAT™ 8x8 HV packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
DS11134 - Rev 4 page 14/15
STL36N60M6
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
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ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2018 STMicroelectronics – All rights reserved
DS11134 - Rev 4 page 15/15
