STL33N60M6
Datasheet
N-channel 600 V, 0.115 Ω typ., 21 A MDmesh™ M6 Power MOSFET in a PowerFLAT™ 8x8 HV package
4
3
2
1
Gate(1)
5
PowerFLAT™ 8x8 HV
Drain(5)
Features
Order code
STL33N60M6
V
DS
600 V
• Reduced switching losses
• Lower R
DS(on)
per area vs previous generation
• Low gate input resistance
• 100% avalanche tested
• Zener-protected
R
DS(on)
max.
137 mΩ
Applications
• Switching applications
• LLC converters
• Boost PFC converters
I
D
21 A
Driver source (2)
Power source (3, 4)
NG1DS2PS34D5Z
Description
The new MDmesh™ M6 technology incorporates the most recent advancements to the well-known and consolidated MDmesh family of SJ MOSFETs.
STMicroelectronics builds on the previous generation of MDmesh devices through its new M6 technology, which combines excellent R
DS(on)
per area improvement with one of the most effective switching behaviors available, as well as a user-friendly experience for maximum end-application efficiency.
Product status link
STL33N60M6
Product summary
Order code STL33N60M6
Marking
Package
Packing
33N60M6
PowerFLAT™ 8x8 HV
Tape and reel
DS12638 - Rev 3 - August 2018
For further information contact your local STMicroelectronics sales office.
www.st.com
STL33N60M6
Electrical ratings
1
Electrical ratings
Table 1. Absolute maximum ratings
Symbol
V
GS
Gate-source voltage
Parameter
I
D
Drain current (continuous) at T case
= 25 °C
Drain current (continuous) at T case
= 100 °C
I
DM
(1)
P
TOT
dv/dt (2)
Drain current (pulsed)
Total dissipation at T case
= 25 °C
dv/dt (3)
T stg
T j
Peak diode recovery voltage slope
MOSFET dv/dt ruggedness
Storage temperature range
Operating junction temperature range
1. Pulse width is limited by safe operating area.
2. I
SD
≤ 21 A, di/dt = 400 A/μs, V
DS
< V
(BR)DSS
, V
DD
= 400 V
3. V
DS
≤ 480 V
Table 2. Thermal data
Symbol
R thj-case
R thj-pcb
(1)
Parameter
Thermal resistance junction-case
Thermal resistance junction-pcb
1. When mounted on FR-4 board of inch², 2oz Cu.
Symbol
I
AR
E
AS
Table 3. Avalanche characteristics
Parameter
Avalanche current, repetitive or non-repetitive
(pulse width limited by T
Jmax
)
Single pulse avalanche energy
(starting T j
= 25 °C, I
D
= I
AR
, V
DD
= 50 V)
Value
±25
21
13
78
150
15
50
-55 to 150
Unit
V
A
A
W
V/ns
°C
Value
0.83
45
Unit
°C/W
°C/W
Value
4
500
Unit
A mJ
DS12638 - Rev 3 page 2/15
2
STL33N60M6
Electrical characteristics
Electrical characteristics
(T case
= 25 °C unless otherwise specified).
Table 4. On/off states
Symbol
V
(BR)DSS
Parameter
Drain-source breakdown voltage
V
GS
= 0 V, I
Test conditions
D
= 1 mA
V
R
I
DSS
I
GSS
GS(th)
DS(on)
Zero gate voltage drain current
Gate-body leakage current
Gate threshold voltage
Static drain-source onresistance
1. Defined by design, not subject to production test.
V
GS
= 0 V, V
DS
= 600 V
V
GS
= 0 V, V
DS
= 600 V,
T case
= 125 °C
(1)
V
DS
V
DS
= 0 V, V
= V
GS
GS
, I
D
= ±25 V
= 250 µA
V
GS
= 10 V, I
D
= 10.5 A
Min.
Typ.
Max.
Unit
600 V
1
µA
100
3.25
4
±5
4.75
0.115
0.137
µA
V
Ω
Table 5. Dynamic
Symbol
C iss
C oss
C rss
C oss eq.
(1)
R
G
Q g
Q gs
Q gd
Parameter
Input capacitance
Test conditions
Output capacitance
Reverse transfer capacitance
V
DS
= 100 V, f = 1 MHz, V
GS
= 0 V
Equivalent output capacitance V
DS
= 0 to 480 V, V
GS
= 0 V
Intrinsic gate resistance f = 1 MHz, I
D
= 0 A
Total gate charge
Gate-source charge
Gate-drain charge
V
DD
= 480 V, I
D
= 25 A,
V
GS
= 0 to 10 V
(see Figure 14. Test circuit for gate charge behavior )
Min.
Typ.
Max.
Unit
-
-
-
-
-
-
-
-
1515
128
4.2
269
1.5
33.4
7.2
16.3
-
-
-
-
-
-
-
pF pF
Ω nC
1. C oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C oss
when V
DS
increases from 0 to 80% V
DSS
.
Symbol t d(on) t r t d(off) t f
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Table 6. Switching times
Test conditions
V
DD
= 300 V, I
D
= 12.5 A,
R
G
= 4.7 Ω, V
GS
= 10 V
(see Figure 13. Switching times test circuit for resistive load and Figure
18. Switching time waveform
)
Min.
Typ.
Max.
Unit
-
-
-
-
19.5
33
38.5
7.5
-
-
-
ns
DS12638 - Rev 3 page 3/15
STL33N60M6
Electrical characteristics
Table 7. Source-drain diode
Symbol
I
SD
I
SDM
(1)
V
SD
I
I t
Q
RRM t
Q rr rr rr rr
(2)
RRM
Parameter
Source-drain current
Source-drain current (pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Reverse recovery time
Reverse recovery charge
Reverse recovery current
1. Pulse width is limited by safe operating area.
2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
Test conditions
I
SD
= 21 A, V
GS
= 0 V
I
SD
= 25 A, di/dt = 100 A/µs,
V
DD
= 60 V
(see Figure 15. Test circuit for inductive load switching and diode recovery times
)
I
SD
= 25 A, di/dt = 100 A/µs, V
DD
= 60 V,
T j
= 150 °C
(see Figure 15. Test circuit for inductive load switching and diode recovery times
)
Min.
Typ.
Max.
Unit
21 A
-
-
-
265
3.07
78
1.6
A
V ns
µC
-
-
-
23.2
374
5.78
30.9
A ns
µC
A
DS12638 - Rev 3 page 4/15
STL33N60M6
Electrical characteristics (curves)
2.1
Electrical characteristics (curves)
I
D
(A)
Figure 1. Safe operating area
GIPG200620181213SOA
10 1 t p
=1 µs t p
=10 µs
10 0
10 -1
10 -1
Operation in this area is limited by R
DS(on)
10 0
T
J
T
C
V
≤150 °C
=25 °C
GS
=10 V single pulse
10 1 10 2 t p
=100 µs t p
=1 ms t p
=10 ms
V
DS
(V)
40
30
20
I
D
(A)
70
60
50
10
0
0
Figure 3. Output characteristics
4
V
GS
= 9, 10 V
GIPG150620181232OCH
V
GS
=8 V
8
V
GS
=7 V
12
V
GS
=6 V
V
GS
=5 V
16 V
DS
(V)
Figure 5. Gate charge vs gate-source voltage
V
GS
(V)
12
10
V
DS
V
I
D
DD
= 480 V
= 25 A
GIPG150620181237QVG V
DS
(V)
600
500
4
2
0
0
8
6
8 16 24 32 40
400
300
200
100
Q
0 g
(nC)
K
Figure 2. Thermal impedance
PowerFLAT8x8HVzth
δ =0.5
10 -1
δ =0.2
δ =0.1
δ =0.05
δ =0.02
δ =0.01
Single pulse
10 -2
10 -5 10 -4 10 -3
Z th
=K*R thj-c
δ=t p
/ Ƭ t p
Ƭ
10 -2 t p
(s)
Figure 4. Transfer characteristics
40
30
20
I
D
(A)
70
60
50
10
0
3 4
V
DS
= 20 V
5 6
GIPG150620181233TCH
7 8 9 V
GS
(V)
Figure 6. Static drain-source on-resistance
R
DS(on)
(Ω)
GIPG260620180835RID
0.125
V
GS
= 10 V
0.120
0.115
0.110
0.105
0 4 8 12 16 20 I
D
(A)
DS12638 - Rev 3 page 5/15
STL33N60M6
Electrical characteristics (curves)
C
(pF)
Figure 7. Capacitance variations
GIPG150620181232CVR
10 4
10 3
10 2
10 1
10 0
10 -1 f = 1 MHz
10 0 10 1 10 2
C
ISS
C
OSS
C
RSS
V
DS
(V)
Figure 9. Normalized on-resistance vs temperature
R
DS(on)
(norm.)
2.5
V
GS
= 10 V
GIPG150620181231RON
2.0
1.5
1.0
0.5
0.0
-75 -25 25 75 125 T
J
(°C)
Figure 11. Output capacitance stored energy
E
OSS
(µJ)
14
12
10
8
6
GADG200620181116EOS
4
2
0
0 100 200 300 400 500 600 V
DS
(V)
Figure 8. Normalized gate threshold voltage vs temperature
V
GS(th)
(norm.)
1.1
GIPG150620181230VTH
I
D
= 250 μA
1.0
0.9
0.8
0.7
0.6
-75 -25 25 75 125 T
J
(°C)
Figure 10. Normalized V
(BR)DSS
vs temperature
V
(BR)DSS
(norm.)
GIPG150620181231BDV
I
D
= 1 mA
1.08
1.04
1.00
0.96
0.92
0.88
-75 -25 25 75 125 T
J
(°C)
Figure 12. Source-drain diode forward characteristics
V
SD
(V)
1.1
GIPG260620180841SDF
1.0
T j
= -50 °C
0.9
0.8
0.7
0.6
0.5
0 4 8
T j
= 25 °C
T j
= 150 °C
12 16 20 I
SD
(A)
DS12638 - Rev 3 page 6/15
STL33N60M6
Test circuits
3
Test circuits
Figure 13. Switching times test circuit for resistive load
R
L
V GS
P W
GND1
(driver signal)
V
D
R
G
GND2
(power)
D.U.T.
+
2200
µF
3.3
µF
V DD
AM15855v1
Figure 15. Test circuit for inductive load switching and diode recovery times
25Ω
G
D
A
D.U.T.
S
B
R
G
A
FAST
DIODE
A
B
B
D
L=100µH
G
S
D.U.T.
3.3
µF
+
1000
µF
V
DD
GND1 GND2
AM15857v1
Figure 17. Unclamped inductive waveform
V
(BR)DSS
V
D
I DM
I D
V
DD V DD
AM01472v1
Figure 14. Test circuit for gate charge behavior
V
DD
RL
V
GS pulse width
2200
μF
+
1 kΩ
I
G
= CONST
2.7 kΩ
47 kΩ
GND1
100 Ω
D.U.T.
V
G
GND2
GADG180720181011SA
Figure 16. Unclamped inductive load test circuit
L
V
D
I D
V i
P w
GND1 GND2
D.U.T.
+
2200
µF
3.3
µF
V DD
AM15858v1
0
Figure 18. Switching time waveform t d(on) t on t r t d(off) t off t f
90% 90%
10%
V
GS
V
DS
90%
10%
0 10%
AM01473v1
DS12638 - Rev 3 page 7/15
4
STL33N60M6
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
. ECOPACK ® is an ST trademark.
DS12638 - Rev 3 page 8/15
4.1
STL33N60M6
PowerFLAT™ 8x8 HV package information
PowerFLAT™ 8x8 HV package information
Figure 19. PowerFLAT™ 8x8 HV package outline
DS12638 - Rev 3
8222871_Rev_4 page 9/15
Ref.
D2
E1
E2 e
L
A
A1
A3 b
D
E
STL33N60M6
PowerFLAT™ 8x8 HV package information
Table 8. PowerFLAT™ 8x8 HV mechanical data
Min.
0.75
0.00
0.10
0.90
7.90
7.90
7.10
2.65
4.25
0.40
Dimensions (in mm)
Typ.
0.85
0.20
1.00
8.00
8.00
7.20
2.75
4.35
2.00 BSC
0.50
Figure 20. PowerFLAT™ 8x8 HV footprint
Max.
0.95
0.05
0.30
1.10
8.10
8.10
7.30
2.85
4.45
0.60
Note: All dimensions are in millimeters.
DS12638 - Rev 3
8222871_REV_4_footprint page 10/15
4.2
STL33N60M6
PowerFLAT™ 8x8 HV packing information
PowerFLAT™ 8x8 HV packing information
Figure 21. PowerFLAT™ 8x8 HV tape
P0 (4.0±0.1) P2 (2.0±0.1)
D0 ( 1.55±0.05) T (0.30±0.05)
E (1.75±0.1)
D1 ( 1.5 Min)
P1 (12.00±0.1) A0 (8.30±0.1)
K0 (1.10±0.1)
Note:
Note: Base and Bulk qu antity 3000 pcs
All dimensions are in millimeters.
Figure 22. PowerFLAT™ 8x8 HV package orientation in carrier tape
8229819_Tape_revA
DS12638 - Rev 3 page 11/15
STL33N60M6
PowerFLAT™ 8x8 HV packing information
Figure 23. PowerFLAT™ 8x8 HV reel
Note: All dimensions are in millimeters.
8229819_Reel_revA
DS12638 - Rev 3 page 12/15
Revision history
Date
02-Jul-2018
18-Jul-2018
02-Aug-2018
Version
1
Table 9. Document revision history
Changes
2
3
Initial release.
Modified Section 3 Test circuits
.
Minor text changes.
Updated features in cover page.
STL33N60M6
DS12638 - Rev 3 page 13/15
STL33N60M6
Contents
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2.1
Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4.1
PowerFLAT™ 8x8 HV package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2
PowerFLAT™ 8x8 HV packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
DS12638 - Rev 3 page 14/15
STL33N60M6
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2018 STMicroelectronics – All rights reserved
DS12638 - Rev 3 page 15/15
