STB33N60M6
Datasheet
N-channel 600 V, 105 mΩ typ., 25 A, MDmesh M6 Power MOSFET in a D²PAK package
G(1)
TAB
2
1
3
D²PAK
D(2, TAB)
S(3)
AM01475V1
Features
Order code
STB33N60M6
V
DS
600 V
• Reduced switching losses
• Lower R
DS(on)
per area vs previous generation
• Low gate input resistance
• 100% avalanche tested
• Zener-protected
R
DS(on)
max.
125 mΩ
I
D
25 A
Applications
• Switching applications
• LLC converters
• Boost PFC converters
Description
The new MDmesh M6 technology incorporates the most recent advancements to the well-known and consolidated MDmesh family of SJ MOSFETs. STMicroelectronics builds on the previous generation of MDmesh devices through its new M6 technology, which combines excellent R
DS(on)
per area improvement with one of the most effective switching behaviors available, as well as a user-friendly experience for maximum end-application efficiency.
Product status link
STB33N60M6
Product summary
Order code
Marking
Package
Packing
STB33N60M6
33N60M6
D²PAK
Tape and reel
DS13003 - Rev 1 - April 2019
For further information contact your local STMicroelectronics sales office.
www.st.com
STB33N60M6
Electrical ratings
1
Electrical ratings
Table 1. Absolute maximum ratings
Symbol
V
I
GS
D
Parameter
Gate-source voltage
Drain current (continuous) at T case
= 25 °C
Drain current (continuous) at T case
= 100 °C
I
D
(1)
P
TOT dv/dt
(2) dv/dt (3)
T stg
T j
Drain current (pulsed)
Total power dissipation at T case
= 25 °C
Peak diode recovery voltage slope
MOSFET dv/dt ruggedness
Storage temperature range
Operating junction temperature range
1. Pulse width limited by safe operating area.
2. I
SD
≤ 25 A, di/dt ≤ 400 A/μs, V
DS(peak)
< V
(BR)DSS
, V
DD
= 400 V
3. V
DS
≤ 480 V
Table 2. Thermal data
Symbol
R thj-case
R thj-pcb
(1)
Parameter
Thermal resistance junction-case
Thermal resistance junction-pcb
1. When mounted on an 1 inch² FR-4, 2 Oz copper board.
Symbol
I
AR
E
AS
Table 3. Avalanche characteristics
Parameter
Avalanche current, repetitive or non-repetitive
(pulse width limited by T
Jmax
)
Single pulse avalanche energy
(starting T j
= 25 °C, I
D
= I
AR
, V
DD
= 50 V)
Value
±25
25
15.8
78
190
15
100
-55 to 150
Unit
V
A
A
W
V/ns
°C
Value
0.66
30
Unit
°C/W
°C/W
Value
4
500
Unit
A mJ
DS13003 - Rev 1 page 2/15
2
STB33N60M6
Electrical characteristics
Electrical characteristics
(T case
= 25 °C unless otherwise specified)
Table 4. On/off states
Symbol
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
Parameter Test conditions
Drain-source breakdown voltage V
GS
= 0 V, I
D
= 1 mA
V
GS
= 0 V, V
DS
= 600 V
Zero gate voltage drain current
Gate-body leakage current
V
GS
= 0 V, V
DS
= 600 V,
T case
= 125 °C (1)
V
DS
= 0 V, V
GS
= ±25 V
Gate threshold voltage V
DS
= V
GS
, I
D
= 250 µA
Static drain-source on-resistance V
GS
= 10 V, I
D
= 12.5 A
1. Defined by design, not subject to production test.
Min.
600
3.25
Typ.
Max.
Unit
V
1
µA
100
4
105
±5
4.75
125
µA
V mΩ
Table 5. Dynamic
Symbol
C iss
C oss
C rss
C oss eq.
(1)
R
G
Q g
Q
Q gs gd
Parameter
Input capacitance
Output capacitance
Reverse transfer capacitance
Equivalent output capacitance
Intrinsic gate resistance
Total gate charge
Gate-source charge
Gate-drain charge
V
DS
Test conditions
= 100 V, f = 1 MHz, V
GS
= 0 V
V
DS
= 0 to 480 V, V
GS
= 0 V f = 1 MHz, I
D
= 0 A
V
DD
= 480 V, I
D
= 25 A,
V
GS
= 0 to 10 V
(see
Figure 14. Test circuit for gate charge behavior
)
Min.
-
-
-
-
-
-
-
-
Typ.
1515
128
4.2
269
1.5
33.4
7.2
16.3
Max.
-
-
-
-
-
-
-
-
Unit pF pF
Ω nC
1. C oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C oss to 80% V
DSS
.
when V
DS
increases from 0
Symbol t d(on) t r t d(off) t f
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Table 6. Switching times
Test conditions
V
DD
= 300 V, I
D
= 12.5 A,
R
G
= 4.7 Ω, V
GS
= 10 V
(see
Figure 13. Test circuit for resistive load switching times and
Figure 18. Switching time waveform
)
Min.
-
-
-
-
Typ.
19.5
33
38.5
7.5
Max.
-
-
-
-
Unit ns
DS13003 - Rev 1 page 3/15
STB33N60M6
Electrical characteristics
Symbol
I
SD
I
SDM
(1)
V
SD
(2)
t rr
Q rr
I
RRM t rr
Q rr
I
RRM
Parameter
Source-drain current
Source-drain current (pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Table 7. Source-drain diode
Test conditions
I
SD
= 25 A, V
GS
= 0 V
I
SD
= 25 A, di/dt = 100 A/µs,
V
DD
= 60 V
(see
Figure 15. Test circuit for inductive load switching and diode recovery times
)
I
SD
= 25 A, di/dt = 100 A/µs,
V
DD
= 60 V, T j
= 150 °C
(see
Figure 15. Test circuit for inductive load switching and diode recovery times
)
1. Pulse width is limited by safe operating area.
2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
-
-
-
Min.
-
-
-
-
-
23.2
374
5.78
30.9
Typ.
Max.
25
78
1.6
265
3.07
Unit
A
A
V ns
µC
A ns
µC
A
DS13003 - Rev 1 page 4/15
STB33N60M6
Electrical characteristics (curves)
2.1
Electrical characteristics (curves)
I
D
(A)
Figure 1. Safe operating area
GIPG210620181235SOA t p
=1 µs
10 1
10 0
10 -1
10 -1
Operation in this area is limited by R
DS(on)
10 0
T
J
T
C
≤150 °C
=25 °C
V
GS
=10 V single pulse
10 1 10 2 t p t p
=10 µs
=100 µs t p
=1 ms t p
=10 ms
V
DS
(V)
50
40
30
I
D
(A)
70
60
20
10
0
0
Figure 3. Output characteristics
4
V
GS
= 9, 10 V
GIPG150620181232OCH
V
GS
=8 V
8
V
GS
=7 V
12
V
GS
=6 V
V
GS
=5 V
16 V
DS
(V)
Figure 5. Gate charge vs gate-source voltage
V
GS
(V)
12
10
V
DS
V
I
D
DD
= 480 V
= 25 A
GIPG150620181237QVG V
DS
(V)
600
500
4
2
0
0
8
6
8 16 24 32 40
400
300
200
100
Q
0 g
(nC)
Figure 2. Thermal impedance
GC20540_ZTH
K
δ=0.5
δ=0.2
0.1
10 -1
0.02
0.05
0.01
Single pulse
10 -2
10 -5 10 -4 10 -3 10 -2 10 -1 t p
(s)
Figure 4. Transfer characteristics
50
40
30
I
D
(A)
70
60
20
10
0
3 4
V
DS
= 20 V
5 6
GIPG150620181233TCH
7 8 9 V
GS
(V)
Figure 6. Static drain-source on-resistance
R
DS(on)
(Ω)
GIPG150620181231RID
V
GS
= 10 V
0.115
0.110
0.105
0.100
0.095
0 4 8 12 16 20 24 I
D
(A)
DS13003 - Rev 1 page 5/15
STB33N60M6
Electrical characteristics (curves)
C
(pF)
Figure 7. Capacitance variations
GIPG150620181232CVR
10 4
10 3
10 2
10 1
10 0
10 -1 f = 1 MHz
10 0 10 1 10 2
C
ISS
C
OSS
C
RSS
V
DS
(V)
Figure 9. Normalized on-resistance vs temperature
R
DS(on)
(norm.)
2.5
V
GS
= 10 V
GIPG150620181231RON
2.0
1.5
1.0
0.5
0.0
-75 -25 25 75 125 T
J
(°C)
Figure 11. Output capacitance stored energy
E
OSS
(µJ)
14
12
10
GADG200620181116EOS
8
6
4
2
0
0 100 200 300 400 500 600 V
DS
(V)
Figure 8. Normalized gate threshold voltage vs temperature
V
GS(th)
(norm.)
GIPG150620181230VTH
I
D
= 250 μA
1.1
1.0
0.9
0.8
0.7
0.6
-75 -25 25 75 125 T
J
(°C)
Figure 10. Normalized V
(BR)DSS
vs temperature
V
(BR)DSS
(norm.)
1.08
I
D
= 1 mA
GIPG150620181231BDV
1.04
1.00
0.96
0.92
0.88
-75 -25 25 75 125 T
J
(°C)
Figure 12. Source-drain diode forward characteristics
0.8
0.7
0.6
0.5
0
V
SD
(V)
1.1
1.0
0.9
4
T
T
J
J
= -50 °C
T
GIPG150620181232SDF
= 150 °C
J
= 25 °C
8 12 16 20 24 I
SD
(A)
DS13003 - Rev 1 page 6/15
STB33N60M6
Test circuits
3
Test circuits
Figure 13. Test circuit for resistive load switching times
V
GS pulse width
V
D
R
G
R
L
+
2200
μF
3.3
μF V
DD
D.U.T.
Figure 14. Test circuit for gate charge behavior
V
DD
RL
V
GS pulse width
2200
μF
+
1 kΩ
I
G
= CONST
2.7 kΩ
47 kΩ
100 Ω D.U.T.
V
G
AM01469v10
AM01468v1
Figure 15. Test circuit for inductive load switching and diode recovery times
Figure 16. Unclamped inductive load test circuit
G
25 Ω
D
A
D.U.T.
S
B
A A fast diode
B
B
G
+
_
R
G
100 µH
D
D.U.T.
S
3.3
µF +
1000
µF
V
DD
AM01470v1
Figure 17. Unclamped inductive waveform
V
(BR)DSS
V
D
I
DM
I
D
V
DD
V
DD
AM01472v1
V i pulse width
V
D
L
I
D
+
2200
µF
3.3
µF V
DD
D.U.T.
AM01471v1
0
Figure 18. Switching time waveform t d(on) t on t r t d(off) t off t f
90% 90%
10%
V
GS
V
DS
90%
10%
0 10%
AM01473v1
DS13003 - Rev 1 page 7/15
4
STB33N60M6
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
DS13003 - Rev 1 page 8/15
4.1
STB33N60M6
D²PAK (TO-263) type A2 package information
D²PAK package information
Figure 19. D²PAK (TO-263) type A2 package outline
DS13003 - Rev 1
0079457_A2_26 page 9/15
DS13003 - Rev 1
STB33N60M6
D²PAK (TO-263) type A2 package information
Dim.
e1
H
J1
L
L1
L2
R
V2
D
D1
D2
E
E1
E2 e
A
A1 b b2 c c2
Table 8. D²PAK (TO-263) type A2 package mechanical data mm
Typ.
1.14
0.45
1.23
8.95
7.50
Min.
4.40
0.03
0.70
1.10
10.00
8.70
7.30
7.75
1.30
8.90
7.50
2.54
4.88
15.00
2.49
2.29
1.27
1.30
0.40
0°
5.28
15.85
2.69
2.79
1.40
1.75
8°
1.70
0.60
1.36
9.35
8.00
Max.
4.60
0.23
0.93
1.50
10.40
9.10
7.70
Figure 20. D²PAK (TO-263) recommended footprint (dimensions are in mm)
Footprint page 10/15
4.2
D²PAK packing information
Figure 21. D²PAK tape outline
STB33N60M6
D²PAK packing information
DS13003 - Rev 1 page 11/15
DS13003 - Rev 1
A
STB33N60M6
D²PAK packing information
D
B
Full radius
Figure 22. D²PAK reel outline
T
40mm min. access hole at slot location
Tape slot in core for tape start
2.5mm min.width
C
N
G measured at hub
Dim.
E
F
K0
P0
P1
P2
R
T
W
A0
B0
D
D1
Min.
1.65
11.4
4.8
3.9
11.9
1.9
50
0.25
23.7
10.5
15.7
1.5
1.59
Tape
Table 9. D²PAK tape and reel mechanical data
Reel mm
Dim.
Max.
10.7
15.9
1.6
1.61
1.85
11.6
5.0
4.1
12.1
2.1
C
D
A
B
G
N
T
Base quantity
Bulk quantity
Min.
1.5
12.8
20.2
24.4
100
0.35
24.3
mm
AM06038v1
Max.
330
13.2
26.4
30.4
1000
1000 page 12/15
Revision history
Date
17-Apr-2019
Version
1
Table 10. Document revision history
Changes
Initial release.
STB33N60M6
DS13003 - Rev 1 page 13/15
STB33N60M6
Contents
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2.1
Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4.1
D²PAK package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2
D²PAK packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
DS13003 - Rev 1 page 14/15
STB33N60M6
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2019 STMicroelectronics – All rights reserved
DS13003 - Rev 1 page 15/15
