STD18N60M6
Datasheet
N-channel 600 V, 230 mΩ typ., 13 A, MDmesh M6
Power MOSFET in a DPAK package
G(1)
TAB
DPAK
1
2 3
D(2, TAB)
S(3)
AM01475V1
Features
Order code
STD18N60M6
V
DS
600 V
• Reduced switching losses
• Lower R
DS(on)
per area vs previous generation
• Low gate input resistance
• 100% avalanche tested
• Zener-protected
R
DS(on)
max.
280 mΩ
I
D
13 A
Applications
• Switching applications
• LLC converters
• Boost PFC converters
Description
The new MDmesh M6 technology incorporates the most recent advancements to the well-known and consolidated MDmesh family of SJ MOSFETs. STMicroelectronics builds on the previous generation of MDmesh devices through its new M6 technology, which combines excellent R
DS(on)
per area improvement with one of the most effective switching behaviors available, as well as a user-friendly experience for maximum end-application efficiency.
Product status link
STD18N60M6
Product summary
Order code
Marking
Package
Packing
STD18N60M6
18N60M6
DPAK
Tape and reel
DS12843 - Rev 2 - April 2019
For further information contact your local STMicroelectronics sales office.
www.st.com
STD18N60M6
Electrical ratings
1
Electrical ratings
Table 1. Absolute maximum ratings
Symbol
V
GS
Gate-source voltage
Parameter
I
D
Drain current (continuous) at T case
= 25 °C
Drain current (continuous) at T case
= 100 °C
Drain current (pulsed) I
DM
(1)
P
TOT
dv/dt (2)
Total power dissipation at T case
= 25 °C
dv/dt (3)
T stg
T j
Peak diode recovery voltage slope
MOSFET dv/dt ruggedness
Storage temperature range
Operating junction temperature range
1. Pulse width is limited by safe operating area.
2. I
SD
≤ 13 A, di/dt ≤ 400 A/μs, V
DS(peak)
< V
(BR)DSS
, V
DD
= 400 V
3. V
DS
≤ 480 V
Table 2. Thermal data
Symbol
R thj-case
R thj-pcb
(1)
Thermal resistance junction-case
Thermal resistance junction-pcb
Parameter
1. When mounted on 1 inch 2 FR-4, 2 Oz copper board
Symbol
I
AR
E
AS
Table 3. Avalanche characteristics
Parameter
Avalanche current, repetitive or non-repetitive
(pulse width limited by T
Jmax
)
Single pulse avalanche energy
(starting T j
= 25 °C, I
D
= I
AR
, V
DD
= 50 V)
Value
±25
13
8.2
38
110
15
100
-55 to 150
Unit
V
A
A
W
V/ns
°C
Value
1.14
50
Unit
°C/W
°C/W
Value
2.7
210
Unit
A mJ
DS12843 - Rev 2 page 2/16
2
STD18N60M6
Electrical characteristics
Electrical characteristics
(T case
= 25 °C unless otherwise specified).
Table 4. On/off states
Symbol
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
Parameter Test conditions
Drain-source breakdown voltage V
GS
= 0 V, I
D
= 1 mA
V
GS
= 0 V, V
DS
= 600 V
Zero gate voltage drain current
Gate-body leakage current
V
GS
= 0 V, V
DS
= 600 V,
T case
= 125 °C (1)
V
DS
= 0 V, V
GS
= ±25 V
Gate threshold voltage V
DS
= V
GS
, I
D
= 250 µA
Static drain-source on-resistance I
D
= 6.5 A, V
GS
= 10 V
1. Defined by design, not subject to production test.
Min.
600
3.25
Typ.
Max.
Unit
V
1
µA
100
4
230
±5
4.75
280
µA
V mΩ
Table 5. Dynamic
Symbol
C iss
C oss
C rss
C oss eq.
(1)
R
Q
Q
Q
G g gs gd
Parameter
Input capacitance
Output capacitance
Reverse transfer capacitance
Equivalent output capacitance
Intrinsic gate resistance
Total gate charge
Gate-source charge
Gate-drain charge
V
DS
Test conditions
= 100 V, f = 1 MHz, V
GS
= 0 V
V
DS
= 0 to 480 V, V
GS
= 0 V f = 1 MHz, I
D
= 0 A
V
DD
= 480 V, I
D
= 13 A,
V
GS
= 0 to 10 V
(see
Figure 14. Test circuit for gate charge behavior
)
Min.
-
-
-
-
-
-
-
-
Typ.
650
45
2
123
4.6
16.8
4.5
8.4
Max.
-
-
-
-
-
-
-
-
Unit pF pF
Ω nC
1. C oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C oss to 80% V
DSS
.
when V
DS
increases from 0
Symbol t d(on) t r t d(off) t f
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Table 6. Switching times
Test conditions
V
DD
= 300 V, I
D
= 6.5 A,
R
G
= 4.7 Ω, V
GS
= 10 V
(see
Figure 13. Test circuit for resistive load switching times and
Figure 18. Switching time waveform
)
Min.
-
-
-
-
Typ.
16
7
28
9
Max.
-
-
-
-
Unit ns
DS12843 - Rev 2 page 3/16
STD18N60M6
Electrical characteristics
Symbol
I
SD
I
SDM
(1)
V
SD
(2)
t rr
Q rr
I
RRM t rr
Q rr
I
RRM
Parameter
Source-drain current
Source-drain current (pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Table 7. Source-drain diode
Test conditions
I
SD
= 13 A, V
GS
= 0 V
I
SD
= 13 A, di/dt = 100 A/µs,
V
DD
= 60 V
(see
Figure 15. Test circuit for inductive load switching and diode recovery times
)
I
SD
= 13 A, di/dt = 100 A/µs,
V
DD
= 60 V, T j
= 150 °C
(see
Figure 15. Test circuit for inductive load switching and diode recovery times
)
1. Pulse width is limited by safe operating area.
2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
Min.
-
-
-
-
-
-
-
-
-
18
290
2.9
20
Typ.
Max.
13
38
1.6
208
1.9
Unit
A
A
V ns
µC
A ns
µC
A
DS12843 - Rev 2 page 4/16
STD18N60M6
Electrical characteristics (curves)
2.1
Electrical characteristics (curves)
Figure 1. Safe operating area
I
D
(A) Operation in this area is limited by R
DS(on)
GIPG191120181209SOA t p
=1 µs t p
=10 µs
10 1 t p
=100 µs
10 0
T
J
T
C
≤150 °C
=25 °C
V
GS
=10 V single pulse t p
=1 ms t p
=10 ms
10 -1
10 -1 10 0 10 1 10 2
V
DS
(V)
20
15
10
5
0
0
I
D
(A)
30
Figure 3. Output characteristics
GIPG311020181052OCH
V
GS
=9 V
V
GS
= 10 V
V
GS
=8 V
25
2 4 6 8
V
GS
=7 V
10 12
V
GS
=6 V
V
DS
(V)
Figure 5. Gate charge vs gate-source voltage
V
DS
(V)
600
500
400
Q gs
V
DD
= 480 V
I
D
= 13 A
V
DS
Q gd
GIPG311020181053QVG V
GS
(V)
12
Q g
10
8
300
200
100
0
0 4 8 12 16
6
4
2
Q
0 g
(nC)
K
Figure 2. Thermal impedance
GC20460
10 0
10 -1
10 -2
10 -5 10 -4 10 -3 10 -2 10 -1 t p
(s)
Figure 4. Transfer characteristics
15
10
5
0
4
I
D
(A)
30
25
20
V
DS
= 14 V
5 6
GIPG311020181052TCH
7 8 9 V
GS
(V)
Figure 6. Static drain-source on-resistance
R
DS(on)
(mΩ)
GIPG311020181050RID
250
V
GS
=10 V
240
230
220
210
0 2 4 6 8 10 12 I
D
(A)
DS12843 - Rev 2 page 5/16
C
(pF)
Figure 7. Capacitance variations
GIPG311020181051CVR
10 3
C
ISS
10 2
10 1 f = 1 MHz
10 0
10 -1 10 0 10 1 10 2
C
OSS
C
RSS
V
DS
(V)
Figure 9. Normalized gate threshold voltage vs temperature
V
GS(th)
(norm.)
1.1
I
D
=250 A
GIPG311020181049VTH
1.0
0.9
0.8
0.7
0.6
-75 -25 25 75 125 T
J
(°C)
Figure 11. Normalized V
(BR)DSS
vs temperature
V
(BR)DSS
(norm.)
1.10
I
D
= 1 mA
GIPG311020181050BDV
1.05
1.00
0.95
0.90
0.85
-75 -25 25 75 125 T
J
(°C)
STD18N60M6
Electrical characteristics (curves)
Figure 8. Output capacitance stored energy
E
OSS
(µJ)
6
GADG311020181207EOS
3
2
5
4
1
0
0 100 200 300 400 500 600 V
DS
(V)
Figure 10. Normalized on-resistance vs temperature
R
DS(on)
(norm.)
2.5
V
GS
= 10 V
GIPG311020181049RON
2.0
1.5
1.0
0.5
0.0
-75 -25 25 75 125 T
J
(°C)
Figure 12. Source-drain diode forward characteristics
V
SD
(V)
1.1
GIPG311020181051SDF
T j
= -50 °C
1.0
0.9
0.8
0.7
0.6
0.5
0 2 4
T j
= 25 °C
T j
= 150 °C
6 8 10 12 I
SD
(A)
DS12843 - Rev 2 page 6/16
STD18N60M6
Test circuits
3
Test circuits
Figure 13. Test circuit for resistive load switching times
V
GS pulse width
V
D
R
G
R
L
+
2200
μF
3.3
μF V
DD
D.U.T.
Figure 14. Test circuit for gate charge behavior
V
DD
RL
V
GS pulse width
2200
μF
+
1 kΩ
I
G
= CONST
2.7 kΩ
47 kΩ
100 Ω D.U.T.
V
G
AM01469v10
AM01468v1
Figure 15. Test circuit for inductive load switching and diode recovery times
Figure 16. Unclamped inductive load test circuit
G
25 Ω
D
A
D.U.T.
S
B
A A fast diode
B
B
G
+
_
R
G
100 µH
D
D.U.T.
S
3.3
µF
+
1000
µF
V
DD
AM01470v1
Figure 17. Unclamped inductive waveform
V
(BR)DSS
V
D
I
DM
I
D
V
DD
V
DD
AM01472v1
V i pulse width
V
D
L
I
D
+
2200
µF
3.3
µF
V
DD
D.U.T.
AM01471v1
0
Figure 18. Switching time waveform t d(on) t on t r t d(off) t off t f
90% 90%
10%
V
GS
V
DS
90%
10%
0 10%
AM01473v1
DS12843 - Rev 2 page 7/16
4
STD18N60M6
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
DS12843 - Rev 2 page 8/16
4.1
STD18N60M6
DPAK (TO-252) type A2 package information
DPAK (TO-252) type A2 package information
Figure 19. DPAK (TO-252) type A2 package outline
DS12843 - Rev 2
0068772_type-A2_rev26 page 9/16
DS12843 - Rev 2
Dim.
c2
D
D1
E
E1 e e1
A
A1
A2 b b4 c
L2
L4
R
V2
H
L
L1
STD18N60M6
DPAK (TO-252) type A2 package information
Table 8. DPAK (TO-252) type A2 mechanical data mm
Typ.
9.35
1.00
2.60
0.65
0.60
4.95
6.40
5.10
2.159
4.445
0.64
5.20
0.45
0.48
6.00
Min.
2.20
0.90
0.03
5.10
5.20
2.286
4.572
2.80
0.80
0.20
0°
10.10
1.50
3.00
0.95
1.00
5.25
6.60
5.30
2.413
4.699
0.90
5.40
0.60
0.60
6.20
Max.
2.40
1.10
0.23
8° page 10/16
STD18N60M6
DPAK (TO-252) type A2 package information
Figure 20. DPAK (TO-252) recommended footprint (dimensions are in mm)
DS12843 - Rev 2
FP_0068772_rev26 page 11/16
4.2
DPAK (TO-252) packing information
Figure 21. DPAK (TO-252) tape outline
T
Top cover tape
10 pitches cumulative tolerance on tape +/- 0.2 mm
P0 D P2
B1
K0
For machine ref. only including draft and radii concentric around B0
B0
A0 P1
User direction of feed
D1
STD18N60M6
DPAK (TO-252) packing information
F
E
W
User direction of feed
R
Bending radius
AM08852v1
DS12843 - Rev 2 page 12/16
DS12843 - Rev 2
A
D
B
Figure 22. DPAK (TO-252) reel outline
STD18N60M6
DPAK (TO-252) packing information
T
40mm min. access hole at slot location
C
N
G measured at hub
Full radius
Tape slot in core for tape start
2.5mm min.width
Dim.
E
F
K0
P0
P1
P2
R
T
W
A0
B0
B1
D
D1
AM06038v1
1.5
1.5
1.65
7.4
2.55
3.9
7.9
1.9
40
0.25
15.7
Table 9. DPAK (TO-252) tape and reel mechanical data
Tape Reel mm
Dim.
Min.
6.8
10.4
Max.
7
10.6
12.1
1.6
N
T
D
G
A
B
C
Min.
1.5
12.8
20.2
16.4
50 1.85
7.6
2.75
4.1
8.1
2.1
0.35
16.3
Base qty.
Bulk qty.
mm
Max.
330
13.2
18.4
22.4
2500
2500 page 13/16
Revision history
Date
19-Nov-2018
19-Apr-2019
Table 10. Document revision history
Version
1
2
Changes
First release.
Updated product status link table in cover page.
STD18N60M6
DS12843 - Rev 2 page 14/16
STD18N60M6
Contents
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2.1
Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4.1
DPAK (TO-252) type A2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2
DPAK (TO-252) packing information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
DS12843 - Rev 2 page 15/16
STD18N60M6
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
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Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks . All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2019 STMicroelectronics – All rights reserved
DS12843 - Rev 2 page 16/16
